* [V2 2/2] Add initial dtsi file to support Hisilicon Hi3660 SoC with support of Octal core CPUs in two clusters(4 * A53 & 4 * A73).
From: Chen Feng @ 2017-01-10 7:49 UTC (permalink / raw)
To: puck.chen-C8/M+/jPZTeaMJb+Lgu22Q, xuwei5-C8/M+/jPZTeaMJb+Lgu22Q,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: puck.chen-H32Fclmsjq1BDgjK7y7TUQ, dan.zhao-C8/M+/jPZTeaMJb+Lgu22Q,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
saberlily.xia-C8/M+/jPZTeaMJb+Lgu22Q,
xuyiping-C8/M+/jPZTeaMJb+Lgu22Q, qijiwen-C8/M+/jPZTeaMJb+Lgu22Q
In-Reply-To: <1484034548-47794-1-git-send-email-puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Also add dts file to support HiKey960 development board which
based on Hi3660 SoC.
The output console is earlycon "earlycon=pl011,0xfdf05000".
And the con_init uart5 with a fixed clock, which already
configured at bootloader.
When clock is available, the uart5 will be modified.
Tested on HiKey960 Board.
Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
---
arch/arm64/boot/dts/hisilicon/Makefile | 1 +
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 34 +++++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 156 ++++++++++++++++++++++
3 files changed, 191 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660.dtsi
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
index c8b8f80..7aee1f3 100644
--- a/arch/arm64/boot/dts/hisilicon/Makefile
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -1,4 +1,5 @@
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
+dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
new file mode 100644
index 0000000..bc5399d
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -0,0 +1,34 @@
+/*
+ * dts file for Hisilicon HiKey960 Development Board
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "hi3660.dtsi"
+
+/ {
+ model = "HiKey960";
+ compatible = "hisilicon,hi3660";
+
+ aliases {
+ serial5 = &uart5; /* console UART */
+ };
+
+ chosen {
+ stdout-path = "serial5:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x00400000 0x0 0xbfe00000>;
+ };
+
+ soc {
+ uart5: uart@fdf05000 {
+ status = "ok";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
new file mode 100644
index 0000000..7f9805c
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -0,0 +1,156 @@
+/*
+ * dts file for Hisilicon Hi3660 SoC
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "hisilicon,hi3660";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+
+ cpu4: cpu@100 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@101 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@102 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@103 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ };
+ };
+
+ gic: interrupt-controller@e82b0000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
+ <0x0 0xe82b2000 0 0x2000>, /* GICC */
+ <0x0 0xe82b4000 0 0x2000>, /* GICH */
+ <0x0 0xe82b6000 0 0x2000>; /* GICV */
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <1920000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ fixed_uart5: fixed_19_2M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ clock-output-names = "fixed:uart5";
+ };
+
+ uart5: uart@fdf05000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf05000 0x0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&fixed_uart5 &fixed_uart5>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "ok";
+ };
+ };
+};
--
1.9.1
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^ permalink raw reply related
* Re: [PATCH v6 1/2] ARM: dts: vf610-zii-dev-rev-b: Remove leftover PWM pingroup
From: Shawn Guo @ 2017-01-10 7:52 UTC (permalink / raw)
To: Andrey Smirnov
Cc: linux-arm-kernel, Rob Herring, Mark Rutland, Russell King,
Sascha Hauer, Stefan Agner, devicetree, linux-kernel, andrew,
Vivien Didelot, cphealy
In-Reply-To: <20170110073555.12178-1-andrew.smirnov@gmail.com>
On Mon, Jan 09, 2017 at 11:35:54PM -0800, Andrey Smirnov wrote:
> Remove pwm0grp since it is:
>
> a) Not referenced anywhere in the DTS file (unlike Tower board it
> is based on, this board does not use/expose FTM0)
>
> b) Configures PTB2 and PTB3 in a way that contradicts
> pinctrl-mdio-mux
>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: andrew@lunn.ch
> Cc: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
> Cc: cphealy@gmail.com
> Tested-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Applied both, thanks.
^ permalink raw reply
* [V2 1/2] document: dt: add binding for Hi3660 SoC
From: Chen Feng @ 2017-01-10 7:55 UTC (permalink / raw)
To: puck.chen-C8/M+/jPZTeaMJb+Lgu22Q, xuwei5-C8/M+/jPZTeaMJb+Lgu22Q,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: puck.chen-H32Fclmsjq1BDgjK7y7TUQ, dan.zhao-C8/M+/jPZTeaMJb+Lgu22Q,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
saberlily.xia-C8/M+/jPZTeaMJb+Lgu22Q,
xuyiping-C8/M+/jPZTeaMJb+Lgu22Q, qijiwen-C8/M+/jPZTeaMJb+Lgu22Q
Add binding for hisilicon Hi3660 SoC and HiKey960 Board.
Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 7df79a7..6de2398 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -8,6 +8,10 @@ Hi6220 SoC
Required root node properties:
- compatible = "hisilicon,hi6220";
+Hi3660 SoC
+Required root node properties:
+ - compatible = "hisilicon,hi3660";
+
HiKey Board
Required root node properties:
- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
--
1.9.1
--
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^ permalink raw reply related
* [V2 2/2] arm64: dts: Add dts files for Hisilicon Hi3660 SoC
From: Chen Feng @ 2017-01-10 7:55 UTC (permalink / raw)
To: puck.chen-C8/M+/jPZTeaMJb+Lgu22Q, xuwei5-C8/M+/jPZTeaMJb+Lgu22Q,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: puck.chen-H32Fclmsjq1BDgjK7y7TUQ, dan.zhao-C8/M+/jPZTeaMJb+Lgu22Q,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
saberlily.xia-C8/M+/jPZTeaMJb+Lgu22Q,
xuyiping-C8/M+/jPZTeaMJb+Lgu22Q, qijiwen-C8/M+/jPZTeaMJb+Lgu22Q
In-Reply-To: <1484034915-48879-1-git-send-email-puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Add initial dtsi file to support Hisilicon Hi3660 SoC with
support of Octal core CPUs in two clusters(4 * A53 & 4 * A73).
Also add dts file to support HiKey960 development board which
based on Hi3660 SoC.
The output console is earlycon "earlycon=pl011,0xfdf05000".
And the con_init uart5 with a fixed clock, which already
configured at bootloader.
When clock is available, the uart5 will be modified.
Tested on HiKey960 Board.
Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
---
arch/arm64/boot/dts/hisilicon/Makefile | 1 +
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 34 +++++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 156 ++++++++++++++++++++++
3 files changed, 191 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660.dtsi
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
index c8b8f80..7aee1f3 100644
--- a/arch/arm64/boot/dts/hisilicon/Makefile
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -1,4 +1,5 @@
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
+dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
new file mode 100644
index 0000000..bc5399d
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -0,0 +1,34 @@
+/*
+ * dts file for Hisilicon HiKey960 Development Board
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "hi3660.dtsi"
+
+/ {
+ model = "HiKey960";
+ compatible = "hisilicon,hi3660";
+
+ aliases {
+ serial5 = &uart5; /* console UART */
+ };
+
+ chosen {
+ stdout-path = "serial5:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x00400000 0x0 0xbfe00000>;
+ };
+
+ soc {
+ uart5: uart@fdf05000 {
+ status = "ok";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
new file mode 100644
index 0000000..7f9805c
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -0,0 +1,156 @@
+/*
+ * dts file for Hisilicon Hi3660 SoC
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "hisilicon,hi3660";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+
+ cpu4: cpu@100 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@101 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@102 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@103 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ };
+ };
+
+ gic: interrupt-controller@e82b0000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
+ <0x0 0xe82b2000 0 0x2000>, /* GICC */
+ <0x0 0xe82b4000 0 0x2000>, /* GICH */
+ <0x0 0xe82b6000 0 0x2000>; /* GICV */
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <1920000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ fixed_uart5: fixed_19_2M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ clock-output-names = "fixed:uart5";
+ };
+
+ uart5: uart@fdf05000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf05000 0x0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&fixed_uart5 &fixed_uart5>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "ok";
+ };
+ };
+};
--
1.9.1
--
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^ permalink raw reply related
* Re: [PATCH v7 1/2] mtd: arasan: Add device tree binding documentation
From: Boris Brezillon @ 2017-01-10 8:06 UTC (permalink / raw)
To: Punnaiah Choudary Kalluri
Cc: Rob Herring, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org,
computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
richard-/L3Ra7n9ekc@public.gmane.org,
cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Michal Simek,
kalluripunnaiahchoudary-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
kpc528-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
In-Reply-To: <03CA77BA8AF6F1469AEDFBDA1322A7B76424ECD2-4lKfpRxZ5ekkx2a1wsGfbYg+Gb3gawCHQz34XiSyOiE@public.gmane.org>
Hi Punnaiah,
On Tue, 10 Jan 2017 06:03:25 +0000
Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> wrote:
> Hi Rob,
>
> Thanks for the review.
>
> > -----Original Message-----
> > From: Rob Herring [mailto:robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> > Sent: Tuesday, January 10, 2017 11:06 AM
> > To: Punnaiah Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> > Cc: dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org; computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org;
> > boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org; marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org;
> > richard-/L3Ra7n9ekc@public.gmane.org; cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org; linux-
> > kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org;
> > devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Michal Simek <michals-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>;
> > kalluripunnaiahchoudary-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; kpc528-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; Punnaiah
> > Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> > Subject: Re: [PATCH v7 1/2] mtd: arasan: Add device tree binding
> > documentation
> >
> > On Mon, Jan 09, 2017 at 08:28:53AM +0530, Punnaiah Choudary Kalluri wrote:
> > > This patch adds the dts binding document for arasan nand flash
> > > controller.
> > >
> > > Signed-off-by: Punnaiah Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> > > ---
> > > Changes in v7:
> > > - Corrected the acronyms those should be in caps
> > > changes in v6:
> > > - Removed num-cs property
> > > - Separated nandchip from nand controller
> > > changes in v5:
> > > - None
> > > Changes in v4:
> > > - Added num-cs property
> > > - Added clock support
> > > Changes in v3:
> > > - None
> > > Changes in v2:
> > > - None
> > > ---
> > > .../devicetree/bindings/mtd/arasan_nfc.txt | 38
> > ++++++++++++++++++++++
> > > 1 file changed, 38 insertions(+)
> > > create mode 100644
> > Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> > b/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> > > new file mode 100644
> > > index 0000000..f20adfc
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> > > @@ -0,0 +1,38 @@
> > > +Arasan NAND Flash Controller with ONFI 3.1 support
> > > +
> > > +Required properties:
> > > +- compatible: Should be "arasan,nfc-v3p10"
> >
> > Needs a note that it must also have an SoC specific compatible string.
> >
> Sorry, I couldn't understand this comment. Could you elaborate it?
Arasan is an IP vendor, and those IPs are usually embedded in specific
SoCs. I guess Rob was suggesting to define something like:
compatible = "<soc-vendor>,<ip-revision>", "arasan,<ip-revision>";
This way you can differentiate minor changes/tweaks between each SoC
(each SoC vendor usually enable/disable specific features based on
their needs).
>
> > > +- reg: Memory map for module access
> > > +- interrupt-parent: Interrupt controller the interrupt is routed through
> > > +- interrupts: Should contain the interrupt for the device
> > > +- clock-name: List of input clocks - "clk_sys", "clk_flash"
> >
> > clk_ is redundant.
> >
>
> I have defined these clock names as per the controller data sheet.
> So, I feel it is fine to have them in sync with the datasheet.
> Please let me know if you still want me to change this.
We already know this is a clock, hence the unneeded clk_ prefix. Please
drop it.
Thanks,
Boris
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^ permalink raw reply
* [PATCH v5 0/2] Support for Axentia TSE-850
From: Peter Rosin @ 2017-01-10 8:08 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: Peter Rosin, Rob Herring, Mark Rutland, Russell King,
Nicolas Ferre, Alexandre Belloni,
Jean-Christophe Plagniol-Villard,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hi!
changes v4 -> v5
- comment from Rob about the memory node made me look closer and
the memory size is actually updated by the bootloader, and that
hid the fact that the entry was always faulty. This version
specifies the correct memory size from the start, which is 64MB.
- ack from Rob
changes v3 -> v4
- rename files arch/arm/boot/dts/axentia-* to .../at91-*
- remove bootargs from at91-tse850-3.dts
- depend on the atmel ssc to register as a sound dai by itself
- bump copyright years
changes v2 -> v3
- document the new compatible strings prefixed with "axentia,".
changes v1 -> v2
- squash the fixup into the correct patch, sorry for the noise.
After finally having all essintial drivers upstreamed I would
like to have the dts and the defconfig also upstreamed.
The atmel-ssc/sound-dai change depends on a change that has been
sitting in the ASoC tree since mid-december, and I have been waiting
for it to hit linux-next before sending this, but it seems to take
longer than I anticipated. So, since I do not want this to in
turn miss the next merge window because of that wait I therefore
request that this is taken now even though it doesn't really work
w/o the ASoC "topic/atmel" branch as of 2016-12-15 [1]. It of course
builds cleanly even w/o those ASoC changes. That effectively means
that noone besides me should notice the inconsistency (I currently
have all affected devices under my control).
Cheers,
peda
[1] http://git.kernel.org/cgit/linux/kernel/git/broonie/sound.git/log/?h=topic/atmel
Peter Rosin (2):
ARM: dts: at91: add devicetree for the Axentia TSE-850
ARM: sama5_defconfig: add support for the Axentia TSE-850 board
Documentation/devicetree/bindings/arm/axentia.txt | 19 ++
MAINTAINERS | 8 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/at91-linea.dtsi | 53 +++++
arch/arm/boot/dts/at91-tse850-3.dts | 274 ++++++++++++++++++++++
arch/arm/configs/sama5_defconfig | 7 +-
6 files changed, 361 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/axentia.txt
create mode 100644 arch/arm/boot/dts/at91-linea.dtsi
create mode 100644 arch/arm/boot/dts/at91-tse850-3.dts
--
2.1.4
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^ permalink raw reply
* [PATCH v5 1/2] ARM: dts: at91: add devicetree for the Axentia TSE-850
From: Peter Rosin @ 2017-01-10 8:08 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: Peter Rosin, Rob Herring, Mark Rutland, Russell King,
Nicolas Ferre, Alexandre Belloni,
Jean-Christophe Plagniol-Villard,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1484035732-31635-1-git-send-email-peda-koto5C5qi+TLoDKTGw+V6w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Peter Rosin <peda-koto5C5qi+TLoDKTGw+V6w@public.gmane.org>
---
Documentation/devicetree/bindings/arm/axentia.txt | 19 ++
MAINTAINERS | 8 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/at91-linea.dtsi | 53 +++++
arch/arm/boot/dts/at91-tse850-3.dts | 274 ++++++++++++++++++++++
5 files changed, 355 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/axentia.txt
create mode 100644 arch/arm/boot/dts/at91-linea.dtsi
create mode 100644 arch/arm/boot/dts/at91-tse850-3.dts
diff --git a/Documentation/devicetree/bindings/arm/axentia.txt b/Documentation/devicetree/bindings/arm/axentia.txt
new file mode 100644
index 000000000000..ea3fb96ae465
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/axentia.txt
@@ -0,0 +1,19 @@
+Device tree bindings for Axentia ARM devices
+============================================
+
+Linea CPU module
+----------------
+
+Required root node properties:
+compatible = "axentia,linea",
+ "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
+and following the rules from atmel-at91.txt for a sama5d31 SoC.
+
+
+TSE-850 v3 board
+----------------
+
+Required root node properties:
+compatible = "axentia,tse850v3", "axentia,linea",
+ "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
+and following the rules from above for the axentia,linea CPU module.
diff --git a/MAINTAINERS b/MAINTAINERS
index 97b78cc5aa51..5c2ea6e9cd7f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2346,6 +2346,14 @@ S: Maintained
F: Documentation/devicetree/bindings/sound/axentia,*
F: sound/soc/atmel/tse850-pcm5142.c
+AXENTIA ARM DEVICES
+M: Peter Rosin <peda-koto5C5qi+TLoDKTGw+V6w@public.gmane.org>
+L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers)
+S: Maintained
+F: Documentation/devicetree/bindings/arm/axentia.txt
+F: arch/arm/boot/dts/at91-linea.dtsi
+F: arch/arm/boot/dts/at91-tse850-3.dts
+
AZ6007 DVB DRIVER
M: Mauro Carvalho Chehab <mchehab-JsYNTwtnfakRB7SZvlqPiA@public.gmane.org>
M: Mauro Carvalho Chehab <mchehab-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9a7375c388a8..7632849866de 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -48,6 +48,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
at91-kizbox2.dtb \
at91-sama5d2_xplained.dtb \
at91-sama5d3_xplained.dtb \
+ at91-tse850-3.dtb \
sama5d31ek.dtb \
sama5d33ek.dtb \
sama5d34ek.dtb \
diff --git a/arch/arm/boot/dts/at91-linea.dtsi b/arch/arm/boot/dts/at91-linea.dtsi
new file mode 100644
index 000000000000..646feb0daa81
--- /dev/null
+++ b/arch/arm/boot/dts/at91-linea.dtsi
@@ -0,0 +1,53 @@
+/*
+ * at91-linea.dtsi - Device Tree Include file for the Axentia Linea Module.
+ *
+ * Copyright (C) 2017 Axentia Technologies AB
+ *
+ * Author: Peter Rosin <peda-koto5C5qi+TLoDKTGw+V6w@public.gmane.org>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "sama5d31.dtsi"
+
+/ {
+ compatible = "axentia,linea",
+ "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
+
+ memory {
+ reg = <0x20000000 0x4000000>;
+ };
+};
+
+&slow_xtal {
+ clock-frequency = <32768>;
+};
+
+&main_xtal {
+ clock-frequency = <12000000>;
+};
+
+&main {
+ clock-frequency = <12000000>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "st,24c64";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+};
+
+&nand0 {
+ status = "okay";
+
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ atmel,has-pmecc;
+ atmel,pmecc-cap = <4>;
+ atmel,pmecc-sector-size = <512>;
+ nand-on-flash-bbt;
+};
diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts
new file mode 100644
index 000000000000..669a2c6bdefc
--- /dev/null
+++ b/arch/arm/boot/dts/at91-tse850-3.dts
@@ -0,0 +1,274 @@
+/*
+ * at91-tse850-3.dts - Device Tree file for the Axentia TSE-850 3.0 board
+ *
+ * Copyright (C) 2017 Axentia Technologies AB
+ *
+ * Author: Peter Rosin <peda-koto5C5qi+TLoDKTGw+V6w@public.gmane.org>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include "at91-linea.dtsi"
+
+/ {
+ model = "Axentia TSE-850 3.0";
+ compatible = "axentia,tse850v3", "axentia,linea",
+ "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
+
+ ahb {
+ apb {
+ pinctrl@fffff200 {
+ tse850 {
+ pinctrl_usba_vbus: usba-vbus {
+ atmel,pins =
+ <AT91_PIOC 31
+ AT91_PERIPH_GPIO
+ AT91_PINCTRL_DEGLITCH>;
+ };
+ };
+ };
+
+ watchdog@fffffe40 {
+ status = "okay";
+ };
+ };
+ };
+
+ sck: oscillator {
+ compatible = "fixed-clock";
+
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ clock-output-names = "sck";
+ };
+
+ reg_3v3: regulator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "3v3-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ana: reg-ana {
+ compatible = "pwm-regulator";
+
+ regulator-name = "ANA";
+
+ pwms = <&pwm0 2 1000 PWM_POLARITY_INVERTED>;
+ pwm-dutycycle-unit = <1000>;
+ pwm-dutycycle-range = <100 1000>;
+
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <20000000>;
+ regulator-ramp-delay = <1000>;
+ };
+
+ sound {
+ compatible = "axentia,tse850-pcm5142";
+
+ axentia,cpu-dai = <&ssc0>;
+ axentia,audio-codec = <&pcm5142>;
+
+ axentia,add-gpios = <&pioA 8 GPIO_ACTIVE_LOW>;
+ axentia,loop1-gpios = <&pioA 10 GPIO_ACTIVE_LOW>;
+ axentia,loop2-gpios = <&pioA 11 GPIO_ACTIVE_LOW>;
+
+ axentia,ana-supply = <&ana>;
+ };
+
+ dac: dpot-dac {
+ compatible = "dpot-dac";
+ vref-supply = <®_3v3>;
+ io-channels = <&dpot 0>;
+ io-channel-names = "dpot";
+ #io-channel-cells = <1>;
+ };
+
+ envelope-detector {
+ compatible = "axentia,tse850-envelope-detector";
+ io-channels = <&dac 0>;
+ io-channel-names = "dac";
+
+ interrupt-parent = <&pioA>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "comp";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ ch1-red {
+ label = "ch-1:red";
+ gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
+ };
+ ch1-green {
+ label = "ch-1:green";
+ gpios = <&pioA 22 GPIO_ACTIVE_LOW>;
+ };
+ ch2-red {
+ label = "ch-2:red";
+ gpios = <&pioA 21 GPIO_ACTIVE_LOW>;
+ };
+ ch2-green {
+ label = "ch-2:green";
+ gpios = <&pioA 20 GPIO_ACTIVE_LOW>;
+ };
+ data-red {
+ label = "data:red";
+ gpios = <&pioA 19 GPIO_ACTIVE_LOW>;
+ };
+ data-green {
+ label = "data:green";
+ gpios = <&pioA 18 GPIO_ACTIVE_LOW>;
+ };
+ alarm-red {
+ label = "alarm:red";
+ gpios = <&pioA 17 GPIO_ACTIVE_LOW>;
+ };
+ alarm-green {
+ label = "alarm:green";
+ gpios = <&pioA 16 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&nand0 {
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ barebox@40000 {
+ label = "bootloader";
+ reg = <0x40000 0x60000>;
+ };
+
+ bareboxenv@c0000 {
+ label = "bareboxenv";
+ reg = <0xc0000 0x40000>;
+ };
+
+ bareboxenv2@100000 {
+ label = "bareboxenv2";
+ reg = <0x100000 0x40000>;
+ };
+
+ oftree@180000 {
+ label = "oftree";
+ reg = <0x180000 0x20000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x500000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
+
+ ovlfs@10000000 {
+ label = "ovlfs";
+ reg = <0x10000000 0x10000000>;
+ };
+};
+
+&ssc0 {
+ #sound-dai-cells = <0>;
+
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ jc42@18 {
+ compatible = "nxp,se97b", "jedec,jc-42.4-temp";
+ reg = <0x18>;
+ };
+
+ dpot: mcp4651-104@28 {
+ compatible = "microchip,mcp4651-104";
+ reg = <0x28>;
+ #io-channel-cells = <1>;
+ };
+
+ pcm5142: pcm5142@4c {
+ compatible = "ti,pcm5142";
+
+ reg = <0x4c>;
+
+ AVDD-supply = <®_3v3>;
+ DVDD-supply = <®_3v3>;
+ CPVDD-supply = <®_3v3>;
+
+ clocks = <&sck>;
+
+ pll-in = <3>;
+ pll-out = <6>;
+ };
+
+ eeprom@50 {
+ compatible = "nxp,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&usart0 {
+ status = "okay";
+
+ atmel,use-dma-rx;
+};
+
+&pwm0 {
+ status = "okay";
+
+ pinctrl-0 = <&pinctrl_pwm0_pwml2_1>;
+ pinctrl-names = "default";
+};
+
+&macb1 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@3 {
+ reg = <3>;
+
+ interrupt-parent = <&pioE>;
+ interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+ atmel,vbus-gpio = <&pioC 31 GPIO_ACTIVE_HIGH>;
+};
+
+&usb1 {
+ status = "okay";
+
+ num-ports = <1>;
+ atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>;
+ atmel,oc-gpio = <&pioC 15 GPIO_ACTIVE_LOW>;
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&dbgu {
+ status = "okay";
+
+ dmas = <0>, <0>; /* Do not use DMA for dbgu */
+};
--
2.1.4
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^ permalink raw reply related
* [PATCH v5 2/2] ARM: sama5_defconfig: add support for the Axentia TSE-850 board
From: Peter Rosin @ 2017-01-10 8:08 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: Peter Rosin, Rob Herring, Mark Rutland, Russell King,
Nicolas Ferre, Alexandre Belloni,
Jean-Christophe Plagniol-Villard,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1484035732-31635-1-git-send-email-peda-koto5C5qi+TLoDKTGw+V6w@public.gmane.org>
Signed-off-by: Peter Rosin <peda-koto5C5qi+TLoDKTGw+V6w@public.gmane.org>
---
arch/arm/configs/sama5_defconfig | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index aca8625b6fc9..bf5b3a73e38c 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -131,7 +131,7 @@ CONFIG_GPIO_SYSFS=y
CONFIG_POWER_SUPPLY=y
CONFIG_BATTERY_ACT8945A=y
CONFIG_POWER_RESET=y
-# CONFIG_HWMON is not set
+CONFIG_SENSORS_JC42=y
CONFIG_WATCHDOG=y
CONFIG_AT91SAM9X_WATCHDOG=y
CONFIG_SAMA5D4_WATCHDOG=y
@@ -142,6 +142,7 @@ CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_ACT8865=y
CONFIG_REGULATOR_ACT8945A=y
+CONFIG_REGULATOR_PWM=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
@@ -164,6 +165,7 @@ CONFIG_SND_ATMEL_SOC=y
CONFIG_SND_ATMEL_SOC_WM8904=y
# CONFIG_HID_GENERIC is not set
CONFIG_SND_ATMEL_SOC_PDMIC=y
+CONFIG_SND_ATMEL_SOC_TSE850_PCM5142=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_EHCI_HCD=y
@@ -199,6 +201,9 @@ CONFIG_AT_XDMAC=y
CONFIG_IIO=y
CONFIG_AT91_ADC=y
CONFIG_AT91_SAMA5D2_ADC=y
+CONFIG_ENVELOPE_DETECTOR=y
+CONFIG_DPOT_DAC=y
+CONFIG_MCP4531=y
CONFIG_PWM=y
CONFIG_PWM_ATMEL=y
CONFIG_PWM_ATMEL_HLCDC_PWM=y
--
2.1.4
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^ permalink raw reply related
* [PATCH v3 1/3] arm64: dts: exynos5433: add DECON_TV node
From: Andrzej Hajda @ 2017-01-10 8:24 UTC (permalink / raw)
To: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Krzysztof Kozlowski
Cc: Andrzej Hajda, Bartlomiej Zolnierkiewicz, Marek Szyprowski,
Inki Dae, Rob Herring, Mark Rutland, Javier Martinez Canillas,
devicetree-u79uwXL29TY76Z2rM5mHXA, Andi Shyti, Chanwoo Choi
In-Reply-To: <CGME20170110082433eucas1p2f7cb7b0974987e2c8294509960468fd3@eucas1p2.samsung.com>
DECON_TV is 2nd display controller on Exynos5433, used in HDMI path
or 2nd DSI path.
Signed-off-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Reviewed-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
Reviewed-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Tested-by: Hoegeun Kwon <hoegeun.kwon-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
Hi Krzysztof,
These patches are based on latest patches separating tm2 and tm2e and
touchscreen patches. I hope this is good base.
Thanks all for quick response/review.
Regards
Andrzej
v2:
- replaced magic numbers with macros,
- removed power domains,
- removed 0x prefixes from node names
v3:
- order nodes by address
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 43 ++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 68f764e..8865fae 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -751,6 +751,29 @@
};
};
+ decon_tv: decon@13880000 {
+ compatible = "samsung,exynos5433-decon-tv";
+ reg = <0x13880000 0x20b8>;
+ clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
+ <&cmu_disp CLK_ACLK_DECON_TV>,
+ <&cmu_disp CLK_ACLK_SMMU_TV0X>,
+ <&cmu_disp CLK_ACLK_XIU_TV0X>,
+ <&cmu_disp CLK_PCLK_SMMU_TV0X>,
+ <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
+ <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
+ clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
+ "aclk_xiu_decon0x", "pclk_smmu_decon0x",
+ "sclk_decon_vclk", "sclk_decon_eclk";
+ samsung,disp-sysreg = <&syscon_disp>;
+ interrupt-names = "fifo", "vsync", "lcd_sys";
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
+ iommu-names = "m0", "m1";
+ };
+
dsi: dsi@13900000 {
compatible = "samsung,exynos5433-mipi-dsi";
reg = <0x13900000 0xC0>;
@@ -912,6 +935,26 @@
#iommu-cells = <0>;
};
+ sysmmu_tv0x: sysmmu@13a20000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x13a20000 0x1000>;
+ interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "pclk", "aclk";
+ clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
+ <&cmu_disp CLK_ACLK_SMMU_TV0X>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_tv1x: sysmmu@13a30000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x13a30000 0x1000>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "pclk", "aclk";
+ clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
+ <&cmu_disp CLK_ACLK_SMMU_TV1X>;
+ #iommu-cells = <0>;
+ };
+
sysmmu_gscl0: sysmmu@0x13C80000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13C80000 0x1000>;
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 2/3] arm64: dts: exynos5433: add HDMI node
From: Andrzej Hajda @ 2017-01-10 8:24 UTC (permalink / raw)
To: linux-samsung-soc, Krzysztof Kozlowski
Cc: Andrzej Hajda, Bartlomiej Zolnierkiewicz, Marek Szyprowski,
Inki Dae, Rob Herring, Mark Rutland, Javier Martinez Canillas,
devicetree, Andi Shyti, Chanwoo Choi
In-Reply-To: <1484036664-15951-1-git-send-email-a.hajda@samsung.com>
HDMI converts RGB/I80 signal from DECON_TV to HDMI/TMDS video stream.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
---
v2:
- replaced magic numbers with macros,
- removed power domains
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 8865fae..441270f 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -837,6 +837,35 @@
};
};
+ hdmi: hdmi@13970000 {
+ compatible = "samsung,exynos5433-hdmi";
+ reg = <0x13970000 0x70000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_disp CLK_PCLK_HDMI>,
+ <&cmu_disp CLK_PCLK_HDMIPHY>,
+ <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
+ <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
+ <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
+ <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
+ <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
+ <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
+ <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
+ clock-names = "hdmi_pclk", "hdmi_i_pclk",
+ "i_tmds_clk", "i_pixel_clk",
+ "tmds_clko", "tmds_clko_user",
+ "pixel_clko", "pixel_clko_user",
+ "oscclk", "i_spdif_clk";
+ phy = <&hdmiphy>;
+ ddc = <&hsi2c_11>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ samsung,sysreg-phandle = <&syscon_disp>;
+ status = "disabled";
+ };
+
+ hdmiphy: hdmiphy@13af0000 {
+ reg = <0x13af0000 0x80>;
+ };
+
syscon_disp: syscon@13b80000 {
compatible = "syscon";
reg = <0x13b80000 0x1010>;
--
2.7.4
^ permalink raw reply related
* [PATCH v3 3/3] arm64: dts: exynos5433-tm2: enable HDMI/TV path
From: Andrzej Hajda @ 2017-01-10 8:24 UTC (permalink / raw)
To: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Krzysztof Kozlowski
Cc: Andrzej Hajda, Bartlomiej Zolnierkiewicz, Marek Szyprowski,
Inki Dae, Rob Herring, Mark Rutland, Javier Martinez Canillas,
devicetree-u79uwXL29TY76Z2rM5mHXA, Andi Shyti, Chanwoo Choi
In-Reply-To: <1484036664-15951-1-git-send-email-a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
TV path consist of following interconnected components:
- DECON_TV - display controller,
- HDMI - video signal converter RGB / HDMI,
- MHL - video signal converter HDMI / MHL,
- DDC - i2c slave device for EDID reading (on hsi2c_11 bus).
Signed-off-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Reviewed-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
Reviewed-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Tested-by: Hoegeun Kwon <hoegeun.kwon-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
v2:
- replaced magic numbers with macros,
- removed assigned-clock properties from sii8620 -
PMU clock is already confgured in PMU node
---
.../boot/dts/exynos/exynos5433-tm2-common.dtsi | 69 ++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index 669bb1f..ca90e6a 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -281,6 +281,22 @@
};
};
+&decon_tv {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ tv_to_hdmi: endpoint {
+ remote-endpoint = <&hdmi_to_tv>;
+ };
+ };
+ };
+};
+
&dsi {
status = "okay";
vddcore-supply = <&ldo6_reg>;
@@ -304,6 +320,33 @@
};
};
+&hdmi {
+ hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ vdd-supply = <&ldo6_reg>;
+ vdd_osc-supply = <&ldo7_reg>;
+ vdd_pll-supply = <&ldo6_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ hdmi_to_tv: endpoint {
+ remote-endpoint = <&tv_to_hdmi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ hdmi_to_mhl: endpoint {
+ remote-endpoint = <&mhl_to_hdmi>;
+ };
+ };
+ };
+};
+
&hsi2c_0 {
status = "okay";
clock-frequency = <2500000>;
@@ -692,6 +735,28 @@
};
};
+&hsi2c_7 {
+ status = "okay";
+
+ sii8620@39 {
+ reg = <0x39>;
+ compatible = "sil,sii8620";
+ cvcc10-supply = <&ldo36_reg>;
+ iovcc18-supply = <&ldo34_reg>;
+ interrupt-parent = <&gpf0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+ reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
+ clocks = <&pmu_system_controller 0>;
+ clock-names = "xtal";
+
+ port {
+ mhl_to_hdmi: endpoint {
+ remote-endpoint = <&hdmi_to_mhl>;
+ };
+ };
+ };
+};
+
&hsi2c_8 {
status = "okay";
@@ -735,6 +800,10 @@
};
};
+&hsi2c_11 {
+ status = "okay";
+};
+
&i2s0 {
status = "okay";
};
--
2.7.4
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^ permalink raw reply related
* Re: [PATCH v2 1/3] dt-bindings: gpio: Add binding documentation for gpio-thunderx
From: Linus Walleij @ 2017-01-10 8:42 UTC (permalink / raw)
To: David Daney
Cc: David Daney, Alexandre Courbot, Rob Herring, Mark Rutland,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, David Daney
In-Reply-To: <a1b6c9da-5b19-c9a7-3774-0bc0e9dcdeb6-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
On Mon, Jan 9, 2017 at 8:44 PM, David Daney <ddaney-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> wrote:
> On 01/09/2017 11:36 AM, Linus Walleij wrote:
>>> +Optional Properties:
>>> +- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding
>>> is used.
>>> +- interrupt-controller: Marks the device node as an interrupt
>>> controller.
>>> +- #interrupt-cells: Must be present and have value of 2 if
>>> + "interrupt-controller" is present.
>>> + - First cell is the GPIO pin number relative to the controller.
>>> + - Second cell is triggering flags as defined in interrupts.txt.
>>
>>
>> AFAICT this device has an optional list of interrupts as well?
>> One per pin even?
>
> I'm not sure I understand your question.
>
> The GPIO hardware supports an interrupt on each pin. The underlying
> interrupt mechanism is via PCI MSI-X, which are fully discoverable by the
> driver, so lack of device tree binding for the these underlying MSI-X is
> fully appropriate.
Sorry I guess I'm just ignorant about how PCI works, that has never
been my strongest subject admittedly.
So what you're saying is that PCI devices do not need specifying
interrupts not interrupt parents in the device tree?
That's fine then.
Yours,
Linus Walleij
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^ permalink raw reply
* RE: [PATCH v7 1/2] mtd: arasan: Add device tree binding documentation
From: Punnaiah Choudary Kalluri @ 2017-01-10 8:48 UTC (permalink / raw)
To: Boris Brezillon
Cc: Rob Herring, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org,
computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
richard-/L3Ra7n9ekc@public.gmane.org,
cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Michal Simek,
kalluripunnaiahchoudary-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
kpc528-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
In-Reply-To: <20170110090621.09d08cfa@bbrezillon>
Hi Boris,
Thanks. I will implement these changes and send the next series.
Regards,
Punnaiah
> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org]
> Sent: Tuesday, January 10, 2017 1:36 PM
> To: Punnaiah Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org;
> computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; richard-/L3Ra7n9ekc@public.gmane.org;
> cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org; linux-
> kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org;
> devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Michal Simek <michals-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>;
> kalluripunnaiahchoudary-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; kpc528-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
> Subject: Re: [PATCH v7 1/2] mtd: arasan: Add device tree binding
> documentation
>
> Hi Punnaiah,
>
> On Tue, 10 Jan 2017 06:03:25 +0000
> Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> wrote:
>
> > Hi Rob,
> >
> > Thanks for the review.
> >
> > > -----Original Message-----
> > > From: Rob Herring [mailto:robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> > > Sent: Tuesday, January 10, 2017 11:06 AM
> > > To: Punnaiah Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> > > Cc: dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org; computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org;
> > > boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org; marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org;
> > > richard-/L3Ra7n9ekc@public.gmane.org; cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org;
> linux-
> > > kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org;
> > > devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Michal Simek <michals-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>;
> > > kalluripunnaiahchoudary-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; kpc528-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; Punnaiah
> > > Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> > > Subject: Re: [PATCH v7 1/2] mtd: arasan: Add device tree binding
> > > documentation
> > >
> > > On Mon, Jan 09, 2017 at 08:28:53AM +0530, Punnaiah Choudary Kalluri
> wrote:
> > > > This patch adds the dts binding document for arasan nand flash
> > > > controller.
> > > >
> > > > Signed-off-by: Punnaiah Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> > > > ---
> > > > Changes in v7:
> > > > - Corrected the acronyms those should be in caps
> > > > changes in v6:
> > > > - Removed num-cs property
> > > > - Separated nandchip from nand controller
> > > > changes in v5:
> > > > - None
> > > > Changes in v4:
> > > > - Added num-cs property
> > > > - Added clock support
> > > > Changes in v3:
> > > > - None
> > > > Changes in v2:
> > > > - None
> > > > ---
> > > > .../devicetree/bindings/mtd/arasan_nfc.txt | 38
> > > ++++++++++++++++++++++
> > > > 1 file changed, 38 insertions(+)
> > > > create mode 100644
> > > Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> > > b/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> > > > new file mode 100644
> > > > index 0000000..f20adfc
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> > > > @@ -0,0 +1,38 @@
> > > > +Arasan NAND Flash Controller with ONFI 3.1 support
> > > > +
> > > > +Required properties:
> > > > +- compatible: Should be "arasan,nfc-v3p10"
> > >
> > > Needs a note that it must also have an SoC specific compatible string.
> > >
> > Sorry, I couldn't understand this comment. Could you elaborate it?
>
> Arasan is an IP vendor, and those IPs are usually embedded in specific
> SoCs. I guess Rob was suggesting to define something like:
>
> compatible = "<soc-vendor>,<ip-revision>", "arasan,<ip-revision>";
>
> This way you can differentiate minor changes/tweaks between each SoC
> (each SoC vendor usually enable/disable specific features based on
> their needs).
>
> >
> > > > +- reg: Memory map for module access
> > > > +- interrupt-parent: Interrupt controller the interrupt is routed through
> > > > +- interrupts: Should contain the interrupt for the device
> > > > +- clock-name: List of input clocks - "clk_sys", "clk_flash"
> > >
> > > clk_ is redundant.
> > >
> >
> > I have defined these clock names as per the controller data sheet.
> > So, I feel it is fine to have them in sync with the datasheet.
> > Please let me know if you still want me to change this.
>
> We already know this is a clock, hence the unneeded clk_ prefix. Please
> drop it.
>
> Thanks,
>
> Boris
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^ permalink raw reply
* Re: [PATCH v5 3/3] dmaengine: xilinx_dma: Fix race condition in the driver for multiple descriptor scenario
From: Vinod Koul @ 2017-01-10 8:49 UTC (permalink / raw)
To: Kedareswara rao Appana
Cc: robh+dt, mark.rutland, dan.j.williams, michal.simek,
soren.brinkmann, appanad, moritz.fischer, laurent.pinchart, luis,
Jose.Abreu, dmaengine, linux-arm-kernel, linux-kernel, devicetree
In-Reply-To: <1483771530-8545-4-git-send-email-appanad@xilinx.com>
On Sat, Jan 07, 2017 at 12:15:30PM +0530, Kedareswara rao Appana wrote:
> When driver is handling AXI DMA SoftIP
> When user submits multiple descriptors back to back on the S2MM(recv)
> side with the current driver flow the last buffer descriptor next bd
> points to a invalid location resulting the invalid data or errors in the
> DMA engine.
Can you rephrase this, it a bit hard to understand.
>
> This patch fixes this issue by creating a BD Chain during
whats a BD?
> channel allocation itself and use those BD's.
>
> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
> ---
> Changes for v5:
> ---> None.
> Changes for v4:
> ---> None.
> Changes for v3:
> ---> None.
> Changes for v2:
> ---> None.
>
> drivers/dma/xilinx/xilinx_dma.c | 133 +++++++++++++++++++++++++---------------
> 1 file changed, 83 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index 0e9c02e..af2159d 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -163,6 +163,7 @@
> #define XILINX_DMA_BD_SOP BIT(27)
> #define XILINX_DMA_BD_EOP BIT(26)
> #define XILINX_DMA_COALESCE_MAX 255
> +#define XILINX_DMA_NUM_DESCS 255
why 255?
> #define XILINX_DMA_NUM_APP_WORDS 5
>
> /* Multi-Channel DMA Descriptor offsets*/
> @@ -310,6 +311,7 @@ struct xilinx_dma_tx_descriptor {
> * @pending_list: Descriptors waiting
> * @active_list: Descriptors ready to submit
> * @done_list: Complete descriptors
> + * @free_seg_list: Free descriptors
> * @common: DMA common channel
> * @desc_pool: Descriptors pool
> * @dev: The dma device
> @@ -331,7 +333,9 @@ struct xilinx_dma_tx_descriptor {
> * @desc_submitcount: Descriptor h/w submitted count
> * @residue: Residue for AXI DMA
> * @seg_v: Statically allocated segments base
> + * @seg_p: Physical allocated segments base
> * @cyclic_seg_v: Statically allocated segment base for cyclic transfers
> + * @cyclic_seg_p: Physical allocated segments base for cyclic dma
> * @start_transfer: Differentiate b/w DMA IP's transfer
> */
> struct xilinx_dma_chan {
> @@ -342,6 +346,7 @@ struct xilinx_dma_chan {
> struct list_head pending_list;
> struct list_head active_list;
> struct list_head done_list;
> + struct list_head free_seg_list;
> struct dma_chan common;
> struct dma_pool *desc_pool;
> struct device *dev;
> @@ -363,7 +368,9 @@ struct xilinx_dma_chan {
> u32 desc_submitcount;
> u32 residue;
> struct xilinx_axidma_tx_segment *seg_v;
> + dma_addr_t seg_p;
> struct xilinx_axidma_tx_segment *cyclic_seg_v;
> + dma_addr_t cyclic_seg_p;
> void (*start_transfer)(struct xilinx_dma_chan *chan);
> u16 tdest;
> };
> @@ -569,17 +576,31 @@ static struct xilinx_axidma_tx_segment *
> xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
> {
> struct xilinx_axidma_tx_segment *segment;
> - dma_addr_t phys;
> -
> - segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
> - if (!segment)
> - return NULL;
> + unsigned long flags;
>
> - segment->phys = phys;
> + spin_lock_irqsave(&chan->lock, flags);
> + if (!list_empty(&chan->free_seg_list)) {
> + segment = list_first_entry(&chan->free_seg_list,
> + struct xilinx_axidma_tx_segment,
> + node);
> + list_del(&segment->node);
> + }
> + spin_unlock_irqrestore(&chan->lock, flags);
>
> return segment;
> }
>
> +static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw)
> +{
> + u32 next_desc = hw->next_desc;
> + u32 next_desc_msb = hw->next_desc_msb;
> +
> + memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw));
> +
> + hw->next_desc = next_desc;
> + hw->next_desc_msb = next_desc_msb;
> +}
> +
> /**
> * xilinx_dma_free_tx_segment - Free transaction segment
> * @chan: Driver specific DMA channel
> @@ -588,7 +609,9 @@ xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
> static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,
> struct xilinx_axidma_tx_segment *segment)
> {
> - dma_pool_free(chan->desc_pool, segment, segment->phys);
> + xilinx_dma_clean_hw_desc(&segment->hw);
> +
> + list_add_tail(&segment->node, &chan->free_seg_list);
> }
>
> /**
> @@ -713,16 +736,26 @@ static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)
> static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
> {
> struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
> + unsigned long flags;
>
> dev_dbg(chan->dev, "Free all channel resources.\n");
>
> xilinx_dma_free_descriptors(chan);
> +
> if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
> - xilinx_dma_free_tx_segment(chan, chan->cyclic_seg_v);
> - xilinx_dma_free_tx_segment(chan, chan->seg_v);
> + spin_lock_irqsave(&chan->lock, flags);
> + INIT_LIST_HEAD(&chan->free_seg_list);
> + spin_unlock_irqrestore(&chan->lock, flags);
> +
> + /* Free Memory that is allocated for cyclic DMA Mode */
> + dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v),
> + chan->cyclic_seg_v, chan->cyclic_seg_p);
> + }
> +
> + if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) {
> + dma_pool_destroy(chan->desc_pool);
> + chan->desc_pool = NULL;
> }
> - dma_pool_destroy(chan->desc_pool);
> - chan->desc_pool = NULL;
> }
>
> /**
> @@ -805,6 +838,7 @@ static void xilinx_dma_do_tasklet(unsigned long data)
> static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
> {
> struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
> + int i;
>
> /* Has this channel already been allocated? */
> if (chan->desc_pool)
> @@ -815,11 +849,30 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
> * for meeting Xilinx VDMA specification requirement.
> */
> if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
> - chan->desc_pool = dma_pool_create("xilinx_dma_desc_pool",
> - chan->dev,
> - sizeof(struct xilinx_axidma_tx_segment),
> - __alignof__(struct xilinx_axidma_tx_segment),
> - 0);
> + /* Allocate the buffer descriptors. */
> + chan->seg_v = dma_zalloc_coherent(chan->dev,
> + sizeof(*chan->seg_v) *
> + XILINX_DMA_NUM_DESCS,
> + &chan->seg_p, GFP_KERNEL);
> + if (!chan->seg_v) {
> + dev_err(chan->dev,
> + "unable to allocate channel %d descriptors\n",
> + chan->id);
> + return -ENOMEM;
> + }
> +
> + for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
> + chan->seg_v[i].hw.next_desc =
> + lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
> + ((i + 1) % XILINX_DMA_NUM_DESCS));
> + chan->seg_v[i].hw.next_desc_msb =
> + upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
> + ((i + 1) % XILINX_DMA_NUM_DESCS));
> + chan->seg_v[i].phys = chan->seg_p +
> + sizeof(*chan->seg_v) * i;
> + list_add_tail(&chan->seg_v[i].node,
> + &chan->free_seg_list);
> + }
> } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
> chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool",
> chan->dev,
> @@ -834,7 +887,8 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
> 0);
> }
>
> - if (!chan->desc_pool) {
> + if (!chan->desc_pool &&
> + (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA)) {
> dev_err(chan->dev,
> "unable to allocate channel %d descriptor pool\n",
> chan->id);
> @@ -843,22 +897,20 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
>
> if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
> /*
> - * For AXI DMA case after submitting a pending_list, keep
> - * an extra segment allocated so that the "next descriptor"
> - * pointer on the tail descriptor always points to a
> - * valid descriptor, even when paused after reaching taildesc.
> - * This way, it is possible to issue additional
> - * transfers without halting and restarting the channel.
> - */
> - chan->seg_v = xilinx_axidma_alloc_tx_segment(chan);
> -
> - /*
> * For cyclic DMA mode we need to program the tail Descriptor
> * register with a value which is not a part of the BD chain
> * so allocating a desc segment during channel allocation for
> * programming tail descriptor.
> */
> - chan->cyclic_seg_v = xilinx_axidma_alloc_tx_segment(chan);
> + chan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,
> + sizeof(*chan->cyclic_seg_v),
> + &chan->cyclic_seg_p, GFP_KERNEL);
> + if (!chan->cyclic_seg_v) {
> + dev_err(chan->dev,
> + "unable to allocate desc segment for cyclic DMA\n");
> + return -ENOMEM;
> + }
> + chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
> }
>
> dma_cookie_init(dchan);
> @@ -1198,7 +1250,7 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
> static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
> {
> struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
> - struct xilinx_axidma_tx_segment *tail_segment, *old_head, *new_head;
> + struct xilinx_axidma_tx_segment *tail_segment;
> u32 reg;
>
> if (chan->err)
> @@ -1217,21 +1269,6 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
> tail_segment = list_last_entry(&tail_desc->segments,
> struct xilinx_axidma_tx_segment, node);
>
> - if (chan->has_sg && !chan->xdev->mcdma) {
> - old_head = list_first_entry(&head_desc->segments,
> - struct xilinx_axidma_tx_segment, node);
> - new_head = chan->seg_v;
> - /* Copy Buffer Descriptor fields. */
> - new_head->hw = old_head->hw;
> -
> - /* Swap and save new reserve */
> - list_replace_init(&old_head->node, &new_head->node);
> - chan->seg_v = old_head;
> -
> - tail_segment->hw.next_desc = chan->seg_v->phys;
> - head_desc->async_tx.phys = new_head->phys;
> - }
> -
> reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
>
> if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
> @@ -1729,7 +1766,7 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
> {
> struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
> struct xilinx_dma_tx_descriptor *desc;
> - struct xilinx_axidma_tx_segment *segment = NULL, *prev = NULL;
> + struct xilinx_axidma_tx_segment *segment = NULL;
> u32 *app_w = (u32 *)context;
> struct scatterlist *sg;
> size_t copy;
> @@ -1780,10 +1817,6 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
> XILINX_DMA_NUM_APP_WORDS);
> }
>
> - if (prev)
> - prev->hw.next_desc = segment->phys;
> -
> - prev = segment;
> sg_used += copy;
>
> /*
> @@ -1797,7 +1830,6 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
> segment = list_first_entry(&desc->segments,
> struct xilinx_axidma_tx_segment, node);
> desc->async_tx.phys = segment->phys;
> - prev->hw.next_desc = segment->phys;
>
> /* For the last DMA_MEM_TO_DEV transfer, set EOP */
> if (chan->direction == DMA_MEM_TO_DEV) {
> @@ -2341,6 +2373,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
> INIT_LIST_HEAD(&chan->pending_list);
> INIT_LIST_HEAD(&chan->done_list);
> INIT_LIST_HEAD(&chan->active_list);
> + INIT_LIST_HEAD(&chan->free_seg_list);
>
> /* Retrieve the channel properties from the device tree */
> has_dre = of_property_read_bool(node, "xlnx,include-dre");
> --
> 2.1.2
>
--
~Vinod
^ permalink raw reply
* Re: [PATCH v7 5/8] IIO: add bindings for STM32 timer trigger driver
From: Benjamin Gaignard @ 2017-01-10 8:55 UTC (permalink / raw)
To: Rob Herring
Cc: Lee Jones, Mark Rutland, Alexandre Torgue, devicetree,
Linux Kernel Mailing List, Thierry Reding, Linux PWM List,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, linux-iio, linux-arm-kernel,
Fabrice Gasnier, Gerald Baeza, Arnaud Pouliquen, Linus Walleij,
Linaro Kernel Mailman List, Benjamin Gaignard <benjamin.g>
In-Reply-To: <20170109180448.f3pcpuarhcddo76b@rob-hp-laptop>
2017-01-09 19:04 GMT+01:00 Rob Herring <robh@kernel.org>:
> On Thu, Jan 05, 2017 at 10:25:41AM +0100, Benjamin Gaignard wrote:
>> Define bindings for STM32 timer trigger
>>
>> version 4:
>> - remove triggers enumeration from DT
>> - add reg parameter
>>
>> version 3:
>> - change file name
>> - add cross reference with mfd bindings
>>
>> version 2:
>> - only keep one compatible
>> - add DT parameters to set lists of the triggers:
>> one list describe the triggers created by the device
>> another one give the triggers accepted by the device
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>> ---
>> .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++++++++++++++++++++++
>> 1 file changed, 23 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>>
>> diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>> new file mode 100644
>> index 0000000..36a6c4a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>> @@ -0,0 +1,23 @@
>> +STMicroelectronics STM32 Timers IIO timer bindings
>> +
>> +Must be a sub-node of an STM32 Timers device tree node.
>> +See ../mfd/stm32-timers.txt for details about the parent node.
>> +
>> +Required parameters:
>> +- compatible: Must be "st,stm32-timer-trigger".
>> +- reg: Define triggers configuration of the hardware IP.
>
> Valid values? Not sure this makes sense for use of reg. reg should be
> how you address or id a device.
I use reg like an id to distinguish device and get the right
configuration inside
the driver.
>
>> +
>> +Example:
>> + timers@40010000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "st,stm32-timers";
>> + reg = <0x40010000 0x400>;
>> + clocks = <&rcc 0 160>;
>> + clock-names = "clk_int";
>> +
>> + timer {
>
> This would also need an unit address.
Ok I will fix that
>
>> + compatible = "st,stm32-timer-trigger";
>> + reg = <0>;
>> + };
>> + };
>> --
>> 1.9.1
>>
--
Benjamin Gaignard
Graphic Study Group
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH v7 2/8] MFD: add STM32 Timers driver
From: Benjamin Gaignard @ 2017-01-10 8:56 UTC (permalink / raw)
To: Rob Herring
Cc: Lee Jones, Mark Rutland, Alexandre Torgue, devicetree,
Linux Kernel Mailing List, Thierry Reding, Linux PWM List,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, linux-iio, linux-arm-kernel,
Fabrice Gasnier, Gerald Baeza, Arnaud Pouliquen, Linus Walleij,
Linaro Kernel Mailman List, Benjamin Gaignard <benjamin.g>
In-Reply-To: <20170109180051.uwd4su3maj5gkf5l@rob-hp-laptop>
2017-01-09 19:00 GMT+01:00 Rob Herring <robh@kernel.org>:
> On Thu, Jan 05, 2017 at 10:25:38AM +0100, Benjamin Gaignard wrote:
>> This hardware block could at used at same time for PWM generation
>> and IIO timers.
>> PWM and IIO timer configuration are mixed in the same registers
>> so we need a multi fonction driver to be able to share those registers.
>>
>> version 7:
>> - rebase on v4.10-rc2
>>
>> version 6:
>> - rename files to stm32-timers
>> - rename functions to stm32_timers_xxx
>>
>> version 5:
>> - fix Lee comments about detect function
>> - add missing dependency on REGMAP_MMIO
>>
>> version 4:
>> - add a function to detect Auto Reload Register (ARR) size
>> - rename the structure shared with other drivers
>>
>> version 2:
>> - rename driver "stm32-gptimer" to be align with SoC documentation
>> - only keep one compatible
>> - use of_platform_populate() instead of devm_mfd_add_devices()
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>> ---
>> .../devicetree/bindings/mfd/stm32-timers.txt | 2 +-
>> drivers/mfd/Kconfig | 11 +++
>> drivers/mfd/Makefile | 2 +
>> drivers/mfd/stm32-timers.c | 80 ++++++++++++++++++++++
>> include/linux/mfd/stm32-timers.h | 71 +++++++++++++++++++
>> 5 files changed, 165 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/mfd/stm32-timers.c
>> create mode 100644 include/linux/mfd/stm32-timers.h
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/stm32-timers.txt b/Documentation/devicetree/bindings/mfd/stm32-timers.txt
>> index a73301d..897e7c2 100644
>> --- a/Documentation/devicetree/bindings/mfd/stm32-timers.txt
>> +++ b/Documentation/devicetree/bindings/mfd/stm32-timers.txt
>> @@ -12,7 +12,7 @@ Required parameters:
>>
>> - reg: Physical base address and length of the controller's
>> registers.
>> -- clock-names: Set to "int".
>> +- clock-names: Set to "int".
>
> This hunk should be dropped or moved to previous patch.
I will move it in the previous patch
>
>> - clocks: Phandle to the clock used by the timer module.
>> For Clk properties, please refer to ../clock/clock-bindings.txt
>>
--
Benjamin Gaignard
Graphic Study Group
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v5 0/5] powernv:stop: Use psscr_val,mask provided by firmware
From: Gautham R. Shenoy @ 2017-01-10 9:06 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Rafael J. Wysocki, Daniel Lezcano, Michael Neuling,
Vaidyanathan Srinivasan, Shreyas B. Prabhu, Shilpasri G Bhat,
Stewart Smith, Balbir Singh, Oliver O'Halloran
Cc: mark.rutland, devicetree, Gautham R. Shenoy, linux-pm,
linux-kernel, Rob Herring, linuxppc-dev
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
This is the fifth iteration of the patchset to use the psscr_val and
psscr_mask provided by the firmware for each of the stop states.
The previous versions can be found here:
[v4]: https://lkml.org/lkml/2016/12/9/288
[v3]: https://lkml.org/lkml/2016/11/10/37
[v2]: https://lkml.org/lkml/2016/10/27/143
[v1]: https://lkml.org/lkml/2016/9/29/45
This version addresses the feedback provided by Balbir and Vaidy to
v4. The key changes are:
- The current code had some functions/variables names containing
arch300_* while others had power9*_. Uniformly rename this to arch300_*.
- Add a comment for POWERNV_THRESHOLD_LATENCY_NS.
- In case of a new firmware, validate that the PSSCR values provided
by the firmware preserves the following invariants as required by the ISA:
a) While running in Hypervisor mode (HV=1), EC bit must have the
same value as ESL bit.
b) For deep stop states that result in state-loss, ESL bit must be set.
- Optimize the sequence of instructions before executing stop with
ESL=EC=0. Reduce one instruction.
- Fixed the typos in the Documentation for the device-tree bindings
describing the stop-states exposed by the firmware.
Synopsis
==========
In the current implementation, the code for ISA
v3.0 stop implementation has a couple of shortcomings.
a) The code hand-codes the values for ESL,EC,TR,MTL bits of PSSCR and
uses only the RL field from the firmware. While this is not
incorrect, since the hand-coded values are legitimate, it is not a
very flexible design since the firmware has the capability to
communicate these values via the "ibm,cpu-idle-state-psscr" and
"ibm,cpu-idle-state-psscr-mask" properties. In case where the
firmware provides values for these fields that is different from
the hand-coded values, the current code will not work as intended.
b) Due to issue a), the current code assumes that ESL=EC=1 for all the
stop states and hence the wakeup from the stop instruction will
happen at 0x100, the system-reset vector. However, the ISA v3.0
allows the ESL=EC=0 behaviour where the corresponding stop-state
loses no state and wakes up from the subsequent instruction. The
current code doesn't handle this case.
This patch series addresses these issues.
The first patch in the series renames the existing
IDLE_STATE_ENTER_SEQ macro to IDLE_STATE_ENTER_SEQ_NORET. It reuses
the name IDLE_STATE_ENTER_SEQ for entering into stop-states which wake
up at the subsequent instruction.
The second patch in the series uniformly renames all occurences of "power9"
to "arch300" thereby making the variable/function names consistent.
The third patch adds a helper function in cpuidle-powernv.c for
initializing entries of the powernv_states[] table that is passed to
the cpu-idle core. This eliminates some of the code duplication in the
function that discovers and initializes the stop states.
The fourth patch in the series fixes issues a) and b) by ensuring that
the psscr-value and the psscr-mask provided by the firmware are what
will be used to set a particular stop state. It also adds support for
handling wake-up from stop states which were entered with ESL=EC=0.
It validates hat the psscr values exposed by the firmware maintains
the invariants mentioned in the ISA.
The fourth patch also handles the older firmware which sets only the
Requested Level (RL) field in the psscr and psscr-mask exposed in the
device tree. In the presence of such older firmware, this patch will
set the default sane values for for remaining PSSCR fields (i.e PSLL,
MTL, ESL, EC, and TR).
The fifth patch provides the documentation for the device-tree
bindings describing the idle state properties under the @power-mgt
node in the device-tree.
The skiboot patch populates all the relevant fields in the PSSCR
values and the mask for all the stop states can be found here:
https://lists.ozlabs.org/pipermail/skiboot/2016-September/004869.html
Gautham R. Shenoy (5):
powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro
powernv:stop: Uniformly rename power9 to arch300
cpuidle:powernv: Add helper function to populate powernv idle states.
powernv: Pass PSSCR value and mask to power9_idle_stop
Documentation:powerpc: Add device-tree bindings for power-mgt
.../devicetree/bindings/powerpc/opal/power-mgt.txt | 125 ++++++++++++++++++
arch/powerpc/include/asm/cpuidle.h | 49 ++++++-
arch/powerpc/include/asm/processor.h | 3 +-
arch/powerpc/kernel/exceptions-64s.S | 6 +-
arch/powerpc/kernel/idle_book3s.S | 53 ++++----
arch/powerpc/platforms/powernv/idle.c | 142 ++++++++++++++++++---
arch/powerpc/platforms/powernv/powernv.h | 3 +-
arch/powerpc/platforms/powernv/smp.c | 14 +-
drivers/cpuidle/cpuidle-powernv.c | 129 +++++++++++++------
include/linux/cpuidle.h | 1 +
10 files changed, 435 insertions(+), 90 deletions(-)
create mode 100644 Documentation/devicetree/bindings/powerpc/opal/power-mgt.txt
--
1.9.4
^ permalink raw reply
* [PATCH v5 1/5] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro
From: Gautham R. Shenoy @ 2017-01-10 9:07 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Rafael J. Wysocki, Daniel Lezcano, Michael Neuling,
Vaidyanathan Srinivasan, Shreyas B. Prabhu, Shilpasri G Bhat,
Stewart Smith, Balbir Singh, Oliver O'Halloran
Cc: mark.rutland, devicetree, Gautham R. Shenoy, linux-pm,
linux-kernel, Rob Herring, linuxppc-dev
In-Reply-To: <1484039224-5630-1-git-send-email-ego@linux.vnet.ibm.com>
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
Currently all the low-power idle states are expected to wake up
at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ
that puts the CPU to an idle state and never returns.
On ISA v3.0, when the ESL and EC bits in the PSSCR are zero, the CPU
is expected to wake up at the next instruction of the idle
instruction.
This patch adds a new macro named IDLE_STATE_ENTER_SEQ_NORET for the
no-return variant and reuses the name IDLE_STATE_ENTER_SEQ
for a variant that allows resuming operation at the instruction next
to the idle-instruction.
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
---
No changes from v4
arch/powerpc/include/asm/cpuidle.h | 5 ++++-
arch/powerpc/kernel/exceptions-64s.S | 6 +++---
arch/powerpc/kernel/idle_book3s.S | 10 +++++-----
3 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/asm/cpuidle.h
index 3919332..0a3255b 100644
--- a/arch/powerpc/include/asm/cpuidle.h
+++ b/arch/powerpc/include/asm/cpuidle.h
@@ -21,7 +21,7 @@
/* Idle state entry routines */
#ifdef CONFIG_PPC_P7_NAP
-#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \
+#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \
/* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
std r0,0(r1); \
ptesync; \
@@ -29,6 +29,9 @@
1: cmpd cr0,r0,r0; \
bne 1b; \
IDLE_INST; \
+
+#define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST) \
+ IDLE_STATE_ENTER_SEQ(IDLE_INST) \
b .
#endif /* CONFIG_PPC_P7_NAP */
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 1ba82ea..7aa8afc 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -381,12 +381,12 @@ EXC_COMMON_BEGIN(machine_check_handle_early)
lbz r3,PACA_THREAD_IDLE_STATE(r13)
cmpwi r3,PNV_THREAD_NAP
bgt 10f
- IDLE_STATE_ENTER_SEQ(PPC_NAP)
+ IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
/* No return */
10:
cmpwi r3,PNV_THREAD_SLEEP
bgt 2f
- IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
+ IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
/* No return */
2:
@@ -400,7 +400,7 @@ EXC_COMMON_BEGIN(machine_check_handle_early)
*/
ori r13,r13,1
SET_PACA(r13)
- IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
+ IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
/* No return */
4:
#endif
diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S
index 72dac0b..be90e2f 100644
--- a/arch/powerpc/kernel/idle_book3s.S
+++ b/arch/powerpc/kernel/idle_book3s.S
@@ -205,7 +205,7 @@ pnv_enter_arch207_idle_mode:
stb r3,PACA_THREAD_IDLE_STATE(r13)
cmpwi cr3,r3,PNV_THREAD_SLEEP
bge cr3,2f
- IDLE_STATE_ENTER_SEQ(PPC_NAP)
+ IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
/* No return */
2:
/* Sleep or winkle */
@@ -239,7 +239,7 @@ pnv_fastsleep_workaround_at_entry:
common_enter: /* common code for all the threads entering sleep or winkle */
bgt cr3,enter_winkle
- IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
+ IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
fastsleep_workaround_at_entry:
ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
@@ -261,7 +261,7 @@ fastsleep_workaround_at_entry:
enter_winkle:
bl save_sprs_to_stack
- IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
+ IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
/*
* r3 - requested stop state
@@ -280,7 +280,7 @@ power_enter_stop:
ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
cmpd r3,r4
bge 2f
- IDLE_STATE_ENTER_SEQ(PPC_STOP)
+ IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
2:
/*
* Entering deep idle state.
@@ -302,7 +302,7 @@ lwarx_loop_stop:
bl save_sprs_to_stack
- IDLE_STATE_ENTER_SEQ(PPC_STOP)
+ IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
_GLOBAL(power7_idle)
/* Now check if user or arch enabled NAP mode */
--
1.9.4
^ permalink raw reply related
* [PATCH v5 2/5] powernv:stop: Uniformly rename power9 to arch300
From: Gautham R. Shenoy @ 2017-01-10 9:07 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Rafael J. Wysocki, Daniel Lezcano, Michael Neuling,
Vaidyanathan Srinivasan, Shreyas B. Prabhu, Shilpasri G Bhat,
Stewart Smith, Balbir Singh, Oliver O'Halloran
Cc: mark.rutland, devicetree, Gautham R. Shenoy, linux-pm,
linux-kernel, Rob Herring, linuxppc-dev
In-Reply-To: <1484039224-5630-1-git-send-email-ego@linux.vnet.ibm.com>
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
Balbir pointed out that in idle_book3s.S and powernv/idle.c some
functions and variables had power9 in their names while some others
had arch300.
This patch uniformly renames all instances of "power9" in the
variables/function/comments occuring in these files to "arch300" in
order to make them consistent.
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
---
New patch in v5
arch/powerpc/include/asm/processor.h | 2 +-
arch/powerpc/kernel/idle_book3s.S | 13 +++++++------
arch/powerpc/platforms/powernv/idle.c | 6 +++---
arch/powerpc/platforms/powernv/smp.c | 2 +-
drivers/cpuidle/cpuidle-powernv.c | 2 +-
5 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index c07c31b..4b47308 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -458,7 +458,7 @@ static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
extern unsigned long power7_nap(int check_irq);
extern unsigned long power7_sleep(void);
extern unsigned long power7_winkle(void);
-extern unsigned long power9_idle_stop(unsigned long stop_level);
+extern unsigned long arch300_idle_stop(unsigned long stop_level);
extern void flush_instruction_cache(void);
extern void hard_reset_now(void);
diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S
index be90e2f..7f6657f 100644
--- a/arch/powerpc/kernel/idle_book3s.S
+++ b/arch/powerpc/kernel/idle_book3s.S
@@ -106,8 +106,9 @@ core_idle_lock_held:
/*
* Pass requested state in r3:
- * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
- * - Requested STOP state in POWER9
+ * r3 - PNV_THREAD_NAP/SLEEP/WINKLE on ISA 2.07 or less
+ (POWER7,POWER8)
+ * - Requested STOP state on ISA 3.0 CPUs
*
* To check IRQ_HAPPENED in r4
* 0 - don't check
@@ -357,7 +358,7 @@ ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
/*
* r3 - requested stop state
*/
-_GLOBAL(power9_idle_stop)
+_GLOBAL(arch300_idle_stop)
LOAD_REG_IMMEDIATE(r4, PSSCR_HV_TEMPLATE)
or r4,r4,r3
mtspr SPRN_PSSCR, r4
@@ -377,7 +378,7 @@ _GLOBAL(pnv_restore_hyp_resource)
BEGIN_FTR_SECTION
ld r2,PACATOC(r13);
/*
- * POWER ISA 3. Use PSSCR to determine if we
+ * POWER ISA 3.0. Use PSSCR to determine if we
* are waking up from deep idle state
*/
LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
@@ -429,8 +430,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
/*
* Called if waking up from idle state which can cause either partial or
* complete hyp state loss.
- * In POWER8, called if waking up from fastsleep or winkle
- * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
+ * In ISA 2.07 (POWER8),called if waking up from fastsleep or winkle
+ * In ISA 3.0, called if waking up from stop state >= pnv_first_deep_stop_state
*
* r13 - PACA
* cr3 - gt if waking up with partial/complete hypervisor state loss
diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c
index 479c256..c3a2fac 100644
--- a/arch/powerpc/platforms/powernv/idle.c
+++ b/arch/powerpc/platforms/powernv/idle.c
@@ -241,10 +241,10 @@ static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600,
/*
* Used for ppc_md.power_save which needs a function with no parameters
*/
-static void power9_idle(void)
+static void arch300_idle(void)
{
/* Requesting stop state 0 */
- power9_idle_stop(0);
+ arch300_idle_stop(0);
}
/*
* First deep stop state. Used to figure out when to save/restore
@@ -415,7 +415,7 @@ static int __init pnv_init_idle_states(void)
if (supported_cpuidle_states & OPAL_PM_NAP_ENABLED)
ppc_md.power_save = power7_idle;
else if (supported_cpuidle_states & OPAL_PM_STOP_INST_FAST)
- ppc_md.power_save = power9_idle;
+ ppc_md.power_save = arch300_idle;
out:
return 0;
diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c
index c789258..c931bb2 100644
--- a/arch/powerpc/platforms/powernv/smp.c
+++ b/arch/powerpc/platforms/powernv/smp.c
@@ -183,7 +183,7 @@ static void pnv_smp_cpu_kill_self(void)
ppc64_runlatch_off();
if (cpu_has_feature(CPU_FTR_ARCH_300))
- srr1 = power9_idle_stop(pnv_deepest_stop_state);
+ srr1 = arch300_idle_stop(pnv_deepest_stop_state);
else if (idle_states & OPAL_PM_WINKLE_ENABLED)
srr1 = power7_winkle();
else if ((idle_states & OPAL_PM_SLEEP_ENABLED) ||
diff --git a/drivers/cpuidle/cpuidle-powernv.c b/drivers/cpuidle/cpuidle-powernv.c
index 7fe442c..a7f6528 100644
--- a/drivers/cpuidle/cpuidle-powernv.c
+++ b/drivers/cpuidle/cpuidle-powernv.c
@@ -102,7 +102,7 @@ static int stop_loop(struct cpuidle_device *dev,
int index)
{
ppc64_runlatch_off();
- power9_idle_stop(stop_psscr_table[index]);
+ arch300_idle_stop(stop_psscr_table[index]);
ppc64_runlatch_on();
return index;
}
--
1.9.4
^ permalink raw reply related
* [PATCH v5 3/5] cpuidle:powernv: Add helper function to populate powernv idle states.
From: Gautham R. Shenoy @ 2017-01-10 9:07 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Rafael J. Wysocki, Daniel Lezcano, Michael Neuling,
Vaidyanathan Srinivasan, Shreyas B. Prabhu, Shilpasri G Bhat,
Stewart Smith, Balbir Singh, Oliver O'Halloran
Cc: mark.rutland, devicetree, Gautham R. Shenoy, linux-pm,
linux-kernel, Rob Herring, linuxppc-dev
In-Reply-To: <1484039224-5630-1-git-send-email-ego@linux.vnet.ibm.com>
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
In the current code for powernv_add_idle_states, there is a lot of code
duplication while initializing an idle state in powernv_states table.
Add an inline helper function to populate the powernv_states[] table
for a given idle state. Invoke this for populating the "Nap",
"Fastsleep" and the stop states in powernv_add_idle_states.
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
---
[v4] --> [v5] : Added a comment above POWERNV_THRESHOLD_LATENCY_NS
drivers/cpuidle/cpuidle-powernv.c | 89 +++++++++++++++++++++++----------------
include/linux/cpuidle.h | 1 +
2 files changed, 54 insertions(+), 36 deletions(-)
diff --git a/drivers/cpuidle/cpuidle-powernv.c b/drivers/cpuidle/cpuidle-powernv.c
index a7f6528..a21f1f0 100644
--- a/drivers/cpuidle/cpuidle-powernv.c
+++ b/drivers/cpuidle/cpuidle-powernv.c
@@ -20,6 +20,10 @@
#include <asm/opal.h>
#include <asm/runlatch.h>
+/*
+ * Expose only those Hardware idle states via the cpuidle framework
+ * that have latency value below POWERNV_THRESHOLD_LATENCY_NS.
+ */
#define POWERNV_THRESHOLD_LATENCY_NS 200000
struct cpuidle_driver powernv_idle_driver = {
@@ -167,6 +171,24 @@ static int powernv_cpuidle_driver_init(void)
return 0;
}
+static inline void add_powernv_state(int index, const char *name,
+ unsigned int flags,
+ int (*idle_fn)(struct cpuidle_device *,
+ struct cpuidle_driver *,
+ int),
+ unsigned int target_residency,
+ unsigned int exit_latency,
+ u64 psscr_val)
+{
+ strlcpy(powernv_states[index].name, name, CPUIDLE_NAME_LEN);
+ strlcpy(powernv_states[index].desc, name, CPUIDLE_NAME_LEN);
+ powernv_states[index].flags = flags;
+ powernv_states[index].target_residency = target_residency;
+ powernv_states[index].exit_latency = exit_latency;
+ powernv_states[index].enter = idle_fn;
+ stop_psscr_table[index] = psscr_val;
+}
+
static int powernv_add_idle_states(void)
{
struct device_node *power_mgt;
@@ -236,6 +258,7 @@ static int powernv_add_idle_states(void)
"ibm,cpu-idle-state-residency-ns", residency_ns, dt_idle_states);
for (i = 0; i < dt_idle_states; i++) {
+ unsigned int exit_latency, target_residency;
/*
* If an idle state has exit latency beyond
* POWERNV_THRESHOLD_LATENCY_NS then don't use it
@@ -243,28 +266,33 @@ static int powernv_add_idle_states(void)
*/
if (latency_ns[i] > POWERNV_THRESHOLD_LATENCY_NS)
continue;
+ /*
+ * Firmware passes residency and latency values in ns.
+ * cpuidle expects it in us.
+ */
+ exit_latency = latency_ns[i] / 1000;
+ if (!rc)
+ target_residency = residency_ns[i] / 1000;
+ else
+ target_residency = 0;
/*
- * Cpuidle accepts exit_latency and target_residency in us.
- * Use default target_residency values if f/w does not expose it.
+ * For nap and fastsleep, use default target_residency
+ * values if f/w does not expose it.
*/
if (flags[i] & OPAL_PM_NAP_ENABLED) {
+ if (!rc)
+ target_residency = 100;
/* Add NAP state */
- strcpy(powernv_states[nr_idle_states].name, "Nap");
- strcpy(powernv_states[nr_idle_states].desc, "Nap");
- powernv_states[nr_idle_states].flags = 0;
- powernv_states[nr_idle_states].target_residency = 100;
- powernv_states[nr_idle_states].enter = nap_loop;
+ add_powernv_state(nr_idle_states, "Nap",
+ CPUIDLE_FLAG_NONE, nap_loop,
+ target_residency, exit_latency, 0);
} else if ((flags[i] & OPAL_PM_STOP_INST_FAST) &&
!(flags[i] & OPAL_PM_TIMEBASE_STOP)) {
- strncpy(powernv_states[nr_idle_states].name,
- names[i], CPUIDLE_NAME_LEN);
- strncpy(powernv_states[nr_idle_states].desc,
- names[i], CPUIDLE_NAME_LEN);
- powernv_states[nr_idle_states].flags = 0;
-
- powernv_states[nr_idle_states].enter = stop_loop;
- stop_psscr_table[nr_idle_states] = psscr_val[i];
+ add_powernv_state(nr_idle_states, names[i],
+ CPUIDLE_FLAG_NONE, stop_loop,
+ target_residency, exit_latency,
+ psscr_val[i]);
}
/*
@@ -274,32 +302,21 @@ static int powernv_add_idle_states(void)
#ifdef CONFIG_TICK_ONESHOT
if (flags[i] & OPAL_PM_SLEEP_ENABLED ||
flags[i] & OPAL_PM_SLEEP_ENABLED_ER1) {
+ if (!rc)
+ target_residency = 300000;
/* Add FASTSLEEP state */
- strcpy(powernv_states[nr_idle_states].name, "FastSleep");
- strcpy(powernv_states[nr_idle_states].desc, "FastSleep");
- powernv_states[nr_idle_states].flags = CPUIDLE_FLAG_TIMER_STOP;
- powernv_states[nr_idle_states].target_residency = 300000;
- powernv_states[nr_idle_states].enter = fastsleep_loop;
+ add_powernv_state(nr_idle_states, "FastSleep",
+ CPUIDLE_FLAG_TIMER_STOP,
+ fastsleep_loop,
+ target_residency, exit_latency, 0);
} else if ((flags[i] & OPAL_PM_STOP_INST_DEEP) &&
(flags[i] & OPAL_PM_TIMEBASE_STOP)) {
- strncpy(powernv_states[nr_idle_states].name,
- names[i], CPUIDLE_NAME_LEN);
- strncpy(powernv_states[nr_idle_states].desc,
- names[i], CPUIDLE_NAME_LEN);
-
- powernv_states[nr_idle_states].flags = CPUIDLE_FLAG_TIMER_STOP;
- powernv_states[nr_idle_states].enter = stop_loop;
- stop_psscr_table[nr_idle_states] = psscr_val[i];
+ add_powernv_state(nr_idle_states, names[i],
+ CPUIDLE_FLAG_TIMER_STOP, stop_loop,
+ target_residency, exit_latency,
+ psscr_val[i]);
}
#endif
- powernv_states[nr_idle_states].exit_latency =
- ((unsigned int)latency_ns[i]) / 1000;
-
- if (!rc) {
- powernv_states[nr_idle_states].target_residency =
- ((unsigned int)residency_ns[i]) / 1000;
- }
-
nr_idle_states++;
}
out:
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index bb31373..c4e10f8 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -62,6 +62,7 @@ struct cpuidle_state {
};
/* Idle State Flags */
+#define CPUIDLE_FLAG_NONE (0x00)
#define CPUIDLE_FLAG_COUPLED (0x02) /* state applies to multiple cpus */
#define CPUIDLE_FLAG_TIMER_STOP (0x04) /* timer is stopped on this state */
--
1.9.4
^ permalink raw reply related
* [PATCH v5 4/5] powernv: Pass PSSCR value and mask to power9_idle_stop
From: Gautham R. Shenoy @ 2017-01-10 9:07 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Rafael J. Wysocki, Daniel Lezcano, Michael Neuling,
Vaidyanathan Srinivasan, Shreyas B. Prabhu, Shilpasri G Bhat,
Stewart Smith, Balbir Singh, Oliver O'Halloran
Cc: linuxppc-dev, linux-kernel, linux-pm, devicetree, Rob Herring,
mark.rutland, Gautham R. Shenoy
In-Reply-To: <1484039224-5630-1-git-send-email-ego@linux.vnet.ibm.com>
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
The arch300_idle_stop method currently takes only the requested stop
level as a parameter and picks up the rest of the PSSCR bits from a
hand-coded macro. This is not a very flexible design, especially when
the firmware has the capability to communicate the psscr value and the
mask associated with a particular stop state via device tree.
This patch modifies the power9_idle_stop API to take as parameters the
PSSCR value and the PSSCR mask corresponding to the stop state that
needs to be set. These PSSCR value and mask are respectively obtained
by parsing the "ibm,cpu-idle-state-psscr" and
"ibm,cpu-idle-state-psscr-mask" fields from the device tree.
In addition to this, the patch adds support for handling stop states
for which ESL and EC bits in the PSSCR are zero. As per the
architecture, a wakeup from these stop states resumes execution from
the subsequent instruction as opposed to waking up at the System
Vector.
The older firmware sets only the Requested Level (RL) field in the
psscr and psscr-mask exposed in the device tree. For older firmware
where psscr-mask=0xf, this patch will set the default sane values that
the set for for remaining PSSCR fields (i.e PSLL, MTL, ESL, EC, and
TR). For the new firmware, the patch will validate that the invariants
required by the ISA for the psscr values are maintained by the
firmware.
This skiboot patch that exports fully populated PSSCR values and the
mask for all the stop states can be found here:
https://lists.ozlabs.org/pipermail/skiboot/2016-September/004869.html
[Optimize the number of instructions before entering STOP with
ESL=EC=0, validate the PSSCR values provided by the firimware
maintains the invariants required as per the ISA suggested by Balbir
Singh]
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
---
[v4] -> [v5]: a) Validate the psscr values provided by firmware.
b) Optimize the number of instructions before entering
stop with ESL=EC=0.
arch/powerpc/include/asm/cpuidle.h | 44 ++++++++++
arch/powerpc/include/asm/processor.h | 3 +-
arch/powerpc/kernel/idle_book3s.S | 30 ++++---
arch/powerpc/platforms/powernv/idle.c | 138 ++++++++++++++++++++++++++++---
arch/powerpc/platforms/powernv/powernv.h | 3 +-
arch/powerpc/platforms/powernv/smp.c | 14 ++--
drivers/cpuidle/cpuidle-powernv.c | 52 +++++++++---
7 files changed, 241 insertions(+), 43 deletions(-)
diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/asm/cpuidle.h
index 0a3255b..ced47ee 100644
--- a/arch/powerpc/include/asm/cpuidle.h
+++ b/arch/powerpc/include/asm/cpuidle.h
@@ -10,11 +10,55 @@
#define PNV_CORE_IDLE_LOCK_BIT 0x100
#define PNV_CORE_IDLE_THREAD_BITS 0x0FF
+/*
+ * ============================ NOTE =================================
+ * The older firmware populates only the RL field in the psscr_val and
+ * sets the psscr_mask to 0xf. On such a firmware, the kernel sets the
+ * remaining PSSCR fields to default values as follows:
+ *
+ * - ESL and EC bits are to 1. So wakeup from any stop state will be
+ * at vector 0x100.
+ *
+ * - MTL and PSLL are set to the maximum allowed value as per the ISA,
+ * i.e. 15.
+ *
+ * - The Transition Rate, TR is set to the Maximum value 3.
+ */
+#define PSSCR_HV_DEFAULT_VAL (PSSCR_ESL | PSSCR_EC | \
+ PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
+ PSSCR_MTL_MASK)
+
+#define PSSCR_HV_DEFAULT_MASK (PSSCR_ESL | PSSCR_EC | \
+ PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
+ PSSCR_MTL_MASK | PSSCR_RL_MASK)
+#define PSSCR_EC_SHIFT 20
+#define PSSCR_ESL_SHIFT 21
+#define GET_PSSCR_EC(x) (((x) & PSSCR_EC) >> PSSCR_EC_SHIFT)
+#define GET_PSSCR_ESL(x) (((x) & PSSCR_ESL) >> PSSCR_ESL_SHIFT)
+#define GET_PSSCR_RL(x) ((x) & PSSCR_RL_MASK)
+
+#define ERR_EC_ESL_MISMATCH -1
+#define ERR_DEEP_STATE_ESL_MISMATCH -2
+
#ifndef __ASSEMBLY__
extern u32 pnv_fastsleep_workaround_at_entry[];
extern u32 pnv_fastsleep_workaround_at_exit[];
extern u64 pnv_first_deep_stop_state;
+
+int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags);
+static inline void report_invalid_psscr_val(u64 psscr_val, int err)
+{
+ switch (err) {
+ case ERR_EC_ESL_MISMATCH:
+ pr_warn("Invalid psscr %llx : ESL,EC bits unequal",
+ psscr_val);
+ break;
+ case ERR_DEEP_STATE_ESL_MISMATCH:
+ pr_warn("Invalid psscr %llx : ESL cleared for deep stop-state",
+ psscr_val);
+ }
+}
#endif
#endif
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 4b47308..da68890 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -458,7 +458,8 @@ static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
extern unsigned long power7_nap(int check_irq);
extern unsigned long power7_sleep(void);
extern unsigned long power7_winkle(void);
-extern unsigned long arch300_idle_stop(unsigned long stop_level);
+extern unsigned long arch300_idle_stop(unsigned long stop_psscr_val,
+ unsigned long stop_psscr_mask);
extern void flush_instruction_cache(void);
extern void hard_reset_now(void);
diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S
index 7f6657f..61965ab 100644
--- a/arch/powerpc/kernel/idle_book3s.S
+++ b/arch/powerpc/kernel/idle_book3s.S
@@ -40,9 +40,7 @@
#define _WORC GPR11
#define _PTCR GPR12
-#define PSSCR_HV_TEMPLATE PSSCR_ESL | PSSCR_EC | \
- PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
- PSSCR_MTL_MASK
+#define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16
.text
@@ -265,7 +263,7 @@ enter_winkle:
IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
/*
- * r3 - requested stop state
+ * r3 - PSSCR value corresponding to the requested stop state.
*/
power_enter_stop:
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
@@ -275,9 +273,18 @@ power_enter_stop:
stb r4,HSTATE_HWTHREAD_STATE(r13)
#endif
/*
+ * Check if we are executing the lite variant with ESL=EC=0
+ */
+ andis. r4, r3, PSSCR_EC_ESL_MASK_SHIFTED
+ clrldi r3, r3, 60 /* r3 = Bits 60:63 = Requested Level (RL) */
+ bne 1f
+ IDLE_STATE_ENTER_SEQ(PPC_STOP)
+ li r3,0 /* Since we didn't lose state, return 0 */
+ b pnv_wakeup_noloss
+/*
* Check if the requested state is a deep idle state.
*/
- LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
+1: LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
cmpd r3,r4
bge 2f
@@ -354,16 +361,17 @@ ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
20: nop;
-
/*
- * r3 - requested stop state
+ * r3 - The PSSCR value corresponding to the stop state.
+ * r4 - The PSSCR mask corrresonding to the stop state.
*/
_GLOBAL(arch300_idle_stop)
- LOAD_REG_IMMEDIATE(r4, PSSCR_HV_TEMPLATE)
- or r4,r4,r3
- mtspr SPRN_PSSCR, r4
- li r4, 1
+ mfspr r5, SPRN_PSSCR
+ andc r5, r5, r4
+ or r3, r3, r5
+ mtspr SPRN_PSSCR, r3
LOAD_REG_ADDR(r5,power_enter_stop)
+ li r4, 1
b pnv_powersave_common
/* No return */
/*
diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c
index c3a2fac..7a6ff4a 100644
--- a/arch/powerpc/platforms/powernv/idle.c
+++ b/arch/powerpc/platforms/powernv/idle.c
@@ -237,15 +237,21 @@ static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600,
show_fastsleep_workaround_applyonce,
store_fastsleep_workaround_applyonce);
+/*
+ * The default stop state that will be used by ppc_md.power_save
+ * function on platforms that support stop instruction.
+ */
+u64 pnv_default_stop_val;
+u64 pnv_default_stop_mask;
/*
* Used for ppc_md.power_save which needs a function with no parameters
*/
static void arch300_idle(void)
{
- /* Requesting stop state 0 */
- arch300_idle_stop(0);
+ arch300_idle_stop(pnv_default_stop_val, pnv_default_stop_mask);
}
+
/*
* First deep stop state. Used to figure out when to save/restore
* hypervisor context.
@@ -253,9 +259,11 @@ static void arch300_idle(void)
u64 pnv_first_deep_stop_state = MAX_STOP_STATE;
/*
- * Deepest stop idle state. Used when a cpu is offlined
+ * psscr value and mask of the deepest stop idle state.
+ * Used when a cpu is offlined.
*/
-u64 pnv_deepest_stop_state;
+u64 pnv_deepest_stop_psscr_val;
+u64 pnv_deepest_stop_psscr_mask;
/*
* Power ISA 3.0 idle initialization.
@@ -292,6 +300,44 @@ static void arch300_idle(void)
* Bits 60:63 - Requested Level
* Used to specify which power-saving level must be entered on executing
* stop instruction
+ */
+
+int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags)
+{
+ int err = 0;
+
+ /*
+ * psscr_mask == 0xf indicates an older firmware.
+ * Set remaining fields of psscr to the default values.
+ * See NOTE above definition of PSSCR_HV_DEFAULT_VAL
+ */
+ if (*psscr_mask == 0xf) {
+ *psscr_val = *psscr_val | PSSCR_HV_DEFAULT_VAL;
+ *psscr_mask = PSSCR_HV_DEFAULT_MASK;
+ return err;
+ }
+
+ /*
+ * New firmware is expected to set the psscr_val bits correctly.
+ * Validate that the following invariants are correctly maintained by
+ * the new firmware.
+ * - ESL bit value matches the EC bit value.
+ * - ESL bit is set for all the deep stop states.
+ */
+ if (GET_PSSCR_ESL(*psscr_val) != GET_PSSCR_EC(*psscr_val)) {
+ err = ERR_EC_ESL_MISMATCH;
+ } else if ((flags & OPAL_PM_LOSE_FULL_CONTEXT) &&
+ GET_PSSCR_ESL(*psscr_val) == 0) {
+ err = ERR_DEEP_STATE_ESL_MISMATCH;
+ }
+
+ return err;
+}
+
+/*
+ * pnv_arch300_idle_init: Initializes the default idle state, first
+ * deep idle state and deepest idle state on
+ * ISA 3.0 CPUs.
*
* @np: /ibm,opal/power-mgt device node
* @flags: cpu-idle-state-flags array
@@ -302,43 +348,109 @@ static int __init pnv_arch300_idle_init(struct device_node *np, u32 *flags,
int dt_idle_states)
{
u64 *psscr_val = NULL;
+ u64 *psscr_mask = NULL;
+ u32 *residency_ns = NULL;
+ u64 max_residency_ns = 0;
int rc = 0, i;
+ bool default_stop_found = false, deepest_stop_found = false;
- psscr_val = kcalloc(dt_idle_states, sizeof(*psscr_val),
- GFP_KERNEL);
- if (!psscr_val) {
+ psscr_val = kcalloc(dt_idle_states, sizeof(*psscr_val), GFP_KERNEL);
+ psscr_mask = kcalloc(dt_idle_states, sizeof(*psscr_mask), GFP_KERNEL);
+ residency_ns = kcalloc(dt_idle_states, sizeof(*residency_ns),
+ GFP_KERNEL);
+
+ if (!psscr_val || !psscr_mask || !residency_ns) {
rc = -1;
goto out;
}
+
if (of_property_read_u64_array(np,
"ibm,cpu-idle-state-psscr",
psscr_val, dt_idle_states)) {
- pr_warn("cpuidle-powernv: missing ibm,cpu-idle-states-psscr in DT\n");
+ pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr in DT\n");
+ rc = -1;
+ goto out;
+ }
+
+ if (of_property_read_u64_array(np,
+ "ibm,cpu-idle-state-psscr-mask",
+ psscr_mask, dt_idle_states)) {
+ pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr-mask in DT\n");
+ rc = -1;
+ goto out;
+ }
+
+ if (of_property_read_u32_array(np,
+ "ibm,cpu-idle-state-residency-ns",
+ residency_ns, dt_idle_states)) {
+ pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-residency-ns in DT\n");
rc = -1;
goto out;
}
/*
- * Set pnv_first_deep_stop_state and pnv_deepest_stop_state.
+ * Set pnv_first_deep_stop_state, pnv_deepest_stop_psscr_{val,mask},
+ * and the pnv_default_stop_{val,mask}.
+ *
* pnv_first_deep_stop_state should be set to the first stop
* level to cause hypervisor state loss.
- * pnv_deepest_stop_state should be set to the deepest stop
- * stop state.
+ *
+ * pnv_deepest_stop_{val,mask} should be set to values corresponding to
+ * the deepest stop state.
+ *
+ * pnv_default_stop_{val,mask} should be set to values corresponding to
+ * the shallowest (OPAL_PM_STOP_INST_FAST) loss-less stop state.
*/
pnv_first_deep_stop_state = MAX_STOP_STATE;
for (i = 0; i < dt_idle_states; i++) {
+ int err;
u64 psscr_rl = psscr_val[i] & PSSCR_RL_MASK;
if ((flags[i] & OPAL_PM_LOSE_FULL_CONTEXT) &&
(pnv_first_deep_stop_state > psscr_rl))
pnv_first_deep_stop_state = psscr_rl;
- if (pnv_deepest_stop_state < psscr_rl)
- pnv_deepest_stop_state = psscr_rl;
+ err = validate_psscr_val_mask(&psscr_val[i], &psscr_mask[i],
+ flags[i]);
+ if (err) {
+ report_invalid_psscr_val(psscr_val[i], err);
+ continue;
+ }
+
+ if (max_residency_ns < residency_ns[i]) {
+ max_residency_ns = residency_ns[i];
+ pnv_deepest_stop_psscr_val = psscr_val[i];
+ pnv_deepest_stop_psscr_mask = psscr_mask[i];
+ deepest_stop_found = true;
+ }
+
+ if (!default_stop_found &&
+ (flags[i] & OPAL_PM_STOP_INST_FAST)) {
+ pnv_default_stop_val = psscr_val[i];
+ pnv_default_stop_mask = psscr_mask[i];
+ default_stop_found = true;
+ }
+ }
+
+ if (!default_stop_found) {
+ pnv_default_stop_val = PSSCR_HV_DEFAULT_VAL;
+ pnv_default_stop_mask = PSSCR_HV_DEFAULT_MASK;
+ pr_warn("Setting default stop psscr val=%llx,mask=%llx\n",
+ pnv_default_stop_val, pnv_default_stop_mask);
+ }
+
+ if (!deepest_stop_found) {
+ pnv_deepest_stop_psscr_val = PSSCR_HV_DEFAULT_VAL;
+ pnv_deepest_stop_psscr_mask = PSSCR_HV_DEFAULT_MASK;
+ pr_warn("Setting default stop psscr val=%llx,mask=%llx\n",
+ pnv_deepest_stop_psscr_val,
+ pnv_deepest_stop_psscr_mask);
}
out:
kfree(psscr_val);
+ kfree(psscr_mask);
+ kfree(residency_ns);
return rc;
}
diff --git a/arch/powerpc/platforms/powernv/powernv.h b/arch/powerpc/platforms/powernv/powernv.h
index da7c843..6130522 100644
--- a/arch/powerpc/platforms/powernv/powernv.h
+++ b/arch/powerpc/platforms/powernv/powernv.h
@@ -18,7 +18,8 @@ static inline void pnv_pci_shutdown(void) { }
#endif
extern u32 pnv_get_supported_cpuidle_states(void);
-extern u64 pnv_deepest_stop_state;
+extern u64 pnv_deepest_stop_psscr_val;
+extern u64 pnv_deepest_stop_psscr_mask;
extern void pnv_lpc_init(void);
diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c
index c931bb2..408695f 100644
--- a/arch/powerpc/platforms/powernv/smp.c
+++ b/arch/powerpc/platforms/powernv/smp.c
@@ -182,15 +182,17 @@ static void pnv_smp_cpu_kill_self(void)
ppc64_runlatch_off();
- if (cpu_has_feature(CPU_FTR_ARCH_300))
- srr1 = arch300_idle_stop(pnv_deepest_stop_state);
- else if (idle_states & OPAL_PM_WINKLE_ENABLED)
+ if (cpu_has_feature(CPU_FTR_ARCH_300)) {
+ srr1 = arch300_idle_stop(pnv_deepest_stop_psscr_val,
+ pnv_deepest_stop_psscr_mask);
+ } else if (idle_states & OPAL_PM_WINKLE_ENABLED) {
srr1 = power7_winkle();
- else if ((idle_states & OPAL_PM_SLEEP_ENABLED) ||
- (idle_states & OPAL_PM_SLEEP_ENABLED_ER1))
+ } else if ((idle_states & OPAL_PM_SLEEP_ENABLED) ||
+ (idle_states & OPAL_PM_SLEEP_ENABLED_ER1)) {
srr1 = power7_sleep();
- else
+ } else {
srr1 = power7_nap(1);
+ }
ppc64_runlatch_on();
diff --git a/drivers/cpuidle/cpuidle-powernv.c b/drivers/cpuidle/cpuidle-powernv.c
index a21f1f0..bbadd91 100644
--- a/drivers/cpuidle/cpuidle-powernv.c
+++ b/drivers/cpuidle/cpuidle-powernv.c
@@ -19,6 +19,7 @@
#include <asm/firmware.h>
#include <asm/opal.h>
#include <asm/runlatch.h>
+#include <asm/cpuidle.h>
/*
* Expose only those Hardware idle states via the cpuidle framework
@@ -34,7 +35,12 @@ struct cpuidle_driver powernv_idle_driver = {
static int max_idle_state;
static struct cpuidle_state *cpuidle_state_table;
-static u64 stop_psscr_table[CPUIDLE_STATE_MAX];
+struct stop_psscr_table {
+ u64 val;
+ u64 mask;
+};
+
+static struct stop_psscr_table stop_psscr_table[CPUIDLE_STATE_MAX];
static u64 snooze_timeout;
static bool snooze_timeout_en;
@@ -106,7 +112,8 @@ static int stop_loop(struct cpuidle_device *dev,
int index)
{
ppc64_runlatch_off();
- arch300_idle_stop(stop_psscr_table[index]);
+ arch300_idle_stop(stop_psscr_table[index].val,
+ stop_psscr_table[index].mask);
ppc64_runlatch_on();
return index;
}
@@ -178,7 +185,7 @@ static inline void add_powernv_state(int index, const char *name,
int),
unsigned int target_residency,
unsigned int exit_latency,
- u64 psscr_val)
+ u64 psscr_val, u64 psscr_mask)
{
strlcpy(powernv_states[index].name, name, CPUIDLE_NAME_LEN);
strlcpy(powernv_states[index].desc, name, CPUIDLE_NAME_LEN);
@@ -186,7 +193,8 @@ static inline void add_powernv_state(int index, const char *name,
powernv_states[index].target_residency = target_residency;
powernv_states[index].exit_latency = exit_latency;
powernv_states[index].enter = idle_fn;
- stop_psscr_table[index] = psscr_val;
+ stop_psscr_table[index].val = psscr_val;
+ stop_psscr_table[index].mask = psscr_mask;
}
static int powernv_add_idle_states(void)
@@ -198,7 +206,9 @@ static int powernv_add_idle_states(void)
u32 residency_ns[CPUIDLE_STATE_MAX];
u32 flags[CPUIDLE_STATE_MAX];
u64 psscr_val[CPUIDLE_STATE_MAX];
+ u64 psscr_mask[CPUIDLE_STATE_MAX];
const char *names[CPUIDLE_STATE_MAX];
+ bool has_stop_states = false;
int i, rc;
/* Currently we have snooze statically defined */
@@ -245,15 +255,25 @@ static int powernv_add_idle_states(void)
/*
* If the idle states use stop instruction, probe for psscr values
- * which are necessary to specify required stop level.
+ * and psscr mask which are necessary to specify required stop level.
*/
- if (flags[0] & (OPAL_PM_STOP_INST_FAST | OPAL_PM_STOP_INST_DEEP))
+ if (flags[0] & (OPAL_PM_STOP_INST_FAST | OPAL_PM_STOP_INST_DEEP)) {
if (of_property_read_u64_array(power_mgt,
"ibm,cpu-idle-state-psscr", psscr_val, dt_idle_states)) {
- pr_warn("cpuidle-powernv: missing ibm,cpu-idle-states-psscr in DT\n");
+ pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr in DT\n");
+ goto out;
+ }
+
+ if (of_property_read_u64_array(power_mgt,
+ "ibm,cpu-idle-state-psscr-mask",
+ psscr_mask, dt_idle_states)) {
+ pr_warn("cpuidle-powernv:Missing ibm,cpu-idle-state-psscr-mask in DT\n");
goto out;
}
+ has_stop_states = true;
+ }
+
rc = of_property_read_u32_array(power_mgt,
"ibm,cpu-idle-state-residency-ns", residency_ns, dt_idle_states);
@@ -276,6 +296,16 @@ static int powernv_add_idle_states(void)
else
target_residency = 0;
+ if (has_stop_states) {
+ int err = validate_psscr_val_mask(&psscr_val[i],
+ &psscr_mask[i],
+ flags[i]);
+ if (err) {
+ report_invalid_psscr_val(psscr_val[i], err);
+ continue;
+ }
+ }
+
/*
* For nap and fastsleep, use default target_residency
* values if f/w does not expose it.
@@ -286,13 +316,13 @@ static int powernv_add_idle_states(void)
/* Add NAP state */
add_powernv_state(nr_idle_states, "Nap",
CPUIDLE_FLAG_NONE, nap_loop,
- target_residency, exit_latency, 0);
+ target_residency, exit_latency, 0, 0);
} else if ((flags[i] & OPAL_PM_STOP_INST_FAST) &&
!(flags[i] & OPAL_PM_TIMEBASE_STOP)) {
add_powernv_state(nr_idle_states, names[i],
CPUIDLE_FLAG_NONE, stop_loop,
target_residency, exit_latency,
- psscr_val[i]);
+ psscr_val[i], psscr_mask[i]);
}
/*
@@ -308,13 +338,13 @@ static int powernv_add_idle_states(void)
add_powernv_state(nr_idle_states, "FastSleep",
CPUIDLE_FLAG_TIMER_STOP,
fastsleep_loop,
- target_residency, exit_latency, 0);
+ target_residency, exit_latency, 0, 0);
} else if ((flags[i] & OPAL_PM_STOP_INST_DEEP) &&
(flags[i] & OPAL_PM_TIMEBASE_STOP)) {
add_powernv_state(nr_idle_states, names[i],
CPUIDLE_FLAG_TIMER_STOP, stop_loop,
target_residency, exit_latency,
- psscr_val[i]);
+ psscr_val[i], psscr_mask[i]);
}
#endif
nr_idle_states++;
--
1.9.4
^ permalink raw reply related
* [PATCH v5 5/5] Documentation:powerpc: Add device-tree bindings for power-mgt
From: Gautham R. Shenoy @ 2017-01-10 9:07 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Rafael J. Wysocki, Daniel Lezcano, Michael Neuling,
Vaidyanathan Srinivasan, Shreyas B. Prabhu, Shilpasri G Bhat,
Stewart Smith, Balbir Singh, Oliver O'Halloran
Cc: linuxppc-dev, linux-kernel, linux-pm, devicetree, Rob Herring,
mark.rutland, Gautham R. Shenoy
In-Reply-To: <1484039224-5630-1-git-send-email-ego@linux.vnet.ibm.com>
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
Document the device-tree bindings defining the the properties under
the @power-mgt node in the device tree that describe the idle states
for Linux running on baremetal POWER servers.
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
---
[v4]-> [v5]: Fixed a couple of typos.
.../devicetree/bindings/powerpc/opal/power-mgt.txt | 125 +++++++++++++++++++++
1 file changed, 125 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/opal/power-mgt.txt
diff --git a/Documentation/devicetree/bindings/powerpc/opal/power-mgt.txt b/Documentation/devicetree/bindings/powerpc/opal/power-mgt.txt
new file mode 100644
index 0000000..4967831
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/opal/power-mgt.txt
@@ -0,0 +1,125 @@
+IBM Power-Management Bindings
+=============================
+
+Linux running on baremetal POWER machines has access to the processor
+idle states. The description of these idle states is exposed via the
+node @power-mgt in the device-tree by the firmware.
+
+Definitions:
+----------------
+Typically each idle state has the following associated properties:
+
+- name: The name of the idle state as defined by the firmware.
+
+- flags: indicating some aspects of this idle states such as the
+ extent of state-loss, whether timebase is stopped on this
+ idle states and so on. The flag bits are as follows:
+
+- exit-latency: The latency involved in transitioning the state of the
+ CPU from idle to running.
+
+- target-residency: The minimum time that the CPU needs to reside in
+ this idle state in order to accrue power-savings
+ benefit.
+
+Properties
+----------------
+The following properties provide details about the idle states. These
+properties are optional unless mentioned otherwise below.
+
+- ibm,cpu-idle-state-names:
+ Array of strings containing the names of the idle states.
+
+- ibm,cpu-idle-state-flags:
+ Array of unsigned 32-bit values containing the values of the
+ flags associated with the the aforementioned idle-states. This
+ property is required on POWER9 whenever
+ ibm,cpu-idle-state-names is defined and the length of this
+ property array should be the same as
+ ibm,-cpu-idle-state-names.The flag bits are as follows:
+ 0x00000001 /* Decrementer would stop */
+ 0x00000002 /* Needs timebase restore */
+ 0x00001000 /* Restore GPRs like nap */
+ 0x00002000 /* Restore hypervisor resource from PACA pointer */
+ 0x00004000 /* Program PORE to restore PACA pointer */
+ 0x00010000 /* This is a nap state */
+ 0x00020000 /* This is a fast-sleep state */
+ 0x00040000 /* This is a winkle state */
+ 0x00080000 /* This is a fast-sleep state which requires a */
+ /* software workaround for restoring the timebase*/
+ 0x00800000 /* This state uses SPR PMICR instruction */
+ 0x00100000 /* This is a fast stop state */
+ 0x00200000 /* This is a deep-stop state */
+
+- ibm,cpu-idle-state-latencies-ns:
+ Array of unsigned 32-bit values containing the values of the
+ exit-latencies (in ns) for the idle states in
+ ibm,cpu-idle-state-names. This property is required whenever
+ ibm,cpu-idle-state-names is defined and the length of this
+ property array should be the same as
+ ibm,-cpu-idle-state-names.
+
+- ibm,cpu-idle-state-residency-ns:
+ Array of unsigned 32-bit values containing the values of the
+ target-residency (in ns) for the idle states in
+ ibm,cpu-idle-state-names. On POWER8 this is an optional
+ property. If the property is absent, the target residency for
+ the "Nap", "FastSleep" are defined to 10000 and 300000000
+ respectively. On POWER9 this property must be defined if
+ ibm,cpu-idle-state-names is defined and the length should be
+ same as that of ibm,cpu-idle-state-names.
+
+- ibm,cpu-idle-state-psscr:
+ Array of unsigned 64-bit values containing the values for the
+ PSSCR for each of the idle states in ibm,cpu-idle-state-names.
+ This property is required on POWER9 whenever
+ ibm,cpu-idle-state-names is defined and the length of this
+ property array should be the same as
+ ibm,cpu-idle-state-names.
+
+- ibm,cpu-idle-state-psscr-mask:
+ Array of unsigned 64-bit values containing the masks
+ indicating which psscr fields are set in the corresponding
+ entries of ibm,cpu-idle-state-psscr. This property is
+ required on POWER9 whenever ibm,cpu-idle-state-names is
+ defined and the length of this property array should be the
+ same as ibm,cpu-idle-state-names.
+
+ Whenever the firmware sets an entry in
+ ibm,cpu-idle-state-psscr-mask value to 0xf, it implies that
+ only the Requested Level (RL) field of the corresponding entry
+ in ibm,cpu-idle-state-psscr should be considered by the
+ kernel. For such idle states, the kernel would set the
+ remaining fields of the psscr to the following sane-default
+ values.
+
+ - ESL and EC bits are to 1. So wakeup from any stop
+ state will be at vector 0x100.
+
+ - MTL and PSLL are set to the maximum allowed value as
+ per the ISA, i.e. 15.
+
+ - The Transition Rate, TR is set to the Maximum value
+ 3.
+
+ For all the other values of the entry in
+ ibm,cpu-idle-state-psscr-mask, the Kernel expects all the
+ psscr fields of the corresponding entry in
+ ibm,cpu-idle-state-psscr to be correctly set by the firmware.
+
+- ibm,cpu-idle-state-pmicr:
+ Array of unsigned 64-bit values containing the pmicr values
+ for the idle states in ibm,cpu-idle-state-names. This 64-bit
+ register value is to be set in pmicr for the corresponding
+ state if the flag indicates that pmicr SPR should be set. This
+ is an optional property on POWER8 and is absent on
+ POWER9. When present on POWER8, the length of this property
+ array should be the same as ibm,cpu-idle-state-names.
+
+- ibm,cpu-idle-state-pmicr:-mask
+ Array of unsigned 64-bit values containing the mask indicating
+ which of the fields of the PMICR are set in the corresponding
+ entries in ibm,cpu-idle-state-pmicr. This is an optional
+ property on POWER8 and is absent on POWER9. When present on
+ POWER8, the length of this property array should be the same
+ as ibm,cpu-idle-state-names.
--
1.9.4
^ permalink raw reply related
* Re: [PATCH v5 2/2] ARM: sama5_defconfig: add support for the Axentia TSE-850 board
From: Nicolas Ferre @ 2017-01-10 9:10 UTC (permalink / raw)
To: Peter Rosin
Cc: linux-kernel, Rob Herring, Mark Rutland, Russell King,
Alexandre Belloni, Jean-Christophe Plagniol-Villard,
linux-arm-kernel, devicetree
In-Reply-To: <1484035732-31635-3-git-send-email-peda@axentia.se>
Le 10/01/2017 à 09:08, Peter Rosin a écrit :
> Signed-off-by: Peter Rosin <peda@axentia.se>
I know that most of the entries in this configuration file are direct
additions to the kernel but what about moving some of your additions to
modules?
Regards,
> ---
> arch/arm/configs/sama5_defconfig | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
> index aca8625b6fc9..bf5b3a73e38c 100644
> --- a/arch/arm/configs/sama5_defconfig
> +++ b/arch/arm/configs/sama5_defconfig
> @@ -131,7 +131,7 @@ CONFIG_GPIO_SYSFS=y
> CONFIG_POWER_SUPPLY=y
> CONFIG_BATTERY_ACT8945A=y
> CONFIG_POWER_RESET=y
> -# CONFIG_HWMON is not set
> +CONFIG_SENSORS_JC42=y
> CONFIG_WATCHDOG=y
> CONFIG_AT91SAM9X_WATCHDOG=y
> CONFIG_SAMA5D4_WATCHDOG=y
> @@ -142,6 +142,7 @@ CONFIG_REGULATOR=y
> CONFIG_REGULATOR_FIXED_VOLTAGE=y
> CONFIG_REGULATOR_ACT8865=y
> CONFIG_REGULATOR_ACT8945A=y
> +CONFIG_REGULATOR_PWM=y
> CONFIG_MEDIA_SUPPORT=y
> CONFIG_MEDIA_CAMERA_SUPPORT=y
> CONFIG_V4L_PLATFORM_DRIVERS=y
> @@ -164,6 +165,7 @@ CONFIG_SND_ATMEL_SOC=y
> CONFIG_SND_ATMEL_SOC_WM8904=y
> # CONFIG_HID_GENERIC is not set
> CONFIG_SND_ATMEL_SOC_PDMIC=y
> +CONFIG_SND_ATMEL_SOC_TSE850_PCM5142=y
> CONFIG_USB=y
> CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
> CONFIG_USB_EHCI_HCD=y
> @@ -199,6 +201,9 @@ CONFIG_AT_XDMAC=y
> CONFIG_IIO=y
> CONFIG_AT91_ADC=y
> CONFIG_AT91_SAMA5D2_ADC=y
> +CONFIG_ENVELOPE_DETECTOR=y
> +CONFIG_DPOT_DAC=y
> +CONFIG_MCP4531=y
> CONFIG_PWM=y
> CONFIG_PWM_ATMEL=y
> CONFIG_PWM_ATMEL_HLCDC_PWM=y
>
--
Nicolas Ferre
^ permalink raw reply
* [PATCH v2 0/2] media: rc: add support for IR receiver on MT7623 SoC
From: sean.wang @ 2017-01-10 9:13 UTC (permalink / raw)
To: mchehab, hdegoede, hkallweit1, robh+dt, mark.rutland,
matthias.bgg
Cc: devicetree, ivo.g.dimitrov.75, keyhaede, sean, Sean Wang,
linux-kernel, andi.shyti, hverkuil, linux-mediatek,
linux-arm-kernel, linux-media
From: Sean Wang <sean.wang@mediatek.com>
This patchset introduces consumer IR (CIR) support on MT7623 SoC
that also works on other similar SoCs and implements raw mode for
more compatibility with different protocols. The driver simply
reports the duration of pulses and spaces to rc-core logic to
decode.
Changes since v1:
- change compatible string from "mediatek,mt7623-ir" into
"mediatek,mt7623-cir"
- use KBUILD_MODNAME to provide consistent device name used in driver.
- remove unused fields in struct mtk_ir.
- use synchronize_irq to give protection between IRQ handler and
remove handler.
- use devm_rc_allocate_device based on Andi Shyti's work.
- simplify error handling patch with devm_rc_register_device and devm_rc_allocate_device.
- remove unused spinlock.
- add comments about hardware limitation and related workarounds.
- enhance the caculation of sampling period for easiler assigned specific
value.
- refine git description.
- fix IR message handling between IR hardware and rc-core.
Sean Wang (2):
Documentation: devicetree: Add document bindings for mtk-cir
media: rc: add driver for IR remote receiver on MT7623 SoC
.../devicetree/bindings/media/mtk-cir.txt | 24 ++
drivers/media/rc/Kconfig | 11 +
drivers/media/rc/Makefile | 1 +
drivers/media/rc/mtk-cir.c | 326 +++++++++++++++++++++
4 files changed, 362 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mtk-cir.txt
create mode 100644 drivers/media/rc/mtk-cir.c
--
2.7.4
^ permalink raw reply
* [PATCH v2 1/2] Documentation: devicetree: Add document bindings for mtk-cir
From: sean.wang @ 2017-01-10 9:13 UTC (permalink / raw)
To: mchehab, hdegoede, hkallweit1, robh+dt, mark.rutland,
matthias.bgg
Cc: devicetree, ivo.g.dimitrov.75, keyhaede, sean, Sean Wang,
linux-kernel, andi.shyti, hverkuil, linux-mediatek,
linux-arm-kernel, linux-media
In-Reply-To: <1484039631-25120-1-git-send-email-sean.wang@mediatek.com>
From: Sean Wang <sean.wang@mediatek.com>
This patch adds documentation for devicetree bindings for
Mediatek consumer IR controller.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
.../devicetree/bindings/media/mtk-cir.txt | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mtk-cir.txt
diff --git a/Documentation/devicetree/bindings/media/mtk-cir.txt b/Documentation/devicetree/bindings/media/mtk-cir.txt
new file mode 100644
index 0000000..3850cbd
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mtk-cir.txt
@@ -0,0 +1,24 @@
+Device-Tree bindings for Mediatek consumer IR controller found in
+Mediatek SoC family
+
+Required properties:
+- compatible : "mediatek,mt7623-cir"
+- clocks : list of clock specifiers, corresponding to
+ entries in clock-names property;
+- clock-names : should contain "clk" entries;
+- interrupts : should contain IR IRQ number;
+- reg : should contain IO map address for IR.
+
+Optional properties:
+- linux,rc-map-name : Remote control map name.
+
+Example:
+
+cir: cir@10013000 {
+ compatible = "mediatek,mt7623-cir";
+ reg = <0 0x10013000 0 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_IRRX>;
+ clock-names = "clk";
+ linux,rc-map-name = "rc-rc6-mce";
+};
--
2.7.4
^ permalink raw reply related
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