* Re: [PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc
From: Kishon Vijay Abraham I @ 2017-01-16 5:19 UTC (permalink / raw)
To: Joao Pinto, Bjorn Helgaas, Jingoo Han, Arnd Bergmann
Cc: devicetree, linux-samsung-soc, linux-doc, linux-pci, nsekhar,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-omap,
linuxppc-dev, linux-arm-kernel
In-Reply-To: <c3c55af3-29d1-dc59-3ae4-9a4132c99092@synopsys.com>
Hi,
On Friday 13 January 2017 10:43 PM, Joao Pinto wrote:
> Hi,
>
> Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>> *num-lanes* dt property is parsed in dw_pcie_host_init. However
>> *num-lanes* property is applicable to both root complex mode and
>> endpoint mode. As a first step, move the parsing of this property
>> outside dw_pcie_host_init. This is in preparation for splitting
>> pcie-designware.c to pcie-designware.c and pcie-designware-host.c
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> drivers/pci/dwc/pcie-designware.c | 18 +++++++++++-------
>> drivers/pci/dwc/pcie-designware.h | 1 -
>> 2 files changed, 11 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
>> index 00a0fdc..89cdb6b 100644
>> --- a/drivers/pci/dwc/pcie-designware.c
>> +++ b/drivers/pci/dwc/pcie-designware.c
>> @@ -551,10 +551,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
>> }
>> }
>>
>> - ret = of_property_read_u32(np, "num-lanes", &pci->lanes);
>> - if (ret)
>> - pci->lanes = 0;
>> -
>> ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
>> if (ret)
>> pci->num_viewport = 2;
>> @@ -751,18 +747,26 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
>>
>> void dw_pcie_setup_rc(struct pcie_port *pp)
>> {
>> + int ret;
>> + u32 lanes;
>> u32 val;
>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct device *dev = pci->dev;
>> + struct device_node *np = dev->of_node;
>>
>> /* get iATU unroll support */
>> pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
>> dev_dbg(pci->dev, "iATU unroll: %s\n",
>> pci->iatu_unroll_enabled ? "enabled" : "disabled");
>>
>> + ret = of_property_read_u32(np, "num-lanes", &lanes);
>> + if (ret)
>> + lanes = 0;
>
> You moved from host_init to root complex setup function, which in my opinion did
> not improve (in this scope).
>
> I suggest that instead of making so much intermediary patches, which is nice to
> understand your development sequence, but hard to review. Wouldn't be better to
> condense some of the patches? We would have a cloear vision of the final product :)
I thought the other way. If squashing patches is easier to review, I'll do it.
Btw, thanks for reviewing.
Cheers
Kishon
^ permalink raw reply
* Re: [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files
From: Kishon Vijay Abraham I @ 2017-01-16 5:21 UTC (permalink / raw)
To: Joao Pinto, Bjorn Helgaas, Jingoo Han, Arnd Bergmann
Cc: linux-pci, linux-doc, linux-kernel, devicetree, linux-omap,
linux-arm-kernel, linux-samsung-soc, linuxppc-dev,
linux-arm-kernel, linux-arm-msm, nsekhar
In-Reply-To: <4a89fb45-af84-d660-5ef0-12227b141cda@synopsys.com>
Hi Joao,
On Friday 13 January 2017 10:19 PM, Joao Pinto wrote:
> Às 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>> Split pcie-designware.c into pcie-designware-host.c that contains
>> the host specific parts of the driver and pcie-designware.c that
>> contains the parts used by both host driver and endpoint driver.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> drivers/pci/dwc/Makefile | 2 +-
>> drivers/pci/dwc/pcie-designware-host.c | 619 ++++++++++++++++++++++++++++++++
>> drivers/pci/dwc/pcie-designware.c | 613 +------------------------------
>> drivers/pci/dwc/pcie-designware.h | 8 +
>> 4 files changed, 634 insertions(+), 608 deletions(-)
>> create mode 100644 drivers/pci/dwc/pcie-designware-host.c
>>
>> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
>> index 7d27c14..3b57e55 100644
>> --- a/drivers/pci/dwc/Makefile
>> +++ b/drivers/pci/dwc/Makefile
>> @@ -1,4 +1,4 @@
>
> (snip...)
>
>> -static void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
>> - int type, u64 cpu_addr, u64 pci_addr,
>> - u32 size)
>> +void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
>> + u64 cpu_addr, u64 pci_addr, u32 size)
>> {
>> u32 retries, val;
>>
>> @@ -186,220 +151,6 @@ static void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
>> dev_err(pci->dev, "iATU is not being enabled\n");
>> }
>
> Kishon, iATU only makes sense in The Root Complex (host), so it should be inside
> the pcie-designware-host.
That is not true. Outbound ATU should be programmed to access host side buffers
and inbound ATU should be programmed for the host to access EP mem space.
Thanks
Kishon
^ permalink raw reply
* Re: [PATCH 12/37] PCI: dwc: Create a new config symbol to enable pci dwc host
From: Kishon Vijay Abraham I @ 2017-01-16 5:22 UTC (permalink / raw)
To: Joao Pinto, Bjorn Helgaas, Jingoo Han, Arnd Bergmann
Cc: linux-pci, linux-doc, linux-kernel, devicetree, linux-omap,
linux-arm-kernel, linux-samsung-soc, linuxppc-dev,
linux-arm-kernel, linux-arm-msm, nsekhar
In-Reply-To: <3d34f9c4-7ec4-ac2b-ea7f-18d239dfa554@synopsys.com>
Hi Joao,
On Friday 13 January 2017 11:20 PM, Joao Pinto wrote:
> Hi Kishon,
>
> Às 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>> Now that pci designware host has a separate file, create a new
>> config symbol to select the host only driver. This is in preparation
>> to enable endpoint support to designware driver.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> drivers/pci/dwc/Kconfig | 26 +++++++++++++++-----------
>> drivers/pci/dwc/Makefile | 3 ++-
>> drivers/pci/dwc/pcie-designware.h | 29 +++++++++++++++++++++++++----
>> 3 files changed, 42 insertions(+), 16 deletions(-)
>>
>
> You are already working in a base where dwc/ already exists. I know you made a
> rename / re-structure patch for pci, but I think it was not yet accepted, right?
> I don't see it in any of Bjorn' dev branches.
He said he'll merge that a little later.
Thanks
Kishon
>
> Thanks.
>
>> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
>> index 8b08519..d0bdfb5 100644
>> --- a/drivers/pci/dwc/Kconfig
>> +++ b/drivers/pci/dwc/Kconfig
>> @@ -3,13 +3,17 @@ menu "DesignWare PCI Core Support"
>>
>> config PCIE_DW
>> bool
>> +
>> +config PCIE_DW_HOST
>> + bool
>> depends on PCI_MSI_IRQ_DOMAIN
>> + select PCIE_DW
>>
>> config PCI_DRA7XX
>> bool "TI DRA7xx PCIe controller"
>> depends on OF && HAS_IOMEM && TI_PIPE3
>> depends on PCI_MSI_IRQ_DOMAIN
>> - select PCIE_DW
>> + select PCIE_DW_HOST
>> help
>> Enables support for the PCIe controller in the DRA7xx SoC. There
>> are two instances of PCIe controller in DRA7xx. This controller can
>> @@ -18,7 +22,7 @@ config PCI_DRA7XX
>> config PCIE_DW_PLAT
>> bool "Platform bus based DesignWare PCIe Controller"
>> depends on PCI_MSI_IRQ_DOMAIN
>> - select PCIE_DW
>> + select PCIE_DW_HOST
>> ---help---
>> This selects the DesignWare PCIe controller support. Select this if
>> you have a PCIe controller on Platform bus.
>> @@ -32,21 +36,21 @@ config PCI_EXYNOS
>> depends on SOC_EXYNOS5440 || COMPILE_TEST
>> depends on PCI_MSI_IRQ_DOMAIN
>> select PCIEPORTBUS
>> - select PCIE_DW
>> + select PCIE_DW_HOST
>>
>> config PCI_IMX6
>> bool "Freescale i.MX6 PCIe controller"
>> depends on SOC_IMX6Q || COMPILE_TEST
>> depends on PCI_MSI_IRQ_DOMAIN
>> select PCIEPORTBUS
>> - select PCIE_DW
>> + select PCIE_DW_HOST
>>
>> config PCIE_SPEAR13XX
>> bool "STMicroelectronics SPEAr PCIe controller"
>> depends on ARCH_SPEAR13XX || COMPILE_TEST
>> depends on PCI_MSI_IRQ_DOMAIN
>> select PCIEPORTBUS
>> - select PCIE_DW
>> + select PCIE_DW_HOST
>> help
>> Say Y here if you want PCIe support on SPEAr13XX SoCs.
>>
>> @@ -55,7 +59,7 @@ config PCI_KEYSTONE
>> depends on ARCH_KEYSTONE || COMPILE_TEST
>> depends on PCI_MSI_IRQ_DOMAIN
>> select PCIEPORTBUS
>> - select PCIE_DW
>> + select PCIE_DW_HOST
>> help
>> Say Y here if you want to enable PCI controller support on Keystone
>> SoCs. The PCI controller on Keystone is based on Designware hardware
>> @@ -67,7 +71,7 @@ config PCI_LAYERSCAPE
>> depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
>> depends on PCI_MSI_IRQ_DOMAIN
>> select MFD_SYSCON
>> - select PCIE_DW
>> + select PCIE_DW_HOST
>> help
>> Say Y here if you want PCIe controller support on Layerscape SoCs.
>>
>> @@ -76,7 +80,7 @@ config PCI_HISI
>> bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
>> depends on PCI_MSI_IRQ_DOMAIN
>> select PCIEPORTBUS
>> - select PCIE_DW
>> + select PCIE_DW_HOST
>> help
>> Say Y here if you want PCIe controller support on HiSilicon
>> Hip05 and Hip06 SoCs
>> @@ -86,7 +90,7 @@ config PCIE_QCOM
>> depends on (ARCH_QCOM || COMPILE_TEST) && OF
>> depends on PCI_MSI_IRQ_DOMAIN
>> select PCIEPORTBUS
>> - select PCIE_DW
>> + select PCIE_DW_HOST
>> help
>> Say Y here to enable PCIe controller support on Qualcomm SoCs. The
>> PCIe controller uses the Designware core plus Qualcomm-specific
>> @@ -97,7 +101,7 @@ config PCIE_ARMADA_8K
>> depends on ARCH_MVEBU || COMPILE_TEST
>> depends on PCI_MSI_IRQ_DOMAIN
>> select PCIEPORTBUS
>> - select PCIE_DW
>> + select PCIE_DW_HOST
>> help
>> Say Y here if you want to enable PCIe controller support on
>> Armada-8K SoCs. The PCIe controller on Armada-8K is based on
>> @@ -109,7 +113,7 @@ config PCIE_ARTPEC6
>> depends on MACH_ARTPEC6 || COMPILE_TEST
>> depends on PCI_MSI_IRQ_DOMAIN
>> select PCIEPORTBUS
>> - select PCIE_DW
>> + select PCIE_DW_HOST
>> help
>> Say Y here to enable PCIe controller support on Axis ARTPEC-6
>> SoCs. This PCIe controller uses the DesignWare core.
>> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
>> index 3b57e55..a2df13c 100644
>> --- a/drivers/pci/dwc/Makefile
>> +++ b/drivers/pci/dwc/Makefile
>> @@ -1,4 +1,5 @@
>> -obj-$(CONFIG_PCIE_DW) += pcie-designware.o pcie-designware-host.o
>> +obj-$(CONFIG_PCIE_DW) += pcie-designware.o
>> +obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
>> obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
>> obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
>> obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
>> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
>> index 808d17b..8f3dcb2 100644
>> --- a/drivers/pci/dwc/pcie-designware.h
>> +++ b/drivers/pci/dwc/pcie-designware.h
>> @@ -162,10 +162,6 @@ struct dw_pcie {
>>
>> int dw_pcie_read(void __iomem *addr, int size, u32 *val);
>> int dw_pcie_write(void __iomem *addr, int size, u32 val);
>> -irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
>> -void dw_pcie_msi_init(struct pcie_port *pp);
>> -void dw_pcie_setup_rc(struct pcie_port *pp);
>> -int dw_pcie_host_init(struct pcie_port *pp);
>>
>> u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg);
>> void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val);
>> @@ -175,4 +171,29 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
>> int type, u64 cpu_addr, u64 pci_addr,
>> u32 size);
>> void dw_pcie_setup(struct dw_pcie *pci);
>> +
>> +#ifdef CONFIG_PCIE_DW_HOST
>> +irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
>> +void dw_pcie_msi_init(struct pcie_port *pp);
>> +void dw_pcie_setup_rc(struct pcie_port *pp);
>> +int dw_pcie_host_init(struct pcie_port *pp);
>> +#else
>> +static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
>> +{
>> + return IRQ_NONE;
>> +}
>> +
>> +static inline void dw_pcie_msi_init(struct pcie_port *pp)
>> +{
>> +}
>> +
>> +static inline void dw_pcie_setup_rc(struct pcie_port *pp)
>> +{
>> +}
>> +
>> +static inline int dw_pcie_host_init(struct pcie_port *pp)
>> +{
>> + return 0;
>> +}
>> +#endif
>> #endif /* _PCIE_DESIGNWARE_H */
>>
>
^ permalink raw reply
* Re: [PATCH 16/37] PCI: endpoint: Introduce configfs entry for configuring EP functions
From: Kishon Vijay Abraham I @ 2017-01-16 6:01 UTC (permalink / raw)
To: Christoph Hellwig
Cc: devicetree, Joao Pinto, Arnd Bergmann, linux-doc, Jingoo Han,
linux-arm-msm, nsekhar, linux-kernel, linux-arm-kernel,
linux-samsung-soc, linux-pci, Bjorn Helgaas, linux-omap,
linuxppc-dev, linux-arm-kernel
In-Reply-To: <20170113180602.GA30346@infradead.org>
Hi Christoph,
On Friday 13 January 2017 11:36 PM, Christoph Hellwig wrote:
> Hi Kishon,
>
> a couple comments on the configfs layout based on my experiments with
> your previous drop to implement a NVMe device using it.
Thanks for trying it out!
>
> I don't think most of these configfs files should be present here, as
> they are properties of the implemented PCIe devices. E.g. for my
> NVMe device they will be sort of hardcoded most of the time, as they
> would be for other devices that would always have a fixed vendor/device/
> class ID, cacheline size, etc.
Actually not all devices have hardcoded headers. E.g the platform I'm using
doesn't have hardcoded headers and it can be configured based on the function
the user would like to use. If the devices are hardcoded, then using configfs
can be skipped altogether. In such cases, APIs like pci_epf_create() can
directly be used by the drivers instead of going via configfs.
Thanks
Kishon
^ permalink raw reply
* Re: [PATCH 36/37] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP
From: Kishon Vijay Abraham I @ 2017-01-16 6:05 UTC (permalink / raw)
To: Tony Lindgren
Cc: devicetree, Joao Pinto, Arnd Bergmann, linux-doc, Jingoo Han,
linux-arm-msm, nsekhar, linux-kernel, linux-arm-kernel,
linux-samsung-soc, linux-pci, Bjorn Helgaas, linux-omap,
linuxppc-dev, linux-arm-kernel
In-Reply-To: <20170113171537.GZ2630@atomide.com>
Hi Tony,
On Friday 13 January 2017 10:45 PM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I <kishon@ti.com> [170112 02:35]:
>> The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should
>> be set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO
>> in RC mode. However in EP mode, the host system is not able to access the
>> MEMSPACE and setting the CLKSTCTRL to SW_WKUP fixes it.
>
> I guess ideally in the long run we would set this dynamically based on
> the selected mode, right?
The programming sequence mentioned in the TRM w.r.t clock programming is same
for both host mode or device mode. Though we never faced any issues in host
mode when HW_AUTO is set, it's better to follow TRM recommended settings IMHO.
Thanks
Kishon
>
> Regards,
>
> Tony
>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> arch/arm/mach-omap2/clockdomains7xx_data.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
>> index 6c67965..67ebff8 100644
>> --- a/arch/arm/mach-omap2/clockdomains7xx_data.c
>> +++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
>> @@ -524,7 +524,7 @@
>> .dep_bit = DRA7XX_PCIE_STATDEP_SHIFT,
>> .wkdep_srcs = pcie_wkup_sleep_deps,
>> .sleepdep_srcs = pcie_wkup_sleep_deps,
>> - .flags = CLKDM_CAN_HWSUP_SWSUP,
>> + .flags = CLKDM_CAN_SWSUP,
>> };
>>
>> static struct clockdomain atl_7xx_clkdm = {
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
^ permalink raw reply
* Re: [PATCH v9 0/8] drivers: touchscreen: tsc2007 and ads7846/tsc2046 improvements (use common touchscreen bindings, pre-calibration, spi fix and provide iio raw values)
From: H. Nikolaus Schaller @ 2017-01-16 6:34 UTC (permalink / raw)
To: Sebastian Reichel, Dmitry Torokhov, Mark Rutland,
Benoît Cousson, Tony Lindgren, Russell King, Arnd Bergmann,
Michael Welling, Mika Penttilä, Javier Martinez Canillas,
Igor Grinberg, Andrew F. Davis, Mark Brown, Jonathan Cameron,
Rob Herring, Nikolaus Schaller, Alexander Stein, Eric Engestrom
Cc: linux-input-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
letux-kernel-S0jZdbWzriLCfDggNXIi3w,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
kernel-Jl6IXVxNIMRxAtABVqVhTwC/G2K4zDHf
In-Reply-To: <cover.1482936802.git.hns-xXXSsgcRVICgSpxsJD1C4w@public.gmane.org>
ping
> Am 28.12.2016 um 15:53 schrieb H. Nikolaus Schaller <hns-xXXSsgcRVICgSpxsJD1C4w@public.gmane.org>:
>
> Changes V9:
> * added explicit CONFIG for TSC2007_IIO and simplified Makefile (suggested by Dmitry Torokhov <dmitry.torokhov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>)
> * make the tsc2007 iio patch the last one in this sequence
>
> 2016-11-22 15:02:42: Changes V8:
> * fix compilation for CONFIG_IIO=m (reported by Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>)
> * add some more Reviewed-by: and Acked-by:
> * mutiple improvements suggested by Dmitry Torokhov <dmitry.torokhov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>:
> ** drop patch "send pendown and penup only once" (input core does take care of it now)
> ** remove not necessary EXPORT_SYMBOL
> ** remove explicit file names from comment header
> ** move tsc2007_iio_configure() to the end of the probe process and simplify the error path again
> ** remove unnecessary input_unregister_device()
> ** improvement for compilation with CONFIG_IIO=m and CONFIG_TSC2007=y
>
> 2016-11-11 20:02:11: Changes V7:
> * rearranged the include files (asked for by Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>)
> * forward reference struct iio_dev * instead of condition in tsc2007.h (asked for by Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>)
> * add some Acked-by:
>
> 2016-10-27 10:44:29: Changes V6:
> * iio patch (no changes elsewhere)
> - tsc2007_iio: fix a missing return 0 for non-iio case (found by kbuid test robot)
> - tsc2007_core: group error return paths so that tsc2007_iio_unconfigure is called at only one place
> - tsc2007_iio: fix copyright (this file is 100% original work)
>
> 2016-10-25 21:26:46: Changes V5:
> * ads7846: remove an empty line (suggested by Andrew F. Davis <afd-l0cyMroinI0@public.gmane.org>)
> * ads7846: remove MODULE_ALIAS for SPI (suggested by Andrew F. Davis <afd-l0cyMroinI0@public.gmane.org>)
> * tsc2007: fix a bug from swapping patch 3/n and patch 4/n (found by kbuild test robot)
> * refactored tsc2007 into tsc2007_core and tsc2007_iio (asked for by Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>)
>
> 2016-10-17 16:00:02: Changes V4:
> * fix a merge/squash issue resulting in a non-bisectable patch set (suggested by kbuid test robot)
> * remove some unnecessary #include (suggested by Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>)
> * make the iio extension depend on CONFIG_IIO rather than selecting it (suggested by Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>)
> * swapped patch 3/n and patch 4/n to remove internal dependency
>
> 2016-09-23 14:41:23: Changes V3:
> * fix an issue with swapping
> * remove hard clipping to min/max rectangle - some systems expect to handle negative coordinates
> * make use of commit ed7c9870c9bc ("Input: of_touchscreen - add support for inverted / swapped axes")
>
> 2015-11-13 21:36:07: Changes V2:
> * add a patch to make drivers still recognise the old "ti,swap-xy" property (suggested by Rob Herring)
>
> 2015-11-06 16:14:53: V1: This patch series improves the drivers for the tsc2007 and
> ads7846/tsc2046 touchscreen controllers which are e.g. used by the GTA04
> OpenPandora and Pyra devices.
>
> New common bindings have been defined by
> commit b98abe52fa8e ("Input: add common DT binding for touchscreens"):
>
> Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
>
> which also defines a helper function to parse the DT. These new parameters
> allow to specify the fuzz factors (jitter suppression), inversion of x or y axis and
> swapping of x and y to achieve inversion and rotation so that the touch
> coordinate axes match the natural orientation of the display panel.
>
> Another improvement is to better use the min/max ADC values and
> scale to the screen size as defined by the DT. This allows to coarsely
> calibrate the touch to match the LCD to which it is glued on so that the
> touch can quite precisely be operated before any user-space fine-calibration
> can be (and needs to be) started.
>
> For the adc7846 we fix an issue with the spi module table.
>
> Finally we add an iio interface for the AUX and temperature ADC channels of
> the tsc2007 and also provide the touch screen raw values. This allows to read
> an optional ambient light sensor installed on the gta04 board and improves
> calibration and hardware monitoring.
>
>
> H. Nikolaus Schaller (8):
> drivers:input:tsc2007: add new common binding names, pre-calibration,
> flipping and rotation
> drivers:input:tsc2007: check for presence and power down tsc2007
> during probe
> DT:omap3+tsc2007: use new common touchscreen bindings
> drivers:input:ads7846(+tsc2046): add new common binding names,
> pre-calibration and flipping
> dt-bindings: input: move ads7846 bindings to touchscreen subdirectory
> drivers:input:ads7846(+tsc2046): fix spi module table
> DT:omap3+ads7846: use new common touchscreen bindings
> drivers:input:tsc2007: add iio interface to read external ADC input
> and temperature
>
> .../bindings/input/{ => touchscreen}/ads7846.txt | 9 +-
> .../bindings/input/touchscreen/tsc2007.txt | 20 +-
> arch/arm/boot/dts/omap3-gta04.dtsi | 25 ++-
> arch/arm/boot/dts/omap3-lilly-a83x.dtsi | 2 +-
> arch/arm/boot/dts/omap3-pandora-common.dtsi | 17 +-
> .../boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi | 3 +-
> drivers/input/touchscreen/Kconfig | 10 +
> drivers/input/touchscreen/Makefile | 2 +
> drivers/input/touchscreen/ads7846.c | 71 ++++++--
> drivers/input/touchscreen/tsc2007.h | 116 ++++++++++++
> .../touchscreen/{tsc2007.c => tsc2007_core.c} | 201 ++++++++++++---------
> drivers/input/touchscreen/tsc2007_iio.c | 150 +++++++++++++++
> include/linux/i2c/tsc2007.h | 8 +
> 13 files changed, 520 insertions(+), 114 deletions(-)
> rename Documentation/devicetree/bindings/input/{ => touchscreen}/ads7846.txt (90%)
> create mode 100644 drivers/input/touchscreen/tsc2007.h
> rename drivers/input/touchscreen/{tsc2007.c => tsc2007_core.c} (74%)
> create mode 100644 drivers/input/touchscreen/tsc2007_iio.c
>
> --
> 2.7.3
>
^ permalink raw reply
* Re: [PATCH] pcie: ti: Provide patch to force GEN1 PCIe operation
From: Kishon Vijay Abraham I @ 2017-01-16 6:37 UTC (permalink / raw)
To: Lukasz Majewski, Bjorn Helgaas
Cc: Rob Herring, Mark Rutland, Jingoo Han, Joao Pinto, linux-omap,
linux-pci, devicetree, linux-kernel
In-Reply-To: <1484486354-4585-1-git-send-email-lukma@denx.de>
Hi,
On Sunday 15 January 2017 06:49 PM, Lukasz Majewski wrote:
> Some devices (due to e.g. bad PCIe signal integrity) require to run
> with forced GEN1 speed on PCIe bus.
>
> This patch changes the speed explicitly on dra7 based devices when
> proper device tree attribute is defined for the PCIe controller.
>
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
Bjorn has already queued a patch to do the same thing
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/log/?h=pci/host-dra7xx
Thanks
Kishon
> ---
>
> Patch applies on newest origin/master
> SHA1: f4d3935e4f4884ba80561db5549394afb8eef8f7
>
> Tested at AM5728
>
> ---
> Documentation/devicetree/bindings/pci/ti-pci.txt | 1 +
> drivers/pci/host/pci-dra7xx.c | 23 +++++++++++++++++++++++
> drivers/pci/host/pcie-designware.h | 1 +
> 3 files changed, 25 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
> index 60e2516..9f97409 100644
> --- a/Documentation/devicetree/bindings/pci/ti-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
> @@ -25,6 +25,7 @@ PCIe Designware Controller
>
> Optional Property:
> - gpios : Should be added if a gpio line is required to drive PERST# line
> + - to,pcie-is-gen1: Indicates that forced gen1 port operation is needed.
>
> Example:
> axi {
> diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
> index 9595fad..eec5fae 100644
> --- a/drivers/pci/host/pci-dra7xx.c
> +++ b/drivers/pci/host/pci-dra7xx.c
> @@ -63,6 +63,13 @@
> #define LINK_UP BIT(16)
> #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
>
> +#define PCIECTRL_EP_DBICS_LNK_CAP 0x007C
> +#define MAX_LINK_SPEEDS_MASK GENMASK(3, 0)
> +#define MAX_LINK_SPEEDS_GEN1 BIT(0)
> +
> +#define PCIECTRL_PL_WIDTH_SPEED_CTL 0x080C
> +#define CFG_DIRECTED_SPEED_CHANGE BIT(17)
> +
> struct dra7xx_pcie {
> struct pcie_port pp;
> void __iomem *base; /* DT ti_conf */
> @@ -270,6 +277,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
> struct pcie_port *pp = &dra7xx->pp;
> struct device *dev = pp->dev;
> struct resource *res;
> + u32 val;
>
> pp->irq = platform_get_irq(pdev, 1);
> if (pp->irq < 0) {
> @@ -296,6 +304,18 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
> if (!pp->dbi_base)
> return -ENOMEM;
>
> + if (pp->is_gen1) {
> + dev_info(dev, "GEN1 forced\n");
> +
> + val = readl(pp->dbi_base + PCIECTRL_EP_DBICS_LNK_CAP);
> + set_mask_bits(&val, MAX_LINK_SPEEDS_MASK, MAX_LINK_SPEEDS_GEN1);
> + writel(val, pp->dbi_base + PCIECTRL_EP_DBICS_LNK_CAP);
> +
> + val = readl(pp->dbi_base + PCIECTRL_PL_WIDTH_SPEED_CTL);
> + val &= ~CFG_DIRECTED_SPEED_CHANGE;
> + writel(val, pp->dbi_base + PCIECTRL_PL_WIDTH_SPEED_CTL);
> + }
> +
> ret = dw_pcie_host_init(pp);
> if (ret) {
> dev_err(dev, "failed to initialize host\n");
> @@ -404,6 +424,9 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
> goto err_gpio;
> }
>
> + if (of_property_read_bool(np, "ti,pcie-is-gen1"))
> + pp->is_gen1 = true;
> +
> reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
> reg &= ~LTSSM_EN;
> dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index a567ea2..2fb0b18 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -50,6 +50,7 @@ struct pcie_port {
> struct irq_domain *irq_domain;
> unsigned long msi_data;
> u8 iatu_unroll_enabled;
> + u8 is_gen1;
> DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
> };
>
>
^ permalink raw reply
* Re: [PATCH] pcie: ti: Provide patch to force GEN1 PCIe operation
From: Lukasz Majewski @ 2017-01-16 6:49 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Bjorn Helgaas, Rob Herring, Mark Rutland, Jingoo Han, Joao Pinto,
linux-omap, linux-pci, devicetree, linux-kernel
In-Reply-To: <587C6A40.8070608@ti.com>
Hi Kishon,
> Hi,
>
> On Sunday 15 January 2017 06:49 PM, Lukasz Majewski wrote:
> > Some devices (due to e.g. bad PCIe signal integrity) require to run
> > with forced GEN1 speed on PCIe bus.
> >
> > This patch changes the speed explicitly on dra7 based devices when
> > proper device tree attribute is defined for the PCIe controller.
> >
> > Signed-off-by: Lukasz Majewski <lukma@denx.de>
>
> Bjorn has already queued a patch to do the same thing
> https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/log/?h=pci/host-dra7xx
It seems like Bjorn only modifies CAP registers.
He also needs to change register with 0x080C offset to actually
( PCIECTRL_PL_WIDTH_SPEED_CTL )
Best regards,
Łukasz
>
> Thanks
> Kishon
>
> > ---
> >
> > Patch applies on newest origin/master
> > SHA1: f4d3935e4f4884ba80561db5549394afb8eef8f7
> >
> > Tested at AM5728
> >
> > ---
> > Documentation/devicetree/bindings/pci/ti-pci.txt | 1 +
> > drivers/pci/host/pci-dra7xx.c | 23
> > +++++++++++++++++++++++
> > drivers/pci/host/pcie-designware.h | 1 + 3 files
> > changed, 25 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
> > b/Documentation/devicetree/bindings/pci/ti-pci.txt index
> > 60e2516..9f97409 100644 ---
> > a/Documentation/devicetree/bindings/pci/ti-pci.txt +++
> > b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -25,6 +25,7
> > @@ PCIe Designware Controller
> > Optional Property:
> > - gpios : Should be added if a gpio line is required to drive
> > PERST# line
> > + - to,pcie-is-gen1: Indicates that forced gen1 port operation is
> > needed.
> > Example:
> > axi {
> > diff --git a/drivers/pci/host/pci-dra7xx.c
> > b/drivers/pci/host/pci-dra7xx.c index 9595fad..eec5fae 100644
> > --- a/drivers/pci/host/pci-dra7xx.c
> > +++
> > b/drivers/pci/host/pci-https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/log/?h=pci/host-dra7xxdra7xx.c
> > @@ -63,6 +63,13 @@ #define
> > LINK_UP BIT(16)
> > #define
> > DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
> > +#define PCIECTRL_EP_DBICS_LNK_CAP
> > 0x007C +#define
> > MAX_LINK_SPEEDS_MASK GENMASK(3, 0)
> > +#define MAX_LINK_SPEEDS_GEN1
> > BIT(0) + +#define
> > PCIECTRL_PL_WIDTH_SPEED_CTL 0x080C
> > +#define CFG_DIRECTED_SPEED_CHANGE
> > BIT(17) + struct dra7xx_pcie { struct pcie_port pp;
> > void __iomem *base; /* DT
> > ti_conf */ @@ -270,6 +277,7 @@ static int __init
> > dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, struct pcie_port
> > *pp = &dra7xx->pp; struct device *dev = pp->dev;
> > struct resource *res;
> > + u32 val;
> >
> > pp->irq = platform_get_irq(pdev, 1);
> > if (pp->irq < 0) {
> > @@ -296,6 +304,18 @@ static int __init dra7xx_add_pcie_port(struct
> > dra7xx_pcie *dra7xx, if (!pp->dbi_base)
> > return -ENOMEM;
> >
> > + if (pp->is_gen1) {
> > + dev_info(dev, "GEN1 forced\n");
> > +
> > + val = readl(pp->dbi_base +
> > PCIECTRL_EP_DBICS_LNK_CAP);
> > + set_mask_bits(&val, MAX_LINK_SPEEDS_MASK,
> > MAX_LINK_SPEEDS_GEN1);
> > + writel(val, pp->dbi_base +
> > PCIECTRL_EP_DBICS_LNK_CAP); +
> > + val = readl(pp->dbi_base +
> > PCIECTRL_PL_WIDTH_SPEED_CTL);
> > + val &= ~CFG_DIRECTED_SPEED_CHANGE;
> > + writel(val, pp->dbi_base +
> > PCIECTRL_PL_WIDTH_SPEED_CTL);
> > + }
> > +
> > ret = dw_pcie_host_init(pp);
> > if (ret) {
> > dev_err(dev, "failed to initialize host\n");
> > @@ -404,6 +424,9 @@ static int __init dra7xx_pcie_probe(struct
> > platform_device *pdev) goto err_gpio;
> > }
> >
> > + if (of_property_read_bool(np, "ti,pcie-is-gen1"))
> > + pp->is_gen1 = true;
> > +
> > reg = dra7xx_pcie_readl(dra7xx,
> > PCIECTRL_DRA7XX_CONF_DEVICE_CMD); reg &= ~LTSSM_EN;
> > dra7xx_pcie_writel(dra7xx,
> > PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); diff --git
> > a/drivers/pci/host/pcie-designware.h
> > b/drivers/pci/host/pcie-designware.h index a567ea2..2fb0b18 100644
> > --- a/drivers/pci/host/pcie-designware.h +++
> > b/drivers/pci/host/pcie-designware.h @@ -50,6 +50,7 @@ struct
> > pcie_port { struct irq_domain *irq_domain;
> > unsigned long msi_data;
> > u8 iatu_unroll_enabled;
> > + u8 is_gen1;
> > DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
> > };
> >
> >
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
^ permalink raw reply
* Re: [PATCH v1 1/3] dt: bindings: add documentation for zx2967 family reset controller
From: Shawn Guo @ 2017-01-16 7:09 UTC (permalink / raw)
To: Baoyou Xie
Cc: jun.nie, p.zabel, robh+dt, mark.rutland, linux-arm-kernel,
devicetree, linux-kernel, xie.baoyou, chen.chaokai, wang.qiang01
In-Reply-To: <1484377530-30635-1-git-send-email-baoyou.xie@linaro.org>
On Sat, Jan 14, 2017 at 03:05:28PM +0800, Baoyou Xie wrote:
> This patch adds dt-binding documentation for zx2967 family
> reset controller.
>
> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Reviewed-by: Shawn Guo <shawnguo@kernel.org>
^ permalink raw reply
* Re: [PATCH v6 2/3] input: tm2-touchkey: Add touchkey driver support for TM2
From: Jaechul Lee @ 2017-01-16 7:24 UTC (permalink / raw)
To: Dmitry Torokhov
Cc: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
Kukjin Kim, Krzysztof Kozlowski, Javier Martinez Canillas,
Andi Shyti, Chanwoo Choi, beomho.seo, galaxyra, linux-arm-kernel,
linux-input, devicetree, linux-kernel, linux-samsung-soc
In-Reply-To: <20170115071110.GA24007@dtor-ws>
Dear Dmitry Torokhov,
On Sat, Jan 14, 2017 at 11:11:10PM -0800, Dmitry Torokhov wrote:
> Hi Jaechul,
>
> On Mon, Jan 09, 2017 at 04:22:14PM +0900, Jaechul Lee wrote:
> > +static irqreturn_t tm2_touchkey_irq_handler(int irq, void *devid)
> > +{
> > + struct tm2_touchkey_data *touchkey = devid;
> > + u32 data;
> > +
> > + data = i2c_smbus_read_byte_data(touchkey->client,
> > + TM2_TOUCHKEY_KEYCODE_REG);
> > +
> > + if (data < 0) {
>
> You declared data as u32 so it will never be negative.
Yes, it won't be negative.
>
> > + dev_err(&touchkey->client->dev, "Failed to read i2c data\n");
> > + return IRQ_HANDLED;
> > + }
> > +
> > + touchkey->keycode_type = data & TM2_TOUCHKEY_BIT_KEYCODE;
> > + touchkey->pressed = !(data & TM2_TOUCHKEY_BIT_PRESS_EV);
>
> There is no need to store this in touchkey structure as you are not
> going to use it past this function.
I agree with you. it doesn't need to store variables in touchkey structure.
>
> Does the version of the patch below work for you?
I found that the condition is inverted.
if data & TM2_TOUCHKEY_BIT_PRESS_EV is true, it means touchkey is released.
it should be changed like this.
if (data & TM2_TOUCHKEY_BIT_PRESS_EV) {
input_report_key(touchkey->input_dev, KEY_PHONE, 0);
input_report_key(touchkey->input_dev, KEY_BACK, 0);
} else {
input_report_key(touchkey->input_dev, key, 1);
}
I will prepare for patch v7 based on your modifications.
Thank you very much for your reviews.
Best Regards,
Jaechul
>
> Thanks.
>
> --
> Dmitry
>
>
> Input: tm2-touchkey - add touchkey driver support for TM2
>
> From: Jaechul Lee <jcsing.lee@samsung.com>
>
> This patch adds support for the TM2 touch key and led functionality.
>
> The driver interfaces with userspace through an input device and
> reports KEY_PHONE and KEY_BACK event types. LED brightness can be
> controlled by "/sys/class/leds/tm2-touchkey/brightness".
>
> Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
> Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
> Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> Patchwork-Id: 9504149
> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
> ---
> drivers/input/keyboard/Kconfig | 11 +
> drivers/input/keyboard/Makefile | 1
> drivers/input/keyboard/tm2-touchkey.c | 286 +++++++++++++++++++++++++++++++++
> 3 files changed, 298 insertions(+)
> create mode 100644 drivers/input/keyboard/tm2-touchkey.c
>
> diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
> index cbd75cf44739..97acd6524ad7 100644
> --- a/drivers/input/keyboard/Kconfig
> +++ b/drivers/input/keyboard/Kconfig
> @@ -666,6 +666,17 @@ config KEYBOARD_TC3589X
> To compile this driver as a module, choose M here: the
> module will be called tc3589x-keypad.
>
> +config KEYBOARD_TM2_TOUCHKEY
> + tristate "TM2 touchkey support"
> + depends on I2C
> + depends on LEDS_CLASS
> + help
> + Say Y here to enable device driver for tm2-touchkey with
> + LED control for the Exynos5433 TM2 board.
> +
> + To compile this driver as a module, choose M here.
> + module will be called tm2-touchkey.
> +
> config KEYBOARD_TWL4030
> tristate "TI TWL4030/TWL5030/TPS659x0 keypad support"
> depends on TWL4030_CORE
> diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
> index d9f4cfcf3410..7d9acff819a7 100644
> --- a/drivers/input/keyboard/Makefile
> +++ b/drivers/input/keyboard/Makefile
> @@ -61,6 +61,7 @@ obj-$(CONFIG_KEYBOARD_SUN4I_LRADC) += sun4i-lradc-keys.o
> obj-$(CONFIG_KEYBOARD_SUNKBD) += sunkbd.o
> obj-$(CONFIG_KEYBOARD_TC3589X) += tc3589x-keypad.o
> obj-$(CONFIG_KEYBOARD_TEGRA) += tegra-kbc.o
> +obj-$(CONFIG_KEYBOARD_TM2_TOUCHKEY) += tm2-touchkey.o
> obj-$(CONFIG_KEYBOARD_TWL4030) += twl4030_keypad.o
> obj-$(CONFIG_KEYBOARD_XTKBD) += xtkbd.o
> obj-$(CONFIG_KEYBOARD_W90P910) += w90p910_keypad.o
> diff --git a/drivers/input/keyboard/tm2-touchkey.c b/drivers/input/keyboard/tm2-touchkey.c
> new file mode 100644
> index 000000000000..79bc2d2bd4b9
> --- /dev/null
> +++ b/drivers/input/keyboard/tm2-touchkey.c
> @@ -0,0 +1,286 @@
> +/*
> + * TM2 touchkey device driver
> + *
> + * Copyright 2005 Phil Blundell
> + * Copyright 2016 Samsung Electronics Co., Ltd.
> + *
> + * Author: Beomho Seo <beomho.seo@samsung.com>
> + * Author: Jaechul Lee <jcsing.lee@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/i2c.h>
> +#include <linux/input.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/leds.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/pm.h>
> +#include <linux/regulator/consumer.h>
> +
> +#define TM2_TOUCHKEY_DEV_NAME "tm2-touchkey"
> +#define TM2_TOUCHKEY_KEYCODE_REG 0x03
> +#define TM2_TOUCHKEY_BASE_REG 0x00
> +#define TM2_TOUCHKEY_CMD_LED_ON 0x10
> +#define TM2_TOUCHKEY_CMD_LED_OFF 0x20
> +#define TM2_TOUCHKEY_BIT_PRESS_EV BIT(3)
> +#define TM2_TOUCHKEY_BIT_KEYCODE GENMASK(2, 0)
> +#define TM2_TOUCHKEY_LED_VOLTAGE_MIN 2500000
> +#define TM2_TOUCHKEY_LED_VOLTAGE_MAX 3300000
> +
> +enum {
> + TM2_TOUCHKEY_KEY_MENU = 0x1,
> + TM2_TOUCHKEY_KEY_BACK,
> +};
> +
> +struct tm2_touchkey_data {
> + struct i2c_client *client;
> + struct input_dev *input_dev;
> + struct led_classdev led_dev;
> + struct regulator *vdd;
> + struct regulator_bulk_data regulators[2];
> +};
> +
> +static void tm2_touchkey_led_brightness_set(struct led_classdev *led_dev,
> + enum led_brightness brightness)
> +{
> + struct tm2_touchkey_data *touchkey =
> + container_of(led_dev, struct tm2_touchkey_data, led_dev);
> + u32 volt;
> + u8 data;
> +
> + if (brightness == LED_OFF) {
> + volt = TM2_TOUCHKEY_LED_VOLTAGE_MIN;
> + data = TM2_TOUCHKEY_CMD_LED_OFF;
> + } else {
> + volt = TM2_TOUCHKEY_LED_VOLTAGE_MAX;
> + data = TM2_TOUCHKEY_CMD_LED_ON;
> + }
> +
> + regulator_set_voltage(touchkey->vdd, volt, volt);
> + i2c_smbus_write_byte_data(touchkey->client,
> + TM2_TOUCHKEY_BASE_REG, data);
> +}
> +
> +static int tm2_touchkey_power_enable(struct tm2_touchkey_data *touchkey)
> +{
> + int error;
> +
> + error = regulator_bulk_enable(ARRAY_SIZE(touchkey->regulators),
> + touchkey->regulators);
> + if (error)
> + return error;
> +
> + /* waiting for device initialization, at least 150ms */
> + msleep(150);
> +
> + return 0;
> +}
> +
> +static void tm2_touchkey_power_disable(void *data)
> +{
> + struct tm2_touchkey_data *touchkey = data;
> +
> + regulator_bulk_disable(ARRAY_SIZE(touchkey->regulators),
> + touchkey->regulators);
> +}
> +
> +static irqreturn_t tm2_touchkey_irq_handler(int irq, void *devid)
> +{
> + struct tm2_touchkey_data *touchkey = devid;
> + int data;
> + int key;
> +
> + data = i2c_smbus_read_byte_data(touchkey->client,
> + TM2_TOUCHKEY_KEYCODE_REG);
> + if (data < 0) {
> + dev_err(&touchkey->client->dev,
> + "failed to read i2c data: %d\n", data);
> + goto out;
> + }
> +
> + switch (data & TM2_TOUCHKEY_BIT_KEYCODE) {
> + case TM2_TOUCHKEY_KEY_MENU:
> + key = KEY_PHONE;
> + break;
> +
> + case TM2_TOUCHKEY_KEY_BACK:
> + key = KEY_BACK;
> + break;
> +
> + default:
> + dev_warn(&touchkey->client->dev,
> + "unhandled keycode, data %#02x\n", data);
> + goto out;
> + }
> +
> + if (data & TM2_TOUCHKEY_BIT_PRESS_EV) {
> + input_report_key(touchkey->input_dev, key, 1);
> + } else {
> + input_report_key(touchkey->input_dev, KEY_PHONE, 0);
> + input_report_key(touchkey->input_dev, KEY_BACK, 0);
> + }
> +
> + input_sync(touchkey->input_dev);
> +
> +out:
> + return IRQ_HANDLED;
> +}
> +
> +static int tm2_touchkey_probe(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + struct tm2_touchkey_data *touchkey;
> + int error;
> +
> + if (!i2c_check_functionality(client->adapter,
> + I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA)) {
> + dev_err(&client->dev, "incompatible I2C adapter\n");
> + return -EIO;
> + }
> +
> + touchkey = devm_kzalloc(&client->dev, sizeof(*touchkey), GFP_KERNEL);
> + if (!touchkey)
> + return -ENOMEM;
> +
> + touchkey->client = client;
> + i2c_set_clientdata(client, touchkey);
> +
> + touchkey->regulators[0].supply = "vcc";
> + touchkey->regulators[1].supply = "vdd";
> + error = devm_regulator_bulk_get(&client->dev,
> + ARRAY_SIZE(touchkey->regulators),
> + touchkey->regulators);
> + if (error) {
> + dev_err(&client->dev, "failed to get regulators: %d\n", error);
> + return error;
> + }
> +
> + /* Save VDD for easy access */
> + touchkey->vdd = touchkey->regulators[1].consumer;
> +
> + error = tm2_touchkey_power_enable(touchkey);
> + if (error) {
> + dev_err(&client->dev, "failed to power up device: %d\n", error);
> + return error;
> + }
> +
> + error = devm_add_action_or_reset(&client->dev,
> + tm2_touchkey_power_disable, touchkey);
> + if (error) {
> + dev_err(&client->dev,
> + "failed to install poweroff handler: %d\n", error);
> + return error;
> + }
> +
> + /* input device */
> + touchkey->input_dev = devm_input_allocate_device(&client->dev);
> + if (!touchkey->input_dev) {
> + dev_err(&client->dev, "failed to allocate input device\n");
> + return -ENOMEM;
> + }
> +
> + touchkey->input_dev->name = TM2_TOUCHKEY_DEV_NAME;
> + touchkey->input_dev->id.bustype = BUS_I2C;
> +
> + input_set_capability(touchkey->input_dev, EV_KEY, KEY_PHONE);
> + input_set_capability(touchkey->input_dev, EV_KEY, KEY_BACK);
> +
> + input_set_drvdata(touchkey->input_dev, touchkey);
> +
> + error = input_register_device(touchkey->input_dev);
> + if (error) {
> + dev_err(&client->dev,
> + "failed to register input device: %d\n", error);
> + return error;
> + }
> +
> + error = devm_request_threaded_irq(&client->dev, client->irq,
> + NULL, tm2_touchkey_irq_handler,
> + IRQF_ONESHOT,
> + TM2_TOUCHKEY_DEV_NAME, touchkey);
> + if (error) {
> + dev_err(&client->dev,
> + "failed to request threaded irq: %d\n", error);
> + return error;
> + }
> +
> + /* led device */
> + touchkey->led_dev.name = TM2_TOUCHKEY_DEV_NAME;
> + touchkey->led_dev.brightness = LED_FULL;
> + touchkey->led_dev.max_brightness = LED_FULL;
> + touchkey->led_dev.brightness_set = tm2_touchkey_led_brightness_set;
> +
> + error = devm_led_classdev_register(&client->dev, &touchkey->led_dev);
> + if (error) {
> + dev_err(&client->dev,
> + "failed to register touchkey led: %d\n", error);
> + return error;
> + }
> +
> + return 0;
> +}
> +
> +static int __maybe_unused tm2_touchkey_suspend(struct device *dev)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> + struct tm2_touchkey_data *touchkey = i2c_get_clientdata(client);
> +
> + disable_irq(client->irq);
> + tm2_touchkey_power_disable(touchkey);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused tm2_touchkey_resume(struct device *dev)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> + struct tm2_touchkey_data *touchkey = i2c_get_clientdata(client);
> + int ret;
> +
> + enable_irq(client->irq);
> +
> + ret = tm2_touchkey_power_enable(touchkey);
> + if (ret)
> + dev_err(dev, "failed to enable power: %d\n", ret);
> +
> + return ret;
> +}
> +
> +static SIMPLE_DEV_PM_OPS(tm2_touchkey_pm_ops,
> + tm2_touchkey_suspend, tm2_touchkey_resume);
> +
> +static const struct i2c_device_id tm2_touchkey_id_table[] = {
> + { TM2_TOUCHKEY_DEV_NAME, 0 },
> + { },
> +};
> +MODULE_DEVICE_TABLE(i2c, tm2_touchkey_id_table);
> +
> +static const struct of_device_id tm2_touchkey_of_match[] = {
> + { .compatible = "cypress,tm2-touchkey", },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, tm2_touchkey_of_match);
> +
> +static struct i2c_driver tm2_touchkey_driver = {
> + .driver = {
> + .name = TM2_TOUCHKEY_DEV_NAME,
> + .pm = &tm2_touchkey_pm_ops,
> + .of_match_table = of_match_ptr(tm2_touchkey_of_match),
> + },
> + .probe = tm2_touchkey_probe,
> + .id_table = tm2_touchkey_id_table,
> +};
> +module_i2c_driver(tm2_touchkey_driver);
> +
> +MODULE_AUTHOR("Beomho Seo <beomho.seo@samsung.com>");
> +MODULE_AUTHOR("Jaechul Lee <jcsing.lee@samsung.com>");
> +MODULE_DESCRIPTION("Samsung touchkey driver");
> +MODULE_LICENSE("GPL v2");
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v4 0/2] Add rockchip serial flash controller support
From: Shawn Lin @ 2017-01-16 7:28 UTC (permalink / raw)
To: David Woodhouse, Brian Norris, Cyrille Pitchen
Cc: shawn.lin-TNX95d0MmH7DzftRWevZcw,
devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner, Marek Vasut,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1481794068-241619-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Hi Cyrille,
On 2016/12/15 17:27, Shawn Lin wrote:
>
> Here is another try for adding serial flash controller
> , namely SFC, found on Rockchip RK1108 platform.
>
Seems this patchset was acked by Marek and there is no more
comments from then. Does it look good to you?
> Feature:
> (1) Support x1, x2, x4 data bits mode
> (2) Support up to 4 chip select
> (3) Support two independent clock domain: AHB clock and SPI clock
> (4) Support DMA master up to 16KB/transfer
>
> Test environment:
> This patchset was tested on RK1108 evb boards with Winboud flash
> (w25q256) and working fine with PIO or DMA mode.
>
> How-to:
> Any rockchip guys who are interested in testing it could refer to
> the following steps:
> (1) enable CONFIG_MTD_M25P80
> (2) enable CONFIG_SPI_ROCKCHIP_SFC
> (3) enable CONFIG_MTD_CMDLINE_PARTS
> (4) enable CONFIG_SQUASHFS
> (4) CONFIG_CMDLINE="root=/dev/mtdblock2
> mtdparts=spi-nor:256k@0(loader)ro,8m(kernel)ro,7m(rootfs),-(freedisk)"
> Of course, you should check the partition layout if you modify it. Also
> you could pass it from your loader to the kernel's cmdline.
> (5) Add dts support:
> nor_flash: sfc@301c0000 {
> compatible = "rockchip,rk1108-sfc", "rockchip,sfc";
> #address-cells = <1>;
> #size-cells = <0>;
> clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
> clock-names = "sfc", "hsfc";
> interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x301c0000 0x1000>;
> /* If you want to use PIO mode, activate this */
> #rockchip,sfc-no-dma;
> spi-nor@0 {
> compatible = "jedec,spi-nor";
> spi-max-frequency = <12000000>;
> reg = <0>;
> }
> };
>
> please make sure your DT's mdtid matchs what you assgin to the
> mdtparts(cmdline), namely they are both *spi-nor* here.
>
> With enabling DBG for cmdlinepart.c, you could get following log and
> boot kernel and rootfs successfully.
>
> [ 0.481420] rockchip-sfc 301c0000.sfc: w25q256 (32768 Kbytes)
> [ 0.481962] DEBUG-CMDLINE-PART: parsing
> <256k@0(loader)ro,8m(kernel)ro,7m(rootfs)ro,-(freedisk)>
> [ 0.482897] DEBUG-CMDLINE-PART: partition 3: name
> <freedisk>, offset ffffffffffffffff, size ffffffffffffffff, mask flags 0
> [ 0.484021] DEBUG-CMDLINE-PART: partition 2: name
> <rootfs>, offset ffffffffffffffff, size 700000, mask flags 400
> [ 0.485066] DEBUG-CMDLINE-PART: partition 1: name
> <kernel>, offset ffffffffffffffff, size 800000, mask flags 400
> [ 0.486108] DEBUG-CMDLINE-PART: partition 0: name
> <loader>, offset 0, size 40000, mask flags 400
> [ 0.487152] DEBUG-CMDLINE-PART: mtdid=<spi-nor> num_parts=<4>
> [ 0.487827] 4 cmdlinepart partitions found on MTD device spi-nor
> [ 0.488370] Creating 4 MTD partitions on "spi-nor":
> [ 0.488826] 0x000000000000-0x000000040000 : "loader"
> [ 0.492340] 0x000000040000-0x000000840000 : "kernel"
> [ 0.495679] 0x000000840000-0x000000f40000 : "rootfs"
> [ 0.499241] 0x000000f40000-0x000002000000 : "freedisk"
>
> [root@arm-linux]#
> [root@arm-linux]#mount
> /dev/root on / type squashfs (ro,relatime)
> devtmpfs on /dev type devtmpfs
> (rw,relatime,size=26124k,nr_inodes=6531,mode=755)
> proc on /proc type proc (rw,relatime)
> none on /tmp type ramfs (rw,relatime)
> none on /var type ramfs (rw,relatime)
> sysfs on /sys type sysfs (rw,relatime)
> debug on /sys/kernel/debug type debugfs (rw,relatime)
> none on /dev/pts type devpts (rw,relatime,mode=600,ptmxmode=000)
>
>
> Changes in v4:
> - use uppercase DMA for description
> - simplify the code of get_if_type
> - use dma_dir to simplify the code
> - simplify the rockchip_sfc_do_rd_wr
> - some minor improvements
> - add reset controller when doing resume
>
> Changes in v3:
> - use io{read32,write32}_rep to simplify the corner cases
> - remove more unnecessary bit definitions
> - some minor comment fixes and improvement
> - fix wrong unregister function
> - unify more code
> - use nor to avoid constantly replicating the whole
> sfc->flash[sfc->num_chip].nor
> - add email for MODULE_AUTHOR
> - remove #if 1 --- #endif
> - extract DMA code to imporve the code structure
> - reset all when failing to do dma
> - pass sfc to get_if_type
> - rename sfc-no-dma to sfc-no-DMA
>
> Changes in v2:
> - fix typos
> - add some comment for buffer and others operations
> - rename SFC_MAX_CHIP_NUM to MAX_CHIPSELECT_NUM
> - use u8 for cs
> - return -EINVAL for default case of get_if_type
> - use readl_poll_*() to check timeout cases
> - simplify and clarify some condition checks
> - rework the bitshifts to simplify the code
> - define SFC_CMD_DUMMY(x)
> - fix ummap for dma read path and finish all the
> cache maintenance.
> - rename to rockchip_sfc_chip_priv and embed struct spi_nor
> in it.
> - add MODULE_AUTHOR
> - add runtime PM and general PM support.
> - Thanks for Marek's comments. Link:
> http://lists.infradead.org/pipermail/linux-mtd/2016-November/070321.html
>
> Shawn Lin (2):
> mtd: spi-nor: Bindings for Rockchip serial flash controller
> mtd: spi-nor: add rockchip serial flash controller driver
>
> .../devicetree/bindings/mtd/rockchip-sfc.txt | 31 +
> MAINTAINERS | 8 +
> drivers/mtd/spi-nor/Kconfig | 7 +
> drivers/mtd/spi-nor/Makefile | 1 +
> drivers/mtd/spi-nor/rockchip-sfc.c | 872 +++++++++++++++++++++
> 5 files changed, 919 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/rockchip-sfc.txt
> create mode 100644 drivers/mtd/spi-nor/rockchip-sfc.c
>
--
Best Regards
Shawn Lin
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH V2] usb: xhci: add support for performing fake doorbell
From: Rafał Miłecki @ 2017-01-16 7:32 UTC (permalink / raw)
To: Mathias Nyman, Jon Mason, Florian Fainelli, BCM Kernel Feedback
Cc: Mathias Nyman, Greg Kroah-Hartman, Hauke Mehrtens, Rob Herring,
Mark Rutland, linux-usb@vger.kernel.org,
devicetree@vger.kernel.org, Linux Kernel Mailing List,
Rafał Miłecki
In-Reply-To: <58331360.5000508@linux.intel.com>
On 21 November 2016 at 16:31, Mathias Nyman
<mathias.nyman@linux.intel.com> wrote:
> On 21.11.2016 09:57, Rafał Miłecki wrote:
>>
>> Hi Mathias,
>>
>> On 17 October 2016 at 22:30, Rafał Miłecki <zajec5@gmail.com> wrote:
>>>
>>> From: Rafał Miłecki <rafal@milecki.pl>
>>>
>>> Broadcom's Northstar XHCI controllers seem to need a special start
>>> procedure to work correctly. There isn't any official documentation of
>>> this, the problem is that controller doesn't detect any connected
>>> devices with default setup. Moreover connecting USB device to controller
>>> that doesn't run properly can cause SoC's watchdog issues.
>>>
>>> A workaround that was successfully tested on multiple devices is to
>>> perform a fake doorbell. This patch adds code for doing this and enables
>>> it on BCM4708 family.
>>>
>>> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
>>> ---
>>> V2: Enable quirk for brcm,bcm4708 machines instead of adding separated
>>> binding
>>> for it. Thanks Rob for your comment on this.
>>
>>
>> Do you think you can pick & push this one? V2 follows Rob's suggestion
>> and he has some DT knowledge for sure, so I guess it should be OK.
>> --
>
>
> Is there some more background information on this?
>
> I don't have any contacts to Broadcom myself, adding the BMC Kernel Feedback
> list to CC.
> Maybe someone over there has an errata, documentation or just general
> feedback.
>
> How was this workaround even figured out? ringing the doorbell for the first
> device doesn't seem like something found by trial and error, especially
> when
> xhci specs state that:
>
> "Software shall not write the Doorbell of an endpoint until after it has
> issued a
> Configure Endpoint Command for the endpoint and received a successful
> Command
> Completion Event."
>
> The whole workaround is a bit intrusive, allocating a fake device, ring a
> doorbell for a
> fake device in the wrong state, clearing off HSE (host system error) which
> should only be set
> when things really go bad, some random usleeps, and possible calling
> xhci_start() twice.
>
> I can't take this as is without some more info.
Hi (ping) Broadcom guys, could you help us with this USB workaround, please?
--
Rafał
^ permalink raw reply
* Re: [PATCH v1 3/3] reset: zx2967: add reset controller driver for ZTE's zx2967 family
From: Shawn Guo @ 2017-01-16 7:44 UTC (permalink / raw)
To: Baoyou Xie
Cc: jun.nie-QSEj5FYQhm4dnm+yROfE0A, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
xie.baoyou-Th6q7B73Y6EnDS1+zs4M5A,
chen.chaokai-Th6q7B73Y6EnDS1+zs4M5A,
wang.qiang01-Th6q7B73Y6EnDS1+zs4M5A
In-Reply-To: <1484377530-30635-3-git-send-email-baoyou.xie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Sat, Jan 14, 2017 at 03:05:30PM +0800, Baoyou Xie wrote:
> This patch adds reset controller driver for ZTE's zx2967 family.
>
> Signed-off-by: Baoyou Xie <baoyou.xie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> drivers/reset/Kconfig | 6 ++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-zx2967.c | 136 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 143 insertions(+)
> create mode 100644 drivers/reset/reset-zx2967.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 172dc96..972d077 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -92,6 +92,12 @@ config RESET_ZYNQ
> help
> This enables the reset controller driver for Xilinx Zynq SoCs.
>
> +config RESET_ZX2967
> + bool "ZX2967 Reset Driver"
> + depends on ARCH_ZX || COMPILE_TEST
> + help
> + This enables the reset controller driver for ZTE zx2967 family.
> +
The config options seem to be sorted alphabetically, so RESET_ZX2967
should be put before RESET_ZYNQ.
> source "drivers/reset/sti/Kconfig"
> source "drivers/reset/hisilicon/Kconfig"
> source "drivers/reset/tegra/Kconfig"
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 13b346e..807b77b 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -14,3 +14,4 @@ obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> obj-$(CONFIG_TI_SYSCON_RESET) += reset-ti-syscon.o
> obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
> obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
> +obj-$(CONFIG_RESET_ZX2967) += reset-zx2967.o
Ditto
> diff --git a/drivers/reset/reset-zx2967.c b/drivers/reset/reset-zx2967.c
> new file mode 100644
> index 0000000..63f9c41
> --- /dev/null
> +++ b/drivers/reset/reset-zx2967.c
> @@ -0,0 +1,136 @@
> +/*
> + * ZTE's zx2967 family thermal sensor driver
> + *
> + * Copyright (C) 2017 ZTE Ltd.
> + *
> + * Author: Baoyou Xie <baoyou.xie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> + *
> + * License terms: GNU General Public License (GPL) version 2
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +
> +struct zx2967_reset {
> + void __iomem *reg_base;
> + spinlock_t lock;
> + struct reset_controller_dev rcdev;
> +};
> +
> +static int zx2967_reset_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct zx2967_reset *reset = NULL;
> + int bank = id / 32;
> + int offset = id % 32;
> + unsigned int reg;
> + unsigned long flags;
> +
> + reset = container_of(rcdev, struct zx2967_reset, rcdev);
> +
> + spin_lock_irqsave(&reset->lock, flags);
> +
> + reg = readl(reset->reg_base + (bank * 4));
> + writel(reg & ~BIT(offset), reset->reg_base + (bank * 4));
> + reg = readl(reset->reg_base + (bank * 4));
> +
> + spin_unlock_irqrestore(&reset->lock, flags);
> +
> + return 0;
> +}
> +
> +static int zx2967_reset_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct zx2967_reset *reset = NULL;
> + int bank = id / 32;
> + int offset = id % 32;
> + unsigned int reg;
> + unsigned long flags;
> +
> + reset = container_of(rcdev, struct zx2967_reset, rcdev);
> +
> + spin_lock_irqsave(&reset->lock, flags);
> +
> + reg = readl(reset->reg_base + (bank * 4));
> + writel(reg | BIT(offset), reset->reg_base + (bank * 4));
> + reg = readl(reset->reg_base + (bank * 4));
> +
> + spin_unlock_irqrestore(&reset->lock, flags);
> +
> + return 0;
> +}
> +
> +static struct reset_control_ops zx2967_reset_ops = {
> + .assert = zx2967_reset_assert,
> + .deassert = zx2967_reset_deassert,
> +};
> +
> +static int zx2967_reset_probe(struct platform_device *pdev)
> +{
> + struct zx2967_reset *reset;
> + struct resource *res;
> +
> + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
> + if (!reset)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + reset->reg_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(reset->reg_base))
> + return PTR_ERR(reset->reg_base);
> +
> + spin_lock_init(&reset->lock);
> +
> + reset->rcdev.owner = THIS_MODULE;
> + reset->rcdev.nr_resets = resource_size(res) * 8;
> + reset->rcdev.ops = &zx2967_reset_ops;
> + reset->rcdev.of_node = pdev->dev.of_node;
> +
> + dev_info(&pdev->dev, "reset controller cnt:%d",
> + reset->rcdev.nr_resets);
> +
> + return reset_controller_register(&reset->rcdev);
Use devm_reset_controller_register(), then we can save the call to
reset_controller_unregister().
Shawn
> +}
> +
> +static int zx2967_reset_remove(struct platform_device *pdev)
> +{
> + struct zx2967_reset *reset = platform_get_drvdata(pdev);
> +
> + reset_controller_unregister(&reset->rcdev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id zx2967_reset_dt_ids[] = {
> + { .compatible = "zte,zx296718-reset", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, zx2967_reset_dt_ids);
> +
> +static struct platform_driver zx2967_reset_driver = {
> + .probe = zx2967_reset_probe,
> + .remove = zx2967_reset_remove,
> + .driver = {
> + .name = "zx2967-reset",
> + .of_match_table = zx2967_reset_dt_ids,
> + },
> +};
> +
> +static int __init zx2967_reset_init(void)
> +{
> + return platform_driver_register(&zx2967_reset_driver);
> +}
> +arch_initcall(zx2967_reset_init);
> +
> +static void __exit zx2967_reset_exit(void)
> +{
> + platform_driver_unregister(&zx2967_reset_driver);
> +}
> +module_exit(zx2967_reset_exit);
> +
> +MODULE_AUTHOR("Baoyou Xie <baoyou.xie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>");
> +MODULE_DESCRIPTION("ZTE zx2967 Reset Controller Driver");
> +MODULE_LICENSE("GPL");
> --
> 2.7.4
>
--
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^ permalink raw reply
* Re: [PATCH v1 3/3] reset: zx2967: add reset controller driver for ZTE's zx2967 family
From: Shawn Guo @ 2017-01-16 7:58 UTC (permalink / raw)
To: Baoyou Xie
Cc: jun.nie, p.zabel, robh+dt, mark.rutland, linux-arm-kernel,
devicetree, linux-kernel, xie.baoyou, chen.chaokai, wang.qiang01
In-Reply-To: <1484377530-30635-3-git-send-email-baoyou.xie@linaro.org>
On Sat, Jan 14, 2017 at 03:05:30PM +0800, Baoyou Xie wrote:
> +static int zx2967_reset_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct zx2967_reset *reset = NULL;
> + int bank = id / 32;
> + int offset = id % 32;
> + unsigned int reg;
u32 is probably better for register value.
> + unsigned long flags;
> +
> + reset = container_of(rcdev, struct zx2967_reset, rcdev);
> +
> + spin_lock_irqsave(&reset->lock, flags);
> +
> + reg = readl(reset->reg_base + (bank * 4));
> + writel(reg & ~BIT(offset), reset->reg_base + (bank * 4));
> + reg = readl(reset->reg_base + (bank * 4));
Is this read on the register is necessary? If so, we should probably
have a comment for that.
> +
> + spin_unlock_irqrestore(&reset->lock, flags);
> +
> + return 0;
> +}
> +
> +static int zx2967_reset_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
Please indent the line right after parentheses.
> +{
> + struct zx2967_reset *reset = NULL;
> + int bank = id / 32;
> + int offset = id % 32;
> + unsigned int reg;
> + unsigned long flags;
> +
> + reset = container_of(rcdev, struct zx2967_reset, rcdev);
> +
> + spin_lock_irqsave(&reset->lock, flags);
> +
> + reg = readl(reset->reg_base + (bank * 4));
> + writel(reg | BIT(offset), reset->reg_base + (bank * 4));
> + reg = readl(reset->reg_base + (bank * 4));
> +
> + spin_unlock_irqrestore(&reset->lock, flags);
> +
> + return 0;
> +}
Only difference between these two functions is only one line. Should we
consolidate them a bit?
Shawn
^ permalink raw reply
* Re: [PATCH] fbdev: ssd1307fb: allow reset-gpios is missing
From: Maxime Ripard @ 2017-01-16 8:02 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, David Airlie, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170115112146.1787-1-icenowy-ymACFijhrKM@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 547 bytes --]
On Sun, Jan 15, 2017 at 07:21:46PM +0800, Icenowy Zheng wrote:
> Currently some SSD1306 OLED modules are sold without a reset pin (only
> VCC, GND, SCK, SDA four pins).
>
> Add support for missing reset-gpios property.
>
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
Unfortunately, a similar patch has been sent a couple of times
already:
https://www.spinics.net/lists/devicetree/msg158330.html
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply
* Re: [PATCH] pcie: ti: Provide patch to force GEN1 PCIe operation
From: Kishon Vijay Abraham I @ 2017-01-16 8:12 UTC (permalink / raw)
To: Lukasz Majewski
Cc: Bjorn Helgaas, Rob Herring, Mark Rutland, Jingoo Han, Joao Pinto,
linux-omap, linux-pci, devicetree, linux-kernel
In-Reply-To: <20170116074927.086418f4@jawa>
Hi Łukasz,
On Monday 16 January 2017 12:19 PM, Lukasz Majewski wrote:
> Hi Kishon,
>
>> Hi,
>>
>> On Sunday 15 January 2017 06:49 PM, Lukasz Majewski wrote:
>>> Some devices (due to e.g. bad PCIe signal integrity) require to run
>>> with forced GEN1 speed on PCIe bus.
>>>
>>> This patch changes the speed explicitly on dra7 based devices when
>>> proper device tree attribute is defined for the PCIe controller.
>>>
>>> Signed-off-by: Lukasz Majewski <lukma@denx.de>
>>
>> Bjorn has already queued a patch to do the same thing
>> https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/log/?h=pci/host-dra7xx
>
> It seems like Bjorn only modifies CAP registers.
The patch also modifies the LNKCTL2 register.
>
> He also needs to change register with 0x080C offset to actually
> ( PCIECTRL_PL_WIDTH_SPEED_CTL )
This bit is used to initiate speed change (after the link is initialized in
GEN1). Resetting the bit (like what you have done here) prevents speed change.
IMO the better way is to set the LNKCTL2 to GEN1 instead of hacking the IP
register.
Thanks
Kishon
>
> Best regards,
> Łukasz
>
>>
>> Thanks
>> Kishon
>>
>>> ---
>>>
>>> Patch applies on newest origin/master
>>> SHA1: f4d3935e4f4884ba80561db5549394afb8eef8f7
>>>
>>> Tested at AM5728
>>>
>>> ---
>>> Documentation/devicetree/bindings/pci/ti-pci.txt | 1 +
>>> drivers/pci/host/pci-dra7xx.c | 23
>>> +++++++++++++++++++++++
>>> drivers/pci/host/pcie-designware.h | 1 + 3 files
>>> changed, 25 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
>>> b/Documentation/devicetree/bindings/pci/ti-pci.txt index
>>> 60e2516..9f97409 100644 ---
>>> a/Documentation/devicetree/bindings/pci/ti-pci.txt +++
>>> b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -25,6 +25,7
>>> @@ PCIe Designware Controller
>>> Optional Property:
>>> - gpios : Should be added if a gpio line is required to drive
>>> PERST# line
>>> + - to,pcie-is-gen1: Indicates that forced gen1 port operation is
>>> needed.
>>> Example:
>>> axi {
>>> diff --git a/drivers/pci/host/pci-dra7xx.c
>>> b/drivers/pci/host/pci-dra7xx.c index 9595fad..eec5fae 100644
>>> --- a/drivers/pci/host/pci-dra7xx.c
>>> +++
>>> b/drivers/pci/host/pci-https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/log/?h=pci/host-dra7xxdra7xx.c
>>> @@ -63,6 +63,13 @@ #define
>>> LINK_UP BIT(16)
>>> #define
>>> DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
>>> +#define PCIECTRL_EP_DBICS_LNK_CAP
>>> 0x007C +#define
>>> MAX_LINK_SPEEDS_MASK GENMASK(3, 0)
>>> +#define MAX_LINK_SPEEDS_GEN1
>>> BIT(0) + +#define
>>> PCIECTRL_PL_WIDTH_SPEED_CTL 0x080C
>>> +#define CFG_DIRECTED_SPEED_CHANGE
>>> BIT(17) + struct dra7xx_pcie { struct pcie_port pp;
>>> void __iomem *base; /* DT
>>> ti_conf */ @@ -270,6 +277,7 @@ static int __init
>>> dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, struct pcie_port
>>> *pp = &dra7xx->pp; struct device *dev = pp->dev;
>>> struct resource *res;
>>> + u32 val;
>>>
>>> pp->irq = platform_get_irq(pdev, 1);
>>> if (pp->irq < 0) {
>>> @@ -296,6 +304,18 @@ static int __init dra7xx_add_pcie_port(struct
>>> dra7xx_pcie *dra7xx, if (!pp->dbi_base)
>>> return -ENOMEM;
>>>
>>> + if (pp->is_gen1) {
>>> + dev_info(dev, "GEN1 forced\n");
>>> +
>>> + val = readl(pp->dbi_base +
>>> PCIECTRL_EP_DBICS_LNK_CAP);
>>> + set_mask_bits(&val, MAX_LINK_SPEEDS_MASK,
>>> MAX_LINK_SPEEDS_GEN1);
>>> + writel(val, pp->dbi_base +
>>> PCIECTRL_EP_DBICS_LNK_CAP); +
>>> + val = readl(pp->dbi_base +
>>> PCIECTRL_PL_WIDTH_SPEED_CTL);
>>> + val &= ~CFG_DIRECTED_SPEED_CHANGE;
>>> + writel(val, pp->dbi_base +
>>> PCIECTRL_PL_WIDTH_SPEED_CTL);
>>> + }
>>> +
>>> ret = dw_pcie_host_init(pp);
>>> if (ret) {
>>> dev_err(dev, "failed to initialize host\n");
>>> @@ -404,6 +424,9 @@ static int __init dra7xx_pcie_probe(struct
>>> platform_device *pdev) goto err_gpio;
>>> }
>>>
>>> + if (of_property_read_bool(np, "ti,pcie-is-gen1"))
>>> + pp->is_gen1 = true;
>>> +
>>> reg = dra7xx_pcie_readl(dra7xx,
>>> PCIECTRL_DRA7XX_CONF_DEVICE_CMD); reg &= ~LTSSM_EN;
>>> dra7xx_pcie_writel(dra7xx,
>>> PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); diff --git
>>> a/drivers/pci/host/pcie-designware.h
>>> b/drivers/pci/host/pcie-designware.h index a567ea2..2fb0b18 100644
>>> --- a/drivers/pci/host/pcie-designware.h +++
>>> b/drivers/pci/host/pcie-designware.h @@ -50,6 +50,7 @@ struct
>>> pcie_port { struct irq_domain *irq_domain;
>>> unsigned long msi_data;
>>> u8 iatu_unroll_enabled;
>>> + u8 is_gen1;
>>> DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
>>> };
>>>
>>>
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
>
^ permalink raw reply
* RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type
From: Jerry Huang @ 2017-01-16 8:15 UTC (permalink / raw)
To: Rob Herring
Cc: mark.rutland@arm.com, balbi@kernel.org,
devicetree@vger.kernel.org, catalin.marinas@arm.com,
linux-usb@vger.kernel.org, will.deacon@arm.com,
linux@armlinux.org.uk, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <CAL_JsqJuifiSQAt-6FgtYYSukAnjzOLuTGEsO-Spn5LxkU-iwQ@mail.gmail.com>
> -----Original Message-----
> From: Jerry Huang
> Sent: Wednesday, January 04, 2017 10:25 AM
> To: 'Rob Herring' <robh@kernel.org>
> Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; linux@armlinux.org.uk; devicetree@vger.kernel.org;
> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
>
> Hi, Rob,
>
> > -----Original Message-----
> > From: Rob Herring [mailto:robh@kernel.org]
> > Sent: Wednesday, January 04, 2017 5:24 AM
> > To: Jerry Huang <jerry.huang@nxp.com>
> > Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> > will.deacon@arm.com; linux@armlinux.org.uk;
> > devicetree@vger.kernel.org; linux-usb@vger.kernel.org;
> > linux-kernel@vger.kernel.org; linux-arm- kernel@lists.infradead.org
> > Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> > type-adjustment" for INCR burst type
> >
> > On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com>
> wrote:
> > > Hi, Rob,
> > >> -----Original Message-----
> > >> From: Rob Herring [mailto:robh@kernel.org]
> > >> Sent: Friday, December 23, 2016 2:45 AM
> > >> To: Jerry Huang <jerry.huang@nxp.com>
> > >> Cc: balbi@kernel.org; mark.rutland@arm.com;
> > >> catalin.marinas@arm.com; will.deacon@arm.com;
> > >> linux@armlinux.org.uk; devicetree@vger.kernel.org;
> > >> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> > >> kernel@lists.infradead.org
> > >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
> > >> incr-burst- type-adjustment" for INCR burst type
> > >>
> > >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> > >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
> > >> > USB3.0
> > >> DWC3.
> > >> > Field "x": 1/0 - undefined length INCR burst type enable or not;
> > >> > Field
> > >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst
> type.
> > >> >
> > >> > While enabling undefined length INCR burst type and INCR16 burst
> > >> > type, get better write performance on NXP Layerscape platform:
> > >> > around 3% improvement (from 364MB/s to 375MB/s).
> > >> >
> > >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> > >> > ---
> > >> > Changes in v3:
> > >> > - add new property for INCR burst in usb node.
> > >> >
> > >> > Documentation/devicetree/bindings/usb/dwc3.txt | 5 +++++
> > >> > arch/arm/boot/dts/ls1021a.dtsi | 1 +
> > >> > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
> > >> > arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 2 ++
> > >> > 4 files changed, 11 insertions(+)
> > >> >
> > >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > index e3e6983..8c405a3 100644
> > >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > @@ -55,6 +55,10 @@ Optional properties:
> > >> > fladj_30mhz_sdbnd signal is invalid or incorrect.
> > >> >
> > >> > - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to
> > >> > be
> > >> reallocated.
> > >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
> > >> GSBUSCFG0
> > >> > + register, undefined length INCR burst type enable and INCRx type.
> > >> > + First field is for undefined length INCR burst type enable or not.
> > >> > + Second field is for largest INCRx type enabled.
> > >>
> > >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> > >> If not, then just use the presence of the property to enable or not.
> > > The first field is one switch.
> > > When it is 1, means undefined length INCR burst type enabled, we can
> > > use
> > any length less than or equal to the largest-enabled burst length of
> > INCR4/8/16/32/64/128/256.
> > > When it is zero, means INCRx burst mode enabled, we can use one
> > > fixed
> > burst length of 1/4/8/16/32/64/128/256 byte.
> > > So, the 2nd field is used if the 1st is 0, we need to select one
> > > largest burst
> > length the USB controller can support.
> > > If we don't want to change the value of this register (use the
> > > default value),
> > we don't need to add this property to usb node.
> >
> > Just make this a single value with 0 meaning INCR and 4/8/16/etc being
> INCRx.
> Maybe, I didn't describe it clearly.
> According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx
> burst mode, 1 means INCR burst mode.
> Regardless of the value of INCRBrstEna [bit0], we need to modify the other
> field bit[1,2,3,4,5,6,7] to one INCR burst type for the platform supported.
> Ad you mentioned, if we just use a single value with 0 meaning INCR and
> 4/8/16/etc being INCRx.
> I understand totally that when it is none-zero, we can use it for INCR burst
> mode.
> Then, when it is 0, how to select the INCRx value?
>
> So, I think we still need two vaue to specify INCRBrstEna and INCRx burst
> type.
Hi, Balbi,
It seems there is no feedback for my comment, so these patches can be accepted?
^ permalink raw reply
* [PATCH v2 0/4] Add support for es8388 on the rock2
From: Romain Perier @ 2017-01-16 8:17 UTC (permalink / raw)
To: Jaroslav Kysela, Takashi Iwai, alsa-devel, Heiko Stuebner
Cc: Mark Rutland, devicetree, Pawel Moll, Ian Campbell,
linux-rockchip, Sjoerd Simons, Rob Herring, Kumar Gala,
Romain Perier
This set of patches adds a machine driver for rockchip boards that use
ES8388 codecs. It also adds slave mode to the es8328 driver that
currently only supported the master mode. Then, it adds the required DT
definitions to link rockchip-i2s to the es8388 analog output.
This work is based on the initial work that was done by Sjoerd Simons
<sjoerd.simons@collabora.co.uk> with some improvements, changes and more
commits.
Changes in v2:
- Fixed wrong use of the data structure i2c_device_id
- Fixed wrong dependencies for SND_SOC_ROCKCHIP_ES8388
Romain Perier (4):
ASoC: es8328-i2c: Add compatible for ES8388
ASoC: es8328: Add support for slave mode
ASoC: rockchip: Add machine driver for ES8388 codecs
arm: dts: Add support for ES8388 to the Radxa Rock 2
Documentation/devicetree/bindings/sound/es8328.txt | 2 +-
.../devicetree/bindings/sound/rockchip-es8388.txt | 28 +++
arch/arm/boot/dts/rk3288-rock2-square.dts | 37 +++
sound/soc/codecs/es8328-i2c.c | 2 +
sound/soc/codecs/es8328.c | 28 ++-
sound/soc/rockchip/Kconfig | 9 +
sound/soc/rockchip/Makefile | 2 +
sound/soc/rockchip/rockchip_es8388.c | 270 +++++++++++++++++++++
8 files changed, 371 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/rockchip-es8388.txt
create mode 100644 sound/soc/rockchip/rockchip_es8388.c
--
2.9.3
^ permalink raw reply
* [PATCH v2 1/4] ASoC: es8328-i2c: Add compatible for ES8388
From: Romain Perier @ 2017-01-16 8:17 UTC (permalink / raw)
To: Jaroslav Kysela, Takashi Iwai, alsa-devel, Heiko Stuebner
Cc: Mark Rutland, devicetree, Pawel Moll, Ian Campbell,
linux-rockchip, Sjoerd Simons, Rob Herring, Kumar Gala,
Romain Perier
In-Reply-To: <20170116081753.13666-1-romain.perier@collabora.com>
This commit adds a compatible string for everest,es8388. This is
an audio codec that is compatible with es8328.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
Changes in v2:
- Fixed wrong use of the i2c_device_id data structure
Documentation/devicetree/bindings/sound/es8328.txt | 2 +-
sound/soc/codecs/es8328-i2c.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/es8328.txt b/Documentation/devicetree/bindings/sound/es8328.txt
index 30ea8a3..33fbf05 100644
--- a/Documentation/devicetree/bindings/sound/es8328.txt
+++ b/Documentation/devicetree/bindings/sound/es8328.txt
@@ -4,7 +4,7 @@ This device supports both I2C and SPI.
Required properties:
- - compatible : "everest,es8328"
+ - compatible : Should be "everest,es8328" or "everest,es8388"
- DVDD-supply : Regulator providing digital core supply voltage 1.8 - 3.6V
- AVDD-supply : Regulator providing analog supply voltage 3.3V
- PVDD-supply : Regulator providing digital IO supply voltage 1.8 - 3.6V
diff --git a/sound/soc/codecs/es8328-i2c.c b/sound/soc/codecs/es8328-i2c.c
index 2d05b5d..318ab28 100644
--- a/sound/soc/codecs/es8328-i2c.c
+++ b/sound/soc/codecs/es8328-i2c.c
@@ -20,12 +20,14 @@
static const struct i2c_device_id es8328_id[] = {
{ "es8328", 0 },
+ { "es8388", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, es8328_id);
static const struct of_device_id es8328_of_match[] = {
{ .compatible = "everest,es8328", },
+ { .compatible = "everest,es8388", },
{ }
};
MODULE_DEVICE_TABLE(of, es8328_of_match);
--
2.9.3
^ permalink raw reply related
* [PATCH v2 2/4] ASoC: es8328: Add support for slave mode
From: Romain Perier @ 2017-01-16 8:17 UTC (permalink / raw)
To: Jaroslav Kysela, Takashi Iwai, alsa-devel, Heiko Stuebner
Cc: Mark Rutland, devicetree, Pawel Moll, Ian Campbell,
linux-rockchip, Sjoerd Simons, Rob Herring, Kumar Gala,
Romain Perier
In-Reply-To: <20170116081753.13666-1-romain.perier@collabora.com>
Currently, the function that changes the DAI format only supports master
mode. Trying to use a slave mode exits the function with -EINVAL and
leave the codec misconfigured. This commits adds support for enabling
the slave mode.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
Changes in v2: None
sound/soc/codecs/es8328.c | 28 ++++++++++++++++++++++------
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/sound/soc/codecs/es8328.c b/sound/soc/codecs/es8328.c
index 37722194..054e123 100644
--- a/sound/soc/codecs/es8328.c
+++ b/sound/soc/codecs/es8328.c
@@ -588,10 +588,18 @@ static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
struct snd_soc_codec *codec = codec_dai->codec;
u8 dac_mode = 0;
u8 adc_mode = 0;
+ bool master;
- /* set master/slave audio interface */
- if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBM_CFM)
- return -EINVAL;
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBM_CFM:
+ master = true;
+ break;
+ case SND_SOC_DAIFMT_CBS_CFS:
+ master = false;
+ break;
+ default:
+ return -EINVAL;
+ }
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -620,9 +628,17 @@ static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
snd_soc_update_bits(codec, ES8328_ADCCONTROL4,
ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode);
- /* Master serial port mode, with BCLK generated automatically */
- snd_soc_update_bits(codec, ES8328_MASTERMODE,
- ES8328_MASTERMODE_MSC, ES8328_MASTERMODE_MSC);
+ if (master) {
+ /* Master serial port mode, with BCLK generated automatically */
+ snd_soc_update_bits(codec, ES8328_MASTERMODE,
+ ES8328_MASTERMODE_MSC,
+ ES8328_MASTERMODE_MSC);
+ } else {
+ /* Slave serial port mode */
+ snd_soc_update_bits(codec, ES8328_MASTERMODE,
+ ES8328_MASTERMODE_MSC,
+ 0);
+ }
return 0;
}
--
2.9.3
^ permalink raw reply related
* [PATCH v2 3/4] ASoC: rockchip: Add machine driver for ES8388 codecs
From: Romain Perier @ 2017-01-16 8:17 UTC (permalink / raw)
To: Jaroslav Kysela, Takashi Iwai, alsa-devel, Heiko Stuebner
Cc: Mark Rutland, devicetree, Pawel Moll, Ian Campbell,
linux-rockchip, Sjoerd Simons, Rob Herring, Kumar Gala,
Romain Perier
In-Reply-To: <20170116081753.13666-1-romain.perier@collabora.com>
The driver is used for Rockchip boards using an audio codec compatible
with ES8388.
This commit is based on the initial work that was done by Sjoerd Simons
<sjoerd.simons@collabora.com> with some improvements.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
Changes in v2:
- Fixed wrong dependencies for SND_SOC_ROCKCHIP_ES8388, SND_SOC_ROCKCHIP_I2S
was selected with unmet direct dependencies
.../devicetree/bindings/sound/rockchip-es8388.txt | 28 +++
sound/soc/rockchip/Kconfig | 9 +
sound/soc/rockchip/Makefile | 2 +
sound/soc/rockchip/rockchip_es8388.c | 270 +++++++++++++++++++++
4 files changed, 309 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/rockchip-es8388.txt
create mode 100644 sound/soc/rockchip/rockchip_es8388.c
diff --git a/Documentation/devicetree/bindings/sound/rockchip-es8388.txt b/Documentation/devicetree/bindings/sound/rockchip-es8388.txt
new file mode 100644
index 0000000..03a0507
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rockchip-es8388.txt
@@ -0,0 +1,28 @@
+ROCKCHIP with ES8388 CODECS
+
+Required properties:
+- compatible: "rockchip,rockchip-audio-es8388"
+- rockchip,model: The user-visible name of this sound complex
+- rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
+ connected to the CODEC
+- rockchip,audio-codec: The phandle of the es8388 audio codec
+
+Optionnal properties:
+- rockchip,hp-en-gpios = The phandle of the GPIO that power up/down the
+ headphone.
+- rockchip,hp-det-gpios = The phandle of the GPIO that detects the headphone
+- pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt
+
+Example:
+
+sound {
+ compatible = "rockchip,rockchip-audio-es8388";
+ rockchip,model = "Analog audio output";
+ rockchip,i2s-controller = <&i2s>;
+ rockchip,audio-codec = <&es8388>;
+ rockchip,hp-en-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
+ rockchip,hp-det-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&headphone>;
+};
+
diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
index c783f9a..b159744 100644
--- a/sound/soc/rockchip/Kconfig
+++ b/sound/soc/rockchip/Kconfig
@@ -42,6 +42,15 @@ config SND_SOC_ROCKCHIP_RT5645
Say Y or M here if you want to add support for SoC audio on Rockchip
boards using the RT5645/RT5650 codec, such as Veyron.
+config SND_SOC_ROCKCHIP_ES8388
+ tristate "ASoC support for Rockchip boards using a ES8388 codec"
+ depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && CLKDEV_LOOKUP
+ select SND_SOC_ROCKCHIP_I2S
+ select SND_SOC_ES8328_I2C
+ help
+ Say Y or M here if you want to add support for SoC audio on Rockchip
+ boards using the ES8388 Codec such as Radxa Rock 2
+
config SND_SOC_RK3399_GRU_SOUND
tristate "ASoC support multiple codecs for Rockchip RK3399 GRU boards"
depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && CLKDEV_LOOKUP && SPI
diff --git a/sound/soc/rockchip/Makefile b/sound/soc/rockchip/Makefile
index 84e5c7c..759db5e 100644
--- a/sound/soc/rockchip/Makefile
+++ b/sound/soc/rockchip/Makefile
@@ -7,8 +7,10 @@ obj-$(CONFIG_SND_SOC_ROCKCHIP_SPDIF) += snd-soc-rockchip-spdif.o
snd-soc-rockchip-max98090-objs := rockchip_max98090.o
snd-soc-rockchip-rt5645-objs := rockchip_rt5645.o
+snd-soc-rockchip-es8388-objs := rockchip_es8388.o
snd-soc-rk3399-gru-sound-objs := rk3399_gru_sound.o
obj-$(CONFIG_SND_SOC_ROCKCHIP_MAX98090) += snd-soc-rockchip-max98090.o
obj-$(CONFIG_SND_SOC_ROCKCHIP_RT5645) += snd-soc-rockchip-rt5645.o
+obj-$(CONFIG_SND_SOC_ROCKCHIP_ES8388) += snd-soc-rockchip-es8388.o
obj-$(CONFIG_SND_SOC_RK3399_GRU_SOUND) += snd-soc-rk3399-gru-sound.o
diff --git a/sound/soc/rockchip/rockchip_es8388.c b/sound/soc/rockchip/rockchip_es8388.c
new file mode 100644
index 0000000..b23ce8e
--- /dev/null
+++ b/sound/soc/rockchip/rockchip_es8388.c
@@ -0,0 +1,270 @@
+/*
+ * Rockchip machine ASoC driver for boards using a ES8388 CODEC.
+ *
+ * Copyright (c) 2016, Collabora Ltd.
+ *
+ * Authors: Sjoerd Simons <sjoerd.simons@collabora.com>,
+ * Romain Perier <romain.perier@collabora.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <sound/core.h>
+#include <sound/jack.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+
+#include "rockchip_i2s.h"
+
+#define DRV_NAME "rockchip-snd-es8388"
+
+struct rk_es8388_drvdata {
+ int gpio_hp_en;
+ int gpio_hp_det;
+};
+
+static int rk_es8388_hp_power(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *k, int event)
+{
+ struct rk_es8388_drvdata *machine = snd_soc_card_get_drvdata(w->dapm->card);
+
+ if (!gpio_is_valid(machine->gpio_hp_en))
+ return 0;
+
+ gpio_set_value_cansleep(machine->gpio_hp_en,
+ SND_SOC_DAPM_EVENT_ON(event));
+
+ return 0;
+}
+
+static struct snd_soc_jack headphone_jack;
+static struct snd_soc_jack_pin headphone_jack_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE
+ },
+};
+
+static const struct snd_soc_dapm_widget rk_dapm_widgets[] = {
+ SND_SOC_DAPM_HP("Headphone", rk_es8388_hp_power),
+};
+
+static const struct snd_soc_dapm_route rk_audio_map[] = {
+ {"Headphone", NULL, "LOUT2"},
+ {"Headphone", NULL, "ROUT2"},
+};
+
+static const struct snd_kcontrol_new rk_mc_controls[] = {
+ SOC_DAPM_PIN_SWITCH("Headphone"),
+};
+
+static int rk_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ int ret = 0;
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ int mclk;
+
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 24000:
+ case 32000:
+ case 48000:
+ case 64000:
+ case 96000:
+ mclk = 12288000;
+ break;
+ case 11025:
+ case 22050:
+ case 44100:
+ case 88200:
+ mclk = 11289600;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk,
+ SND_SOC_CLOCK_OUT);
+
+ if (ret && ret != -ENOTSUPP) {
+ dev_err(codec_dai->dev, "Can't set codec clock %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
+ SND_SOC_CLOCK_IN);
+ if (ret && ret != -ENOTSUPP) {
+ dev_err(codec_dai->dev, "Can't set codec clock %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct snd_soc_jack_gpio rk_hp_jack_gpio = {
+ .name = "Headphone detection",
+ .report = SND_JACK_HEADPHONE,
+ .debounce_time = 150
+};
+
+static int rk_init(struct snd_soc_pcm_runtime *runtime)
+{
+ struct rk_es8388_drvdata *machine = snd_soc_card_get_drvdata(runtime->card);
+
+ /* Enable Headset Jack detection */
+ if (gpio_is_valid(machine->gpio_hp_det)) {
+ snd_soc_card_jack_new(runtime->card, "Headphone Jack",
+ SND_JACK_HEADPHONE, &headphone_jack,
+ headphone_jack_pins,
+ ARRAY_SIZE(headphone_jack_pins));
+ rk_hp_jack_gpio.gpio = machine->gpio_hp_det;
+ snd_soc_jack_add_gpios(&headphone_jack, 1, &rk_hp_jack_gpio);
+ }
+
+ return 0;
+}
+
+static struct snd_soc_ops rk_ops = {
+ .hw_params = rk_hw_params,
+};
+
+static struct snd_soc_dai_link rk_dailink = {
+ .name = "ES8388",
+ .stream_name = "Audio",
+ .codec_dai_name = "es8328-hifi-analog",
+ .init = rk_init,
+ .ops = &rk_ops,
+ /* Set es8388 as slave */
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBS_CFS,
+};
+
+static struct snd_soc_card snd_soc_card_rk = {
+ .name = "I2S-ES8388",
+ .dai_link = &rk_dailink,
+ .num_links = 1,
+ .num_aux_devs = 0,
+ .dapm_widgets = rk_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(rk_dapm_widgets),
+ .dapm_routes = rk_audio_map,
+ .num_dapm_routes = ARRAY_SIZE(rk_audio_map),
+ .controls = rk_mc_controls,
+ .num_controls = ARRAY_SIZE(rk_mc_controls),
+};
+
+static int snd_rk_mc_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+ struct snd_soc_card *card = &snd_soc_card_rk;
+ struct device_node *np = pdev->dev.of_node;
+ struct rk_es8388_drvdata *machine;
+
+ machine = devm_kzalloc(&pdev->dev, sizeof(struct rk_es8388_drvdata),
+ GFP_KERNEL);
+
+ if (!machine)
+ return -ENOMEM;
+
+ card->dev = &pdev->dev;
+
+ machine->gpio_hp_det = of_get_named_gpio(np,
+ "rockchip,hp-det-gpios", 0);
+ if (machine->gpio_hp_det == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ machine->gpio_hp_en = of_get_named_gpio(np,
+ "rockchip,hp-en-gpios", 0);
+ if (machine->gpio_hp_en == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ if (gpio_is_valid(machine->gpio_hp_en)) {
+ ret = devm_gpio_request_one(&pdev->dev, machine->gpio_hp_en,
+ GPIOF_OUT_INIT_LOW, "hp_en");
+ if (ret) {
+ dev_err(card->dev, "cannot get hp_en gpio\n");
+ return ret;
+ }
+ }
+
+ ret = snd_soc_of_parse_card_name(card, "rockchip,model");
+ if (ret) {
+ dev_err(card->dev, "SoC parse card name failed %d\n", ret);
+ return ret;
+ }
+
+ rk_dailink.codec_of_node = of_parse_phandle(np, "rockchip,audio-codec",
+ 0);
+ if (!rk_dailink.codec_of_node) {
+ dev_err(&pdev->dev,
+ "Property 'rockchip,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+
+ rk_dailink.cpu_of_node = of_parse_phandle(np, "rockchip,i2s-controller",
+ 0);
+ if (!rk_dailink.cpu_of_node) {
+ dev_err(&pdev->dev,
+ "Property 'rockchip,i2s-controller' missing or invalid\n");
+ return -EINVAL;
+ }
+
+ rk_dailink.platform_of_node = rk_dailink.cpu_of_node;
+ snd_soc_card_set_drvdata(card, machine);
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Soc register card failed %d\n", ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, card);
+
+ return ret;
+}
+
+static const struct of_device_id rockchip_es8388_of_match[] = {
+ { .compatible = "rockchip,rockchip-audio-es8388", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_es8388_of_match);
+
+static struct platform_driver snd_rk_es8388_driver = {
+ .probe = snd_rk_mc_probe,
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ .pm = &snd_soc_pm_ops,
+ .of_match_table = rockchip_es8388_of_match,
+ },
+};
+
+module_platform_driver(snd_rk_es8388_driver);
+
+MODULE_AUTHOR("Sjoerd Simons");
+MODULE_DESCRIPTION("Rockchip es8388 machine ASoC driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRV_NAME);
--
2.9.3
^ permalink raw reply related
* [PATCH v2 4/4] arm: dts: Add support for ES8388 to the Radxa Rock 2
From: Romain Perier @ 2017-01-16 8:17 UTC (permalink / raw)
To: Jaroslav Kysela, Takashi Iwai, alsa-devel, Heiko Stuebner
Cc: Mark Rutland, devicetree, Pawel Moll, Ian Campbell,
linux-rockchip, Sjoerd Simons, Rob Herring, Kumar Gala,
Romain Perier
In-Reply-To: <20170116081753.13666-1-romain.perier@collabora.com>
This commit adds the DT definition of the es8388 i2c device
found at address 0x10. It also adds the definition for connecting
the Rockchip I2S to the es8388 analog output.
This commit is based on the initial work that was done by Sjoerd Simons
<sjoerd.simons@collabora.com> with some improvements.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
Changes in v2: None
arch/arm/boot/dts/rk3288-rock2-square.dts | 37 +++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts
index 96a2e74..4f9b7d2 100644
--- a/arch/arm/boot/dts/rk3288-rock2-square.dts
+++ b/arch/arm/boot/dts/rk3288-rock2-square.dts
@@ -86,6 +86,17 @@
#sound-dai-cells = <0>;
};
+ sound_es8388 {
+ compatible = "rockchip,rockchip-audio-es8388";
+ rockchip,model = "Analog audio output";
+ rockchip,i2s-controller = <&i2s>;
+ rockchip,audio-codec = <&es8388>;
+ rockchip,hp-en-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
+ rockchip,hp-det-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&headphone>;
+ };
+
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&hym8563>;
@@ -173,10 +184,29 @@
};
};
+&i2c2 {
+ status = "okay";
+
+ es8388: es8388@10 {
+ compatible = "everest,es8388", "everest,es8328";
+ reg = <0x10>;
+ AVDD-supply = <&vcca_codec>;
+ DVDD-supply = <&vcca_codec>;
+ HPVDD-supply = <&vcca_codec>;
+ PVDD-supply = <&vcca_codec>;
+ clocks = <&cru SCLK_I2S0_OUT>;
+ clock-names = "i2s_clk_out";
+ };
+};
+
&i2c5 {
status = "okay";
};
+&i2s {
+ status = "okay";
+};
+
&pinctrl {
ir {
ir_int: ir-int {
@@ -190,6 +220,13 @@
};
};
+ sound {
+ headphone: headphone {
+ rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>,
+ <7 7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
usb {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.9.3
^ permalink raw reply related
* Re: [PATCH 1/4] ASoC: es8328-i2c: Add compatible for ES8388
From: Romain Perier @ 2017-01-16 8:19 UTC (permalink / raw)
To: Heiko Stuebner
Cc: Jaroslav Kysela, Takashi Iwai, alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sjoerd Simons
In-Reply-To: <3724319.rPxRAuBZBQ@phil>
Hi Heiko,
Le 13/01/2017 à 17:43, Heiko Stuebner a écrit :
> Hi Romain,
>
> Am Freitag, 13. Januar 2017, 17:14:49 CET schrieb Romain Perier:
>> This commit adds a compatible string for everest,es8388. This is
>> an audio codec that is compatible with es8328.
>>
>> Signed-off-by: Romain Perier <romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
>> ---
>> Documentation/devicetree/bindings/sound/es8328.txt | 2 +-
>> sound/soc/codecs/es8328-i2c.c | 3 ++-
>> 2 files changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/sound/es8328.txt
>> b/Documentation/devicetree/bindings/sound/es8328.txt index 30ea8a3..33fbf05
>> 100644
>> --- a/Documentation/devicetree/bindings/sound/es8328.txt
>> +++ b/Documentation/devicetree/bindings/sound/es8328.txt
>> @@ -4,7 +4,7 @@ This device supports both I2C and SPI.
>>
>> Required properties:
>>
>> - - compatible : "everest,es8328"
>> + - compatible : Should be "everest,es8328" or "everest,es8388"
>> - DVDD-supply : Regulator providing digital core supply voltage 1.8 -
>> 3.6V - AVDD-supply : Regulator providing analog supply voltage 3.3V
>> - PVDD-supply : Regulator providing digital IO supply voltage 1.8 - 3.6V
>> diff --git a/sound/soc/codecs/es8328-i2c.c b/sound/soc/codecs/es8328-i2c.c
>> index 2d05b5d..09ae67f 100644
>> --- a/sound/soc/codecs/es8328-i2c.c
>> +++ b/sound/soc/codecs/es8328-i2c.c
>> @@ -19,13 +19,14 @@
>> #include "es8328.h"
>>
>> static const struct i2c_device_id es8328_id[] = {
>> - { "es8328", 0 },
>> + { "es8328", "es8388", 0 },
> that looks strange or I'm just blind.
>
> struct i2c_device_id {
> char name[I2C_NAME_SIZE];
> kernel_ulong_t driver_data; /* Data private to the driver */
> };
>
> so shouldn't this be
>
> static const struct i2c_device_id es8328_id[] = {
> { "es8328", 0 },
> + { "es8388", 0 },
>
> instead?
Good catch!
thanks,
Romain
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^ permalink raw reply
* Re: [PATCH v29 9/9] Documentation: dt: chosen properties for arm64 kdump
From: AKASHI Takahiro @ 2017-01-16 8:25 UTC (permalink / raw)
To: Mark Rutland
Cc: catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, james.morse-5wv7dgnIgG8,
geoff-wEGCiKHe2LqWVfeAwA7xHQ,
bauerman-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8,
dyoung-H+wXaHxf7aLQT0dZR+AlfA,
kexec-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170113111756.GC26120@leverpostej>
On Fri, Jan 13, 2017 at 11:17:56AM +0000, Mark Rutland wrote:
> On Fri, Jan 13, 2017 at 06:13:49PM +0900, AKASHI Takahiro wrote:
> > On Thu, Jan 12, 2017 at 03:39:45PM +0000, Mark Rutland wrote:
> > > On Wed, Dec 28, 2016 at 01:37:34PM +0900, AKASHI Takahiro wrote:
> > > > +linux,crashkernel-base
> > > > +linux,crashkernel-size
> > > > +----------------------
> > > > +
> > > > +These properties (currently used on PowerPC and arm64) indicates
> > > > +the base address and the size, respectively, of the reserved memory
> > > > +range for crash dump kernel.
> > >
> > > From this description, it's not clear to me what the (expected)
> > > consumers of this property are, nor what is expected to provide it.
> > >
> > > In previous rounds of review, I had assumed that this was used to
> > > describe a preference to the first kernel as to what region of memory
> > > should be used for a subsequent kdump kernel. Looking around, I'm not
> > > sure if I was correct in that assessment.
> > >
> > > I see that arch/powerpc seems to consume this property to configure
> > > crashk_res, but it also rewrites it based on crashk_res, presumably for
> > > the benefit of userspace. It's not clear to me how on powerpc the kdump
> > > kernel knows its memory range -- is more DT modification done in the
> > > kernel and/or userspace?
> >
> > I don't believe that powerpc will rewrite the property any way.
> > As far as I know from *the source code*, powerpc kernel retrieves
> > the memory range for crash dump kernel from a kernel command line, i.e.
> > crashkernel=, and then exposes it through DT to userspace (assuming
> > kexec-tools).
>
> The rewriting I describe is in export_crashk_values() in
> arch/powerpc/kernel/machine_kexec.c, where the code deletes existing the
> properties, and adds new ones, to the DT exposed to userspace.
>
> So I think we're just quibbling over the definition of "rewrite".
Gotcha
> > > arm64 we should either ensure that /proc/iomem is consistently usable
> > > (and have userspace consistently use it), or we should expose a new file
> > > specifically to expose this information.
> >
> > The thing that I had in my mind when adding this property is that
> > /proc/iomem would be obsolete in the future, then we should have
> > an alternative in hand.
>
> Ok.
>
> My disagreement is with using the DT as a channel to convey information
> from the kernel to userspace.
>
> I'm more than happy for a new file or other mechanism to express this
> information. For example, we could add
> /sys/kernel/kexec_crash_{base,size} or similar.
It may make sense because /sys/kernel/kexec_crash_size already exists,
so why not kexec_crash_base?
My concern, however, is that this kind of interface might prevent us from
allowing multiple regions to be reserved for crash dump kernel in the future.
(There is an assumption that we have only one region at least on arm64 though.)
Thanks,
-Takahiro AKASHI
>
> > > Further, I do not think we need this property. It makes more sense to me
> > > for the preference of a a region to be described to the *first* kernel
> > > using the command line consistently.
> > >
> > > So I think we should drop this property, and not use it on arm64. Please
> > > document this as powerpc only.
> >
> > OK, but if we drop the property from arm64 code, we have no reason
> > to leave its description in this patch.
> > (In fact, there are a few more (undocumented) properties that only ppc
> > uses for kdump.)
>
> I'm happy to drop it, then.
>
> > > > +linux,usable-memory-range
> > > > +-------------------------
> > > > +
> > > > +This property (currently used only on arm64) holds the memory range,
> > > > +the base address and the size, which can be used as system ram on
> > > > +the *current* kernel. Note that, if this property is present, any memory
> > > > +regions under "memory" nodes in DT blob or ones marked as "conventional
> > > > +memory" in EFI memory map should be ignored.
> > >
> > > Could you please replace this with:
> > >
> > > This property (arm64 only) holds a base address and size, describing a
> > > limited region in which memory may be considered available for use by
> > > the kernel. Memory outside of this range is not available for use.
> > >
> > > This property describes a limitation: memory within this range is only
> > > valid when also described through another mechanism that the kernel
> > > would otherwise use to determine available memory (e.g. memory nodes
> > > or the EFI memory map). Valid memory may be sparse within the range.
> >
> > Sure.
>
> Cheers!
>
> Thanks,
> Mark.
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^ permalink raw reply
* Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy
From: Kishon Vijay Abraham I @ 2017-01-16 8:37 UTC (permalink / raw)
To: Jaehoon Chung, linux-pci
Cc: devicetree, linux-kernel, linux-samsung-soc, bhelgaas, robh+dt,
mark.rutland, kgene, krzk, jingoohan1, vivek.gautam, pankaj.dubey,
alim.akhtar, cpgs
In-Reply-To: <20170104123435.30740-3-jh80.chung@samsung.com>
Hi,
On Wednesday 04 January 2017 06:04 PM, Jaehoon Chung wrote:
> This patch supports to use Generic Phy framework for Exynos PCIe phy.
> When Exynos that supported the pcie want to use the PCIe,
> it needs to control the phy resgister.
> But it should be more complex to control in their own PCIe device drivers.
>
> Currently, there is an exynos5440 case to support the pcie.
> So this driver is based on Exynos5440 PCIe.
> In future, will support the Other exynos SoCs likes exynos5433, exynos7.
please re-write the commit message.
>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> ---
> Changelog on V2:
> - Not include the codes relevant to pci-exynos.
> - Remove the getting child node.
>
> drivers/phy/Kconfig | 9 ++
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-exynos-pcie.c | 280 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 290 insertions(+)
> create mode 100644 drivers/phy/phy-exynos-pcie.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index e8eb7f2..2dddef4 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
> This driver provides PHY interface for USB 3.0 DRD controller
> present on Exynos5 SoC series.
>
> +config PHY_EXYNOS_PCIE
> + bool "Exynos PCIe PHY driver"
> + depends on ARCH_EXYNOS && OF
include COMPILE_TEST
> + depends on PCI_EXYNOS
PCI_EXYNOS should depend on PHY_EXYNOS_PCIE if at all required. Or else do away
with this dependency.
> + select GENERIC_PHY
> + help
> + Enable PCIe PHY support for Exynos SoC series.
> + This driver provides PHY interface for Exynos PCIe controller.
> +
> config PHY_PISTACHIO_USB
> tristate "IMG Pistachio USB2.0 PHY driver"
> depends on MACH_PISTACHIO
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 65eb2f4..081aeb4 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
> phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
> phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> +obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
> new file mode 100644
> index 0000000..b57f49b
> --- /dev/null
> +++ b/drivers/phy/phy-exynos-pcie.c
> @@ -0,0 +1,280 @@
> +/*
> + * Samsung EXYNOS SoC series PCIe PHY driver
> + *
> + * Phy provider for PCIe controller on Exynos SoC series
> + *
> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
2017?
> + * Jaehoon Chung <jh80.chung@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +
> +/* PCIe Purple registers */
> +#define PCIE_PHY_GLOBAL_RESET 0x000
> +#define PCIE_PHY_COMMON_RESET 0x004
> +#define PCIE_PHY_CMN_REG 0x008
> +#define PCIE_PHY_MAC_RESET 0x00c
> +#define PCIE_PHY_PLL_LOCKED 0x010
> +#define PCIE_PHY_TRSVREG_RESET 0x020
> +#define PCIE_PHY_TRSV_RESET 0x024
Please use BIT() macro for bit definitions.
> +
> +/* PCIe PHY registers */
> +#define PCIE_PHY_IMPEDANCE 0x004
> +#define PCIE_PHY_PLL_DIV_0 0x008
> +#define PCIE_PHY_PLL_BIAS 0x00c
> +#define PCIE_PHY_DCC_FEEDBACK 0x014
> +#define PCIE_PHY_PLL_DIV_1 0x05c
> +#define PCIE_PHY_COMMON_POWER 0x064
> +#define PCIE_PHY_COMMON_PD_CMN BIT(3)
> +#define PCIE_PHY_TRSV0_EMP_LVL 0x084
> +#define PCIE_PHY_TRSV0_DRV_LVL 0x088
> +#define PCIE_PHY_TRSV0_RXCDR 0x0ac
> +#define PCIE_PHY_TRSV0_POWER 0x0c4
> +#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
> +#define PCIE_PHY_TRSV0_LVCC 0x0dc
> +#define PCIE_PHY_TRSV1_EMP_LVL 0x144
> +#define PCIE_PHY_TRSV1_RXCDR 0x16c
> +#define PCIE_PHY_TRSV1_POWER 0x184
> +#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
> +#define PCIE_PHY_TRSV1_LVCC 0x19c
> +#define PCIE_PHY_TRSV2_EMP_LVL 0x204
> +#define PCIE_PHY_TRSV2_RXCDR 0x22c
> +#define PCIE_PHY_TRSV2_POWER 0x244
> +#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
> +#define PCIE_PHY_TRSV2_LVCC 0x25c
> +#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
> +#define PCIE_PHY_TRSV3_RXCDR 0x2ec
> +#define PCIE_PHY_TRSV3_POWER 0x304
> +#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
> +#define PCIE_PHY_TRSV3_LVCC 0x31c
> +
> +struct exynos_pcie_phy_data {
> + struct phy_ops *ops;
> +};
> +
> +/* For Exynos pcie phy */
> +struct exynos_pcie_phy {
> + const struct exynos_pcie_phy_data *drv_data;
> + void __iomem *phy_base;
> + void __iomem *blk_base; /* For exynos5440 */
> +};
> +
> +static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
> +{
> + writel(val, base + offset);
> +}
> +
> +static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
> +{
> + return readl(base + offset);
> +}
> +
> +/* For Exynos5440 specific functions */
> +static int exynos5440_pcie_phy_init(struct phy *phy)
> +{
> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +
> + /* DCC feedback control off */
> + exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
> +
> + /* set TX/RX impedance */
> + exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
> +
> + /* set 50Mhz PHY clock */
> + exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
> + exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
> +
> + /* set TX Differential output for lane 0 */
> + exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
> +
> + /* set TX Pre-emphasis Level Control for lane 0 to minimum */
> + exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
> +
> + /* set RX clock and data recovery bandwidth */
> + exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
> + exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
> + exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
> + exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
> + exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
> +
> + /* change TX Pre-emphasis Level Control for lanes */
> + exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
> + exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
> + exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
> + exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
> +
> + /* set LVCC */
> + exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
> + exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
> + exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
> + exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
I'm starting to dis-like all this hard-coded hw params. All this should come
from dt. Define a dt binding like this for all hw params..
phy,tx-differential = <val, reg-offset, mask>
and have one API in phy-core to do all these settings.
> +
> + /* pulse for common reset */
> + exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
> + udelay(500);
how did you get this delay value? Adding a comment might help.
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
> +
> + return 0;
> +}
> +
> +static int exynos5440_pcie_phy_power_on(struct phy *phy)
> +{
> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> + u32 val;
> +
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
> + val &= ~PCIE_PHY_COMMON_PD_CMN;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
> + val &= ~PCIE_PHY_TRSV0_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
> + val &= ~PCIE_PHY_TRSV1_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
> + val &= ~PCIE_PHY_TRSV2_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
> + val &= ~PCIE_PHY_TRSV3_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
> +
> + return 0;
> +}
> +
> +static int exynos5440_pcie_phy_power_off(struct phy *phy)
> +{
> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> + u32 val;
> +
> + while (exynos_pcie_phy_readl(ep->phy_base,
> + PCIE_PHY_PLL_LOCKED) == 0) {
> + val = exynos_pcie_phy_readl(ep->blk_base,
> + PCIE_PHY_PLL_LOCKED);
> + dev_info(&phy->dev, "PLL Locked: 0x%x\n", val);
> + }
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
> + val |= PCIE_PHY_COMMON_PD_CMN;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
> + val |= PCIE_PHY_TRSV0_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
> + val |= PCIE_PHY_TRSV1_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
> + val |= PCIE_PHY_TRSV2_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
> + val |= PCIE_PHY_TRSV3_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
> +
> + return 0;
> +}
> +
> +static int exynos5440_pcie_phy_reset(struct phy *phy)
> +{
> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
> + exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
> +
> + return 0;
> +}
> +
> +static struct phy_ops exynos5440_phy_ops = {
> + .init = exynos5440_pcie_phy_init,
> + .power_on = exynos5440_pcie_phy_power_on,
> + .power_off = exynos5440_pcie_phy_power_off,
> + .reset = exynos5440_pcie_phy_reset,
add .owner
> +};
> +
> +static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
> + .ops = &exynos5440_phy_ops,
why do you need a wrapper for phy_ops?
> +};
> +
> +static const struct of_device_id exynos_pcie_phy_match[] = {
> + {
> + .compatible = "samsung,exynos5440-pcie-phy",
> + .data = &exynos5440_pcie_phy_data,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, exynos_pcie_phy_match);
> +
> +static int exynos_pcie_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct exynos_pcie_phy *exynos_phy;
> + struct phy *generic_phy;
> + struct phy_provider *phy_provider;
> + struct resource *res;
> + const struct exynos_pcie_phy_data *drv_data;
> +
> + drv_data = of_device_get_match_data(dev);
> + if (!drv_data)
> + return -ENODEV;
> +
> + exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
> + if (!exynos_phy)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + exynos_phy->phy_base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(exynos_phy->phy_base))
> + return PTR_ERR(exynos_phy->phy_base);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + exynos_phy->blk_base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(exynos_phy->phy_base))
> + return PTR_ERR(exynos_phy->phy_base);
> +
> + exynos_phy->drv_data = drv_data;
> +
> + generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
> + if (IS_ERR(generic_phy)) {
> + dev_err(dev, "failed to create PHY\n");
> + return PTR_ERR(generic_phy);
> + }
> +
> + phy_set_drvdata(generic_phy, exynos_phy);
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static struct platform_driver exynos_pcie_phy_driver = {
> + .probe = exynos_pcie_phy_probe,
> + .driver = {
> + .of_match_table = exynos_pcie_phy_match,
> + .name = "exynos_pcie_phy",
> + }
> +};
> +module_platform_driver(exynos_pcie_phy_driver);
>
Thanks
Kishon
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