* [PATCHv3 RESEND 5/8] ARM: dts: stm32: enable RTC on stm32f429-disco
From: Amelie Delaunay @ 2017-01-16 13:29 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Maxime Coquelin,
Alexandre Torgue
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Amelie Delaunay
In-Reply-To: <1484573388-590-1-git-send-email-amelie.delaunay-qxv4g6HH51o@public.gmane.org>
This patch enables RTC on stm32f429-disco with LSI as clock source because
X2 crystal for LSE is not fitted by default.
Signed-off-by: Amelie Delaunay <amelie.delaunay-qxv4g6HH51o@public.gmane.org>
---
arch/arm/boot/dts/stm32f429-disco.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 7d0415e..9222b9f 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -94,6 +94,12 @@
clock-frequency = <8000000>;
};
+&rtc {
+ assigned-clocks = <&rcc 1 CLK_RTC>;
+ assigned-clock-parents = <&rcc 1 CLK_LSI>;
+ status = "okay";
+};
+
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCHv3 RESEND 4/8] ARM: dts: stm32: Add RTC support for STM32F429 MCU
From: Amelie Delaunay @ 2017-01-16 13:29 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Maxime Coquelin,
Alexandre Torgue
Cc: devicetree, linux-arm-kernel, linux-kernel, Amelie Delaunay
In-Reply-To: <1484573388-590-1-git-send-email-amelie.delaunay@st.com>
This patch adds STM32 RTC bindings for STM32F429.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 557c1f4..f05a9d9 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -125,6 +125,20 @@
status = "disabled";
};
+ rtc: rtc@40002800 {
+ compatible = "st,stm32-rtc";
+ reg = <0x40002800 0x400>;
+ clocks = <&rcc 1 CLK_RTC>;
+ clock-names = "ck_rtc";
+ assigned-clocks = <&rcc 1 CLK_RTC>;
+ assigned-clock-parents = <&rcc 1 CLK_LSE>;
+ interrupt-parent = <&exti>;
+ interrupts = <17 1>;
+ interrupt-names = "alarm";
+ st,syscfg = <&pwrcfg>;
+ status = "disabled";
+ };
+
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
--
1.9.1
^ permalink raw reply related
* [PATCHv3 RESEND 1/8] ARM: dts: stm32: set HSE_RTC clock frequency to 1 MHz on stm32f429
From: Amelie Delaunay @ 2017-01-16 13:29 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Maxime Coquelin,
Alexandre Torgue
Cc: devicetree, linux-arm-kernel, linux-kernel, Amelie Delaunay
This patch set HSE_RTC clock frequency to 1 MHz, as the clock supplied to
the RTC must be 1 MHz.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index e9324a3..557c1f4 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -433,6 +433,8 @@
reg = <0x40023800 0x400>;
clocks = <&clk_hse>, <&clk_i2s_ckin>;
st,syscfg = <&pwrcfg>;
+ assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
+ assigned-clock-rates = <1000000>;
};
dma1: dma-controller@40026000 {
--
1.9.1
^ permalink raw reply related
* [PATCH v1 7/7] ARM: configs: Add STM32 LTDC support in STM32 defconfig
From: Yannick Fertre @ 2017-01-16 13:29 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann
Cc: devicetree, kernel, Philippe Cornu, dri-devel, Mickael Reulier,
Gabriel FERNANDEZ, linux-arm-kernel
In-Reply-To: <1484573344-11609-1-git-send-email-yannick.fertre@st.com>
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
arch/arm/configs/stm32_defconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 29068f5..e3974d9 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -71,3 +71,8 @@ CONFIG_MAGIC_SYSRQ=y
# CONFIG_FTRACE is not set
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
+CONFIG_DRM=y
+CONFIG_DRM_ST=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v1 6/7] ARM: dts: stm32429i-eval: Enable ltdc & simple panel on Eval board
From: Yannick Fertre @ 2017-01-16 13:29 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann
Cc: devicetree, kernel, Philippe Cornu, dri-devel, Mickael Reulier,
Gabriel FERNANDEZ, linux-arm-kernel
In-Reply-To: <1484573344-11609-1-git-send-email-yannick.fertre@st.com>
Enable ltdc & enable am-480272h3tmqw-t01h panel.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
arch/arm/boot/dts/stm32429i-eval.dts | 58 ++++++++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 2de6487..f987ca5 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -88,6 +88,52 @@
clocks = <&rcc 0 30>;
clock-names = "main_clk";
};
+
+ panel_rgb: panel-rgb {
+ compatible = "ampire,am-480272h3tmqw-t01h";
+ status = "okay";
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <<dc_out_rgb>;
+ };
+ };
+ };
+};
+
+&pinctrl {
+ pinctrl_ltdc: ltdc@0 {
+ pins {
+ pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
+ <STM32F429_PI13_FUNC_LCD_VSYNC>,
+ <STM32F429_PI14_FUNC_LCD_CLK>,
+ <STM32F429_PI15_FUNC_LCD_R0>,
+ <STM32F429_PJ0_FUNC_LCD_R1>,
+ <STM32F429_PJ1_FUNC_LCD_R2>,
+ <STM32F429_PJ2_FUNC_LCD_R3>,
+ <STM32F429_PJ3_FUNC_LCD_R4>,
+ <STM32F429_PJ4_FUNC_LCD_R5>,
+ <STM32F429_PJ5_FUNC_LCD_R6>,
+ <STM32F429_PJ6_FUNC_LCD_R7>,
+ <STM32F429_PJ7_FUNC_LCD_G0>,
+ <STM32F429_PJ8_FUNC_LCD_G1>,
+ <STM32F429_PJ9_FUNC_LCD_G2>,
+ <STM32F429_PJ10_FUNC_LCD_G3>,
+ <STM32F429_PJ11_FUNC_LCD_G4>,
+ <STM32F429_PJ12_FUNC_LCD_B0>,
+ <STM32F429_PJ13_FUNC_LCD_B1>,
+ <STM32F429_PJ14_FUNC_LCD_B2>,
+ <STM32F429_PJ15_FUNC_LCD_B3>,
+ <STM32F429_PK0_FUNC_LCD_G5>,
+ <STM32F429_PK1_FUNC_LCD_G6>,
+ <STM32F429_PK2_FUNC_LCD_G7>,
+ <STM32F429_PK3_FUNC_LCD_B4>,
+ <STM32F429_PK4_FUNC_LCD_B5>,
+ <STM32F429_PK5_FUNC_LCD_B6>,
+ <STM32F429_PK6_FUNC_LCD_B7>,
+ <STM32F429_PK7_FUNC_LCD_DE>;
+ slew-rate = <2>;
+ };
+ };
};
&clk_hse {
@@ -123,3 +169,15 @@
pinctrl-names = "default";
status = "okay";
};
+
+<dc_host{
+ status = "okay";
+ pinctrl-0 = <&pinctrl_ltdc>;
+ pinctrl-names = "default";
+
+ port {
+ ltdc_out_rgb: endpoint {
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
+};
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v1 5/7] ARM: dts: stm32f429: Add ltdc support
From: Yannick Fertre @ 2017-01-16 13:29 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann
Cc: devicetree, kernel, Philippe Cornu, dri-devel, Mickael Reulier,
Gabriel FERNANDEZ, linux-arm-kernel
In-Reply-To: <1484573344-11609-1-git-send-email-yannick.fertre@st.com>
Add LTDC (Lcd-tft Display Controller) support.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 25 ++++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 336ee4f..fc43415 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -185,7 +185,7 @@
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
};
- pin-controller {
+ pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
@@ -404,6 +404,29 @@
interrupts = <80>;
clocks = <&rcc 0 38>;
};
+
+ st-display-subsystem {
+ compatible = "st,display-subsystem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dma-ranges;
+
+ ltdc_host: stm32-ltdc@40016800 {
+ compatible = "st,ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc 314>;
+ clocks = <&rcc 1 8>;
+ clock-names = "clk-lcd";
+ status = "disabled";
+
+ port {
+ ltdc_out_rgb: endpoint {
+ };
+ };
+ };
+ };
};
};
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v1 4/7] drm/panel: simple: Add support for Ampire AM-480272H3TMQW-T01H
From: Yannick Fertre @ 2017-01-16 13:29 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann
Cc: devicetree, kernel, Philippe Cornu, dri-devel, Mickael Reulier,
Gabriel FERNANDEZ, linux-arm-kernel
In-Reply-To: <1484573344-11609-1-git-send-email-yannick.fertre@st.com>
Add simple-panel support for the Ampire AM-480272H3TMQW-T01H,
which is a 4.3" WQVGA panel.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
drivers/gpu/drm/panel/panel-simple.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 06aaf79..ee5d2ff 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -386,6 +386,32 @@ static void panel_simple_shutdown(struct device *dev)
panel_simple_disable(&panel->base);
}
+static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
+ .clock = 9000,
+ .hdisplay = 480,
+ .hsync_start = 480 + 2,
+ .hsync_end = 480 + 2 + 41,
+ .htotal = 480 + 2 + 41 + 2,
+ .vdisplay = 272,
+ .vsync_start = 272 + 2,
+ .vsync_end = 272 + 2 + 10,
+ .vtotal = 272 + 2 + 10 + 2,
+ .vrefresh = 60,
+ .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+};
+
+static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
+ .modes = &ire_am_480272h3tmqw_t01h_mode,
+ .num_modes = 1,
+ .bpc = 8,
+
+ .size = {
+ .width = 105,
+ .height = 67,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+};
+
static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
.clock = 33333,
.hdisplay = 800,
@@ -1715,6 +1741,9 @@ static void panel_simple_shutdown(struct device *dev)
static const struct of_device_id platform_of_match[] = {
{
+ .compatible = "ampire,am-480272h3tmqw-t01h",
+ .data = &ire_am_480272h3tmqw_t01h,
+ }, {
.compatible = "ampire,am800480r3tmqwa1h",
.data = &ire_am800480r3tmqwa1h,
}, {
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v1 3/7] dt-bindings: Add Ampire AM-480272H3TMQW-T01H panel
From: Yannick Fertre @ 2017-01-16 13:29 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann
Cc: devicetree, kernel, Philippe Cornu, dri-devel, Mickael Reulier,
Gabriel FERNANDEZ, linux-arm-kernel
In-Reply-To: <1484573344-11609-1-git-send-email-yannick.fertre@st.com>
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
.../bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt | 7 +++++++
1 file changed, 7 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt
diff --git a/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt b/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt
new file mode 100644
index 0000000..f59e3c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt
@@ -0,0 +1,7 @@
+Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "ampire,am-480272h3tmqw-t01h"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v1 2/7] drm/st: Add STM32 LTDC driver
From: Yannick Fertre @ 2017-01-16 13:28 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann
Cc: devicetree, kernel, Philippe Cornu, dri-devel, Mickael Reulier,
Gabriel FERNANDEZ, linux-arm-kernel
In-Reply-To: <1484573344-11609-1-git-send-email-yannick.fertre@st.com>
This patch adds support for the STM32 LCD-TFT display controller.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/st/Kconfig | 14 +
drivers/gpu/drm/st/Makefile | 7 +
drivers/gpu/drm/st/drv.c | 279 +++++++++
drivers/gpu/drm/st/drv.h | 25 +
drivers/gpu/drm/st/ltdc.c | 1438 +++++++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/st/ltdc.h | 20 +
8 files changed, 1786 insertions(+)
create mode 100644 drivers/gpu/drm/st/Kconfig
create mode 100644 drivers/gpu/drm/st/Makefile
create mode 100644 drivers/gpu/drm/st/drv.c
create mode 100644 drivers/gpu/drm/st/drv.h
create mode 100644 drivers/gpu/drm/st/ltdc.c
create mode 100644 drivers/gpu/drm/st/ltdc.h
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 6f3f9e6..d8e6f92 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -237,6 +237,8 @@ source "drivers/gpu/drm/fsl-dcu/Kconfig"
source "drivers/gpu/drm/tegra/Kconfig"
+source "drivers/gpu/drm/st/Kconfig"
+
source "drivers/gpu/drm/panel/Kconfig"
source "drivers/gpu/drm/bridge/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 92de399..7434c09 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -81,6 +81,7 @@ obj-$(CONFIG_DRM_BOCHS) += bochs/
obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio/
obj-$(CONFIG_DRM_MSM) += msm/
obj-$(CONFIG_DRM_TEGRA) += tegra/
+obj-$(CONFIG_DRM_ST) += st/
obj-$(CONFIG_DRM_STI) += sti/
obj-$(CONFIG_DRM_IMX) += imx/
obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
diff --git a/drivers/gpu/drm/st/Kconfig b/drivers/gpu/drm/st/Kconfig
new file mode 100644
index 0000000..fa0ac0c
--- /dev/null
+++ b/drivers/gpu/drm/st/Kconfig
@@ -0,0 +1,14 @@
+config DRM_ST
+ tristate "DRM Support for STMicroelectronics SoC Series"
+ depends on DRM && (ARCH_STM32 || ARCH_MULTIPLATFORM)
+ select DRM_KMS_HELPER
+ select DRM_GEM_CMA_HELPER
+ select DRM_KMS_CMA_HELPER
+ select DRM_PANEL
+ select VIDEOMODE_HELPERS
+ select FB_PROVIDE_GET_FB_UNMAPPED_AREA
+ help
+ Choose this option if you have an ST STMicroelectronics SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called st-drm.
diff --git a/drivers/gpu/drm/st/Makefile b/drivers/gpu/drm/st/Makefile
new file mode 100644
index 0000000..b2a9025
--- /dev/null
+++ b/drivers/gpu/drm/st/Makefile
@@ -0,0 +1,7 @@
+ccflags-y := -Iinclude/drm
+
+st-drm-y := \
+ drv.o \
+ ltdc.o
+
+obj-$(CONFIG_DRM_ST) += st-drm.o
diff --git a/drivers/gpu/drm/st/drv.c b/drivers/gpu/drm/st/drv.c
new file mode 100644
index 0000000..a275019
--- /dev/null
+++ b/drivers/gpu/drm/st/drv.c
@@ -0,0 +1,279 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ * Yannick Fertre <yannick.fertre@st.com>
+ * Fabien Dessenne <fabien.dessenne@st.com>
+ * Mickael Reulier <mickael.reulier@st.com>
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/component.h>
+#include <linux/of_platform.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+
+#include "drv.h"
+#include "ltdc.h"
+
+#define DRIVER_NAME "st"
+#define DRIVER_DESC "STMicroelectronics SoC DRM"
+#define DRIVER_DATE "20170110"
+#define DRIVER_MAJOR 1
+#define DRIVER_MINOR 0
+
+#define ST_MAX_FB_WIDTH 2048
+#define ST_MAX_FB_HEIGHT 2048 /* same as width to handle orientation */
+
+static void st_output_poll_changed(struct drm_device *ddev)
+{
+ struct st_private *priv = ddev->dev_private;
+
+ drm_fbdev_cma_hotplug_event(priv->fbdev);
+}
+
+static const struct drm_mode_config_funcs st_mode_config_funcs = {
+ .fb_create = drm_fb_cma_create,
+ .output_poll_changed = st_output_poll_changed,
+ .atomic_check = drm_atomic_helper_check,
+ .atomic_commit = drm_atomic_helper_commit,
+};
+
+static void st_mode_config_init(struct drm_device *ddev)
+{
+ ddev->mode_config.min_width = 0;
+ ddev->mode_config.min_height = 0;
+
+ /*
+ * set max width and height as default value.
+ * this value would be used to check framebuffer size limitation
+ * at drm_mode_addfb().
+ */
+ ddev->mode_config.max_width = ST_MAX_FB_WIDTH;
+ ddev->mode_config.max_height = ST_MAX_FB_HEIGHT;
+ ddev->mode_config.funcs = &st_mode_config_funcs;
+}
+
+static const struct file_operations st_driver_fops = {
+ .owner = THIS_MODULE,
+ .open = drm_open,
+ .get_unmapped_area = drm_gem_cma_get_unmapped_area,
+ .mmap = drm_gem_cma_mmap,
+ .poll = drm_poll,
+ .read = drm_read,
+ .unlocked_ioctl = drm_ioctl,
+#ifdef CONFIG_COMPAT
+ .compat_ioctl = drm_compat_ioctl,
+#endif
+ .release = drm_release,
+};
+
+static struct drm_driver st_driver = {
+ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
+ DRIVER_ATOMIC,
+ .gem_free_object_unlocked = drm_gem_cma_free_object,
+ .gem_vm_ops = &drm_gem_cma_vm_ops,
+ .dumb_create = drm_gem_cma_dumb_create,
+ .dumb_map_offset = drm_gem_cma_dumb_map_offset,
+ .dumb_destroy = drm_gem_dumb_destroy,
+ .fops = &st_driver_fops,
+
+ .get_vblank_counter = drm_vblank_no_hw_counter,
+ .enable_vblank = ltdc_crtc_enable_vblank,
+ .disable_vblank = ltdc_crtc_disable_vblank,
+
+ .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+ .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+ .gem_prime_export = drm_gem_prime_export,
+ .gem_prime_import = drm_gem_prime_import,
+ .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
+ .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
+ .gem_prime_vmap = drm_gem_cma_prime_vmap,
+ .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
+ .gem_prime_mmap = drm_gem_cma_prime_mmap,
+
+ .name = DRIVER_NAME,
+ .desc = DRIVER_DESC,
+ .date = DRIVER_DATE,
+ .major = DRIVER_MAJOR,
+ .minor = DRIVER_MINOR,
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+ return dev->of_node == data;
+}
+
+static int st_init(struct drm_device *ddev)
+{
+ struct st_private *priv;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ ddev->dev_private = (void *)priv;
+ dev_set_drvdata(ddev->dev, ddev);
+ priv->ddev = ddev;
+
+ drm_mode_config_init(ddev);
+
+ st_mode_config_init(ddev);
+
+ drm_kms_helper_poll_init(ddev);
+
+ return 0;
+}
+
+static void st_cleanup(struct drm_device *ddev)
+{
+ struct st_private *priv = ddev->dev_private;
+
+ if (priv->fbdev) {
+ drm_fbdev_cma_fini(priv->fbdev);
+ priv->fbdev = NULL;
+ }
+
+ drm_kms_helper_poll_fini(ddev);
+ drm_vblank_cleanup(ddev);
+ kfree(priv);
+ ddev->dev_private = NULL;
+}
+
+static int st_bind(struct device *dev)
+{
+ struct drm_device *ddev;
+ struct st_private *priv;
+ struct drm_fbdev_cma *fbdev;
+ int ret;
+
+ ddev = drm_dev_alloc(&st_driver, dev);
+ if (IS_ERR(ddev))
+ return PTR_ERR(ddev);
+
+ ddev->platformdev = to_platform_device(dev);
+
+ ret = st_init(ddev);
+ if (ret)
+ goto err_drm_dev_unref;
+
+ ret = component_bind_all(ddev->dev, ddev);
+ if (ret)
+ goto err_cleanup;
+
+ ret = drm_dev_register(ddev, 0);
+ if (ret)
+ goto err_register;
+
+ drm_mode_config_reset(ddev);
+
+ if (ddev->mode_config.num_connector) {
+ priv = ddev->dev_private;
+ fbdev = drm_fbdev_cma_init(ddev, 16,
+ ddev->mode_config.num_crtc,
+ ddev->mode_config.num_connector);
+ if (IS_ERR(fbdev)) {
+ DRM_DEBUG_DRIVER("Warning: fails to create fbdev\n");
+ fbdev = NULL;
+ }
+ priv->fbdev = fbdev;
+ }
+
+ return 0;
+
+err_register:
+ component_unbind_all(ddev->dev, ddev);
+err_cleanup:
+ st_cleanup(ddev);
+err_drm_dev_unref:
+ drm_dev_unref(ddev);
+ return ret;
+}
+
+static void st_unbind(struct device *dev)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+
+ drm_dev_unregister(ddev);
+ st_cleanup(ddev);
+ drm_dev_unref(ddev);
+}
+
+static const struct component_master_ops st_ops = {
+ .bind = st_bind,
+ .unbind = st_unbind,
+};
+
+static int st_platform_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ struct device_node *child_np;
+ struct component_match *match = NULL;
+
+ dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
+
+ of_platform_populate(node, NULL, NULL, dev);
+
+ child_np = of_get_next_available_child(node, NULL);
+
+ while (child_np) {
+ component_match_add(dev, &match, compare_of, child_np);
+ of_node_put(child_np);
+ child_np = of_get_next_available_child(node, child_np);
+ }
+
+ return component_master_add_with_match(dev, &st_ops, match);
+}
+
+static int st_platform_remove(struct platform_device *pdev)
+{
+ component_master_del(&pdev->dev, &st_ops);
+ of_platform_depopulate(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id st_dt_ids[] = {
+ { .compatible = "st,display-subsystem", },
+ { /* end node */ },
+};
+MODULE_DEVICE_TABLE(of, st_dt_ids);
+
+static struct platform_driver st_platform_driver = {
+ .probe = st_platform_probe,
+ .remove = st_platform_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = st_dt_ids,
+ },
+};
+
+static struct platform_driver * const drivers[] = {
+ <dc_driver,
+ &st_platform_driver,
+};
+
+static int st_drm_init(void)
+{
+ return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
+}
+module_init(st_drm_init);
+
+static void st_drm_exit(void)
+{
+ platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
+}
+module_exit(st_drm_exit);
+
+MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
+MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
+MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
+MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/st/drv.h b/drivers/gpu/drm/st/drv.h
new file mode 100644
index 0000000..d3da1bc
--- /dev/null
+++ b/drivers/gpu/drm/st/drv.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ * Yannick Fertre <yannick.fertre@st.com>
+ * Fabien Dessenne <fabien.dessenne@st.com>
+ * Mickael Reulier <mickael.reulier@st.com>
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#ifndef _DRV_H_
+#define _DRV_H_
+
+#include <drm/drmP.h>
+
+struct st_private {
+ struct ltdc *ltdc;
+ struct drm_device *ddev;
+ struct drm_fbdev_cma *fbdev;
+};
+
+extern struct platform_driver ltdc_driver;
+
+#endif
diff --git a/drivers/gpu/drm/st/ltdc.c b/drivers/gpu/drm/st/ltdc.c
new file mode 100644
index 0000000..46a7ab2
--- /dev/null
+++ b/drivers/gpu/drm/st/ltdc.c
@@ -0,0 +1,1438 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ * Yannick Fertre <yannick.fertre@st.com>
+ * Fabien Dessenne <fabien.dessenne@st.com>
+ * Mickael Reulier <mickael.reulier@st.com>
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_address.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_plane_helper.h>
+
+#include <video/videomode.h>
+
+#include "drv.h"
+#include "ltdc.h"
+
+#define NB_CRTC 1
+#define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
+
+#define MAX_IRQ 4
+
+#define HWVER_10200 0x010200
+#define HWVER_10300 0x010300
+#define HWVER_20101 0x020101
+
+/*
+ * The address of some registers depends on the HW version: such registers have
+ * an extra offset specified with reg_ofs.
+ */
+#define REG_OFS_NONE 0
+#define REG_OFS_4 4 /* Insertion of "Layer Configuration 2" reg */
+#define REG_OFS (ltdc->caps.reg_ofs)
+#define LAY_OFS 0x80 /* Register Offset between 2 layers */
+
+/* Global register offsets */
+#define LTDC_IDR 0x0000 /* IDentification */
+#define LTDC_LCR 0x0004 /* Layer Count */
+#define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */
+#define LTDC_BPCR 0x000C /* Back Porch Configuration */
+#define LTDC_AWCR 0x0010 /* Active Width Configuration */
+#define LTDC_TWCR 0x0014 /* Total Width Configuration */
+#define LTDC_GCR 0x0018 /* Global Control */
+#define LTDC_GC1R 0x001C /* Global Configuration 1 */
+#define LTDC_GC2R 0x0020 /* Global Configuration 2 */
+#define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */
+#define LTDC_GACR 0x0028 /* GAmma Correction */
+#define LTDC_BCCR 0x002C /* Background Color Configuration */
+#define LTDC_IER 0x0034 /* Interrupt Enable */
+#define LTDC_ISR 0x0038 /* Interrupt Status */
+#define LTDC_ICR 0x003C /* Interrupt Clear */
+#define LTDC_LIPCR 0x0040 /* Line Interrupt Position Configuration */
+#define LTDC_CPSR 0x0044 /* Current Position Status */
+#define LTDC_CDSR 0x0048 /* Current Display Status */
+
+/* Layer register offsets */
+#define LTDC_L1LC1R (0x0080) /* L1 Layer Configuration 1 */
+#define LTDC_L1LC2R (0x0084) /* L1 Layer Configuration 2 */
+#define LTDC_L1CR (0x0084 + REG_OFS) /* L1 Control */
+#define LTDC_L1WHPCR (0x0088 + REG_OFS) /* L1 Window Hor Position Config */
+#define LTDC_L1WVPCR (0x008C + REG_OFS) /* L1 Window Vert Position Config */
+#define LTDC_L1CKCR (0x0090 + REG_OFS) /* L1 Color Keying Configuration */
+#define LTDC_L1PFCR (0x0094 + REG_OFS) /* L1 Pixel Format Configuration */
+#define LTDC_L1CACR (0x0098 + REG_OFS) /* L1 Constant Alpha Config */
+#define LTDC_L1DCCR (0x009C + REG_OFS) /* L1 Default Color Configuration */
+#define LTDC_L1BFCR (0x00A0 + REG_OFS) /* L1 Blend Factors Configuration */
+#define LTDC_L1FBBCR (0x00A4 + REG_OFS) /* L1 FrameBuffer Bus Control */
+#define LTDC_L1AFBCR (0x00A8 + REG_OFS) /* L1 AuxFB Control */
+#define LTDC_L1CFBAR (0x00AC + REG_OFS) /* L1 Color FrameBuffer Address */
+#define LTDC_L1CFBLR (0x00B0 + REG_OFS) /* L1 Color FrameBuffer Length */
+#define LTDC_L1CFBLNR (0x00B4 + REG_OFS) /* L1 Color FrameBuffer Line Nb */
+#define LTDC_L1AFBAR (0x00B8 + REG_OFS) /* L1 AuxFB Address */
+#define LTDC_L1AFBLR (0x00BC + REG_OFS) /* L1 AuxFB Length */
+#define LTDC_L1AFBLNR (0x00C0 + REG_OFS) /* L1 AuxFB Line Number */
+#define LTDC_L1CLUTWR (0x00C4 + REG_OFS) /* L1 CLUT Write */
+#define LTDC_L1YS1R (0x00E0 + REG_OFS) /* L1 YCbCr Scale 1 */
+#define LTDC_L1YS2R (0x00E4 + REG_OFS) /* L1 YCbCr Scale 2 */
+
+/* Bit definitions */
+#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
+#define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
+
+#define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
+#define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
+
+#define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
+#define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
+
+#define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
+#define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
+
+#define GCR_LTDCEN BIT(0) /* LTDC ENable */
+#define GCR_DEN BIT(16) /* Dither ENable */
+#define GCR_PCPOL BIT(28) /* Pixel Clock POLarity */
+#define GCR_DEPOL BIT(29) /* Data Enable POLarity */
+#define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity */
+#define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity */
+
+#define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
+#define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
+#define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
+#define GC1R_PBEN BIT(12) /* Precise Blending ENable */
+#define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
+#define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
+#define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
+#define GC1R_BCP BIT(22) /* Background Colour Programmable */
+#define GC1R_BBEN BIT(23) /* Background Blending ENabled */
+#define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
+#define GC1R_TP BIT(25) /* Timing Programmable */
+#define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
+#define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
+#define GC1R_DWP BIT(28) /* Dither Width Programmable */
+#define GC1R_STREN BIT(29) /* STatus Registers ENabled */
+#define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
+
+#define GC2R_EDCA BIT(0) /* External Display Control Ability */
+#define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
+#define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
+#define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
+#define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
+#define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
+
+#define SRCR_IMR BIT(0) /* IMmediate Reload */
+#define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
+
+#define BCCR_BCBLACK 0x00 /* Background Color BLACK */
+#define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */
+#define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */
+#define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */
+#define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */
+
+#define IER_LIE BIT(0) /* Line Interrupt Enable */
+#define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */
+#define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */
+#define IER_RRIE BIT(3) /* Register Reload Interrupt enable */
+
+#define ISR_LIF BIT(0) /* Line Interrupt Flag */
+#define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */
+#define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */
+#define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */
+
+#define LXCR_LEN BIT(0) /* Layer ENable */
+#define LXCR_COLKEN BIT(1) /* Color Keying Enable */
+#define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
+
+#define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
+#define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
+
+#define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
+#define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
+
+#define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
+
+#define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
+
+#define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
+#define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
+
+#define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
+#define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
+
+#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
+
+#define HSPOL_AL 0 /* Horizontal Sync POLarity Active Low */
+#define VSPOL_AL 0 /* Vertical Sync POLarity Active Low */
+#define DEPOL_AL 0 /* Data Enable POLarity Active Low */
+#define PCPOL_IPC 0 /* Input Pixel Clock */
+#define HSPOL_AH GCR_HSPOL /* Horizontal Sync POLarity Active High */
+#define VSPOL_AH GCR_VSPOL /* Vertical Sync POLarity Active High */
+#define DEPOL_AH GCR_DEPOL /* Data Enable POLarity Active High */
+#define PCPOL_IIPC GCR_PCPOL /* Inverted Input Pixel Clock */
+#define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
+#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
+#define BF1_CA 0x400 /* Constant Alpha */
+#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
+#define BF2_1CA 0x005 /* 1 - Constant Alpha */
+
+enum ltdc_pix_fmt {
+ PF_NONE,
+ /* RGB formats */
+ PF_ARGB8888, /* ARGB [32 bits] */
+ PF_RGBA8888, /* RGBA [32 bits] */
+ PF_RGB888, /* RGB [24 bits] */
+ PF_RGB565, /* RGB [16 bits] */
+ PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
+ PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
+ /* Indexed formats */
+ PF_L8, /* Indexed 8 bits [8 bits] */
+ PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
+ PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */
+};
+
+#define NB_PF 8 /* Max nb of HW pixel format */
+
+/* The index gives the encoding of the pixel format for an HW version */
+static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
+ PF_ARGB8888, /* 0x00 */
+ PF_RGB888, /* 0x01 */
+ PF_RGB565, /* 0x02 */
+ PF_ARGB1555, /* 0x03 */
+ PF_ARGB4444, /* 0x04 */
+ PF_L8, /* 0x05 */
+ PF_AL44, /* 0x06 */
+ PF_AL88 /* 0x07 */
+};
+
+static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
+ PF_ARGB8888, /* 0x00 */
+ PF_RGB888, /* 0x01 */
+ PF_RGB565, /* 0x02 */
+ PF_RGBA8888, /* 0x03 */
+ PF_AL44, /* 0x04 */
+ PF_L8, /* 0x05 */
+ PF_ARGB1555, /* 0x06 */
+ PF_ARGB4444 /* 0x07 */
+};
+
+struct ltdc_caps {
+ u32 hw_version; /* hardware version */
+ u32 nb_layers; /* number of supported layers */
+ u32 reg_ofs; /* register offset for applicable regs */
+ u32 bus_width; /* bus width (32 or 64 bits) */
+ const enum ltdc_pix_fmt *pix_fmt_hw; /* supported pixel formats */
+};
+
+struct ltdc {
+ struct device *dev;
+ struct drm_device *ddev;
+ struct regmap *map;
+ struct clk *pixel_clk; /* lcd pixel clock */
+ struct drm_panel *panel;
+ struct drm_pending_vblank_event *pending_event;
+ u32 irq_status;
+ u32 error_status;
+ struct mutex err_lock; /* protecting error_status */
+ struct ltdc_caps caps;
+ u32 clut[256]; /* color look up table */
+};
+
+static struct regmap_config ltdc_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0x400,
+ .fast_io = true,
+};
+
+static inline struct ltdc *crtc_to_ltdc(struct drm_crtc *crtc)
+{
+ return ((struct st_private *)crtc->dev->dev_private)->ltdc;
+}
+
+static inline struct ltdc *plane_to_ltdc(struct drm_plane *plane)
+{
+ return ((struct st_private *)plane->dev->dev_private)->ltdc;
+}
+
+static inline struct ltdc *encoder_to_ltdc(struct drm_encoder *encoder)
+{
+ return ((struct st_private *)encoder->dev->dev_private)->ltdc;
+}
+
+static inline struct ltdc *connector_to_ltdc(struct drm_connector *connector)
+{
+ return ((struct st_private *)connector->dev->dev_private)->ltdc;
+}
+
+static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
+{
+ enum ltdc_pix_fmt pf;
+
+ switch (drm_fmt) {
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XRGB8888:
+ pf = PF_ARGB8888;
+ break;
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_RGBX8888:
+ pf = PF_RGBA8888;
+ break;
+ case DRM_FORMAT_RGB888:
+ pf = PF_RGB888;
+ break;
+ case DRM_FORMAT_RGB565:
+ pf = PF_RGB565;
+ break;
+ case DRM_FORMAT_ARGB1555:
+ case DRM_FORMAT_XRGB1555:
+ pf = PF_ARGB1555;
+ break;
+ case DRM_FORMAT_ARGB4444:
+ case DRM_FORMAT_XRGB4444:
+ pf = PF_ARGB4444;
+ break;
+ case DRM_FORMAT_C8:
+ pf = PF_L8;
+ break;
+ default:
+ pf = PF_NONE;
+ break;
+ /* Note: There are no DRM_FORMAT for AL44 and AL88 */
+ }
+
+ return pf;
+}
+
+static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
+{
+ switch (pf) {
+ case PF_ARGB8888:
+ return DRM_FORMAT_ARGB8888;
+ case PF_RGBA8888:
+ return DRM_FORMAT_RGBA8888;
+ case PF_RGB888:
+ return DRM_FORMAT_RGB888;
+ case PF_RGB565:
+ return DRM_FORMAT_RGB565;
+ case PF_ARGB1555:
+ return DRM_FORMAT_ARGB1555;
+ case PF_ARGB4444:
+ return DRM_FORMAT_ARGB4444;
+ case PF_L8:
+ return DRM_FORMAT_C8;
+ case PF_AL44: /* No DRM support */
+ case PF_AL88: /* No DRM support */
+ case PF_NONE:
+ default:
+ return 0;
+ }
+}
+
+static struct drm_crtc *crtc_from_pipe(struct drm_device *ddev,
+ unsigned int pipe)
+{
+ struct drm_crtc *crtc;
+
+ list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
+ if (pipe == drm_crtc_index(crtc))
+ return crtc;
+ }
+
+ return NULL;
+}
+
+static void ltdc_send_vblank(struct ltdc *ltdc)
+{
+ struct drm_device *ddev = ltdc->ddev;
+ struct drm_crtc *crtc = crtc_from_pipe(ddev, 0);
+ unsigned long flags;
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+
+ drm_crtc_handle_vblank(crtc);
+
+ spin_lock_irqsave(&ddev->event_lock, flags);
+ if (ltdc->pending_event) {
+ drm_crtc_send_vblank_event(crtc, ltdc->pending_event);
+ drm_crtc_vblank_put(crtc);
+ ltdc->pending_event = NULL;
+ }
+
+ spin_unlock_irqrestore(&ddev->event_lock, flags);
+}
+
+static irqreturn_t ltdc_irq_thread(int irq, void *arg)
+{
+ struct ltdc *ltdc = arg;
+
+ /* Line IRQ : trigger the vblank event */
+ if (ltdc->irq_status & ISR_LIF)
+ ltdc_send_vblank(ltdc);
+
+ /* Save FIFO Underrun & Transfer Error status */
+ mutex_lock(<dc->err_lock);
+ if (ltdc->irq_status & ISR_FUIF)
+ ltdc->error_status |= ISR_FUIF;
+ if (ltdc->irq_status & ISR_TERRIF)
+ ltdc->error_status |= ISR_TERRIF;
+ mutex_unlock(<dc->err_lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t ltdc_irq(int irq, void *arg)
+{
+ struct ltdc *ltdc = arg;
+
+ /* Read & Clear the interrupt status */
+ regmap_read(ltdc->map, LTDC_ISR, <dc->irq_status);
+ regmap_write(ltdc->map, LTDC_ICR, ltdc->irq_status);
+
+ return IRQ_WAKE_THREAD;
+}
+
+/*
+ * DRM_CRTC
+ */
+
+static void ltdc_crtc_load_lut(struct drm_crtc *crtc)
+{
+ struct ltdc *ltdc = crtc_to_ltdc(crtc);
+ unsigned int i, lay;
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+
+ for (lay = 0; lay < ltdc->caps.nb_layers; lay++)
+ for (i = 0; i < 256; i++)
+ regmap_write(ltdc->map, LTDC_L1CLUTWR + lay * LAY_OFS,
+ ltdc->clut[i]);
+}
+
+static void ltdc_crtc_enable(struct drm_crtc *crtc)
+{
+ struct ltdc *ltdc = crtc_to_ltdc(crtc);
+
+ DRM_DEBUG_DRIVER("\n");
+
+ if (clk_enable(ltdc->pixel_clk))
+ DRM_ERROR("failed to enable pixel clock\n");
+
+ /* Sets the background color value */
+ regmap_write(ltdc->map, LTDC_BCCR, BCCR_BCBLACK);
+
+ /* Enable IRQ */
+ regmap_update_bits(ltdc->map, LTDC_IER,
+ IER_RRIE | IER_FUIE | IER_TERRIE,
+ IER_RRIE | IER_FUIE | IER_TERRIE);
+
+ /* Immediately commit the planes */
+ regmap_update_bits(ltdc->map, LTDC_SRCR, SRCR_IMR, SRCR_IMR);
+
+ /* Enable LTDC */
+ regmap_update_bits(ltdc->map, LTDC_GCR, GCR_LTDCEN, GCR_LTDCEN);
+
+ drm_crtc_vblank_on(crtc);
+}
+
+static void ltdc_crtc_disable(struct drm_crtc *crtc)
+{
+ struct ltdc *ltdc = crtc_to_ltdc(crtc);
+ unsigned int i;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ if (!crtc->enabled) {
+ DRM_DEBUG_DRIVER("already disabled\n");
+ return;
+ }
+
+ drm_crtc_vblank_off(crtc);
+
+ /* disable LTDC */
+ regmap_update_bits(ltdc->map, LTDC_GCR, GCR_LTDCEN, 0);
+
+ /* disable IRQ */
+ regmap_update_bits(ltdc->map, LTDC_IER,
+ IER_RRIE | IER_FUIE | IER_TERRIE, 0);
+
+ /* disable layers */
+ for (i = 0; i < ltdc->caps.nb_layers; i++)
+ regmap_update_bits(ltdc->map, LTDC_L1CR + i * LAY_OFS,
+ LXCR_LEN, 0);
+
+ /* immediately commit disable of layers before switching off LTDC */
+ regmap_write(ltdc->map, LTDC_SRCR, SRCR_IMR);
+
+ clk_disable(ltdc->pixel_clk);
+
+ if (crtc->state->event && !crtc->state->active) {
+ spin_lock_irq(&crtc->dev->event_lock);
+ drm_crtc_send_vblank_event(crtc, crtc->state->event);
+ spin_unlock_irq(&crtc->dev->event_lock);
+
+ crtc->state->event = NULL;
+ }
+}
+
+static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct ltdc *ltdc = crtc_to_ltdc(crtc);
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+ /* accept the provided drm_display_mode, do not fix it up */
+ return true;
+}
+
+static u32 ltdc_get_paddr(struct drm_framebuffer *fb, int x, int y)
+{
+ struct drm_gem_cma_object *cma_obj;
+ unsigned int pixsize;
+ u32 paddr;
+
+ cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
+ if (IS_ERR(cma_obj)) {
+ DRM_ERROR("Can't get CMA GEM object for fb\n");
+ return 0;
+ }
+
+ pixsize = drm_format_plane_cpp(fb->format->format, 0);
+ paddr = (u32)cma_obj->paddr + fb->offsets[0];
+ paddr += (x * pixsize) + (y * fb->pitches[0]);
+
+ return paddr;
+}
+
+static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
+{
+ struct ltdc *ltdc = crtc_to_ltdc(crtc);
+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ struct videomode vm;
+ int rate = mode->clock * 1000;
+ u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
+ u32 total_width, total_height;
+ u32 val;
+
+ drm_display_mode_to_videomode(mode, &vm);
+
+ dev_dbg(ltdc->dev, "CRTC:%d mode:%s\n", crtc->base.id, mode->name);
+ dev_dbg(ltdc->dev, "Video mode: %dx%d", vm.hactive, vm.vactive);
+ dev_dbg(ltdc->dev, " hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
+ vm.hfront_porch, vm.hback_porch, vm.hsync_len,
+ vm.vfront_porch, vm.vback_porch, vm.vsync_len);
+
+ /* Convert video timings to ltdc timings */
+ hsync = vm.hsync_len - 1;
+ vsync = vm.vsync_len - 1;
+ accum_hbp = hsync + vm.hback_porch;
+ accum_vbp = vsync + vm.vback_porch;
+ accum_act_w = accum_hbp + vm.hactive;
+ accum_act_h = accum_vbp + vm.vactive;
+ total_width = accum_act_w + vm.hfront_porch;
+ total_height = accum_act_h + vm.vfront_porch;
+
+ if (clk_set_rate(ltdc->pixel_clk, rate) < 0) {
+ DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
+ return;
+ }
+
+ /*
+ * Configures the HS, VS, DE and PC polarities.
+ * It would be better to get polarities from panel, but since
+ * these values are quite standard, use hard coded values here
+ */
+ val = HSPOL_AL | VSPOL_AL | DEPOL_AL | PCPOL_IPC;
+ regmap_update_bits(ltdc->map, LTDC_GCR, GCR_HSPOL | GCR_VSPOL |
+ GCR_DEPOL | GCR_PCPOL, val);
+
+ /* Set Synchronization size */
+ val = (hsync << 16) | vsync;
+ regmap_update_bits(ltdc->map, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
+
+ /* Set Accumulated Back porch */
+ val = (accum_hbp << 16) | accum_vbp;
+ regmap_update_bits(ltdc->map, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
+
+ /* Set Accumulated Active Width */
+ val = (accum_act_w << 16) | accum_act_h;
+ regmap_update_bits(ltdc->map, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
+
+ /* Set total width & height */
+ val = (total_width << 16) | total_height;
+ regmap_update_bits(ltdc->map, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW,
+ val);
+}
+
+static void ltdc_crtc_atomic_begin(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ struct ltdc *ltdc = crtc_to_ltdc(crtc);
+ unsigned long flags;
+
+ DRM_DEBUG_ATOMIC("\n");
+
+ if (crtc->state->event) {
+ if (drm_crtc_vblank_get(crtc) != 0)
+ DRM_DEBUG_ATOMIC("Failed do get vblank");
+
+ spin_lock_irqsave(&crtc->dev->event_lock, flags);
+ ltdc->pending_event = crtc->state->event;
+ spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+
+ crtc->state->event = NULL;
+ }
+}
+
+static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ struct ltdc *ltdc = crtc_to_ltdc(crtc);
+ struct drm_pending_vblank_event *event = crtc->state->event;
+
+ DRM_DEBUG_ATOMIC("\n");
+
+ /* Commit shadow registers = update planes at next vblank */
+ regmap_update_bits(ltdc->map, LTDC_SRCR, SRCR_VBR, SRCR_VBR);
+
+ if (event) {
+ crtc->state->event = NULL;
+
+ spin_lock_irq(&crtc->dev->event_lock);
+ if (drm_crtc_vblank_get(crtc) == 0)
+ drm_crtc_arm_vblank_event(crtc, event);
+ else
+ drm_crtc_send_vblank_event(crtc, event);
+ spin_unlock_irq(&crtc->dev->event_lock);
+ }
+}
+
+static struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
+ .load_lut = ltdc_crtc_load_lut,
+ .enable = ltdc_crtc_enable,
+ .disable = ltdc_crtc_disable,
+ .mode_fixup = ltdc_crtc_mode_fixup,
+ .mode_set_nofb = ltdc_crtc_mode_set_nofb,
+ .atomic_begin = ltdc_crtc_atomic_begin,
+ .atomic_flush = ltdc_crtc_atomic_flush,
+};
+
+int ltdc_crtc_enable_vblank(struct drm_device *ddev, unsigned int pipe)
+{
+ struct st_private *priv = ddev->dev_private;
+ struct ltdc *ltdc = priv->ltdc;
+
+ DRM_DEBUG_DRIVER("\n");
+ regmap_update_bits(ltdc->map, LTDC_IER, IER_LIE, IER_LIE);
+
+ return 0;
+}
+
+void ltdc_crtc_disable_vblank(struct drm_device *ddev, unsigned int pipe)
+{
+ struct drm_crtc *crtc = crtc_from_pipe(ddev, pipe);
+ struct st_private *priv = ddev->dev_private;
+ struct ltdc *ltdc = priv->ltdc;
+
+ DRM_DEBUG_DRIVER("\n");
+ regmap_update_bits(ltdc->map, LTDC_IER, IER_LIE, 0);
+
+ if (ltdc->pending_event) {
+ drm_crtc_vblank_put(crtc);
+ ltdc->pending_event = NULL;
+ }
+}
+
+static struct drm_crtc_funcs ltdc_crtc_funcs = {
+ .destroy = drm_crtc_cleanup,
+ .set_config = drm_atomic_helper_set_config,
+ .page_flip = drm_atomic_helper_page_flip,
+ .reset = drm_atomic_helper_crtc_reset,
+ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+};
+
+/*
+ * DRM_PLANE
+ */
+
+static int ltdc_plane_atomic_check(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+ struct ltdc *ltdc = plane_to_ltdc(plane);
+ struct drm_framebuffer *fb = state->fb;
+ u32 src_x, src_y, src_w, src_h;
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+
+ if (!fb)
+ return 0;
+
+ /* convert src_ from 16:16 format */
+ src_x = state->src_x >> 16;
+ src_y = state->src_y >> 16;
+ src_w = state->src_w >> 16;
+ src_h = state->src_h >> 16;
+
+ /* Reject scaling */
+ if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) {
+ DRM_ERROR("Scaling is not supported");
+ return -EINVAL;
+ }
+
+ if (!ltdc_get_paddr(fb, src_x, src_y)) {
+ DRM_ERROR("Cannot get fb address\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static void ltdc_plane_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *oldstate)
+{
+ struct ltdc *ltdc = plane_to_ltdc(plane);
+ struct drm_plane_state *state = plane->state;
+ struct drm_framebuffer *fb = state->fb;
+ u32 lofs = plane->index * LAY_OFS;
+ u32 x0 = state->crtc_x;
+ u32 x1 = state->crtc_x + state->crtc_w - 1;
+ u32 y0 = state->crtc_y;
+ u32 y1 = state->crtc_y + state->crtc_h - 1;
+ u32 src_x, src_y, src_w, src_h;
+ u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr;
+ enum ltdc_pix_fmt pf;
+
+ if (!state->crtc || !fb) {
+ DRM_DEBUG_DRIVER("fb or crtc NULL");
+ return;
+ }
+
+ /* convert src_ from 16:16 format */
+ src_x = state->src_x >> 16;
+ src_y = state->src_y >> 16;
+ src_w = state->src_w >> 16;
+ src_h = state->src_h >> 16;
+
+ DRM_DEBUG_DRIVER(
+ "plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
+ plane->base.id, fb->base.id,
+ src_w, src_h, src_x, src_y,
+ state->crtc_w, state->crtc_h, state->crtc_x, state->crtc_y);
+
+ regmap_read(ltdc->map, LTDC_BPCR, &bpcr);
+ ahbp = (bpcr & BPCR_AHBP) >> 16;
+ avbp = bpcr & BPCR_AVBP;
+
+ /* Configures the horizontal start and stop position */
+ val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
+ regmap_update_bits(ltdc->map, LTDC_L1WHPCR + lofs,
+ LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
+
+ /* Configures the vertical start and stop position */
+ val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
+ regmap_update_bits(ltdc->map, LTDC_L1WVPCR + lofs,
+ LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
+
+ /* Specifies the pixel format */
+ pf = to_ltdc_pixelformat(fb->format->format);
+ for (val = 0; val < NB_PF; val++)
+ if (ltdc->caps.pix_fmt_hw[val] == pf)
+ break;
+
+ if (val == NB_PF) {
+ DRM_ERROR("Pixel format %.4s not supported\n",
+ (char *)&fb->format->format);
+ val = 0; /* set by default ARGB 32 bits */
+ }
+ regmap_update_bits(ltdc->map, LTDC_L1PFCR + lofs,
+ LXPFCR_PF, val);
+
+ /* Configures the color frame buffer pitch in bytes & line length */
+ pitch_in_bytes = fb->pitches[0];
+ line_length = drm_format_plane_cpp(fb->format->format, 0) *
+ (x1 - x0 + 1) + (ltdc->caps.bus_width >> 3) - 1;
+ val = ((pitch_in_bytes << 16) | line_length);
+ regmap_update_bits(ltdc->map, LTDC_L1CFBLR + lofs,
+ LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
+
+ /* Specifies the constant alpha value */
+ val = CONSTA_MAX;
+ regmap_update_bits(ltdc->map, LTDC_L1CACR + lofs,
+ LXCACR_CONSTA, val);
+
+ /* Specifies the blending factors */
+ val = BF1_PAXCA | BF2_1PAXCA;
+ regmap_update_bits(ltdc->map, LTDC_L1BFCR + lofs,
+ LXBFCR_BF2 | LXBFCR_BF1, val);
+
+ /* Configures the frame buffer line number */
+ val = y1 - y0 + 1;
+ regmap_update_bits(ltdc->map, LTDC_L1CFBLNR + lofs,
+ LXCFBLNR_CFBLN, val);
+
+ /* Sets the FB address */
+ paddr = ltdc_get_paddr(fb, src_x, src_y);
+ dev_dbg(ltdc->dev, "fb: phys 0x%08x", paddr);
+ regmap_write(ltdc->map, LTDC_L1CFBAR + lofs, paddr);
+
+ /* Enable layer and CLUT if needed */
+ val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
+ val |= LXCR_LEN;
+ regmap_update_bits(ltdc->map, LTDC_L1CR + lofs,
+ LXCR_LEN | LXCR_CLUTEN, val);
+
+ mutex_lock(<dc->err_lock);
+ if (ltdc->error_status & ISR_FUIF) {
+ dev_dbg(ltdc->dev, "Fifo underrun\n");
+ ltdc->error_status &= ~ISR_FUIF;
+ }
+ if (ltdc->error_status & ISR_TERRIF) {
+ dev_dbg(ltdc->dev, "Transfer error\n");
+ ltdc->error_status &= ~ISR_TERRIF;
+ }
+ mutex_unlock(<dc->err_lock);
+}
+
+static void ltdc_plane_atomic_disable(struct drm_plane *plane,
+ struct drm_plane_state *oldstate)
+{
+ struct ltdc *ltdc = plane_to_ltdc(plane);
+ u32 lofs = plane->index * LAY_OFS;
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+
+ if (!oldstate->crtc) {
+ DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", plane->base.id);
+ return;
+ }
+
+ /* disable layer */
+ regmap_update_bits(ltdc->map, LTDC_L1CR + lofs, LXCR_LEN, 0);
+
+ DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
+ oldstate->crtc->base.id, plane->base.id);
+}
+
+static void ltdc_plane_destroy(struct drm_plane *plane)
+{
+ struct ltdc *ltdc = plane_to_ltdc(plane);
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+
+ drm_plane_helper_disable(plane);
+ drm_plane_cleanup(plane);
+}
+
+static struct drm_plane_funcs ltdc_plane_funcs = {
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .destroy = ltdc_plane_destroy,
+ .set_property = drm_atomic_helper_plane_set_property,
+ .reset = drm_atomic_helper_plane_reset,
+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+};
+
+static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
+ .atomic_check = ltdc_plane_atomic_check,
+ .atomic_update = ltdc_plane_atomic_update,
+ .atomic_disable = ltdc_plane_atomic_disable,
+};
+
+static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
+ enum drm_plane_type type)
+{
+ struct st_private *priv = ddev->dev_private;
+ unsigned long possible_crtcs = CRTC_MASK;
+ struct ltdc *ltdc = priv->ltdc;
+ struct drm_plane *plane;
+ unsigned int i, nb_fmt = 0;
+ u32 formats[NB_PF];
+ u32 drm_fmt;
+ int err;
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+
+ /* Get supported pixel formats */
+ for (i = 0; i < NB_PF; i++) {
+ drm_fmt = to_drm_pixelformat(ltdc->caps.pix_fmt_hw[i]);
+ if (!drm_fmt)
+ continue;
+ formats[nb_fmt++] = drm_fmt;
+ }
+
+ plane = devm_kzalloc(ltdc->dev, sizeof(*plane), GFP_KERNEL);
+ if (!plane)
+ return 0;
+
+ err = drm_universal_plane_init(ddev, plane, possible_crtcs,
+ <dc_plane_funcs, formats, nb_fmt,
+ type, NULL);
+ if (err < 0)
+ return 0;
+
+ drm_plane_helper_add(plane, <dc_plane_helper_funcs);
+
+ DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
+
+ return plane;
+}
+
+static void ltdc_plane_destroy_all(struct ltdc *ltdc)
+{
+ struct drm_plane *plane, *plane_temp;
+
+ list_for_each_entry_safe(plane, plane_temp,
+ <dc->ddev->mode_config.plane_list, head)
+ drm_plane_cleanup(plane);
+}
+
+static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
+{
+ struct st_private *priv = ddev->dev_private;
+ struct ltdc *ltdc = priv->ltdc;
+ struct drm_plane *primary, *overlay;
+ unsigned int i;
+ int res;
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+
+ primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY);
+ if (!primary) {
+ DRM_ERROR("Can not create primary plane\n");
+ return -EINVAL;
+ }
+
+ res = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
+ <dc_crtc_funcs, NULL);
+ if (res) {
+ DRM_ERROR("Can not initialize CRTC\n");
+ goto cleanup;
+ }
+
+ drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs);
+
+ DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
+
+ /* Add planes. Note : the first layer is used by primary plane */
+ for (i = 1; i < ltdc->caps.nb_layers; i++) {
+ overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY);
+ if (!overlay) {
+ res = -ENOMEM;
+ DRM_ERROR("Can not create overlay plane %d\n", i);
+ goto cleanup;
+ }
+ }
+
+ return 0;
+
+cleanup:
+ ltdc_plane_destroy_all(ltdc);
+ return res;
+}
+
+/*
+ * DRM_ENCODER
+ */
+
+static void ltdc_rgb_encoder_enable(struct drm_encoder *encoder)
+{
+ struct ltdc *ltdc = encoder_to_ltdc(encoder);
+
+ DRM_DEBUG_DRIVER("\n");
+ drm_panel_prepare(ltdc->panel);
+ drm_panel_enable(ltdc->panel);
+}
+
+static void ltdc_rgb_encoder_disable(struct drm_encoder *encoder)
+{
+ struct ltdc *ltdc = encoder_to_ltdc(encoder);
+
+ DRM_DEBUG_DRIVER("\n");
+
+ drm_panel_disable(ltdc->panel);
+ drm_panel_unprepare(ltdc->panel);
+}
+
+static const struct drm_encoder_helper_funcs ltdc_rgb_encoder_helper_funcs = {
+ .enable = ltdc_rgb_encoder_enable,
+ .disable = ltdc_rgb_encoder_disable,
+};
+
+static const struct drm_encoder_funcs ltdc_rgb_encoder_funcs = {
+ .destroy = drm_encoder_cleanup,
+};
+
+static struct drm_encoder *ltdc_rgb_encoder_create(struct drm_device *ddev)
+{
+ struct drm_encoder *encoder;
+
+ encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
+ if (!encoder)
+ return NULL;
+
+ encoder->possible_crtcs = CRTC_MASK;
+ encoder->possible_clones = 0; /* No cloning support */
+
+ drm_encoder_init(ddev, encoder, <dc_rgb_encoder_funcs,
+ DRM_MODE_ENCODER_LVDS, NULL);
+
+ drm_encoder_helper_add(encoder, <dc_rgb_encoder_helper_funcs);
+
+ DRM_DEBUG_DRIVER("RGB encoder:%d created\n", encoder->base.id);
+
+ return encoder;
+}
+
+static struct drm_encoder *ltdc_rgb_encoder_find(struct drm_device *ddev)
+{
+ struct drm_encoder *encoder;
+
+ list_for_each_entry(encoder, &ddev->mode_config.encoder_list, head) {
+ if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
+ return encoder;
+ }
+
+ return NULL;
+}
+
+static int ltdc_create_encoders(struct ltdc *ltdc)
+{
+ struct drm_device *ddev = ltdc->ddev;
+ struct drm_encoder *encoder;
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+
+ if (ltdc->panel) {
+ encoder = ltdc_rgb_encoder_create(ddev);
+ if (!encoder)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void ltdc_destroy_encoders(struct ltdc *ltdc)
+{
+ struct drm_encoder *encoder, *encoder_temp;
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+
+ list_for_each_entry_safe(encoder, encoder_temp,
+ <dc->ddev->mode_config.encoder_list, head)
+ drm_encoder_cleanup(encoder);
+}
+
+/*
+ * DRM_CONNECTOR
+ */
+
+static int ltdc_rgb_connector_get_modes(struct drm_connector *connector)
+{
+ struct ltdc *ltdc = connector_to_ltdc(connector);
+ int ret = 0;
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+
+ if (ltdc->panel)
+ ret = drm_panel_get_modes(ltdc->panel);
+
+ return ret < 0 ? 0 : ret;
+}
+
+/* Set a tolerance of 10% on pixel clock */
+#define CLK_TOLERANCE_PCT 10
+
+static enum drm_mode_status
+ltdc_rgb_connector_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ struct ltdc *ltdc = connector_to_ltdc(connector);
+ unsigned long rate = mode->clock * 1000;
+ long rate_min = rate - (rate * CLK_TOLERANCE_PCT) / 100;
+ long rate_max = rate;
+ long rounded_rate;
+
+ rounded_rate = clk_round_rate(ltdc->pixel_clk, rate);
+
+ DRM_DEBUG_DRIVER("Target rate = %ld => available rate = %ld\n",
+ rate, rounded_rate);
+
+ if (rounded_rate < rate_min)
+ return MODE_CLOCK_LOW;
+
+ if (rounded_rate > rate_max)
+ return MODE_CLOCK_HIGH;
+
+ if (!rate)
+ return MODE_BAD;
+
+ return MODE_OK;
+}
+
+static struct drm_connector_helper_funcs ltdc_rgb_connector_helper_funcs = {
+ .get_modes = ltdc_rgb_connector_get_modes,
+ .mode_valid = ltdc_rgb_connector_mode_valid,
+};
+
+static enum drm_connector_status
+ltdc_rgb_connector_detect(struct drm_connector *connector, bool force)
+{
+ struct ltdc *ltdc = connector_to_ltdc(connector);
+ int ret = 0;
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+
+ if (ltdc->panel) {
+ ret = drm_panel_attach(ltdc->panel, connector);
+
+ if (!ret || ret == -EBUSY) {
+ DRM_DEBUG_DRIVER("connector status connected");
+ return connector_status_connected;
+ }
+ }
+
+ DRM_DEBUG_DRIVER("connector status disconnected");
+ return connector_status_disconnected;
+}
+
+static void ltdc_rgb_connector_destroy(struct drm_connector *connector)
+{
+ struct ltdc *ltdc = connector_to_ltdc(connector);
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+
+ if (ltdc->panel)
+ drm_panel_detach(ltdc->panel);
+ drm_connector_cleanup(connector);
+}
+
+static const struct drm_connector_funcs ltdc_rgb_connector_funcs = {
+ .dpms = drm_atomic_helper_connector_dpms,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .detect = ltdc_rgb_connector_detect,
+ .destroy = ltdc_rgb_connector_destroy,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+struct drm_connector *ltdc_rgb_connector_create(struct drm_device *ddev)
+{
+ struct drm_connector *connector;
+ int err;
+
+ connector = devm_kzalloc(ddev->dev, sizeof(*connector), GFP_KERNEL);
+ if (!connector) {
+ DRM_ERROR("Failed to allocate connector\n");
+ return NULL;
+ }
+
+ connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+ err = drm_connector_init(ddev, connector, <dc_rgb_connector_funcs,
+ DRM_MODE_CONNECTOR_LVDS);
+ if (err) {
+ DRM_ERROR("Failed to initialize connector\n");
+ return NULL;
+ }
+
+ drm_connector_helper_add(connector, <dc_rgb_connector_helper_funcs);
+
+ DRM_DEBUG_DRIVER("RGB connector:%d created\n", connector->base.id);
+
+ return connector;
+}
+
+/*
+ * PROBE & BINDING
+ */
+
+static int ltdc_bind(struct device *dev, struct device *master, void *data)
+{
+ struct ltdc *ltdc = dev_get_drvdata(dev);
+ struct drm_device *ddev = data;
+ struct drm_encoder *encoder;
+ struct drm_connector *connector = NULL;
+ struct st_private *priv = ddev->dev_private;
+ struct drm_crtc *crtc;
+ int err;
+
+ dev_dbg(ltdc->dev, "%s drm_device *dev 0x%08x\n",
+ __func__, (u32)(ddev));
+
+ priv->ltdc = ltdc;
+ ltdc->ddev = ddev;
+
+ if (ltdc_create_encoders(ltdc)) {
+ DRM_ERROR("Failed to create encoders\n");
+ return -EINVAL;
+ }
+
+ if (ltdc->panel) {
+ encoder = ltdc_rgb_encoder_find(ddev);
+ if (!encoder) {
+ DRM_ERROR("Failed to find RGB encoder\n");
+ err = -EINVAL;
+ goto err_encoder;
+ }
+
+ connector = ltdc_rgb_connector_create(ddev);
+ if (!connector) {
+ DRM_ERROR("Failed to create RGB connector\n");
+ err = -EINVAL;
+ goto err_encoder;
+ }
+
+ err = drm_mode_connector_attach_encoder(connector, encoder);
+ if (err) {
+ DRM_ERROR("Failed to attach connector to encoder\n");
+ goto err_connector;
+ }
+ }
+
+ crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
+ if (!crtc) {
+ DRM_ERROR("Failed to allocate crtc\n");
+ err = -ENOMEM;
+ goto err_connector;
+ }
+
+ err = ltdc_crtc_init(ddev, crtc);
+ if (err) {
+ DRM_ERROR("Failed to init crtc\n");
+ goto err_connector;
+ }
+
+ err = drm_vblank_init(ddev, NB_CRTC);
+ if (err) {
+ DRM_ERROR("Failed calling drm_vblank_init()\n");
+ goto err_vblank;
+ }
+
+ /* Allow usage of vblank without having to call drm_irq_install */
+ ddev->irq_enabled = 1;
+
+ return 0;
+
+err_vblank:
+ ltdc_plane_destroy_all(ltdc);
+err_connector:
+ ltdc_rgb_connector_destroy(connector);
+err_encoder:
+ ltdc_destroy_encoders(ltdc);
+
+ return err;
+}
+
+static void ltdc_unbind(struct device *dev, struct device *master, void *data)
+{
+ struct ltdc *ltdc = dev_get_drvdata(dev);
+
+ dev_dbg(ltdc->dev, "%s\n", __func__);
+
+ drm_vblank_cleanup(ltdc->ddev);
+ ltdc_plane_destroy_all(ltdc);
+ ltdc_destroy_encoders(ltdc);
+}
+
+static const struct component_ops ltdc_ops = {
+ .bind = ltdc_bind,
+ .unbind = ltdc_unbind,
+};
+
+static int ltdc_get_caps(struct ltdc *ltdc)
+{
+ u32 bus_width_log2, lcr, gc2r;
+
+ /* at least 1 layer must be managed */
+ regmap_read(ltdc->map, LTDC_LCR, &lcr);
+
+ ltdc->caps.nb_layers = max_t(int, lcr, 1);
+
+ /* set data bus width */
+ regmap_read(ltdc->map, LTDC_GC2R, &gc2r);
+ bus_width_log2 = (gc2r & GC2R_BW) >> 4;
+ ltdc->caps.bus_width = 8 << bus_width_log2;
+ regmap_read(ltdc->map, LTDC_IDR, <dc->caps.hw_version);
+
+ switch (ltdc->caps.hw_version) {
+ case HWVER_10200:
+ case HWVER_10300:
+ ltdc->caps.reg_ofs = REG_OFS_NONE;
+ ltdc->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
+ break;
+ case HWVER_20101:
+ ltdc->caps.reg_ofs = REG_OFS_4;
+ ltdc->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int ltdc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct reset_control *rstc;
+ struct resource res;
+ struct ltdc *ltdc;
+ struct drm_panel *panel = NULL;
+ struct device_node *entity, *remote_pt = NULL;
+ void __iomem *regs;
+ int irq, ret, i;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ /*
+ * Parse ltdc node to get remote port and find RGB panel / HDMI slave
+ * If a dsi or a bridge (hdmi, lvds...) is connected to ltdc,
+ * a remote port & RGB panel will not be found.
+ */
+ for_each_endpoint_of_node(np, entity) {
+ if (!of_device_is_available(entity))
+ continue;
+
+ remote_pt = of_graph_get_remote_port_parent(entity);
+ if (remote_pt) {
+ if (!panel) {
+ panel = of_drm_find_panel(remote_pt);
+ of_node_put(remote_pt);
+ if (panel) {
+ dev_dbg(dev, "remote panel %s\n",
+ remote_pt->full_name);
+ } else {
+ dev_dbg(dev, "deferred (panel missing)\n");
+ of_node_put(entity);
+ return -EPROBE_DEFER;
+ }
+ }
+ }
+ }
+
+ ltdc = devm_kzalloc(dev, sizeof(*ltdc), GFP_KERNEL);
+ if (!ltdc) {
+ DRM_ERROR("Cannot allocate memory for ltdc\n");
+ return -ENOMEM;
+ }
+
+ ltdc->dev = dev;
+ ltdc->panel = panel;
+
+ rstc = of_reset_control_get(np, NULL);
+
+ mutex_init(<dc->err_lock);
+
+ ltdc->pixel_clk = devm_clk_get(dev, "clk-lcd");
+ if (IS_ERR(ltdc->pixel_clk)) {
+ DRM_ERROR("Unable to get lcd clock\n");
+ return -ENODEV;
+ }
+
+ if (of_address_to_resource(np, 0, &res)) {
+ DRM_ERROR("Unable to get resource\n");
+ return -ENODEV;
+ }
+
+ regs = devm_ioremap_resource(dev, &res);
+ if (IS_ERR(regs)) {
+ DRM_ERROR("Unable to get ltdc registers\n");
+ return PTR_ERR(regs);
+ }
+
+ ltdc->map = devm_regmap_init_mmio_clk(dev, "clk-lcd", regs,
+ <dc_regmap_config);
+ if (IS_ERR(ltdc->map)) {
+ dev_err(dev, "Couldn't create ltdc register mapping\n");
+ return PTR_ERR(ltdc->map);
+ }
+
+ for (i = 0; i < MAX_IRQ; i++) {
+ irq = platform_get_irq(pdev, i);
+ if (irq < 0)
+ continue;
+
+ ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
+ ltdc_irq_thread, IRQF_ONESHOT,
+ dev_name(dev), ltdc);
+ if (ret) {
+ DRM_ERROR("Failed to register LTDC interrupt\n");
+ return ret;
+ }
+ }
+
+ if (!IS_ERR(rstc))
+ reset_control_deassert(rstc);
+
+ /* Disable interrupts */
+ regmap_update_bits(ltdc->map, LTDC_IER,
+ IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE, 0);
+
+ ret = ltdc_get_caps(ltdc);
+ if (ret) {
+ DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
+ ltdc->caps.hw_version);
+ return ret;
+ }
+
+ DRM_INFO("ltdc hw version 0x%08x - ready\n", ltdc->caps.hw_version);
+
+ platform_set_drvdata(pdev, ltdc);
+
+ ret = component_add(&pdev->dev, <dc_ops);
+ if (ret) {
+ DRM_ERROR("Cannot add component\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ltdc_remove(struct platform_device *pdev)
+{
+ DRM_DEBUG_DRIVER("\n");
+ component_del(&pdev->dev, <dc_ops);
+
+ return 0;
+}
+
+static const struct of_device_id ltdc_of_match[] = {
+ { .compatible = "st,ltdc" },
+ { /* end node */ }
+};
+MODULE_DEVICE_TABLE(of, ltdc_of_match);
+
+struct platform_driver ltdc_driver = {
+ .driver = {
+ .name = "st-ltdc",
+ .of_match_table = ltdc_of_match,
+ },
+ .probe = ltdc_probe,
+ .remove = ltdc_remove,
+};
+
+MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
+MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
+MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
+MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/st/ltdc.h b/drivers/gpu/drm/st/ltdc.h
new file mode 100644
index 0000000..f99142c
--- /dev/null
+++ b/drivers/gpu/drm/st/ltdc.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ * Yannick Fertre <yannick.fertre@st.com>
+ * Fabien Dessenne <fabien.dessenne@st.com>
+ * Mickael Reulier <mickael.reulier@st.com>
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#ifndef _LTDC_H_
+#define _LTDC_H_
+
+#include <drm/drmP.h>
+
+int ltdc_crtc_enable_vblank(struct drm_device *dev, unsigned int pipe);
+void ltdc_crtc_disable_vblank(struct drm_device *dev, unsigned int pipe);
+
+#endif
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v1 1/7] dt-bindings: display: add STM32 LTDC driver
From: Yannick Fertre @ 2017-01-16 13:28 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann
Cc: devicetree, kernel, Philippe Cornu, dri-devel, Mickael Reulier,
Gabriel FERNANDEZ, linux-arm-kernel
In-Reply-To: <1484573344-11609-1-git-send-email-yannick.fertre@st.com>
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
.../devicetree/bindings/display/st,ltdc.txt | 57 ++++++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/st,ltdc.txt
diff --git a/Documentation/devicetree/bindings/display/st,ltdc.txt b/Documentation/devicetree/bindings/display/st,ltdc.txt
new file mode 100644
index 0000000..20e89da
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/st,ltdc.txt
@@ -0,0 +1,57 @@
+* STMicroelectronics STM32 lcd-tft display controller
+
+- st-display-subsystem: Master device for DRM sub-components
+ This device must be the parent of all the sub-components and is responsible
+ of bind them.
+ Required properties:
+ - compatible: "st,display-subsystem"
+ - ranges: to allow probing of subdevices
+
+- ltdc_host: lcd-tft display controller host
+ must be a sub-node of st-display-subsystem
+ Required properties:
+ - compatible: "st,ltdc"
+ - reg: Physical base address of the IP registers and length of memory mapped region.
+ - clocks: from common clock binding: handle hardware IP needed clocks, the
+ number of clocks may depend of the SoC type.
+ See ../clocks/clock-bindings.txt for details.
+ - clock-names: names of the clocks listed in clocks property in the same
+ order.
+ - resets: resets to be used by the device
+ See ../reset/reset.txt for details.
+ - reset-names: names of the resets listed in resets property in the same
+ order.
+ Required nodes:
+ - Video port for RGB output.
+
+Example:
+
+/ {
+ ...
+ soc {
+ ...
+ st-display-subsystem {
+ compatible = "st,display-subsystem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dma-ranges;
+
+ ltdc_host: stm32-ltdc@40016800 {
+ compatible = "st,ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc 314>;
+ clocks = <&rcc 1 8>;
+ clock-names = "clk-lcd";
+ status = "disabled";
+
+ port {
+ ltdc_out_rgb: endpoint {
+ };
+ };
+ };
+ };
+ ...
+ };
+};
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v1 0/7] DRM: add LTDC support for STM32F4
From: Yannick Fertre @ 2017-01-16 13:28 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann
Cc: devicetree, kernel, Philippe Cornu, dri-devel, Mickael Reulier,
Gabriel FERNANDEZ, linux-arm-kernel
The purpose of this set of patches is to add a new driver for stm32f429.
This driver was developed and tested on evaluation board stm32429i.
Stm32f4 is a MCU platform which don't have MMU so the last patches developed
by Benjamin Gaignard regarding "DRM: allow to use mmuless devices"
are necessary.
The board stm429i embeds a Ampire AM-480272H3TMQW-T01H screen.
A new simple panel am-480272h3tmqw-t01h have been added to support it.
Yannick Fertre (7):
dt-bindings: display: add STM32 LTDC driver
drm/st: Add STM32 LTDC driver
dt-bindings: Add Ampire AM-480272H3TMQW-T01H panel
drm/panel: simple: Add support for Ampire AM-480272H3TMQW-T01H
ARM: dts: stm32f429: Add ltdc support
ARM: dts: stm32429i-eval: Enable ltdc & simple panel on Eval board
ARM: configs: Add STM32 LTDC support in STM32 defconfig
.../display/panel/ampire,am-480272h3tmqw-t01h.txt | 7 +
.../devicetree/bindings/display/st,ltdc.txt | 57 +
arch/arm/boot/dts/stm32429i-eval.dts | 58 +
arch/arm/boot/dts/stm32f429.dtsi | 25 +-
arch/arm/configs/stm32_defconfig | 5 +
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/panel/panel-simple.c | 29 +
drivers/gpu/drm/st/Kconfig | 14 +
drivers/gpu/drm/st/Makefile | 7 +
drivers/gpu/drm/st/drv.c | 279 ++++
drivers/gpu/drm/st/drv.h | 25 +
drivers/gpu/drm/st/ltdc.c | 1438 ++++++++++++++++++++
drivers/gpu/drm/st/ltdc.h | 20 +
14 files changed, 1966 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt
create mode 100644 Documentation/devicetree/bindings/display/st,ltdc.txt
create mode 100644 drivers/gpu/drm/st/Kconfig
create mode 100644 drivers/gpu/drm/st/Makefile
create mode 100644 drivers/gpu/drm/st/drv.c
create mode 100644 drivers/gpu/drm/st/drv.h
create mode 100644 drivers/gpu/drm/st/ltdc.c
create mode 100644 drivers/gpu/drm/st/ltdc.h
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* [PATCH 3/3] mtd: spi-nor: add SPI_NOR_DUAL_READ to mx66l51235l
From: Cédric Le Goater @ 2017-01-16 13:27 UTC (permalink / raw)
To: linux-mtd
Cc: Mark Rutland, Boris Brezillon, Robert Lippert, devicetree,
Richard Weinberger, Marek Vasut, Robert Lippert, Rob Herring,
Cédric Le Goater, Cyrille Pitchen, Brian Norris,
David Woodhouse
In-Reply-To: <1484573225-19095-1-git-send-email-clg@kaod.org>
From: Robert Lippert <roblip@gmail.com>
Signed-off-by: Robert Lippert <rlippert@google.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/mtd/spi-nor/spi-nor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index da7cd69d4857..775788f9828a 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -876,7 +876,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) },
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
- { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
+ { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
/* Micron */
--
2.7.4
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related
* [PATCH 2/3] dt-bindings: mtd: add a common label property to all mtd devices
From: Cédric Le Goater @ 2017-01-16 13:27 UTC (permalink / raw)
To: linux-mtd
Cc: Mark Rutland, Boris Brezillon, devicetree, Richard Weinberger,
Marek Vasut, Rob Herring, Cédric Le Goater, Cyrille Pitchen,
Brian Norris, David Woodhouse
In-Reply-To: <1484573225-19095-1-git-send-email-clg@kaod.org>
This can be used to easily identify a specific chip on a system with
multiple chips.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
Documentation/devicetree/bindings/mtd/common.txt | 12 ++++++++++++
1 file changed, 12 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/common.txt
diff --git a/Documentation/devicetree/bindings/mtd/common.txt b/Documentation/devicetree/bindings/mtd/common.txt
new file mode 100644
index 000000000000..a781641a3b00
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/common.txt
@@ -0,0 +1,12 @@
+* Common properties of all MTD devices
+
+Optional properties:
+- label : name to assign to mtd. If omitted, the label is the MTD device name.
+
+Example:
+
+ flash@0 {
+ label = "System-firmware";
+
+ /* flash type specific properties */
+ };
--
2.7.4
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related
* [PATCH 1/3] mtd: name the mtd device with an optional label property
From: Cédric Le Goater @ 2017-01-16 13:27 UTC (permalink / raw)
To: linux-mtd
Cc: Mark Rutland, Boris Brezillon, devicetree, Richard Weinberger,
Marek Vasut, Rob Herring, Cédric Le Goater, Cyrille Pitchen,
Brian Norris, David Woodhouse
In-Reply-To: <1484573225-19095-1-git-send-email-clg@kaod.org>
This can be used to easily identify a specific chip on a system with
multiple chips.
Suggested-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/mtd/mtdcore.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index 052772f7caef..bf61557b599d 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -654,6 +654,13 @@ static int mtd_add_device_partitions(struct mtd_info *mtd,
*/
static void mtd_set_dev_defaults(struct mtd_info *mtd)
{
+ /*
+ * If DT support is enabled and we have a valid of_node pointer, try to
+ * extract the MTD name from the label property.
+ */
+ if (IS_ENABLED(CONFIG_OF) && mtd->dev.of_node)
+ of_property_read_string(mtd->dev.of_node, "label", &mtd->name);
+
if (mtd->dev.parent) {
if (!mtd->owner && mtd->dev.parent->driver)
mtd->owner = mtd->dev.parent->driver->owner;
--
2.7.4
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related
* [PATCH 0/3] Add a "label" property to the mtd device
From: Cédric Le Goater @ 2017-01-16 13:27 UTC (permalink / raw)
To: linux-mtd
Cc: Mark Rutland, Boris Brezillon, devicetree, Richard Weinberger,
Marek Vasut, Rob Herring, Cédric Le Goater, Cyrille Pitchen,
Brian Norris, David Woodhouse
Hello,
Herer are a couple of patches adding a "label" property to the mtd
device, which can be used to identify a specific chip on a system with
multiple chips. This is common on the OpenPower boards, there can be
four chips holding the firmware for the BMC and the firmware for the
host, plus chips with golden images for recovery.
Also included a patch from Robert adding dual data read to the
mx66l51235l chip. It was tested on a Zaius board which has a AST2500
SoC for BMC.
Thanks,
C.
Cédric Le Goater (2):
mtd: name the mtd device with an optional label property
dt-bindings: mtd: add a common label property to all mtd devices
Robert Lippert (1):
mtd: spi-nor: add SPI_NOR_DUAL_READ to mx66l51235l
Documentation/devicetree/bindings/mtd/common.txt | 12 ++++++++++++
drivers/mtd/mtdcore.c | 7 +++++++
drivers/mtd/spi-nor/spi-nor.c | 2 +-
3 files changed, 20 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/mtd/common.txt
--
2.7.4
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply
* [PATCH v1 0/7] DRM: add LTDC support for STM32F4
From: Yannick Fertre @ 2017-01-16 13:27 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann
Cc: devicetree, kernel, Philippe Cornu, dri-devel, Mickael Reulier,
Gabriel FERNANDEZ, linux-arm-kernel
The purpose of this set of patches is to add a new driver for stm32f429.
This driver was developed and tested on evaluation board stm32429i.
Stm32f4 is a MCU platform which don't have MMU so the last patches developed
by Benjamin Gaignard regarding "DRM: allow to use mmuless devices"
are necessary.
The board stm429i embeds a Ampire AM-480272H3TMQW-T01H screen.
A new simple panel am-480272h3tmqw-t01h have been added to support it.
Yannick Fertre (7):
dt-bindings: display: add STM32 LTDC driver
drm/st: Add STM32 LTDC driver
dt-bindings: Add Ampire AM-480272H3TMQW-T01H panel
drm/panel: simple: Add support for Ampire AM-480272H3TMQW-T01H
ARM: dts: stm32f429: Add ltdc support
ARM: dts: stm32429i-eval: Enable ltdc & simple panel on Eval board
ARM: configs: Add STM32 LTDC support in STM32 defconfig
.../display/panel/ampire,am-480272h3tmqw-t01h.txt | 7 +
.../devicetree/bindings/display/st,ltdc.txt | 57 +
arch/arm/boot/dts/stm32429i-eval.dts | 58 +
arch/arm/boot/dts/stm32f429.dtsi | 25 +-
arch/arm/configs/stm32_defconfig | 5 +
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/panel/panel-simple.c | 29 +
drivers/gpu/drm/st/Kconfig | 14 +
drivers/gpu/drm/st/Makefile | 7 +
drivers/gpu/drm/st/drv.c | 279 ++++
drivers/gpu/drm/st/drv.h | 25 +
drivers/gpu/drm/st/ltdc.c | 1438 ++++++++++++++++++++
drivers/gpu/drm/st/ltdc.h | 20 +
14 files changed, 1966 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt
create mode 100644 Documentation/devicetree/bindings/display/st,ltdc.txt
create mode 100644 drivers/gpu/drm/st/Kconfig
create mode 100644 drivers/gpu/drm/st/Makefile
create mode 100644 drivers/gpu/drm/st/drv.c
create mode 100644 drivers/gpu/drm/st/drv.h
create mode 100644 drivers/gpu/drm/st/ltdc.c
create mode 100644 drivers/gpu/drm/st/ltdc.h
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* [PATCH 2/2] ARM: sun8i: dt: Add mali node
From: Maxime Ripard @ 2017-01-16 13:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Carlo Caione, Kevin Hilman,
Heiko Stuebner, Matthias Brugger, Kukjin Kim, Krzysztof Kozlowski,
Javier Martinez Canillas, Linus Walleij, Alexandre Belloni,
Thomas Petazzoni, Boris Brezillon, Antoine Ténart,
Maxime Ripard
In-Reply-To: <20170116132424.7038-1-maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
The A23 and A33 have an ARM Mali 400 GPU. Now that we have a binding, add
it to our DT.
Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index e4991a78ad73..1aaa68ec1880 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -486,6 +486,33 @@
#size-cells = <0>;
};
+ mali: gpu@01c40000 {
+ compatible = "allwinner,sun8i-a23-mali",
+ "allwinner,sun7i-a20-mali",
+ "arm,mali-400", "arm,mali-utgard";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
+
+ assigned-clocks = <&ccu CLK_GPU>;
+ assigned-clock-rates = <408000000>;
+ };
+
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: gpu: Add Mali Utgard bindings
From: Maxime Ripard @ 2017-01-16 13:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Carlo Caione, Kevin Hilman,
Heiko Stuebner, Matthias Brugger, Kukjin Kim, Krzysztof Kozlowski,
Javier Martinez Canillas, Linus Walleij, Alexandre Belloni,
Thomas Petazzoni, Boris Brezillon, Antoine Ténart,
Maxime Ripard
The ARM Mali Utgard GPU family is embedded into a number of SoCs from
Allwinner, Amlogic, Mediatek or Rockchip.
Add a binding for the GPU of that family.
Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
.../devicetree/bindings/gpu/arm,mali-utgard.txt | 76 ++++++++++++++++++++++
1 file changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
new file mode 100644
index 000000000000..df05ba0ec357
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
@@ -0,0 +1,76 @@
+ARM Mali Utgard GPU
+===================
+
+Required properties:
+ - compatible:
+ * "arm,mali-utgard" and one of the following:
+ + "arm,mali-300"
+ + "arm,mali-400"
+ + "arm,mali-450"
+
+ - reg: Physical base address and length of the GPU registers
+
+ - interrupts: an entry for each entry in interrupt-names.
+ See ../interrupt-controller/interrupts.txt for details.
+
+ - interrupt-names:
+ * ppX: Pixel Processor X interrupt (X from 0 to 7)
+ * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
+ * pp: Pixel Processor broadcast interrupt (mali-450 only)
+ * gp: Geometry Processor interrupt
+ * gpmmu: Geometry Processor MMU interrupt
+
+
+Optional properties:
+ - interrupt-names:
+ * pmu: Power Management Unit interrupt, if implemented in hardware
+
+Vendor-specific bindings
+------------------------
+
+The Mali GPU is integrated very differently from one SoC to
+another. In order to accommodate those differences, you have the option
+to specify one more vendor-specific compatible, among:
+
+ - allwinner,sun4i-a10-mali
+ Required properties:
+ * clocks: an entry for each entry in clock-names
+ * clock-names:
+ + bus: bus clock for the GPU
+ + core: clock driving the GPU itself
+ * resets: phandle to the reset line for the GPU
+
+ - allwinner,sun7i-a20-mali
+ Required properties:
+ * clocks: an entry for each entry in clock-names
+ * clock-names:
+ + bus: bus clock for the GPU
+ + core: clock driving the GPU itself
+ * resets: phandle to the reset line for the GPU
+
+Example:
+
+mali: gpu@01c40000 {
+ compatible = "allwinner,sun7i-a20-mali", "arm,mali-400",
+ "arm,mali-utgard";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
+};
+
+
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH] of: Add EXPORT_SYMBOL for of_device_compatible_match
From: Neil Armstrong @ 2017-01-16 13:11 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w
Cc: Neil Armstrong, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Add missing EXPORT_SYMBOL for of_device_compatible_match function.
Fixes: b9c13fe32faa ("dt: Add of_device_compatible_match()")
Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
drivers/of/base.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index d4bea3c..dfbcf17 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -523,6 +523,7 @@ int of_device_compatible_match(struct device_node *device,
return score;
}
+EXPORT_SYMBOL(of_device_compatible_match);
/**
* of_machine_is_compatible - Test root of device tree for a given compatible value
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH v7 0/4] arm64: arch_timer: Add workaround for hisilicon-161601 erratum
From: Ding Tianhong @ 2017-01-16 13:04 UTC (permalink / raw)
To: Marc Zyngier, catalin.marinas, will.deacon, mark.rutland, oss,
devicetree, shawnguo, stuart.yoder, linux-arm-kernel, linuxarm
In-Reply-To: <63e1f4de-f5e8-6a19-2f8f-61b198f6369f@arm.com>
On 2017/1/16 19:29, Marc Zyngier wrote:
> On 16/01/17 10:37, Ding Tianhong wrote:
>>
>>
>> On 2017/1/12 21:24, Ding Tianhong wrote:
>>>
>>> On 2017/1/12 17:11, Marc Zyngier wrote:
>>>> On 12/01/17 04:23, Ding Tianhong wrote:
>>>>> Hi Marc:
>>>>>
>>>>> How about this v7, if any suggestions very grateful.
>>>>
>>>> It's been less than 5 days since you posted this. I'll get to it once I
>>>> finish reviewing all the other patches that are sitting in the queue
>>>> right before yours.
>>>>
>>>
>>> Ok and sorry for the noisy.
>>>
>>
>> Hi Marc：
>>
>> After discussion with the chip developer, we decide to update the erratum id for this bug, so I will resend a new version
>> about this, if you has start to review this v7 patch set, I think I could wait until you have finished yet. :)
>
> This has to be a stable erratum ID, and it won't be changed once the
> workaround is merged (all you'll be able to do is to add new IDs where
> the same fix is applicable). So please post the revised series, and make
> sure that this is the *final* ID update.
>
Yes，the *final* ID will be the stable ID and could be record in CPU erratum doc which could be get from Hisilicon webpage.
The final format for erratum ID is just like:
<Errata-Prefix><SeriesFlag><ModuleID><SerialNum>
Errata-Prefix=1610, SeriesFlag=1, ModuleID=0x, SerialNum=01.
Thanks
Ding
> Thanks,
>
> M.
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v3 06/24] ARM: dts: imx6-sabrelite: add OV5642 and OV5640 camera sensors
From: Philipp Zabel @ 2017-01-16 12:55 UTC (permalink / raw)
To: Steve Longerbeam
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
fabio.estevam-3arQi8VN3Tc, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
mchehab-DgEjT+Ai2ygdnm+yROfE0A, hverkuil-qWit8jRvyhVmR6Xm/wNWPw,
nick-gcszYUEDH4VrovVCs/uTlw, markus.heiser-O6JHGLzbNUwb1SvskN2V4Q,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
bparrot-l0cyMroinI0, geert-Td1EMuHUCqxL1ZNQvxDV9g,
arnd-r2nGTMty4D4, sudipm.mukherjee-Re5JQEeQqe8AvxtiuMwx3w,
minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w,
tiffany.lin-NuS5LvNUpcJWk0Htik3J/w,
jean-christophe.trotin-qxv4g6HH51o,
horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ,
niklas.soderlund+renesas-1zkq55x86MTxsAP9Fp7wbw,
robert.jarzmik-GANU6spQydw, songjun.wu-UWL1GkI3JZL3oGB3hsPCZA,
andrew-ct.chen-NuS5LvNUpcJWk0Htik3J/w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b, Steve Longerbeam
In-Reply-To: <1bb64209-7c58-fe10-3db9-c5b8103eda90-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Fri, 2017-01-13 at 15:04 -0800, Steve Longerbeam wrote:
>
> On 01/13/2017 04:03 AM, Philipp Zabel wrote:
> > Am Freitag, den 06.01.2017, 18:11 -0800 schrieb Steve Longerbeam:
> >> Enables the OV5642 parallel-bus sensor, and the OV5640 MIPI CSI-2 sensor.
> >> Both hang off the same i2c2 bus, so they require different (and non-
> >> default) i2c slave addresses.
> >>
> >> The OV5642 connects to the parallel-bus mux input port on ipu1_csi0_mux.
> >>
> >> The OV5640 connects to the input port on the MIPI CSI-2 receiver on
> >> mipi_csi. It is set to transmit over MIPI virtual channel 1.
> >>
> >> Signed-off-by: Steve Longerbeam <steve_longerbeam-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
> >> ---
> >> arch/arm/boot/dts/imx6dl-sabrelite.dts | 5 ++
> >> arch/arm/boot/dts/imx6q-sabrelite.dts | 6 ++
> >> arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 118 +++++++++++++++++++++++++++++++
> >> 3 files changed, 129 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/imx6dl-sabrelite.dts b/arch/arm/boot/dts/imx6dl-sabrelite.dts
> >> index 0f06ca5..fec2524 100644
> >> --- a/arch/arm/boot/dts/imx6dl-sabrelite.dts
> >> +++ b/arch/arm/boot/dts/imx6dl-sabrelite.dts
[...]
> >> @@ -299,6 +326,52 @@
> >> pinctrl-names = "default";
> >> pinctrl-0 = <&pinctrl_i2c2>;
> >> status = "okay";
> >> +
> >> + ov5640: camera@40 {
> >> + compatible = "ovti,ov5640";
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_ov5640>;
> >> + clocks = <&mipi_xclk>;
> >> + clock-names = "xclk";
> >> + reg = <0x40>;
> >> + xclk = <22000000>;
> > This is superfluous, you can use clk_get_rate on mipi_xclk.
>
> This property is actually there to tell the driver what to set the
> rate to, with clk_set_rate(). So you are saying it would be better
> to set the rate in the device tree and the driver should only
> retrieve the rate?
Yes. Given that this is a reference clock input that is constant on a
given board and never changes during runtime, I think this is the
correct way. The clock will be fixed rate on most boards, I assume.
regards
Philipp
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 03/10] devicetree: bindings: add bindings for ahci-da850
From: Sekhar Nori @ 2017-01-16 12:45 UTC (permalink / raw)
To: Bartosz Golaszewski, David Lechner
Cc: Mark Rutland, linux-devicetree, Kevin Hilman, Michael Turquette,
Russell King, LKML, linux-ide, Rob Herring, Patrick Titiano,
Tejun Heo, arm-soc
In-Reply-To: <CAMpxmJUau9BgAOhacPvcA=NwyE6-yEfDgPdcCZ_JCuNH-amJSA@mail.gmail.com>
On Monday 16 January 2017 03:43 PM, Bartosz Golaszewski wrote:
> 2017-01-13 20:25 GMT+01:00 David Lechner <david@lechnology.com>:
>> On 01/13/2017 06:37 AM, Bartosz Golaszewski wrote:
>>>
>>> Add DT bindings for the TI DA850 AHCI SATA controller.
>>>
>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>>> ---
>>> .../devicetree/bindings/ata/ahci-da850.txt | 21
>>> +++++++++++++++++++++
>>> 1 file changed, 21 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/ata/ahci-da850.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/ata/ahci-da850.txt
>>> b/Documentation/devicetree/bindings/ata/ahci-da850.txt
>>> new file mode 100644
>>> index 0000000..d07c241
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/ata/ahci-da850.txt
>>> @@ -0,0 +1,21 @@
>>> +Device tree binding for the TI DA850 AHCI SATA Controller
>>> +---------------------------------------------------------
>>> +
>>> +Required properties:
>>> + - compatible: must be "ti,da850-ahci"
>>> + - reg: physical base addresses and sizes of the controller's register
>>> areas
>>> + - interrupts: interrupt specifier (refer to the interrupt binding)
>>> +
>>> +Optional properties:
>>> + - clocks: clock specifier (refer to the common clock binding)
>>> + - da850,clk_multiplier: the multiplier for the reference clock needed
>>> + for 1.5GHz PLL output
>>
>>
>> A clock multiplier property seems redundant if you are specifying a clock.
>> It should be possible to get the rate from the clock to determine which
>> multiplier is needed.
>>
>
> I probably should have named it differently. This is not a multiplier
> of a clock derived from PLL0 or PLL1. Instead it's a value set by
> writing to the Port PHY Control Register (MPY bits) of the SATA
> controller that configures the multiplier for the external low-jitter
> clock. On the lcdk the signals (REFCLKP, REFCLKN) are provided by
> CDCM61001 (SATA OSCILLATOR component on the schematics).
>
> I'll find a better name and comment the property accordingly.
>
> FYI: the da850 platform does not use the common clock framework, so I
> don't specify the clock property on the sata node in the device tree.
> Instead I add the clock lookup entry in patch [01/10]. This is
> transparent for AHCI which can get the clock as usual by calling
> clk_get() in ahci_platform_get_resources().
I think David's point is that the SATA_REFCLK needs to be modeled as a
actual clock input to the IP. You should be able to get the rate using
clk_get_rate() and make the MPY bits calculation depending on the
incoming rate.
You should be able to model the clock even when not using common clock
framework.
DA850 AHCI does not use a con_id at the moment (it assumes a single
clock), and that needs to change.
Thanks,
Sekhar
^ permalink raw reply
* Re: [PATCH v2 11/11] drm/rockchip/dsi: fix insufficient bandwidth of some panel
From: John Keeping @ 2017-01-16 12:44 UTC (permalink / raw)
To: Chris Zhong
Cc: mark.rutland, devicetree, heiko, pawel.moll, linux-rockchip, yzq,
linux-kernel, dianders, dri-devel, tfiga, David Airlie, robh+dt,
seanpaul, galak, linux-arm-kernel, Mark Yao
In-Reply-To: <1484561311-494-12-git-send-email-zyw@rock-chips.com>
On Mon, 16 Jan 2017 18:08:31 +0800, Chris Zhong wrote:
> Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
> for some panel, it will cause the screen display is not normal, so
> increases the badnwidth to 1 / 0.8.
>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
>
> ---
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index 9dfa73d..5a973fe 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -501,8 +501,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
>
> mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC);
> if (mpclk) {
> - /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
> - tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
> + /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
> + tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
This and patch 9 are just hacking around the underlying problem in order
to make particular panels work. I'm pretty sure the actual issue is the
use of hardcoded values when configuring the PHY, since the PHY
parameters are specified in clock cycles but the MIPI spec requires
absolute time durations.
I posted a series addressing this a while ago, although I screwed up
sending it so some patches were included twice and since no one
expressed any interest I didn't post a cleaned up version.
The relevant patch is here:
https://patchwork.kernel.org/patch/9340193/
> if (tmp < max_mbps)
> target_mbps = tmp;
> else
^ permalink raw reply
* Re: [PATCH 04/10] sata: hardreset: retry if phys link is down
From: Bartosz Golaszewski @ 2017-01-16 12:28 UTC (permalink / raw)
To: Tejun Heo
Cc: Kevin Hilman, Sekhar Nori, Patrick Titiano, Michael Turquette,
Rob Herring, Mark Rutland, Russell King, David Lechner, linux-ide,
linux-devicetree, LKML, arm-soc
In-Reply-To: <20170115231049.GC14446@mtj.duckdns.org>
2017-01-16 0:10 GMT+01:00 Tejun Heo <tj@kernel.org>:
> Hello,
>
> On Fri, Jan 13, 2017 at 01:37:58PM +0100, Bartosz Golaszewski wrote:
>> The sata core driver already retries to resume the link because some
>> controllers ignore writes to the SControl register.
>>
>> We have a use case with the da850 SATA controller where at PLL0
>> frequency of 456MHz (needed to properly service the LCD controller)
>> the chip becomes unstable and the hardreset operation is ignored the
>> first time 50% of times.
>>
>> Retrying just the resume operation doesn't work - we need to issue
>> the phy/wake reset again to make it work.
>>
>> If ata_phys_link_offline() returns true in sata_link_hardreset(),
>> retry a couple times before really giving up.
>
> I think it'd be better to implement the driver specific implementation
> rather than changing the behavior for everybody.
>
> Thanks.
>
For v2 I created a new ahci-locally exported function:
ahci_do_hardreset() that allows to retrieve the online state of the
link and used it in the da850-specific hardreset implementation.
Hope that'll be good.
Thanks,
Bartosz Golaszewski
^ permalink raw reply
* Re: [PATCH v3 01/24] [media] dt-bindings: Add bindings for i.MX media driver
From: Philipp Zabel @ 2017-01-16 12:09 UTC (permalink / raw)
To: Steve Longerbeam
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
fabio.estevam-3arQi8VN3Tc, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
mchehab-DgEjT+Ai2ygdnm+yROfE0A, hverkuil-qWit8jRvyhVmR6Xm/wNWPw,
nick-gcszYUEDH4VrovVCs/uTlw, markus.heiser-O6JHGLzbNUwb1SvskN2V4Q,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
bparrot-l0cyMroinI0, geert-Td1EMuHUCqxL1ZNQvxDV9g,
arnd-r2nGTMty4D4, sudipm.mukherjee-Re5JQEeQqe8AvxtiuMwx3w,
minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w,
tiffany.lin-NuS5LvNUpcJWk0Htik3J/w,
jean-christophe.trotin-qxv4g6HH51o,
horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ,
niklas.soderlund+renesas-1zkq55x86MTxsAP9Fp7wbw,
robert.jarzmik-GANU6spQydw, songjun.wu-UWL1GkI3JZL3oGB3hsPCZA,
andrew-ct.chen-NuS5LvNUpcJWk0Htik3J/w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b, Steve Longerbeam
In-Reply-To: <e609fd03-a546-330c-ec89-de1844d1b46f-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Fri, 2017-01-13 at 11:03 -0800, Steve Longerbeam wrote:
>
> On 01/13/2017 03:55 AM, Philipp Zabel wrote:
> > Am Freitag, den 06.01.2017, 18:11 -0800 schrieb Steve Longerbeam:
> >> Add bindings documentation for the i.MX media driver.
> >>
> >> Signed-off-by: Steve Longerbeam <steve_longerbeam-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
> >> ---
> >> Documentation/devicetree/bindings/media/imx.txt | 57 +++++++++++++++++++++++++
> >> 1 file changed, 57 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/media/imx.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/media/imx.txt b/Documentation/devicetree/bindings/media/imx.txt
> >> new file mode 100644
> >> index 0000000..254b64a
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/media/imx.txt
> >> @@ -0,0 +1,57 @@
> >> +Freescale i.MX Media Video Devices
> >> +
> >> +Video Media Controller node
> >> +---------------------------
> >> +
> >> +This is the parent media controller node for video capture support.
> >> +
> >> +Required properties:
> >> +- compatible : "fsl,imx-media";
> > Would you be opposed to calling this "capture-subsystem" instead of
> > "imx-media"? We already use "fsl,imx-display-subsystem" and
> > "fsl,imx-gpu-subsystem" for the display and GPU compound devices.
>
> sure. Some pie-in-the-sky day when DRM and media are unified,
> there could be a single device that handles them all,
Indeed :)
> but for now
> I'm fine with "fsl,capture-subsystem".
Actually, I meant fsl,imx-capture-subsystem. fsl,imx-media-subsystem
would be fine, too. Either way, I'll be happy if it looks similar to the
other two.
[...]
> > This is a clever method to get better frame timestamps. Too bad about
> > the routing requirements. Can this be used on Nitrogen6X?
>
> Absolutely, this support just needs use of the input-capture channels in the
> imx GPT. I still need to submit the patch to the imx-gpt driver that adds an
> input capture API, so at this point fsl,input-capture-channel has no effect,
> but it does work (tested on SabreAuto).
Nice.
[...]
> >> +Required properties:
> >> +- compatible : "fsl,imx6-mipi-csi2";
> > I think this should get an additional "snps,dw-mipi-csi2" compatible,
> > since the only i.MX6 specific part is the bolted-on IPU2CSI gasket.
>
> right, minus the gasket it's a Synopsys core. I'll add that compatible flag.
> Or should wait until the day this subdev is exported for general use, after
> pulling out the gasket specifics?
It can be added right away.
> >> +- reg : physical base address and length of the register set;
> >> +- clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx
> >> + (the DPHY clock), video_27m, and eim_sel;
> > Note that hsi_tx is incorrectly named. CCGR3[CG8] just happens to be the
> > shared gate bit that gates the HSI clocks as well as the MIPI
> > "ac_clk_125m", "cfg_clk", "ips_clk", and "pll_refclk" inputs to the mipi
> > csi-2 core, but we are missing shared gate clocks in the clock tree for
> > these.
>
> Yes, so many clocks for the MIPI core. Why so many? I would think
> there would need to be at most three: a clock for the MIPI CSI-2 core
> and HSI core, and a clock for the D-PHY (oh and maybe a clock for an
> M-PHY if there is one). I have no clue what all these other clocks are.
> But anyway, a single gating bit, CCGR3[CG8], seems to enable them all.
I would imagine the CSI-2 core has a high-speed clock input from the
D-PHY for serial input, an APB clock for register access (ips_clk), and
a pixel clock input for the parallel output (pixel_clk), at least.
The D-PHY will have a PLL reference input (pll_refclk?) and probably its
own register clock (cfg_clk?).
I've looked at the MIPI DSI chapter, and it looks like ac_clk_125m is
used for DSI only.
> > Both cfg_clk and pll_refclk are sourced from video_27m, so "cfg" ->
> > video_27m seems fine.
> > But I don't get "dphy".
>
> I presume it's the clock for the D-PHY.
>
> > Which input clock would that correspond to?
> > "pll_refclk?"
>
> the mux at CDCDR says it comes from PLL3_120M, or PLL2_PFD2.
I think that makes sense.
regards
Philipp
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox