* Re: [PATCH v3 2/2] mmc: pwrseq: add support for Marvell SD8787 chip
From: Matt Ranostay @ 2017-01-18 7:50 UTC (permalink / raw)
To: Shawn Lin
Cc: linux-wireless, Linux Kernel, linux-mmc, devicetree,
Tony Lindgren, Ulf Hansson
In-Reply-To: <0a49ba8d-e749-8462-fa48-7d8a17cecc75@rock-chips.com>
On Sun, Jan 15, 2017 at 6:35 PM, Shawn Lin <shawn.lin@rock-chips.com> wrote:
> On 2017/1/16 5:41, Matt Ranostay wrote:
>>
>> On Thu, Jan 12, 2017 at 11:16 PM, Shawn Lin <shawn.lin@rock-chips.com>
>> wrote:
>>>
>>> On 2017/1/13 13:29, Matt Ranostay wrote:
>>>>
>>>>
>>>> Allow power sequencing for the Marvell SD8787 Wifi/BT chip.
>>>> This can be abstracted to other chipsets if needed in the future.
>>>>
>>>> Cc: Tony Lindgren <tony@atomide.com>
>>>> Cc: Ulf Hansson <ulf.hansson@linaro.org>
>>>> Signed-off-by: Matt Ranostay <matt@ranostay.consulting>
>>>> ---
>>>> drivers/mmc/core/Kconfig | 10 ++++
>>>> drivers/mmc/core/Makefile | 1 +
>>>> drivers/mmc/core/pwrseq_sd8787.c | 117
>>>> +++++++++++++++++++++++++++++++++++++++
>>>> 3 files changed, 128 insertions(+)
>>>> create mode 100644 drivers/mmc/core/pwrseq_sd8787.c
>>>>
>>>> diff --git a/drivers/mmc/core/Kconfig b/drivers/mmc/core/Kconfig
>>>> index cdfa8520a4b1..fc1ecdaaa9ca 100644
>>>> --- a/drivers/mmc/core/Kconfig
>>>> +++ b/drivers/mmc/core/Kconfig
>>>> @@ -12,6 +12,16 @@ config PWRSEQ_EMMC
>>>> This driver can also be built as a module. If so, the module
>>>> will be called pwrseq_emmc.
>>>>
>>>> +config PWRSEQ_SD8787
>>>> + tristate "HW reset support for SD8787 BT + Wifi module"
>>>> + depends on OF && (MWIFIEX || BT_MRVL_SDIO)
>>>> + help
>>>> + This selects hardware reset support for the SD8787 BT + Wifi
>>>> + module. By default this option is set to n.
>>>> +
>>>> + This driver can also be built as a module. If so, the module
>>>> + will be called pwrseq_sd8787.
>>>> +
>>>
>>>
>>>
>>> I don't like this way, as we have a chance to list lots
>>> configure options here. wifi A,B,C,D...Z, all of them need a
>>> new section here if needed?
>>>
>>> Instead, could you just extent pwrseq_simple.c and add you
>>> .compatible = "mmc-pwrseq-sd8787", "mmc-pwrseq-simple"?
>>
>>
>> You mean all the chipset pwrseqs linked into the pwrseq-simple module?
>
>
> What I mean was if you just extent the pwrseq-simple a bit, you could
> just add your chipset pwrseqs linked into the pwrseq-simple. But if you
> need a different *pattern* of pwrseqs, you should need a new name, for
> instance, pwrseq-sdio.c etc... But please don't use the name of
> sd8787? So if I use a wifi named ABC but using the same pwrseq pattenr,
> should I include your "mmc-pwrseq- sd8787" for that or I need a new
> mmc-pwrseq-ABC.c?
Ah so pwrseq-sdio.c seems reasonable and having chipsets functions
defined in a structure. That could be abstracted out for other
chipsets that could needed in the future.
- Matt
>
>
>>
>> Ulf your thoughts on this?
>>
>>>
>>>
>>>
>>>> config PWRSEQ_SIMPLE
>>>> tristate "Simple HW reset support for MMC"
>>>> default y
>>>> diff --git a/drivers/mmc/core/Makefile b/drivers/mmc/core/Makefile
>>>> index b2a257dc644f..0f81464fa824 100644
>>>> --- a/drivers/mmc/core/Makefile
>>>> +++ b/drivers/mmc/core/Makefile
>>>> @@ -10,6 +10,7 @@ mmc_core-y := core.o bus.o host.o \
>>>> quirks.o slot-gpio.o
>>>> mmc_core-$(CONFIG_OF) += pwrseq.o
>>>> obj-$(CONFIG_PWRSEQ_SIMPLE) += pwrseq_simple.o
>>>> +obj-$(CONFIG_PWRSEQ_SD8787) += pwrseq_sd8787.o
>>>> obj-$(CONFIG_PWRSEQ_EMMC) += pwrseq_emmc.o
>>>> mmc_core-$(CONFIG_DEBUG_FS) += debugfs.o
>>>> obj-$(CONFIG_MMC_BLOCK) += mmc_block.o
>>>> diff --git a/drivers/mmc/core/pwrseq_sd8787.c
>>>> b/drivers/mmc/core/pwrseq_sd8787.c
>>>> new file mode 100644
>>>> index 000000000000..f4080fe6439e
>>>> --- /dev/null
>>>> +++ b/drivers/mmc/core/pwrseq_sd8787.c
>>>> @@ -0,0 +1,117 @@
>>>> +/*
>>>> + * pwrseq_sd8787.c - power sequence support for Marvell SD8787 BT +
>>>> Wifi
>>>> chip
>>>> + *
>>>> + * Copyright (C) 2016 Matt Ranostay <matt@ranostay.consulting>
>>>> + *
>>>> + * Based on the original work pwrseq_simple.c
>>>> + * Copyright (C) 2014 Linaro Ltd
>>>> + * Author: Ulf Hansson <ulf.hansson@linaro.org>
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or modify
>>>> + * it under the terms of the GNU General Public License as published by
>>>> + * the Free Software Foundation; either version 2 of the License, or
>>>> + * (at your option) any later version.
>>>> + *
>>>> + * This program is distributed in the hope that it will be useful,
>>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>>> + * GNU General Public License for more details.
>>>> + *
>>>> + */
>>>> +
>>>> +#include <linux/delay.h>
>>>> +#include <linux/init.h>
>>>> +#include <linux/kernel.h>
>>>> +#include <linux/platform_device.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/slab.h>
>>>> +#include <linux/device.h>
>>>> +#include <linux/err.h>
>>>> +#include <linux/gpio/consumer.h>
>>>> +
>>>> +#include <linux/mmc/host.h>
>>>> +
>>>> +#include "pwrseq.h"
>>>> +
>>>> +struct mmc_pwrseq_sd8787 {
>>>> + struct mmc_pwrseq pwrseq;
>>>> + struct gpio_desc *reset_gpio;
>>>> + struct gpio_desc *pwrdn_gpio;
>>>> +};
>>>> +
>>>> +#define to_pwrseq_sd8787(p) container_of(p, struct mmc_pwrseq_sd8787,
>>>> pwrseq)
>>>> +
>>>> +static void mmc_pwrseq_sd8787_pre_power_on(struct mmc_host *host)
>>>> +{
>>>> + struct mmc_pwrseq_sd8787 *pwrseq =
>>>> to_pwrseq_sd8787(host->pwrseq);
>>>> +
>>>> + gpiod_set_value_cansleep(pwrseq->reset_gpio, 1);
>>>> +
>>>> + msleep(300);
>>>> + gpiod_set_value_cansleep(pwrseq->pwrdn_gpio, 1);
>>>> +}
>>>> +
>>>> +static void mmc_pwrseq_sd8787_power_off(struct mmc_host *host)
>>>> +{
>>>> + struct mmc_pwrseq_sd8787 *pwrseq =
>>>> to_pwrseq_sd8787(host->pwrseq);
>>>> +
>>>> + gpiod_set_value_cansleep(pwrseq->pwrdn_gpio, 0);
>>>> + gpiod_set_value_cansleep(pwrseq->reset_gpio, 0);
>>>> +}
>>>> +
>>>> +static const struct mmc_pwrseq_ops mmc_pwrseq_sd8787_ops = {
>>>> + .pre_power_on = mmc_pwrseq_sd8787_pre_power_on,
>>>> + .power_off = mmc_pwrseq_sd8787_power_off,
>>>> +};
>>>> +
>>>> +static const struct of_device_id mmc_pwrseq_sd8787_of_match[] = {
>>>> + { .compatible = "mmc-pwrseq-sd8787",},
>>>> + {/* sentinel */},
>>>> +};
>>>> +MODULE_DEVICE_TABLE(of, mmc_pwrseq_sd8787_of_match);
>>>> +
>>>> +static int mmc_pwrseq_sd8787_probe(struct platform_device *pdev)
>>>> +{
>>>> + struct mmc_pwrseq_sd8787 *pwrseq;
>>>> + struct device *dev = &pdev->dev;
>>>> +
>>>> + pwrseq = devm_kzalloc(dev, sizeof(*pwrseq), GFP_KERNEL);
>>>> + if (!pwrseq)
>>>> + return -ENOMEM;
>>>> +
>>>> + pwrseq->pwrdn_gpio = devm_gpiod_get(dev, "pwrdn",
>>>> GPIOD_OUT_LOW);
>>>> + if (IS_ERR(pwrseq->pwrdn_gpio))
>>>> + return PTR_ERR(pwrseq->pwrdn_gpio);
>>>> +
>>>> + pwrseq->reset_gpio = devm_gpiod_get(dev, "reset",
>>>> GPIOD_OUT_LOW);
>>>> + if (IS_ERR(pwrseq->reset_gpio))
>>>> + return PTR_ERR(pwrseq->reset_gpio);
>>>> +
>>>> + pwrseq->pwrseq.dev = dev;
>>>> + pwrseq->pwrseq.ops = &mmc_pwrseq_sd8787_ops;
>>>> + pwrseq->pwrseq.owner = THIS_MODULE;
>>>> + platform_set_drvdata(pdev, pwrseq);
>>>> +
>>>> + return mmc_pwrseq_register(&pwrseq->pwrseq);
>>>> +}
>>>> +
>>>> +static int mmc_pwrseq_sd8787_remove(struct platform_device *pdev)
>>>> +{
>>>> + struct mmc_pwrseq_sd8787 *pwrseq = platform_get_drvdata(pdev);
>>>> +
>>>> + mmc_pwrseq_unregister(&pwrseq->pwrseq);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static struct platform_driver mmc_pwrseq_sd8787_driver = {
>>>> + .probe = mmc_pwrseq_sd8787_probe,
>>>> + .remove = mmc_pwrseq_sd8787_remove,
>>>> + .driver = {
>>>> + .name = "pwrseq_sd8787",
>>>> + .of_match_table = mmc_pwrseq_sd8787_of_match,
>>>> + },
>>>> +};
>>>> +
>>>> +module_platform_driver(mmc_pwrseq_sd8787_driver);
>>>> +MODULE_LICENSE("GPL v2");
>>>>
>>>
>>>
>>> --
>>> Best Regards
>>> Shawn Lin
>>>
>>
>>
>>
>
>
> --
> Best Regards
> Shawn Lin
>
^ permalink raw reply
* Re: [PATCH v11 09/12] drm/mediatek: add dsi transfer function
From: CK Hu @ 2017-01-18 7:49 UTC (permalink / raw)
To: YT Shen
Cc: Mark Rutland, devicetree, srv_heupstream, emil.l.velikov,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Matthias Brugger, yingjoe.chen, shaoming chen, linux-arm-kernel
In-Reply-To: <1484117473-46644-10-git-send-email-yt.shen@mediatek.com>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> From: shaoming chen <shaoming.chen@mediatek.com>
>
> add dsi read/write commands for transfer function
>
> Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 168 ++++++++++++++++++++++++++++++++++++-
> 1 file changed, 166 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 474861a..b3c7fd8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -24,6 +24,7 @@
> #include <linux/of_graph.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <video/mipi_display.h>
> #include <video/videomode.h>
>
> #include "mtk_drm_ddp_comp.h"
> @@ -80,8 +81,16 @@
> #define DSI_HBP_WC 0x54
> #define DSI_HFP_WC 0x58
>
> +#define DSI_CMDQ_SIZE 0x60
> +#define CMDQ_SIZE 0x3f
> +
> #define DSI_HSTX_CKL_WC 0x64
>
> +#define DSI_RX_DATA0 0x74
> +#define DSI_RX_DATA1 0x78
> +#define DSI_RX_DATA2 0x7c
> +#define DSI_RX_DATA3 0x80
> +
> #define DSI_RACK 0x84
> #define RACK BIT(0)
>
> @@ -117,6 +126,15 @@
> #define CLK_HS_POST (0xff << 8)
> #define CLK_HS_EXIT (0xff << 16)
>
> +#define DSI_CMDQ0 0x180
> +#define CONFIG (0xff << 0)
> +#define SHORT_PACKET 0
> +#define LONG_PACKET 2
> +#define BTA BIT(2)
> +#define DATA_ID (0xff << 8)
> +#define DATA_0 (0xff << 16)
> +#define DATA_1 (0xff << 24)
> +
> #define T_LPX 5
> #define T_HS_PREP 6
> #define T_HS_TRAIL 8
> @@ -125,6 +143,12 @@
>
> #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
>
> +#define MTK_DSI_HOST_IS_READ(type) \
> + ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
> + (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
> + (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
> + (type == MIPI_DSI_DCS_READ))
> +
> struct phy;
>
> struct mtk_dsi {
> @@ -497,12 +521,12 @@ static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
> dsi->irq_data |= irq_bit;
> }
>
> -static __maybe_unused void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
> +static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
> {
> dsi->irq_data &= ~irq_bit;
> }
>
> -static __maybe_unused s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
> +static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
> unsigned int timeout)
> {
> s32 ret = 0;
> @@ -832,9 +856,149 @@ static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
> return 0;
> }
>
> +static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
> +{
> + u32 timeout_ms = 500000; /* total 1s ~ 2s timeout */
> +
> + while (timeout_ms--) {
> + if (!(readl(dsi->regs + DSI_INTSTA) & DSI_BUSY))
> + break;
> +
> + usleep_range(2, 4);
> + }
> +
> + if (timeout_ms == 0) {
> + DRM_WARN("polling dsi wait not busy timeout!\n");
> +
> + mtk_dsi_enable(dsi);
> + mtk_dsi_reset_engine(dsi);
> + }
> +}
> +
> +static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
> +{
> + switch (type) {
> + case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
> + case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
> + return 1;
> + case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
> + case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
> + return 2;
> + case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
> + case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
> + return read_data[1] + read_data[2] * 16;
> + case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
> + DRM_INFO("type is 0x02, try again\n");
> + break;
> + default:
> + DRM_INFO("type(0x%x) cannot be non-recognite\n", type);
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
> +{
> + const char *tx_buf = msg->tx_buf;
> + u8 config, cmdq_size, cmdq_off, type = msg->type;
> + u32 reg_val, cmdq_mask, i;
> +
> + if (MTK_DSI_HOST_IS_READ(type))
> + config = BTA;
> + else
> + config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
> +
> + if (msg->tx_len > 2) {
> + cmdq_size = 1 + (msg->tx_len + 3) / 4;
> + cmdq_off = 4;
> + cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
> + reg_val = (msg->tx_len << 16) | (type << 8) | config;
> + } else {
> + cmdq_size = 1;
> + cmdq_off = 2;
> + cmdq_mask = CONFIG | DATA_ID;
> + reg_val = (type << 8) | config;
> + }
> +
> + for (i = 0; i < msg->tx_len; i++)
> + writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
> +
> + mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
> + mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
> +}
> +
> +static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
> + const struct mipi_dsi_msg *msg, u8 flag)
> +{
> + mtk_dsi_wait_for_idle(dsi);
> + mtk_dsi_irq_data_clear(dsi, flag);
> + mtk_dsi_cmdq(dsi, msg);
> + mtk_dsi_start(dsi);
> +
> + if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
> + return -ETIME;
> + else
> + return 0;
> +}
> +
> +static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
> + const struct mipi_dsi_msg *msg)
> +{
> + struct mtk_dsi *dsi = host_to_dsi(host);
> + u32 recv_cnt, i;
> + u8 read_data[16];
> + void *src_addr;
> + u8 irq_flag = CMD_DONE_INT_FLAG;
> +
> + if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
> + DRM_ERROR("dsi engine is not command mode\n");
> + return -EINVAL;
> + }
> +
> + if (MTK_DSI_HOST_IS_READ(msg->type))
> + irq_flag |= LPRX_RD_RDY_INT_FLAG;
> +
> + if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
> + return -ETIME;
> +
> + if (!MTK_DSI_HOST_IS_READ(msg->type))
> + return 0;
> +
> + if (!msg->rx_buf) {
> + DRM_ERROR("dsi receive buffer size may be NULL\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < 16; i++)
> + *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
> +
> + recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
> +
> + if (recv_cnt > 2)
> + src_addr = &read_data[4];
> + else
> + src_addr = &read_data[1];
> +
> + if (recv_cnt > 10)
> + recv_cnt = 10;
> +
> + if (recv_cnt > msg->rx_len)
> + recv_cnt = msg->rx_len;
> +
> + if (recv_cnt)
> + memcpy(msg->rx_buf, src_addr, recv_cnt);
> +
> + DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
> + recv_cnt, *((u8 *)(msg->tx_buf)));
> +
> + return recv_cnt;
> +}
> +
> static const struct mipi_dsi_host_ops mtk_dsi_ops = {
> .attach = mtk_dsi_host_attach,
> .detach = mtk_dsi_host_detach,
> + .transfer = mtk_dsi_host_transfer,
> };
>
> static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
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^ permalink raw reply
* Re: [PATCH 13/13] MIPS: jz4740: Remove custom GPIO code
From: Thierry Reding @ 2017-01-18 7:27 UTC (permalink / raw)
To: Paul Cercueil, Ralf Baechle
Cc: Mark Rutland, Boris Brezillon, Ulf Hansson, Lars-Peter Clausen,
james.hogan, Paul Burton, Bartlomiej Zolnierkiewicz,
Linus Walleij, linux-mmc, linux-kernel, linux-pwm, linux-gpio,
devicetree, Rob Herring, linux-mips, linux-fbdev,
Maarten ter Huurne, linux-mtd
In-Reply-To: <20170117231421.16310-14-paul@crapouillou.net>
[-- Attachment #1.1: Type: text/plain, Size: 1641 bytes --]
On Wed, Jan 18, 2017 at 12:14:21AM +0100, Paul Cercueil wrote:
> All the drivers for the various hardware elements of the jz4740 SoC have
> been modified to use the pinctrl framework for their pin configuration
> needs.
> As such, this platform code is now unused and can be deleted.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
> arch/mips/include/asm/mach-jz4740/gpio.h | 371 ----------------------
> arch/mips/jz4740/Makefile | 2 -
> arch/mips/jz4740/gpio.c | 519 -------------------------------
> 3 files changed, 892 deletions(-)
> delete mode 100644 arch/mips/jz4740/gpio.c
Have you considered how this could best be merged? It's probably easiest
to take all of this through the MIPS tree because we have an addition of
the pinctrl that would be a replacement for the GPIO code, while at the
same time a bunch of drivers rely on the JZ4740 GPIO code for successful
compilation.
That's slightly complicated by the number of drivers, so needs a lot of
coordination, but it's not the worst I've seen.
Maybe one other solution that would make the transition easier would be
to stub out the GPIO functions if the pinctrl driver is enabled, and do
the removal of the mach-jz4740/gpio.h after all drivers have been merged
through their corresponding subsystem trees. That way all drivers should
remain compilable and functional at runtime, while still having the
possibility to merge through the subsystem trees.
That said, the whole series is fairly simple, so merging everything
through the MIPS tree sounds like the easiest way to go.
Thierry
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______________________________________________________
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^ permalink raw reply
* Re: [PATCH 12/13] pwm: jz4740: Let the pinctrl driver configure the pins
From: Thierry Reding @ 2017-01-18 7:20 UTC (permalink / raw)
To: Paul Cercueil
Cc: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Ulf Hansson, Boris Brezillon, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, linux-gpio,
devicetree, linux-kernel, linux-mips, linux-mmc, linux-mtd,
linux-pwm, linux-fbdev, james.hogan
In-Reply-To: <20170117231421.16310-13-paul@crapouillou.net>
[-- Attachment #1: Type: text/plain, Size: 1857 bytes --]
On Wed, Jan 18, 2017 at 12:14:20AM +0100, Paul Cercueil wrote:
> Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
> the pins being properly configured before the driver probes.
>
> One inherent problem of this new approach is that the pinctrl framework
> does not allow us to configure each pin on demand, when the various PWM
> channels are requested or released. For instance, the PWM channels can
> be configured from sysfs, which would require all PWM pins to be configured
> properly beforehand for the PWM function, eventually causing conflicts
> with other platform or board drivers.
>
> The proper solution here would be to modify the pwm-jz4740 driver to
> handle only one PWM channel, and create an instance of this driver
> for each one of the 8 PWM channels. Then, it could use the pinctrl
> framework to dynamically configure the PWM pin it controls.
>
> Until this can be done, the only jz4740 board supported upstream
> (Qi lb60) could configure all of its connected PWM pins in PWM function
> mode, if those are not used by other drivers nor by GPIOs on the
> board.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
> drivers/pwm/pwm-jz4740.c | 29 -----------------------------
> 1 file changed, 29 deletions(-)
>
> diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c
> index 76d13150283f..a75ff3622450 100644
> --- a/drivers/pwm/pwm-jz4740.c
> +++ b/drivers/pwm/pwm-jz4740.c
> @@ -21,22 +21,10 @@
> #include <linux/platform_device.h>
> #include <linux/pwm.h>
>
> -#include <asm/mach-jz4740/gpio.h>
What about the linux/gpio.h header? It seems to me like that would be no
longer needed after this patch either.
Other than that this looks like the patch I'd expect if the pinmux was
configured statically, based on board design.
Thierry
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^ permalink raw reply
* Re: [PATCH 00/13] Ingenic JZ4740 / JZ4780 pinctrl driver
From: Thierry Reding @ 2017-01-18 7:15 UTC (permalink / raw)
To: Paul Cercueil
Cc: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Ulf Hansson, Boris Brezillon, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, linux-gpio,
devicetree, linux-kernel, linux-mips, linux-mmc, linux-mtd,
linux-pwm, linux-fbdev, james.hogan
In-Reply-To: <20170117231421.16310-1-paul@crapouillou.net>
[-- Attachment #1: Type: text/plain, Size: 2322 bytes --]
On Wed, Jan 18, 2017 at 12:14:08AM +0100, Paul Cercueil wrote:
[...]
> One problem still unresolved: the pinctrl framework does not allow us to
> configure each pin on demand (someone please prove me wrong), when the
> various PWM channels are requested or released. For instance, the PWM
> channels can be configured from sysfs, which would require all PWM pins
> to be configured properly beforehand for the PWM function, eventually
> causing conflicts with other platform or board drivers.
Still catching up on a lot of email, so I haven't gone through the
entire series. But I don't think the above is true.
My understanding is that you can have separate pin groups for each
pin (provided the hardware supports that) and then control each of
these groups dynamically at runtime.
That is you could have the PWM driver's ->request() and ->free()
call into the pinctrl framework to select the correct pinmux
configuration as necessary.
> The proper solution here would be to modify the pwm-jz4740 driver to
> handle only one PWM channel, and create an instance of this driver
> for each one of the 8 PWM channels. Then, it could use the pinctrl
> framework to dynamically configure the PWM pin it controls.
That could probably work. From only looking at the JZ4740 PWM driver
there's no separate IP block to deal with the PWM outputs, but they are
merely GPIOs controller via a timer, so one instance per GPIO seems like
a fine solution to me.
> Until this can be done, the only jz4740 board supported upstream
> (Qi lb60) could configure all of its connected PWM pins in PWM function
> mode, if those are not used by other drivers nor by GPIOs on the
> board. The only jz4780 board upstream (CI20) does not yet support the
> PWM driver.
Typically all of the pinmux is pre-determined by the board design. That
is if you've got 8 pins that can be driven by a PWM signal, not all of
those might be exposed by the design. If, say, only 0-4 and 6 expose the
PWM signal while 5 and 7 expose a different function then you can simply
use a static pinmux configuration and ignore PWMs 5 and 7. Even if
someone were to configure them, the signal would simply go nowhere.
Of course you'd have to check that your hardware actually matches those
assumptions. They certainly apply to many SoCs that I've come across.
Thierry
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^ permalink raw reply
* Re: [PATCH] ARM: dts: sun6i: sina31s: Enable USB OTG controller in peripheral mode
From: Maxime Ripard @ 2017-01-18 7:11 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20170118010105.20069-1-wens-jdAy2FN1RRM@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 962 bytes --]
On Wed, Jan 18, 2017 at 09:01:05AM +0800, Chen-Yu Tsai wrote:
> While the SinA31s does have a proper 5-pin mini USB OTG port, the ID
> pin does not seem to work. The pin used in the schematics is always low,
> regardless of the attached OTG cable or SoC internal pin bias settings.
>
> The v1.5 board is missing bias resistors shown in the schematics for
> earlier revisions, and the connections of the remaining one does not
> match the schematics either.
>
> In addition, VBUS for this port is disconnected from the board's 5V
> power rail. The board features a pad to solder jumper pins to connect
> VBUS to 5V manually.
>
> Given the above and the fact that the board has 5 more USB host ports,
> it makes more sense to have the OTG port work in peripheral mode.
>
> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH] arm64: dts: exynos: Remove address node from usb parent node
From: Chanwoo Choi @ 2017-01-18 7:04 UTC (permalink / raw)
To: Pankaj Dubey, devicetree, linux-kernel, linux-samsung-soc
Cc: robh+dt, krzk, kgene, javier
In-Reply-To: <1484718408-28933-1-git-send-email-pankaj.dubey@samsung.com>
Hi Pankaj,
This issue already posted by Javier Martinez Canillas[1].
Maybe, he will post v2.
[1] https://lkml.org/lkml/2017/1/10/907
- ("Re: [PATCH v2 3/3] arm64: dts: exynos: Remove unneeded unit names in Exynos5433 nodes")
On 2017년 01월 18일 14:46, Pankaj Dubey wrote:
> Address node does not required to be put after parent't node,
> so remove address node from usb parent node.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 68f764e..0d7a55d 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -1285,7 +1285,7 @@
> status = "disabled";
> };
>
> - usbdrd30: usb@15400000 {
> + usbdrd30: usb3-0 {
> compatible = "samsung,exynos5250-dwusb3";
> clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
> <&cmu_fsys CLK_SCLK_USBDRD30>;
> @@ -1332,7 +1332,7 @@
> status = "disabled";
> };
>
> - usbhost30: usb@15a00000 {
> + usbhost30: usbhost3-0 {
> compatible = "samsung,exynos5250-dwusb3";
> clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
> <&cmu_fsys CLK_SCLK_USBHOST30>;
>
--
Best Regards,
Chanwoo Choi
S/W Center, Samsung Electronics
^ permalink raw reply
* Re: [PATCH v4 3/4] dt-bindings: phy: Add support for QMP phy
From: Vivek Gautam @ 2017-01-18 6:54 UTC (permalink / raw)
To: Kishon Vijay Abraham I, robh+dt, linux-kernel, devicetree
Cc: mark.rutland, sboyd, bjorn.andersson, srinivas.kandagatla,
linux-arm-msm
In-Reply-To: <587C88FE.2040900@ti.com>
Hi Kishon,
On 01/16/2017 02:19 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 10 January 2017 04:21 PM, Vivek Gautam wrote:
>> Qualcomm chipsets have QMP phy controller that provides
>> support to a number of controller, viz. PCIe, UFS, and USB.
>> Adding dt binding information for the same.
>>
>> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
>> Acked-by: Rob Herring <robh@kernel.org>
>> ---
>>
>> Changes since v3:
>> - Added #clock-cells = <1>, indicating that phy is a clock provider.
>>
>> Changes since v2:
>> - Removed binding for "ref_clk_src" since we don't request this
>> clock in the driver.
>> - Addressed s/ref_clk/ref. Don't need to add '_clk' suffix to clock names.
>> - Using 'phy' for the node name.
>>
>> Changes since v1:
>> - New patch, forked out of the original driver patch:
>> "phy: qcom-qmp: new qmp phy driver for qcom-chipsets"
>> - Added 'Acked-by' from Rob.
>> - Updated bindings to include mem resource as a list of
>> offset - length pair for serdes block and for each lane.
>> - Added a new binding for 'lane-offsets' that contains offsets
>> to tx, rx and pcs blocks from each lane base address.
>>
>> .../devicetree/bindings/phy/qcom-qmp-phy.txt | 76 ++++++++++++++++++++++
>> 1 file changed, 76 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>> new file mode 100644
>> index 000000000000..6f510fe48f46
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>> @@ -0,0 +1,76 @@
>> +Qualcomm QMP PHY controller
>> +===========================
>> +
>> +QMP phy controller supports physical layer functionality for a number of
>> +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
>> +
>> +Required properties:
>> + - compatible: compatible list, contains:
>> + "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
>> + "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
>> + - reg: list of offset and length pair of the PHY register sets.
>> + at index 0: offset and length of register set for PHY common
>> + serdes block.
>> + from index 1 - N: offset and length of register set for each lane,
>> + for N number of phy lanes (ports).
>> + - lane-offsets: array of offsets to tx, rx and pcs blocks for phy lanes.
>> + - #phy-cells: must be 1
>> + - Cell after phy phandle should be the port (lane) number.
>> + - #clock-cells: must be 1
>> + - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
>> + interface (for pipe based PHYs). These clock are then gate-controlled
>> + by gcc.
>> + - clocks: a list of phandles and clock-specifier pairs,
>> + one for each entry in clock-names.
>> + - clock-names: must be "cfg_ahb" for phy config clock,
>> + "aux" for phy aux clock,
>> + "ref" for 19.2 MHz ref clk,
>> + "pipe<port-number>" for pipe clock specific to
>> + each port/lane (Optional).
>> + - resets: a list of phandles and reset controller specifier pairs,
>> + one for each entry in reset-names.
>> + - reset-names: must be "phy" for reset of phy block,
>> + "common" for phy common block reset,
>> + "cfg" for phy's ahb cfg block reset (Optional).
>> + "port<port-number>" for reset specific to
>> + each port/lane (Optional).
>> + - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
>> + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
>> +
>> +Optional properties:
>> + - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
>> + pll block.
>> +
>> +Example:
>> + pcie_phy: phy@34000 {
>> + compatible = "qcom,msm8996-qmp-pcie-phy";
>> + reg = <0x034000 0x48f>,
>> + <0x035000 0x5bf>,
>> + <0x036000 0x5bf>,
>> + <0x037000 0x5bf>;
>> + /* tx, rx, pcs */
>> + lane-offsets = <0x0 0x200 0x400>;
>> + #phy-cells = <1>;
>> + #clock-cells = <1>;
>> +
>> + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
>> + <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
>> + <&gcc GCC_PCIE_CLKREF_CLK>,
>> + <&gcc GCC_PCIE_0_PIPE_CLK>,
>> + <&gcc GCC_PCIE_1_PIPE_CLK>,
>> + <&gcc GCC_PCIE_2_PIPE_CLK>;
>> + clock-names = "aux", "cfg_ahb", "ref",
>> + "pipe0", "pipe1", "pipe2";
>> +
>> + vdda-phy-supply = <&pm8994_l28>;
>> + vdda-pll-supply = <&pm8994_l12>;
>> +
>> + resets = <&gcc GCC_PCIE_PHY_BCR>,
>> + <&gcc GCC_PCIE_PHY_COM_BCR>,
>> + <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>,
>> + <&gcc GCC_PCIE_0_PHY_BCR>,
>> + <&gcc GCC_PCIE_1_PHY_BCR>,
>> + <&gcc GCC_PCIE_2_PHY_BCR>;
>> + reset-names = "phy", "common", "cfg",
>> + "lane0", "lane1", "lane2";
> Each lane has a separate clock, separate reset.. why not create sub-nodes for
> each lane?
Yes, each lane has separate pipe clock and resets.
I can have a binding such as written below.
Does it makes sense to pull in the tx, rx and pcs offsets as well
to the child node, and iomap the entire address space of the phy ?
+ pcie_phy: pciephy@34000 {
+ compatible = "qcom,qmp-14nm-phy";
+ reg = <0x034000 0x3fff>;
+ #address-cells = <1>;
+ #size-cells = <0>;
...
+ port@0 {
+ reg = <0>;
+ tx-offset = <0x1000>;
+ rx-offset = <0x1200>;
+ pcs-offset = <0x1400>;
+ clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "lane0";
+ };
+ };
Regards
Vivek
>
> Thanks
> Kishon
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 2/2] arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
From: Pankaj Dubey @ 2017-01-18 6:32 UTC (permalink / raw)
To: linux-samsung-soc, linux-arm-kernel, devicetree
Cc: Pankaj Dubey, krzk, Vivek Gautam, javier, robh+dt, kgene, sanath
In-Reply-To: <1484721173-30474-1-git-send-email-pankaj.dubey@samsung.com>
From: Vivek Gautam <gautamvivek1987@gmail.com>
Adding fixed voltage regulators for Vbus and Vbus-boost required
by USB 3.0 DRD controller on Exynos7-espresso board.
Signed-off-by: Vivek Gautam <gautamvivek1987@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 45 +++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 1b2db9f0..e4705fd 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -13,6 +13,7 @@
#include "exynos7.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Samsung Exynos7 Espresso board based on EXYNOS7";
@@ -32,6 +33,29 @@
device_type = "memory";
reg = <0x0 0x40000000 0x0 0xC0000000>;
};
+
+ usb30_vbus_reg: regulator-usb30 {
+ compatible = "regulator-fixed";
+ regulator-name = "VBUS_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gph1 1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb30_vbus_en>;
+ enable-active-high;
+ };
+
+ usb3drd_boost_5v: regulator-usb3drd-boost {
+ compatible = "regulator-fixed";
+ regulator-name = "VUSB_VBUS_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpf4 1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3drd_boost_en>;
+ enable-active-high;
+ };
+
};
&fin_pll {
@@ -365,3 +389,24 @@
vqmmc-supply = <&ldo2_reg>;
disable-wp;
};
+
+&usbdrd_phy {
+ vbus-supply = <&usb30_vbus_reg>;
+ vbus-boost-supply = <&usb3drd_boost_5v>;
+};
+
+&pinctrl_bus1 {
+ usb30_vbus_en: usb30-vbus-en {
+ samsung,pins = "gph1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ usb3drd_boost_en: usb3drd-boost-en {
+ samsung,pins = "gpf4-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v3 1/2] arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
From: Pankaj Dubey @ 2017-01-18 6:32 UTC (permalink / raw)
To: linux-samsung-soc, linux-arm-kernel, devicetree
Cc: Pankaj Dubey, krzk, Vivek Gautam, javier, robh+dt, kgene, sanath
In-Reply-To: <1484721173-30474-1-git-send-email-pankaj.dubey@samsung.com>
From: Vivek Gautam <gautamvivek1987@gmail.com>
Add USB 3.0 DRD controller device node, with its clock
and phy information to enable the same on Exynos7.
Signed-off-by: Vivek Gautam <gautamvivek1987@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 34 +++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 80aa60e..9a3fbed 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -603,6 +603,40 @@
#include "exynos7-trip-points.dtsi"
};
};
+
+ usbdrd_phy: phy@15500000 {
+ compatible = "samsung,exynos7-usbdrd-phy";
+ reg = <0x15500000 0x100>;
+ clocks = <&clock_fsys0 ACLK_USBDRD300>,
+ <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
+ <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
+ <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
+ <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
+ clock-names = "phy", "ref", "phy_pipe",
+ "phy_utmi", "itp";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <1>;
+ };
+
+ usbdrd3 {
+ compatible = "samsung,exynos7-dwusb3";
+ clocks = <&clock_fsys0 ACLK_USBDRD300>,
+ <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
+ <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
+ clock-names = "usbdrd30", "usbdrd30_susp_clk",
+ "usbdrd30_axius_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dwc3@15400000 {
+ compatible = "snps,dwc3";
+ reg = <0x15400000 0x10000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH v3 0/2] Add USB DRD 3.0 device node for Exynos7
From: Pankaj Dubey @ 2017-01-18 6:32 UTC (permalink / raw)
To: linux-samsung-soc, linux-arm-kernel, devicetree
Cc: Pankaj Dubey, krzk, javier, robh+dt, kgene, sanath
In-Reply-To: <CGME20170118063006epcas5p28e5430460e604e9c1017ea0a46c89baa@epcas5p2.samsung.com>
This patch series adds USB 3.0 DRD device node for Exynos7 and
required Vbus and Vbus-boost support for espresso dev boards.
These patches are part of patch series [1] earlier submitted by Vivek
While other patches in these series got merged, DTS related change were
left. I have prepared and tested these patches on top of krzk/for-next and
my patch series "Use macros for pinctrl configuration on Exynos7" [2].
[1]: https://lkml.org/lkml/2014/11/21/247
[2]: https://www.spinics.net/lists/arm-kernel/msg555333.html
Changes since v1:
- Updated S-o-B order and Authorship of patches.
- Added Javier's Reviewed-by.
- Replaced GPIO polarity values with appropriate macros.
Changes since v2:
- Changed order of S-o-B and R-o-B lines
- Removed address node from parent usb node
- Replaced pinctrl configuration values with macros
Vivek Gautam (2):
arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 45 +++++++++++++++++++++++++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 34 +++++++++++++++++++
2 files changed, 79 insertions(+)
--
2.7.4
^ permalink raw reply
* Re: [PATCH v11 08/12] drm/mediatek: add dsi interrupt control
From: CK Hu @ 2017-01-18 6:21 UTC (permalink / raw)
To: YT Shen
Cc: Mark Rutland, devicetree, srv_heupstream, emil.l.velikov,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Matthias Brugger, yingjoe.chen, shaoming chen, linux-arm-kernel
In-Reply-To: <1484117473-46644-9-git-send-email-yt.shen@mediatek.com>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> From: shaoming chen <shaoming.chen@mediatek.com>
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 92 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 92 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 6f4b3bb..474861a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -18,6 +18,7 @@
> #include <drm/drm_panel.h>
> #include <linux/clk.h>
> #include <linux/component.h>
> +#include <linux/irq.h>
> #include <linux/of.h>
> #include <linux/of_platform.h>
> #include <linux/of_graph.h>
> @@ -29,6 +30,16 @@
>
> #define DSI_START 0x00
>
> +#define DSI_INTEN 0x08
> +
> +#define DSI_INTSTA 0x0c
> +#define LPRX_RD_RDY_INT_FLAG BIT(0)
> +#define CMD_DONE_INT_FLAG BIT(1)
> +#define TE_RDY_INT_FLAG BIT(2)
> +#define VM_DONE_INT_FLAG BIT(3)
> +#define EXT_TE_RDY_INT_FLAG BIT(4)
> +#define DSI_BUSY BIT(31)
> +
> #define DSI_CON_CTRL 0x10
> #define DSI_RESET BIT(0)
> #define DSI_EN BIT(1)
> @@ -71,6 +82,9 @@
>
> #define DSI_HSTX_CKL_WC 0x64
>
> +#define DSI_RACK 0x84
> +#define RACK BIT(0)
> +
> #define DSI_PHY_LCCON 0x104
> #define LC_HS_TX_EN BIT(0)
> #define LC_ULPM_EN BIT(1)
> @@ -137,6 +151,8 @@ struct mtk_dsi {
> struct videomode vm;
> int refcount;
> bool enabled;
> + u32 irq_data;
> + wait_queue_head_t irq_wait_queue;
> };
>
> static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
> @@ -469,6 +485,64 @@ static void mtk_dsi_start(struct mtk_dsi *dsi)
> writel(1, dsi->regs + DSI_START);
> }
>
> +static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
> +{
> + u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
> +
> + writel(inten, dsi->regs + DSI_INTEN);
> +}
> +
> +static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
> +{
> + dsi->irq_data |= irq_bit;
> +}
> +
> +static __maybe_unused void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
> +{
> + dsi->irq_data &= ~irq_bit;
> +}
> +
> +static __maybe_unused s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
> + unsigned int timeout)
> +{
> + s32 ret = 0;
> + unsigned long jiffies = msecs_to_jiffies(timeout);
> +
> + ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
> + dsi->irq_data & irq_flag,
> + jiffies);
> + if (ret == 0) {
> + DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
> +
> + mtk_dsi_enable(dsi);
> + mtk_dsi_reset_engine(dsi);
> + }
> +
> + return ret;
> +}
> +
> +static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
> +{
> + struct mtk_dsi *dsi = dev_id;
> + u32 status, tmp;
> + u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
> +
> + status = readl(dsi->regs + DSI_INTSTA) & flag;
> +
> + if (status) {
> + do {
> + mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
> + tmp = readl(dsi->regs + DSI_INTSTA);
> + } while (tmp & DSI_BUSY);
> +
> + mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
> + mtk_dsi_irq_data_set(dsi, status);
> + wake_up_interruptible(&dsi->irq_wait_queue);
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
> {
> if (WARN_ON(dsi->refcount == 0))
> @@ -517,6 +591,7 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
>
> mtk_dsi_ps_control_vact(dsi);
> mtk_dsi_config_vdo_timing(dsi);
> + mtk_dsi_set_interrupt_enable(dsi);
>
> mtk_dsi_set_mode(dsi);
> mtk_dsi_clk_hs_mode(dsi, 1);
> @@ -818,6 +893,7 @@ static int mtk_dsi_probe(struct platform_device *pdev)
> struct device *dev = &pdev->dev;
> struct device_node *remote_node, *endpoint;
> struct resource *regs;
> + int irq_num;
> int comp_id;
> int ret;
>
> @@ -894,6 +970,22 @@ static int mtk_dsi_probe(struct platform_device *pdev)
> return ret;
> }
>
> + irq_num = platform_get_irq(pdev, 0);
> + if (irq_num < 0) {
> + dev_err(&pdev->dev, "failed to request dsi irq resource\n");
> + return -EPROBE_DEFER;
> + }
> +
> + irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
> + ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
> + IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
> + return -EPROBE_DEFER;
> + }
> +
> + init_waitqueue_head(&dsi->irq_wait_queue);
> +
> platform_set_drvdata(pdev, dsi);
>
> return component_add(&pdev->dev, &mtk_dsi_component_ops);
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* [PATCH 6/6] dt-bindings: mt8173-mtu3: add reference clock
From: Chunfeng Yun @ 2017-01-18 6:08 UTC (permalink / raw)
To: Mathias Nyman, Felipe Balbi
Cc: Greg Kroah-Hartman, Matthias Brugger, Rob Herring, Mark Rutland,
Ian Campbell, Chunfeng Yun, linux-kernel, linux-arm-kernel,
linux-usb, linux-mediatek, devicetree
In-Reply-To: <1484719707-12107-1-git-send-email-chunfeng.yun@mediatek.com>
add a reference clock for compatibility
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../devicetree/bindings/usb/mt8173-mtu3.txt | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt b/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
index e049d19..8c976cd 100644
--- a/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
+++ b/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
@@ -10,7 +10,7 @@ Required properties:
- vusb33-supply : regulator of USB avdd3.3v
- clocks : a list of phandle + clock-specifier pairs, one for each
entry in clock-names
- - clock-names : must contain "sys_ck" for clock of controller;
+ - clock-names : must contain "sys_ck" and "ref_ck" for clock of controller;
"wakeup_deb_p0" and "wakeup_deb_p1" are optional, they are
depends on "mediatek,enable-wakeup"
- phys : a list of phandle + phy specifier pairs
@@ -56,10 +56,10 @@ ssusb: usb@11271000 {
phys = <&phy_port0 PHY_TYPE_USB3>,
<&phy_port1 PHY_TYPE_USB2>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>,
+ clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
<&pericfg CLK_PERI_USB0>,
<&pericfg CLK_PERI_USB1>;
- clock-names = "sys_ck",
+ clock-names = "sys_ck", "ref_ck",
"wakeup_deb_p0",
"wakeup_deb_p1";
vusb33-supply = <&mt6397_vusb_reg>;
@@ -79,8 +79,8 @@ ssusb: usb@11271000 {
reg-names = "mac";
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>;
- clock-names = "sys_ck";
+ clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
+ clock-names = "sys_ck", "ref_ck";
vusb33-supply = <&mt6397_vusb_reg>;
status = "disabled";
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 5/6] dt-bindings: mt8173-xhci: add reference clock
From: Chunfeng Yun @ 2017-01-18 6:08 UTC (permalink / raw)
To: Mathias Nyman, Felipe Balbi
Cc: Greg Kroah-Hartman, Matthias Brugger, Rob Herring, Mark Rutland,
Ian Campbell, Chunfeng Yun, linux-kernel, linux-arm-kernel,
linux-usb, linux-mediatek, devicetree
In-Reply-To: <1484719707-12107-1-git-send-email-chunfeng.yun@mediatek.com>
add a reference clock for compatibility
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../devicetree/bindings/usb/mt8173-xhci.txt | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
index 2a930bd..ab8bb27 100644
--- a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
@@ -23,6 +23,7 @@ Required properties:
entry in clock-names
- clock-names : must contain
"sys_ck": for clock of xHCI MAC
+ "ref_ck": for reference clock of xHCI MAC
"wakeup_deb_p0": for USB wakeup debounce clock of port0
"wakeup_deb_p1": for USB wakeup debounce clock of port1
@@ -47,10 +48,10 @@ usb30: usb@11270000 {
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>,
+ clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
<&pericfg CLK_PERI_USB0>,
<&pericfg CLK_PERI_USB1>;
- clock-names = "sys_ck",
+ clock-names = "sys_ck", "ref_ck",
"wakeup_deb_p0",
"wakeup_deb_p1";
phys = <&phy_port0 PHY_TYPE_USB3>,
@@ -82,6 +83,7 @@ Required properties:
entry in clock-names
- clock-names : must be
"sys_ck": for clock of xHCI MAC
+ "ref_ck": for reference clock of xHCI MAC
Optional properties:
- vbus-supply : reference to the VBUS regulator;
@@ -94,8 +96,8 @@ usb30: usb@11270000 {
reg-names = "mac";
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>;
- clock-names = "sys_ck";
+ clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
+ clock-names = "sys_ck", "ref_ck";
vusb33-supply = <&mt6397_vusb_reg>;
usb3-lpm-capable;
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 4/6] arm64: dts: mt8173: add reference clock for usb
From: Chunfeng Yun @ 2017-01-18 6:08 UTC (permalink / raw)
To: Mathias Nyman, Felipe Balbi
Cc: Greg Kroah-Hartman, Matthias Brugger, Rob Herring, Mark Rutland,
Ian Campbell, Chunfeng Yun, linux-kernel, linux-arm-kernel,
linux-usb, linux-mediatek, devicetree
In-Reply-To: <1484719707-12107-1-git-send-email-chunfeng.yun@mediatek.com>
add 26M reference clock for ssusb and xhci nodes
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 07fd2eb..e2862b6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -729,9 +729,11 @@
<&u2port1 PHY_TYPE_USB2>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
clocks = <&topckgen CLK_TOP_USB30_SEL>,
+ <&clk26m>,
<&pericfg CLK_PERI_USB0>,
<&pericfg CLK_PERI_USB1>;
clock-names = "sys_ck",
+ "ref_ck",
"wakeup_deb_p0",
"wakeup_deb_p1";
mediatek,syscon-wakeup = <&pericfg>;
@@ -746,8 +748,8 @@
reg-names = "mac";
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>;
- clock-names = "sys_ck";
+ clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
+ clock-names = "sys_ck", "ref_ck";
status = "disabled";
};
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 3/6] usb: xhci-mtk: add reference clock
From: Chunfeng Yun @ 2017-01-18 6:08 UTC (permalink / raw)
To: Mathias Nyman, Felipe Balbi
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Ian Campbell,
Greg Kroah-Hartman, linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Chunfeng Yun, Rob Herring,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Matthias Brugger,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1484719707-12107-1-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
usually, the reference clock comes from 26M oscillator directly,
but some SoCs are not, add it for compatibility.
Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/usb/host/xhci-mtk.c | 15 +++++++++++++++
drivers/usb/host/xhci-mtk.h | 1 +
2 files changed, 16 insertions(+)
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 1094ebd..4d75ac5 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -212,6 +212,12 @@ static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
{
int ret;
+ ret = clk_prepare_enable(mtk->ref_clk);
+ if (ret) {
+ dev_err(mtk->dev, "failed to enable ref_clk\n");
+ goto ref_clk_err;
+ }
+
ret = clk_prepare_enable(mtk->sys_clk);
if (ret) {
dev_err(mtk->dev, "failed to enable sys_clk\n");
@@ -238,6 +244,8 @@ static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
usb_p0_err:
clk_disable_unprepare(mtk->sys_clk);
sys_clk_err:
+ clk_disable_unprepare(mtk->ref_clk);
+ref_clk_err:
return -EINVAL;
}
@@ -248,6 +256,7 @@ static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
clk_disable_unprepare(mtk->wk_deb_p0);
}
clk_disable_unprepare(mtk->sys_clk);
+ clk_disable_unprepare(mtk->ref_clk);
}
/* only clocks can be turn off for ip-sleep wakeup mode */
@@ -550,6 +559,12 @@ static int xhci_mtk_probe(struct platform_device *pdev)
return PTR_ERR(mtk->sys_clk);
}
+ mtk->ref_clk = devm_clk_get(dev, "ref_ck");
+ if (IS_ERR(mtk->ref_clk)) {
+ dev_err(dev, "fail to get ref_ck\n");
+ return PTR_ERR(mtk->ref_clk);
+ }
+
mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
ret = usb_wakeup_of_property_parse(mtk, node);
diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
index 2845c49..3aa5e1d 100644
--- a/drivers/usb/host/xhci-mtk.h
+++ b/drivers/usb/host/xhci-mtk.h
@@ -124,6 +124,7 @@ struct xhci_hcd_mtk {
struct regulator *vusb33;
struct regulator *vbus;
struct clk *sys_clk; /* sys and mac clock */
+ struct clk *ref_clk;
struct clk *wk_deb_p0; /* port0's wakeup debounce clock */
struct clk *wk_deb_p1;
struct regmap *pericfg;
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/6] usb: mtu3: add reference clock
From: Chunfeng Yun @ 2017-01-18 6:08 UTC (permalink / raw)
To: Mathias Nyman, Felipe Balbi
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Ian Campbell,
Greg Kroah-Hartman, linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Chunfeng Yun, Rob Herring,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Matthias Brugger,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1484719707-12107-1-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
usually, the reference clock comes from 26M oscillator directly,
but some SoCs are not, add it for compatibility.
Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/usb/mtu3/mtu3.h | 1 +
drivers/usb/mtu3/mtu3_plat.c | 21 +++++++++++++++++++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/mtu3/mtu3.h b/drivers/usb/mtu3/mtu3.h
index ba9df71..aa6fd6a 100644
--- a/drivers/usb/mtu3/mtu3.h
+++ b/drivers/usb/mtu3/mtu3.h
@@ -225,6 +225,7 @@ struct ssusb_mtk {
/* common power & clock */
struct regulator *vusb33;
struct clk *sys_clk;
+ struct clk *ref_clk;
/* otg */
struct otg_switch_mtk otg_switch;
enum usb_dr_mode dr_mode;
diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
index 6344859..19a345d 100644
--- a/drivers/usb/mtu3/mtu3_plat.c
+++ b/drivers/usb/mtu3/mtu3_plat.c
@@ -123,7 +123,13 @@ static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
ret = clk_prepare_enable(ssusb->sys_clk);
if (ret) {
dev_err(ssusb->dev, "failed to enable sys_clk\n");
- goto clk_err;
+ goto sys_clk_err;
+ }
+
+ ret = clk_prepare_enable(ssusb->ref_clk);
+ if (ret) {
+ dev_err(ssusb->dev, "failed to enable ref_clk\n");
+ goto ref_clk_err;
}
ret = ssusb_phy_init(ssusb);
@@ -143,8 +149,10 @@ static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
phy_err:
ssusb_phy_exit(ssusb);
phy_init_err:
+ clk_disable_unprepare(ssusb->ref_clk);
+ref_clk_err:
clk_disable_unprepare(ssusb->sys_clk);
-clk_err:
+sys_clk_err:
regulator_disable(ssusb->vusb33);
vusb33_err:
@@ -154,6 +162,7 @@ static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
{
clk_disable_unprepare(ssusb->sys_clk);
+ clk_disable_unprepare(ssusb->ref_clk);
regulator_disable(ssusb->vusb33);
ssusb_phy_power_off(ssusb);
ssusb_phy_exit(ssusb);
@@ -216,6 +225,12 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
return PTR_ERR(ssusb->sys_clk);
}
+ ssusb->ref_clk = devm_clk_get(dev, "ref_ck");
+ if (IS_ERR(ssusb->ref_clk)) {
+ dev_err(dev, "failed to get ref clock\n");
+ return PTR_ERR(ssusb->ref_clk);
+ }
+
ssusb->num_phys = of_count_phandle_with_args(node,
"phys", "#phy-cells");
if (ssusb->num_phys > 0) {
@@ -428,6 +443,7 @@ static int __maybe_unused mtu3_suspend(struct device *dev)
ssusb_host_disable(ssusb, true);
ssusb_phy_power_off(ssusb);
clk_disable_unprepare(ssusb->sys_clk);
+ clk_disable_unprepare(ssusb->ref_clk);
ssusb_wakeup_enable(ssusb);
return 0;
@@ -445,6 +461,7 @@ static int __maybe_unused mtu3_resume(struct device *dev)
ssusb_wakeup_disable(ssusb);
clk_prepare_enable(ssusb->sys_clk);
+ clk_prepare_enable(ssusb->ref_clk);
ssusb_phy_power_on(ssusb);
ssusb_host_enable(ssusb);
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/6] usb: mtu3: get resources that cause deferred probe earlier
From: Chunfeng Yun @ 2017-01-18 6:08 UTC (permalink / raw)
To: Mathias Nyman, Felipe Balbi
Cc: Greg Kroah-Hartman, Matthias Brugger, Rob Herring, Mark Rutland,
Ian Campbell, Chunfeng Yun, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Some resources such as regulator, clock usually cause deferred
probe, get them earlier to avoid more ineffective processing.
Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/usb/mtu3/mtu3_plat.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
index 7833678..6344859 100644
--- a/drivers/usb/mtu3/mtu3_plat.c
+++ b/drivers/usb/mtu3/mtu3_plat.c
@@ -204,6 +204,18 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
int i;
int ret;
+ ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
+ if (IS_ERR(ssusb->vusb33)) {
+ dev_err(dev, "failed to get vusb33\n");
+ return PTR_ERR(ssusb->vusb33);
+ }
+
+ ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
+ if (IS_ERR(ssusb->sys_clk)) {
+ dev_err(dev, "failed to get sys clock\n");
+ return PTR_ERR(ssusb->sys_clk);
+ }
+
ssusb->num_phys = of_count_phandle_with_args(node,
"phys", "#phy-cells");
if (ssusb->num_phys > 0) {
@@ -230,18 +242,6 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
return PTR_ERR(ssusb->ippc_base);
}
- ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
- if (IS_ERR(ssusb->vusb33)) {
- dev_err(dev, "failed to get vusb33\n");
- return PTR_ERR(ssusb->vusb33);
- }
-
- ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
- if (IS_ERR(ssusb->sys_clk)) {
- dev_err(dev, "failed to get sys clock\n");
- return PTR_ERR(ssusb->sys_clk);
- }
-
ssusb->dr_mode = usb_get_dr_mode(dev);
if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) {
dev_err(dev, "dr_mode is error\n");
--
1.7.9.5
--
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^ permalink raw reply related
* [RESEND PATCH 6/6] dt-bindings: phy-mt65xx-usb: add support for mt2712 platform
From: Chunfeng Yun @ 2017-01-18 6:00 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Matthias Brugger, Felipe Balbi, Rob Herring, Mark Rutland,
Ian Campbell, Chunfeng Yun, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1484719214-11989-1-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
add a new compatible string for "mt2712", and a new reference clock
for SuperSpeed analog phy;
Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
.../devicetree/bindings/phy/phy-mt65xx-usb.txt | 81 +++++++++++++++++---
1 file changed, 70 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
index 33a2b1e..8f91136 100644
--- a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
@@ -6,19 +6,25 @@ This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
Required properties (controller (parent) node):
- compatible : should be one of
"mediatek,mt2701-u3phy"
+ "mediatek,mt2712-u3phy"
"mediatek,mt8173-u3phy"
- - reg : offset and length of register for phy, exclude port's
- register.
- clocks : a list of phandle + clock-specifier pairs, one for each
entry in clock-names
- clock-names : must contain
- "u3phya_ref": for reference clock of usb3.0 analog phy.
+ "u2ref_clk": 48M reference clock of HighSpeed analog phy.
+ "u3ref_clk": 26M reference clock of SuperSpeed analog phy,
+ sometimes is 24M, 25M or 27M, depended on platform.
Required nodes : a sub-node is required for each port the controller
provides. Address range information including the usual
'reg' property is used inside these nodes to describe
the controller's topology.
+Optional properties (controller (parent) node):
+ - reg : offset and length of register shared by multiple ports,
+ exclude port's private register. It is needed on mt2701
+ and mt8173, but not on mt2712.
+
Required properties (port (child) node):
- reg : address and length of the register set for the port.
- #phy-cells : should be 1 (See second example)
@@ -31,21 +37,27 @@ Example:
u3phy: usb-phy@11290000 {
compatible = "mediatek,mt8173-u3phy";
reg = <0 0x11290000 0 0x800>;
- clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
- clock-names = "u3phya_ref";
+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk26m>;
+ clock-names = "u2ref_clk", "u3ref_clk";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "okay";
- phy_port0: port@11290800 {
- reg = <0 0x11290800 0 0x800>;
+ u2port0: port@11290800 {
+ reg = <0 0x11290800 0 0x100>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: port@11290900 {
+ reg = <0 0x11290800 0 0x700>;
#phy-cells = <1>;
status = "okay";
};
- phy_port1: port@11291000 {
- reg = <0 0x11291000 0 0x800>;
+ u2port1: port@11291000 {
+ reg = <0 0x11291000 0 0x100>;
#phy-cells = <1>;
status = "okay";
};
@@ -64,7 +76,54 @@ Example:
usb30: usb@11270000 {
...
- phys = <&phy_port0 PHY_TYPE_USB3>;
- phy-names = "usb3-0";
+ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+ phy-names = "usb2-0", "usb3-0";
...
};
+
+
+Layout differences of banks between mt8173/mt2701 and mt2712
+-------------------------------------------------------------
+mt8173 and mt2701:
+port offset bank
+shared 0x0000 SPLLC
+ 0x0100 FMREG
+u2 port0 0x0800 U2PHY_COM
+u3 port0 0x0900 U3PHYD
+ 0x0a00 U3PHYD_BANK2
+ 0x0b00 U3PHYA
+ 0x0c00 U3PHYA_DA
+u2 port1 0x1000 U2PHY_COM
+u3 port1 0x1100 U3PHYD
+ 0x1200 U3PHYD_BANK2
+ 0x1300 U3PHYA
+ 0x1400 U3PHYA_DA
+u2 port2 0x1800 U2PHY_COM
+ ...
+
+mt2712:
+port offset bank
+u2 port0 0x0000 MISC
+ 0x0100 FMREG
+ 0x0300 U2PHY_COM
+u3 port0 0x0700 SPLLC
+ 0x0800 CHIP
+ 0x0900 U3PHYD
+ 0x0a00 U3PHYD_BANK2
+ 0x0b00 U3PHYA
+ 0x0c00 U3PHYA_DA
+u2 port1 0x1000 MISC
+ 0x1100 FMREG
+ 0x1300 U2PHY_COM
+u3 port1 0x1700 SPLLC
+ 0x1800 CHIP
+ 0x1900 U3PHYD
+ 0x1a00 U3PHYD_BANK2
+ 0x1b00 U3PHYA
+ 0x1c00 U3PHYA_DA
+u2 port2 0x2000 MISC
+ ...
+
+ SPLLC shared by u3 ports and FMREG shared by u2 ports on
+mt8173/mt2701 are put back into each port; a new bank MISC for
+u2 ports and CHIP for u3 ports are added on mt2712.
--
1.7.9.5
--
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^ permalink raw reply related
* [RESEND PATCH 5/6] arm64: dts: mt8173: split usb SuperSpeed port into two ports
From: Chunfeng Yun @ 2017-01-18 6:00 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Felipe Balbi,
Ian Campbell, linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Chunfeng Yun, Rob Herring,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Matthias Brugger,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1484719214-11989-1-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
split the old SuperSpeed port node into a HighSpeed one and a new
SuperSpeed one.
Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 5d1663b..07fd2eb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -724,8 +724,9 @@
<0 0x11280700 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
- phys = <&phy_port0 PHY_TYPE_USB3>,
- <&phy_port1 PHY_TYPE_USB2>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
clocks = <&topckgen CLK_TOP_USB30_SEL>,
<&pericfg CLK_PERI_USB0>,
@@ -761,14 +762,20 @@
ranges;
status = "okay";
- phy_port0: port@11290800 {
- reg = <0 0x11290800 0 0x800>;
+ u2port0: port@11290800 {
+ reg = <0 0x11290800 0 0x100>;
#phy-cells = <1>;
status = "okay";
};
- phy_port1: port@11291000 {
- reg = <0 0x11291000 0 0x800>;
+ u3port0: port@11290900 {
+ reg = <0 0x11290900 0 0x700>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u2port1: port@11291000 {
+ reg = <0 0x11291000 0 0x100>;
#phy-cells = <1>;
status = "okay";
};
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH 4/6] arm64: dts: mt8173: add a new reference clock for usb3 analog phy
From: Chunfeng Yun @ 2017-01-18 6:00 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Mark Rutland, devicetree, Felipe Balbi, Ian Campbell, linux-usb,
linux-kernel, Chunfeng Yun, Rob Herring, linux-mediatek,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <1484719214-11989-1-git-send-email-chunfeng.yun@mediatek.com>
add a new reference clock which comes from 26M oscillator directly
for SuperSpeed analog phy. and the old one which comes for PLL is
48M for HighSpeed analog phy.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 12e7027..5d1663b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -754,8 +754,8 @@
u3phy: usb-phy@11290000 {
compatible = "mediatek,mt8173-u3phy";
reg = <0 0x11290000 0 0x800>;
- clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
- clock-names = "u3phya_ref";
+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk26m>;
+ clock-names = "u2ref_clk", "u3ref_clk";
#address-cells = <2>;
#size-cells = <2>;
ranges;
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH 3/6] phy: phy-mt65xx-usb3: add support for mt2712 platform
From: Chunfeng Yun @ 2017-01-18 6:00 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Matthias Brugger, Felipe Balbi, Rob Herring, Mark Rutland,
Ian Campbell, Chunfeng Yun, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1484719214-11989-1-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
There are some variations from mt2701 to mt2712:
1. banks shared by multiple ports are put back into each port,
such as SPLLC and U2FREQ;
2. add a new bank MISC for u2port, and CHIP for u3port;
3. bank's offset in each port are also rearranged;
Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/phy/phy-mt65xx-usb3.c | 326 ++++++++++++++++++++++++++---------------
1 file changed, 208 insertions(+), 118 deletions(-)
diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
index c187a3b..d515c69 100644
--- a/drivers/phy/phy-mt65xx-usb3.c
+++ b/drivers/phy/phy-mt65xx-usb3.c
@@ -23,46 +23,54 @@
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
-/*
- * for sifslv2 register, but exclude port's;
- * relative to USB3_SIF2_BASE base address
- */
-#define SSUSB_SIFSLV_SPLLC 0x0000
-#define SSUSB_SIFSLV_U2FREQ 0x0100
-
-/* offsets of banks in each u2phy registers */
-#define SSUSB_SIFSLV_U2PHY_COM_BASE 0x0000
-/* offsets of banks in each u3phy registers */
-#define SSUSB_SIFSLV_U3PHYD_BASE 0x0000
-#define SSUSB_SIFSLV_U3PHYA_BASE 0x0200
-
-#define U3P_USBPHYACR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0000)
+/* version V1 sub-banks offset base address */
+/* banks shared by multiple phys */
+#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
+#define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
+/* u2 phy bank */
+#define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
+/* u3 phy banks */
+#define SSUSB_SIFSLV_V1_U3PHYD 0x000
+#define SSUSB_SIFSLV_V1_U3PHYA 0x200
+
+/* version V2 sub-banks offset base address */
+/* u2 phy banks */
+#define SSUSB_SIFSLV_V2_MISC 0x000
+#define SSUSB_SIFSLV_V2_U2FREQ 0x100
+#define SSUSB_SIFSLV_V2_U2PHY_COM 0x300
+/* u3 phy banks */
+#define SSUSB_SIFSLV_V2_SPLLC 0x000
+#define SSUSB_SIFSLV_V2_CHIP 0x100
+#define SSUSB_SIFSLV_V2_U3PHYD 0x200
+#define SSUSB_SIFSLV_V2_U3PHYA 0x400
+
+#define U3P_USBPHYACR0 0x000
#define PA0_RG_U2PLL_FORCE_ON BIT(15)
-#define U3P_USBPHYACR2 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0008)
+#define U3P_USBPHYACR2 0x008
#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
-#define U3P_USBPHYACR5 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0014)
+#define U3P_USBPHYACR5 0x014
#define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
#define PA5_RG_U2_HS_100U_U3_EN BIT(11)
-#define U3P_USBPHYACR6 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0018)
+#define U3P_USBPHYACR6 0x018
#define PA6_RG_U2_BC11_SW_EN BIT(23)
#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
#define PA6_RG_U2_SQTH GENMASK(3, 0)
#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
-#define U3P_U2PHYACR4 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0020)
+#define U3P_U2PHYACR4 0x020
#define P2C_RG_USB20_GPIO_CTL BIT(9)
#define P2C_USB20_GPIO_MODE BIT(8)
#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
-#define U3D_U2PHYDCR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0060)
+#define U3D_U2PHYDCR0 0x060
#define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24)
-#define U3P_U2PHYDTM0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0068)
+#define U3P_U2PHYDTM0 0x068
#define P2C_FORCE_UART_EN BIT(26)
#define P2C_FORCE_DATAIN BIT(23)
#define P2C_FORCE_DM_PULLDOWN BIT(21)
@@ -84,47 +92,44 @@
P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
-#define U3P_U2PHYDTM1 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x006C)
+#define U3P_U2PHYDTM1 0x06C
#define P2C_RG_UART_EN BIT(16)
#define P2C_RG_VBUSVALID BIT(5)
#define P2C_RG_SESSEND BIT(4)
#define P2C_RG_AVALID BIT(2)
-#define U3P_U3_PHYA_REG0 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0000)
-#define P3A_RG_U3_VUSB10_ON BIT(5)
-
-#define U3P_U3_PHYA_REG6 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0018)
+#define U3P_U3_PHYA_REG6 0x018
#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
-#define U3P_U3_PHYA_REG9 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0024)
+#define U3P_U3_PHYA_REG9 0x024
#define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
-#define U3P_U3PHYA_DA_REG0 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0100)
+#define U3P_U3_PHYA_DA_REG0 0x100
#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
-#define U3P_PHYD_CDR1 (SSUSB_SIFSLV_U3PHYD_BASE + 0x005c)
+#define U3P_U3_PHYD_CDR1 0x05c
#define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
#define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
-#define U3P_XTALCTL3 (SSUSB_SIFSLV_SPLLC + 0x0018)
+#define U3P_SPLLC_XTALCTL3 0x018
#define XC3_RG_U3_XTAL_RX_PWD BIT(9)
#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
-#define U3P_U2FREQ_FMCR0 (SSUSB_SIFSLV_U2FREQ + 0x00)
+#define U3P_U2FREQ_FMCR0 0x00
#define P2F_RG_MONCLK_SEL GENMASK(27, 26)
#define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26)
#define P2F_RG_FREQDET_EN BIT(24)
#define P2F_RG_CYCLECNT GENMASK(23, 0)
#define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
-#define U3P_U2FREQ_VALUE (SSUSB_SIFSLV_U2FREQ + 0x0c)
+#define U3P_U2FREQ_VALUE 0x0c
-#define U3P_U2FREQ_FMMONR1 (SSUSB_SIFSLV_U2FREQ + 0x10)
+#define U3P_U2FREQ_FMMONR1 0x10
#define P2F_USB_FM_VALID BIT(0)
#define P2F_RG_FRCK_EN BIT(8)
@@ -133,14 +138,37 @@
#define U3P_SR_COEF_DIVISOR 1000
#define U3P_FM_DET_CYCLE_CNT 1024
+enum mt_phy_version {
+ MT_PHY_V1 = 1,
+ MT_PHY_V2,
+};
+
struct mt65xx_phy_pdata {
/* avoid RX sensitivity level degradation only for mt8173 */
bool avoid_rx_sen_degradation;
+ enum mt_phy_version version;
+};
+
+struct u2phy_banks {
+ void __iomem *misc;
+ void __iomem *fmreg;
+ void __iomem *com;
+};
+
+struct u3phy_banks {
+ void __iomem *spllc;
+ void __iomem *chip;
+ void __iomem *phyd; /* include u3phyd_bank2 */
+ void __iomem *phya; /* include u3phya_da */
};
struct mt65xx_phy_instance {
struct phy *phy;
void __iomem *port_base;
+ union {
+ struct u2phy_banks u2_banks;
+ struct u3phy_banks u3_banks;
+ };
u32 index;
u8 type;
};
@@ -158,49 +186,53 @@ struct mt65xx_u3phy {
static void hs_slew_rate_calibrate(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
- void __iomem *sif_base = u3phy->sif_base;
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *fmreg = u2_banks->fmreg;
+ void __iomem *com = u2_banks->com;
int calibration_val;
int fm_out;
u32 tmp;
/* enable USB ring oscillator */
- tmp = readl(instance->port_base + U3P_USBPHYACR5);
+ tmp = readl(com + U3P_USBPHYACR5);
tmp |= PA5_RG_U2_HSTX_SRCAL_EN;
- writel(tmp, instance->port_base + U3P_USBPHYACR5);
+ writel(tmp, com + U3P_USBPHYACR5);
udelay(1);
/*enable free run clock */
- tmp = readl(sif_base + U3P_U2FREQ_FMMONR1);
+ tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
tmp |= P2F_RG_FRCK_EN;
- writel(tmp, sif_base + U3P_U2FREQ_FMMONR1);
+ writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
/* set cycle count as 1024, and select u2 channel */
- tmp = readl(sif_base + U3P_U2FREQ_FMCR0);
+ tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
- tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
- writel(tmp, sif_base + U3P_U2FREQ_FMCR0);
+ if (u3phy->pdata->version == MT_PHY_V1)
+ tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
+
+ writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
/* enable frequency meter */
- tmp = readl(sif_base + U3P_U2FREQ_FMCR0);
+ tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
tmp |= P2F_RG_FREQDET_EN;
- writel(tmp, sif_base + U3P_U2FREQ_FMCR0);
+ writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
/* ignore return value */
- readl_poll_timeout(sif_base + U3P_U2FREQ_FMMONR1, tmp,
+ readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp,
(tmp & P2F_USB_FM_VALID), 10, 200);
- fm_out = readl(sif_base + U3P_U2FREQ_VALUE);
+ fm_out = readl(fmreg + U3P_U2FREQ_VALUE);
/* disable frequency meter */
- tmp = readl(sif_base + U3P_U2FREQ_FMCR0);
+ tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
tmp &= ~P2F_RG_FREQDET_EN;
- writel(tmp, sif_base + U3P_U2FREQ_FMCR0);
+ writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
/*disable free run clock */
- tmp = readl(sif_base + U3P_U2FREQ_FMMONR1);
+ tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
tmp &= ~P2F_RG_FRCK_EN;
- writel(tmp, sif_base + U3P_U2FREQ_FMMONR1);
+ writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
if (fm_out) {
/* ( 1024 / FM_OUT ) x reference clock frequency x 0.028 */
@@ -215,48 +247,48 @@ static void hs_slew_rate_calibrate(struct mt65xx_u3phy *u3phy,
instance->index, fm_out, calibration_val);
/* set HS slew rate */
- tmp = readl(instance->port_base + U3P_USBPHYACR5);
+ tmp = readl(com + U3P_USBPHYACR5);
tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val);
- writel(tmp, instance->port_base + U3P_USBPHYACR5);
+ writel(tmp, com + U3P_USBPHYACR5);
/* disable USB ring oscillator */
- tmp = readl(instance->port_base + U3P_USBPHYACR5);
+ tmp = readl(com + U3P_USBPHYACR5);
tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN;
- writel(tmp, instance->port_base + U3P_USBPHYACR5);
+ writel(tmp, com + U3P_USBPHYACR5);
}
static void u3_phy_instance_init(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
- void __iomem *port_base = instance->port_base;
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
u32 tmp;
/* gating PCIe Analog XTAL clock */
- tmp = readl(u3phy->sif_base + U3P_XTALCTL3);
+ tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3);
tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
- writel(tmp, u3phy->sif_base + U3P_XTALCTL3);
+ writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3);
/* gating XSQ */
- tmp = readl(port_base + U3P_U3PHYA_DA_REG0);
+ tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
- writel(tmp, port_base + U3P_U3PHYA_DA_REG0);
+ writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
- tmp = readl(port_base + U3P_U3_PHYA_REG9);
+ tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9);
tmp &= ~P3A_RG_RX_DAC_MUX;
tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
- writel(tmp, port_base + U3P_U3_PHYA_REG9);
+ writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9);
- tmp = readl(port_base + U3P_U3_PHYA_REG6);
+ tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6);
tmp &= ~P3A_RG_TX_EIDLE_CM;
tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
- writel(tmp, port_base + U3P_U3_PHYA_REG6);
+ writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6);
- tmp = readl(port_base + U3P_PHYD_CDR1);
+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1);
tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
- writel(tmp, port_base + U3P_PHYD_CDR1);
+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1);
dev_dbg(u3phy->dev, "%s(%d)\n", __func__, instance->index);
}
@@ -264,51 +296,52 @@ static void u3_phy_instance_init(struct mt65xx_u3phy *u3phy,
static void phy_instance_init(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
- void __iomem *port_base = instance->port_base;
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *com = u2_banks->com;
u32 index = instance->index;
u32 tmp;
/* switch to USB function. (system register, force ip into usb mode) */
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp &= ~P2C_FORCE_UART_EN;
tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0);
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
- tmp = readl(port_base + U3P_U2PHYDTM1);
+ tmp = readl(com + U3P_U2PHYDTM1);
tmp &= ~P2C_RG_UART_EN;
- writel(tmp, port_base + U3P_U2PHYDTM1);
+ writel(tmp, com + U3P_U2PHYDTM1);
if (!index) {
- tmp = readl(port_base + U3P_U2PHYACR4);
+ tmp = readl(com + U3P_U2PHYACR4);
tmp &= ~P2C_U2_GPIO_CTR_MSK;
- writel(tmp, port_base + U3P_U2PHYACR4);
+ writel(tmp, com + U3P_U2PHYACR4);
}
if (u3phy->pdata->avoid_rx_sen_degradation) {
if (!index) {
- tmp = readl(port_base + U3P_USBPHYACR2);
+ tmp = readl(com + U3P_USBPHYACR2);
tmp |= PA2_RG_SIF_U2PLL_FORCE_EN;
- writel(tmp, port_base + U3P_USBPHYACR2);
+ writel(tmp, com + U3P_USBPHYACR2);
- tmp = readl(port_base + U3D_U2PHYDCR0);
+ tmp = readl(com + U3D_U2PHYDCR0);
tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
- writel(tmp, port_base + U3D_U2PHYDCR0);
+ writel(tmp, com + U3D_U2PHYDCR0);
} else {
- tmp = readl(port_base + U3D_U2PHYDCR0);
+ tmp = readl(com + U3D_U2PHYDCR0);
tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
- writel(tmp, port_base + U3D_U2PHYDCR0);
+ writel(tmp, com + U3D_U2PHYDCR0);
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
}
}
- tmp = readl(port_base + U3P_USBPHYACR6);
+ tmp = readl(com + U3P_USBPHYACR6);
tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */
tmp &= ~PA6_RG_U2_SQTH;
tmp |= PA6_RG_U2_SQTH_VAL(2);
- writel(tmp, port_base + U3P_USBPHYACR6);
+ writel(tmp, com + U3P_USBPHYACR6);
dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
}
@@ -316,41 +349,42 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy,
static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
- void __iomem *port_base = instance->port_base;
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *com = u2_banks->com;
u32 index = instance->index;
u32 tmp;
/* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp &= ~(P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL);
tmp &= ~(P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
/* OTG Enable */
- tmp = readl(port_base + U3P_USBPHYACR6);
+ tmp = readl(com + U3P_USBPHYACR6);
tmp |= PA6_RG_U2_OTG_VBUSCMP_EN;
- writel(tmp, port_base + U3P_USBPHYACR6);
+ writel(tmp, com + U3P_USBPHYACR6);
if (!index) {
/* switch 100uA current to SSUSB */
- tmp = readl(port_base + U3P_USBPHYACR5);
+ tmp = readl(com + U3P_USBPHYACR5);
tmp |= PA5_RG_U2_HS_100U_U3_EN;
- writel(tmp, port_base + U3P_USBPHYACR5);
+ writel(tmp, com + U3P_USBPHYACR5);
}
- tmp = readl(port_base + U3P_U2PHYDTM1);
+ tmp = readl(com + U3P_U2PHYDTM1);
tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID;
tmp &= ~P2C_RG_SESSEND;
- writel(tmp, port_base + U3P_U2PHYDTM1);
+ writel(tmp, com + U3P_U2PHYDTM1);
if (u3phy->pdata->avoid_rx_sen_degradation && index) {
- tmp = readl(port_base + U3D_U2PHYDCR0);
+ tmp = readl(com + U3D_U2PHYDCR0);
tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
- writel(tmp, port_base + U3D_U2PHYDCR0);
+ writel(tmp, com + U3D_U2PHYDCR0);
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
}
dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
}
@@ -358,42 +392,43 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
static void phy_instance_power_off(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
- void __iomem *port_base = instance->port_base;
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *com = u2_banks->com;
u32 index = instance->index;
u32 tmp;
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN);
tmp |= P2C_FORCE_SUSPENDM;
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
/* OTG Disable */
- tmp = readl(port_base + U3P_USBPHYACR6);
+ tmp = readl(com + U3P_USBPHYACR6);
tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN;
- writel(tmp, port_base + U3P_USBPHYACR6);
+ writel(tmp, com + U3P_USBPHYACR6);
if (!index) {
/* switch 100uA current back to USB2.0 */
- tmp = readl(port_base + U3P_USBPHYACR5);
+ tmp = readl(com + U3P_USBPHYACR5);
tmp &= ~PA5_RG_U2_HS_100U_U3_EN;
- writel(tmp, port_base + U3P_USBPHYACR5);
+ writel(tmp, com + U3P_USBPHYACR5);
}
/* let suspendm=0, set utmi into analog power down */
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp &= ~P2C_RG_SUSPENDM;
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
udelay(1);
- tmp = readl(port_base + U3P_U2PHYDTM1);
+ tmp = readl(com + U3P_U2PHYDTM1);
tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID);
tmp |= P2C_RG_SESSEND;
- writel(tmp, port_base + U3P_U2PHYDTM1);
+ writel(tmp, com + U3P_U2PHYDTM1);
if (u3phy->pdata->avoid_rx_sen_degradation && index) {
- tmp = readl(port_base + U3D_U2PHYDCR0);
+ tmp = readl(com + U3D_U2PHYDCR0);
tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
- writel(tmp, port_base + U3D_U2PHYDCR0);
+ writel(tmp, com + U3D_U2PHYDCR0);
}
dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
@@ -402,18 +437,55 @@ static void phy_instance_power_off(struct mt65xx_u3phy *u3phy,
static void phy_instance_exit(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
- void __iomem *port_base = instance->port_base;
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *com = u2_banks->com;
u32 index = instance->index;
u32 tmp;
if (u3phy->pdata->avoid_rx_sen_degradation && index) {
- tmp = readl(port_base + U3D_U2PHYDCR0);
+ tmp = readl(com + U3D_U2PHYDCR0);
tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
- writel(tmp, port_base + U3D_U2PHYDCR0);
+ writel(tmp, com + U3D_U2PHYDCR0);
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp &= ~P2C_FORCE_SUSPENDM;
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
+ }
+}
+
+static void phy_v1_banks_init(struct mt65xx_u3phy *u3phy,
+ struct mt65xx_phy_instance *instance)
+{
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
+
+ if (instance->type == PHY_TYPE_USB2) {
+ u2_banks->misc = NULL;
+ u2_banks->fmreg = u3phy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
+ u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
+ } else if (instance->type == PHY_TYPE_USB3) {
+ u3_banks->spllc = u3phy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
+ u3_banks->chip = NULL;
+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
+ }
+}
+
+static void phy_v2_banks_init(struct mt65xx_u3phy *u3phy,
+ struct mt65xx_phy_instance *instance)
+{
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
+
+ if (instance->type == PHY_TYPE_USB2) {
+ u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
+ u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
+ u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
+ } else if (instance->type == PHY_TYPE_USB3) {
+ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
+ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
}
}
@@ -490,7 +562,6 @@ static struct phy *mt65xx_phy_xlate(struct device *dev,
struct device_node *phy_np = args->np;
int index;
-
if (args->args_count != 1) {
dev_err(dev, "invalid number of cells in 'phy' property\n");
return ERR_PTR(-EINVAL);
@@ -508,13 +579,21 @@ static struct phy *mt65xx_phy_xlate(struct device *dev,
}
instance->type = args->args[0];
-
if (!(instance->type == PHY_TYPE_USB2 ||
instance->type == PHY_TYPE_USB3)) {
dev_err(dev, "unsupported device type: %d\n", instance->type);
return ERR_PTR(-EINVAL);
}
+ if (u3phy->pdata->version == MT_PHY_V1) {
+ phy_v1_banks_init(u3phy, instance);
+ } else if (u3phy->pdata->version == MT_PHY_V2) {
+ phy_v2_banks_init(u3phy, instance);
+ } else {
+ dev_err(dev, "phy version is not supported\n");
+ return ERR_PTR(-EINVAL);
+ }
+
return instance->phy;
}
@@ -528,14 +607,22 @@ static struct phy *mt65xx_phy_xlate(struct device *dev,
static const struct mt65xx_phy_pdata mt2701_pdata = {
.avoid_rx_sen_degradation = false,
+ .version = MT_PHY_V1,
+};
+
+static const struct mt65xx_phy_pdata mt2712_pdata = {
+ .avoid_rx_sen_degradation = false,
+ .version = MT_PHY_V2,
};
static const struct mt65xx_phy_pdata mt8173_pdata = {
.avoid_rx_sen_degradation = true,
+ .version = MT_PHY_V1,
};
static const struct of_device_id mt65xx_u3phy_id_table[] = {
{ .compatible = "mediatek,mt2701-u3phy", .data = &mt2701_pdata },
+ { .compatible = "mediatek,mt2712-u3phy", .data = &mt2712_pdata },
{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
{ },
};
@@ -571,11 +658,14 @@ static int mt65xx_u3phy_probe(struct platform_device *pdev)
u3phy->dev = dev;
platform_set_drvdata(pdev, u3phy);
- sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- u3phy->sif_base = devm_ioremap_resource(dev, sif_res);
- if (IS_ERR(u3phy->sif_base)) {
- dev_err(dev, "failed to remap sif regs\n");
- return PTR_ERR(u3phy->sif_base);
+ if (u3phy->pdata->version == MT_PHY_V1) {
+ /* get banks shared by multiple phys */
+ sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ u3phy->sif_base = devm_ioremap_resource(dev, sif_res);
+ if (IS_ERR(u3phy->sif_base)) {
+ dev_err(dev, "failed to remap sif regs\n");
+ return PTR_ERR(u3phy->sif_base);
+ }
}
u3phy->u2ref_clk = devm_clk_get(dev, "u2ref_clk");
--
1.7.9.5
--
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^ permalink raw reply related
* [RESEND PATCH 2/6] phy: phy-mt65xx-usb3: split SuperSpeed port into two ones
From: Chunfeng Yun @ 2017-01-18 6:00 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Felipe Balbi,
Ian Campbell, linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Chunfeng Yun, Rob Herring,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Matthias Brugger,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1484719214-11989-1-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Currently usb3 port in fact includes two sub-ports, but it is not
flexible for some cases, such as following one:
usb3 port0 includes u2port0 and u3port0;
usb2 port0 includes u2port1;
If wants to support only HS, we can use u2port0 or u2port1, when
select u2port0, u3port0 is not needed;
If wants to support SS, we can compound u2port0 and u3port0,
or u2port1 and u3port0, if select latter one, u2port0 is not needed.
So it's more flexible to split usb3 port into two ones and also try
best to save power by disabling unnecessary ports.
Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/phy/phy-mt65xx-usb3.c | 124 ++++++++++++++++++++---------------------
1 file changed, 61 insertions(+), 63 deletions(-)
diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
index fc9a4f0..c187a3b 100644
--- a/drivers/phy/phy-mt65xx-usb3.c
+++ b/drivers/phy/phy-mt65xx-usb3.c
@@ -30,11 +30,11 @@
#define SSUSB_SIFSLV_SPLLC 0x0000
#define SSUSB_SIFSLV_U2FREQ 0x0100
-/* offsets of sub-segment in each port registers */
+/* offsets of banks in each u2phy registers */
#define SSUSB_SIFSLV_U2PHY_COM_BASE 0x0000
-#define SSUSB_SIFSLV_U3PHYD_BASE 0x0100
-#define SSUSB_USB30_PHYA_SIV_B_BASE 0x0300
-#define SSUSB_SIFSLV_U3PHYA_DA_BASE 0x0400
+/* offsets of banks in each u3phy registers */
+#define SSUSB_SIFSLV_U3PHYD_BASE 0x0000
+#define SSUSB_SIFSLV_U3PHYA_BASE 0x0200
#define U3P_USBPHYACR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0000)
#define PA0_RG_U2PLL_FORCE_ON BIT(15)
@@ -49,7 +49,6 @@
#define PA5_RG_U2_HS_100U_U3_EN BIT(11)
#define U3P_USBPHYACR6 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0018)
-#define PA6_RG_U2_ISO_EN BIT(31)
#define PA6_RG_U2_BC11_SW_EN BIT(23)
#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
#define PA6_RG_U2_SQTH GENMASK(3, 0)
@@ -91,18 +90,18 @@
#define P2C_RG_SESSEND BIT(4)
#define P2C_RG_AVALID BIT(2)
-#define U3P_U3_PHYA_REG0 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0000)
+#define U3P_U3_PHYA_REG0 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0000)
#define P3A_RG_U3_VUSB10_ON BIT(5)
-#define U3P_U3_PHYA_REG6 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0018)
+#define U3P_U3_PHYA_REG6 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0018)
#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
-#define U3P_U3_PHYA_REG9 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0024)
+#define U3P_U3_PHYA_REG9 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0024)
#define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
-#define U3P_U3PHYA_DA_REG0 (SSUSB_SIFSLV_U3PHYA_DA_BASE + 0x0000)
+#define U3P_U3PHYA_DA_REG0 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0100)
#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
@@ -148,7 +147,7 @@ struct mt65xx_phy_instance {
struct mt65xx_u3phy {
struct device *dev;
- void __iomem *sif_base; /* include sif2, but exclude port's */
+ void __iomem *sif_base; /* only shared sif */
struct clk *u2ref_clk; /* reference clock of u2 analog phy */
struct clk *u3ref_clk; /* reference clock of u3 analog phy */
const struct mt65xx_phy_pdata *pdata;
@@ -179,7 +178,7 @@ static void hs_slew_rate_calibrate(struct mt65xx_u3phy *u3phy,
tmp = readl(sif_base + U3P_U2FREQ_FMCR0);
tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
- tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index);
+ tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
writel(tmp, sif_base + U3P_U2FREQ_FMCR0);
/* enable frequency meter */
@@ -227,6 +226,41 @@ static void hs_slew_rate_calibrate(struct mt65xx_u3phy *u3phy,
writel(tmp, instance->port_base + U3P_USBPHYACR5);
}
+static void u3_phy_instance_init(struct mt65xx_u3phy *u3phy,
+ struct mt65xx_phy_instance *instance)
+{
+ void __iomem *port_base = instance->port_base;
+ u32 tmp;
+
+ /* gating PCIe Analog XTAL clock */
+ tmp = readl(u3phy->sif_base + U3P_XTALCTL3);
+ tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
+ writel(tmp, u3phy->sif_base + U3P_XTALCTL3);
+
+ /* gating XSQ */
+ tmp = readl(port_base + U3P_U3PHYA_DA_REG0);
+ tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
+ tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
+ writel(tmp, port_base + U3P_U3PHYA_DA_REG0);
+
+ tmp = readl(port_base + U3P_U3_PHYA_REG9);
+ tmp &= ~P3A_RG_RX_DAC_MUX;
+ tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
+ writel(tmp, port_base + U3P_U3_PHYA_REG9);
+
+ tmp = readl(port_base + U3P_U3_PHYA_REG6);
+ tmp &= ~P3A_RG_TX_EIDLE_CM;
+ tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
+ writel(tmp, port_base + U3P_U3_PHYA_REG6);
+
+ tmp = readl(port_base + U3P_PHYD_CDR1);
+ tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
+ tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
+ writel(tmp, port_base + U3P_PHYD_CDR1);
+
+ dev_dbg(u3phy->dev, "%s(%d)\n", __func__, instance->index);
+}
+
static void phy_instance_init(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
@@ -276,26 +310,6 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy,
tmp |= PA6_RG_U2_SQTH_VAL(2);
writel(tmp, port_base + U3P_USBPHYACR6);
- tmp = readl(port_base + U3P_U3PHYA_DA_REG0);
- tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
- tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
- writel(tmp, port_base + U3P_U3PHYA_DA_REG0);
-
- tmp = readl(port_base + U3P_U3_PHYA_REG9);
- tmp &= ~P3A_RG_RX_DAC_MUX;
- tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
- writel(tmp, port_base + U3P_U3_PHYA_REG9);
-
- tmp = readl(port_base + U3P_U3_PHYA_REG6);
- tmp &= ~P3A_RG_TX_EIDLE_CM;
- tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
- writel(tmp, port_base + U3P_U3_PHYA_REG6);
-
- tmp = readl(port_base + U3P_PHYD_CDR1);
- tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
- tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
- writel(tmp, port_base + U3P_PHYD_CDR1);
-
dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
}
@@ -306,13 +320,6 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
u32 index = instance->index;
u32 tmp;
- if (!index) {
- /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
- tmp = readl(port_base + U3P_U3_PHYA_REG0);
- tmp |= P3A_RG_U3_VUSB10_ON;
- writel(tmp, port_base + U3P_U3_PHYA_REG0);
- }
-
/* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */
tmp = readl(port_base + U3P_U2PHYDTM0);
tmp &= ~(P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL);
@@ -325,10 +332,6 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
writel(tmp, port_base + U3P_USBPHYACR6);
if (!index) {
- tmp = readl(u3phy->sif_base + U3P_XTALCTL3);
- tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
- writel(tmp, u3phy->sif_base + U3P_XTALCTL3);
-
/* switch 100uA current to SSUSB */
tmp = readl(port_base + U3P_USBPHYACR5);
tmp |= PA5_RG_U2_HS_100U_U3_EN;
@@ -340,12 +343,6 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
tmp &= ~P2C_RG_SESSEND;
writel(tmp, port_base + U3P_U2PHYDTM1);
- /* USB 2.0 slew rate calibration */
- tmp = readl(port_base + U3P_USBPHYACR5);
- tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
- tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(4);
- writel(tmp, port_base + U3P_USBPHYACR5);
-
if (u3phy->pdata->avoid_rx_sen_degradation && index) {
tmp = readl(port_base + U3D_U2PHYDCR0);
tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
@@ -393,12 +390,6 @@ static void phy_instance_power_off(struct mt65xx_u3phy *u3phy,
tmp |= P2C_RG_SESSEND;
writel(tmp, port_base + U3P_U2PHYDTM1);
- if (!index) {
- tmp = readl(port_base + U3P_U3_PHYA_REG0);
- tmp &= ~P3A_RG_U3_VUSB10_ON;
- writel(tmp, port_base + U3P_U3_PHYA_REG0);
- }
-
if (u3phy->pdata->avoid_rx_sen_degradation && index) {
tmp = readl(port_base + U3D_U2PHYDCR0);
tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
@@ -444,7 +435,11 @@ static int mt65xx_phy_init(struct phy *phy)
return ret;
}
- phy_instance_init(u3phy, instance);
+ if (instance->type == PHY_TYPE_USB2)
+ phy_instance_init(u3phy, instance);
+ else
+ u3_phy_instance_init(u3phy, instance);
+
return 0;
}
@@ -453,8 +448,10 @@ static int mt65xx_phy_power_on(struct phy *phy)
struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
- phy_instance_power_on(u3phy, instance);
- hs_slew_rate_calibrate(u3phy, instance);
+ if (instance->type == PHY_TYPE_USB2) {
+ phy_instance_power_on(u3phy, instance);
+ hs_slew_rate_calibrate(u3phy, instance);
+ }
return 0;
}
@@ -463,7 +460,9 @@ static int mt65xx_phy_power_off(struct phy *phy)
struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
- phy_instance_power_off(u3phy, instance);
+ if (instance->type == PHY_TYPE_USB2)
+ phy_instance_power_off(u3phy, instance);
+
return 0;
}
@@ -473,13 +472,12 @@ static int mt65xx_phy_exit(struct phy *phy)
struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
struct clk *ref_clk;
- phy_instance_exit(u3phy, instance);
-
- if (instance->type == PHY_TYPE_USB2)
+ if (instance->type == PHY_TYPE_USB2) {
+ phy_instance_exit(u3phy, instance);
ref_clk = u3phy->u2ref_clk;
- else
+ } else {
ref_clk = u3phy->u3ref_clk;
-
+ }
clk_disable_unprepare(ref_clk);
return 0;
}
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH 1/6] phy: phy-mt65xx-usb3: add reference clock of usb3 analog phy
From: Chunfeng Yun @ 2017-01-18 6:00 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Felipe Balbi,
Ian Campbell, linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Chunfeng Yun, Rob Herring,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Matthias Brugger,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
usually, the reference clock of usb3 analog phy comes from
26M oscillator directly, but some SoCs are not, add it for
compatibility.
Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/phy/phy-mt65xx-usb3.c | 36 ++++++++++++++++++++++++++++--------
1 file changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
index d972067..fc9a4f0 100644
--- a/drivers/phy/phy-mt65xx-usb3.c
+++ b/drivers/phy/phy-mt65xx-usb3.c
@@ -149,7 +149,8 @@ struct mt65xx_phy_instance {
struct mt65xx_u3phy {
struct device *dev;
void __iomem *sif_base; /* include sif2, but exclude port's */
- struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
+ struct clk *u2ref_clk; /* reference clock of u2 analog phy */
+ struct clk *u3ref_clk; /* reference clock of u3 analog phy */
const struct mt65xx_phy_pdata *pdata;
struct mt65xx_phy_instance **phys;
int nphys;
@@ -429,11 +430,17 @@ static int mt65xx_phy_init(struct phy *phy)
{
struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
+ struct clk *ref_clk;
int ret;
- ret = clk_prepare_enable(u3phy->u3phya_ref);
+ if (instance->type == PHY_TYPE_USB2)
+ ref_clk = u3phy->u2ref_clk;
+ else
+ ref_clk = u3phy->u3ref_clk;
+
+ ret = clk_prepare_enable(ref_clk);
if (ret) {
- dev_err(u3phy->dev, "failed to enable u3phya_ref\n");
+ dev_err(u3phy->dev, "failed to enable ref clk\n");
return ret;
}
@@ -464,9 +471,16 @@ static int mt65xx_phy_exit(struct phy *phy)
{
struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
+ struct clk *ref_clk;
phy_instance_exit(u3phy, instance);
- clk_disable_unprepare(u3phy->u3phya_ref);
+
+ if (instance->type == PHY_TYPE_USB2)
+ ref_clk = u3phy->u2ref_clk;
+ else
+ ref_clk = u3phy->u3ref_clk;
+
+ clk_disable_unprepare(ref_clk);
return 0;
}
@@ -566,10 +580,16 @@ static int mt65xx_u3phy_probe(struct platform_device *pdev)
return PTR_ERR(u3phy->sif_base);
}
- u3phy->u3phya_ref = devm_clk_get(dev, "u3phya_ref");
- if (IS_ERR(u3phy->u3phya_ref)) {
- dev_err(dev, "error to get u3phya_ref\n");
- return PTR_ERR(u3phy->u3phya_ref);
+ u3phy->u2ref_clk = devm_clk_get(dev, "u2ref_clk");
+ if (IS_ERR(u3phy->u2ref_clk)) {
+ dev_err(dev, "failed to get u2ref_clk\n");
+ return PTR_ERR(u3phy->u2ref_clk);
+ }
+
+ u3phy->u3ref_clk = devm_clk_get(dev, "u3ref_clk");
+ if (IS_ERR(u3phy->u3ref_clk)) {
+ dev_err(dev, "failed to get u3ref_clk\n");
+ return PTR_ERR(u3phy->u3ref_clk);
}
port = 0;
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH v11 07/12] drm/mediatek: cleaning up and refine
From: CK Hu @ 2017-01-18 5:55 UTC (permalink / raw)
To: YT Shen
Cc: Mark Rutland, devicetree, srv_heupstream, emil.l.velikov,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Matthias Brugger, yingjoe.chen, shaoming chen, linux-arm-kernel
In-Reply-To: <1484117473-46644-8-git-send-email-yt.shen@mediatek.com>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> cleaning up unused define and refine function name and variable
>
> Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 73 ++++++++++++++++------------------
> drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 8 ++--
> 2 files changed, 39 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 2c42f90..6f4b3bb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -27,9 +27,6 @@
>
> #include "mtk_drm_ddp_comp.h"
>
> -#define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
> -#define DSI_HOST_FIFO_DEPTH 64
> -
> #define DSI_START 0x00
>
> #define DSI_CON_CTRL 0x10
> @@ -46,7 +43,7 @@
> #define MIX_MODE BIT(17)
>
> #define DSI_TXRX_CTRL 0x18
> -#define VC_NUM (2 << 0)
> +#define VC_NUM BIT(1)
> #define LANE_NUM (0xf << 2)
> #define DIS_EOT BIT(6)
> #define NULL_EN BIT(7)
> @@ -164,7 +161,7 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
> writel((temp & ~mask) | (data & mask), dsi->regs + offset);
> }
>
> -static void dsi_phy_timconfig(struct mtk_dsi *dsi)
> +static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
> {
> u32 timcon0, timcon1, timcon2, timcon3;
> u32 ui, cycle_time;
> @@ -196,7 +193,7 @@ static void mtk_dsi_disable(struct mtk_dsi *dsi)
> mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
> }
>
> -static void mtk_dsi_reset(struct mtk_dsi *dsi)
> +static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
> {
> mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
> mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
> @@ -267,8 +264,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> }
>
> mtk_dsi_enable(dsi);
> - mtk_dsi_reset(dsi);
> - dsi_phy_timconfig(dsi);
> + mtk_dsi_reset_engine(dsi);
> + mtk_dsi_phy_timconfig(dsi);
>
> return 0;
>
> @@ -281,33 +278,33 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> return ret;
> }
>
> -static void dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
> +static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
> {
> mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
> mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
> }
>
> -static void dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
> +static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
> {
> mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
> mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
> mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
> }
>
> -static void dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
> +static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
> {
> mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
> mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
> }
>
> -static void dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
> +static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
> {
> mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
> mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
> mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
> }
>
> -static bool dsi_clk_hs_state(struct mtk_dsi *dsi)
> +static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
> {
> u32 tmp_reg1;
>
> @@ -315,15 +312,15 @@ static bool dsi_clk_hs_state(struct mtk_dsi *dsi)
> return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
> }
>
> -static void dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
> +static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
> {
> - if (enter && !dsi_clk_hs_state(dsi))
> + if (enter && !mtk_dsi_clk_hs_state(dsi))
> mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
> - else if (!enter && dsi_clk_hs_state(dsi))
> + else if (!enter && mtk_dsi_clk_hs_state(dsi))
> mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
> }
>
> -static void dsi_set_mode(struct mtk_dsi *dsi)
> +static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
> {
> u32 vid_mode = CMD_MODE;
>
> @@ -338,7 +335,7 @@ static void dsi_set_mode(struct mtk_dsi *dsi)
> writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
> }
>
> -static void dsi_ps_control_vact(struct mtk_dsi *dsi)
> +static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
> {
> struct videomode *vm = &dsi->vm;
> u32 dsi_buf_bpp, ps_wc;
> @@ -372,7 +369,7 @@ static void dsi_ps_control_vact(struct mtk_dsi *dsi)
> writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
> }
>
> -static void dsi_rxtx_control(struct mtk_dsi *dsi)
> +static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
> {
> u32 tmp_reg;
>
> @@ -397,9 +394,9 @@ static void dsi_rxtx_control(struct mtk_dsi *dsi)
> writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
> }
>
> -static void dsi_ps_control(struct mtk_dsi *dsi)
> +static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
> {
> - unsigned int dsi_tmp_buf_bpp;
> + u32 dsi_tmp_buf_bpp;
> u32 tmp_reg;
>
> switch (dsi->format) {
> @@ -429,12 +426,12 @@ static void dsi_ps_control(struct mtk_dsi *dsi)
> writel(tmp_reg, dsi->regs + DSI_PSCTRL);
> }
>
> -static void dsi_config_vdo_timing(struct mtk_dsi *dsi)
> +static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> {
> - unsigned int horizontal_sync_active_byte;
> - unsigned int horizontal_backporch_byte;
> - unsigned int horizontal_frontporch_byte;
> - unsigned int dsi_tmp_buf_bpp;
> + u32 horizontal_sync_active_byte;
> + u32 horizontal_backporch_byte;
> + u32 horizontal_frontporch_byte;
> + u32 dsi_tmp_buf_bpp;
>
> struct videomode *vm = &dsi->vm;
>
> @@ -463,7 +460,7 @@ static void dsi_config_vdo_timing(struct mtk_dsi *dsi)
> writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
> writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
>
> - dsi_ps_control(dsi);
> + mtk_dsi_ps_control(dsi);
> }
>
> static void mtk_dsi_start(struct mtk_dsi *dsi)
> @@ -480,8 +477,8 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
> if (--dsi->refcount != 0)
> return;
>
> - dsi_lane0_ulp_mode_enter(dsi);
> - dsi_clk_ulp_mode_enter(dsi);
> + mtk_dsi_lane0_ulp_mode_enter(dsi);
> + mtk_dsi_clk_ulp_mode_enter(dsi);
>
> mtk_dsi_disable(dsi);
>
> @@ -511,18 +508,18 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
> return;
> }
>
> - dsi_rxtx_control(dsi);
> + mtk_dsi_rxtx_control(dsi);
>
> - dsi_clk_ulp_mode_leave(dsi);
> - dsi_lane0_ulp_mode_leave(dsi);
> - dsi_clk_hs_mode(dsi, 0);
> - dsi_set_mode(dsi);
> + mtk_dsi_clk_ulp_mode_leave(dsi);
> + mtk_dsi_lane0_ulp_mode_leave(dsi);
> + mtk_dsi_clk_hs_mode(dsi, 0);
> + mtk_dsi_set_mode(dsi);
>
> - dsi_ps_control_vact(dsi);
> - dsi_config_vdo_timing(dsi);
> + mtk_dsi_ps_control_vact(dsi);
> + mtk_dsi_config_vdo_timing(dsi);
>
> - dsi_set_mode(dsi);
> - dsi_clk_hs_mode(dsi, 1);
> + mtk_dsi_set_mode(dsi);
> + mtk_dsi_clk_hs_mode(dsi, 1);
>
> mtk_dsi_start(dsi);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
> index c4a0165..fd84914 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
> @@ -134,7 +134,7 @@ struct mtk_mipitx_data {
> struct mtk_mipi_tx {
> struct device *dev;
> void __iomem *regs;
> - unsigned int data_rate;
> + u32 data_rate;
> const struct mtk_mipitx_data *driver_data;
> struct clk_hw pll_hw;
> struct clk *pll;
> @@ -172,7 +172,7 @@ static void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
> static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
> {
> struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
> - unsigned int txdiv, txdiv0, txdiv1;
> + u8 txdiv, txdiv0, txdiv1;
> u64 pcw;
>
> dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate);
> @@ -326,7 +326,7 @@ static unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
> static int mtk_mipi_tx_power_on_signal(struct phy *phy)
> {
> struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
> - unsigned int reg;
> + u32 reg;
>
> for (reg = MIPITX_DSI_CLOCK_LANE;
> reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
> @@ -357,7 +357,7 @@ static int mtk_mipi_tx_power_on(struct phy *phy)
> static void mtk_mipi_tx_power_off_signal(struct phy *phy)
> {
> struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
> - unsigned int reg;
> + u32 reg;
>
> mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_TOP_CON,
> RG_DSI_PAD_TIE_LOW_EN);
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