* Re: [PATCH] of: Export __of_find_all_nodes()
From: Alexander Sverdlin @ 2017-01-19 9:43 UTC (permalink / raw)
To: Frank Rowand; +Cc: Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <587FDF1B.1060206-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi!
On 18/01/17 22:33, Frank Rowand wrote:
>> This is necessary for for_each_of_allnodes() to work in the modules.
>>
>> Signed-off-by: Alexander Sverdlin <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
>> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> ---
>> drivers/of/base.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/of/base.c b/drivers/of/base.c
>> index 2eb4dea62b84..f576c33e0b84 100644
>> --- a/drivers/of/base.c
>> +++ b/drivers/of/base.c
>> @@ -270,6 +270,7 @@ struct device_node *__of_find_all_nodes(struct device_node *prev)
>> }
>> return np;
>> }
>> +EXPORT_SYMBOL_GPL(__of_find_all_nodes);
>>
>> /**
>> * of_find_all_nodes - Get next node in global list
>>
> Quoting Rob from the last request for this:
>
> "What driver needs this? This isn't really a function I'd expect drivers to use."
This one and the one from previous patch/mail are used in a module which reads DT overlays
from pluggable extension boards, eventually performs some sanity checks/corrections and
applies these overlays. This eventual corrections require low-level access to DT.
I cannot judge, how relevant this usecase is for the community, but I was driven by the fact,
that the functions which require the functions I export are defined statically in .h files
and therefore are exposed to the modules.
--
Best regards,
Alexander Sverdlin.
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^ permalink raw reply
* Re: [PATCH 0/5] meson-gx: reset RGMII PHYs and configure TX delay
From: Jerome Brunet @ 2017-01-19 9:47 UTC (permalink / raw)
To: Martin Blumenstingl, Kevin Hilman
Cc: mark.rutland, devicetree, catalin.marinas, will.deacon, robh+dt,
carlo, linux-amlogic, linux-arm-kernel
In-Reply-To: <CAFBinCACbeZPRXQO4OA5mJdGRvMkQoUmQEAKCi8KU2ZvrspF6A@mail.gmail.com>
On Wed, 2017-01-18 at 20:40 +0100, Martin Blumenstingl wrote:
> Kevin,
>
> On Wed, Jan 18, 2017 at 8:28 PM, Kevin Hilman <khilman@baylibre.com>
> wrote:
> >
> > Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> >
> > >
> > > This partially fixes the 1000Mbit/s ethernet TX throughput issues
> > > (on
> > > networks which are not affected by the EEE problem, as reported
> > > here:
> >
> > Based on the discussions with Jerome, I'm dropping this series from
> > the
> > v4.11/dt64 branch for now.
> what is you opinion on having the MDIO node in meson-gx (and keeping
> GXBB and GXL/GXM consistent) vs not having PHY autodetection for GXBB
> (= not having the MDIO in meson-gx)?
> I cannot send a v2 until we have a decision for this
>
> >
> > This series also had a small conflict with Jerome's fix[1] for the
> > odroid-c2, so please rebase any updates here on my v4.10/fixes
> > branch.
> will keep that in mind, noted.
Most this patch can go away with your patch.
Just make sure to keep "eee-broken-1000t;" in the odroidc2 dtsi and
it'll be OK.
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply
* Re: [PATCH 2/2] ARM: dts: rockchip: add dts for RK3288-Tinker board
From: Heiko Stuebner @ 2017-01-19 9:58 UTC (permalink / raw)
To: Eddie Cai
Cc: mark.rutland, devicetree, linux, linux-kernel, linux-rockchip,
robh+dt, Eddie Cai, linux-arm-kernel
In-Reply-To: <1484791919-4665-3-git-send-email-eddie.cai@rock-chips.com>
Hi Eddie,
Am Donnerstag, 19. Januar 2017, 10:11:59 CET schrieb Eddie Cai:
> This patch add basic support for RK3288-Tinker board. We can boot in to
> rootfs with this patch.
>
> Signed-off-by: Eddie Cai <eddie.cai@rock-chips.com>
looks good in general, just some small question down below.
[...]
> + /*
> + * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from
> + * vcc_io directly. Those boards won't be able to power cycle SD cards
> + * but it shouldn't hurt to toggle this pin there anyway.
> + */
just to clarify, later board will have that pin connected, right?
> + vcc_sd: sdmmc-regulator {
> + compatible = "regulator-fixed";
> + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc_pwr>;
> + regulator-name = "vcc_sd";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + startup-delay-us = <100000>;
> + vin-supply = <&vcc_io>;
> + };
> +};
[...]
> +&hdmi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #sound-dai-cells = <0>;
> + ddc-i2c-bus = <&i2c5>;
> + status = "okay";
> + /* Don't use vopl for HDMI */
> + ports {
> + hdmi_in: port {
> + /delete-node/ endpoint@1;
> + };
what is the reason for this? You enable both VOPs below and the linux display
subsystem should be able to select an appropriate VOP for output just fine on
its own. So there should be no reason for capping the hdmi's connection to one
of the vops.
> + };
> +};
[...]
> +&usb_host0_ehci {
> + no-relinquish-port;
This seems like an unused/undocumented property
> + status = "okay";
> +};
[...]
> +&vopl {
> + status = "okay";
> + /* Don't use vopl for HDMI */
> + vopl_out: port {
> + /delete-node/ endpoint@0;
> + };
see comment at the hdmi node
> +};
Thanks
Heiko
^ permalink raw reply
* Re: [PATCHv4 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
From: Russell King - ARM Linux @ 2017-01-19 10:02 UTC (permalink / raw)
To: Chris Packham
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
Thomas Petazzoni, linux-gpio-u79uwXL29TY76Z2rM5mHXA,
Linus Walleij, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
Kalyan Kinthada, devicetree-u79uwXL29TY76Z2rM5mHXA,
Laxman Dewangan, Sebastian Hesselbarth
In-Reply-To: <20170113091222.7132-4-chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>
On Fri, Jan 13, 2017 at 10:12:18PM +1300, Chris Packham wrote:
> +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
> + MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl),
> +};
As Linus has taken my mvebu pinctrl series, this will need to be
changed to "mvebu_mmio_mpp_ctrl" rather than "armada_xp_mpp_ctrl"
when it's merged.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
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^ permalink raw reply
* Re: [PATCH 1/5] ARM: OMAP2+: omap_hwmod: Add support for earlycon
From: Lokesh Vutla @ 2017-01-19 10:05 UTC (permalink / raw)
To: Tony Lindgren
Cc: Linux OMAP Mailing List, Device Tree Mailing List, Rob Herring,
Tero Kristo, Sekhar Nori, Vignesh R, Nishanth Menon
In-Reply-To: <20170118170033.GD7403-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
On Wednesday 18 January 2017 10:30 PM, Tony Lindgren wrote:
> * Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org> [170117 19:50]:
>>
>>
>> On Wednesday 18 January 2017 04:53 AM, Tony Lindgren wrote:
>>> * Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org> [170116 20:06]:
>>>> Hwmod core tries to reset and idles each IP that is registered with hwmod.
>>>> In case of earlycon, that specific uart IP cannot be reset or keep it in
>>>> idle state else earlycon hangs once hwmod resets that uart IP. So add support
>>>> to not reset uart that is being used as earlycon only if CONFIG_SERIAL_EARLYCON
>>>> is enabled.
>>>
>>> Nice :)
>>>
>>> I guess this has no dependency to SERIAL_OMAP vs 8250_OMAP selection?
>>
>> Unfortunately SERIAL_OMAP does not support earlycon yet. As I mentioned
>> in my cover letter, I verified this series only with 8250_OMAP.
>
> OK. So just to understand why it would not work with omap-serial, do we
> need something implemented in drivers/tty/serial/earlycon.c for non 8250
> drivers to make it work? Or are there other dependencies?
Yeah, OF_EARLYCON_DECLARE should be declared for omap-serial. Just
posted a patch[1] adding support for earlycon in omap-serial.
[1] https://patchwork.kernel.org/patch/9525377/
Thanks and regards,
Lokesh
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^ permalink raw reply
* [PATCH] of/unittest: Swap arguments of of_unittest_apply_overlay()
From: Alexander Sverdlin @ 2017-01-19 10:06 UTC (permalink / raw)
Cc: Alexander Sverdlin, Rob Herring, Frank Rowand,
devicetree-u79uwXL29TY76Z2rM5mHXA
Function signature
of_unittest_apply_overlay(int unittest_nr, int overlay_nr, ...
and call sites, like in of_unittest_apply_overlay_check():
ret = of_unittest_apply_overlay(overlay_nr, unittest_nr, ...
do not match. Fix this in one place (function signature).
The only affected test case is 15, which supplies non-existing
overlay number 16, but two bugs matched here. Fix the test case.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
drivers/of/unittest.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
index 53c83d66eb7e..66bfa8d674ce 100644
--- a/drivers/of/unittest.c
+++ b/drivers/of/unittest.c
@@ -1181,7 +1181,7 @@ static void of_unittest_destroy_tracked_overlays(void)
} while (defers > 0);
}
-static int of_unittest_apply_overlay(int unittest_nr, int overlay_nr,
+static int of_unittest_apply_overlay(int overlay_nr, int unittest_nr,
int *overlay_id)
{
struct device_node *np = NULL;
@@ -1840,7 +1840,7 @@ static void of_unittest_overlay_i2c_15(void)
int ret;
/* device should enable */
- ret = of_unittest_apply_overlay_check(16, 15, 0, 1, I2C_OVERLAY);
+ ret = of_unittest_apply_overlay_check(15, 15, 0, 1, I2C_OVERLAY);
if (ret != 0)
return;
--
2.11.0
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^ permalink raw reply related
* Re: [PATCH 2/2] of: Add function for generating a DT modalias with a newline
From: Greg Kroah-Hartman @ 2017-01-19 10:35 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, linux-kernel, Frank Rowand, Benjamin Herrenschmidt,
Paul Mackerras, Michael Ellerman, linuxppc-dev
In-Reply-To: <20170116204122.5858-2-robh@kernel.org>
On Mon, Jan 16, 2017 at 02:41:22PM -0600, Rob Herring wrote:
> The modalias sysfs attr is lacking a newline for DT aliases on platform
> devices. The macio and ibmebus correctly add the newline, but open code it.
> Introduce a new function, of_device_modalias(), that fills the buffer with
> the modalias including the newline and update users of the old
> of_device_get_modalias function.
>
> Signed-off-by: Rob Herring <robh@kernel.org>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: Frank Rowand <frowand.list@gmail.com>
> Cc: linuxppc-dev@lists.ozlabs.org
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply
* Re: [PATCH v1 0/7] DRM: add LTDC support for STM32F4
From: Yannick FERTRE @ 2017-01-19 10:35 UTC (permalink / raw)
To: Neil Armstrong, Alexandre TORGUE, Thierry Reding, David Airlie,
Maxime Coquelin, Russell King, Mark Rutland, Rob Herring,
Arnd Bergmann
Cc: devicetree@vger.kernel.org, kernel@stlinux.com, Philippe CORNU,
dri-devel@lists.freedesktop.org, Mickael REULIER,
Gabriel FERNANDEZ, linux-arm-kernel@lists.infradead.org
In-Reply-To: <cf29809f-f951-eeed-5886-02d0a7a1e56f@baylibre.com>
Hi Neil,
ST may use this hardware IP also in other SoC, even that is not true
now, I hope that "st" is a more futur proof name.
Best regards
Yannick Fertré
On 01/16/2017 05:02 PM, Neil Armstrong wrote:
> On 01/16/2017 02:28 PM, Yannick Fertre wrote:
>> The purpose of this set of patches is to add a new driver for stm32f429.
>> This driver was developed and tested on evaluation board stm32429i.
>>
>> Stm32f4 is a MCU platform which don't have MMU so the last patches developed
>> by Benjamin Gaignard regarding "DRM: allow to use mmuless devices"
>> are necessary.
>>
>> The board stm429i embeds a Ampire AM-480272H3TMQW-T01H screen.
>> A new simple panel am-480272h3tmqw-t01h have been added to support it.
>>
>> Yannick Fertre (7):
>> dt-bindings: display: add STM32 LTDC driver
>> drm/st: Add STM32 LTDC driver
>> dt-bindings: Add Ampire AM-480272H3TMQW-T01H panel
>> drm/panel: simple: Add support for Ampire AM-480272H3TMQW-T01H
>> ARM: dts: stm32f429: Add ltdc support
>> ARM: dts: stm32429i-eval: Enable ltdc & simple panel on Eval board
>> ARM: configs: Add STM32 LTDC support in STM32 defconfig
>>
>> .../display/panel/ampire,am-480272h3tmqw-t01h.txt | 7 +
>> .../devicetree/bindings/display/st,ltdc.txt | 57 +
>> arch/arm/boot/dts/stm32429i-eval.dts | 58 +
>> arch/arm/boot/dts/stm32f429.dtsi | 25 +-
>> arch/arm/configs/stm32_defconfig | 5 +
>> drivers/gpu/drm/Kconfig | 2 +
>> drivers/gpu/drm/Makefile | 1 +
>> drivers/gpu/drm/panel/panel-simple.c | 29 +
>> drivers/gpu/drm/st/Kconfig | 14 +
>> drivers/gpu/drm/st/Makefile | 7 +
>> drivers/gpu/drm/st/drv.c | 279 ++++
>> drivers/gpu/drm/st/drv.h | 25 +
>> drivers/gpu/drm/st/ltdc.c | 1438 ++++++++++++++++++++
>> drivers/gpu/drm/st/ltdc.h | 20 +
>> 14 files changed, 1966 insertions(+), 1 deletion(-)
>> create mode 100644 Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt
>> create mode 100644 Documentation/devicetree/bindings/display/st,ltdc.txt
>> create mode 100644 drivers/gpu/drm/st/Kconfig
>> create mode 100644 drivers/gpu/drm/st/Makefile
>> create mode 100644 drivers/gpu/drm/st/drv.c
>> create mode 100644 drivers/gpu/drm/st/drv.h
>> create mode 100644 drivers/gpu/drm/st/ltdc.c
>> create mode 100644 drivers/gpu/drm/st/ltdc.h
>>
>
> Hi Yannick,
>
> Shouldn't be more logical to use stm32 for the driver instead of st ?
> It would eventually collude with the other STMicroelectronics SoCs and
> will be aligned with other drivers like stm32-rtc, stm32-i2c, ...
>
> Neil
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [RFC v2 1/5] UDC: Split the driver into amd (pci) and Synopsys core driver
From: Raviteja Garimella @ 2017-01-19 10:44 UTC (permalink / raw)
To: Florian Fainelli
Cc: Rob Herring, Mark Rutland, Greg Kroah-Hartman, Felipe Balbi,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, BCM Kernel Feedback,
linux-usb-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <e1453122-164a-e1a8-6aa6-fb25eb33101f-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi,
On Thu, Jan 19, 2017 at 12:15 AM, Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On 01/17/2017 12:05 AM, Raviteja Garimella wrote:
>> This patch splits the amd5536udc driver into two -- one that does
>> pci device registration and the other file that does the rest of
>> the driver tasks like the gadget/ep ops etc for Synopsys UDC.
>>
>> This way of splitting helps in exporting core driver symbols which
>> can be used by any other platform/pci driver that is written for
>> the same Synopsys USB device controller.
>>
>> The current patch also includes a change in the Kconfig and Makefile.
>> A new config option USB_SNP_CORE will be selected automatically when
>> any one of the platform or pci driver for the same UDC is selected.
>>
>> Signed-off-by: Raviteja Garimella <raviteja.garimella-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>
> Although the changes you have done make sense and it is most certainly a
> good idea to split udc core from bus specific glue logic, it is really
> hard to review the changes per-se because of the file rename, could that
> happen at a later time?
If you start looking at this specific patch from the header file (amd5536udc.h),
the additions in there comprise of:
- 9 function declarations
- some module parameter variable declarations that's moved out from the older
common file amd5536udc.c
- 2 #includes that are needed by all files.
So, basically what's done for this split is that:
1. the static keyword is removed from those 9 functions in the new file
snps_udc_core.c and are exported.
2. The module parameters declarations (since they are used in both core
and pci file) are moved to the header file now.
Rest all is same as in old amd5536udc.c common file. It's just a copy from the
old file.
And, the file amd5536udc.c will now only do the pci device probe and
remove functions.
I hope this helps. Please let me know of any clarifications needed.
Since both the files are required to be reviewed, I think renaming is
inevitable.
Thanks,
Ravi
>
> Also, keep in mind that anytime a driver file is renamed, this poses a
> backport/maintenance issue where backporting fixes from latest upstream
> to a kernel version that has a different file/directory structure is a
> major pain.
> --
> Florian
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* [PATCH 3/4] phy: qcom-ufs: Remove -always-on property
From: Bjorn Andersson @ 2017-01-19 10:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: linux-kernel, linux-arm-msm, Rob Herring, Mark Rutland,
devicetree, Subhash Jadavani, Vivek Gautam
In-Reply-To: <20170119104739.4376-1-bjorn.andersson@linaro.org>
The fact that a regulator is always-on is a property of the regulator,
not a specific consumer. Implementing this in the driver leads to a
system behaviour that is dependent on if the Qualcomm UFS PHY was ever
(partially) probed.
If the specific regulator should be always on in a particular device,
mark it so by specifying "regulator-always-on" in the regulator node.
Cc: Subhash Jadavani <subhashj@codeaurora.org>
Cc: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Documentation/devicetree/bindings/ufs/ufs-qcom.txt | 1 -
drivers/phy/phy-qcom-ufs-i.h | 1 -
drivers/phy/phy-qcom-ufs.c | 5 +----
3 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
index b6b5130e5f65..1f69ee1a61ea 100644
--- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
+++ b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
@@ -29,7 +29,6 @@ Optional properties:
- vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
- vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply
- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
-- vddp-ref-clk-always-on : specifies if this supply needs to be kept always on
Example:
diff --git a/drivers/phy/phy-qcom-ufs-i.h b/drivers/phy/phy-qcom-ufs-i.h
index d505d98cf5f8..13b02b7de30b 100644
--- a/drivers/phy/phy-qcom-ufs-i.h
+++ b/drivers/phy/phy-qcom-ufs-i.h
@@ -77,7 +77,6 @@ struct ufs_qcom_phy_vreg {
int min_uV;
int max_uV;
bool enabled;
- bool is_always_on;
};
struct ufs_qcom_phy {
diff --git a/drivers/phy/phy-qcom-ufs.c b/drivers/phy/phy-qcom-ufs.c
index bbd317158084..c145fa6e824c 100644
--- a/drivers/phy/phy-qcom-ufs.c
+++ b/drivers/phy/phy-qcom-ufs.c
@@ -242,9 +242,6 @@ static int ufs_qcom_phy_init_vreg(struct device *dev,
}
err = 0;
}
- snprintf(prop_name, MAX_PROP_NAME, "%s-always-on", name);
- vreg->is_always_on = of_property_read_bool(dev->of_node,
- prop_name);
}
if (!strcmp(name, "vdda-pll")) {
@@ -402,7 +399,7 @@ static int ufs_qcom_phy_disable_vreg(struct device *dev,
{
int ret = 0;
- if (!vreg || !vreg->enabled || vreg->is_always_on)
+ if (!vreg || !vreg->enabled)
goto out;
ret = regulator_disable(vreg->reg);
--
2.11.0
^ permalink raw reply related
* Re: [PATCH v3 09/13] sata: ahci: export ahci_do_hardreset() locally
From: Bartosz Golaszewski @ 2017-01-19 10:55 UTC (permalink / raw)
To: Tejun Heo
Cc: Kevin Hilman, Sekhar Nori, Patrick Titiano, Michael Turquette,
Rob Herring, Mark Rutland, Russell King, David Lechner,
linux-ide-u79uwXL29TY76Z2rM5mHXA, linux-devicetree, LKML, arm-soc
In-Reply-To: <20170118182826.GA1451-qYNAdHglDFBN0TnZuCh8vA@public.gmane.org>
2017-01-18 19:28 GMT+01:00 Tejun Heo <tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>:
> Hello, Bartosz.
>
> On Wed, Jan 18, 2017 at 02:19:57PM +0100, Bartosz Golaszewski wrote:
>> We need a way to retrieve the information about the online state of
>> the link in the ahci-da850 driver.
>>
>> Create a new function: ahci_do_hardreset() which is called from
>> ahci_hardreset() for backwards compatibility, but has an additional
>> argument: 'online' - which can be used to check if the link is online
>> after this function returns.
>
> Please just add @online to ahci_hardreset() and update the callers.
> Other than that, the sata changes look good to me.
>
Are you sure? There are 23 places in drivers/ata/ where the .hardreset
callback is assigned. I'd prefer not to change the drivers I can't
test. Besides all other **reset callbacks take three arguments -
should we really only change one of them for a single driver's needs?
Thanks,
Bartosz
--
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^ permalink raw reply
* Re: [PATCH 09/13] mmc: jz4740: Let the pinctrl driver configure the pins
From: Ulf Hansson @ 2017-01-19 10:55 UTC (permalink / raw)
To: Paul Cercueil
Cc: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mips,
linux-mmc@vger.kernel.org, linux-mtd, linux-pwm, Linux
In-Reply-To: <20170117231421.16310-10-paul@crapouillou.net>
[...]
>
> -#ifdef CONFIG_PM_SLEEP
> -
> -static int jz4740_mmc_suspend(struct device *dev)
> -{
> - struct jz4740_mmc_host *host = dev_get_drvdata(dev);
> -
> - jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
> -
Shouldn't this be replaced with a call to:
pinctrl_pm_select_sleep_state();
> - return 0;
> -}
> -
> -static int jz4740_mmc_resume(struct device *dev)
> -{
> - struct jz4740_mmc_host *host = dev_get_drvdata(dev);
> -
> - jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
Shouldn't this be replaced with a call to:
pinctrl_pm_select_default_state();
[...]
Kind regards
Uffe
^ permalink raw reply
* Re: [PATCH v3 2/2] mmc: host: s3cmci: allow probing from device tree
From: Ulf Hansson @ 2017-01-19 11:10 UTC (permalink / raw)
To: Sergio Prado
Cc: Rob Herring, Mark Rutland, linux-mmc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Ben Dooks, linux-arm-kernel@lists.infradead.org
In-Reply-To: <1484319953-6479-3-git-send-email-sergio.prado@e-labworks.com>
On 13 January 2017 at 16:05, Sergio Prado <sergio.prado@e-labworks.com> wrote:
> Allows configuring Samsung S3C24XX MMC/SD/SDIO controller using a device
> tree.
>
> Signed-off-by: Sergio Prado <sergio.prado@e-labworks.com>
Looks good to me. Waiting for Rob's ack for the DT changes in patch1
(needed a re-spin) before I queue it.
Kind regards
Uffe
> ---
> drivers/mmc/host/s3cmci.c | 298 ++++++++++++++++++++++++----------------------
> drivers/mmc/host/s3cmci.h | 3 +-
> 2 files changed, 158 insertions(+), 143 deletions(-)
>
> diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
> index 932a4b1fed33..55535b65e0b3 100644
> --- a/drivers/mmc/host/s3cmci.c
> +++ b/drivers/mmc/host/s3cmci.c
> @@ -23,6 +23,10 @@
> #include <linux/gpio.h>
> #include <linux/irq.h>
> #include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_gpio.h>
> +#include <linux/mmc/slot-gpio.h>
>
> #include <plat/gpio-cfg.h>
> #include <mach/dma.h>
> @@ -127,6 +131,22 @@ enum dbg_channels {
> dbg_conf = (1 << 8),
> };
>
> +struct s3cmci_variant_data {
> + int s3c2440_compatible;
> +};
> +
> +static const struct s3cmci_variant_data s3c2410_s3cmci_variant_data = {
> + .s3c2440_compatible = 0,
> +};
> +
> +static const struct s3cmci_variant_data s3c2412_s3cmci_variant_data = {
> + .s3c2440_compatible = 1,
> +};
> +
> +static const struct s3cmci_variant_data s3c2440_s3cmci_variant_data = {
> + .s3c2440_compatible = 1,
> +};
> +
> static const int dbgmap_err = dbg_fail;
> static const int dbgmap_info = dbg_info | dbg_conf;
> static const int dbgmap_debug = dbg_err | dbg_debug;
> @@ -730,7 +750,7 @@ static irqreturn_t s3cmci_irq(int irq, void *dev_id)
> goto clear_status_bits;
>
> /* Check for FIFO failure */
> - if (host->is2440) {
> + if (host->variant->s3c2440_compatible) {
> if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
> dbg(host, dbg_err, "FIFO failure\n");
> host->mrq->data->error = -EILSEQ;
> @@ -806,21 +826,6 @@ static irqreturn_t s3cmci_irq(int irq, void *dev_id)
>
> }
>
> -/*
> - * ISR for the CardDetect Pin
> -*/
> -
> -static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
> -{
> - struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
> -
> - dbg(host, dbg_irq, "card detect\n");
> -
> - mmc_detect_change(host->mmc, msecs_to_jiffies(500));
> -
> - return IRQ_HANDLED;
> -}
> -
> static void s3cmci_dma_done_callback(void *arg)
> {
> struct s3cmci_host *host = arg;
> @@ -912,7 +917,7 @@ static void finalize_request(struct s3cmci_host *host)
> if (s3cmci_host_usedma(host))
> dmaengine_terminate_all(host->dma);
>
> - if (host->is2440) {
> + if (host->variant->s3c2440_compatible) {
> /* Clear failure register and reset fifo. */
> writel(S3C2440_SDIFSTA_FIFORESET |
> S3C2440_SDIFSTA_FIFOFAIL,
> @@ -1025,7 +1030,7 @@ static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
> dcon |= S3C2410_SDIDCON_XFER_RXSTART;
> }
>
> - if (host->is2440) {
> + if (host->variant->s3c2440_compatible) {
> dcon |= S3C2440_SDIDCON_DS_WORD;
> dcon |= S3C2440_SDIDCON_DATSTART;
> }
> @@ -1044,7 +1049,7 @@ static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
>
> /* write TIMER register */
>
> - if (host->is2440) {
> + if (host->variant->s3c2440_compatible) {
> writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
> } else {
> writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
> @@ -1176,19 +1181,6 @@ static void s3cmci_send_request(struct mmc_host *mmc)
> s3cmci_enable_irq(host, true);
> }
>
> -static int s3cmci_card_present(struct mmc_host *mmc)
> -{
> - struct s3cmci_host *host = mmc_priv(mmc);
> - struct s3c24xx_mci_pdata *pdata = host->pdata;
> - int ret;
> -
> - if (pdata->no_detect)
> - return -ENOSYS;
> -
> - ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
> - return ret ^ pdata->detect_invert;
> -}
> -
> static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
> {
> struct s3cmci_host *host = mmc_priv(mmc);
> @@ -1197,7 +1189,7 @@ static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
> host->cmd_is_stop = 0;
> host->mrq = mrq;
>
> - if (s3cmci_card_present(mmc) == 0) {
> + if (mmc_gpio_get_cd(mmc) == 0) {
> dbg(host, dbg_err, "%s: no medium present\n", __func__);
> host->mrq->cmd->error = -ENOMEDIUM;
> mmc_request_done(mmc, mrq);
> @@ -1241,22 +1233,24 @@ static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> case MMC_POWER_ON:
> case MMC_POWER_UP:
> /* Configure GPE5...GPE10 pins in SD mode */
> - s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
> - S3C_GPIO_PULL_NONE);
> + if (!host->pdev->dev.of_node)
> + s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
> + S3C_GPIO_PULL_NONE);
>
> if (host->pdata->set_power)
> host->pdata->set_power(ios->power_mode, ios->vdd);
>
> - if (!host->is2440)
> + if (!host->variant->s3c2440_compatible)
> mci_con |= S3C2410_SDICON_FIFORESET;
>
> break;
>
> case MMC_POWER_OFF:
> default:
> - gpio_direction_output(S3C2410_GPE(5), 0);
> + if (!host->pdev->dev.of_node)
> + gpio_direction_output(S3C2410_GPE(5), 0);
>
> - if (host->is2440)
> + if (host->variant->s3c2440_compatible)
> mci_con |= S3C2440_SDICON_SDRESET;
>
> if (host->pdata->set_power)
> @@ -1294,21 +1288,6 @@ static void s3cmci_reset(struct s3cmci_host *host)
> writel(con, host->base + S3C2410_SDICON);
> }
>
> -static int s3cmci_get_ro(struct mmc_host *mmc)
> -{
> - struct s3cmci_host *host = mmc_priv(mmc);
> - struct s3c24xx_mci_pdata *pdata = host->pdata;
> - int ret;
> -
> - if (pdata->no_wprotect)
> - return 0;
> -
> - ret = gpio_get_value(pdata->gpio_wprotect) ? 1 : 0;
> - ret ^= pdata->wprotect_invert;
> -
> - return ret;
> -}
> -
> static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
> {
> struct s3cmci_host *host = mmc_priv(mmc);
> @@ -1352,8 +1331,8 @@ static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
> static struct mmc_host_ops s3cmci_ops = {
> .request = s3cmci_request,
> .set_ios = s3cmci_set_ios,
> - .get_ro = s3cmci_get_ro,
> - .get_cd = s3cmci_card_present,
> + .get_ro = mmc_gpio_get_ro,
> + .get_cd = mmc_gpio_get_cd,
> .enable_sdio_irq = s3cmci_enable_sdio_irq,
> };
>
> @@ -1429,7 +1408,7 @@ static int s3cmci_state_show(struct seq_file *seq, void *v)
> seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
> seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
> seq_printf(seq, "Prescale = %d\n", host->prescaler);
> - seq_printf(seq, "is2440 = %d\n", host->is2440);
> + seq_printf(seq, "S3C2440 compatible = %d\n", host->variant->s3c2440_compatible);
> seq_printf(seq, "IRQ = %d\n", host->irq);
> seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
> seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
> @@ -1544,21 +1523,15 @@ static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
>
> #endif /* CONFIG_DEBUG_FS */
>
> -static int s3cmci_probe(struct platform_device *pdev)
> +static int s3cmci_probe_pdata(struct s3cmci_host *host)
> {
> - struct s3cmci_host *host;
> - struct mmc_host *mmc;
> - int ret;
> - int is2440;
> - int i;
> + struct platform_device *pdev = host->pdev;
> + struct mmc_host *mmc = host->mmc;
> + struct s3c24xx_mci_pdata *pdata;
> + int i, ret;
>
> - is2440 = platform_get_device_id(pdev)->driver_data;
> -
> - mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
> - if (!mmc) {
> - ret = -ENOMEM;
> - goto probe_out;
> - }
> + host->variant = (const struct s3cmci_variant_data *)
> + platform_get_device_id(pdev)->driver_data;
>
> for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
> ret = gpio_request(i, dev_name(&pdev->dev));
> @@ -1568,25 +1541,103 @@ static int s3cmci_probe(struct platform_device *pdev)
> for (i--; i >= S3C2410_GPE(5); i--)
> gpio_free(i);
>
> - goto probe_free_host;
> + return ret;
> }
> }
>
> + if (!pdev->dev.platform_data)
> + pdev->dev.platform_data = &s3cmci_def_pdata;
> +
> + pdata = pdev->dev.platform_data;
> +
> + if (pdata->no_wprotect)
> + mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
> +
> + if (pdata->no_detect)
> + mmc->caps |= MMC_CAP_NEEDS_POLL;
> +
> + if (pdata->wprotect_invert);
> + mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
> +
> + if (pdata->detect_invert)
> + mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
> +
> + if (gpio_is_valid(pdata->gpio_detect)) {
> + ret = mmc_gpio_request_cd(mmc, pdata->gpio_detect, 0);
> + if (ret) {
> + dev_err(&pdev->dev, "error requesting GPIO for CD %d\n",
> + ret);
> + return ret;
> + }
> + }
> +
> + if (gpio_is_valid(pdata->gpio_wprotect)) {
> + ret = mmc_gpio_request_ro(mmc, pdata->gpio_wprotect);
> + if (ret) {
> + dev_err(&pdev->dev, "error requesting GPIO for WP %d\n",
> + ret);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int s3cmci_probe_dt(struct s3cmci_host *host)
> +{
> + struct platform_device *pdev = host->pdev;
> + struct s3c24xx_mci_pdata *pdata;
> + struct mmc_host *mmc = host->mmc;
> + int ret;
> +
> + host->variant = of_device_get_match_data(&pdev->dev);
> + if (!host->variant)
> + return -ENODEV;
> +
> + ret = mmc_of_parse(mmc);
> + if (ret)
> + return ret;
> +
> + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> + if (!pdata)
> + return -ENOMEM;
> +
> + pdev->dev.platform_data = pdata;
> +
> + return 0;
> +}
> +
> +static int s3cmci_probe(struct platform_device *pdev)
> +{
> + struct s3cmci_host *host;
> + struct mmc_host *mmc;
> + int ret;
> + int i;
> +
> + mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
> + if (!mmc) {
> + ret = -ENOMEM;
> + goto probe_out;
> + }
> +
> host = mmc_priv(mmc);
> host->mmc = mmc;
> host->pdev = pdev;
> - host->is2440 = is2440;
> +
> + if (pdev->dev.of_node)
> + ret = s3cmci_probe_dt(host);
> + else
> + ret = s3cmci_probe_pdata(host);
> +
> + if (ret)
> + goto probe_free_host;
>
> host->pdata = pdev->dev.platform_data;
> - if (!host->pdata) {
> - pdev->dev.platform_data = &s3cmci_def_pdata;
> - host->pdata = &s3cmci_def_pdata;
> - }
>
> spin_lock_init(&host->complete_lock);
> tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
>
> - if (is2440) {
> + if (host->variant->s3c2440_compatible) {
> host->sdiimsk = S3C2440_SDIIMSK;
> host->sdidata = S3C2440_SDIDATA;
> host->clk_div = 1;
> @@ -1644,43 +1695,6 @@ static int s3cmci_probe(struct platform_device *pdev)
> disable_irq(host->irq);
> host->irq_state = false;
>
> - if (!host->pdata->no_detect) {
> - ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
> - if (ret) {
> - dev_err(&pdev->dev, "failed to get detect gpio\n");
> - goto probe_free_irq;
> - }
> -
> - host->irq_cd = gpio_to_irq(host->pdata->gpio_detect);
> -
> - if (host->irq_cd >= 0) {
> - if (request_irq(host->irq_cd, s3cmci_irq_cd,
> - IRQF_TRIGGER_RISING |
> - IRQF_TRIGGER_FALLING,
> - DRIVER_NAME, host)) {
> - dev_err(&pdev->dev,
> - "can't get card detect irq.\n");
> - ret = -ENOENT;
> - goto probe_free_gpio_cd;
> - }
> - } else {
> - dev_warn(&pdev->dev,
> - "host detect has no irq available\n");
> - gpio_direction_input(host->pdata->gpio_detect);
> - }
> - } else
> - host->irq_cd = -1;
> -
> - if (!host->pdata->no_wprotect) {
> - ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
> - if (ret) {
> - dev_err(&pdev->dev, "failed to get writeprotect\n");
> - goto probe_free_irq_cd;
> - }
> -
> - gpio_direction_input(host->pdata->gpio_wprotect);
> - }
> -
> /* Depending on the dma state, get a DMA channel to use. */
>
> if (s3cmci_host_usedma(host)) {
> @@ -1688,7 +1702,7 @@ static int s3cmci_probe(struct platform_device *pdev)
> ret = PTR_ERR_OR_ZERO(host->dma);
> if (ret) {
> dev_err(&pdev->dev, "cannot get DMA channel.\n");
> - goto probe_free_gpio_wp;
> + goto probe_free_irq;
> }
> }
>
> @@ -1730,7 +1744,7 @@ static int s3cmci_probe(struct platform_device *pdev)
>
> dbg(host, dbg_debug,
> "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
> - (host->is2440?"2440":""),
> + (host->variant->s3c2440_compatible?"2440":""),
> host->base, host->irq, host->irq_cd, host->dma);
>
> ret = s3cmci_cpufreq_register(host);
> @@ -1767,18 +1781,6 @@ static int s3cmci_probe(struct platform_device *pdev)
> if (s3cmci_host_usedma(host))
> dma_release_channel(host->dma);
>
> - probe_free_gpio_wp:
> - if (!host->pdata->no_wprotect)
> - gpio_free(host->pdata->gpio_wprotect);
> -
> - probe_free_gpio_cd:
> - if (!host->pdata->no_detect)
> - gpio_free(host->pdata->gpio_detect);
> -
> - probe_free_irq_cd:
> - if (host->irq_cd >= 0)
> - free_irq(host->irq_cd, host);
> -
> probe_free_irq:
> free_irq(host->irq, host);
>
> @@ -1789,8 +1791,9 @@ static int s3cmci_probe(struct platform_device *pdev)
> release_mem_region(host->mem->start, resource_size(host->mem));
>
> probe_free_gpio:
> - for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
> - gpio_free(i);
> + if (!pdev->dev.of_node)
> + for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
> + gpio_free(i);
>
> probe_free_host:
> mmc_free_host(mmc);
> @@ -1817,7 +1820,6 @@ static int s3cmci_remove(struct platform_device *pdev)
> {
> struct mmc_host *mmc = platform_get_drvdata(pdev);
> struct s3cmci_host *host = mmc_priv(mmc);
> - struct s3c24xx_mci_pdata *pd = host->pdata;
> int i;
>
> s3cmci_shutdown(pdev);
> @@ -1831,15 +1833,9 @@ static int s3cmci_remove(struct platform_device *pdev)
>
> free_irq(host->irq, host);
>
> - if (!pd->no_wprotect)
> - gpio_free(pd->gpio_wprotect);
> -
> - if (!pd->no_detect)
> - gpio_free(pd->gpio_detect);
> -
> - for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
> - gpio_free(i);
> -
> + if (!pdev->dev.of_node)
> + for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
> + gpio_free(i);
>
> iounmap(host->base);
> release_mem_region(host->mem->start, resource_size(host->mem));
> @@ -1848,16 +1844,33 @@ static int s3cmci_remove(struct platform_device *pdev)
> return 0;
> }
>
> +static const struct of_device_id s3cmci_dt_match[] = {
> + {
> + .compatible = "samsung,s3c2410-sdi",
> + .data = &s3c2410_s3cmci_variant_data,
> + },
> + {
> + .compatible = "samsung,s3c2412-sdi",
> + .data = &s3c2412_s3cmci_variant_data,
> + },
> + {
> + .compatible = "samsung,s3c2440-sdi",
> + .data = &s3c2440_s3cmci_variant_data,
> + },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
> +
> static const struct platform_device_id s3cmci_driver_ids[] = {
> {
> .name = "s3c2410-sdi",
> - .driver_data = 0,
> + .driver_data = (kernel_ulong_t) &s3c2410_s3cmci_variant_data,
> }, {
> .name = "s3c2412-sdi",
> - .driver_data = 1,
> + .driver_data = (kernel_ulong_t) &s3c2412_s3cmci_variant_data,
> }, {
> .name = "s3c2440-sdi",
> - .driver_data = 1,
> + .driver_data = (kernel_ulong_t) &s3c2440_s3cmci_variant_data,
> },
> { }
> };
> @@ -1867,6 +1880,7 @@ static int s3cmci_remove(struct platform_device *pdev)
> static struct platform_driver s3cmci_driver = {
> .driver = {
> .name = "s3c-sdi",
> + .of_match_table = s3cmci_dt_match,
> },
> .id_table = s3cmci_driver_ids,
> .probe = s3cmci_probe,
> diff --git a/drivers/mmc/host/s3cmci.h b/drivers/mmc/host/s3cmci.h
> index 30c2c0dd1bc8..e9fe48915a2e 100644
> --- a/drivers/mmc/host/s3cmci.h
> +++ b/drivers/mmc/host/s3cmci.h
> @@ -33,7 +33,8 @@ struct s3cmci_host {
> unsigned long real_rate;
> u8 prescaler;
>
> - int is2440;
> + const struct s3cmci_variant_data *variant;
> +
> unsigned sdiimsk;
> unsigned sdidata;
>
> --
> 1.9.1
>
^ permalink raw reply
* Re: Question about OF-graph ports
From: Mark Brown @ 2017-01-19 11:12 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Rob Herring, Linux-DT, Linux-ALSA
In-Reply-To: <87r33z4maj.wl%kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 277 bytes --]
On Thu, Jan 19, 2017 at 06:07:43AM +0000, Kuninori Morimoto wrote:
> My question is in this case, how to know CPU/Codec pair on "card" ?
This is more of a DT question but, I don't think I have that strong an
opinion based on the snippets you posted, they both seem readable.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* [PATCH v8 0/4] arm64: arch_timer: Add workaround for hisilicon-161601 erratum
From: Ding Tianhong @ 2017-01-19 11:14 UTC (permalink / raw)
To: catalin.marinas, will.deacon, marc.zyngier, mark.rutland, oss,
devicetree, shawnguo, stuart.yoder, linux-arm-kernel, linuxarm
Cc: Ding Tianhong
Erratum Hisilicon-161601 says that the ARM generic timer counter "has the
potential to contain an erroneous value when the timer value changes".
Accesses to TVAL (both read and write) are also affected due to the implicit counter
read. Accesses to CVAL are not affected.
The workaround is to reread the system count registers until the value of the second
read is larger than the first one by less than 32, the system counter can be guaranteed
not to return wrong value twice by back-to-back read and the error value is always larger
than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.
v2: Introducing a new generic erratum handling mechanism for fsl,a008585 and hisilicon,161601.
Significant rework based on feedback, including seperate the fsl erratum a008585
to another patch, update the erratum name and remove unwanted code.
v3: Introducing the erratum_workaround_set_sne generic function for fsl erratum a008585
and make the #define __fsl_a008585_read_reg to be private to the .c file instead of
being globally visible. After discussion with Marc and Will, a consensus decision was
made to remove the commandline parameter for enabling fsl,erratum-a008585 erratum,
and make some generic name more specific, export timer_unstable_counter_workaround
for module access.
Significant rework based on feedback, including fix some alignment problem, make the
#define __hisi_161601_read_reg to be private to the .c file instead of being globally
visible, add more accurate annotation and modify a bit of logical format to enable
arch_timer_read_ool_enabled, remove the kernel commandline parameter
clocksource.arm_arch_timer.hisilicon-161601.
Introduce a generic aquick framework for erratum in ACPI mode.
v4: rename the quirk handler parameter to make it more generic, and
avoid break loop when handling the quirk becasue it need to
support multi quirks handler.
update some data structures for acpi mode.
v5: Adapt the new kernel-parameters.txt for latest kernel version.
Set the retries of reread system counter to 50, because it is possible
that some interrupts may lead to more than twice read errors and break the loop,
it will trigger the warning, so we set the number of retries far beyond the number of
iterations the loop has been observed to take.
v6: The last 2 patches in the previous version about the ACPI mode will conflict witch Fuwei's
GTDT patches, so remove the ACPI part and only support the DT base code for this patch set.
We have trigger a bug when select the CONFIG_FUNCTION_GRAPH_TRACER and enable function_graph
to /sys/kernel/debug/tracing/current_tracer, the system will stall into an endless loop, it looks
like that the ftrace_graph_caller will be related to xxx.read_cntvct_el0 and read the system counter
again, so mark the xxx.read_cntvct_el0 with notrace to fix the problem.
v7: Introduce a new general config symbol named CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND to enable the workaround
for any chips which has similar arch timer erratum just like "fsl,erratum_a008585" and "hisilicon,erratum_161601",
modify the struct arch_timer_erratum_workaround to be compatible different chip erratum more easily, and
reconstruction some code base on the new config symbol and struct, thanks to Marc's suggestion.
v8: The original erratum ID could not cover all modules, which only specified <Errata-Prefix><SerialNum>, so after
discussion with the soc team, we decide to use the new ID "161010101" for this timer erratum which consist of
<Errata-Prefix><SeriesFlag><ModuleID><SerialNum> and also update the hisilicon erratum official documents.
Ding Tianhong (4):
arm64: arch_timer: Add device tree binding for hisilicon-161010101
erratum
arm64: arch_timer: Introduce a generic erratum handing mechanism for
fsl-a008585
arm64: arch_timer: Work around Erratum Hisilicon-161010101
arm64: arch timer: Add timer erratum property for Hip05-d02 and
Hip06-d03
Documentation/admin-guide/kernel-parameters.txt | 9 --
Documentation/arm64/silicon-errata.txt | 43 +++---
.../devicetree/bindings/arm/arch_timer.txt | 8 ++
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 1 +
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 1 +
arch/arm64/include/asm/arch_timer.h | 38 ++----
drivers/clocksource/Kconfig | 18 +++
drivers/clocksource/arm_arch_timer.c | 150 +++++++++++++++------
8 files changed, 173 insertions(+), 95 deletions(-)
--
1.9.0
^ permalink raw reply
* [PATCH v8 1/4] arm64: arch_timer: Add device tree binding for hisilicon-161010101 erratum
From: Ding Tianhong @ 2017-01-19 11:14 UTC (permalink / raw)
To: catalin.marinas, will.deacon, marc.zyngier, mark.rutland, oss,
devicetree, shawnguo, stuart.yoder, linux-arm-kernel, linuxarm
Cc: Ding Tianhong
In-Reply-To: <1484824474-12172-1-git-send-email-dingtianhong@huawei.com>
This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward. So, describe it
in the device tree.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/arch_timer.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index ad440a2..9116934 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -31,6 +31,14 @@ to deliver its interrupts via SPIs.
This also affects writes to the tval register, due to the implicit
counter read.
+- hisilicon,erratum-161010101 : A boolean property. Indicates the presence of
+ erratum 161010101, which says that reading the counter is unreliable unless
+ reading twice on the register and the value of the second read is larger
+ than the first by less than 32. If the verification is unsuccessful, then
+ discard the value of this read and repeat this procedure until the verification
+ is successful. This also affects writes to the tval register, due to the
+ implicit counter read.
+
** Optional properties:
- arm,cpu-registers-not-fw-configured : Firmware does not initialize
--
1.9.0
^ permalink raw reply related
* [PATCH v8 2/4] arm64: arch_timer: Introduce a generic erratum handing mechanism for fsl-a008585
From: Ding Tianhong @ 2017-01-19 11:14 UTC (permalink / raw)
To: catalin.marinas, will.deacon, marc.zyngier, mark.rutland, oss,
devicetree, shawnguo, stuart.yoder, linux-arm-kernel, linuxarm
Cc: Ding Tianhong
In-Reply-To: <1484824474-12172-1-git-send-email-dingtianhong@huawei.com>
The workaround for hisilicon,161010101 will check the return value of the system counter
by different way, in order to distinguish with the fsl-a008585 workaround, introduce
a new generic erratum handing mechanism for fsl-a008585 and rename some functions.
After discussion with Marc and Will, a consensus decision was made to remove the commandline
parameter for enabling fsl,erratum-a008585 erratum.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
Documentation/admin-guide/kernel-parameters.txt | 9 --
arch/arm64/include/asm/arch_timer.h | 38 +++------
drivers/clocksource/Kconfig | 8 ++
drivers/clocksource/arm_arch_timer.c | 105 ++++++++++++++----------
4 files changed, 84 insertions(+), 76 deletions(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 21e2d88..76437ad 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -539,15 +539,6 @@
loops can be debugged more effectively on production
systems.
- clocksource.arm_arch_timer.fsl-a008585=
- [ARM64]
- Format: <bool>
- Enable/disable the workaround of Freescale/NXP
- erratum A-008585. This can be useful for KVM
- guests, if the guest device tree doesn't show the
- erratum. If unspecified, the workaround is
- enabled based on the device tree.
-
clearcpuid=BITNUM [X86]
Disable CPUID feature X for the kernel. See
arch/x86/include/asm/cpufeatures.h for the valid bit
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index eaa5bbe..b4b3400 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -29,41 +29,29 @@
#include <clocksource/arm_arch_timer.h>
-#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585)
+#if IS_ENABLED(CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND)
extern struct static_key_false arch_timer_read_ool_enabled;
-#define needs_fsl_a008585_workaround() \
+#define needs_unstable_timer_counter_workaround() \
static_branch_unlikely(&arch_timer_read_ool_enabled)
#else
-#define needs_fsl_a008585_workaround() false
+#define needs_unstable_timer_counter_workaround() false
#endif
-u32 __fsl_a008585_read_cntp_tval_el0(void);
-u32 __fsl_a008585_read_cntv_tval_el0(void);
-u64 __fsl_a008585_read_cntvct_el0(void);
-/*
- * The number of retries is an arbitrary value well beyond the highest number
- * of iterations the loop has been observed to take.
- */
-#define __fsl_a008585_read_reg(reg) ({ \
- u64 _old, _new; \
- int _retries = 200; \
- \
- do { \
- _old = read_sysreg(reg); \
- _new = read_sysreg(reg); \
- _retries--; \
- } while (unlikely(_old != _new) && _retries); \
- \
- WARN_ON_ONCE(!_retries); \
- _new; \
-})
+struct arch_timer_erratum_workaround {
+ const char *id; /* Indicate the Erratum ID */
+ u32 (*read_cntp_tval_el0)(void);
+ u32 (*read_cntv_tval_el0)(void);
+ u64 (*read_cntvct_el0)(void);
+};
+
+extern const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround;
#define arch_timer_reg_read_stable(reg) \
({ \
u64 _val; \
- if (needs_fsl_a008585_workaround()) \
- _val = __fsl_a008585_read_##reg(); \
+ if (needs_unstable_timer_counter_workaround()) \
+ _val = timer_unstable_counter_workaround->read_##reg();\
else \
_val = read_sysreg(reg); \
_val; \
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 4866f7a..04c2b93 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -325,10 +325,18 @@ config ARM_ARCH_TIMER_EVTSTREAM
This must be disabled for hardware validation purposes to detect any
hardware anomalies of missing events.
+config ARM_ARCH_TIMER_OOL_WORKAROUND
+ bool "Workaround for arm arch timer unstable counter"
+ depends on FSL_ERRATUM_A008585
+ help
+ This option would only be enabled by Freescale/NXP Erratum A-008585
+ or something else chip has similar erratum.
+
config FSL_ERRATUM_A008585
bool "Workaround for Freescale/NXP Erratum A-008585"
default y
depends on ARM_ARCH_TIMER && ARM64
+ select ARM_ARCH_TIMER_OOL_WORKAROUND
help
This option enables a workaround for Freescale/NXP Erratum
A-008585 ("ARM generic timer may contain an erroneous
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 02fef68..2487c66 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -96,41 +96,59 @@ static int __init early_evtstrm_cfg(char *buf)
*/
#ifdef CONFIG_FSL_ERRATUM_A008585
-DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
-EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
-
-static int fsl_a008585_enable = -1;
-
-static int __init early_fsl_a008585_cfg(char *buf)
-{
- int ret;
- bool val;
- ret = strtobool(buf, &val);
- if (ret)
- return ret;
-
- fsl_a008585_enable = val;
- return 0;
-}
-early_param("clocksource.arm_arch_timer.fsl-a008585", early_fsl_a008585_cfg);
-
-u32 __fsl_a008585_read_cntp_tval_el0(void)
+/*
+ * The number of retries is an arbitrary value well beyond the highest number
+ * of iterations the loop has been observed to take.
+ */
+#define __fsl_a008585_read_reg(reg) ({ \
+ u64 _old, _new; \
+ int _retries = 200; \
+ \
+ do { \
+ _old = read_sysreg(reg); \
+ _new = read_sysreg(reg); \
+ _retries--; \
+ } while (unlikely(_old != _new) && _retries); \
+ \
+ WARN_ON_ONCE(!_retries); \
+ _new; \
+})
+
+static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
{
return __fsl_a008585_read_reg(cntp_tval_el0);
}
-u32 __fsl_a008585_read_cntv_tval_el0(void)
+static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
{
return __fsl_a008585_read_reg(cntv_tval_el0);
}
-u64 __fsl_a008585_read_cntvct_el0(void)
+static u64 notrace fsl_a008585_read_cntvct_el0(void)
{
return __fsl_a008585_read_reg(cntvct_el0);
}
-EXPORT_SYMBOL(__fsl_a008585_read_cntvct_el0);
-#endif /* CONFIG_FSL_ERRATUM_A008585 */
+#endif
+
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
+const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL;
+EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
+
+DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
+EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
+
+static const struct arch_timer_erratum_workaround ool_workarounds[] = {
+#ifdef CONFIG_FSL_ERRATUM_A008585
+ {
+ .id = "fsl,erratum-a008585",
+ .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
+ .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
+ .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
+ },
+#endif
+};
+#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
static __always_inline
void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
@@ -281,8 +299,8 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
}
-#ifdef CONFIG_FSL_ERRATUM_A008585
-static __always_inline void fsl_a008585_set_next_event(const int access,
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
+static __always_inline void erratum_set_next_event_generic(const int access,
unsigned long evt, struct clock_event_device *clk)
{
unsigned long ctrl;
@@ -300,20 +318,20 @@ static __always_inline void fsl_a008585_set_next_event(const int access,
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
}
-static int fsl_a008585_set_next_event_virt(unsigned long evt,
+static int erratum_set_next_event_virt(unsigned long evt,
struct clock_event_device *clk)
{
- fsl_a008585_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
+ erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
return 0;
}
-static int fsl_a008585_set_next_event_phys(unsigned long evt,
+static int erratum_set_next_event_phys(unsigned long evt,
struct clock_event_device *clk)
{
- fsl_a008585_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
+ erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
return 0;
}
-#endif /* CONFIG_FSL_ERRATUM_A008585 */
+#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
static int arch_timer_set_next_event_virt(unsigned long evt,
struct clock_event_device *clk)
@@ -343,16 +361,16 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
return 0;
}
-static void fsl_a008585_set_sne(struct clock_event_device *clk)
+static void erratum_workaround_set_sne(struct clock_event_device *clk)
{
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
return;
if (arch_timer_uses_ppi == VIRT_PPI)
- clk->set_next_event = fsl_a008585_set_next_event_virt;
+ clk->set_next_event = erratum_set_next_event_virt;
else
- clk->set_next_event = fsl_a008585_set_next_event_phys;
+ clk->set_next_event = erratum_set_next_event_phys;
#endif
}
@@ -385,7 +403,7 @@ static void __arch_timer_setup(unsigned type,
BUG();
}
- fsl_a008585_set_sne(clk);
+ erratum_workaround_set_sne(clk);
} else {
clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
clk->name = "arch_mem_timer";
@@ -605,7 +623,7 @@ static void __init arch_counter_register(unsigned type)
clocksource_counter.archdata.vdso_direct = true;
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
/*
* Don't use the vdso fastpath if errata require using
* the out-of-line counter accessor.
@@ -893,12 +911,15 @@ static int __init arch_timer_of_init(struct device_node *np)
arch_timer_c3stop = !of_property_read_bool(np, "always-on");
-#ifdef CONFIG_FSL_ERRATUM_A008585
- if (fsl_a008585_enable < 0)
- fsl_a008585_enable = of_property_read_bool(np, "fsl,erratum-a008585");
- if (fsl_a008585_enable) {
- static_branch_enable(&arch_timer_read_ool_enabled);
- pr_info("Enabling workaround for FSL erratum A-008585\n");
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
+ for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
+ if (of_property_read_bool(np, ool_workarounds[i].id)) {
+ timer_unstable_counter_workaround = &ool_workarounds[i];
+ static_branch_enable(&arch_timer_read_ool_enabled);
+ pr_info("arch_timer: Enabling workaround for %s\n",
+ timer_unstable_counter_workaround->id);
+ break;
+ }
}
#endif
--
1.9.0
^ permalink raw reply related
* [PATCH v8 3/4] arm64: arch_timer: Work around Erratum Hisilicon-161010101
From: Ding Tianhong @ 2017-01-19 11:14 UTC (permalink / raw)
To: catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
marc.zyngier-5wv7dgnIgG8, mark.rutland-5wv7dgnIgG8,
oss-fOR+EgIDQEHk1uMJSBkQmQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A, stuart.yoder-3arQi8VN3Tc,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linuxarm-hv44wF8Li93QT0dZR+AlfA
Cc: Ding Tianhong
In-Reply-To: <1484824474-12172-1-git-send-email-dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Erratum Hisilicon-161010101 says that the ARM generic timer counter "has the
potential to contain an erroneous value when the timer value changes".
Accesses to TVAL (both read and write) are also affected due to the implicit counter
read. Accesses to CVAL are not affected.
The workaround is to reread the system count registers until the value of the second
read is larger than the first one by less than 32, the system counter can be guaranteed
not to return wrong value twice by back-to-back read and the error value is always larger
than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.
The hisilicon erratum CONFIG name is too long, breaking the line format in silicon-errata.txt,
so extended the character spacing to fit all the erratum config.
Signed-off-by: Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
Documentation/arm64/silicon-errata.txt | 43 ++++++++++++++---------------
drivers/clocksource/Kconfig | 12 ++++++++-
drivers/clocksource/arm_arch_timer.c | 49 ++++++++++++++++++++++++++++++++++
3 files changed, 82 insertions(+), 22 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 405da11..0aaae35 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -42,24 +42,25 @@ file acts as a registry of software workarounds in the Linux Kernel and
will be updated when new workarounds are committed and backported to
stable kernels.
-| Implementor | Component | Erratum ID | Kconfig |
-+----------------+-----------------+-----------------+-------------------------+
-| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
-| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
-| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
-| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
-| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
-| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
-| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
-| ARM | Cortex-A57 | #852523 | N/A |
-| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
-| ARM | Cortex-A72 | #853709 | N/A |
-| ARM | MMU-500 | #841119,#826419 | N/A |
-| | | | |
-| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
-| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
-| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
-| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
-| Cavium | ThunderX SMMUv2 | #27704 | N/A |
-| | | | |
-| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
+| Implementor | Component | Erratum ID | Kconfig |
++----------------+-----------------+-----------------+---------------------------------+
+| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
+| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
+| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
+| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
+| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
+| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
+| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
+| ARM | Cortex-A57 | #852523 | N/A |
+| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
+| ARM | Cortex-A72 | #853709 | N/A |
+| ARM | MMU-500 | #841119,#826419 | N/A |
+| | | | |
+| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
+| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
+| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
+| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
+| Cavium | ThunderX SMMUv2 | #27704 | N/A |
+| | | | |
+| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
+| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 04c2b93..628cb44 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -327,7 +327,7 @@ config ARM_ARCH_TIMER_EVTSTREAM
config ARM_ARCH_TIMER_OOL_WORKAROUND
bool "Workaround for arm arch timer unstable counter"
- depends on FSL_ERRATUM_A008585
+ depends on FSL_ERRATUM_A008585 || HISILICON_ERRATUM_161010101
help
This option would only be enabled by Freescale/NXP Erratum A-008585
or something else chip has similar erratum.
@@ -343,6 +343,16 @@ config FSL_ERRATUM_A008585
value"). The workaround will only be active if the
fsl,erratum-a008585 property is found in the timer node.
+config HISILICON_ERRATUM_161010101
+ bool "Workaround for Hisilicon Erratum 161010101"
+ default y
+ select ARM_ARCH_TIMER_OOL_WORKAROUND
+ depends on ARM_ARCH_TIMER && ARM64
+ help
+ This option enables a workaround for Hisilicon Erratum
+ 161010101. The workaround will be active if the hisilicon,erratum-161010101
+ property is found in the timer node.
+
config ARM_GLOBAL_TIMER
bool "Support for the ARM global timer" if COMPILE_TEST
select CLKSRC_OF if OF
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 2487c66..7451b62 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -131,6 +131,47 @@ static u64 notrace fsl_a008585_read_cntvct_el0(void)
}
#endif
+#ifdef CONFIG_HISILICON_ERRATUM_161010101
+/*
+ * Verify whether the value of the second read is larger than the first by
+ * less than 32 is the only way to confirm the value is correct, so clear the
+ * lower 5 bits to check whether the difference is greater than 32 or not.
+ * Theoretically the erratum should not occur more than twice in succession
+ * when reading the system counter, but it is possible that some interrupts
+ * may lead to more than twice read errors, triggering the warning, so setting
+ * the number of retries far beyond the number of iterations the loop has been
+ * observed to take.
+ */
+#define __hisi_161010101_read_reg(reg) ({ \
+ u64 _old, _new; \
+ int _retries = 50; \
+ \
+ do { \
+ _old = read_sysreg(reg); \
+ _new = read_sysreg(reg); \
+ _retries--; \
+ } while (unlikely((_new - _old) >> 5) && _retries); \
+ \
+ WARN_ON_ONCE(!_retries); \
+ _new; \
+})
+
+static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
+{
+ return __hisi_161010101_read_reg(cntp_tval_el0);
+}
+
+static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
+{
+ return __hisi_161010101_read_reg(cntv_tval_el0);
+}
+
+static u64 notrace hisi_161010101_read_cntvct_el0(void)
+{
+ return __hisi_161010101_read_reg(cntvct_el0);
+}
+#endif
+
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL;
EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
@@ -147,6 +188,14 @@ static u64 notrace fsl_a008585_read_cntvct_el0(void)
.read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
},
#endif
+#ifdef CONFIG_HISILICON_ERRATUM_161010101
+ {
+ .id = "hisilicon,erratum-161010101",
+ .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
+ .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
+ .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
+ },
+#endif
};
#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
--
1.9.0
--
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^ permalink raw reply related
* [PATCH v8 4/4] arm64: arch timer: Add timer erratum property for Hip05-d02 and Hip06-d03
From: Ding Tianhong @ 2017-01-19 11:14 UTC (permalink / raw)
To: catalin.marinas, will.deacon, marc.zyngier, mark.rutland, oss,
devicetree, shawnguo, stuart.yoder, linux-arm-kernel, linuxarm
Cc: Ding Tianhong
In-Reply-To: <1484824474-12172-1-git-send-email-dingtianhong@huawei.com>
Enable workaround for hisilicon erratum 161010101 on Hip05-d02 and Hip06-d03 board.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 1 +
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 4b472a3..6b76f3a 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -281,6 +281,7 @@
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ hisilicon,erratum-161010101;
};
pmu {
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index a049b64..cf8b9db 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -260,6 +260,7 @@
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ hisilicon,erratum-161010101;
};
pmu {
--
1.9.0
^ permalink raw reply related
* Re: [PATCH v3 06/13] ARM: davinci: da850: model the SATA refclk
From: Bartosz Golaszewski @ 2017-01-19 11:18 UTC (permalink / raw)
To: David Lechner
Cc: Kevin Hilman, Sekhar Nori, Patrick Titiano, Michael Turquette,
Tejun Heo, Rob Herring, Mark Rutland, Russell King, linux-ide,
linux-devicetree, LKML, arm-soc
In-Reply-To: <ff4deee6-9700-fff3-be96-0ad2f008914b@lechnology.com>
2017-01-18 18:26 GMT+01:00 David Lechner <david@lechnology.com>:
> On 01/18/2017 07:19 AM, Bartosz Golaszewski wrote:
>>
>> int __init da850_register_sata(unsigned long refclkpn)
>> {
>> + int ret;
>> +
>> /* please see comment in drivers/ata/ahci_da850.c */
>> BUG_ON(refclkpn != 100 * 1000 * 1000);
>
>
> This BUG_ON() should be removed since the sata driver can now handle other
> clock frequencies.
>
Right, will fix in v4.
Thanks,
Bartosz Golaszewski
^ permalink raw reply
* Re: [PATCH 00/13] Ingenic JZ4740 / JZ4780 pinctrl driver
From: Paul Cercueil @ 2017-01-19 11:19 UTC (permalink / raw)
To: Thierry Reding
Cc: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Ulf Hansson, Boris Brezillon, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, linux-gpio,
devicetree, linux-kernel, linux-mips, linux-mmc, linux-mtd,
linux-pwm, linux-fbdev, james.hogan
In-Reply-To: <20170118071530.GA18989@ulmo.ba.sec>
Le 2017-01-18 08:15, Thierry Reding a écrit :
> On Wed, Jan 18, 2017 at 12:14:08AM +0100, Paul Cercueil wrote:
> [...]
>
>> One problem still unresolved: the pinctrl framework does not allow us
>> to configure each pin on demand (someone please prove me wrong), when
>> the various PWM channels are requested or released. For instance, the
>> PWM channels can be configured from sysfs, which would require all PWM
>> pins to be configured properly beforehand for the PWM function,
>> eventually causing conflicts with other platform or board drivers.
>
> Still catching up on a lot of email, so I haven't gone through the
> entire series. But I don't think the above is true.
>
> My understanding is that you can have separate pin groups for each
> pin (provided the hardware supports that) and then control each of
> these groups dynamically at runtime.
>
> That is you could have the PWM driver's ->request() and ->free()
> call into the pinctrl framework to select the correct pinmux
> configuration as necessary.
Thanks for the feedback.
The problem with pinctrl and PWM, is that the pinctrl API works by
"states".
A default state, sleep state, and basically any custom state that the
devicetree
provides. This works well until you need to control individually each
pin; with
8 pins, you would need 2^8 states, each one corresponding to a given
configuration.
-Paul
^ permalink raw reply
* Re: [PATCH 13/13] MIPS: jz4740: Remove custom GPIO code
From: Paul Cercueil @ 2017-01-19 11:24 UTC (permalink / raw)
To: Thierry Reding
Cc: Ralf Baechle, Linus Walleij, Rob Herring, Mark Rutland,
Ulf Hansson, Boris Brezillon, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, linux-gpio,
devicetree, linux-kernel, linux-mips, linux-mmc, linux-mtd,
linux-pwm, linux-fbdev, james.hogan
In-Reply-To: <20170118072751.GC18989@ulmo.ba.sec>
Le 2017-01-18 08:27, Thierry Reding a écrit :
> On Wed, Jan 18, 2017 at 12:14:21AM +0100, Paul Cercueil wrote:
>
>> All the drivers for the various hardware elements of the jz4740 SoC
>> have been modified to use the pinctrl framework for their pin
>> configuration needs. As such, this platform code is now unused and can
>> be deleted. Signed-off-by: Paul Cercueil <paul@crapouillou.net> ---
>> arch/mips/include/asm/mach-jz4740/gpio.h | 371 ----------------------
>> arch/mips/jz4740/Makefile | 2 - arch/mips/jz4740/gpio.c | 519
>> ------------------------------- 3 files changed, 892 deletions(-)
>> delete mode 100644 arch/mips/jz4740/gpio.c
>
> Have you considered how this could best be merged? It's probably
> easiest
> to take all of this through the MIPS tree because we have an addition
> of
> the pinctrl that would be a replacement for the GPIO code, while at the
> same time a bunch of drivers rely on the JZ4740 GPIO code for
> successful
> compilation.
>
> That's slightly complicated by the number of drivers, so needs a lot of
> coordination, but it's not the worst I've seen.
>
> Maybe one other solution that would make the transition easier would be
> to stub out the GPIO functions if the pinctrl driver is enabled, and do
> the removal of the mach-jz4740/gpio.h after all drivers have been
> merged
> through their corresponding subsystem trees. That way all drivers
> should
> remain compilable and functional at runtime, while still having the
> possibility to merge through the subsystem trees.
>
> That said, the whole series is fairly simple, so merging everything
> through the MIPS tree sounds like the easiest way to go.
>
> Thierry
I think it would make sense to merge it through the MIPS tree, yes,
considering that the patches for the drivers in the other subsystems are
quite small, and that they just remove code (well, except the pinctrl
driver itself). Besides, the files modified are not touched very often
so the chances of breakage are pretty low.
-Paul
^ permalink raw reply
* [PATCH RESEND v8 0/4] arm64: arch_timer: Add workaround for hisilicon-161010101 erratum
From: Ding Tianhong @ 2017-01-19 11:46 UTC (permalink / raw)
To: catalin.marinas, will.deacon, marc.zyngier, mark.rutland, oss,
devicetree, shawnguo, stuart.yoder, linux-arm-kernel, linuxarm
Cc: Ding Tianhong
Erratum Hisilicon-161010101 says that the ARM generic timer counter "has the
potential to contain an erroneous value when the timer value changes".
Accesses to TVAL (both read and write) are also affected due to the implicit counter
read. Accesses to CVAL are not affected.
The workaround is to reread the system count registers until the value of the second
read is larger than the first one by less than 32, the system counter can be guaranteed
not to return wrong value twice by back-to-back read and the error value is always larger
than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.
v2: Introducing a new generic erratum handling mechanism for fsl,a008585 and hisilicon,161601.
Significant rework based on feedback, including seperate the fsl erratum a008585
to another patch, update the erratum name and remove unwanted code.
v3: Introducing the erratum_workaround_set_sne generic function for fsl erratum a008585
and make the #define __fsl_a008585_read_reg to be private to the .c file instead of
being globally visible. After discussion with Marc and Will, a consensus decision was
made to remove the commandline parameter for enabling fsl,erratum-a008585 erratum,
and make some generic name more specific, export timer_unstable_counter_workaround
for module access.
Significant rework based on feedback, including fix some alignment problem, make the
#define __hisi_161601_read_reg to be private to the .c file instead of being globally
visible, add more accurate annotation and modify a bit of logical format to enable
arch_timer_read_ool_enabled, remove the kernel commandline parameter
clocksource.arm_arch_timer.hisilicon-161601.
Introduce a generic aquick framework for erratum in ACPI mode.
v4: rename the quirk handler parameter to make it more generic, and
avoid break loop when handling the quirk becasue it need to
support multi quirks handler.
update some data structures for acpi mode.
v5: Adapt the new kernel-parameters.txt for latest kernel version.
Set the retries of reread system counter to 50, because it is possible
that some interrupts may lead to more than twice read errors and break the loop,
it will trigger the warning, so we set the number of retries far beyond the number of
iterations the loop has been observed to take.
v6: The last 2 patches in the previous version about the ACPI mode will conflict witch Fuwei's
GTDT patches, so remove the ACPI part and only support the DT base code for this patch set.
We have trigger a bug when select the CONFIG_FUNCTION_GRAPH_TRACER and enable function_graph
to /sys/kernel/debug/tracing/current_tracer, the system will stall into an endless loop, it looks
like that the ftrace_graph_caller will be related to xxx.read_cntvct_el0 and read the system counter
again, so mark the xxx.read_cntvct_el0 with notrace to fix the problem.
v7: Introduce a new general config symbol named CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND to enable the workaround
for any chips which has similar arch timer erratum just like "fsl,erratum_a008585" and "hisilicon,erratum_161601",
modify the struct arch_timer_erratum_workaround to be compatible different chip erratum more easily, and
reconstruction some code base on the new config symbol and struct, thanks to Marc's suggestion.
v8: The original erratum ID could not cover all modules, which only specified <Errata-Prefix><SerialNum>, so after
discussion with the soc team, we decide to use the new ID "161010101" for this timer erratum which consist of
<Errata-Prefix><SeriesFlag><ModuleID><SerialNum> and also update the hisilicon erratum official documents.
Ding Tianhong (4):
arm64: arch_timer: Add device tree binding for hisilicon-161010101
erratum
arm64: arch_timer: Introduce a generic erratum handing mechanism for
fsl-a008585
arm64: arch_timer: Work around Erratum Hisilicon-161010101
arm64: arch timer: Add timer erratum property for Hip05-d02 and
Hip06-d03
Documentation/admin-guide/kernel-parameters.txt | 9 --
Documentation/arm64/silicon-errata.txt | 43 +++---
.../devicetree/bindings/arm/arch_timer.txt | 8 ++
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 1 +
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 1 +
arch/arm64/include/asm/arch_timer.h | 38 ++----
drivers/clocksource/Kconfig | 18 +++
drivers/clocksource/arm_arch_timer.c | 150 +++++++++++++++------
8 files changed, 173 insertions(+), 95 deletions(-)
--
1.9.0
^ permalink raw reply
* [PATCH RESEND v8 1/4] arm64: arch_timer: Add device tree binding for hisilicon-161010101 erratum
From: Ding Tianhong @ 2017-01-19 11:46 UTC (permalink / raw)
To: catalin.marinas, will.deacon, marc.zyngier, mark.rutland, oss,
devicetree, shawnguo, stuart.yoder, linux-arm-kernel, linuxarm
Cc: Ding Tianhong
In-Reply-To: <1484826406-16348-1-git-send-email-dingtianhong@huawei.com>
This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward. So, describe it
in the device tree.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/arch_timer.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index ad440a2..9116934 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -31,6 +31,14 @@ to deliver its interrupts via SPIs.
This also affects writes to the tval register, due to the implicit
counter read.
+- hisilicon,erratum-161010101 : A boolean property. Indicates the presence of
+ erratum 161010101, which says that reading the counter is unreliable unless
+ reading twice on the register and the value of the second read is larger
+ than the first by less than 32. If the verification is unsuccessful, then
+ discard the value of this read and repeat this procedure until the verification
+ is successful. This also affects writes to the tval register, due to the
+ implicit counter read.
+
** Optional properties:
- arm,cpu-registers-not-fw-configured : Firmware does not initialize
--
1.9.0
^ permalink raw reply related
* [PATCH RESEND v8 2/4] arm64: arch_timer: Introduce a generic erratum handing mechanism for fsl-a008585
From: Ding Tianhong @ 2017-01-19 11:46 UTC (permalink / raw)
To: catalin.marinas, will.deacon, marc.zyngier, mark.rutland, oss,
devicetree, shawnguo, stuart.yoder, linux-arm-kernel, linuxarm
Cc: Ding Tianhong
In-Reply-To: <1484826406-16348-1-git-send-email-dingtianhong@huawei.com>
The workaround for hisilicon,161010101 will check the return value of the system counter
by different way, in order to distinguish with the fsl-a008585 workaround, introduce
a new generic erratum handing mechanism for fsl-a008585 and rename some functions.
After discussion with Marc and Will, a consensus decision was made to remove the commandline
parameter for enabling fsl,erratum-a008585 erratum.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
Documentation/admin-guide/kernel-parameters.txt | 9 --
arch/arm64/include/asm/arch_timer.h | 38 +++------
drivers/clocksource/Kconfig | 8 ++
drivers/clocksource/arm_arch_timer.c | 105 ++++++++++++++----------
4 files changed, 84 insertions(+), 76 deletions(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 21e2d88..76437ad 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -539,15 +539,6 @@
loops can be debugged more effectively on production
systems.
- clocksource.arm_arch_timer.fsl-a008585=
- [ARM64]
- Format: <bool>
- Enable/disable the workaround of Freescale/NXP
- erratum A-008585. This can be useful for KVM
- guests, if the guest device tree doesn't show the
- erratum. If unspecified, the workaround is
- enabled based on the device tree.
-
clearcpuid=BITNUM [X86]
Disable CPUID feature X for the kernel. See
arch/x86/include/asm/cpufeatures.h for the valid bit
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index eaa5bbe..b4b3400 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -29,41 +29,29 @@
#include <clocksource/arm_arch_timer.h>
-#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585)
+#if IS_ENABLED(CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND)
extern struct static_key_false arch_timer_read_ool_enabled;
-#define needs_fsl_a008585_workaround() \
+#define needs_unstable_timer_counter_workaround() \
static_branch_unlikely(&arch_timer_read_ool_enabled)
#else
-#define needs_fsl_a008585_workaround() false
+#define needs_unstable_timer_counter_workaround() false
#endif
-u32 __fsl_a008585_read_cntp_tval_el0(void);
-u32 __fsl_a008585_read_cntv_tval_el0(void);
-u64 __fsl_a008585_read_cntvct_el0(void);
-/*
- * The number of retries is an arbitrary value well beyond the highest number
- * of iterations the loop has been observed to take.
- */
-#define __fsl_a008585_read_reg(reg) ({ \
- u64 _old, _new; \
- int _retries = 200; \
- \
- do { \
- _old = read_sysreg(reg); \
- _new = read_sysreg(reg); \
- _retries--; \
- } while (unlikely(_old != _new) && _retries); \
- \
- WARN_ON_ONCE(!_retries); \
- _new; \
-})
+struct arch_timer_erratum_workaround {
+ const char *id; /* Indicate the Erratum ID */
+ u32 (*read_cntp_tval_el0)(void);
+ u32 (*read_cntv_tval_el0)(void);
+ u64 (*read_cntvct_el0)(void);
+};
+
+extern const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround;
#define arch_timer_reg_read_stable(reg) \
({ \
u64 _val; \
- if (needs_fsl_a008585_workaround()) \
- _val = __fsl_a008585_read_##reg(); \
+ if (needs_unstable_timer_counter_workaround()) \
+ _val = timer_unstable_counter_workaround->read_##reg();\
else \
_val = read_sysreg(reg); \
_val; \
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 4866f7a..04c2b93 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -325,10 +325,18 @@ config ARM_ARCH_TIMER_EVTSTREAM
This must be disabled for hardware validation purposes to detect any
hardware anomalies of missing events.
+config ARM_ARCH_TIMER_OOL_WORKAROUND
+ bool "Workaround for arm arch timer unstable counter"
+ depends on FSL_ERRATUM_A008585
+ help
+ This option would only be enabled by Freescale/NXP Erratum A-008585
+ or something else chip has similar erratum.
+
config FSL_ERRATUM_A008585
bool "Workaround for Freescale/NXP Erratum A-008585"
default y
depends on ARM_ARCH_TIMER && ARM64
+ select ARM_ARCH_TIMER_OOL_WORKAROUND
help
This option enables a workaround for Freescale/NXP Erratum
A-008585 ("ARM generic timer may contain an erroneous
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 02fef68..2487c66 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -96,41 +96,59 @@ static int __init early_evtstrm_cfg(char *buf)
*/
#ifdef CONFIG_FSL_ERRATUM_A008585
-DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
-EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
-
-static int fsl_a008585_enable = -1;
-
-static int __init early_fsl_a008585_cfg(char *buf)
-{
- int ret;
- bool val;
- ret = strtobool(buf, &val);
- if (ret)
- return ret;
-
- fsl_a008585_enable = val;
- return 0;
-}
-early_param("clocksource.arm_arch_timer.fsl-a008585", early_fsl_a008585_cfg);
-
-u32 __fsl_a008585_read_cntp_tval_el0(void)
+/*
+ * The number of retries is an arbitrary value well beyond the highest number
+ * of iterations the loop has been observed to take.
+ */
+#define __fsl_a008585_read_reg(reg) ({ \
+ u64 _old, _new; \
+ int _retries = 200; \
+ \
+ do { \
+ _old = read_sysreg(reg); \
+ _new = read_sysreg(reg); \
+ _retries--; \
+ } while (unlikely(_old != _new) && _retries); \
+ \
+ WARN_ON_ONCE(!_retries); \
+ _new; \
+})
+
+static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
{
return __fsl_a008585_read_reg(cntp_tval_el0);
}
-u32 __fsl_a008585_read_cntv_tval_el0(void)
+static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
{
return __fsl_a008585_read_reg(cntv_tval_el0);
}
-u64 __fsl_a008585_read_cntvct_el0(void)
+static u64 notrace fsl_a008585_read_cntvct_el0(void)
{
return __fsl_a008585_read_reg(cntvct_el0);
}
-EXPORT_SYMBOL(__fsl_a008585_read_cntvct_el0);
-#endif /* CONFIG_FSL_ERRATUM_A008585 */
+#endif
+
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
+const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL;
+EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
+
+DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
+EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
+
+static const struct arch_timer_erratum_workaround ool_workarounds[] = {
+#ifdef CONFIG_FSL_ERRATUM_A008585
+ {
+ .id = "fsl,erratum-a008585",
+ .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
+ .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
+ .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
+ },
+#endif
+};
+#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
static __always_inline
void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
@@ -281,8 +299,8 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
}
-#ifdef CONFIG_FSL_ERRATUM_A008585
-static __always_inline void fsl_a008585_set_next_event(const int access,
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
+static __always_inline void erratum_set_next_event_generic(const int access,
unsigned long evt, struct clock_event_device *clk)
{
unsigned long ctrl;
@@ -300,20 +318,20 @@ static __always_inline void fsl_a008585_set_next_event(const int access,
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
}
-static int fsl_a008585_set_next_event_virt(unsigned long evt,
+static int erratum_set_next_event_virt(unsigned long evt,
struct clock_event_device *clk)
{
- fsl_a008585_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
+ erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
return 0;
}
-static int fsl_a008585_set_next_event_phys(unsigned long evt,
+static int erratum_set_next_event_phys(unsigned long evt,
struct clock_event_device *clk)
{
- fsl_a008585_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
+ erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
return 0;
}
-#endif /* CONFIG_FSL_ERRATUM_A008585 */
+#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
static int arch_timer_set_next_event_virt(unsigned long evt,
struct clock_event_device *clk)
@@ -343,16 +361,16 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
return 0;
}
-static void fsl_a008585_set_sne(struct clock_event_device *clk)
+static void erratum_workaround_set_sne(struct clock_event_device *clk)
{
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
return;
if (arch_timer_uses_ppi == VIRT_PPI)
- clk->set_next_event = fsl_a008585_set_next_event_virt;
+ clk->set_next_event = erratum_set_next_event_virt;
else
- clk->set_next_event = fsl_a008585_set_next_event_phys;
+ clk->set_next_event = erratum_set_next_event_phys;
#endif
}
@@ -385,7 +403,7 @@ static void __arch_timer_setup(unsigned type,
BUG();
}
- fsl_a008585_set_sne(clk);
+ erratum_workaround_set_sne(clk);
} else {
clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
clk->name = "arch_mem_timer";
@@ -605,7 +623,7 @@ static void __init arch_counter_register(unsigned type)
clocksource_counter.archdata.vdso_direct = true;
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
/*
* Don't use the vdso fastpath if errata require using
* the out-of-line counter accessor.
@@ -893,12 +911,15 @@ static int __init arch_timer_of_init(struct device_node *np)
arch_timer_c3stop = !of_property_read_bool(np, "always-on");
-#ifdef CONFIG_FSL_ERRATUM_A008585
- if (fsl_a008585_enable < 0)
- fsl_a008585_enable = of_property_read_bool(np, "fsl,erratum-a008585");
- if (fsl_a008585_enable) {
- static_branch_enable(&arch_timer_read_ool_enabled);
- pr_info("Enabling workaround for FSL erratum A-008585\n");
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
+ for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
+ if (of_property_read_bool(np, ool_workarounds[i].id)) {
+ timer_unstable_counter_workaround = &ool_workarounds[i];
+ static_branch_enable(&arch_timer_read_ool_enabled);
+ pr_info("arch_timer: Enabling workaround for %s\n",
+ timer_unstable_counter_workaround->id);
+ break;
+ }
}
#endif
--
1.9.0
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