* [PATCH v2 1/3] arm64: dts: exynos: Fix drive strength of sd0_xxx pin definitions
From: Pankaj Dubey @ 2017-01-20 4:19 UTC (permalink / raw)
To: linux-samsung-soc, linux-arm-kernel, devicetree
Cc: krzk, kgene, robh+dt, sanath, javier, s.nawrocki, Pankaj Dubey
In-Reply-To: <1484885997-21004-1-git-send-email-pankaj.dubey@samsung.com>
As per Exynos7 datasheet FSYS1 pinctrl block does not support drive
strength value of 0x3. This patch fixes this and update the correct
drive strength for sd0_xxx pin definitions.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
index 8232198..7ebb939 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -497,49 +497,49 @@
samsung,pins = "gpr0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
- samsung,pin-drv = <3>;
+ samsung,pin-drv = <4>;
};
sd0_cmd: sd0-cmd {
samsung,pins = "gpr0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
- samsung,pin-drv = <3>;
+ samsung,pin-drv = <4>;
};
sd0_ds: sd0-ds {
samsung,pins = "gpr0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
- samsung,pin-drv = <3>;
+ samsung,pin-drv = <4>;
};
sd0_qrdy: sd0-qrdy {
samsung,pins = "gpr0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
- samsung,pin-drv = <3>;
+ samsung,pin-drv = <4>;
};
sd0_bus1: sd0-bus-width1 {
samsung,pins = "gpr1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
- samsung,pin-drv = <3>;
+ samsung,pin-drv = <4>;
};
sd0_bus4: sd0-bus-width4 {
samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
- samsung,pin-drv = <3>;
+ samsung,pin-drv = <4>;
};
sd0_bus8: sd0-bus-width8 {
samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
- samsung,pin-drv = <3>;
+ samsung,pin-drv = <4>;
};
sd1_clk: sd1-clk {
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/3] pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions
From: Pankaj Dubey @ 2017-01-20 4:19 UTC (permalink / raw)
To: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: krzk-DgEjT+Ai2ygdnm+yROfE0A, kgene-DgEjT+Ai2ygdnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, sanath-Sze3O3UU22JBDgjK7y7TUQ,
javier-JPH+aEBZ4P+UEJcrhfAQsw, s.nawrocki-Sze3O3UU22JBDgjK7y7TUQ,
Pankaj Dubey
In-Reply-To: <1484885997-21004-1-git-send-email-pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Exynos7 SoC pinctrl configurations are similar to existing Exynos4/5 except
for FSYS1 pinctrl drive strengths. So adding Exynos7 specific FSYS1 blocks
pinctrl driver strength related macros which will be used in Exynos7
DTSi files.
Signed-off-by: Pankaj Dubey <pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Reviewed-by: Alim Akhtar <alim.akhtar-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Acked-by: Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
include/dt-bindings/pinctrl/samsung.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pinctrl/samsung.h
index 6276eb7..3f1d583 100644
--- a/include/dt-bindings/pinctrl/samsung.h
+++ b/include/dt-bindings/pinctrl/samsung.h
@@ -54,4 +54,12 @@
#define EXYNOS_PIN_FUNC_6 6
#define EXYNOS_PIN_FUNC_F 0xf
+/* Drive strengths for Exynos7 FSYS1 block */
+#define EXYNOS7_FSYS1_PIN_DRV_LV1 0
+#define EXYNOS7_FSYS1_PIN_DRV_LV2 4
+#define EXYNOS7_FSYS1_PIN_DRV_LV3 2
+#define EXYNOS7_FSYS1_PIN_DRV_LV4 6
+#define EXYNOS7_FSYS1_PIN_DRV_LV5 1
+#define EXYNOS7_FSYS1_PIN_DRV_LV6 5
+
#endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v2 3/3] arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7
From: Pankaj Dubey @ 2017-01-20 4:19 UTC (permalink / raw)
To: linux-samsung-soc, linux-arm-kernel, devicetree
Cc: krzk, kgene, robh+dt, sanath, javier, s.nawrocki, Pankaj Dubey
In-Reply-To: <1484885997-21004-1-git-send-email-pankaj.dubey@samsung.com>
Usage of DTS macros instead of hard-coded numbers makes code easier to
read. One does not have to remember which value means pull-up/down or
specific driver strength.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 4 +-
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 302 ++++++++++++------------
2 files changed, 154 insertions(+), 152 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index c528dd5..25d9b4a 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -328,8 +328,8 @@
&pinctrl_alive {
pmic_irq: pmic-irq {
samsung,pins = "gpa0-2";
- samsung,pin-pud = <3>;
- samsung,pin-drv = <3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
};
};
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
index 7ebb939..8f58850 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -12,6 +12,8 @@
* published by the Free Software Foundation.
*/
+#include <dt-bindings/pinctrl/samsung.h>
+
&pinctrl_alive {
gpa0: gpa0 {
gpio-controller;
@@ -187,163 +189,163 @@
hs_i2c10_bus: hs-i2c10-bus {
samsung,pins = "gpb0-1", "gpb0-0";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
hs_i2c11_bus: hs-i2c11-bus {
samsung,pins = "gpb0-3", "gpb0-2";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
hs_i2c2_bus: hs-i2c2-bus {
samsung,pins = "gpd0-3", "gpd0-2";
- samsung,pin-function = <3>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
uart0_data: uart0-data {
samsung,pins = "gpd0-0", "gpd0-1";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
uart0_fctl: uart0-fctl {
samsung,pins = "gpd0-2", "gpd0-3";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
uart2_data: uart2-data {
samsung,pins = "gpd1-4", "gpd1-5";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
hs_i2c3_bus: hs-i2c3-bus {
samsung,pins = "gpd1-3", "gpd1-2";
- samsung,pin-function = <3>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
uart1_data: uart1-data {
samsung,pins = "gpd1-0", "gpd1-1";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
uart1_fctl: uart1-fctl {
samsung,pins = "gpd1-2", "gpd1-3";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
hs_i2c0_bus: hs-i2c0-bus {
samsung,pins = "gpd2-1", "gpd2-0";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
hs_i2c1_bus: hs-i2c1-bus {
samsung,pins = "gpd2-3", "gpd2-2";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
hs_i2c9_bus: hs-i2c9-bus {
samsung,pins = "gpd2-7", "gpd2-6";
- samsung,pin-function = <3>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
pwm0_out: pwm0-out {
samsung,pins = "gpd2-4";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
pwm1_out: pwm1-out {
samsung,pins = "gpd2-5";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
pwm2_out: pwm2-out {
samsung,pins = "gpd2-6";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
pwm3_out: pwm3-out {
samsung,pins = "gpd2-7";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
hs_i2c8_bus: hs-i2c8-bus {
samsung,pins = "gpd5-3", "gpd5-2";
- samsung,pin-function = <3>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
uart3_data: uart3-data {
samsung,pins = "gpd5-0", "gpd5-1";
- samsung,pin-function = <3>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
spi2_bus: spi2-bus {
samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
spi1_bus: spi1-bus {
samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
spi0_bus: spi0-bus {
samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
hs_i2c4_bus: hs-i2c4-bus {
samsung,pins = "gpg3-1", "gpg3-0";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
hs_i2c5_bus: hs-i2c5-bus {
samsung,pins = "gpg3-3", "gpg3-2";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
};
@@ -358,9 +360,9 @@
hs_i2c6_bus: hs-i2c6-bus {
samsung,pins = "gpj0-1", "gpj0-0";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
};
@@ -375,9 +377,9 @@
hs_i2c7_bus: hs-i2c7-bus {
samsung,pins = "gpj1-1", "gpj1-0";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
};
@@ -392,9 +394,9 @@
spi3_bus: spi3-bus {
samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
};
@@ -409,9 +411,9 @@
spi4_bus: spi4-bus {
samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
};
@@ -426,37 +428,37 @@
sd2_clk: sd2-clk {
samsung,pins = "gpr4-0";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <3>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
};
sd2_cmd: sd2-cmd {
samsung,pins = "gpr4-1";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <3>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
};
sd2_cd: sd2-cd {
samsung,pins = "gpr4-2";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <3>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
};
sd2_bus1: sd2-bus-width1 {
samsung,pins = "gpr4-3";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <3>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
};
sd2_bus4: sd2-bus-width4 {
samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <3>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
};
};
@@ -495,107 +497,107 @@
sd0_clk: sd0-clk {
samsung,pins = "gpr0-0";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <4>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
};
sd0_cmd: sd0-cmd {
samsung,pins = "gpr0-1";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <4>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
};
sd0_ds: sd0-ds {
samsung,pins = "gpr0-2";
- samsung,pin-function = <2>;
- samsung,pin-pud = <1>;
- samsung,pin-drv = <4>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
};
sd0_qrdy: sd0-qrdy {
samsung,pins = "gpr0-3";
- samsung,pin-function = <2>;
- samsung,pin-pud = <1>;
- samsung,pin-drv = <4>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
};
sd0_bus1: sd0-bus-width1 {
samsung,pins = "gpr1-0";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <4>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
};
sd0_bus4: sd0-bus-width4 {
samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <4>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
};
sd0_bus8: sd0-bus-width8 {
samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <4>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
};
sd1_clk: sd1-clk {
samsung,pins = "gpr2-0";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <2>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
};
sd1_cmd: sd1-cmd {
samsung,pins = "gpr2-1";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <2>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
};
sd1_ds: sd1-ds {
samsung,pins = "gpr2-2";
- samsung,pin-function = <2>;
- samsung,pin-pud = <1>;
- samsung,pin-drv = <6>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV4>;
};
sd1_qrdy: sd1-qrdy {
samsung,pins = "gpr2-3";
- samsung,pin-function = <2>;
- samsung,pin-pud = <1>;
- samsung,pin-drv = <6>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV4>;
};
sd1_int: sd1-int {
samsung,pins = "gpr2-4";
- samsung,pin-function = <2>;
- samsung,pin-pud = <1>;
- samsung,pin-drv = <6>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV4>;
};
sd1_bus1: sd1-bus-width1 {
samsung,pins = "gpr3-0";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <2>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
};
sd1_bus4: sd1-bus-width4 {
samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <2>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
};
sd1_bus8: sd1-bus-width8 {
samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <2>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
};
};
@@ -682,22 +684,22 @@
spi5_bus: spi5-bus {
samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
ufs_refclk_out: ufs-refclk-out {
samsung,pins = "gpg2-4";
- samsung,pin-function = <2>;
- samsung,pin-pud = <0>;
- samsung,pin-drv = <2>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
};
ufs_rst_n: ufs-rst-n {
samsung,pins = "gph1-5";
- samsung,pin-function = <2>;
- samsung,pin-pud = <3>;
- samsung,pin-drv = <0>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
};
--
2.7.4
^ permalink raw reply related
* Re: [PATCH] arm64: dts: exynos: Remove address node from usb parent node
From: pankaj.dubey @ 2017-01-20 4:23 UTC (permalink / raw)
To: Javier Martinez Canillas, Chanwoo Choi, devicetree, linux-kernel,
linux-samsung-soc
Cc: robh+dt, krzk, kgene
In-Reply-To: <7280351b-d26a-accb-b442-fc1eb056c8d6@osg.samsung.com>
Hi Javier,
On Wednesday 18 January 2017 09:06 PM, Javier Martinez Canillas wrote:
> Hello,
>
> On 01/18/2017 04:04 AM, Chanwoo Choi wrote:
>> Hi Pankaj,
>>
>> This issue already posted by Javier Martinez Canillas[1].
>> Maybe, he will post v2.
>>
>
> That's correct, I didn't post a v2 since I was waiting for feedback
> from the DT maintainers on patches 1/2 and 2/2 from the same series:
>
> https://www.spinics.net/lists/arm-kernel/msg553286.html
>
> But I'll re-spin just this patch since the changes are independent.
>
I didn't noticed this earlier. In this case my patch [1] can be ignored.
[1]: https://patchwork.kernel.org/patch/9522645/
Thanks,
Pankaj Dubey
> Best regards,
>
^ permalink raw reply
* [PATCH 1/2] devicetree: add documentation for MAX30102 oximeter
From: Matt Ranostay @ 2017-01-20 5:40 UTC (permalink / raw)
To: jic23-DgEjT+Ai2ygdnm+yROfE0A
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA, Matt Ranostay,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170120054100.902-1-matt-sk+viVC6FLCDq+mSdOJa79kegs52MxvZ@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Matt Ranostay <matt-sk+viVC6FLCDq+mSdOJa79kegs52MxvZ@public.gmane.org>
---
.../devicetree/bindings/iio/health/max30102.txt | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/health/max30102.txt
diff --git a/Documentation/devicetree/bindings/iio/health/max30102.txt b/Documentation/devicetree/bindings/iio/health/max30102.txt
new file mode 100644
index 000000000000..c93d1bb25597
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/health/max30102.txt
@@ -0,0 +1,30 @@
+Maxim MAX30102 heart rate and pulse oximeter sensor
+
+* https://datasheets.maximintegrated.com/en/ds/MAX30102.pdf
+
+Required properties:
+ - compatible: must be "maxim,max30102"
+ - reg: the I2C address of the sensor
+ - interrupt-parent: should be the phandle for the interrupt controller
+ - interrupts: the sole interrupt generated by the device
+
+ Refer to interrupt-controller/interrupts.txt for generic
+ interrupt client node bindings.
+
+Optional properties:
+ - maxim,red-led-current-microamp: configuration for RED LED current
+ - maxim,ir-led-current-microamp: configuration for IR LED current
+
+ Note that each step is approximately 200 microamps, ranging from 0 uA to
+ 50800 uA.
+
+Example:
+
+max30100@57 {
+ compatible = "maxim,max30102";
+ reg = <57>;
+ maxim,red-led-current-microamp = <7000>;
+ maxim,ir-led-current-microamp = <7000>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <16 2>;
+};
--
2.10.2
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH v2 3/3] watchdog: zx2967: add watchdog controller driver for ZTE's zx2967 family
From: Shawn Guo @ 2017-01-20 6:08 UTC (permalink / raw)
To: Baoyou Xie
Cc: jun.nie-QSEj5FYQhm4dnm+yROfE0A, wim-IQzOog9fTRqzQB+pC5nmwQ,
linux-0h96xk9xTtrk1uMJSBkQmQ, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
xie.baoyou-Th6q7B73Y6EnDS1+zs4M5A,
chen.chaokai-Th6q7B73Y6EnDS1+zs4M5A,
wang.qiang01-Th6q7B73Y6EnDS1+zs4M5A
In-Reply-To: <1484791192-31674-3-git-send-email-baoyou.xie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Thu, Jan 19, 2017 at 09:59:52AM +0800, Baoyou Xie wrote:
> This patch adds watchdog controller driver for ZTE's zx2967 family.
>
> Signed-off-by: Baoyou Xie <baoyou.xie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> drivers/watchdog/Kconfig | 10 ++
> drivers/watchdog/Makefile | 1 +
> drivers/watchdog/zx2967_wdt.c | 383 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 394 insertions(+)
> create mode 100644 drivers/watchdog/zx2967_wdt.c
>
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index acb00b5..05093a2 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -714,6 +714,16 @@ config ASPEED_WATCHDOG
> To compile this driver as a module, choose M here: the
> module will be called aspeed_wdt.
>
> +config ZX2967_WATCHDOG
> + tristate "ZTE zx2967 SoCs watchdog support"
> + depends on ARCH_ZX
> + select WATCHDOG_CORE
> + help
> + Say Y here to include support for the watchdog timer
> + in ZTE zx2967 SoCs.
> + To compile this driver as a module, choose M here: the
> + module will be called zx2967_wdt.
> +
> # AVR32 Architecture
>
> config AT32AP700X_WDT
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index 0c3d35e..bf2d296 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -82,6 +82,7 @@ obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o
> obj-$(CONFIG_ATLAS7_WATCHDOG) += atlas7_wdt.o
> obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
> obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
> +obj-$(CONFIG_ZX2967_WATCHDOG) += zx2967_wdt.o
>
> # AVR32 Architecture
> obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
> diff --git a/drivers/watchdog/zx2967_wdt.c b/drivers/watchdog/zx2967_wdt.c
> new file mode 100644
> index 0000000..35eaecd
> --- /dev/null
> +++ b/drivers/watchdog/zx2967_wdt.c
> @@ -0,0 +1,383 @@
> +/*
> + * watchdog driver for ZTE's zx2967 family
> + *
> + * Copyright (C) 2017 ZTE Ltd.
> + *
> + * Author: Baoyou Xie <baoyou.xie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> + *
> + * License terms: GNU General Public License (GPL) version 2
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/reboot.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/watchdog.h>
> +
> +#define ZX2967_WDT_CFG_REG 0x4
> +#define ZX2967_WDT_LOAD_REG 0x8
> +#define ZX2967_WDT_REFRESH_REG 0x18
> +#define ZX2967_WDT_START_REG 0x1c
> +
> +#define ZX2967_WDT_REFRESH_MASK 0x3f
> +
> +#define ZX2967_WDT_CFG_DIV(n) ((((n) & 0xff) - 1) << 8)
> +#define ZX2967_WDT_START_EN 0x1
> +
> +#define ZX2967_WDT_WRITEKEY 0x12340000
> +
> +#define ZX2967_WDT_DIV_DEFAULT 16
> +#define ZX2967_WDT_DEFAULT_TIMEOUT 32
> +#define ZX2967_WDT_MIN_TIMEOUT 1
> +#define ZX2967_WDT_MAX_TIMEOUT 500
> +#define ZX2967_WDT_MAX_COUNT 0xffff
> +
> +#define ZX2967_WDT_FLAG_REBOOT_MON (1 << 0)
> +
> +#define ZX2967_RESET_MASK_REG 0xb0
> +
> +struct zx2967_wdt {
> + struct device *dev;
> + struct clk *clock;
> + void __iomem *reg_base;
> + unsigned int conf;
> + unsigned int load;
> + unsigned int flags;
> + struct watchdog_device wdt_device;
> + struct notifier_block restart_handler;
> + struct notifier_block reboot_handler;
> +};
> +
> +#define zx2967_wdt_read_reg(r) readl_relaxed(r)
> +
> +static inline void
> +zx2967_wdt_write_reg(u32 val, void __iomem *addr)
> +{
> + writel_relaxed(val | ZX2967_WDT_WRITEKEY, addr);
> +}
static inline u32 zx2967_wdt_readl(struct zx2967_wdt *wdt, u16 reg)
{
return readl_relaxed(wdt->reg_base + reg);
}
static inline void zx2967_wdt_writel(struct zx2967_wdt *wdt, u16 reg, u32 val)
{
writel_relaxed(val | ZX2967_WDT_WRITEKEY, wdt->reg_base + reg);
}
This is what I would suggest to make the caller a bit easier. Anyway,
it's just a suggestion, not a strong opinion.
> +
> +static void zx2967_wdt_refresh(struct zx2967_wdt *wdt)
> +{
> + u32 val;
> +
> + val = zx2967_wdt_read_reg(wdt->reg_base + ZX2967_WDT_REFRESH_REG);
> + val ^= ZX2967_WDT_REFRESH_MASK;
> + zx2967_wdt_write_reg(val, wdt->reg_base + ZX2967_WDT_REFRESH_REG);
> +}
> +
> +static unsigned int
> +__zx2967_wdt_set_timeout(struct zx2967_wdt *wdt, unsigned int timeout)
> +{
> + unsigned int freq = clk_get_rate(wdt->clock);
> + unsigned int divisor = ZX2967_WDT_DIV_DEFAULT;
> + unsigned int count;
> +
> + count = timeout * freq;
> + if (count > divisor * ZX2967_WDT_MAX_COUNT)
> + divisor = DIV_ROUND_UP(count, ZX2967_WDT_MAX_COUNT);
> + count = DIV_ROUND_UP(count, divisor);
> + zx2967_wdt_write_reg(ZX2967_WDT_CFG_DIV(divisor),
> + wdt->reg_base + ZX2967_WDT_CFG_REG);
> + zx2967_wdt_write_reg(count, wdt->reg_base + ZX2967_WDT_LOAD_REG);
> + zx2967_wdt_refresh(wdt);
> + wdt->load = count;
> +
> + return (count * divisor) / freq;
> +}
> +
> +static int zx2967_wdt_set_timeout(struct watchdog_device *wdd,
> + unsigned int timeout)
> +{
> + struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
> +
> + if (watchdog_timeout_invalid(&wdt->wdt_device, timeout)) {
> + dev_err(wdt->dev, "timeout %d is invalid\n", timeout);
> + return -EINVAL;
> + }
> +
> + wdd->timeout = __zx2967_wdt_set_timeout(wdt, timeout);
> +
> + return 0;
> +}
> +
> +static void __zx2967_wdt_start(struct zx2967_wdt *wdt)
> +{
> + u32 val;
> +
> + val = zx2967_wdt_read_reg(wdt->reg_base + ZX2967_WDT_START_REG);
> + val |= ZX2967_WDT_START_EN;
> + zx2967_wdt_write_reg(val, wdt->reg_base + ZX2967_WDT_START_REG);
> +}
> +
> +static void __zx2967_wdt_stop(struct zx2967_wdt *wdt)
> +{
> + u32 val;
> +
> + val = zx2967_wdt_read_reg(wdt->reg_base + ZX2967_WDT_START_REG);
> + val &= ~ZX2967_WDT_START_EN;
> + zx2967_wdt_write_reg(val, wdt->reg_base + ZX2967_WDT_START_REG);
> +}
> +
> +static int zx2967_wdt_start(struct watchdog_device *wdd)
> +{
> + struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
> +
> + __zx2967_wdt_stop(wdt);
> + zx2967_wdt_set_timeout(wdd, wdd->timeout);
> + __zx2967_wdt_start(wdt);
> +
> + return 0;
> +}
> +
> +static int zx2967_wdt_stop(struct watchdog_device *wdd)
> +{
> + struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
> +
> + __zx2967_wdt_stop(wdt);
> +
> + return 0;
> +}
> +
> +static int zx2967_wdt_keepalive(struct watchdog_device *wdd)
> +{
> + struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
> +
> + zx2967_wdt_refresh(wdt);
> +
> + return 0;
> +}
> +
> +#define ZX2967_WDT_OPTIONS \
> + (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
> +static const struct watchdog_info zx2967_wdt_ident = {
> + .options = ZX2967_WDT_OPTIONS,
> + .firmware_version = 0,
> + .identity = "zx2967 watchdog",
> +};
> +
> +static struct watchdog_ops zx2967_wdt_ops = {
> + .owner = THIS_MODULE,
> + .start = zx2967_wdt_start,
> + .stop = zx2967_wdt_stop,
> + .ping = zx2967_wdt_keepalive,
> + .set_timeout = zx2967_wdt_set_timeout,
> +};
> +
> +static void zx2967_wdt_fix_sysdown(struct zx2967_wdt *wdt)
> +{
> + __zx2967_wdt_stop(wdt);
> + __zx2967_wdt_set_timeout(wdt, 15);
> + __zx2967_wdt_start(wdt);
> +}
> +
> +static int zx2967_wdt_notify_sys(struct notifier_block *this,
> + unsigned long code, void *unused)
> +{
> + struct zx2967_wdt *wdt = container_of(this, struct zx2967_wdt,
> + reboot_handler);
> +
> + wdt->flags |= ZX2967_WDT_FLAG_REBOOT_MON;
> + switch (code) {
> + case SYS_HALT:
> + case SYS_POWER_OFF:
> + case SYS_RESTART:
> + zx2967_wdt_fix_sysdown(wdt);
> + break;
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static int zx2967_wdt_restart(struct notifier_block *this,
> + unsigned long mode, void *cmd)
> +{
> + struct zx2967_wdt *wdt;
> +
> + wdt = container_of(this, struct zx2967_wdt, restart_handler);
> +
> + zx2967_wdt_stop(&wdt->wdt_device);
> +
> + zx2967_wdt_write_reg(0x80, wdt->reg_base + ZX2967_WDT_LOAD_REG);
> + zx2967_wdt_refresh(wdt);
> + zx2967_wdt_write_reg(ZX2967_WDT_START_EN,
> + wdt->reg_base + ZX2967_WDT_START_REG);
> +
> + zx2967_wdt_start(&wdt->wdt_device);
> + /* wait for reset*/
> + mdelay(500);
> +
> + return NOTIFY_DONE;
> +}
> +
> +static void zx2967_wdt_reset_sysctrl(struct device *dev)
> +{
> + int ret;
> + struct device_node *np = NULL;
> + void __iomem *regmap;
> + unsigned int val, mask, config;
> + struct of_phandle_args out_args;
> +
> + ret = of_parse_phandle_with_fixed_args(dev->of_node,
> + "wdt-reset-sysctrl", 2, 0, &out_args);
> + if (ret) {
> + dev_info(dev, "have no wdt-reset-sysctrl node");
wdt-reset-sysctrl is not a node but a property. Also, the call can fail
on other reasons, e.g. the arguments are not two. So I suggest the
message like "failed to parse wdt-reset-sysctrl".
> + return;
> + }
> + config = out_args.args[0];
> + mask = out_args.args[1];
> +
> + regmap = syscon_node_to_regmap(out_args.np);
> + if (IS_ERR(regmap))
> + goto out;
> +
> + ret = regmap_read(regmap, ZX2967_RESET_MASK_REG, &val);
I think this register offset can also be an argument of phandle in
device tree.
> +
> + val &= ~mask;
> + val |= config;
> + regmap_write(regmap, ZX2967_RESET_MASK_REG, val);
regmap_update_bits() can be used.
> +out:
> + of_node_put(np);
> +}
> +
> +static int zx2967_wdt_probe(struct platform_device *pdev)
> +{
> + struct device *dev;
> + struct zx2967_wdt *wdt;
> + struct resource *base;
> + int err, ret = 0;
> + unsigned int rate;
> +
> + struct reset_control *rstc;
> +
> + dev = &pdev->dev;
> +
> + wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
> + if (!wdt)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, wdt);
> +
> + wdt->dev = dev;
> + wdt->wdt_device.info = &zx2967_wdt_ident;
> + wdt->wdt_device.ops = &zx2967_wdt_ops;
> + wdt->wdt_device.timeout = ZX2967_WDT_DEFAULT_TIMEOUT;
> + wdt->wdt_device.max_timeout = ZX2967_WDT_MAX_TIMEOUT;
> + wdt->wdt_device.min_timeout = ZX2967_WDT_MIN_TIMEOUT;
> + wdt->wdt_device.parent = &pdev->dev;
> +
> + base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + wdt->reg_base = devm_ioremap_resource(dev, base);
> + if (IS_ERR(wdt->reg_base)) {
> + dev_err(dev, "ioremap failed\n");
> + return PTR_ERR(wdt->reg_base);
> + }
> +
> + zx2967_wdt_reset_sysctrl(dev);
> +
> + wdt->reboot_handler.notifier_call = zx2967_wdt_notify_sys;
> + ret = register_reboot_notifier(&wdt->reboot_handler);
> + wdt->clock = devm_clk_get(dev, "wdtclk");
devm_clk_get(dev, NULL), so that clock-names can be saved from DT.
> + if (IS_ERR(wdt->clock)) {
> + dev_err(dev, "failed to find watchdog clock source\n");
> + return PTR_ERR(wdt->clock);
> + }
> + ret = clk_prepare_enable(wdt->clock);
> + if (ret < 0) {
> + dev_err(dev, "failed to enable clock\n");
> + return ret;
> + }
> +
> + rate = clk_get_rate(wdt->clock);
> + if (rate == 24000000)
> + clk_set_rate(wdt->clock, 32768);
What's the logic behind this? We need to set the frequency to 32768
only when it's 24000000? Any other frequency will just work?
> +
> + rstc = devm_reset_control_get(dev, "wdtrst");
devm_reset_control_get(dev, NULL), so that reset-names can be saved.
> + if (!rstc) {
> + dev_err(dev, "rstc get failed");
Will it still work if "reset" property is missing? If yes, the property
should be documented as optional, not required. If no, we should stop
probing and return error right here.
> + } else {
> + reset_control_assert(rstc);
> + mdelay(10);
> + reset_control_deassert(rstc);
> + }
> +
> + watchdog_set_drvdata(&wdt->wdt_device, wdt);
> +
> + watchdog_init_timeout(&wdt->wdt_device,
> + ZX2967_WDT_DEFAULT_TIMEOUT, dev);
> + watchdog_set_nowayout(&wdt->wdt_device, WATCHDOG_NOWAYOUT);
> +
> + zx2967_wdt_stop(&wdt->wdt_device);
> +
> + err = watchdog_register_device(&wdt->wdt_device);
Why not use 'ret' directly?
Shawn
> + if (unlikely(err)) {
> + ret = err;
> + goto fail_register;
> + }
> +
> + wdt->restart_handler.notifier_call = zx2967_wdt_restart;
> + wdt->restart_handler.priority = 128;
> + ret = register_restart_handler(&wdt->restart_handler);
> + if (ret) {
> + dev_err(dev, "cannot register restart handler, %d\n", ret);
> + goto fail_restart;
> + }
> +
> + dev_info(dev, "watchdog enabled (timeout=%d sec, nowayout=%d)",
> + wdt->wdt_device.timeout, WATCHDOG_NOWAYOUT);
> +
> + return 0;
> +
> +fail_restart:
> + watchdog_unregister_device(&wdt->wdt_device);
> +fail_register:
> + clk_disable_unprepare(wdt->clock);
> + return ret;
> +}
> +
> +static int zx2967_wdt_remove(struct platform_device *pdev)
> +{
> + struct zx2967_wdt *wdt = platform_get_drvdata(pdev);
> +
> + unregister_restart_handler(&wdt->restart_handler);
> + watchdog_unregister_device(&wdt->wdt_device);
> + clk_disable_unprepare(wdt->clock);
> +
> + return 0;
> +}
> +
> +static void zx2967_wdt_shutdown(struct platform_device *pdev)
> +{
> + struct zx2967_wdt *wdt = platform_get_drvdata(pdev);
> +
> + if (!(wdt->flags & ZX2967_WDT_FLAG_REBOOT_MON))
> + zx2967_wdt_stop(&wdt->wdt_device);
> +}
> +
> +static const struct of_device_id zx2967_wdt_match[] = {
> + { .compatible = "zte,zx296718-wdt", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, zx2967_wdt_match);
> +
> +static struct platform_driver zx2967_wdt_driver = {
> + .probe = zx2967_wdt_probe,
> + .remove = zx2967_wdt_remove,
> + .shutdown = zx2967_wdt_shutdown,
> + .driver = {
> + .name = "zx2967-wdt",
> + .of_match_table = of_match_ptr(zx2967_wdt_match),
> + },
> +};
> +module_platform_driver(zx2967_wdt_driver);
> +
> +MODULE_AUTHOR("Baoyou Xie <baoyou.xie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>");
> +MODULE_DESCRIPTION("ZTE zx2967 Watchdog Device Driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.7.4
>
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^ permalink raw reply
* Re: [PATCH 2/2] ARM: dts: rockchip: add dts for RK3288-Tinker board
From: Eddie Cai @ 2017-01-20 6:42 UTC (permalink / raw)
To: Heiko Stuebner
Cc: robh+dt, mark.rutland, linux, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, Eddie Cai
In-Reply-To: <40159140.kOHBSj8v8b@phil>
[-- Attachment #1: Type: text/plain, Size: 2473 bytes --]
2017-01-19 17:58 GMT+08:00 Heiko Stuebner <heiko@sntech.de>:
> Hi Eddie,
>
> Am Donnerstag, 19. Januar 2017, 10:11:59 CET schrieb Eddie Cai:
> > This patch add basic support for RK3288-Tinker board. We can boot in to
> > rootfs with this patch.
> >
> > Signed-off-by: Eddie Cai <eddie.cai@rock-chips.com>
>
> looks good in general, just some small question down below.
>
> [...]
>
> > + /*
> > + * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes
> from
> > + * vcc_io directly. Those boards won't be able to power cycle SD
> cards
> > + * but it shouldn't hurt to toggle this pin there anyway.
> > + */
>
> just to clarify, later board will have that pin connected, right?
>
Copy from rk3288-evb.dtsi. forgot to delete it. I will remove it next
version
>
> > + vcc_sd: sdmmc-regulator {
> > + compatible = "regulator-fixed";
> > + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&sdmmc_pwr>;
> > + regulator-name = "vcc_sd";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + startup-delay-us = <100000>;
> > + vin-supply = <&vcc_io>;
> > + };
> > +};
>
> [...]
>
> > +&hdmi {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #sound-dai-cells = <0>;
> > + ddc-i2c-bus = <&i2c5>;
> > + status = "okay";
> > + /* Don't use vopl for HDMI */
> > + ports {
> > + hdmi_in: port {
> > + /delete-node/ endpoint@1;
> > + };
>
> what is the reason for this? You enable both VOPs below and the linux
> display
> subsystem should be able to select an appropriate VOP for output just fine
> on
> its own. So there should be no reason for capping the hdmi's connection to
> one
> of the vops.
>
The VOP big support 4k display. is designed for HDMI 4K display. VOP
little is for other display(eDP, LVDS, Mipi etc)
>
> > + };
> > +};
>
> [...]
>
> > +&usb_host0_ehci {
> > + no-relinquish-port;
>
> This seems like an unused/undocumented property
>
I will remove it next version
>
> > + status = "okay";
> > +};
>
> [...]
>
> > +&vopl {
> > + status = "okay";
> > + /* Don't use vopl for HDMI */
> > + vopl_out: port {
> > + /delete-node/ endpoint@0;
> > + };
>
> see comment at the hdmi node
>
> > +};
>
>
> Thanks
> Heiko
>
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^ permalink raw reply
* [PATCH 1/3 v2] ahci: qoriq: added a condition to enable dma coherence
From: yuantian.tang @ 2017-01-20 6:59 UTC (permalink / raw)
To: tj
Cc: mathieu.poirier, robin.murphy, robh+dt, mark.rutland, linux-ide,
devicetree, linux-kernel, linux-arm-kernel, Tang Yuantian,
Tang Yuantian
From: Tang Yuantian <Yuantian.Tang@nxp.com>
Enable DMA coherence in SATA controller on condition that
dma-coherent property exists in sata node in DTS.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
---
v2:
- use of_dma_is_coherent() instead of open-coding.
drivers/ata/ahci_qoriq.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 9884c8c..01ef662 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -59,6 +59,7 @@ struct ahci_qoriq_priv {
struct ccsr_ahci *reg_base;
enum ahci_qoriq_type type;
void __iomem *ecc_addr;
+ bool is_dmacoherent;
};
static const struct of_device_id ahci_qoriq_of_match[] = {
@@ -164,26 +165,31 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- writel(AHCI_PORT_AXICC_CFG, reg_base + LS1021A_AXICC_ADDR);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG,
+ reg_base + LS1021A_AXICC_ADDR);
break;
case AHCI_LS1043A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
case AHCI_LS2080A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
case AHCI_LS1046A:
writel(LS1046A_SATA_ECC_DIS, qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
}
@@ -221,6 +227,7 @@ static int ahci_qoriq_probe(struct platform_device *pdev)
if (IS_ERR(qoriq_priv->ecc_addr))
return PTR_ERR(qoriq_priv->ecc_addr);
}
+ qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
rc = ahci_platform_enable_resources(hpriv);
if (rc)
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 2/3 v2] ahci: qoriq: report error when ecc register address is missing in dts
From: yuantian.tang @ 2017-01-20 6:59 UTC (permalink / raw)
To: tj
Cc: mathieu.poirier, robin.murphy, robh+dt, mark.rutland, linux-ide,
devicetree, linux-kernel, linux-arm-kernel, Tang Yuantian,
Tang Yuantian
In-Reply-To: <1484895576-40379-1-git-send-email-yuantian.tang@nxp.com>
From: Tang Yuantian <Yuantian.Tang@nxp.com>
For ls1021a, and armv8 chasis 2 socs, sata ecc must be disabled.
If ecc register is not found in sata node in dts, report error.
This is a chip erratum described as bellow:
The Read DMA operations get early termination indication from the
controller. This issue is observed as CRC error in the status registers.
The issue is due to address collision at address 0 in the dual port
memory. The read is a dummy read to flush out the header, but due to
collision the controller logs the mbit error reported by the ECC check
logic. This results in the early termination of the Read DMA operation
by the controller. The issue happens to all the interface
speeds(GEN1/2/3) for all the products.
Workaround:
Disable ECC feature on those platforms.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
---
v2:
- refine the title and description
- change reporting warning to reporting error
drivers/ata/ahci_qoriq.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 01ef662..137b1c7 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -46,7 +46,7 @@
#define LS1021A_AXICC_ADDR 0xC0
#define SATA_ECC_DISABLE 0x00020000
-#define LS1046A_SATA_ECC_DIS 0x80000000
+#define ECC_DIS_ARMV8_CH2 0x80000000
enum ahci_qoriq_type {
AHCI_LS1021A,
@@ -158,6 +158,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
switch (qpriv->type) {
case AHCI_LS1021A:
+ if (!qpriv->ecc_addr)
+ return -EINVAL;
writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
@@ -171,6 +173,9 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
break;
case AHCI_LS1043A:
+ if (!qpriv->ecc_addr)
+ return -EINVAL;
+ writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
@@ -185,7 +190,9 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
break;
case AHCI_LS1046A:
- writel(LS1046A_SATA_ECC_DIS, qpriv->ecc_addr);
+ if (!qpriv->ecc_addr)
+ return -EINVAL;
+ writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 3/3 v2] ahci: qoriq: added ls2088a platforms support
From: yuantian.tang @ 2017-01-20 6:59 UTC (permalink / raw)
To: tj
Cc: mathieu.poirier, robin.murphy, robh+dt, mark.rutland, linux-ide,
devicetree, linux-kernel, linux-arm-kernel, Tang Yuantian,
Tang Yuantian
In-Reply-To: <1484895576-40379-1-git-send-email-yuantian.tang@nxp.com>
From: Tang Yuantian <Yuantian.Tang@nxp.com>
Ls2088a is new introduced arm-based soc with sata support with
following features:
1. Complies with the serial ATA 3.0 specification and the AHCI 1.3.1
specification
2. Contains a high-speed descriptor-based DMA controller
3. Supports the following:
a. Speeds of 1.5 Gb/s (first-generation SATA), 3 Gb/s
(second-generation SATA), and 6 Gb/s (third-generation SATA)
b. FIS-based switching
c. Native command queuing (NCQ) commands
d. Port multiplier operation
e. Asynchronous notification
f. SATA BIST mode
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
---
v2:
- no change
drivers/ata/ahci_qoriq.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 137b1c7..85d8332 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -53,6 +53,7 @@ enum ahci_qoriq_type {
AHCI_LS1043A,
AHCI_LS2080A,
AHCI_LS1046A,
+ AHCI_LS2088A,
};
struct ahci_qoriq_priv {
@@ -67,6 +68,7 @@ static const struct of_device_id ahci_qoriq_of_match[] = {
{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
+ { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
@@ -198,6 +200,13 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
+
+ case AHCI_LS2088A:
+ writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
+ writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+ break;
}
return 0;
--
2.1.0.27.g96db324
^ permalink raw reply related
* Re: [PATCH 2/2] ARM: dts: rockchip: add dts for RK3288-Tinker board
From: Eddie Cai @ 2017-01-20 7:07 UTC (permalink / raw)
To: Shawn Lin
Cc: mark.rutland, devicetree, Heiko Stuebner, linux, linux-kernel,
linux-rockchip, robh+dt, Eddie Cai, linux-arm-kernel
In-Reply-To: <c8e937f3-1d0b-ecdc-e1af-5db2339c52ef@rock-chips.com>
2017-01-20 10:29 GMT+08:00 Shawn Lin <shawn.lin@rock-chips.com>:
>
> On 2017/1/19 10:11, Eddie Cai wrote:
>>
>> This patch add basic support for RK3288-Tinker board. We can boot in to rootfs
>> with this patch.
>>
>> Signed-off-by: Eddie Cai <eddie.cai@rock-chips.com>
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/rk3288-tinker.dts | 556 ++++++++++++++++++++++++++++++++++++
>> 2 files changed, 557 insertions(+)
>> create mode 100644 arch/arm/boot/dts/rk3288-tinker.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 7327250..4fc05b7 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -679,6 +679,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>> rk3288-popmetal.dtb \
>> rk3288-r89.dtb \
>> rk3288-rock2-square.dtb \
>> + rk3288-tinker.dtb \
>> rk3288-veyron-brain.dtb \
>> rk3288-veyron-jaq.dtb \
>> rk3288-veyron-jerry.dtb \
>> diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
>> new file mode 100644
>> index 0000000..37cb431
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/rk3288-tinker.dts
>> @@ -0,0 +1,556 @@
>> +/*
>> + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "rk3288.dtsi"
>> +
>> +/ {
>> + model = "Rockchip RK3288 Tinker Board";
>> + compatible = "rockchip,rk3288-tinker", "rockchip,rk3288";
>> +
>> + memory {
>> + reg = <0x0 0x80000000>;
>> + device_type = "memory";
>> + };
>> +
>> + ext_gmac: external-gmac-clock {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <125000000>;
>> + clock-output-names = "ext_gmac";
>> + };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + autorepeat;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pwrbtn>;
>> +
>> + button@0 {
>> + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
>> + linux,code = <116>;
>> + label = "GPIO Key Power";
>> + linux,input-type = <1>;
>> + gpio-key,wakeup = <1>;
>> + debounce-interval = <100>;
>> + };
>> + };
>> +
>> + gpio-leds {
>> + compatible = "gpio-leds";
>> +
>> + pwr-led {
>> + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "default-on";
>> + };
>> +
>> + act-led {
>> + gpios=<&gpio2 3 GPIO_ACTIVE_LOW>;
>> + linux,default-trigger="mmc0";
>> + };
>> + };
>> +
>> + sound {
>> + compatible = "simple-audio-card";
>> + simple-audio-card,format = "i2s";
>> + simple-audio-card,name = "rockchip,tinker-codec";
>> + simple-audio-card,mclk-fs = <512>;
>> + simple-audio-card,cpu {
>> + sound-dai = <&i2s>;
>> + };
>> + simple-audio-card,codec {
>> + sound-dai = <&hdmi>;
>> + };
>> + };
>> +
>> + vcc_sys: vsys-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc_sys";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + /*
>> + * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from
>> + * vcc_io directly. Those boards won't be able to power cycle SD cards
>> + * but it shouldn't hurt to toggle this pin there anyway.
>> + */
>> + vcc_sd: sdmmc-regulator {
>> + compatible = "regulator-fixed";
>> + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&sdmmc_pwr>;
>> + regulator-name = "vcc_sd";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + startup-delay-us = <100000>;
>> + vin-supply = <&vcc_io>;
>> + };
>> +};
>> +
>> +&cpu0 {
>> + cpu0-supply = <&vdd_cpu>;
>> +};
>> +
>> +&gmac {
>> + phy-supply = <&vcc33_lan>;
>> + phy-mode = "rgmii";
>> + clock_in_out = "input";
>> + snps,reset-gpio = <&gpio4 7 0>;
>> + snps,reset-active-low;
>> + snps,reset-delays-us = <0 10000 1000000>;
>> + assigned-clocks = <&cru SCLK_MAC>;
>> + assigned-clock-parents = <&ext_gmac>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&rgmii_pins>;
>> + tx_delay = <0x30>;
>> + rx_delay = <0x10>;
>> + status = "ok";
>> +};
>> +
>> +&hdmi {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + #sound-dai-cells = <0>;
>> + ddc-i2c-bus = <&i2c5>;
>> + status = "okay";
>> + /* Don't use vopl for HDMI */
>> + ports {
>> + hdmi_in: port {
>> + /delete-node/ endpoint@1;
>> + };
>> + };
>> +};
>> +
>> +&i2c0 {
>> + status = "okay";
>> + clock-frequency = <400000>;
>> +
>> + rk808: pmic@1b {
>> + compatible = "rockchip,rk808";
>> + reg = <0x1b>;
>> + interrupt-parent = <&gpio0>;
>> + interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>;
>> + dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
>> + <&gpio0 12 GPIO_ACTIVE_HIGH>;
>> +
>> + rockchip,system-power-controller;
>> + wakeup-source;
>> + #clock-cells = <1>;
>> + clock-output-names = "xin32k", "rk808-clkout2";
>> +
>> + vcc1-supply = <&vcc_sys>;
>> + vcc2-supply = <&vcc_sys>;
>> + vcc3-supply = <&vcc_sys>;
>> + vcc4-supply = <&vcc_sys>;
>> + vcc6-supply = <&vcc_sys>;
>> + vcc7-supply = <&vcc_sys>;
>> + vcc8-supply = <&vcc_18>;
>> + vcc9-supply = <&vcc_io>;
>> + vcc10-supply = <&vcc_io>;
>> + vcc11-supply = <&vcc_sys>;
>> + vcc12-supply = <&vcc_io>;
>> + vddio-supply = <&vcc18_ldo1>;
>> +
>> + regulators {
>> + vdd_cpu: DCDC_REG1 {
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <750000>;
>> + regulator-max-microvolt = <1350000>;
>> + regulator-name = "vdd_arm";
>> + regulator-ramp-delay = <6000>;
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vdd_gpu: DCDC_REG2 {
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <850000>;
>> + regulator-max-microvolt = <1250000>;
>> + regulator-name = "vdd_gpu";
>> + regulator-ramp-delay = <6000>;
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <1000000>;
>> + };
>> + };
>> +
>> + vcc_ddr: DCDC_REG3 {
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-name = "vcc_ddr";
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + };
>> + };
>> +
>> + vcc_io: DCDC_REG4 {
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-name = "vcc_io";
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <3300000>;
>> + };
>> + };
>> +
>> + vcc18_ldo1: LDO_REG1 {
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-name = "vcc18_ldo1";
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <1800000>;
>> + };
>> + };
>> +
>> + vcc33_mipi: LDO_REG2 {
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-name = "vcc33_mipi";
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vdd_10: LDO_REG3 {
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <1000000>;
>> + regulator-max-microvolt = <1000000>;
>> + regulator-name = "vdd_10";
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <1000000>;
>> + };
>> + };
>> +
>> + vcc18_codec: LDO_REG4 {
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-name = "vcc18_codec";
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <1800000>;
>> + };
>> + };
>> +
>> + vccio_sd: LDO_REG5 {
>> + regulator-always-on;
>> + regulator-boot-on;
>
>
>
> are some other io banks or devices powered by
> vccio_sd, so that you mark it as boot-on and always-on?
This board do not have emmc, It use SD card to store firmware image.
So have to always on.
>
>
>
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-name = "vccio_sd";
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <3300000>;
>> + };
>> + };
>> +
>> + vdd10_lcd: LDO_REG6 {
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <1000000>;
>> + regulator-max-microvolt = <1000000>;
>> + regulator-name = "vdd10_lcd";
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <1000000>;
>> + };
>> + };
>> +
>> + vcc_18: LDO_REG7 {
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-name = "vcc_18";
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <1800000>;
>> + };
>> + };
>> +
>> + vcc18_lcd: LDO_REG8 {
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-name = "vcc18_lcd";
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <1800000>;
>> + };
>> + };
>> +
>> + vcc33_sd: SWITCH_REG1 {
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-name = "vcc33_sd";
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + };
>> + };
>> +
>> + vcc33_lan: SWITCH_REG2 {
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-name = "vcc33_lan";
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + };
>> + };
>> + };
>> + };
>> +};
>> +
>> +&i2c2 {
>> + status = "okay";
>> +};
>> +
>> +&i2c5 {
>> + status = "okay";
>> +};
>> +
>> +&i2s {
>> + #sound-dai-cells = <0>;
>> + status = "okay";
>> +};
>> +
>> +&io_domains {
>> + status = "okay";
>> +
>> + sdcard-supply = <&vccio_sd>;
>> +};
>> +
>> +&pinctrl {
>> + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
>> + drive-strength = <8>;
>> + };
>> +
>> + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
>> + bias-pull-up;
>> + drive-strength = <8>;
>> + };
>> +
>> + backlight {
>> + bl_en: bl-en {
>> + rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
>> + };
>> + };
>> +
>> + buttons {
>> + pwrbtn: pwrbtn {
>> + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
>> + };
>> + };
>> +
>> + eth_phy {
>> + eth_phy_pwr: eth-phy-pwr {
>> + rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
>> + };
>> + };
>> +
>> + pmic {
>> + pmic_int: pmic-int {
>> + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO \
>> + &pcfg_pull_up>;
>> + };
>> +
>> + dvs_1: dvs-1 {
>> + rockchip,pins = <RK_GPIO0 11 RK_FUNC_GPIO \
>> + &pcfg_pull_down>;
>> + };
>> +
>> + dvs_2: dvs-2 {
>> + rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO \
>> + &pcfg_pull_down>;
>> + };
>> + };
>> +
>> + sdmmc {
>> + /*
>> + * Default drive strength isn't enough to achieve even
>> + * high-speed mode on EVB board so bump up to 8ma.
>> + */
>> + sdmmc_bus4: sdmmc-bus4 {
>> + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
>> + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
>> + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
>> + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
>> + };
>> +
>> + sdmmc_clk: sdmmc-clk {
>> + rockchip,pins = <6 20 RK_FUNC_1 \
>> + &pcfg_pull_none_drv_8ma>;
>> + };
>> +
>> + sdmmc_cmd: sdmmc-cmd {
>> + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
>> + };
>> +
>> + sdmmc_pwr: sdmmc-pwr {
>> + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
>> + };
>> + };
>> +
>> + usb {
>> + host_vbus_drv: host-vbus-drv {
>> + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
>> + };
>> +
>> + pwr_3g: pwr-3g {
>> + rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
>> + };
>> + };
>> +};
>> +
>> +&pwm0 {
>> + status = "okay";
>> +};
>> +
>> +&saradc {
>> + vref-supply = <&vcc18_ldo1>;
>> + status ="okay";
>> +};
>> +
>> +&sdmmc {
>> + bus-width = <4>;
>> + cap-mmc-highspeed;
>> + cap-sd-highspeed;
>> + card-detect-delay = <200>;
>> + disable-wp; /* wp not hooked up */
>> + num-slots = <1>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
>> + status = "okay";
>> + supports-sd;
>
>
> This is not upstreamed property. We have no-sdio/no-emmc there to
> skip the init sequence.
OK, I will remove it next version
>
>
>> + vmmc-supply = <&vcc_sd>;
>> + vqmmc-supply = <&vccio_sd>;
>> +};
>> +
>> +&tsadc {
>> + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
>> + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
>> + status = "okay";
>> +};
>> +
>> +&uart0 {
>> + status = "okay";
>> +};
>> +
>> +&uart1 {
>> + status = "okay";
>> +};
>> +
>> +&uart2 {
>> + status = "okay";
>> +};
>> +
>> +&uart3 {
>> + status = "okay";
>> +};
>> +
>> +&uart4 {
>> + status = "okay";
>> +};
>> +
>> +&usbphy {
>> + status = "okay";
>> +};
>> +
>> +&usb_host0_ehci {
>> + no-relinquish-port;
>> + status = "okay";
>> +};
>> +
>> +&usb_host1 {
>> + status = "okay";
>> +};
>> +
>> +&usb_otg {
>> + status= "okay";
>> +};
>> +
>> +&vopb {
>> + status = "okay";
>> +};
>> +
>> +&vopb_mmu {
>> + status = "okay";
>> +};
>> +
>> +&vopl {
>> + status = "okay";
>> + /* Don't use vopl for HDMI */
>> + vopl_out: port {
>> + /delete-node/ endpoint@0;
>> + };
>> +};
>> +
>> +&vopl_mmu {
>> + status = "okay";
>> +};
>> +
>> +&wdt {
>> + status = "okay";
>> +};
>> +
>>
>
>
> --
> Best Regards
> Shawn Lin
>
^ permalink raw reply
* Re: [PATCH 2/2] ARM: dts: rockchip: add dts for RK3288-Tinker board
From: Eddie Cai @ 2017-01-20 7:10 UTC (permalink / raw)
To: Heiko Stuebner
Cc: robh+dt, mark.rutland, linux, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, Eddie Cai
In-Reply-To: <40159140.kOHBSj8v8b@phil>
2017-01-19 17:58 GMT+08:00 Heiko Stuebner <heiko@sntech.de>:
> Hi Eddie,
>
> Am Donnerstag, 19. Januar 2017, 10:11:59 CET schrieb Eddie Cai:
>> This patch add basic support for RK3288-Tinker board. We can boot in to
>> rootfs with this patch.
>>
>> Signed-off-by: Eddie Cai <eddie.cai@rock-chips.com>
>
> looks good in general, just some small question down below.
>
> [...]
>
>> + /*
>> + * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from
>> + * vcc_io directly. Those boards won't be able to power cycle SD cards
>> + * but it shouldn't hurt to toggle this pin there anyway.
>> + */
>
> just to clarify, later board will have that pin connected, right?
Copy from rk3288-evb.dtsi. forgot to delete it. I will remove it in next version
>
>> + vcc_sd: sdmmc-regulator {
>> + compatible = "regulator-fixed";
>> + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&sdmmc_pwr>;
>> + regulator-name = "vcc_sd";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + startup-delay-us = <100000>;
>> + vin-supply = <&vcc_io>;
>> + };
>> +};
>
> [...]
>
>> +&hdmi {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + #sound-dai-cells = <0>;
>> + ddc-i2c-bus = <&i2c5>;
>> + status = "okay";
>> + /* Don't use vopl for HDMI */
>> + ports {
>> + hdmi_in: port {
>> + /delete-node/ endpoint@1;
>> + };
>
> what is the reason for this? You enable both VOPs below and the linux display
> subsystem should be able to select an appropriate VOP for output just fine on
> its own. So there should be no reason for capping the hdmi's connection to one
> of the vops.
The VOP big support 4k display. is designed for HDMI 4K display. VOP
little is for other display(eDP, LVDS, Mipi etc)
>
>> + };
>> +};
>
> [...]
>
>> +&usb_host0_ehci {
>> + no-relinquish-port;
>
> This seems like an unused/undocumented property
I will remove it in next version
>
>> + status = "okay";
>> +};
>
> [...]
>
>> +&vopl {
>> + status = "okay";
>> + /* Don't use vopl for HDMI */
>> + vopl_out: port {
>> + /delete-node/ endpoint@0;
>> + };
>
> see comment at the hdmi node
>
>> +};
>
>
> Thanks
> Heiko
^ permalink raw reply
* Re: [PATCH v3 2/2] mmc: pwrseq: add support for Marvell SD8787 chip
From: Ulf Hansson @ 2017-01-20 7:31 UTC (permalink / raw)
To: Shawn Lin
Cc: Matt Ranostay, linux-wireless@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org,
devicetree@vger.kernel.org, Tony Lindgren
In-Reply-To: <68de9e67-a7f2-2cc4-26e6-0d3c0afd95db@rock-chips.com>
On 20 January 2017 at 03:42, Shawn Lin <shawn.lin@rock-chips.com> wrote:
> On 2017/1/19 22:13, Ulf Hansson wrote:
>>
>> +Shawn
>>
>> On 13 January 2017 at 06:29, Matt Ranostay <matt@ranostay.consulting>
>> wrote:
>>>
>>> Allow power sequencing for the Marvell SD8787 Wifi/BT chip.
>>> This can be abstracted to other chipsets if needed in the future.
>>>
>>> Cc: Tony Lindgren <tony@atomide.com>
>>> Cc: Ulf Hansson <ulf.hansson@linaro.org>
>>> Signed-off-by: Matt Ranostay <matt@ranostay.consulting>
>>> ---
>>> drivers/mmc/core/Kconfig | 10 ++++
>>> drivers/mmc/core/Makefile | 1 +
>>> drivers/mmc/core/pwrseq_sd8787.c | 117
>>> +++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 128 insertions(+)
>>> create mode 100644 drivers/mmc/core/pwrseq_sd8787.c
>>>
>>> diff --git a/drivers/mmc/core/Kconfig b/drivers/mmc/core/Kconfig
>>> index cdfa8520a4b1..fc1ecdaaa9ca 100644
>>> --- a/drivers/mmc/core/Kconfig
>>> +++ b/drivers/mmc/core/Kconfig
>>> @@ -12,6 +12,16 @@ config PWRSEQ_EMMC
>>> This driver can also be built as a module. If so, the module
>>> will be called pwrseq_emmc.
>>>
>>> +config PWRSEQ_SD8787
>>> + tristate "HW reset support for SD8787 BT + Wifi module"
>>> + depends on OF && (MWIFIEX || BT_MRVL_SDIO)
>>> + help
>>> + This selects hardware reset support for the SD8787 BT + Wifi
>>> + module. By default this option is set to n.
>>> +
>>> + This driver can also be built as a module. If so, the module
>>> + will be called pwrseq_sd8787.
>>> +
>>> config PWRSEQ_SIMPLE
>>> tristate "Simple HW reset support for MMC"
>>> default y
>>> diff --git a/drivers/mmc/core/Makefile b/drivers/mmc/core/Makefile
>>> index b2a257dc644f..0f81464fa824 100644
>>> --- a/drivers/mmc/core/Makefile
>>> +++ b/drivers/mmc/core/Makefile
>>> @@ -10,6 +10,7 @@ mmc_core-y := core.o bus.o host.o \
>>> quirks.o slot-gpio.o
>>> mmc_core-$(CONFIG_OF) += pwrseq.o
>>> obj-$(CONFIG_PWRSEQ_SIMPLE) += pwrseq_simple.o
>>> +obj-$(CONFIG_PWRSEQ_SD8787) += pwrseq_sd8787.o
>>> obj-$(CONFIG_PWRSEQ_EMMC) += pwrseq_emmc.o
>>> mmc_core-$(CONFIG_DEBUG_FS) += debugfs.o
>>> obj-$(CONFIG_MMC_BLOCK) += mmc_block.o
>>> diff --git a/drivers/mmc/core/pwrseq_sd8787.c
>>> b/drivers/mmc/core/pwrseq_sd8787.c
>>> new file mode 100644
>>> index 000000000000..f4080fe6439e
>>> --- /dev/null
>>> +++ b/drivers/mmc/core/pwrseq_sd8787.c
>>> @@ -0,0 +1,117 @@
>>> +/*
>>> + * pwrseq_sd8787.c - power sequence support for Marvell SD8787 BT + Wifi
>>> chip
>>> + *
>>> + * Copyright (C) 2016 Matt Ranostay <matt@ranostay.consulting>
>>> + *
>>> + * Based on the original work pwrseq_simple.c
>>> + * Copyright (C) 2014 Linaro Ltd
>>> + * Author: Ulf Hansson <ulf.hansson@linaro.org>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License as published by
>>> + * the Free Software Foundation; either version 2 of the License, or
>>> + * (at your option) any later version.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + */
>>> +
>>> +#include <linux/delay.h>
>>> +#include <linux/init.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/module.h>
>>> +#include <linux/slab.h>
>>> +#include <linux/device.h>
>>> +#include <linux/err.h>
>>> +#include <linux/gpio/consumer.h>
>>> +
>>> +#include <linux/mmc/host.h>
>>> +
>>> +#include "pwrseq.h"
>>> +
>>> +struct mmc_pwrseq_sd8787 {
>>> + struct mmc_pwrseq pwrseq;
>>> + struct gpio_desc *reset_gpio;
>>> + struct gpio_desc *pwrdn_gpio;
>>> +};
>>> +
>>> +#define to_pwrseq_sd8787(p) container_of(p, struct mmc_pwrseq_sd8787,
>>> pwrseq)
>>> +
>>> +static void mmc_pwrseq_sd8787_pre_power_on(struct mmc_host *host)
>>> +{
>>> + struct mmc_pwrseq_sd8787 *pwrseq =
>>> to_pwrseq_sd8787(host->pwrseq);
>>> +
>>> + gpiod_set_value_cansleep(pwrseq->reset_gpio, 1);
>>> +
>>> + msleep(300);
>>> + gpiod_set_value_cansleep(pwrseq->pwrdn_gpio, 1);
>>> +}
>>> +
>>> +static void mmc_pwrseq_sd8787_power_off(struct mmc_host *host)
>>> +{
>>> + struct mmc_pwrseq_sd8787 *pwrseq =
>>> to_pwrseq_sd8787(host->pwrseq);
>>> +
>>> + gpiod_set_value_cansleep(pwrseq->pwrdn_gpio, 0);
>>> + gpiod_set_value_cansleep(pwrseq->reset_gpio, 0);
>>> +}
>>> +
>>> +static const struct mmc_pwrseq_ops mmc_pwrseq_sd8787_ops = {
>>> + .pre_power_on = mmc_pwrseq_sd8787_pre_power_on,
>>> + .power_off = mmc_pwrseq_sd8787_power_off,
>>> +};
>>> +
>>> +static const struct of_device_id mmc_pwrseq_sd8787_of_match[] = {
>>> + { .compatible = "mmc-pwrseq-sd8787",},
>>> + {/* sentinel */},
>>> +};
>>> +MODULE_DEVICE_TABLE(of, mmc_pwrseq_sd8787_of_match);
>>> +
>>> +static int mmc_pwrseq_sd8787_probe(struct platform_device *pdev)
>>> +{
>>> + struct mmc_pwrseq_sd8787 *pwrseq;
>>> + struct device *dev = &pdev->dev;
>>> +
>>> + pwrseq = devm_kzalloc(dev, sizeof(*pwrseq), GFP_KERNEL);
>>> + if (!pwrseq)
>>> + return -ENOMEM;
>>> +
>>> + pwrseq->pwrdn_gpio = devm_gpiod_get(dev, "pwrdn", GPIOD_OUT_LOW);
>>> + if (IS_ERR(pwrseq->pwrdn_gpio))
>>> + return PTR_ERR(pwrseq->pwrdn_gpio);
>>> +
>>> + pwrseq->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
>>> + if (IS_ERR(pwrseq->reset_gpio))
>>> + return PTR_ERR(pwrseq->reset_gpio);
>>> +
>>> + pwrseq->pwrseq.dev = dev;
>>> + pwrseq->pwrseq.ops = &mmc_pwrseq_sd8787_ops;
>>> + pwrseq->pwrseq.owner = THIS_MODULE;
>>> + platform_set_drvdata(pdev, pwrseq);
>>> +
>>> + return mmc_pwrseq_register(&pwrseq->pwrseq);
>>> +}
>>> +
>>> +static int mmc_pwrseq_sd8787_remove(struct platform_device *pdev)
>>> +{
>>> + struct mmc_pwrseq_sd8787 *pwrseq = platform_get_drvdata(pdev);
>>> +
>>> + mmc_pwrseq_unregister(&pwrseq->pwrseq);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static struct platform_driver mmc_pwrseq_sd8787_driver = {
>>> + .probe = mmc_pwrseq_sd8787_probe,
>>> + .remove = mmc_pwrseq_sd8787_remove,
>>> + .driver = {
>>> + .name = "pwrseq_sd8787",
>>> + .of_match_table = mmc_pwrseq_sd8787_of_match,
>>> + },
>>> +};
>>> +
>>> +module_platform_driver(mmc_pwrseq_sd8787_driver);
>>> +MODULE_LICENSE("GPL v2");
>>> --
>>> 2.10.2
>>>
>>
>> Twisting my head around how this could be integrated smoothly into
>> pwrseq simple. No, I just can find a good way forward without messing
>> up pwrseq simple itself.
>>
>> So, for now I decided (once more :-), that let's keep this as separate
>> driver!
>
>
> I still worry about if there will be more and more seperate drivers. :)
Yes, me to. However, in some cases it's just going to be too device
specific to make a generic pwrseq driver to deal with it.
Also, if we do see that the new Marvell driver can be used together
with some other devices, we can always consider to make it more
generic in a second step.
>
> IIRC Peter Chen was trying to move pwrseq out of mmc and use it
> for USB stuff. It seems there is no follow-up plan there but should
> we invent a new directory to fold in all the pweseq stuff there,
> for instance, drivers/mmc/pweseqs/.
The problem with a new directory is that we need to export the mmc
pwseq interface via a public mmc header. I would rather try to keep as
close as possible to the mmc core.
Although, I also think it's a good idea to look into how to convert
existing mmc pwrseq into using the generic pwrseq instead. Although,
we still need to keep the existing mmc DT bindings, even if we can
mark them as deprecated.
[...]
Kind regards
Uffe
^ permalink raw reply
* Re: [PATCH 1/3] ARM: dts: Add support for phyCORE-AM335x PCM-953 carrier board
From: Teresa Remmet @ 2017-01-20 7:36 UTC (permalink / raw)
To: Vladimir Zapolskiy, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Benoît Cousson, Tony Lindgren, Rob Herring, Mark Rutland,
Wadim Egorov
In-Reply-To: <dda40964-44b5-e9ca-ebcf-273814e27440-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
Hello Vladimir,
thank you for your review.
Am Donnerstag, den 19.01.2017, 16:24 +0200 schrieb Vladimir Zapolskiy:
> On 01/19/2017 03:07 PM, Teresa Remmet wrote:
> >
> > The phyCORE-AM335x development kit is a combination of the
> > phyCORE-AM335x SoM and a PCM-953 carrier board. The features
> > of the PCM-953 are:
> > * ETH phy on carrier board: 1x RGMII
> > * 1x CAN
> > * Up to 4x UART
> > * USB0 (otg)
> > * USB1 (host)
> > * SD slot
> > * User gpio-keys
> > * User LEDs
> >
> > Signed-off-by: Teresa Remmet <t.remmet-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org>
> > Reviewed-by: Wadim Egorov <w.egorov-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org>
> > ---
> > .../devicetree/bindings/arm/omap/omap.txt | 3 +
> > arch/arm/boot/dts/Makefile | 1 +
> > arch/arm/boot/dts/am335x-pcm-953.dtsi | 303
> > +++++++++++++++++++++
> > arch/arm/boot/dts/am335x-phycore-rdk.dts | 27 ++
> > 4 files changed, 334 insertions(+)
> > create mode 100644 arch/arm/boot/dts/am335x-pcm-953.dtsi
> > create mode 100644 arch/arm/boot/dts/am335x-phycore-rdk.dts
> >
> > diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt
> > b/Documentation/devicetree/bindings/arm/omap/omap.txt
> > index 05f95c3..8219b2c 100644
> > --- a/Documentation/devicetree/bindings/arm/omap/omap.txt
> > +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
> > @@ -151,6 +151,9 @@ Boards:
> > - AM335X SBC-T335 : single board computer, built around the Sitara
> > AM3352/4
> > compatible = "compulab,sbc-t335", "compulab,cm-t335",
> > "ti,am33xx"
> >
> > +- AM335X phyCORE-AM335x: Development kit
> > + compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-
> > som", "ti,am33xx"
> > +
> > - OMAP5 EVM : Evaluation Module
> > compatible = "ti,omap5-evm", "ti,omap5"
> >
> > diff --git a/arch/arm/boot/dts/Makefile
> > b/arch/arm/boot/dts/Makefile
> > index 7327250..dd71afe 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -573,6 +573,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
> > am335x-lxm.dtb \
> > am335x-nano.dtb \
> > am335x-pepper.dtb \
> > + am335x-phycore-rdk.dtb \
> > am335x-shc.dtb \
> > am335x-sbc-t335.dtb \
> > am335x-sl50.dtb \
> > diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi
> > b/arch/arm/boot/dts/am335x-pcm-953.dtsi
> > new file mode 100644
> > index 0000000..54a171d
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/am335x-pcm-953.dtsi
> > @@ -0,0 +1,303 @@
> > +/*
> > + * Copyright (C) 2014-2017 Phytec Messtechnik GmbH
> > + * Author: Wadim Egorov <w.egorov-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org>
> > + * Teresa Remmet <t.remmet-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > modify
> > + * it under the terms of the GNU General Public License version 2
> > as
> > + * published by the Free Software Foundation.
> > + */
> > +
> > +#include <dt-bindings/input/input.h>
> > +
> > +/ {
> > + model = "Phytec AM335x PCM-953";
> > + compatible = "phytec,am335x-pcm-953", "phytec,am335x-
> > phycore-som", "ti,am33xx";
> > +
> > + user_leds: user_leds {
> > + compatible = "gpio-leds";
> > + };
> > +
> > + user_buttons: user_buttons {
> > + compatible = "gpio-keys";
> > + };
> > +
> > + regulators {
> > + compatible = "simple-bus";
> Please drop "simple-bus" compatible, see http://www.spinics.net/lists
> /linux-usb/msg101497.html
>
Ok, I will.
> >
> > +
> > + vcc3v3: fixedregulator@1 {
> > + compatible = "regulator-fixed";
> > + };
> > +
> > + vcc1v8: fixedregulator@2 {
> > + compatible = "regulator-fixed";
> > + };
> > + };
> > +};
> > +
> > +/* CAN */
> > +&am33xx_pinmux {
> Which .dtsi file contains the referenced am33xx_pinmux device node?
>
> You should include that file firstly, this is relevant to all other
> references to device nodes used in this file.
The device tree for the Phytec AM335x boards is spitted apart, as they
consist of an SoM and a carrier board. The am33xx_pinmux is defined in
the am33xx.dtsi which is included in the am335x-phycore-som.dtsi.
>
> >
> > + dcan1_pins: pinmux_dcan1 {
> > + pinctrl-single,pins = <
> > + AM33XX_IOPAD(0x980, PIN_OUTPUT_PULLUP |
> > MUX_MODE2) /* uart1_rxd.dcan1_tx_mux2 */
> > + AM33XX_IOPAD(0x984, PIN_INPUT_PULLUP |
> > MUX_MODE2) /* uart1_txd.dcan1_rx_mux2 */
> > + >;
> > + };
> > +};
> > +
> > +&dcan1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&dcan1_pins>;
> > + status = "okay";
> > +};
> > +
> > +/* Ethernet */
> > +&am33xx_pinmux {
> > + ethernet1_pins: pinmux_ethernet1 {
> > + pinctrl-single,pins = <
> > + AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
> > + AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN |
> > MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
> > + AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
> > + AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
> > + AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
> > + AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
> > + AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
> > + AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN |
> > MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
> > + AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN |
> > MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
> > + AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN |
> > MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
> > + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN |
> > MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
> > + AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN |
> > MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
> > + >;
> > + };
> > +};
> > +
> > +&cpsw_emac1 {
> > + phy-handle = <&phy1>;
> > + phy-mode = "rgmii-id";
> > + dual_emac_res_vlan = <2>;
> > + status = "okay";
> > +};
> > +
> > +&davinci_mdio {
> > + phy1: ethernet-phy@1 {
> > + reg = <2>;
> There is a mismatch between unit address and 'reg' property values.
I will fix that.
>
> >
> > +
> > + /* Register 260 (104h) – RGMII Clock and Control
> > Pad Skew */
> > + rxc-skew-ps = <1400>;
> > + rxdv-skew-ps = <0>;
> > + txc-skew-ps = <1400>;
> > + txen-skew-ps = <0>;
> > + /* Register 261 (105h) – RGMII RX Data Pad Skew */
> > + rxd3-skew-ps = <0>;
> > + rxd2-skew-ps = <0>;
> > + rxd1-skew-ps = <0>;
> > + rxd0-skew-ps = <0>;
> > + /* Register 262 (106h) – RGMII TX Data Pad Skew */
> > + txd3-skew-ps = <0>;
> > + txd2-skew-ps = <0>;
> > + txd1-skew-ps = <0>;
> > + txd0-skew-ps = <0>;
> > + };
> > +};
> > +
> > +&mac {
> > + slaves = <2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <ðernet0_pins ðernet1_pins>;
> > + dual_emac;
> It seems that TI has properties with underscores in the names, acked.
>
> >
> > +};
> > +
> > +/* Misc */
> > +&am33xx_pinmux {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&cb_gpio_pins>;
> > +
> > + cb_gpio_pins: pinmux_cb_gpio {
> > + pinctrl-single,pins = <
> > + AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE7) /* uart0_ctsn.gpio1_8 */
> > + AM33XX_IOPAD(0x96c, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE7) /* uart0_rtsn.gpio1_9 */
> > + >;
> > + };
> > +};
> > +
> > +/* MMC */
> > +&am33xx_pinmux {
> > + mmc1_pins: pinmux_mmc1_pins {
> > + pinctrl-single,pins = <
> > + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP |
> > MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
> > + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP |
> > MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
> > + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP |
> > MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
> > + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP |
> > MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
> > + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP |
> > MUX_MODE0) /* mmc0_clk.mmc0_clk */
> > + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP |
> > MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
> > + AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP |
> > MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
> > + >;
> > + };
> > +};
> > +
> > +&mmc1 {
> > + vmmc-supply = <&vcc3v3>;
> > + bus-width = <4>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&mmc1_pins>;
> > + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
> > + status = "okay";
> > +};
> > +
> > +/* Power */
> > +&vcc3v3 {
> > + regulator-name = "vcc3v3";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-boot-on;
> > +};
> Please add properties directly into vcc3v3 device node.
I spitted the node apart as we structured the device tree in different
section. If I move this to the node directly the device tree
is not so readable in general any more. My opinion.
The same fits to the user leds and user buttons.
>
> >
> > +
> > +&vcc1v8 {
> > + regulator-name = "vcc1v8";
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-boot-on;
> > +};
> > +
> Please add properties directly into vcc1v8 device node.
>
> >
> > +/* UARTs */
> > +&am33xx_pinmux {
> > + uart0_pins: pinmux_uart0 {
> > + pinctrl-single,pins = <
> > + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP |
> > MUX_MODE0) /* uart0_rxd.uart0_rxd */
> > + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE0) /* uart0_txd.uart0_txd */
> > + >;
> > + };
> > +
> > + uart1_pins: pinmux_uart1 {
> > + pinctrl-single,pins = <
> > + AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP |
> > MUX_MODE0) /* uart1_rxd.uart1_rxd */
> > + AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE0) /* uart1_txd.uart1_txd */
> > + AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)
> > /* uart1_ctsn.uart1_ctsn */
> > + AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
> > + >;
> > + };
> > +
> > + uart2_pins: pinmux_uart2 {
> > + pinctrl-single,pins = <
> > + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP |
> > MUX_MODE1) /* mii1_tx_clk.uart2_rxd */
> > + AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE1) /* mii1_rx_clk.uart2_txd */
> > + >;
> > + };
> > +
> > + uart3_pins: pinmux_uart3 {
> > + pinctrl-single,pins = <
> > + AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP |
> > MUX_MODE1) /* mii1_rxd3.uart3_rxd */
> > + AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE1) /* mii1_rxd2.uart3_txd */
> > + >;
> > + };
> > +};
> > +
> > +&uart0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart0_pins>;
> > + status = "okay";
> > +};
> > +
> > +&uart1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart1_pins>;
> > +};
> > +
> > +&uart2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart2_pins>;
> > + status = "okay";
> > +};
> > +
> > +&uart3 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart3_pins>;
> > + status = "okay";
> > +};
> > +
> > +/* USB */
> > +&cppi41dma {
> > + status = "okay";
> > +};
> > +
> > +&usb_ctrl_mod {
> > + status = "okay";
> > +};
> > +
> > +&usb {
> > + status = "okay";
> > +};
> > +
> > +&usb0 {
> > + status = "okay";
> > +};
> > +
> > +&usb0_phy {
> > + status = "okay";
> > +};
> > +
> > +&usb1 {
> > + status = "okay";
> > + dr_mode = "host";
> > +};
> > +
> > +&usb1_phy {
> > + status = "okay";
> > +};
> > +
> > +/* User IO */
> > +&am33xx_pinmux {
> > + user_buttons_pins: pinmux_user_buttons {
> > + pinctrl-single,pins = <
> > + AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLDOWN |
> > MUX_MODE7) /* emu0.gpio3_7 */
> > + AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLDOWN |
> > MUX_MODE7) /* emu1.gpio3_8 */
> > + >;
> > + };
> > +
> > + user_leds_pins: pinmux_user_leds {
> > + pinctrl-single,pins = <
> > + AM33XX_IOPAD(0x880, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE7) /* gpmc_csn1.gpio1_30 */
> > + AM33XX_IOPAD(0x884, PIN_OUTPUT_PULLDOWN |
> > MUX_MODE7) /* gpmc_csn2.gpio1_31 */
> > + >;
> > + };
> > +};
> > +
> > +&user_buttons {
> Please add properties directly into user_buttons device node.
>
> >
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&user_buttons_pins>;
> > + status = "okay";
> Please remove the redundant property above.
I will remove it.
>
> >
> > +
> > + button@0 {
> > + label = "home";
> > + linux,code = ;
> > + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
> > + gpio-key,wakeup;
> > + };
> > +
> > + button@1 {
> > + label = "menu";
> > + linux,code = ;
> > + gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
> > + gpio-key,wakeup;
> > + };
> > +};
> > +
> > +&user_leds {
> Please add properties directly into user_leds device node.
>
> >
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&user_leds_pins>;
> > + status = "okay";
> Please remove the redundant property above.
I will remove it.
Thank you,
Teresa
>
> >
> > +
> > + green {
> > + label = "green:user";
> > + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
> > + linux,default-trigger = "gpio";
> > + default-state = "on";
> > + };
> > +
> > + yellow {
> > + label = "yellow:user";
> > + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
> > + linux,default-trigger = "gpio";
> > + default-state = "on";
> > + };
> > +};
> > diff --git a/arch/arm/boot/dts/am335x-phycore-rdk.dts
> > b/arch/arm/boot/dts/am335x-phycore-rdk.dts
> > new file mode 100644
> > index 0000000..305f0b3
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/am335x-phycore-rdk.dts
> > @@ -0,0 +1,27 @@
> > +/*
> > + * Copyright (C) 2014 PHYTEC Messtechnik GmbH
> > + * Author: Wadim Egorov <w.egorov-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > modify
> > + * it under the terms of the GNU General Public License version 2
> > as
> > + * published by the Free Software Foundation.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "am335x-phycore-som.dtsi"
> > +#include "am335x-pcm-953.dtsi"
> > +
> > +/* SoM */
> > +&i2c_eeprom {
> > + status = "okay";
> > +};
> > +
> > +&i2c_rtc {
> > + status = "okay";
> > +};
> > +
> > +&serial_flash {
> > + status = "okay";
> > +
> > +};
> >
--
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^ permalink raw reply
* Re: [PATCH v6 00/25] Support qcom's HSIC USB and rewrite USB2 HS support
From: Peter Chen @ 2017-01-20 7:40 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-usb, Felipe Balbi, Heikki Krogerus, Arnd Bergmann,
Neil Armstrong, linux-arm-msm, linux-kernel, Bjorn Andersson,
devicetree, Peter Chen, Greg Kroah-Hartman, Andy Gross,
Ivan T. Ivanov, Kishon Vijay Abraham I, linux-arm-kernel
In-Reply-To: <20161228225711.698-1-stephen.boyd@linaro.org>
On Wed, Dec 28, 2016 at 02:56:46PM -0800, Stephen Boyd wrote:
> The state of USB ChipIdea support on Qualcomm's platforms is not great.
> The DT description of these devices requires up to three different nodes
> for what amounts to be the same hardware block, when there should really
> only be one. Furthermore, the "phy" driver that is in mainline (phy-msm-usb.c)
> duplicates the OTG state machine and touches the ci controller wrapper
> registers when it should really be focused on the phy and the ULPI accesses
> needed to get the phy working. There's also a slimmed down phy driver for
> the msm8916 platform, but really the phy hardware is the same as other MSMs,
> so we have two drivers doing pretty much the same thing. This leads to a
> situtaion where we have the chipidea core driver, the "phy" driver, and
> sometimes the ehci-msm.c driver operating the same device all at the same
> time with very little coordination. This just isn't very safe and is
> confusing from a driver perspective when trying to figure out who does what.
> Finally, there isn't any HSIC support on platforms like apq8074 so we
> should add that.
>
> This patch series updates the ChipIdea driver and the MSM wrapper
> (ci_hdrc_msm.c) to properly handle the PHY and wrapper bits at the right
> times in the right places. To get there, we update the ChipIdea core to
> have support for the ULPI phy bus introduced by Heikki. Along the way
> we fix bugs with the extcon handling for peripheral and OTG mode controllers
> and move the parts of phy-usb-msm.c that are touching the CI controller
> wrapper into the wrapper driver (ci_hdrc_msm.c). Finally we add support
> for the HSIC phy based on the ULPI bus and rewrite the HS phy driver
> (phy-usb-msm.c) as a standard ULPI phy driver.
>
> Once this series is accepted, we should be able to delete the phy-usb-msm.c,
> phy-qcom-8x16-usb.c, and ehci-msm.c drivers from the tree and use the ULPI
> based phy driver (which also lives in drivers/phy/ instead of drivers/usb/phy/)
> and the chipidea host core instead.
>
> I've also sent separate patches for other minor pieces to make this
> all work. The full tree can be found here[1], hacks and all to get
> things working. I've tested this on the db410c, apq8074 dragonboard,
> and ifc6410 with configfs gadgets and otg cables.
>
> Patches based on v4.10-rc1
>
> Changes from v5:
> * Replaced "Emulate OTGSC interrupt enable path" patch with a patch
> from Peter
> * Updated HS phy driver to support set_mode callback to handle pullup
> * New patch to set the mode to device or host in chipidea udc pullup
> function to toggle the pullup for HS mode
> * New patch to drop lock around event_notify callback to avoid lockdep
> issues
> * Removal of extcon usage from HS phy driver
> * Picked up acks from Heikki and Peter on ULPI core patch
>
Hi Stephen,
I have pushed your first 22 patches to my ci-for-usb-next, fixed the
conflict for patch 10, and dropped your patch 23.
Peter
> Changes from v4:
> * Picked up Acks from Rob
> * Updated HS phy init sequence DT property to restrict it to offsets
>
> Changes from v3:
> * Picked up Acks from Peter
> * Updated extcon consolidation patch per Peter's comments
> * Folded in simplification from Heikki for ULPI DT matching
>
> Changes from v2:
> * Added SoC specific compatibles in phy bindings
> * Dropped AVVIS patch for OTG statemachine
> * New patch to consolidate extcon handlers
> * Picked up Acks from Peter
> * Rebased onto v4.8-rc1
> * Reworked ULPI OF code to look at vid == 0 instead of pid == 0
> * Dropped ULPI bindings for vid and pid overrides
>
> Changes from v1:
> * Reworked ULPI device probing to keep using vendor/product ids that
> come from DT if needed and falls back to OF style match when product id
> is 0
> * PHY init later patch was rejected so that moved to a quirk flag and
> the msm wrapper started managing the phy on/off
> * Updated clk requirements for HSIC phy in binding doc
> * Added optional clk in wrapper for "housekeeping" found on older qcom
> platforms
> * Bug fix to OTGSC polling function
> * Changed runtime PM patch to set as active instead of get/put
>
> TODO:
> * DMA fails on arm64 so we need something like [2] to make it work.
> * The db410c needs a driver to toggle the onboard switch to connect
> the usb hub instead of micro port when the usb cable is disconnected.
> I've sent a patch set for this[3], which needs some further
> discussion/development.
> * apq8064 platforms need a vbus regulator to really use otg and I haven't
> tried out the RPM based regulators yet
> * The HSIC phy on the apq8074 dragonboard is connected to a usb4604
> device which requires the i2c driver to probe and send an i2c
> sequence before the HSIC controller enumerates or HSIC doesn't work.
> Right now I have a hack to force the controller to probe defer
> once so that usb4604 probes first. This needs a more proper solution
> like having the DT describe a linkage between the controller and
> the usb device so we can enforce probe ordering.
>
> [1] https://git.linaro.org/people/stephen.boyd/linux.git/log/?h=usb-hsic-8074
> [2] https://patchwork.kernel.org/patch/9319527/
> [3] https://lkml.kernel.org/r/20160914014246.31847-1-stephen.boyd@linaro.org
>
> Peter Chen (1):
> usb: chipidea: vbus event may exist before starting gadget
>
> Stephen Boyd (24):
> of: device: Support loading a module with OF based modalias
> of: device: Export of_device_{get_modalias,uvent_modalias} to modules
> usb: ulpi: Support device discovery via DT
> usb: chipidea: Only read/write OTGSC from one place
> usb: chipidea: Handle extcon events properly
> usb: chipidea: Add platform flag for wrapper phy management
> usb: chipidea: Notify events when switching host mode
> usb: chipidea: Remove locking in ci_udc_start()
> usb: chipidea: Add support for ULPI PHY bus
> usb: chipidea: Consolidate extcon notifiers
> usb: chipidea: msm: Mark device as runtime pm active
> usb: chipidea: msm: Rely on core to override AHBBURST
> usb: chipidea: msm: Use hw_write_id_reg() instead of writel
> usb: chipidea: msm: Add proper clk and reset support
> usb: chipidea: msm: Mux over secondary phy at the right time
> usb: chipidea: msm: Restore wrapper settings after reset
> usb: chipidea: msm: Make platform data driver local instead of global
> usb: chipidea: msm: Add reset controller for PHY POR bit
> usb: chipidea: msm: Handle phy power states
> usb: chipidea: msm: Be silent on probe defer errors
> usb: chipidea: Drop lock across event_notify during gadget stop
> usb: chipidea: Pullup D+ in device mode via phy APIs
> phy: Add support for Qualcomm's USB HSIC phy
> phy: Add support for Qualcomm's USB HS phy
>
> .../devicetree/bindings/phy/qcom,usb-hs-phy.txt | 78 ++++++
> .../devicetree/bindings/phy/qcom,usb-hsic-phy.txt | 65 +++++
> Documentation/devicetree/bindings/usb/ulpi.txt | 20 ++
> drivers/of/device.c | 25 ++
> drivers/phy/Kconfig | 15 ++
> drivers/phy/Makefile | 2 +
> drivers/phy/phy-qcom-usb-hs.c | 243 ++++++++++++++++++
> drivers/phy/phy-qcom-usb-hsic.c | 160 ++++++++++++
> drivers/usb/chipidea/Kconfig | 8 +
> drivers/usb/chipidea/Makefile | 1 +
> drivers/usb/chipidea/ci.h | 22 +-
> drivers/usb/chipidea/ci_hdrc_msm.c | 280 ++++++++++++++++++---
> drivers/usb/chipidea/core.c | 126 ++++------
> drivers/usb/chipidea/host.c | 10 +
> drivers/usb/chipidea/otg.c | 96 +++++--
> drivers/usb/chipidea/udc.c | 17 +-
> drivers/usb/chipidea/ulpi.c | 113 +++++++++
> drivers/usb/common/ulpi.c | 79 +++++-
> include/linux/of_device.h | 6 +
> include/linux/usb/chipidea.h | 9 +-
> 20 files changed, 1227 insertions(+), 148 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt
> create mode 100644 Documentation/devicetree/bindings/usb/ulpi.txt
> create mode 100644 drivers/phy/phy-qcom-usb-hs.c
> create mode 100644 drivers/phy/phy-qcom-usb-hsic.c
> create mode 100644 drivers/usb/chipidea/ulpi.c
>
> --
> 2.10.0.297.gf6727b0
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Best Regards,
Peter Chen
^ permalink raw reply
* Re: [PATCH 2/2] ARM: dts: rockchip: add dts for RK3288-Tinker board
From: Shawn Lin @ 2017-01-20 7:48 UTC (permalink / raw)
To: Eddie Cai
Cc: shawn.lin, robh+dt, mark.rutland, Heiko Stuebner, linux,
devicetree, Eddie Cai, linux-kernel, linux-arm-kernel,
linux-rockchip
In-Reply-To: <CAJrj+DMf1_SKnTexMxiQC=x6dywCQvh2jBJVg=zs4QtdgQ6BCw@mail.gmail.com>
On 2017/1/20 15:07, Eddie Cai wrote:
> 2017-01-20 10:29 GMT+08:00 Shawn Lin <shawn.lin@rock-chips.com>:
>>
>> On 2017/1/19 10:11, Eddie Cai wrote:
>>>
>>> This patch add basic support for RK3288-Tinker board. We can boot in to rootfs
>>> with this patch.
>>>
>>> Signed-off-by: Eddie Cai <eddie.cai@rock-chips.com>
>>> ---
>>> arch/arm/boot/dts/Makefile | 1 +
>>> arch/arm/boot/dts/rk3288-tinker.dts | 556 ++++++++++++++++++++++++++++++++++++
>>> 2 files changed, 557 insertions(+)
>>> create mode 100644 arch/arm/boot/dts/rk3288-tinker.dts
>>>
>>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>>> index 7327250..4fc05b7 100644
>>> --- a/arch/arm/boot/dts/Makefile
>>> +++ b/arch/arm/boot/dts/Makefile
>>> @@ -679,6 +679,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>>> rk3288-popmetal.dtb \
>>> rk3288-r89.dtb \
>>> rk3288-rock2-square.dtb \
>>> + rk3288-tinker.dtb \
>>> rk3288-veyron-brain.dtb \
>>> rk3288-veyron-jaq.dtb \
>>> rk3288-veyron-jerry.dtb \
>>> diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
>>> new file mode 100644
>>> index 0000000..37cb431
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/rk3288-tinker.dts
>>> @@ -0,0 +1,556 @@
>>> +/*
>>> + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
>>> + *
>>> + * This file is dual-licensed: you can use it either under the terms
>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>> + * licensing only applies to this file, and not this project as a
>>> + * whole.
>>> + *
>>> + * a) This file is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation; either version 2 of the
>>> + * License, or (at your option) any later version.
>>> + *
>>> + * This file is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * Or, alternatively,
>>> + *
>>> + * b) Permission is hereby granted, free of charge, to any person
>>> + * obtaining a copy of this software and associated documentation
>>> + * files (the "Software"), to deal in the Software without
>>> + * restriction, including without limitation the rights to use,
>>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>>> + * sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following
>>> + * conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be
>>> + * included in all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include "rk3288.dtsi"
>>> +
>>> +/ {
>>> + model = "Rockchip RK3288 Tinker Board";
>>> + compatible = "rockchip,rk3288-tinker", "rockchip,rk3288";
>>> +
>>> + memory {
>>> + reg = <0x0 0x80000000>;
>>> + device_type = "memory";
>>> + };
>>> +
>>> + ext_gmac: external-gmac-clock {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <125000000>;
>>> + clock-output-names = "ext_gmac";
>>> + };
>>> +
>>> + gpio-keys {
>>> + compatible = "gpio-keys";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + autorepeat;
>>> +
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pwrbtn>;
>>> +
>>> + button@0 {
>>> + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
>>> + linux,code = <116>;
>>> + label = "GPIO Key Power";
>>> + linux,input-type = <1>;
>>> + gpio-key,wakeup = <1>;
>>> + debounce-interval = <100>;
>>> + };
>>> + };
>>> +
>>> + gpio-leds {
>>> + compatible = "gpio-leds";
>>> +
>>> + pwr-led {
>>> + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
>>> + linux,default-trigger = "default-on";
>>> + };
>>> +
>>> + act-led {
>>> + gpios=<&gpio2 3 GPIO_ACTIVE_LOW>;
>>> + linux,default-trigger="mmc0";
>>> + };
>>> + };
>>> +
>>> + sound {
>>> + compatible = "simple-audio-card";
>>> + simple-audio-card,format = "i2s";
>>> + simple-audio-card,name = "rockchip,tinker-codec";
>>> + simple-audio-card,mclk-fs = <512>;
>>> + simple-audio-card,cpu {
>>> + sound-dai = <&i2s>;
>>> + };
>>> + simple-audio-card,codec {
>>> + sound-dai = <&hdmi>;
>>> + };
>>> + };
>>> +
>>> + vcc_sys: vsys-regulator {
>>> + compatible = "regulator-fixed";
>>> + regulator-name = "vcc_sys";
>>> + regulator-min-microvolt = <5000000>;
>>> + regulator-max-microvolt = <5000000>;
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + };
>>> +
>>> + /*
>>> + * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from
>>> + * vcc_io directly. Those boards won't be able to power cycle SD cards
>>> + * but it shouldn't hurt to toggle this pin there anyway.
>>> + */
>>> + vcc_sd: sdmmc-regulator {
>>> + compatible = "regulator-fixed";
>>> + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&sdmmc_pwr>;
>>> + regulator-name = "vcc_sd";
>>> + regulator-min-microvolt = <3300000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + startup-delay-us = <100000>;
>>> + vin-supply = <&vcc_io>;
>>> + };
>>> +};
>>> +
>>> +&cpu0 {
>>> + cpu0-supply = <&vdd_cpu>;
>>> +};
>>> +
>>> +&gmac {
>>> + phy-supply = <&vcc33_lan>;
>>> + phy-mode = "rgmii";
>>> + clock_in_out = "input";
>>> + snps,reset-gpio = <&gpio4 7 0>;
>>> + snps,reset-active-low;
>>> + snps,reset-delays-us = <0 10000 1000000>;
>>> + assigned-clocks = <&cru SCLK_MAC>;
>>> + assigned-clock-parents = <&ext_gmac>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&rgmii_pins>;
>>> + tx_delay = <0x30>;
>>> + rx_delay = <0x10>;
>>> + status = "ok";
>>> +};
>>> +
>>> +&hdmi {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + #sound-dai-cells = <0>;
>>> + ddc-i2c-bus = <&i2c5>;
>>> + status = "okay";
>>> + /* Don't use vopl for HDMI */
>>> + ports {
>>> + hdmi_in: port {
>>> + /delete-node/ endpoint@1;
>>> + };
>>> + };
>>> +};
>>> +
>>> +&i2c0 {
>>> + status = "okay";
>>> + clock-frequency = <400000>;
>>> +
>>> + rk808: pmic@1b {
>>> + compatible = "rockchip,rk808";
>>> + reg = <0x1b>;
>>> + interrupt-parent = <&gpio0>;
>>> + interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>;
>>> + dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
>>> + <&gpio0 12 GPIO_ACTIVE_HIGH>;
>>> +
>>> + rockchip,system-power-controller;
>>> + wakeup-source;
>>> + #clock-cells = <1>;
>>> + clock-output-names = "xin32k", "rk808-clkout2";
>>> +
>>> + vcc1-supply = <&vcc_sys>;
>>> + vcc2-supply = <&vcc_sys>;
>>> + vcc3-supply = <&vcc_sys>;
>>> + vcc4-supply = <&vcc_sys>;
>>> + vcc6-supply = <&vcc_sys>;
>>> + vcc7-supply = <&vcc_sys>;
>>> + vcc8-supply = <&vcc_18>;
>>> + vcc9-supply = <&vcc_io>;
>>> + vcc10-supply = <&vcc_io>;
>>> + vcc11-supply = <&vcc_sys>;
>>> + vcc12-supply = <&vcc_io>;
>>> + vddio-supply = <&vcc18_ldo1>;
>>> +
>>> + regulators {
>>> + vdd_cpu: DCDC_REG1 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + regulator-min-microvolt = <750000>;
>>> + regulator-max-microvolt = <1350000>;
>>> + regulator-name = "vdd_arm";
>>> + regulator-ramp-delay = <6000>;
>>> + regulator-state-mem {
>>> + regulator-off-in-suspend;
>>> + };
>>> + };
>>> +
>>> + vdd_gpu: DCDC_REG2 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + regulator-min-microvolt = <850000>;
>>> + regulator-max-microvolt = <1250000>;
>>> + regulator-name = "vdd_gpu";
>>> + regulator-ramp-delay = <6000>;
>>> + regulator-state-mem {
>>> + regulator-on-in-suspend;
>>> + regulator-suspend-microvolt = <1000000>;
>>> + };
>>> + };
>>> +
>>> + vcc_ddr: DCDC_REG3 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + regulator-name = "vcc_ddr";
>>> + regulator-state-mem {
>>> + regulator-on-in-suspend;
>>> + };
>>> + };
>>> +
>>> + vcc_io: DCDC_REG4 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + regulator-min-microvolt = <3300000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-name = "vcc_io";
>>> + regulator-state-mem {
>>> + regulator-on-in-suspend;
>>> + regulator-suspend-microvolt = <3300000>;
>>> + };
>>> + };
>>> +
>>> + vcc18_ldo1: LDO_REG1 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <1800000>;
>>> + regulator-name = "vcc18_ldo1";
>>> + regulator-state-mem {
>>> + regulator-on-in-suspend;
>>> + regulator-suspend-microvolt = <1800000>;
>>> + };
>>> + };
>>> +
>>> + vcc33_mipi: LDO_REG2 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + regulator-min-microvolt = <3300000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-name = "vcc33_mipi";
>>> + regulator-state-mem {
>>> + regulator-off-in-suspend;
>>> + };
>>> + };
>>> +
>>> + vdd_10: LDO_REG3 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + regulator-min-microvolt = <1000000>;
>>> + regulator-max-microvolt = <1000000>;
>>> + regulator-name = "vdd_10";
>>> + regulator-state-mem {
>>> + regulator-on-in-suspend;
>>> + regulator-suspend-microvolt = <1000000>;
>>> + };
>>> + };
>>> +
>>> + vcc18_codec: LDO_REG4 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <1800000>;
>>> + regulator-name = "vcc18_codec";
>>> + regulator-state-mem {
>>> + regulator-on-in-suspend;
>>> + regulator-suspend-microvolt = <1800000>;
>>> + };
>>> + };
>>> +
>>> + vccio_sd: LDO_REG5 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>
>>
>>
>> are some other io banks or devices powered by
>> vccio_sd, so that you mark it as boot-on and always-on?
>
> This board do not have emmc, It use SD card to store firmware image.
> So have to always on.
mmc core will take over tis properly. I undertand that the SD card will
be always on but it shouldn't be the reason we need to it to be
always-on. And obvious we don't need it to be boot-on since again
mmc core will turn on it when starting to init SD card.
>>
>>
>>
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-name = "vccio_sd";
>>> + regulator-state-mem {
>>> + regulator-on-in-suspend;
>>> + regulator-suspend-microvolt = <3300000>;
>>> + };
>>> + };
>>> +
>>> + vdd10_lcd: LDO_REG6 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + regulator-min-microvolt = <1000000>;
>>> + regulator-max-microvolt = <1000000>;
>>> + regulator-name = "vdd10_lcd";
>>> + regulator-state-mem {
>>> + regulator-on-in-suspend;
>>> + regulator-suspend-microvolt = <1000000>;
>>> + };
>>> + };
>>> +
>>> + vcc_18: LDO_REG7 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <1800000>;
>>> + regulator-name = "vcc_18";
>>> + regulator-state-mem {
>>> + regulator-on-in-suspend;
>>> + regulator-suspend-microvolt = <1800000>;
>>> + };
>>> + };
>>> +
>>> + vcc18_lcd: LDO_REG8 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <1800000>;
>>> + regulator-name = "vcc18_lcd";
>>> + regulator-state-mem {
>>> + regulator-on-in-suspend;
>>> + regulator-suspend-microvolt = <1800000>;
>>> + };
>>> + };
>>> +
>>> + vcc33_sd: SWITCH_REG1 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + regulator-name = "vcc33_sd";
>>> + regulator-state-mem {
>>> + regulator-on-in-suspend;
>>> + };
>>> + };
>>> +
>>> + vcc33_lan: SWITCH_REG2 {
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + regulator-name = "vcc33_lan";
>>> + regulator-state-mem {
>>> + regulator-on-in-suspend;
>>> + };
>>> + };
>>> + };
>>> + };
>>> +};
>>> +
>>> +&i2c2 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&i2c5 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&i2s {
>>> + #sound-dai-cells = <0>;
>>> + status = "okay";
>>> +};
>>> +
>>> +&io_domains {
>>> + status = "okay";
>>> +
>>> + sdcard-supply = <&vccio_sd>;
>>> +};
>>> +
>>> +&pinctrl {
>>> + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
>>> + drive-strength = <8>;
>>> + };
>>> +
>>> + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
>>> + bias-pull-up;
>>> + drive-strength = <8>;
>>> + };
>>> +
>>> + backlight {
>>> + bl_en: bl-en {
>>> + rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
>>> + };
>>> + };
>>> +
>>> + buttons {
>>> + pwrbtn: pwrbtn {
>>> + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
>>> + };
>>> + };
>>> +
>>> + eth_phy {
>>> + eth_phy_pwr: eth-phy-pwr {
>>> + rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
>>> + };
>>> + };
>>> +
>>> + pmic {
>>> + pmic_int: pmic-int {
>>> + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO \
>>> + &pcfg_pull_up>;
>>> + };
>>> +
>>> + dvs_1: dvs-1 {
>>> + rockchip,pins = <RK_GPIO0 11 RK_FUNC_GPIO \
>>> + &pcfg_pull_down>;
>>> + };
>>> +
>>> + dvs_2: dvs-2 {
>>> + rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO \
>>> + &pcfg_pull_down>;
>>> + };
>>> + };
>>> +
>>> + sdmmc {
>>> + /*
>>> + * Default drive strength isn't enough to achieve even
>>> + * high-speed mode on EVB board so bump up to 8ma.
>>> + */
>>> + sdmmc_bus4: sdmmc-bus4 {
>>> + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
>>> + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
>>> + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
>>> + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
>>> + };
>>> +
>>> + sdmmc_clk: sdmmc-clk {
>>> + rockchip,pins = <6 20 RK_FUNC_1 \
>>> + &pcfg_pull_none_drv_8ma>;
>>> + };
>>> +
>>> + sdmmc_cmd: sdmmc-cmd {
>>> + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
>>> + };
>>> +
>>> + sdmmc_pwr: sdmmc-pwr {
>>> + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
>>> + };
>>> + };
>>> +
>>> + usb {
>>> + host_vbus_drv: host-vbus-drv {
>>> + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
>>> + };
>>> +
>>> + pwr_3g: pwr-3g {
>>> + rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
>>> + };
>>> + };
>>> +};
>>> +
>>> +&pwm0 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&saradc {
>>> + vref-supply = <&vcc18_ldo1>;
>>> + status ="okay";
>>> +};
>>> +
>>> +&sdmmc {
>>> + bus-width = <4>;
>>> + cap-mmc-highspeed;
>>> + cap-sd-highspeed;
>>> + card-detect-delay = <200>;
>>> + disable-wp; /* wp not hooked up */
>>> + num-slots = <1>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
>>> + status = "okay";
>>> + supports-sd;
>>
>>
>> This is not upstreamed property. We have no-sdio/no-emmc there to
>> skip the init sequence.
> OK, I will remove it next version
>>
>>
>>> + vmmc-supply = <&vcc_sd>;
>>> + vqmmc-supply = <&vccio_sd>;
>>> +};
>>> +
>>> +&tsadc {
>>> + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
>>> + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
>>> + status = "okay";
>>> +};
>>> +
>>> +&uart0 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&uart1 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&uart2 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&uart3 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&uart4 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&usbphy {
>>> + status = "okay";
>>> +};
>>> +
>>> +&usb_host0_ehci {
>>> + no-relinquish-port;
>>> + status = "okay";
>>> +};
>>> +
>>> +&usb_host1 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&usb_otg {
>>> + status= "okay";
>>> +};
>>> +
>>> +&vopb {
>>> + status = "okay";
>>> +};
>>> +
>>> +&vopb_mmu {
>>> + status = "okay";
>>> +};
>>> +
>>> +&vopl {
>>> + status = "okay";
>>> + /* Don't use vopl for HDMI */
>>> + vopl_out: port {
>>> + /delete-node/ endpoint@0;
>>> + };
>>> +};
>>> +
>>> +&vopl_mmu {
>>> + status = "okay";
>>> +};
>>> +
>>> +&wdt {
>>> + status = "okay";
>>> +};
>>> +
>>>
>>
>>
>> --
>> Best Regards
>> Shawn Lin
>>
>
>
>
--
Best Regards
Shawn Lin
^ permalink raw reply
* Re: [PATCH v3 1/3] mmc: dt-bindings: update Mediatek MMC bindings
From: Ulf Hansson @ 2017-01-20 7:52 UTC (permalink / raw)
To: Yong Mao
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
srv_heupstream, Linus Walleij,
linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Chunfeng Yun,
Eddie Huang, Chaotian Jing
In-Reply-To: <1484821156-20565-2-git-send-email-yong.mao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
+devicetree, Rob
On 19 January 2017 at 11:19, Yong Mao <yong.mao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> From: yong mao <yong.mao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>
> Add description for mtk-hs200-cmd-int-delay
> Add description for mtk-hs400-cmd-int-delay
> Add description for mtk-hs400-cmd-resp-sel
>
> Signed-off-by: Yong Mao <yong.mao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.txt | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
> index 0120c7f..149f472 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
> @@ -21,6 +21,12 @@ Optional properties:
> - assigned-clocks: PLL of the source clock
> - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
> - hs400-ds-delay: HS400 DS delay setting
> +- mtk-hs200-cmd-int-delay: HS200 command internal delay setting.
> + The value is an integer from 0 to 31
Please change to:
mediatek,hs200-cmd-delay
... and if there is a unit, like ns or us, please add that a suffix.
> +- mtk-hs400-cmd-int-delay: HS400 command internal delay setting
> + The value is an integer from 0 to 31
mediatek,hs400-cmd-delay and add unit if applicable.
> +- mtk-hs400-cmd-resp-sel: HS400 command response sample selection
> + The value is an integer from 0 to 1
mediatek,hs400-cmd-resp-sel
And make it a boolean value instead!
>
> Examples:
> mmc0: mmc@11230000 {
> @@ -38,4 +44,7 @@ mmc0: mmc@11230000 {
> assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
> assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
> hs400-ds-delay = <0x14015>;
> + mtk-hs200-cmd-int-delay = <26>;
> + mtk-hs400-cmd-int-delay = <14>;
> + mtk-hs400-cmd-resp-sel = <0>; /* 0: rising, 1: falling */
The rising/falling information belongs in description of the binding a
few lines above. Please move it there.
> };
> --
> 1.7.9.5
>
Kind regards
Uffe
^ permalink raw reply
* Re: [PATCH v11 2/8] power: add power sequence library
From: Peter Chen @ 2017-01-20 7:52 UTC (permalink / raw)
To: rjw
Cc: mark.rutland, Peter Chen, ulf.hansson, heiko, stephen.boyd, sre,
gary.bisson, festevam, stillcompiling, arnd, dbaryshkov,
vaibhav.hiremath, Krzysztof Kozlowski, mka, stern, devicetree,
mail, pawel.moll, linux-pm, s.hauer, troy.kisky, robh+dt,
linux-arm-kernel, hverkuil, oscar, gregkh, linux-usb,
linux-kernel, broonie, p.zabel, shawnguo
In-Reply-To: <20170110070240.GA29454@b29397-desktop>
On Tue, Jan 10, 2017 at 03:02:41PM +0800, Peter Chen wrote:
> On Sat, Jan 07, 2017 at 10:54:56AM +0200, Krzysztof Kozlowski wrote:
> > On Thu, Jan 05, 2017 at 02:01:53PM +0800, Peter Chen wrote:
> > > We have an well-known problem that the device needs to do some power
> > > sequence before it can be recognized by related host, the typical
> > > example like hard-wired mmc devices and usb devices.
> > >
> > > This power sequence is hard to be described at device tree and handled by
> > > related host driver, so we have created a common power sequence
> > > library to cover this requirement. The core code has supplied
> > > some common helpers for host driver, and individual power sequence
> > > libraries handle kinds of power sequence for devices. The pwrseq
> > > librares always need to allocate extra instance for compatible
> > > string match.
> > >
> > > pwrseq_generic is intended for general purpose of power sequence, which
> > > handles gpios and clocks currently, and can cover other controls in
> > > future. The host driver just needs to call of_pwrseq_on/of_pwrseq_off
> > > if only one power sequence is needed, else call of_pwrseq_on_list
> > > /of_pwrseq_off_list instead (eg, USB hub driver).
> > >
> > > For new power sequence library, it can add its compatible string
> > > to pwrseq_of_match_table, then the pwrseq core will match it with
> > > DT's, and choose this library at runtime.
> > >
> > > Signed-off-by: Peter Chen <peter.chen@nxp.com>
> > > Tested-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
> > > Tested-by Joshua Clayton <stillcompiling@gmail.com>
> > > Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> > > Tested-by: Matthias Kaehlcke <mka@chromium.org>
> >
> > Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> > Tested on Odroid U3 (reset sequence for LAN9730):
> > Tested-by: Krzysztof Kozlowski <krzk@kernel.org>
> >
>
> A nice ping...
>
Rafael, would you please review it? This series was discussed about
half a year, and many people need it, I hope it can be in v4.11-rc1,
thanks.
--
Best Regards,
Peter Chen
^ permalink raw reply
* Re: [PATCHv2] dt: bindings: Add support for CSI1 bus
From: Ivaylo Dimitrov @ 2017-01-20 7:59 UTC (permalink / raw)
To: Sakari Ailus, Pavel Machek
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
sre-DgEjT+Ai2ygdnm+yROfE0A, pali.rohar-Re5JQEeQqe8AvxtiuMwx3w,
linux-media-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170119214905.GD3205-S+BSfZ9RZZmRSg0ZkenSGLdO1Tsj/99ntUK59QYPAWc@public.gmane.org>
Hi,
On 19.01.2017 23:49, Sakari Ailus wrote:
> Hi Pavel,
>
> On Wed, Jan 11, 2017 at 11:53:35PM +0100, Pavel Machek wrote:
>> From: Sakari Ailus <sakari.ailus-X3B1VOXEql0@public.gmane.org>
>>
>> In the vast majority of cases the bus type is known to the driver(s)
>> since a receiver or transmitter can only support a single one. There
>> are cases however where different options are possible.
>>
>> The existing V4L2 OF support tries to figure out the bus type and
>> parse the bus parameters based on that. This does not scale too well
>> as there are multiple serial busses that share common properties.
>>
>> Some hardware also supports multiple types of busses on the same
>> interfaces.
>>
>> Document the CSI1/CCP2 property strobe. It signifies the clock or
>> strobe mode.
>>
>> Signed-off-by: Sakari Ailus <sakari.ailus-X3B1VOXEql0@public.gmane.org>
>> Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> Signed-off-by: Pavel Machek <pavel-+ZI9xUNit7I@public.gmane.org>
>>
>> diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt
>> index 9cd2a36..08c4498 100644
>> --- a/Documentation/devicetree/bindings/media/video-interfaces.txt
>> +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt
>> @@ -76,6 +76,11 @@ Optional endpoint properties
>> mode horizontal and vertical synchronization signals are provided to the
>> slave device (data source) by the master device (data sink). In the master
>> mode the data source device is also the source of the synchronization signals.
>> +- bus-type: data bus type. Possible values are:
>> + 0 - MIPI CSI2
>> + 1 - parallel / Bt656
>> + 2 - MIPI CSI1
>> + 3 - CCP2
>
> Actually, thinking about this again --- we only need to explictly specify
> busses if we're dealing with either CCP2 or CSI-1. The vast majority of the
> actual busses are and continue to be CSI-2 or either parallel or Bt.656. As
> they can be implicitly detected, we would have an option to just drop values
> 0 and 1 from above, i.e. only leave CSI-1 and CCP2. For now, specifying
> CSI-2 or parallel / Bt.656 adds no value as the old DT binaries without
> bus-type will need to be supported anyway.
>
>> - bus-width: number of data lines actively used, valid for the parallel busses.
>> - data-shift: on the parallel data busses, if bus-width is used to specify the
>> number of data lines, data-shift can be used to specify which data lines are
>> @@ -112,7 +117,8 @@ Optional endpoint properties
>> should be the combined length of data-lanes and clock-lanes properties.
>> If the lane-polarities property is omitted, the value must be interpreted
>> as 0 (normal). This property is valid for serial busses only.
>> -
>> +- strobe: Whether the clock signal is used as clock or strobe. Used
>> + with CCP2, for instance.
>
> How about the "ti,strobe-clock-inv" I proposed? No-one seems to know what
> this really truly means... or just drop it if it's not really needed.
>
Not really :), see
https://www.spinics.net/lists/linux-media/msg99802.html and
https://www.spinics.net/lists/linux-media/msg99800.html
"clock/strobe", and "strobe-inv" are two distinct properties, see
CSI1B_CTRL description in OMAP TRM. BTW there is another property that
is needed for both n900 cameras to operate correctly (VP_CLK_POL, bit 12
from the same reg), but that can be added later on when we have the
other bits in place.
Ivo
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^ permalink raw reply
* Re: Re: [PATCH 1/4] phy: sun4i-usb: support PHY0 on H3 in MUSB mode
From: Hans de Goede @ 2017-01-20 8:04 UTC (permalink / raw)
To: Karsten Merker, Icenowy Zheng
Cc: Maxime Ripard, Chen-Yu Tsai, Rob Herring, Kishon Vijay Abraham I,
Greg Kroah-Hartman, Bin Liu,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
In-Reply-To: <20170119202709.GA1853-Hlt6eto4P0pdWf7zwHaZWbNAH6kLmebB@public.gmane.org>
HI,
On 19-01-17 21:27, Karsten Merker wrote:
> On Thu, Jan 19, 2017 at 11:10:08PM +0800, Icenowy Zheng wrote:
>> 19.01.2017, 22:34, "Maxime Ripard" <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>:
>>> On Wed, Jan 18, 2017 at 04:09:32AM +0800, Chen-Yu Tsai wrote:
>>>> On Wed, Jan 18, 2017 at 4:06 AM, Maxime Ripard
>>>> <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
>>>> > On Wed, Jan 18, 2017 at 12:57:08AM +0800, Icenowy Zheng wrote:
>>>> >> 17.01.2017, 16:06, "Maxime Ripard" <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>:
>>>> >> > On Tue, Jan 17, 2017 at 03:14:46AM +0800, Icenowy Zheng wrote:
>>>> >> >> The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
>>>> >> >> controller.
>>>> >> >>
>>>> >> >> The original driver wired it to OHCI/EHCI controller; however, as the
>>>> >> >> code to use PHY0 as OHCI/EHCI is missing, it makes the PHY fully
>>>> >> >> unusable.
>>>> >> >>
>>>> >> >> Rename the register (according to its function and the name in BSP
>>>> >> >> driver), and remove the code which wires the PHY0 to OHCI/EHCI, as MUSB
>>>> >> >> can support both peripheral and host mode (although the host mode of
>>>> >> >> MUSB is buggy).
>>>> >> >
>>>> >> > Can you elaborate on that? What's wrong with it?
>>>> >>
>>>> >> The configuration is at bit 0 of register 0x20 in PHY.
>>>> >>
>>>> >> When the PHY is reseted, it defaults as MUSB mode.
>>>> >>
>>>> >> However, the original author of the H3 PHY code seems to be lack of
>>>> >> this knowledge (He named it PHY_UNK_H3), and changed the PHY to HCI
>>>> >> mode.
>>>> >>
>>>> >> I just removed the code that wires it to HCI mode, thus it will work
>>>> >> in MUSB mode, with my sun8i-h3-musb patch.
>>>> >
>>>> > I have no idea what you mean by MUSB mode.
>>>> >
>>>> > Do you mean that the previous code was only working in host mode, and
>>>> > now it only works in peripheral?
>>>>
>>>> From what I understand, with the H3, Allwinner has put a mux
>>>> in front of the MUSB controller. The mux can send the USB data
>>>> to/from the MUSB controller, or a standard EHCI/OHCI pair.
>>>> This register controls said mux.
>>>>
>>>> This means we can use a proper USB host for host mode,
>>>> instead of the limited support in MUSB.
>>>
>>> But musb can still operate as a host, right?
>>
>> Yes!
>
> Hello,
>
> I don't know how the MUSB implementation in the H3 behaves as I
> don't have any H3-based systems, but if it should happen to be
> similar to the one in the A31s, it probably isn't a full-fledged
> alternative to using an OHCI/EHCI controller.
You right it isn't which is why I suggested that the phy-sun4i-usb
code should set the mux to the OCHI/EHCI pair when the id pin
is pulled low (host-mode).
> From my practical experiments with the MUSB in the A31s in host
> mode I can report that I hadn't been able to get multiple HIDs
> (in my case keyboard and mouse) working at the same time. The
> keyboard alone worked without problems, the mouse alone worked
> without problems, but when both were connected, only one of them
> worked.
>
> I had at that time talked to Hans de Goede about the problem and
> if I remenber correctly, he had mentioned that the MUSB has
> problems servicing more than one device that does interrupt
> transfers (as HIDs do).
>
> Hans, can you perhaps shed some light on this?
Everything you've said is correct, the MUSB can emulate a
host-controller, but it is not really one and when possible
should not be used as such.
Regards,
Hans
^ permalink raw reply
* Re: [PATCH 2/2] ARM: dts: rockchip: add dts for RK3288-Tinker board
From: Heiko Stuebner @ 2017-01-20 8:12 UTC (permalink / raw)
To: Eddie Cai
Cc: mark.rutland, devicetree, linux, linux-kernel, linux-rockchip,
robh+dt, Eddie Cai, linux-arm-kernel
In-Reply-To: <CAJrj+DM5hVsmB_q+P8WPd0z_F1cYcGafyYZHXdX6P=nrqxpFyA@mail.gmail.com>
Hi Eddie,
Am Freitag, 20. Januar 2017, 15:10:47 CET schrieb Eddie Cai:
> 2017-01-19 17:58 GMT+08:00 Heiko Stuebner <heiko@sntech.de>:
> > Hi Eddie,
> >
> > Am Donnerstag, 19. Januar 2017, 10:11:59 CET schrieb Eddie Cai:
> >> This patch add basic support for RK3288-Tinker board. We can boot in to
> >> rootfs with this patch.
> >>
> >> Signed-off-by: Eddie Cai <eddie.cai@rock-chips.com>
> >
> > looks good in general, just some small question down below.
> >
> > [...]
> >
> >> + /*
> >> + * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes
> >> from
> >> + * vcc_io directly. Those boards won't be able to power cycle SD
> >> cards + * but it shouldn't hurt to toggle this pin there anyway.
> >> + */
> >
> > just to clarify, later board will have that pin connected, right?
>
> Copy from rk3288-evb.dtsi. forgot to delete it. I will remove it in next
> version
> >> + vcc_sd: sdmmc-regulator {
> >> + compatible = "regulator-fixed";
> >> + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&sdmmc_pwr>;
> >> + regulator-name = "vcc_sd";
> >> + regulator-min-microvolt = <3300000>;
> >> + regulator-max-microvolt = <3300000>;
> >> + startup-delay-us = <100000>;
> >> + vin-supply = <&vcc_io>;
> >> + };
> >> +};
> >
> > [...]
> >
> >> +&hdmi {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + #sound-dai-cells = <0>;
> >> + ddc-i2c-bus = <&i2c5>;
> >> + status = "okay";
> >> + /* Don't use vopl for HDMI */
> >> + ports {
> >> + hdmi_in: port {
> >> + /delete-node/ endpoint@1;
> >> + };
> >
> > what is the reason for this? You enable both VOPs below and the linux
> > display subsystem should be able to select an appropriate VOP for output
> > just fine on its own. So there should be no reason for capping the hdmi's
> > connection to one of the vops.
>
> The VOP big support 4k display. is designed for HDMI 4K display. VOP
> little is for other display(eDP, LVDS, Mipi etc)
The hdmi _can_ talk to both vops, which is why it has the connection to both.
Resolution-limitations and selecting a matching vop should be handled in the
drm driver I'd think - but you'll need to talk to Mark Yao or some else
knowledgable in graphics.
The devicetree is about describing the _available_ hardware, not configuring
how it is supposed to be used ;-) .
Heiko
^ permalink raw reply
* [PATCH v2, 1/6] phy: phy-mt65xx-usb3: split SuperSpeed port into two ones
From: Chunfeng Yun @ 2017-01-20 8:18 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Matthias Brugger, Felipe Balbi, Rob Herring, Mark Rutland,
Ian Campbell, Chunfeng Yun, linux-kernel, linux-arm-kernel,
linux-usb, linux-mediatek, devicetree
Currently usb3 port in fact includes two sub-ports, but it is not
flexible for some cases, such as following one:
usb3 port0 includes u2port0 and u3port0;
usb2 port0 includes u2port1;
If wants to support only HS, we can use u2port0 or u2port1, when
select u2port0, u3port0 is not needed;
If wants to support SS, we can compound u2port0 and u3port0,
or u2port1 and u3port0, if select latter one, u2port0 is not needed.
So it's more flexible to split usb3 port into two ones and also try
best to save power by disabling unnecessary ports.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/phy-mt65xx-usb3.c | 119 +++++++++++++++++++++--------------------
1 file changed, 60 insertions(+), 59 deletions(-)
diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
index d972067..93f57d9 100644
--- a/drivers/phy/phy-mt65xx-usb3.c
+++ b/drivers/phy/phy-mt65xx-usb3.c
@@ -30,11 +30,11 @@
#define SSUSB_SIFSLV_SPLLC 0x0000
#define SSUSB_SIFSLV_U2FREQ 0x0100
-/* offsets of sub-segment in each port registers */
+/* offsets of banks in each u2phy registers */
#define SSUSB_SIFSLV_U2PHY_COM_BASE 0x0000
-#define SSUSB_SIFSLV_U3PHYD_BASE 0x0100
-#define SSUSB_USB30_PHYA_SIV_B_BASE 0x0300
-#define SSUSB_SIFSLV_U3PHYA_DA_BASE 0x0400
+/* offsets of banks in each u3phy registers */
+#define SSUSB_SIFSLV_U3PHYD_BASE 0x0000
+#define SSUSB_SIFSLV_U3PHYA_BASE 0x0200
#define U3P_USBPHYACR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0000)
#define PA0_RG_U2PLL_FORCE_ON BIT(15)
@@ -49,7 +49,6 @@
#define PA5_RG_U2_HS_100U_U3_EN BIT(11)
#define U3P_USBPHYACR6 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0018)
-#define PA6_RG_U2_ISO_EN BIT(31)
#define PA6_RG_U2_BC11_SW_EN BIT(23)
#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
#define PA6_RG_U2_SQTH GENMASK(3, 0)
@@ -91,18 +90,18 @@
#define P2C_RG_SESSEND BIT(4)
#define P2C_RG_AVALID BIT(2)
-#define U3P_U3_PHYA_REG0 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0000)
+#define U3P_U3_PHYA_REG0 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0000)
#define P3A_RG_U3_VUSB10_ON BIT(5)
-#define U3P_U3_PHYA_REG6 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0018)
+#define U3P_U3_PHYA_REG6 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0018)
#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
-#define U3P_U3_PHYA_REG9 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0024)
+#define U3P_U3_PHYA_REG9 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0024)
#define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
-#define U3P_U3PHYA_DA_REG0 (SSUSB_SIFSLV_U3PHYA_DA_BASE + 0x0000)
+#define U3P_U3PHYA_DA_REG0 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0100)
#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
@@ -148,7 +147,7 @@ struct mt65xx_phy_instance {
struct mt65xx_u3phy {
struct device *dev;
- void __iomem *sif_base; /* include sif2, but exclude port's */
+ void __iomem *sif_base; /* only shared sif */
struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
const struct mt65xx_phy_pdata *pdata;
struct mt65xx_phy_instance **phys;
@@ -178,7 +177,7 @@ static void hs_slew_rate_calibrate(struct mt65xx_u3phy *u3phy,
tmp = readl(sif_base + U3P_U2FREQ_FMCR0);
tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
- tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index);
+ tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
writel(tmp, sif_base + U3P_U2FREQ_FMCR0);
/* enable frequency meter */
@@ -226,6 +225,41 @@ static void hs_slew_rate_calibrate(struct mt65xx_u3phy *u3phy,
writel(tmp, instance->port_base + U3P_USBPHYACR5);
}
+static void u3_phy_instance_init(struct mt65xx_u3phy *u3phy,
+ struct mt65xx_phy_instance *instance)
+{
+ void __iomem *port_base = instance->port_base;
+ u32 tmp;
+
+ /* gating PCIe Analog XTAL clock */
+ tmp = readl(u3phy->sif_base + U3P_XTALCTL3);
+ tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
+ writel(tmp, u3phy->sif_base + U3P_XTALCTL3);
+
+ /* gating XSQ */
+ tmp = readl(port_base + U3P_U3PHYA_DA_REG0);
+ tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
+ tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
+ writel(tmp, port_base + U3P_U3PHYA_DA_REG0);
+
+ tmp = readl(port_base + U3P_U3_PHYA_REG9);
+ tmp &= ~P3A_RG_RX_DAC_MUX;
+ tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
+ writel(tmp, port_base + U3P_U3_PHYA_REG9);
+
+ tmp = readl(port_base + U3P_U3_PHYA_REG6);
+ tmp &= ~P3A_RG_TX_EIDLE_CM;
+ tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
+ writel(tmp, port_base + U3P_U3_PHYA_REG6);
+
+ tmp = readl(port_base + U3P_PHYD_CDR1);
+ tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
+ tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
+ writel(tmp, port_base + U3P_PHYD_CDR1);
+
+ dev_dbg(u3phy->dev, "%s(%d)\n", __func__, instance->index);
+}
+
static void phy_instance_init(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
@@ -275,26 +309,6 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy,
tmp |= PA6_RG_U2_SQTH_VAL(2);
writel(tmp, port_base + U3P_USBPHYACR6);
- tmp = readl(port_base + U3P_U3PHYA_DA_REG0);
- tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
- tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
- writel(tmp, port_base + U3P_U3PHYA_DA_REG0);
-
- tmp = readl(port_base + U3P_U3_PHYA_REG9);
- tmp &= ~P3A_RG_RX_DAC_MUX;
- tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
- writel(tmp, port_base + U3P_U3_PHYA_REG9);
-
- tmp = readl(port_base + U3P_U3_PHYA_REG6);
- tmp &= ~P3A_RG_TX_EIDLE_CM;
- tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
- writel(tmp, port_base + U3P_U3_PHYA_REG6);
-
- tmp = readl(port_base + U3P_PHYD_CDR1);
- tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
- tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
- writel(tmp, port_base + U3P_PHYD_CDR1);
-
dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
}
@@ -305,13 +319,6 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
u32 index = instance->index;
u32 tmp;
- if (!index) {
- /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
- tmp = readl(port_base + U3P_U3_PHYA_REG0);
- tmp |= P3A_RG_U3_VUSB10_ON;
- writel(tmp, port_base + U3P_U3_PHYA_REG0);
- }
-
/* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */
tmp = readl(port_base + U3P_U2PHYDTM0);
tmp &= ~(P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL);
@@ -324,10 +331,6 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
writel(tmp, port_base + U3P_USBPHYACR6);
if (!index) {
- tmp = readl(u3phy->sif_base + U3P_XTALCTL3);
- tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
- writel(tmp, u3phy->sif_base + U3P_XTALCTL3);
-
/* switch 100uA current to SSUSB */
tmp = readl(port_base + U3P_USBPHYACR5);
tmp |= PA5_RG_U2_HS_100U_U3_EN;
@@ -339,12 +342,6 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
tmp &= ~P2C_RG_SESSEND;
writel(tmp, port_base + U3P_U2PHYDTM1);
- /* USB 2.0 slew rate calibration */
- tmp = readl(port_base + U3P_USBPHYACR5);
- tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
- tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(4);
- writel(tmp, port_base + U3P_USBPHYACR5);
-
if (u3phy->pdata->avoid_rx_sen_degradation && index) {
tmp = readl(port_base + U3D_U2PHYDCR0);
tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
@@ -392,12 +389,6 @@ static void phy_instance_power_off(struct mt65xx_u3phy *u3phy,
tmp |= P2C_RG_SESSEND;
writel(tmp, port_base + U3P_U2PHYDTM1);
- if (!index) {
- tmp = readl(port_base + U3P_U3_PHYA_REG0);
- tmp &= ~P3A_RG_U3_VUSB10_ON;
- writel(tmp, port_base + U3P_U3_PHYA_REG0);
- }
-
if (u3phy->pdata->avoid_rx_sen_degradation && index) {
tmp = readl(port_base + U3D_U2PHYDCR0);
tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
@@ -437,7 +428,11 @@ static int mt65xx_phy_init(struct phy *phy)
return ret;
}
- phy_instance_init(u3phy, instance);
+ if (instance->type == PHY_TYPE_USB2)
+ phy_instance_init(u3phy, instance);
+ else
+ u3_phy_instance_init(u3phy, instance);
+
return 0;
}
@@ -446,8 +441,10 @@ static int mt65xx_phy_power_on(struct phy *phy)
struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
- phy_instance_power_on(u3phy, instance);
- hs_slew_rate_calibrate(u3phy, instance);
+ if (instance->type == PHY_TYPE_USB2) {
+ phy_instance_power_on(u3phy, instance);
+ hs_slew_rate_calibrate(u3phy, instance);
+ }
return 0;
}
@@ -456,7 +453,9 @@ static int mt65xx_phy_power_off(struct phy *phy)
struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
- phy_instance_power_off(u3phy, instance);
+ if (instance->type == PHY_TYPE_USB2)
+ phy_instance_power_off(u3phy, instance);
+
return 0;
}
@@ -465,7 +464,9 @@ static int mt65xx_phy_exit(struct phy *phy)
struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
- phy_instance_exit(u3phy, instance);
+ if (instance->type == PHY_TYPE_USB2)
+ phy_instance_exit(u3phy, instance);
+
clk_disable_unprepare(u3phy->u3phya_ref);
return 0;
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2, 2/6] phy: phy-mt65xx-usb3: move clock from phy node into port nodes
From: Chunfeng Yun @ 2017-01-20 8:18 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Mark Rutland, devicetree, Felipe Balbi, Ian Campbell, linux-usb,
linux-kernel, Chunfeng Yun, Rob Herring, linux-mediatek,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <1484900321-26933-1-git-send-email-chunfeng.yun@mediatek.com>
the reference clock of HighSpeed port is 48M which comes from PLL;
the reference clock of SuperSpeed port is 26M which usually comes
from 26M oscillator directly, but some SoCs are not, add it for
compatibility, and put them into port node for flexibility.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/phy-mt65xx-usb3.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
index 93f57d9..0995433 100644
--- a/drivers/phy/phy-mt65xx-usb3.c
+++ b/drivers/phy/phy-mt65xx-usb3.c
@@ -141,6 +141,7 @@ struct mt65xx_phy_pdata {
struct mt65xx_phy_instance {
struct phy *phy;
void __iomem *port_base;
+ struct clk *ref_clk; /* reference clock of anolog phy */
u32 index;
u8 type;
};
@@ -148,7 +149,6 @@ struct mt65xx_phy_instance {
struct mt65xx_u3phy {
struct device *dev;
void __iomem *sif_base; /* only shared sif */
- struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
const struct mt65xx_phy_pdata *pdata;
struct mt65xx_phy_instance **phys;
int nphys;
@@ -422,9 +422,9 @@ static int mt65xx_phy_init(struct phy *phy)
struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
int ret;
- ret = clk_prepare_enable(u3phy->u3phya_ref);
+ ret = clk_prepare_enable(instance->ref_clk);
if (ret) {
- dev_err(u3phy->dev, "failed to enable u3phya_ref\n");
+ dev_err(u3phy->dev, "failed to enable ref_clk\n");
return ret;
}
@@ -467,7 +467,7 @@ static int mt65xx_phy_exit(struct phy *phy)
if (instance->type == PHY_TYPE_USB2)
phy_instance_exit(u3phy, instance);
- clk_disable_unprepare(u3phy->u3phya_ref);
+ clk_disable_unprepare(instance->ref_clk);
return 0;
}
@@ -567,12 +567,6 @@ static int mt65xx_u3phy_probe(struct platform_device *pdev)
return PTR_ERR(u3phy->sif_base);
}
- u3phy->u3phya_ref = devm_clk_get(dev, "u3phya_ref");
- if (IS_ERR(u3phy->u3phya_ref)) {
- dev_err(dev, "error to get u3phya_ref\n");
- return PTR_ERR(u3phy->u3phya_ref);
- }
-
port = 0;
for_each_child_of_node(np, child_np) {
struct mt65xx_phy_instance *instance;
@@ -607,6 +601,13 @@ static int mt65xx_u3phy_probe(struct platform_device *pdev)
goto put_child;
}
+ instance->ref_clk = devm_clk_get(&phy->dev, "ref_clk");
+ if (IS_ERR(instance->ref_clk)) {
+ dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
+ retval = PTR_ERR(instance->ref_clk);
+ goto put_child;
+ }
+
instance->phy = phy;
instance->index = port;
phy_set_drvdata(phy, instance);
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2, 3/6] phy: phy-mt65xx-usb3: add support for new version phy
From: Chunfeng Yun @ 2017-01-20 8:18 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Felipe Balbi,
Ian Campbell, linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Chunfeng Yun, Rob Herring,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Matthias Brugger,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1484900321-26933-1-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
There are some variations from mt2701 to mt2712:
1. banks shared by multiple ports are put back into each port,
such as SPLLC and U2FREQ;
2. add a new bank MISC for u2port, and CHIP for u3port;
3. bank's offset in each port are also rearranged;
Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/phy/phy-mt65xx-usb3.c | 326 ++++++++++++++++++++++++++---------------
1 file changed, 208 insertions(+), 118 deletions(-)
diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
index 0995433..462e02b 100644
--- a/drivers/phy/phy-mt65xx-usb3.c
+++ b/drivers/phy/phy-mt65xx-usb3.c
@@ -23,46 +23,54 @@
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
-/*
- * for sifslv2 register, but exclude port's;
- * relative to USB3_SIF2_BASE base address
- */
-#define SSUSB_SIFSLV_SPLLC 0x0000
-#define SSUSB_SIFSLV_U2FREQ 0x0100
-
-/* offsets of banks in each u2phy registers */
-#define SSUSB_SIFSLV_U2PHY_COM_BASE 0x0000
-/* offsets of banks in each u3phy registers */
-#define SSUSB_SIFSLV_U3PHYD_BASE 0x0000
-#define SSUSB_SIFSLV_U3PHYA_BASE 0x0200
-
-#define U3P_USBPHYACR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0000)
+/* version V1 sub-banks offset base address */
+/* banks shared by multiple phys */
+#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
+#define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
+/* u2 phy bank */
+#define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
+/* u3 phy banks */
+#define SSUSB_SIFSLV_V1_U3PHYD 0x000
+#define SSUSB_SIFSLV_V1_U3PHYA 0x200
+
+/* version V2 sub-banks offset base address */
+/* u2 phy banks */
+#define SSUSB_SIFSLV_V2_MISC 0x000
+#define SSUSB_SIFSLV_V2_U2FREQ 0x100
+#define SSUSB_SIFSLV_V2_U2PHY_COM 0x300
+/* u3 phy banks */
+#define SSUSB_SIFSLV_V2_SPLLC 0x000
+#define SSUSB_SIFSLV_V2_CHIP 0x100
+#define SSUSB_SIFSLV_V2_U3PHYD 0x200
+#define SSUSB_SIFSLV_V2_U3PHYA 0x400
+
+#define U3P_USBPHYACR0 0x000
#define PA0_RG_U2PLL_FORCE_ON BIT(15)
-#define U3P_USBPHYACR2 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0008)
+#define U3P_USBPHYACR2 0x008
#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
-#define U3P_USBPHYACR5 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0014)
+#define U3P_USBPHYACR5 0x014
#define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
#define PA5_RG_U2_HS_100U_U3_EN BIT(11)
-#define U3P_USBPHYACR6 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0018)
+#define U3P_USBPHYACR6 0x018
#define PA6_RG_U2_BC11_SW_EN BIT(23)
#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
#define PA6_RG_U2_SQTH GENMASK(3, 0)
#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
-#define U3P_U2PHYACR4 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0020)
+#define U3P_U2PHYACR4 0x020
#define P2C_RG_USB20_GPIO_CTL BIT(9)
#define P2C_USB20_GPIO_MODE BIT(8)
#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
-#define U3D_U2PHYDCR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0060)
+#define U3D_U2PHYDCR0 0x060
#define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24)
-#define U3P_U2PHYDTM0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0068)
+#define U3P_U2PHYDTM0 0x068
#define P2C_FORCE_UART_EN BIT(26)
#define P2C_FORCE_DATAIN BIT(23)
#define P2C_FORCE_DM_PULLDOWN BIT(21)
@@ -84,47 +92,44 @@
P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
-#define U3P_U2PHYDTM1 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x006C)
+#define U3P_U2PHYDTM1 0x06C
#define P2C_RG_UART_EN BIT(16)
#define P2C_RG_VBUSVALID BIT(5)
#define P2C_RG_SESSEND BIT(4)
#define P2C_RG_AVALID BIT(2)
-#define U3P_U3_PHYA_REG0 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0000)
-#define P3A_RG_U3_VUSB10_ON BIT(5)
-
-#define U3P_U3_PHYA_REG6 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0018)
+#define U3P_U3_PHYA_REG6 0x018
#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
-#define U3P_U3_PHYA_REG9 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0024)
+#define U3P_U3_PHYA_REG9 0x024
#define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
-#define U3P_U3PHYA_DA_REG0 (SSUSB_SIFSLV_U3PHYA_BASE + 0x0100)
+#define U3P_U3_PHYA_DA_REG0 0x100
#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
-#define U3P_PHYD_CDR1 (SSUSB_SIFSLV_U3PHYD_BASE + 0x005c)
+#define U3P_U3_PHYD_CDR1 0x05c
#define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
#define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
-#define U3P_XTALCTL3 (SSUSB_SIFSLV_SPLLC + 0x0018)
+#define U3P_SPLLC_XTALCTL3 0x018
#define XC3_RG_U3_XTAL_RX_PWD BIT(9)
#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
-#define U3P_U2FREQ_FMCR0 (SSUSB_SIFSLV_U2FREQ + 0x00)
+#define U3P_U2FREQ_FMCR0 0x00
#define P2F_RG_MONCLK_SEL GENMASK(27, 26)
#define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26)
#define P2F_RG_FREQDET_EN BIT(24)
#define P2F_RG_CYCLECNT GENMASK(23, 0)
#define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
-#define U3P_U2FREQ_VALUE (SSUSB_SIFSLV_U2FREQ + 0x0c)
+#define U3P_U2FREQ_VALUE 0x0c
-#define U3P_U2FREQ_FMMONR1 (SSUSB_SIFSLV_U2FREQ + 0x10)
+#define U3P_U2FREQ_FMMONR1 0x10
#define P2F_USB_FM_VALID BIT(0)
#define P2F_RG_FRCK_EN BIT(8)
@@ -133,14 +138,37 @@
#define U3P_SR_COEF_DIVISOR 1000
#define U3P_FM_DET_CYCLE_CNT 1024
+enum mt_phy_version {
+ MT_PHY_V1 = 1,
+ MT_PHY_V2,
+};
+
struct mt65xx_phy_pdata {
/* avoid RX sensitivity level degradation only for mt8173 */
bool avoid_rx_sen_degradation;
+ enum mt_phy_version version;
+};
+
+struct u2phy_banks {
+ void __iomem *misc;
+ void __iomem *fmreg;
+ void __iomem *com;
+};
+
+struct u3phy_banks {
+ void __iomem *spllc;
+ void __iomem *chip;
+ void __iomem *phyd; /* include u3phyd_bank2 */
+ void __iomem *phya; /* include u3phya_da */
};
struct mt65xx_phy_instance {
struct phy *phy;
void __iomem *port_base;
+ union {
+ struct u2phy_banks u2_banks;
+ struct u3phy_banks u3_banks;
+ };
struct clk *ref_clk; /* reference clock of anolog phy */
u32 index;
u8 type;
@@ -157,49 +185,53 @@ struct mt65xx_u3phy {
static void hs_slew_rate_calibrate(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
- void __iomem *sif_base = u3phy->sif_base;
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *fmreg = u2_banks->fmreg;
+ void __iomem *com = u2_banks->com;
int calibration_val;
int fm_out;
u32 tmp;
/* enable USB ring oscillator */
- tmp = readl(instance->port_base + U3P_USBPHYACR5);
+ tmp = readl(com + U3P_USBPHYACR5);
tmp |= PA5_RG_U2_HSTX_SRCAL_EN;
- writel(tmp, instance->port_base + U3P_USBPHYACR5);
+ writel(tmp, com + U3P_USBPHYACR5);
udelay(1);
/*enable free run clock */
- tmp = readl(sif_base + U3P_U2FREQ_FMMONR1);
+ tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
tmp |= P2F_RG_FRCK_EN;
- writel(tmp, sif_base + U3P_U2FREQ_FMMONR1);
+ writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
/* set cycle count as 1024, and select u2 channel */
- tmp = readl(sif_base + U3P_U2FREQ_FMCR0);
+ tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
- tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
- writel(tmp, sif_base + U3P_U2FREQ_FMCR0);
+ if (u3phy->pdata->version == MT_PHY_V1)
+ tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
+
+ writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
/* enable frequency meter */
- tmp = readl(sif_base + U3P_U2FREQ_FMCR0);
+ tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
tmp |= P2F_RG_FREQDET_EN;
- writel(tmp, sif_base + U3P_U2FREQ_FMCR0);
+ writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
/* ignore return value */
- readl_poll_timeout(sif_base + U3P_U2FREQ_FMMONR1, tmp,
+ readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp,
(tmp & P2F_USB_FM_VALID), 10, 200);
- fm_out = readl(sif_base + U3P_U2FREQ_VALUE);
+ fm_out = readl(fmreg + U3P_U2FREQ_VALUE);
/* disable frequency meter */
- tmp = readl(sif_base + U3P_U2FREQ_FMCR0);
+ tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
tmp &= ~P2F_RG_FREQDET_EN;
- writel(tmp, sif_base + U3P_U2FREQ_FMCR0);
+ writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
/*disable free run clock */
- tmp = readl(sif_base + U3P_U2FREQ_FMMONR1);
+ tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
tmp &= ~P2F_RG_FRCK_EN;
- writel(tmp, sif_base + U3P_U2FREQ_FMMONR1);
+ writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
if (fm_out) {
/* ( 1024 / FM_OUT ) x reference clock frequency x 0.028 */
@@ -214,48 +246,48 @@ static void hs_slew_rate_calibrate(struct mt65xx_u3phy *u3phy,
instance->index, fm_out, calibration_val);
/* set HS slew rate */
- tmp = readl(instance->port_base + U3P_USBPHYACR5);
+ tmp = readl(com + U3P_USBPHYACR5);
tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val);
- writel(tmp, instance->port_base + U3P_USBPHYACR5);
+ writel(tmp, com + U3P_USBPHYACR5);
/* disable USB ring oscillator */
- tmp = readl(instance->port_base + U3P_USBPHYACR5);
+ tmp = readl(com + U3P_USBPHYACR5);
tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN;
- writel(tmp, instance->port_base + U3P_USBPHYACR5);
+ writel(tmp, com + U3P_USBPHYACR5);
}
static void u3_phy_instance_init(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
- void __iomem *port_base = instance->port_base;
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
u32 tmp;
/* gating PCIe Analog XTAL clock */
- tmp = readl(u3phy->sif_base + U3P_XTALCTL3);
+ tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3);
tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
- writel(tmp, u3phy->sif_base + U3P_XTALCTL3);
+ writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3);
/* gating XSQ */
- tmp = readl(port_base + U3P_U3PHYA_DA_REG0);
+ tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
- writel(tmp, port_base + U3P_U3PHYA_DA_REG0);
+ writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
- tmp = readl(port_base + U3P_U3_PHYA_REG9);
+ tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9);
tmp &= ~P3A_RG_RX_DAC_MUX;
tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
- writel(tmp, port_base + U3P_U3_PHYA_REG9);
+ writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9);
- tmp = readl(port_base + U3P_U3_PHYA_REG6);
+ tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6);
tmp &= ~P3A_RG_TX_EIDLE_CM;
tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
- writel(tmp, port_base + U3P_U3_PHYA_REG6);
+ writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6);
- tmp = readl(port_base + U3P_PHYD_CDR1);
+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1);
tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
- writel(tmp, port_base + U3P_PHYD_CDR1);
+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1);
dev_dbg(u3phy->dev, "%s(%d)\n", __func__, instance->index);
}
@@ -263,51 +295,52 @@ static void u3_phy_instance_init(struct mt65xx_u3phy *u3phy,
static void phy_instance_init(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
- void __iomem *port_base = instance->port_base;
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *com = u2_banks->com;
u32 index = instance->index;
u32 tmp;
/* switch to USB function. (system register, force ip into usb mode) */
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp &= ~P2C_FORCE_UART_EN;
tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0);
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
- tmp = readl(port_base + U3P_U2PHYDTM1);
+ tmp = readl(com + U3P_U2PHYDTM1);
tmp &= ~P2C_RG_UART_EN;
- writel(tmp, port_base + U3P_U2PHYDTM1);
+ writel(tmp, com + U3P_U2PHYDTM1);
if (!index) {
- tmp = readl(port_base + U3P_U2PHYACR4);
+ tmp = readl(com + U3P_U2PHYACR4);
tmp &= ~P2C_U2_GPIO_CTR_MSK;
- writel(tmp, port_base + U3P_U2PHYACR4);
+ writel(tmp, com + U3P_U2PHYACR4);
}
if (u3phy->pdata->avoid_rx_sen_degradation) {
if (!index) {
- tmp = readl(port_base + U3P_USBPHYACR2);
+ tmp = readl(com + U3P_USBPHYACR2);
tmp |= PA2_RG_SIF_U2PLL_FORCE_EN;
- writel(tmp, port_base + U3P_USBPHYACR2);
+ writel(tmp, com + U3P_USBPHYACR2);
- tmp = readl(port_base + U3D_U2PHYDCR0);
+ tmp = readl(com + U3D_U2PHYDCR0);
tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
- writel(tmp, port_base + U3D_U2PHYDCR0);
+ writel(tmp, com + U3D_U2PHYDCR0);
} else {
- tmp = readl(port_base + U3D_U2PHYDCR0);
+ tmp = readl(com + U3D_U2PHYDCR0);
tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
- writel(tmp, port_base + U3D_U2PHYDCR0);
+ writel(tmp, com + U3D_U2PHYDCR0);
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
}
}
- tmp = readl(port_base + U3P_USBPHYACR6);
+ tmp = readl(com + U3P_USBPHYACR6);
tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */
tmp &= ~PA6_RG_U2_SQTH;
tmp |= PA6_RG_U2_SQTH_VAL(2);
- writel(tmp, port_base + U3P_USBPHYACR6);
+ writel(tmp, com + U3P_USBPHYACR6);
dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
}
@@ -315,41 +348,42 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy,
static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
- void __iomem *port_base = instance->port_base;
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *com = u2_banks->com;
u32 index = instance->index;
u32 tmp;
/* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp &= ~(P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL);
tmp &= ~(P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
/* OTG Enable */
- tmp = readl(port_base + U3P_USBPHYACR6);
+ tmp = readl(com + U3P_USBPHYACR6);
tmp |= PA6_RG_U2_OTG_VBUSCMP_EN;
- writel(tmp, port_base + U3P_USBPHYACR6);
+ writel(tmp, com + U3P_USBPHYACR6);
if (!index) {
/* switch 100uA current to SSUSB */
- tmp = readl(port_base + U3P_USBPHYACR5);
+ tmp = readl(com + U3P_USBPHYACR5);
tmp |= PA5_RG_U2_HS_100U_U3_EN;
- writel(tmp, port_base + U3P_USBPHYACR5);
+ writel(tmp, com + U3P_USBPHYACR5);
}
- tmp = readl(port_base + U3P_U2PHYDTM1);
+ tmp = readl(com + U3P_U2PHYDTM1);
tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID;
tmp &= ~P2C_RG_SESSEND;
- writel(tmp, port_base + U3P_U2PHYDTM1);
+ writel(tmp, com + U3P_U2PHYDTM1);
if (u3phy->pdata->avoid_rx_sen_degradation && index) {
- tmp = readl(port_base + U3D_U2PHYDCR0);
+ tmp = readl(com + U3D_U2PHYDCR0);
tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
- writel(tmp, port_base + U3D_U2PHYDCR0);
+ writel(tmp, com + U3D_U2PHYDCR0);
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
}
dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
}
@@ -357,42 +391,43 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
static void phy_instance_power_off(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
- void __iomem *port_base = instance->port_base;
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *com = u2_banks->com;
u32 index = instance->index;
u32 tmp;
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN);
tmp |= P2C_FORCE_SUSPENDM;
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
/* OTG Disable */
- tmp = readl(port_base + U3P_USBPHYACR6);
+ tmp = readl(com + U3P_USBPHYACR6);
tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN;
- writel(tmp, port_base + U3P_USBPHYACR6);
+ writel(tmp, com + U3P_USBPHYACR6);
if (!index) {
/* switch 100uA current back to USB2.0 */
- tmp = readl(port_base + U3P_USBPHYACR5);
+ tmp = readl(com + U3P_USBPHYACR5);
tmp &= ~PA5_RG_U2_HS_100U_U3_EN;
- writel(tmp, port_base + U3P_USBPHYACR5);
+ writel(tmp, com + U3P_USBPHYACR5);
}
/* let suspendm=0, set utmi into analog power down */
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp &= ~P2C_RG_SUSPENDM;
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
udelay(1);
- tmp = readl(port_base + U3P_U2PHYDTM1);
+ tmp = readl(com + U3P_U2PHYDTM1);
tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID);
tmp |= P2C_RG_SESSEND;
- writel(tmp, port_base + U3P_U2PHYDTM1);
+ writel(tmp, com + U3P_U2PHYDTM1);
if (u3phy->pdata->avoid_rx_sen_degradation && index) {
- tmp = readl(port_base + U3D_U2PHYDCR0);
+ tmp = readl(com + U3D_U2PHYDCR0);
tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
- writel(tmp, port_base + U3D_U2PHYDCR0);
+ writel(tmp, com + U3D_U2PHYDCR0);
}
dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
@@ -401,18 +436,55 @@ static void phy_instance_power_off(struct mt65xx_u3phy *u3phy,
static void phy_instance_exit(struct mt65xx_u3phy *u3phy,
struct mt65xx_phy_instance *instance)
{
- void __iomem *port_base = instance->port_base;
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *com = u2_banks->com;
u32 index = instance->index;
u32 tmp;
if (u3phy->pdata->avoid_rx_sen_degradation && index) {
- tmp = readl(port_base + U3D_U2PHYDCR0);
+ tmp = readl(com + U3D_U2PHYDCR0);
tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
- writel(tmp, port_base + U3D_U2PHYDCR0);
+ writel(tmp, com + U3D_U2PHYDCR0);
- tmp = readl(port_base + U3P_U2PHYDTM0);
+ tmp = readl(com + U3P_U2PHYDTM0);
tmp &= ~P2C_FORCE_SUSPENDM;
- writel(tmp, port_base + U3P_U2PHYDTM0);
+ writel(tmp, com + U3P_U2PHYDTM0);
+ }
+}
+
+static void phy_v1_banks_init(struct mt65xx_u3phy *u3phy,
+ struct mt65xx_phy_instance *instance)
+{
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
+
+ if (instance->type == PHY_TYPE_USB2) {
+ u2_banks->misc = NULL;
+ u2_banks->fmreg = u3phy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
+ u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
+ } else if (instance->type == PHY_TYPE_USB3) {
+ u3_banks->spllc = u3phy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
+ u3_banks->chip = NULL;
+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
+ }
+}
+
+static void phy_v2_banks_init(struct mt65xx_u3phy *u3phy,
+ struct mt65xx_phy_instance *instance)
+{
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
+
+ if (instance->type == PHY_TYPE_USB2) {
+ u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
+ u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
+ u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
+ } else if (instance->type == PHY_TYPE_USB3) {
+ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
+ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
}
}
@@ -479,7 +551,6 @@ static struct phy *mt65xx_phy_xlate(struct device *dev,
struct device_node *phy_np = args->np;
int index;
-
if (args->args_count != 1) {
dev_err(dev, "invalid number of cells in 'phy' property\n");
return ERR_PTR(-EINVAL);
@@ -497,13 +568,21 @@ static struct phy *mt65xx_phy_xlate(struct device *dev,
}
instance->type = args->args[0];
-
if (!(instance->type == PHY_TYPE_USB2 ||
instance->type == PHY_TYPE_USB3)) {
dev_err(dev, "unsupported device type: %d\n", instance->type);
return ERR_PTR(-EINVAL);
}
+ if (u3phy->pdata->version == MT_PHY_V1) {
+ phy_v1_banks_init(u3phy, instance);
+ } else if (u3phy->pdata->version == MT_PHY_V2) {
+ phy_v2_banks_init(u3phy, instance);
+ } else {
+ dev_err(dev, "phy version is not supported\n");
+ return ERR_PTR(-EINVAL);
+ }
+
return instance->phy;
}
@@ -517,14 +596,22 @@ static struct phy *mt65xx_phy_xlate(struct device *dev,
static const struct mt65xx_phy_pdata mt2701_pdata = {
.avoid_rx_sen_degradation = false,
+ .version = MT_PHY_V1,
+};
+
+static const struct mt65xx_phy_pdata mt2712_pdata = {
+ .avoid_rx_sen_degradation = false,
+ .version = MT_PHY_V2,
};
static const struct mt65xx_phy_pdata mt8173_pdata = {
.avoid_rx_sen_degradation = true,
+ .version = MT_PHY_V1,
};
static const struct of_device_id mt65xx_u3phy_id_table[] = {
{ .compatible = "mediatek,mt2701-u3phy", .data = &mt2701_pdata },
+ { .compatible = "mediatek,mt2712-u3phy", .data = &mt2712_pdata },
{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
{ },
};
@@ -560,11 +647,14 @@ static int mt65xx_u3phy_probe(struct platform_device *pdev)
u3phy->dev = dev;
platform_set_drvdata(pdev, u3phy);
- sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- u3phy->sif_base = devm_ioremap_resource(dev, sif_res);
- if (IS_ERR(u3phy->sif_base)) {
- dev_err(dev, "failed to remap sif regs\n");
- return PTR_ERR(u3phy->sif_base);
+ if (u3phy->pdata->version == MT_PHY_V1) {
+ /* get banks shared by multiple phys */
+ sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ u3phy->sif_base = devm_ioremap_resource(dev, sif_res);
+ if (IS_ERR(u3phy->sif_base)) {
+ dev_err(dev, "failed to remap sif regs\n");
+ return PTR_ERR(u3phy->sif_base);
+ }
}
port = 0;
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2, 4/6] arm64: dts: mt8173: split usb SuperSpeed port into two ports
From: Chunfeng Yun @ 2017-01-20 8:18 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Matthias Brugger, Felipe Balbi, Rob Herring, Mark Rutland,
Ian Campbell, Chunfeng Yun, linux-kernel, linux-arm-kernel,
linux-usb, linux-mediatek, devicetree
In-Reply-To: <1484900321-26933-1-git-send-email-chunfeng.yun@mediatek.com>
split the old SuperSpeed port node into a HighSpeed one and a new
SuperSpeed one.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 12e7027..1074ed2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -724,8 +724,9 @@
<0 0x11280700 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
- phys = <&phy_port0 PHY_TYPE_USB3>,
- <&phy_port1 PHY_TYPE_USB2>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
clocks = <&topckgen CLK_TOP_USB30_SEL>,
<&pericfg CLK_PERI_USB0>,
@@ -761,14 +762,20 @@
ranges;
status = "okay";
- phy_port0: port@11290800 {
- reg = <0 0x11290800 0 0x800>;
+ u2port0: port@11290800 {
+ reg = <0 0x11290800 0 0x100>;
#phy-cells = <1>;
status = "okay";
};
- phy_port1: port@11291000 {
- reg = <0 0x11291000 0 0x800>;
+ u3port0: port@11290900 {
+ reg = <0 0x11290900 0 0x700>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u2port1: port@11291000 {
+ reg = <0 0x11291000 0 0x100>;
#phy-cells = <1>;
status = "okay";
};
--
1.7.9.5
^ permalink raw reply related
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