* [PATCH 07/18] ARM64: dts: meson-gxl-s905x: Comment typo fix
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Neil Armstrong, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, devicetree
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
index 08237ee1e362..d49ee3c04dd7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
@@ -47,7 +47,7 @@
compatible = "amlogic,s905x", "amlogic,meson-gxl";
};
-/* S905X Only has access to its internal PHY */
+/* S905X only has access to its internal PHY */
ðmac {
phy-mode = "rmii";
phy-handle = <&internal_phy>;
--
2.10.2
^ permalink raw reply related
* [PATCH 08/18] ARM64: dts: meson-gxm: Drop trailing white line
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Carlo Caione, Kevin Hilman,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andreas Färber,
Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170120222118.21476-1-afaerber-l3A5Bk7waGM@public.gmane.org>
Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
---
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
index 4c55665a253f..78a004d13236 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
@@ -125,4 +125,3 @@
&vpu {
compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu";
};
-
--
2.10.2
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 09/18] ARM64: dts: meson-gxbb-wetek-hub: Reference CVBS node by label
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, devicetree
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 2 +-
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
index 5183c5ce90c6..0d134a85e3a0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
@@ -126,7 +126,7 @@
clock-names = "ext_clock";
};
- cvbs-connector {
+ cvbs_connector: cvbs-connector {
compatible = "composite-video-connector";
port {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
index 56f855901262..6e35265dc2fc 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
@@ -59,8 +59,8 @@
panic-indicator;
};
};
+};
- cvbs-connector {
- status = "disabled";
- };
+&cvbs_connector {
+ status = "disabled";
};
--
2.10.2
^ permalink raw reply related
* [PATCH 10/18] ARM64: dts: meson-gxbb: Reorder nodes
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, devicetree
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
Sort nodes referenced by label alphabetically.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 76 ++++++++++++++---------------
1 file changed, 38 insertions(+), 38 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 39a774ad83ce..5c22c794ed95 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -97,24 +97,6 @@
};
};
-&cbus {
- spifc: spi@8c80 {
- compatible = "amlogic,meson-gxbb-spifc";
- reg = <0x0 0x08c80 0x0 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc CLKID_SPI>;
- status = "disabled";
- };
-};
-
-ðmac {
- clocks = <&clkc CLKID_ETH>,
- <&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
-};
-
&aobus {
pinctrl_aobus: pinctrl@14 {
compatible = "amlogic,meson-gxbb-aobus-pinctrl";
@@ -230,6 +212,44 @@
};
};
+&cbus {
+ spifc: spi@8c80 {
+ compatible = "amlogic,meson-gxbb-spifc";
+ reg = <0x0 0x08c80 0x0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_SPI>;
+ status = "disabled";
+ };
+};
+
+ðmac {
+ clocks = <&clkc CLKID_ETH>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_MPLL2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1";
+};
+
+&hiubus {
+ clkc: clock-controller@0 {
+ compatible = "amlogic,gxbb-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0x0 0x0 0x3db>;
+ };
+};
+
+&i2c_A {
+ clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_B {
+ clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_C {
+ clocks = <&clkc CLKID_I2C>;
+};
+
&periphs {
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxbb-periphs-pinctrl";
@@ -470,26 +490,6 @@
};
};
-&hiubus {
- clkc: clock-controller@0 {
- compatible = "amlogic,gxbb-clkc";
- #clock-cells = <1>;
- reg = <0x0 0x0 0x0 0x3db>;
- };
-};
-
-&i2c_A {
- clocks = <&clkc CLKID_I2C>;
-};
-
-&i2c_B {
- clocks = <&clkc CLKID_I2C>;
-};
-
-&i2c_C {
- clocks = <&clkc CLKID_I2C>;
-};
-
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
--
2.10.2
^ permalink raw reply related
* [PATCH 11/18] ARM64: dts: meson-gxbb-odroidc2: Reorder nodes
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, devicetree
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
Sort nodes referenced by label alphabetically.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
.../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 52 +++++++++++-----------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index 238fbeacd330..a1ccfe702c27 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -137,45 +137,22 @@
};
};
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
ðmac {
status = "okay";
pinctrl-0 = <ð_rgmii_pins>;
pinctrl-names = "default";
};
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
&i2c_A {
status = "okay";
pinctrl-0 = <&i2c_a_pins>;
pinctrl-names = "default";
};
-&usb0_phy {
- status = "okay";
- phy-supply = <&usb_otg_pwr>;
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
+&ir {
status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
};
/* SD */
@@ -215,3 +192,26 @@
vmmc-supply = <&vcc3v3>;
vqmmc-supply = <&vcc1v8>;
};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb0_phy {
+ status = "okay";
+ phy-supply = <&usb_otg_pwr>;
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
--
2.10.2
^ permalink raw reply related
* [PATCH 12/18] ARM64: dts: meson-gxbb-vega-s95: Reorder nodes
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Carlo Caione, Kevin Hilman,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andreas Färber,
Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170120222118.21476-1-afaerber-l3A5Bk7waGM@public.gmane.org>
Sort nodes referenced by label alphabetically.
Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
---
.../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 51 +++++++++++-----------
1 file changed, 25 insertions(+), 26 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
index e688e8971a95..81024886d232 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
@@ -111,11 +111,10 @@
};
};
-&uart_AO {
+ðmac {
status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-0 = <ð_rgmii_pins>;
pinctrl-names = "default";
-
};
&ir {
@@ -124,27 +123,12 @@
pinctrl-names = "default";
};
-ðmac {
+&pwm_ef {
status = "okay";
- pinctrl-0 = <ð_rgmii_pins>;
+ pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
-};
-
-&usb0_phy {
- status = "okay";
- phy-supply = <&usb_vbus>;
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
};
/* Wireless SDIO Module */
@@ -210,10 +194,25 @@
vmmcq-sumpply = <&vcc_1v8>;
};
-&pwm_ef {
+&uart_AO {
status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
+};
+
+&usb0_phy {
+ status = "okay";
+ phy-supply = <&usb_vbus>;
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
};
--
2.10.2
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 13/18] ARM64: dts: meson-gxbb-nexbox-a95x: Reorder nodes
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, devicetree
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
Sort nodes referenced by label alphabetically.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
.../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 28 +++++++++++-----------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
index 4cbd626a9e88..e642bfd5eec5 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
@@ -154,10 +154,10 @@
};
};
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
};
ðmac {
@@ -173,6 +173,14 @@
pinctrl-names = "default";
};
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
@@ -232,16 +240,8 @@
vqmmc-supply = <&vddio_boot>;
};
-&pwm_ef {
+&uart_AO {
status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
};
--
2.10.2
^ permalink raw reply related
* [PATCH 14/18] ARM64: dts: meson-gxbb-p20x: Reorder nodes
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, devicetree
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
Sort nodes referenced by label alphabetically.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 54 ++++++++++++------------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
index 0d134a85e3a0..b6f9d051439c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
@@ -137,11 +137,10 @@
};
};
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
};
ðmac {
@@ -156,21 +155,12 @@
pinctrl-names = "default";
};
-&usb0_phy {
- status = "okay";
- phy-supply = <&usb_pwr>;
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
+&pwm_ef {
status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
};
/* Wireless SDIO Module */
@@ -237,16 +227,26 @@
vqmmc-supply = <&vddio_boot>;
};
-&pwm_ef {
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
};
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
+&usb0_phy {
+ status = "okay";
+ phy-supply = <&usb_pwr>;
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
};
--
2.10.2
^ permalink raw reply related
* [PATCH 15/18] ARM64: dts: meson-gxl: Reorder nodes
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, devicetree
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
Sort nodes referenced by label alphabetically.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 40 +++++++++++++++---------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index bdf2305a2e25..afa74455e1de 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -120,6 +120,26 @@
};
};
+&hiubus {
+ clkc: clock-controller@0 {
+ compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0x0 0x0 0x3db>;
+ };
+};
+
+&i2c_A {
+ clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_B {
+ clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_C {
+ clocks = <&clkc CLKID_I2C>;
+};
+
&periphs {
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxl-periphs-pinctrl";
@@ -320,26 +340,6 @@
};
};
-&hiubus {
- clkc: clock-controller@0 {
- compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
- #clock-cells = <1>;
- reg = <0x0 0x0 0x0 0x3db>;
- };
-};
-
-&i2c_A {
- clocks = <&clkc CLKID_I2C>;
-};
-
-&i2c_B {
- clocks = <&clkc CLKID_I2C>;
-};
-
-&i2c_C {
- clocks = <&clkc CLKID_I2C>;
-};
-
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
--
2.10.2
^ permalink raw reply related
* [PATCH 16/18] ARM64: dts: meson-gxl-s905x-nexbox-a95x: Reorder nodes
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, devicetree
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
Sort nodes referenced by label alphabetically.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
.../dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts | 28 +++++++++++-----------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
index cea4a3eded9b..9e91f0809dcd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
@@ -129,10 +129,10 @@
};
};
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
};
ðmac {
@@ -147,6 +147,14 @@
pinctrl-names = "default";
};
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
@@ -206,16 +214,8 @@
vqmmc-supply = <&vddio_boot>;
};
-&pwm_ef {
+&uart_AO {
status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
};
--
2.10.2
^ permalink raw reply related
* [PATCH 17/18] ARM64: dts: meson-gxm-nexbox-a1: Reorder nodes
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, devicetree
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
Sort nodes referenced by label alphabetically.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
.../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 58 +++++++++++-----------
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
index 439060652689..804e8de80f37 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
@@ -102,10 +102,35 @@
};
};
-&uart_AO {
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+ðmac {
status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
+
+ pinctrl-0 = <ð_pins>;
pinctrl-names = "default";
+
+ /* Select external PHY by default */
+ phy-handle = <&external_phy>;
+
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+
+ /* External PHY is in RGMII */
+ phy-mode = "rgmii";
+};
+
+&external_mdio {
+ external_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ max-speed = <1000>;
+ };
};
&ir {
@@ -152,33 +177,8 @@
vqmmc-supply = <&vddio_boot>;
};
-ðmac {
+&uart_AO {
status = "okay";
-
- pinctrl-0 = <ð_pins>;
+ pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
-
- /* Select external PHY by default */
- phy-handle = <&external_phy>;
-
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
- /* External PHY is in RGMII */
- phy-mode = "rgmii";
-};
-
-&external_mdio {
- external_phy: ethernet-phy@0 {
- compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- max-speed = <1000>;
- };
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
};
--
2.10.2
^ permalink raw reply related
* [PATCH 18/18] ARM64: dts: meson-gx-p23x-q20x: Reorder nodes
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Carlo Caione, Kevin Hilman,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andreas Färber,
Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170120222118.21476-1-afaerber-l3A5Bk7waGM@public.gmane.org>
Sort nodes referenced by label alphabetically.
Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
---
.../arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 24 +++++++++++-----------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
index 419c46cc64e4..cfc26a2a3a90 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
@@ -100,11 +100,8 @@
};
};
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
+ðmac {
status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
};
&ir {
@@ -113,6 +110,14 @@
pinctrl-names = "default";
};
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
@@ -177,14 +182,9 @@
vqmmc-supply = <&vddio_boot>;
};
-&pwm_ef {
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
-};
-
-ðmac {
- status = "okay";
};
--
2.10.2
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH] Add more recommended generic node names
From: Rob Herring @ 2017-01-20 22:29 UTC (permalink / raw)
To: devicetree-spec-u79uwXL29TY76Z2rM5mHXA; +Cc: devicetree-u79uwXL29TY76Z2rM5mHXA
DT usage and hardware types have evolved quite a bit and the generic
node names list is quite out of date. Add new entries to the list based
on dumping out node names from dts files. This is by no means complete,
but is low hanging fruit.
Signed-off-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
source/devicetree-basics.rst | 51 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/source/devicetree-basics.rst b/source/devicetree-basics.rst
index be80af3d825b..93cea8e82a64 100644
--- a/source/devicetree-basics.rst
+++ b/source/devicetree-basics.rst
@@ -182,44 +182,95 @@ name should be one of the following choices:
.. hlist::
:columns: 3
+ * adc
+ * accelerometer
* atm
+ * audio-codec
+ * audio-controller
+ * backlight
+ * bluetooth
+ * bus
* cache-controller
+ * camera
+ * can
+ * charger
+ * clock
+ * clock-controller
* compact-flash
* can
* cpu
+ * cpus
* crypto
* disk
* display
* dma-controller
+ * dsp
+ * eeprom
+ * efuse
+ * endpoint
* ethernet
* ethernet-phy
* fdc
* flash
* gpio
+ * gpu
+ * gyrometer
+ * hdmi
* i2c
* ide
* interrupt-controller
* isa
* keyboard
+ * key
+ * keys
+ * lcd-controller
+ * led
+ * leds
+ * led-controller
+ * light-sensor
+ * magnetometer
+ * mailbox
* mdio
* memory
* memory-controller
+ * mmc
+ * mmc-slot
* mouse
+ * nand-controller
* nvram
+ * oscillator
* parallel
* pc-card
* pci
* pcie
+ * phy
+ * pinctrl
+ * pmic
+ * pmu
+ * port
+ * ports
+ * pwm
+ * regulator
+ * reset-controller
* rtc
* sata
* scsi
* serial
* sound
* spi
+ * sram-controller
+ * ssi-controller
+ * syscon
+ * temperature-sensor
* timer
+ * touchscreen
* usb
+ * usb-hub
+ * usb-phy
+ * video-codec
* vme
* watchdog
+ * wifi
Path Names
~~~~~~~~~~
--
2.10.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH] ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency
From: Andreas Färber @ 2017-01-20 22:34 UTC (permalink / raw)
To: Neil Armstrong, khilman, carlo
Cc: linux-amlogic, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <1484814117-7593-1-git-send-email-narmstrong@baylibre.com>
Am 19.01.2017 um 09:21 schrieb Neil Armstrong:
> In order to keep consistency naming with the Nexbox A1 DTS file, remove the
If dt64 branch does get rebased: "consistency with" or "consistent naming"
> S912 SoC name in the GXM DT files.
>
> Suggested-by: Andreas Färber <afaerber@suse.de>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
^ permalink raw reply
* RE: [PATCH v4 2/3] mmc: sh_mobile_sdhi: explain clock bindings
From: Chris Brandt @ 2017-01-20 22:35 UTC (permalink / raw)
To: Wolfram Sang
Cc: Ulf Hansson, Rob Herring, Mark Rutland, Simon Horman,
Wolfram Sang, Geert Uytterhoeven, devicetree@vger.kernel.org,
linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org
In-Reply-To: <20170120213901.GC1438@katana>
Hello Wolfram,
Ulf's request was for more info, but it wasn't clear if he wanted more
info in the commit logs or in the files themselves.
On Friday, January 20, 2017, Wolfram Sang wrote:
> > +- clocks: Most controllers only have 1 clock source per channel.
> However, on
> > + some variations of this controller, the internal card detection
> > + logic that exists in this controller is sectioned off to be run by
> a
> > + separate second clock source to allow the main core clock to be
> turned
> > + off to save power. Unfortunately, the existing driver architecture
> > + does not support such a separation of clocks.
> > + Additionally, it is prohibited to supply a clock to the core but
> not
> > + to the card detect circuit. That leaves you with if separate
> clocks
> > + are presented, you must treat them both as 1.
> > + If 2 clocks are specified by the hardware, you must name them as
> > + "core" and "cd".
> > + If the controller only has 1 clock, naming is not required.
>
> I know we are not perfect in this area, but DT binding should be OS
> agnostic and should refrain from specifying Linux internals.
>
> So, I'd think the comments about driver architecture should be put into
> the driver, not into the bindings.
It sounds like your suggestion is to just put the HW description in
the DT bindings, but move the dirty details into the driver.
Keep in DT:
+- clocks: Most controllers only have 1 clock source per channel. However, on
+ some variations of this controller, the internal card detection
+ logic that exists in this controller is sectioned off to be run by a
+ separate second clock source to allow the main core clock to be turned
+ off to save power.
+ If 2 clocks are specified by the hardware, you must name them as
+ "core" and "cd".
+ If the controller only has 1 clock, naming is not required.
Move somewhere in the driver (maybe where the 2nd clock is detected):
+ Unfortunately, the existing driver architecture
+ does not support such a separation of clocks.
+ Additionally, it is prohibited to supply a clock to the core but not
+ to the card detect circuit. That leaves you with if separate clocks
+ are presented, you must treat them both as 1.
Is this what you were thinking?
Thank you,
Chris
^ permalink raw reply
* Re: [PATCH V2 1/2] dt-bindings: leds: document new led-triggers property
From: Jacek Anaszewski @ 2017-01-20 22:35 UTC (permalink / raw)
To: Rafał Miłecki, Greg Kroah-Hartman
Cc: linux-usb, linux-leds, Richard Purdie, Pavel Machek, devicetree,
Rob Herring, Mark Rutland, Rafał Miłecki
In-Reply-To: <20170120215605.15728-1-zajec5@gmail.com>
Hi Rafał,
On 01/20/2017 10:56 PM, Rafał Miłecki wrote:
> From: Rafał Miłecki <rafal@milecki.pl>
>
> Some LEDs can be related to particular devices described in DT. This
> property allows specifying such relations. E.g. USB LED should usually
> be used to indicate some USB port(s) state.
>
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
> ---
> V2: Replace "usb-ports" with "led-triggers" property which is more generic and
> allows specifying other devices as well.
>
> When bindings patch is related to some followup implementation, they usually go
> through the same tree.
>
> Greg: this patch is based on top of e64b8cc72bf9 ("DT: leds: Improve examples by
> adding some context") from kernel/git/j.anaszewski/linux-leds.git . Is there any
> way to solve this dependency issue? Or should this patch wait until 3.11 is
> released?
> ---
> Documentation/devicetree/bindings/leds/common.txt | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/leds/common.txt b/Documentation/devicetree/bindings/leds/common.txt
> index 24b656014089..17632a041196 100644
> --- a/Documentation/devicetree/bindings/leds/common.txt
> +++ b/Documentation/devicetree/bindings/leds/common.txt
> @@ -49,6 +49,17 @@ Optional properties for child nodes:
> - panic-indicator : This property specifies that the LED should be used,
> if at all possible, as a panic indicator.
>
> +- led-triggers : List of devices that should trigger this LED activity. Some
> + LEDs can be related to a specific device and should somehow
> + indicate its state. E.g. USB 2.0 LED may react to device(s) in
> + a USB 2.0 port(s). Another common example is switch or router
> + with multiple Ethernet ports each of them having its own LED
> + assigned (assuminled-trigger-usbportg they are not hardwired).
> + In such cases this property should contain phandle(s) of
> + related device(s). In many cases LED can be related to more
> + than one device (e.g. one USB LED vs. multiple USB ports) so a
> + list of entries can be specified.
> +
This implies that it is possible to define multiple triggers for
a LED class device but it is not supported by LED Trigger core.
There is linux,default-trigger property which allows to define one
trigger that will be initially assigned.
I am aware that this is renamed usb-ports property from v1,
that attempts to address Rob's comment, but we can't do that this way.
Maybe usb-ports property could be documented in led-trigger-usbport's
specific bindings and a reference to it could be added next to the
related entry on the list of the available LED triggers (which is
actually missing) in Documentation/devicetree/bindings/leds/common.txt.
> Required properties for flash LED child nodes:
> - flash-max-microamp : Maximum flash LED supply current in microamperes.
> - flash-max-timeout-us : Maximum timeout in microseconds after which the flash
> @@ -69,6 +80,11 @@ gpio-leds {
> linux,default-trigger = "heartbeat";
> gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
> };
> +
> + usb {
> + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
> + led-triggers = <&ohci_port1>, <&ehci_port1>;
> + };
> };
>
> max77693-led {
>
--
Best regards,
Jacek Anaszewski
^ permalink raw reply
* Re: [PATCH v4 2/3] mmc: sh_mobile_sdhi: explain clock bindings
From: Wolfram Sang @ 2017-01-20 22:41 UTC (permalink / raw)
To: Chris Brandt
Cc: Ulf Hansson, Rob Herring, Mark Rutland, Simon Horman,
Wolfram Sang, Geert Uytterhoeven, devicetree@vger.kernel.org,
linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org
In-Reply-To: <SG2PR06MB1165035F107F504185B525658A710@SG2PR06MB1165.apcprd06.prod.outlook.com>
[-- Attachment #1: Type: text/plain, Size: 1238 bytes --]
> It sounds like your suggestion is to just put the HW description in
> the DT bindings, but move the dirty details into the driver.
>
> Keep in DT:
>
> +- clocks: Most controllers only have 1 clock source per channel. However, on
> + some variations of this controller, the internal card detection
> + logic that exists in this controller is sectioned off to be run by a
> + separate second clock source to allow the main core clock to be turned
> + off to save power.
> + If 2 clocks are specified by the hardware, you must name them as
> + "core" and "cd".
> + If the controller only has 1 clock, naming is not required.
>
>
>
> Move somewhere in the driver (maybe where the 2nd clock is detected):
>
> + Unfortunately, the existing driver architecture
> + does not support such a separation of clocks.
"such" is not explained. Maybe "does not support a seperation of clocks.
It doesn't work with Runtime PM because ..."?
> + Additionally, it is prohibited to supply a clock to the core but not
> + to the card detect circuit. That leaves you with if separate clocks
> + are presented, you must treat them both as 1.
>
>
> Is this what you were thinking?
Exactly.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply
* Re: [PATCH 3/4] phy: qcom-ufs: Remove -always-on property
From: Subhash Jadavani @ 2017-01-20 22:53 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Kishon Vijay Abraham I, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA, Vivek Gautam
In-Reply-To: <20170119104739.4376-3-bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On 2017-01-19 02:47, Bjorn Andersson wrote:
> The fact that a regulator is always-on is a property of the regulator,
> not a specific consumer. Implementing this in the driver leads to a
> system behaviour that is dependent on if the Qualcomm UFS PHY was ever
> (partially) probed.
>
> If the specific regulator should be always on in a particular device,
> mark it so by specifying "regulator-always-on" in the regulator node.
>
> Cc: Subhash Jadavani <subhashj-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Cc: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> Documentation/devicetree/bindings/ufs/ufs-qcom.txt | 1 -
> drivers/phy/phy-qcom-ufs-i.h | 1 -
> drivers/phy/phy-qcom-ufs.c | 5 +----
> 3 files changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
> b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
> index b6b5130e5f65..1f69ee1a61ea 100644
> --- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
> +++ b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
> @@ -29,7 +29,6 @@ Optional properties:
> - vdda-pll-max-microamp : specifies max. load that can be drawn from
> pll supply
> - vddp-ref-clk-supply : phandle to UFS device ref_clk pad power
> supply
> - vddp-ref-clk-max-microamp : specifies max. load that can be drawn
> from this supply
> -- vddp-ref-clk-always-on : specifies if this supply needs to be kept
> always on
>
> Example:
>
> diff --git a/drivers/phy/phy-qcom-ufs-i.h
> b/drivers/phy/phy-qcom-ufs-i.h
> index d505d98cf5f8..13b02b7de30b 100644
> --- a/drivers/phy/phy-qcom-ufs-i.h
> +++ b/drivers/phy/phy-qcom-ufs-i.h
> @@ -77,7 +77,6 @@ struct ufs_qcom_phy_vreg {
> int min_uV;
> int max_uV;
> bool enabled;
> - bool is_always_on;
> };
>
> struct ufs_qcom_phy {
> diff --git a/drivers/phy/phy-qcom-ufs.c b/drivers/phy/phy-qcom-ufs.c
> index bbd317158084..c145fa6e824c 100644
> --- a/drivers/phy/phy-qcom-ufs.c
> +++ b/drivers/phy/phy-qcom-ufs.c
> @@ -242,9 +242,6 @@ static int ufs_qcom_phy_init_vreg(struct device
> *dev,
> }
> err = 0;
> }
> - snprintf(prop_name, MAX_PROP_NAME, "%s-always-on", name);
> - vreg->is_always_on = of_property_read_bool(dev->of_node,
> - prop_name);
> }
>
> if (!strcmp(name, "vdda-pll")) {
> @@ -402,7 +399,7 @@ static int ufs_qcom_phy_disable_vreg(struct device
> *dev,
> {
> int ret = 0;
>
> - if (!vreg || !vreg->enabled || vreg->is_always_on)
> + if (!vreg || !vreg->enabled)
> goto out;
>
> ret = regulator_disable(vreg->reg);
Looks good to me.
Reviewed-by: Subhash Jadavani <subhashj-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2 1/3] of: Support parsing phandle argument lists through a nexus node
From: Rob Herring @ 2017-01-20 23:16 UTC (permalink / raw)
To: Stephen Boyd
Cc: Frank Rowand, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org, Pantelis Antoniou, Linus Walleij,
Mark Brown
In-Reply-To: <20170118005038.9216-2-stephen.boyd@linaro.org>
On Tue, Jan 17, 2017 at 6:50 PM, Stephen Boyd <stephen.boyd@linaro.org> wrote:
> Platforms like 96boards have a standardized connector/expansion
> slot that exposes signals like GPIOs to expansion boards in an
> SoC agnostic way. We'd like the DT overlays for the expansion
> boards to be written once without knowledge of the SoC on the
> other side of the connector. This avoids the unscalable
> combinatorial explosion of a different DT overlay for each
> expansion board and SoC pair.
>
> We need a way to describe the GPIOs routed through the connector
> in an SoC agnostic way. Let's introduce nexus property parsing
> into the OF core to do this. This is largely based on the
> interrupt nexus support we already have. This allows us to remap
> a phandle list in a consumer node (e.g. reset-gpios) through a
> connector in a generic way (e.g. via gpio-map). Do this in a
> generic routine so that we can remap any sort of variable length
> phandle list.
>
> Taking GPIOs as an example, the connector would be a GPIO nexus,
> supporting the remapping of a GPIO specifier space to multiple
> GPIO providers on the SoC. DT would look as shown below, where
> 'soc_gpio1' and 'soc_gpio2' are inside the SoC, 'connector' is an
> expansion port where boards can be plugged in, and
> 'expansion_device' is a device on the expansion board.
>
> soc {
> soc_gpio1: gpio-controller1 {
> #gpio-cells = <2>;
> };
>
> soc_gpio2: gpio-controller2 {
> #gpio-cells = <2>;
> };
> };
>
> connector: connector {
> #gpio-cells = <2>;
> gpio-map = <0 0 &soc_gpio1 1 0>,
> <1 0 &soc_gpio2 4 0>,
> <2 0 &soc_gpio1 3 0>,
> <3 0 &soc_gpio2 2 0>;
> gpio-map-mask = <0xf 0x0>;
> gpio-map-pass-thru = <0x0 0x1>
> };
>
> expansion_device {
> reset-gpios = <&connector 2 GPIO_ACTIVE_LOW>;
> };
This all looks good to me. A few nits below.
>
> The GPIO core would use of_parse_phandle_with_args_map() instead
> of of_parse_phandle_with_args() and arrive at the same type of
> result, a phandle and argument list. The difference is that the
> phandle and arguments will be remapped through the nexus node to
> the underlying SoC GPIO controller node. In the example above,
> we would remap 'reset-gpios' from <&connector 2 GPIO_ACTIVE_LOW>
> to <&soc_gpio1 3 GPIO_ACTIVE_LOW>.
>
> Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Mark Brown <broonie@kernel.org>
> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
> ---
> drivers/of/base.c | 186 +++++++++++++++++++++++++++++++++++++++++++++++++++++
> include/linux/of.h | 12 ++++
> 2 files changed, 198 insertions(+)
>
> diff --git a/drivers/of/base.c b/drivers/of/base.c
> index d4bea3c797d6..277a81ff0479 100644
> --- a/drivers/of/base.c
> +++ b/drivers/of/base.c
> @@ -1775,6 +1775,192 @@ int of_parse_phandle_with_args(const struct device_node *np, const char *list_na
> EXPORT_SYMBOL(of_parse_phandle_with_args);
>
> /**
> + * of_parse_phandle_with_args_map() - Find a node pointed by phandle in a list and remap it
> + * @np: pointer to a device tree node containing a list
> + * @list_name: property name that contains a list
> + * @stem_name: stem of property names that specify phandles' arguments count
> + * @index: index of a phandle to parse out
> + * @out_args: optional pointer to output arguments structure (will be filled)
> + *
> + * This function is useful to parse lists of phandles and their arguments.
> + * Returns 0 on success and fills out_args, on error returns appropriate errno
> + * value. The difference between this function and of_parse_phandle_with_args()
> + * is that this API remaps a phandle if the node the phandle points to has
> + * a <@stem_name>-map property.
> + *
> + * Caller is responsible to call of_node_put() on the returned out_args->np
> + * pointer.
> + *
> + * Example:
> + *
> + * phandle1: node1 {
> + * #list-cells = <2>;
> + * }
> + *
> + * phandle2: node2 {
> + * #list-cells = <1>;
> + * }
> + *
> + * phandle3: node3 {
> + * #list-cells = <1>;
> + * list-map = <0 &phandle2 3>,
> + * <1 &phandle2 2>,
> + * <2 &phandle1 5 1>;
> + * list-map-mask = <0x3>;
> + * };
> + *
> + * node4 {
> + * list = <&phandle1 1 2 &phandle3 0>;
> + * }
> + *
> + * To get a device_node of the `node2' node you may call this:
> + * of_parse_phandle_with_args(node4, "list", "list", 1, &args);
> + */
> +int of_parse_phandle_with_args_map(const struct device_node *np,
> + const char *list_name,
> + const char *stem_name,
> + int index, struct of_phandle_args *out_args)
> +{
> + char *cells_name, *map_name = NULL, *mask_name = NULL;
> + char *pass_name = NULL;
> + struct device_node *cur, *new = NULL;
> + const __be32 *map, *mask, *pass, *tmp;
> + const __be32 dummy_mask[] = { [0 ... MAX_PHANDLE_ARGS] = ~0 };
> + const __be32 dummy_pass[] = { [0 ... MAX_PHANDLE_ARGS] = 0 };
These could be static and save some stack space.
> + __be32 initial_match_array[MAX_PHANDLE_ARGS];
We worked to get rid of this MAX_PHANDLE_ARGS limitation. I guess this
is fine as I don't think we'll do an IOMMU thru a connector which is
the main thing having long args list.
> + const __be32 *match_array = initial_match_array;
> + int i, ret, map_len, match;
> + u32 list_size, new_size;
> +
> + if (index < 0)
> + return -EINVAL;
> +
> + cells_name = kasprintf(GFP_KERNEL, "#%s-cells", stem_name);
> + if (!cells_name)
> + return -ENOMEM;
> +
> + ret = -ENOMEM;
> + map_name = kasprintf(GFP_KERNEL, "%s-map", stem_name);
> + if (!map_name)
> + goto free;
> +
> + mask_name = kasprintf(GFP_KERNEL, "%s-map-mask", stem_name);
> + if (!mask_name)
> + goto free;
> +
> + pass_name = kasprintf(GFP_KERNEL, "%s-map-pass-thru", stem_name);
> + if (!pass_name)
> + goto free;
> +
> + ret = __of_parse_phandle_with_args(np, list_name, cells_name, 0, index,
> + out_args);
> + if (ret)
> + goto free;
> +
> + /* Get the #<list>-cells property */
> + cur = out_args->np;
> + ret = of_property_read_u32(cur, cells_name, &list_size);
> + if (ret < 0)
> + goto put;
> +
> + /* Precalculate the match array - this simplifies match loop */
> + for (i = 0; i < list_size; i++)
> + initial_match_array[i] = cpu_to_be32(out_args->args[i]);
> +
> + ret = -EINVAL;
> + while (cur) {
> + /* Get the <list>-map property */
> + map = of_get_property(cur, map_name, &map_len);
> + if (!map) {
> + ret = 0;
> + goto free;
> + }
> + map_len /= sizeof(u32);
> +
> + /* Get the <list>-map-mask property (optional) */
> + mask = of_get_property(cur, mask_name, NULL);
> + if (!mask)
> + mask = dummy_mask;
> + /* Iterate through <list>-map property */
> + match = 0;
> + while (map_len > (list_size + 1) && !match) {
> + /* Compare specifiers */
> + match = 1;
> + for (i = 0; i < list_size; i++, map_len--)
> + match &= !((match_array[i] ^ *map++) & mask[i]);
> +
> + of_node_put(new);
> + new = of_find_node_by_phandle(be32_to_cpup(map));
> + map++;
> + map_len--;
> +
> + /* Check if not found */
> + if (!new)
> + goto put;
> +
> + if (!of_device_is_available(new))
> + match = 0;
> +
> + tmp = of_get_property(new, cells_name, NULL);
> + if (!tmp)
> + goto put;
> +
> + new_size = be32_to_cpu(*tmp);
This can use of_property_read_u32.
> +
> + /* Check for malformed properties */
> + if (WARN_ON(new_size > MAX_PHANDLE_ARGS))
> + goto put;
> + if (map_len < new_size)
> + goto put;
> +
> + /* Move forward by new node's #<list>-cells amount */
> + map += new_size;
> + map_len -= new_size;
> + }
> + if (!match)
> + goto put;
> +
> + /* Get the <list>-map-pass-thru property (optional) */
> + pass = of_get_property(cur, pass_name, NULL);
> + if (!pass)
> + pass = dummy_pass;
> +
> + /*
> + * Successfully parsed a <list>-map translation; copy new
> + * specifier into the out_args structure, keeping the
> + * bits specified in <list>-map-pass-thru.
> + */
> + match_array = map - new_size;
> + for (i = 0; i < new_size; i++) {
> + __be32 val = *(map - new_size + i);
> +
> + if (i < list_size) {
> + val &= ~pass[i];
> + val |= cpu_to_be32(out_args->args[i]) & pass[i];
> + }
> +
> + out_args->args[i] = be32_to_cpu(val);
> + }
> + out_args->args_count = list_size = new_size;
> + /* Iterate again with new provider */
> + out_args->np = new;
> + of_node_put(cur);
> + cur = new;
> + }
> +put:
> + of_node_put(cur);
> + of_node_put(new);
> +free:
> + kfree(mask_name);
> + kfree(map_name);
> + kfree(cells_name);
> + kfree(pass_name);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL(of_parse_phandle_with_args_map);
> +
> +/**
> * of_parse_phandle_with_fixed_args() - Find a node pointed by phandle in a list
> * @np: pointer to a device tree node containing a list
> * @list_name: property name that contains a list
^ permalink raw reply
* Re: [PATCH v7 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs
From: Joshua Clayton @ 2017-01-20 23:39 UTC (permalink / raw)
To: kbuild test robot
Cc: kbuild-all, Alan Tull, Moritz Fischer, Russell King, Shawn Guo,
Sascha Hauer, Fabio Estevam, Mark Rutland, Rob Herring,
Anatolij Gustschin, devicetree, linux-kernel, linux-arm-kernel,
linux-fpga
In-Reply-To: <201701202037.FWBSni3B%fengguang.wu@intel.com>
Sigh...
On 01/20/2017 04:07 AM, kbuild test robot wrote:
> Hi Joshua,
>
> [auto build test WARNING on linus/master]
> [also build test WARNING on v4.10-rc4 next-20170120]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>
> url: https://github.com/0day-ci/linux/commits/Joshua-Clayton/Altera-Cyclone-Passive-Serial-SPI-FPGA-Manager/20170120-172349
> reproduce:
> # apt-get install sparse
> make ARCH=x86_64 allmodconfig
> make C=1 CF=-D__CHECK_ENDIAN__
>
>
> sparse warnings: (new ones prefixed by >>)
>
> include/linux/compiler.h:253:8: sparse: attribute 'no_sanitize_address': unknown attribute
>>> drivers/fpga/cyclone-ps-spi.c:86:20: sparse: incompatible types in comparison expression (different signedness)
> drivers/fpga/cyclone-ps-spi.c:101:33: sparse: incompatible types in comparison expression (different type sizes)
> drivers/fpga/cyclone-ps-spi.c: In function 'rev_buf':
> drivers/fpga/cyclone-ps-spi.c:86:13: warning: comparison of distinct pointer types lacks a cast
> while (buf < fw_end) {
> ^
> In file included from include/linux/delay.h:10:0,
> from drivers/fpga/cyclone-ps-spi.c:17:
> drivers/fpga/cyclone-ps-spi.c: In function 'cyclonespi_write':
> include/linux/kernel.h:753:16: warning: comparison of distinct pointer types lacks a cast
> (void) (&min1 == &min2); \
> ^
> include/linux/kernel.h:756:2: note: in expansion of macro '__min'
> __min(typeof(x), typeof(y), \
> ^~~~~
> drivers/fpga/cyclone-ps-spi.c:101:19: note: in expansion of macro 'min'
> size_t stride = min(fw_data_end - fw_data, SZ_4K);
> ^~~
> drivers/fpga/cyclone-ps-spi.c:103:11: warning: passing argument 1 of 'rev_buf' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
> rev_buf(fw_data, stride);
> ^~~~~~~
> drivers/fpga/cyclone-ps-spi.c:81:13: note: expected 'char *' but argument is of type 'const char *'
> static void rev_buf(char *buf, size_t len)
> ^~~~~~~
>
> vim +86 drivers/fpga/cyclone-ps-spi.c
>
> 70 gpiod_set_value(conf->config, 0);
> 71 for (i = 0; i < (FPGA_MAX_DELAY / FPGA_MIN_DELAY); i++) {
> 72 usleep_range(FPGA_MIN_DELAY, FPGA_MIN_DELAY + 20);
> 73 if (!gpiod_get_value(conf->status))
> 74 return 0;
> 75 }
> 76
> 77 dev_err(&mgr->dev, "Status pin not ready.\n");
> 78 return -EIO;
> 79 }
> 80
> 81 static void rev_buf(char *buf, size_t len)
> 82 {
> 83 const u8 *fw_end = (buf + len);
Bah!
u8 * should be char *
> 84
> 85 /* set buffer to lsb first */
> > 86 while (buf < fw_end) {
> 87 *buf = bitrev8(*buf);
> 88 buf++;
> 89 }
> 90 }
> 91
> 92 static int cyclonespi_write(struct fpga_manager *mgr, const char *buf,
> 93 size_t count)
> 94 {
>
> ---
> 0-DAY kernel test infrastructure Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all Intel Corporation
Guess I had better add sparse to my pre send regimen.
v8 posted shortly.
~Joshua
^ permalink raw reply
* Re: [PATCH V2 1/2] clk: vc5: Add bindings for IDT VersaClock 5P49V5923 and 5P49V5933
From: Stephen Boyd @ 2017-01-21 0:12 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-clk, Michael Turquette, Laurent Pinchart, Rob Herring,
devicetree, linux-renesas-soc
In-Reply-To: <20170112010324.28068-1-marek.vasut@gmail.com>
On 01/12, Marek Vasut wrote:
> Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips.
> These are I2C clock generators with optional clock source from
> either XTal or dedicated clock generator and, depending on the
> model, two or more clock outputs.
>
> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH v5 01/12] clk: apn806: Add eMMC clock to system controller driver
From: Stephen Boyd @ 2017-01-21 0:16 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Jimmy Xu, Andrew Lunn, Ulf Hansson, Mike Turquette, linux-kernel,
Nadav Haklai, Ziji Hu, Victor Gu, Doug Jones, linux-clk,
Jisheng Zhang, Yehuda Yitschak, Marcin Wojtas, Kostya Porotchkin,
Hanna Hawa, Sebastian Hesselbarth, devicetree, Jason Cooper,
Russell King, Rob Herring, Ryan Gao, Wei(SOCP) Liu,
linux-arm-kernel, Thomas Petazzoni, linux-mmc
In-Reply-To: <e84d52dfbd9f7d2a14a5ec9d53918119fdc90404.1484154449.git-series.gregory.clement@free-electrons.com>
On 01/11, Gregory CLEMENT wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
>
> Add fixed clock of 400MHz to system controller driver. This clock is
> used as SD/eMMC clock source.
>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> Reviewed-by: Omri Itach <omrii@marvell.com>
> Reviewed-by: Hanna Hawa <hannah@marvell.com>
> [fixed up conflicts, added error handling --rmk]
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
> diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c
> index 8181b919f062..0a785076b0c6 100644
> --- a/drivers/clk/mvebu/ap806-system-controller.c
> +++ b/drivers/clk/mvebu/ap806-system-controller.c
> @@ -117,6 +117,17 @@ static int ap806_syscon_clk_probe(struct platform_device *pdev)
> goto fail3;
> }
>
> + /* eMMC Clock is fixed clock divided by 3 */
> + of_property_read_string_index(np, "clock-output-names",
> + 4, &name);
This could check for failure and not register the clk if the name
isn't there? Then dts can be backwards compatible.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH 1/8] clk: renesas: cpg-mssr: Document reset control support
From: Stephen Boyd @ 2017-01-21 0:31 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Philipp Zabel, Simon Horman, Magnus Damm, Michael Turquette,
Rob Herring, Mark Rutland, linux-clk, devicetree,
linux-renesas-soc, linux-kernel, linux-arm-kernel
In-Reply-To: <1484921306-9967-2-git-send-email-geert+renesas@glider.be>
On 01/20, Geert Uytterhoeven wrote:
> Document properties needed to use the Reset Control feature of the
> Renesas Clock Pulse Generator / Module Standby and Software Reset
> module.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Subject should be "dt-bindings: clock:" ?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH 2/8] clk: renesas: cpg-mssr: Document suitability for RZ/G1
From: Stephen Boyd @ 2017-01-21 0:32 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Philipp Zabel, Simon Horman, Magnus Damm, Michael Turquette,
Rob Herring, Mark Rutland, linux-clk, devicetree,
linux-renesas-soc, linux-kernel, linux-arm-kernel
In-Reply-To: <1484921306-9967-3-git-send-email-geert+renesas@glider.be>
On 01/20, Geert Uytterhoeven wrote:
> The Renesas CPG/MSSR driver is already in active use for RZ/G1 since
> commits c0b2d75d2a4bf6a3 ("clk: renesas: cpg-mssr: Add R8A7743 support")
> and 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support").
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH 3/8] clk: renesas: cpg-mssr: Rename cpg_mssr_priv.mstp_lock
From: Stephen Boyd @ 2017-01-21 0:32 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Philipp Zabel, Simon Horman, Magnus Damm, Michael Turquette,
Rob Herring, Mark Rutland, linux-clk, devicetree,
linux-renesas-soc, linux-kernel, linux-arm-kernel
In-Reply-To: <1484921306-9967-4-git-send-email-geert+renesas@glider.be>
On 01/20, Geert Uytterhoeven wrote:
> The spinlock is used to protect Read-Modify-Write register accesses,
> which won't be limited to SMSTPCR register accesses.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox