* [PATCH v2 05/14] MIPS: ingenic: Enable pinctrl for all ingenic SoCs
From: Paul Cercueil @ 2017-01-22 14:49 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Ulf Hansson
Cc: Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, linux-gpio,
devicetree, linux-kernel, linux-mips, linux-mmc, linux-mtd,
linux-pwm, linux-fbdev, james.hogan, Paul Cercueil
In-Reply-To: <20170122144947.16158-1-paul@crapouillou.net>
There is a pinctrl driver for each of the Ingenic SoCs supported by the
upstream Linux kernel. In order to switch away from the old GPIO
platform code, we now enable the pinctrl drivers by default for the
Ingenic SoCs.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)
v2: No changes
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b3c5bde43d34..fc720e37661e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -359,6 +359,7 @@ config MACH_INGENIC
select SYS_SUPPORTS_ZBOOT_UART16550
select DMA_NONCOHERENT
select IRQ_MIPS_CPU
+ select PINCTRL
select GPIOLIB
select COMMON_CLK
select GENERIC_IRQ_CHIP
--
2.11.0
^ permalink raw reply related
* [PATCH v2 06/14] MIPS: jz4740: DTS: Add nodes for ingenic pinctrl and gpio drivers
From: Paul Cercueil @ 2017-01-22 14:49 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Ulf Hansson
Cc: Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, linux-gpio,
devicetree, linux-kernel, linux-mips, linux-mmc, linux-mtd,
linux-pwm, linux-fbdev, james.hogan, Paul Cercueil
In-Reply-To: <20170122144947.16158-1-paul@crapouillou.net>
For a description of the pinctrl devicetree node, please read
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
For a description of the gpio devicetree nodes, please read
Documentation/devicetree/bindings/gpio/ingenic,gpio.txt
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
arch/mips/boot/dts/ingenic/jz4740.dtsi | 194 +++++++++++++++++++++++++++++++++
1 file changed, 194 insertions(+)
v2: Changed the devicetree bindings to match the new driver
diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi
index 3e1587f1f77a..960e060eb725 100644
--- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
@@ -55,6 +55,200 @@
clock-names = "rtc";
};
+ pinctrl: ingenic-pinctrl@10010000 {
+ compatible = "ingenic,jz4740-pinctrl";
+ reg = <0x10010000 0x400>;
+
+ ingenic,pull-ups = <0xffffffff 0xffffffff 0xffffffff 0xdfffffff>;
+ ingenic,pull-downs = <0x00000000 0x00000000 0x00000000 0x00000000>;
+
+ functions {
+ mmc {
+ mmc-1bit {
+ /* CLK, CMD, D0 */
+ ingenic,pins = <0x69 0 0x68 0 0x6a 0>;
+ };
+
+ mmc-4bit {
+ /* D1, D2, D3 */
+ ingenic,pins = <0x6b 0 0x6c 0 0x6d 0>;
+ };
+ };
+
+ uart0 {
+ uart0-data {
+ /* RXD, TXD */
+ ingenic,pins = <0x7a 1 0x79 1>;
+ };
+
+ uart0-hwflow {
+ /* CTS, RTS */
+ ingenic,pins = <0x7e 1 0x7f 1>;
+ };
+ };
+
+ uart1 {
+ uart1-data {
+ /* RXD, TXD */
+ ingenic,pins = <0x7e 2 0x7f 2>;
+ };
+ };
+
+ lcd {
+ lcd-8bit {
+ /* LCD_DATA0 ... LCD_DATA7, PCLK, HSYNC, VSYNC */
+ ingenic,pins = <0x40 0 0x41 0 0x42 0 0x43 0
+ 0x44 0 0x45 0 0x46 0 0x47 0
+ 0x52 0 0x53 0 0x54 0>;
+ };
+
+ lcd-16bit {
+ /* LCD_DATA8 ... LCD_DATA15, DE */
+ ingenic,pins = <0x48 0 0x49 0 0x4a 0 0x4b 0
+ 0x4c 0 0x4d 0 0x4e 0 0x4f 0
+ 0x55 0>;
+ };
+
+ lcd-18bit {
+ /* LCD_DATA16, LCD_DATA17 */
+ ingenic,pins = <0x50 0 0x51 0>;
+ };
+
+ lcd-18bit-tft {
+ /* PS, REV, CLS, SPL */
+ ingenic,pins = <0x56 0 0x57 0 0x31 0 0x32 0>;
+ };
+
+ lcd-no-pins {
+ ingenic,pins = <>;
+ };
+ };
+
+ nand {
+ nand {
+ /* CS1, CS2, CS3, CS4 */
+ ingenic,pins = <0x39 0 0x3a 0 0x3b 0 0x3c 0>;
+ };
+ };
+
+ pwm0 {
+ pwm0 {
+ ingenic,pins = <0x77 0>;
+ };
+ };
+
+ pwm1 {
+ pwm1 {
+ ingenic,pins = <0x78 0>;
+ };
+ };
+
+ pwm2 {
+ pwm2 {
+ ingenic,pins = <0x79 0>;
+ };
+ };
+
+ pwm3 {
+ pwm3 {
+ ingenic,pins = <0x7a 0>;
+ };
+ };
+
+ pwm4 {
+ pwm4 {
+ ingenic,pins = <0x7b 0>;
+ };
+ };
+
+ pwm5 {
+ pwm5 {
+ ingenic,pins = <0x7c 0>;
+ };
+ };
+
+ pwm6 {
+ pwm6 {
+ ingenic,pins = <0x7e 0>;
+ };
+ };
+
+ pwm7 {
+ pwm7 {
+ ingenic,pins = <0x7f 0>;
+ };
+ };
+ };
+ };
+
+ gpa: gpio-controller@10010000 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <0x10010000 0x100>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ base = <0x00>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <28>;
+ };
+
+ gpb: gpio-controller@10010100 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <0x10010100 0x100>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ #gpio-cells = <2>;
+
+ base = <0x20>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <27>;
+ };
+
+ gpc: gpio-controller@10010200 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <0x10010200 0x100>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ #gpio-cells = <2>;
+
+ base = <0x40>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <26>;
+ };
+
+ gpd: gpio-controller@10010300 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <0x10010300 0x100>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ #gpio-cells = <2>;
+
+ base = <0x60>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <25>;
+ };
+
uart0: serial@10030000 {
compatible = "ingenic,jz4740-uart";
reg = <0x10030000 0x100>;
--
2.11.0
^ permalink raw reply related
* [PATCH v2 07/14] MIPS: jz4780: DTS: Add nodes for ingenic pinctrl and gpio drivers
From: Paul Cercueil @ 2017-01-22 14:49 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Ulf Hansson
Cc: Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, linux-gpio,
devicetree, linux-kernel, linux-mips, linux-mmc, linux-mtd,
linux-pwm, linux-fbdev, james.hogan, Paul Cercueil
In-Reply-To: <20170122144947.16158-1-paul@crapouillou.net>
For a description of the devicetree node, please read
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
For a description of the gpio devicetree nodes, please read
Documentation/devicetree/bindings/gpio/ingenic,gpio.txt
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 297 +++++++++++++++++++++++++++++++++
1 file changed, 297 insertions(+)
v2: Changed the devicetree bindings to match the new driver
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index b868b429add2..47e079e9236e 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -44,6 +44,303 @@
#clock-cells = <1>;
};
+ pinctrl: ingenic-pinctrl@10010000 {
+ compatible = "ingenic,jz4780-pinctrl";
+ reg = <0x10010000 0x600>;
+
+ ingenic,pull-ups = <0x3fffffff 0xfff0030c 0xffffffff
+ 0xffff4fff 0xfffffb7c 0xffa7f00f>;
+ ingenic,pull-downs = <0x00000000 0x000f0c03 0x00000000
+ 0x0000b000 0x00000483 0x00580ff0>;
+
+ functions {
+ uart0 {
+ uart0-data {
+ /* RXD, TXD */
+ ingenic,pins = <0xa0 0 0xa3 0>;
+ };
+
+ uart0-hwflow {
+ /* CTS, RTS */
+ ingenic,pins = <0xa1 0 0xa2 0>;
+ };
+ };
+
+ uart1 {
+ uart1-data {
+ /* RXD, TXD */
+ ingenic,pins = <0x7a 0 0x7c 0>;
+ };
+
+ uart1-hwflow {
+ /* CTS, RTS */
+ ingenic,pins = <0x7b 0 0x7d 0>;
+ };
+ };
+
+ uart2 {
+ uart2-data {
+ /* RXD, TXD */
+ ingenic,pins = <0x66 1 0x67 1>;
+ };
+
+ uart2-hwflow {
+ /* CTS, RTS */
+ ingenic,pins = <0x65 1 0x64 1>;
+ };
+ };
+
+ uart3 {
+ uart3-data {
+ /* RXD, TXD */
+ ingenic,pins = <0x6c 0 0x85 1>;
+ };
+
+ uart3-hwflow {
+ /* CTS, RTS */
+ ingenic,pins = <0x88 0 0x89 0>;
+ };
+ };
+
+ uart4 {
+ uart4-data {
+ /* RXD, TXD */
+ ingenic,pins = <0x54 2 0x4a 2>;
+ };
+ };
+
+ msc0 {
+ msc0-8bit-a {
+ /* D4, D5, D6, D7, RST */
+ ingenic,pins = <0x04 1 0x05 1 0x06 1 0x07 1
+ 0x18 1>;
+ };
+
+ msc0-4bit-a {
+ /* D1, D2, D3 */
+ ingenic,pins = <0x15 1 0x16 1 0x17 1>;
+ };
+
+ msc0-1bit-a {
+ /* CLK, CMD, D0 */
+ ingenic,pins = <0x12 1 0x13 1 0x14 1>;
+ };
+
+ msc0-1bit-e {
+ /* CLK, CMD, D0 */
+ ingenic,pins = <0x9c 0 0x9d 0 0x94 0>;
+ };
+
+ msc0-4bit-e {
+ /* D1, D2, D3 */
+ ingenic,pins = <0x95 0 0x96 0 0x97 0>;
+ };
+ };
+
+ msc1 {
+ msc1-1bit-d {
+ /* CLK, CMD, D0 */
+ ingenic,pins = <0x78 0 0x79 0 0x74 0>;
+ };
+
+ msc1-4bit-d {
+ /* D1, D2, D3 */
+ ingenic,pins = <0x75 0 0x76 0 0x77 0>;
+ };
+
+ msc1-1bit-e {
+ /* CLK, CMD, D0 */
+ ingenic,pins = <0x9c 1 0x9d 1 0x94 1>;
+ };
+
+ msc1-4bit-e {
+ /* D1, D2, D3 */
+ ingenic,pins = <0x95 1 0x96 1 0x97 1>;
+ };
+ };
+
+ nemc {
+ nemc-data {
+ /* SD0, SD1, SD2, SD3, SD4, SD5, SD6, SD7 */
+ ingenic,pins = <0x00 0 0x01 0 0x02 0 0x03 0
+ 0x04 0 0x05 0 0x06 0 0x07 0>;
+ };
+
+ nemc-cle-ale {
+ /* SA0_CL, SA1_AL */
+ ingenic,pins = <0x20 0 0x21 0>;
+ };
+
+ nemc-addr {
+ /* SA2, SA3, SA4, SA5 */
+ ingenic,pins = <0x22 0 0x23 0 0x24 0 0x25 0>;
+ };
+
+ nemc-rd-we {
+ /* RD, WE */
+ ingenic,pins = <0x10 0 0x11 0>;
+ };
+
+ nemc-frd-fwe {
+ /* RD, WE */
+ ingenic,pins = <0x12 0 0x13 0>;
+ };
+ };
+
+ nemc-cs1 {
+ nemc-cs1 {
+ /* CS1 */
+ ingenic,pins = <0x15 0>;
+ };
+ };
+
+ nemc-cs6 {
+ nemc-cs6 {
+ /* CS6 */
+ ingenic,pins = <0x1a 0>;
+ };
+ };
+
+ i2c0 {
+ i2c0-data {
+ /* SDA, SCL */
+ ingenic,pins = <0x6e 0 0x6f 0>;
+ };
+ };
+
+ i2c1 {
+ i2c1-data {
+ /* SDA, SCL */
+ ingenic,pins = <0x8e 0 0x8f 0>;
+ };
+ };
+
+ i2c2 {
+ i2c2-data {
+ /* SDA, SCL */
+ ingenic,pins = <0xb0 2 0xb1 2>;
+ };
+ };
+
+ i2c3 {
+ i2c3-data {
+ /* SDA, SCL */
+ ingenic,pins = <0x6a 1 0x6b 1>;
+ };
+ };
+
+ i2c4 {
+ i2c4-data-pe {
+ /* SDA, SCL */
+ ingenic,pins = <0x8c 1 0x8d 1>;
+ };
+
+ i2c4-data-pf {
+ /* HDMI_SDA, HDMI_SCL */
+ ingenic,pins = <0xb9 1 0xb8 1>;
+ };
+ };
+
+ cim {
+ cim-pb {
+ ingenic,pins = <0x26 0 0x27 0 0x28 0 0x29 0
+ 0x2a 0 0x2b 0 0x2c 0 0x2d 0
+ 0x2e 0 0x2f 0 0x30 0 0x31 0>;
+ };
+ };
+ };
+ };
+
+ gpa: gpio-controller@10010000 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <0x10010000 0x100>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <17>;
+ };
+
+ gpb: gpio-controller@10010100 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <0x10010100 0x100>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <16>;
+ };
+
+ gpc: gpio-controller@10010200 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <0x10010200 0x100>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <15>;
+ };
+
+ gpd: gpio-controller@10010300 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <0x10010300 0x100>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <14>;
+ };
+
+ gpe: gpio-controller@10010400 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <0x10010400 0x100>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <13>;
+ };
+
+ gpf: gpio-controller@10010500 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <0x10010500 0x100>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 160 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <12>;
+ };
+
uart0: serial@10030000 {
compatible = "ingenic,jz4780-uart";
reg = <0x10030000 0x100>;
--
2.11.0
^ permalink raw reply related
* [PATCH v2 08/14] MIPS: JZ4740: Qi LB60: Add pinctrl configuration for several drivers
From: Paul Cercueil @ 2017-01-22 14:49 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Ulf Hansson
Cc: Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA,
james.hogan-1AXoQHu6uovQT0dZR+AlfA, Paul Cercueil
In-Reply-To: <20170122144947.16158-1-paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
We set the pin configuration for the jz4740-nand, jz4740-mmc,
jz4740-fb, jz4740-pwm and jz4740-uart drivers.
This will permit those drivers to be cleaned out of the custom GPIO code
that they currently use.
Signed-off-by: Paul Cercueil <paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
---
arch/mips/boot/dts/ingenic/qi_lb60.dts | 13 +++++++++++
arch/mips/jz4740/board-qi_lb60.c | 42 ++++++++++++++++++++++++++--------
2 files changed, 46 insertions(+), 9 deletions(-)
v2: Changed the devicetree bindings to match the new driver
diff --git a/arch/mips/boot/dts/ingenic/qi_lb60.dts b/arch/mips/boot/dts/ingenic/qi_lb60.dts
index be1a7d3a3e1b..b715ee2ac2ee 100644
--- a/arch/mips/boot/dts/ingenic/qi_lb60.dts
+++ b/arch/mips/boot/dts/ingenic/qi_lb60.dts
@@ -17,3 +17,16 @@
&rtc_dev {
system-power-controller;
};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart0>;
+};
+
+&pinctrl {
+ pins_uart0: uart0 {
+ function = "uart0";
+ groups = "uart0-data";
+ bias-disable;
+ };
+};
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
index a5bd94b95263..bf3dcc9ee9f8 100644
--- a/arch/mips/jz4740/board-qi_lb60.c
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -22,6 +22,8 @@
#include <linux/input/matrix_keypad.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_gpio.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
#include <linux/power_supply.h>
#include <linux/power/jz4740-battery.h>
#include <linux/power/gpio-charger.h>
@@ -447,13 +449,36 @@ static struct platform_device *jz_platform_devices[] __initdata = {
&qi_lb60_audio_device,
};
-static void __init board_gpio_setup(void)
-{
- /* We only need to enable/disable pullup here for pins used in generic
- * drivers. Everything else is done by the drivers themselves. */
- jz_gpio_disable_pullup(QI_LB60_GPIO_SD_VCC_EN_N);
- jz_gpio_disable_pullup(QI_LB60_GPIO_SD_CD);
-}
+static unsigned long pin_cfg_bias_disable[] = {
+ PIN_CONFIG_BIAS_DISABLE,
+};
+
+static struct pinctrl_map pin_map[] __initdata = {
+ /* NAND pin configuration */
+ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-nand",
+ "10010000.jz4740-pinctrl", "nand", "nand"),
+
+ /* fbdev pin configuration */
+ PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_DEFAULT,
+ "10010000.jz4740-pinctrl", "lcd", "lcd-8bit"),
+ PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_SLEEP,
+ "10010000.jz4740-pinctrl", "lcd", "lcd-no-pins"),
+
+ /* MMC pin configuration */
+ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
+ "10010000.jz4740-pinctrl", "mmc", "mmc-1bit"),
+ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
+ "10010000.jz4740-pinctrl", "mmc", "mmc-4bit"),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
+ "10010000.jz4740-pinctrl", "PD0", pin_cfg_bias_disable),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
+ "10010000.jz4740-pinctrl", "PD2", pin_cfg_bias_disable),
+
+ /* PWM pin configuration */
+ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-pwm",
+ "10010000.jz4740-pinctrl", "pwm4", "pwm4"),
+};
+
static int __init qi_lb60_init_platform_devices(void)
{
@@ -469,6 +494,7 @@ static int __init qi_lb60_init_platform_devices(void)
ARRAY_SIZE(qi_lb60_spi_board_info));
pwm_add_table(qi_lb60_pwm_lookup, ARRAY_SIZE(qi_lb60_pwm_lookup));
+ pinctrl_register_mappings(pin_map, ARRAY_SIZE(pin_map));
return platform_add_devices(jz_platform_devices,
ARRAY_SIZE(jz_platform_devices));
@@ -479,8 +505,6 @@ static int __init qi_lb60_board_setup(void)
{
printk(KERN_INFO "Qi Hardware JZ4740 QI LB60 setup\n");
- board_gpio_setup();
-
if (qi_lb60_init_platform_devices())
panic("Failed to initialize platform devices");
--
2.11.0
--
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^ permalink raw reply related
* [PATCH v2 09/14] MIPS: JZ4780: CI20: Add pinctrl configuration for several drivers
From: Paul Cercueil @ 2017-01-22 14:49 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Ulf Hansson
Cc: Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, linux-gpio,
devicetree, linux-kernel, linux-mips, linux-mmc, linux-mtd,
linux-pwm, linux-fbdev, james.hogan, Paul Cercueil
In-Reply-To: <20170122144947.16158-1-paul@crapouillou.net>
We set the pin configuration for the jz4780-nand and jz4780-uart
drivers.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
arch/mips/boot/dts/ingenic/ci20.dts | 60 +++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
v2: Changed the devicetree bindings to match the new driver
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 1652d8d60b1e..fd138d9978c1 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -29,18 +29,30 @@
&uart0 {
status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart0>;
};
&uart1 {
status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart1>;
};
&uart3 {
status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart2>;
};
&uart4 {
status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart4>;
};
&nemc {
@@ -61,6 +73,13 @@
ingenic,nemc-tAW = <15>;
ingenic,nemc-tSTRV = <100>;
+ /*
+ * Only CLE/ALE are needed for the devices that are connected, rather
+ * than the full address line set.
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc>;
+
nand@1 {
reg = <1>;
@@ -69,6 +88,9 @@
nand-ecc-mode = "hw";
nand-on-flash-bbt;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc_cs1>;
+
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
@@ -106,3 +128,41 @@
&bch {
status = "okay";
};
+
+&pinctrl {
+ pins_uart0: uart0 {
+ function = "uart0";
+ groups = "uart0-data";
+ bias-disable;
+ };
+
+ pins_uart1: uart1 {
+ function = "uart1";
+ groups = "uart1-data";
+ bias-disable;
+ };
+
+ pins_uart2: uart2 {
+ function = "uart2";
+ groups = "uart2-data", "uart2-hwflow";
+ bias-disable;
+ };
+
+ pins_uart4: uart4 {
+ function = "uart4";
+ groups = "uart4-data";
+ bias-disable;
+ };
+
+ pins_nemc: nemc {
+ function = "nemc";
+ groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe";
+ bias-disable;
+ };
+
+ pins_nemc_cs1: nemc-cs1 {
+ function = "nemc-cs1";
+ groups = "nemc-cs1";
+ bias-disable;
+ };
+};
--
2.11.0
^ permalink raw reply related
* [PATCH v2 10/14] mmc: jz4740: Let the pinctrl driver configure the pins
From: Paul Cercueil @ 2017-01-22 14:49 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Ulf Hansson
Cc: Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, linux-gpio,
devicetree, linux-kernel, linux-mips, linux-mmc, linux-mtd,
linux-pwm, linux-fbdev, james.hogan, Paul Cercueil
In-Reply-To: <20170122144947.16158-1-paul@crapouillou.net>
Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/mmc/host/jz4740_mmc.c | 45 +++++--------------------------------------
1 file changed, 5 insertions(+), 40 deletions(-)
v2: Set pin sleep/default state in suspend/resume callbacks
diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c
index 819ad32964fc..b5fec5b7ee7b 100644
--- a/drivers/mmc/host/jz4740_mmc.c
+++ b/drivers/mmc/host/jz4740_mmc.c
@@ -20,14 +20,13 @@
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/module.h>
+#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/scatterlist.h>
#include <linux/clk.h>
#include <linux/bitops.h>
-#include <linux/gpio.h>
-#include <asm/mach-jz4740/gpio.h>
#include <asm/cacheflush.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
@@ -906,15 +905,6 @@ static const struct mmc_host_ops jz4740_mmc_ops = {
.enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
};
-static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
- JZ_GPIO_BULK_PIN(MSC_CMD),
- JZ_GPIO_BULK_PIN(MSC_CLK),
- JZ_GPIO_BULK_PIN(MSC_DATA0),
- JZ_GPIO_BULK_PIN(MSC_DATA1),
- JZ_GPIO_BULK_PIN(MSC_DATA2),
- JZ_GPIO_BULK_PIN(MSC_DATA3),
-};
-
static int jz4740_mmc_request_gpio(struct device *dev, int gpio,
const char *name, bool output, int value)
{
@@ -978,15 +968,6 @@ static void jz4740_mmc_free_gpios(struct platform_device *pdev)
gpio_free(pdata->gpio_power);
}
-static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
-{
- size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins);
- if (host->pdata && host->pdata->data_1bit)
- num_pins -= 3;
-
- return num_pins;
-}
-
static int jz4740_mmc_probe(struct platform_device* pdev)
{
int ret;
@@ -1027,15 +1008,9 @@ static int jz4740_mmc_probe(struct platform_device* pdev)
goto err_free_host;
}
- ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
- if (ret) {
- dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret);
- goto err_free_host;
- }
-
ret = jz4740_mmc_request_gpios(mmc, pdev);
if (ret)
- goto err_gpio_bulk_free;
+ goto err_release_dma;
mmc->ops = &jz4740_mmc_ops;
mmc->f_min = JZ_MMC_CLK_RATE / 128;
@@ -1091,10 +1066,9 @@ static int jz4740_mmc_probe(struct platform_device* pdev)
free_irq(host->irq, host);
err_free_gpios:
jz4740_mmc_free_gpios(pdev);
-err_gpio_bulk_free:
+err_release_dma:
if (host->use_dma)
jz4740_mmc_release_dma_channels(host);
- jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
err_free_host:
mmc_free_host(mmc);
@@ -1114,7 +1088,6 @@ static int jz4740_mmc_remove(struct platform_device *pdev)
free_irq(host->irq, host);
jz4740_mmc_free_gpios(pdev);
- jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
if (host->use_dma)
jz4740_mmc_release_dma_channels(host);
@@ -1128,20 +1101,12 @@ static int jz4740_mmc_remove(struct platform_device *pdev)
static int jz4740_mmc_suspend(struct device *dev)
{
- struct jz4740_mmc_host *host = dev_get_drvdata(dev);
-
- jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
-
- return 0;
+ return pinctrl_pm_select_sleep_state(dev);
}
static int jz4740_mmc_resume(struct device *dev)
{
- struct jz4740_mmc_host *host = dev_get_drvdata(dev);
-
- jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
-
- return 0;
+ return pinctrl_pm_select_default_state(dev);
}
static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
--
2.11.0
^ permalink raw reply related
* [PATCH v2 11/14] mtd: nand: jz4740: Let the pinctrl driver configure the pins
From: Paul Cercueil @ 2017-01-22 14:49 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Ulf Hansson
Cc: Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA,
james.hogan-1AXoQHu6uovQT0dZR+AlfA, Paul Cercueil
In-Reply-To: <20170122144947.16158-1-paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
Before, this NAND driver would set itself the configuration of the
chip-select pins for the various NAND banks.
Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.
Signed-off-by: Paul Cercueil <paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
---
drivers/mtd/nand/jz4740_nand.c | 23 +----------------------
1 file changed, 1 insertion(+), 22 deletions(-)
v2: No changes
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index 5551c36adbdf..0d06a1f07d82 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -25,7 +25,6 @@
#include <linux/gpio.h>
-#include <asm/mach-jz4740/gpio.h>
#include <asm/mach-jz4740/jz4740_nand.h>
#define JZ_REG_NAND_CTRL 0x50
@@ -310,34 +309,20 @@ static int jz_nand_detect_bank(struct platform_device *pdev,
uint8_t *nand_dev_id)
{
int ret;
- int gpio;
- char gpio_name[9];
char res_name[6];
uint32_t ctrl;
struct nand_chip *chip = &nand->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
- /* Request GPIO port. */
- gpio = JZ_GPIO_MEM_CS0 + bank - 1;
- sprintf(gpio_name, "NAND CS%d", bank);
- ret = gpio_request(gpio, gpio_name);
- if (ret) {
- dev_warn(&pdev->dev,
- "Failed to request %s gpio %d: %d\n",
- gpio_name, gpio, ret);
- goto notfound_gpio;
- }
-
/* Request I/O resource. */
sprintf(res_name, "bank%d", bank);
ret = jz_nand_ioremap_resource(pdev, res_name,
&nand->bank_mem[bank - 1],
&nand->bank_base[bank - 1]);
if (ret)
- goto notfound_resource;
+ return ret;
/* Enable chip in bank. */
- jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0);
ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
@@ -377,12 +362,8 @@ static int jz_nand_detect_bank(struct platform_device *pdev,
dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
- jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
nand->bank_base[bank - 1]);
-notfound_resource:
- gpio_free(gpio);
-notfound_gpio:
return ret;
}
@@ -503,7 +484,6 @@ static int jz_nand_probe(struct platform_device *pdev)
err_unclaim_banks:
while (chipnr--) {
unsigned char bank = nand->banks[chipnr];
- gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
nand->bank_base[bank - 1]);
}
@@ -530,7 +510,6 @@ static int jz_nand_remove(struct platform_device *pdev)
if (bank != 0) {
jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
nand->bank_base[bank - 1]);
- gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
}
}
--
2.11.0
--
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^ permalink raw reply related
* [PATCH v2 12/14] fbdev: jz4740-fb: Let the pinctrl driver configure the pins
From: Paul Cercueil @ 2017-01-22 14:49 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Ulf Hansson
Cc: Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, linux-gpio,
devicetree, linux-kernel, linux-mips, linux-mmc, linux-mtd,
linux-pwm, linux-fbdev, james.hogan, Paul Cercueil
In-Reply-To: <20170122144947.16158-1-paul@crapouillou.net>
Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/video/fbdev/jz4740_fb.c | 104 ++--------------------------------------
1 file changed, 3 insertions(+), 101 deletions(-)
v2: No changes
diff --git a/drivers/video/fbdev/jz4740_fb.c b/drivers/video/fbdev/jz4740_fb.c
index 87790e9644d0..b57df83fdbd3 100644
--- a/drivers/video/fbdev/jz4740_fb.c
+++ b/drivers/video/fbdev/jz4740_fb.c
@@ -17,6 +17,7 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
#include <linux/clk.h>
#include <linux/delay.h>
@@ -27,7 +28,6 @@
#include <linux/dma-mapping.h>
#include <asm/mach-jz4740/jz4740_fb.h>
-#include <asm/mach-jz4740/gpio.h>
#define JZ_REG_LCD_CFG 0x00
#define JZ_REG_LCD_VSYNC 0x04
@@ -146,93 +146,6 @@ static const struct fb_fix_screeninfo jzfb_fix = {
.accel = FB_ACCEL_NONE,
};
-static const struct jz_gpio_bulk_request jz_lcd_ctrl_pins[] = {
- JZ_GPIO_BULK_PIN(LCD_PCLK),
- JZ_GPIO_BULK_PIN(LCD_HSYNC),
- JZ_GPIO_BULK_PIN(LCD_VSYNC),
- JZ_GPIO_BULK_PIN(LCD_DE),
- JZ_GPIO_BULK_PIN(LCD_PS),
- JZ_GPIO_BULK_PIN(LCD_REV),
- JZ_GPIO_BULK_PIN(LCD_CLS),
- JZ_GPIO_BULK_PIN(LCD_SPL),
-};
-
-static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = {
- JZ_GPIO_BULK_PIN(LCD_DATA0),
- JZ_GPIO_BULK_PIN(LCD_DATA1),
- JZ_GPIO_BULK_PIN(LCD_DATA2),
- JZ_GPIO_BULK_PIN(LCD_DATA3),
- JZ_GPIO_BULK_PIN(LCD_DATA4),
- JZ_GPIO_BULK_PIN(LCD_DATA5),
- JZ_GPIO_BULK_PIN(LCD_DATA6),
- JZ_GPIO_BULK_PIN(LCD_DATA7),
- JZ_GPIO_BULK_PIN(LCD_DATA8),
- JZ_GPIO_BULK_PIN(LCD_DATA9),
- JZ_GPIO_BULK_PIN(LCD_DATA10),
- JZ_GPIO_BULK_PIN(LCD_DATA11),
- JZ_GPIO_BULK_PIN(LCD_DATA12),
- JZ_GPIO_BULK_PIN(LCD_DATA13),
- JZ_GPIO_BULK_PIN(LCD_DATA14),
- JZ_GPIO_BULK_PIN(LCD_DATA15),
- JZ_GPIO_BULK_PIN(LCD_DATA16),
- JZ_GPIO_BULK_PIN(LCD_DATA17),
-};
-
-static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb)
-{
- unsigned int num;
-
- switch (jzfb->pdata->lcd_type) {
- case JZ_LCD_TYPE_GENERIC_16_BIT:
- num = 4;
- break;
- case JZ_LCD_TYPE_GENERIC_18_BIT:
- num = 4;
- break;
- case JZ_LCD_TYPE_8BIT_SERIAL:
- num = 3;
- break;
- case JZ_LCD_TYPE_SPECIAL_TFT_1:
- case JZ_LCD_TYPE_SPECIAL_TFT_2:
- case JZ_LCD_TYPE_SPECIAL_TFT_3:
- num = 8;
- break;
- default:
- num = 0;
- break;
- }
- return num;
-}
-
-static unsigned int jzfb_num_data_pins(struct jzfb *jzfb)
-{
- unsigned int num;
-
- switch (jzfb->pdata->lcd_type) {
- case JZ_LCD_TYPE_GENERIC_16_BIT:
- num = 16;
- break;
- case JZ_LCD_TYPE_GENERIC_18_BIT:
- num = 18;
- break;
- case JZ_LCD_TYPE_8BIT_SERIAL:
- num = 8;
- break;
- case JZ_LCD_TYPE_SPECIAL_TFT_1:
- case JZ_LCD_TYPE_SPECIAL_TFT_2:
- case JZ_LCD_TYPE_SPECIAL_TFT_3:
- if (jzfb->pdata->bpp == 18)
- num = 18;
- else
- num = 16;
- break;
- default:
- num = 0;
- break;
- }
- return num;
-}
-
/* Based on CNVT_TOHW macro from skeletonfb.c */
static inline uint32_t jzfb_convert_color_to_hw(unsigned val,
struct fb_bitfield *bf)
@@ -487,8 +400,7 @@ static void jzfb_enable(struct jzfb *jzfb)
clk_prepare_enable(jzfb->ldclk);
- jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
- jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
+ pinctrl_pm_select_default_state(&jzfb->pdev->dev);
writel(0, jzfb->base + JZ_REG_LCD_STATE);
@@ -511,8 +423,7 @@ static void jzfb_disable(struct jzfb *jzfb)
ctrl = readl(jzfb->base + JZ_REG_LCD_STATE);
} while (!(ctrl & JZ_LCD_STATE_DISABLED));
- jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
- jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
+ pinctrl_pm_select_sleep_state(&jzfb->pdev->dev);
clk_disable_unprepare(jzfb->ldclk);
}
@@ -701,9 +612,6 @@ static int jzfb_probe(struct platform_device *pdev)
fb->mode = NULL;
jzfb_set_par(fb);
- jz_gpio_bulk_request(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
- jz_gpio_bulk_request(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
-
ret = register_framebuffer(fb);
if (ret) {
dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret);
@@ -715,9 +623,6 @@ static int jzfb_probe(struct platform_device *pdev)
return 0;
err_free_devmem:
- jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
- jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
-
fb_dealloc_cmap(&fb->cmap);
jzfb_free_devmem(jzfb);
err_framebuffer_release:
@@ -731,9 +636,6 @@ static int jzfb_remove(struct platform_device *pdev)
jzfb_blank(FB_BLANK_POWERDOWN, jzfb->fb);
- jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
- jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
-
fb_dealloc_cmap(&jzfb->fb->cmap);
jzfb_free_devmem(jzfb);
--
2.11.0
^ permalink raw reply related
* [PATCH v2 13/14] pwm: jz4740: Let the pinctrl driver configure the pins
From: Paul Cercueil @ 2017-01-22 14:49 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Ulf Hansson
Cc: Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, linux-gpio,
devicetree, linux-kernel, linux-mips, linux-mmc, linux-mtd,
linux-pwm, linux-fbdev, james.hogan, Paul Cercueil
In-Reply-To: <20170122144947.16158-1-paul@crapouillou.net>
Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.
One inherent problem of this new approach is that the pinctrl framework
does not allow us to configure each pin on demand, when the various PWM
channels are requested or released. For instance, the PWM channels can
be configured from sysfs, which would require all PWM pins to be configured
properly beforehand for the PWM function, eventually causing conflicts
with other platform or board drivers.
The proper solution here would be to modify the pwm-jz4740 driver to
handle only one PWM channel, and create an instance of this driver
for each one of the 8 PWM channels. Then, it could use the pinctrl
framework to dynamically configure the PWM pin it controls.
Until this can be done, the only jz4740 board supported upstream
(Qi lb60) can configure all of its connected PWM pins in PWM function
mode, since those are not used by other drivers nor by GPIOs on the
board.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/pwm/pwm-jz4740.c | 29 -----------------------------
1 file changed, 29 deletions(-)
v2: No changes
diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c
index 76d13150283f..a75ff3622450 100644
--- a/drivers/pwm/pwm-jz4740.c
+++ b/drivers/pwm/pwm-jz4740.c
@@ -21,22 +21,10 @@
#include <linux/platform_device.h>
#include <linux/pwm.h>
-#include <asm/mach-jz4740/gpio.h>
#include <asm/mach-jz4740/timer.h>
#define NUM_PWM 8
-static const unsigned int jz4740_pwm_gpio_list[NUM_PWM] = {
- JZ_GPIO_PWM0,
- JZ_GPIO_PWM1,
- JZ_GPIO_PWM2,
- JZ_GPIO_PWM3,
- JZ_GPIO_PWM4,
- JZ_GPIO_PWM5,
- JZ_GPIO_PWM6,
- JZ_GPIO_PWM7,
-};
-
struct jz4740_pwm_chip {
struct pwm_chip chip;
struct clk *clk;
@@ -49,9 +37,6 @@ static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
- unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm];
- int ret;
-
/*
* Timers 0 and 1 are used for system tasks, so they are unavailable
* for use as PWMs.
@@ -59,15 +44,6 @@ static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
if (pwm->hwpwm < 2)
return -EBUSY;
- ret = gpio_request(gpio, pwm->label);
- if (ret) {
- dev_err(chip->dev, "Failed to request GPIO#%u for PWM: %d\n",
- gpio, ret);
- return ret;
- }
-
- jz_gpio_set_function(gpio, JZ_GPIO_FUNC_PWM);
-
jz4740_timer_start(pwm->hwpwm);
return 0;
@@ -75,13 +51,8 @@ static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
- unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm];
-
jz4740_timer_set_ctrl(pwm->hwpwm, 0);
- jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
- gpio_free(gpio);
-
jz4740_timer_stop(pwm->hwpwm);
}
--
2.11.0
^ permalink raw reply related
* [PATCH v2 14/14] MIPS: jz4740: Remove custom GPIO code
From: Paul Cercueil @ 2017-01-22 14:49 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Mark Rutland, Ralf Baechle,
Ulf Hansson
Cc: Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, linux-gpio,
devicetree, linux-kernel, linux-mips, linux-mmc, linux-mtd,
linux-pwm, linux-fbdev, james.hogan, Paul Cercueil
In-Reply-To: <20170122144947.16158-1-paul@crapouillou.net>
All the drivers for the various hardware elements of the jz4740 SoC have
been modified to use the pinctrl framework for their pin configuration
needs.
As such, this platform code is now unused and can be deleted.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
arch/mips/include/asm/mach-jz4740/gpio.h | 371 ----------------------
arch/mips/jz4740/Makefile | 2 -
arch/mips/jz4740/gpio.c | 519 -------------------------------
3 files changed, 892 deletions(-)
delete mode 100644 arch/mips/jz4740/gpio.c
v2: No changes
diff --git a/arch/mips/include/asm/mach-jz4740/gpio.h b/arch/mips/include/asm/mach-jz4740/gpio.h
index 7c7708a23baa..fd847c984701 100644
--- a/arch/mips/include/asm/mach-jz4740/gpio.h
+++ b/arch/mips/include/asm/mach-jz4740/gpio.h
@@ -16,380 +16,9 @@
#ifndef _JZ_GPIO_H
#define _JZ_GPIO_H
-#include <linux/types.h>
-
-enum jz_gpio_function {
- JZ_GPIO_FUNC_NONE,
- JZ_GPIO_FUNC1,
- JZ_GPIO_FUNC2,
- JZ_GPIO_FUNC3,
-};
-
-/*
- Usually a driver for a SoC component has to request several gpio pins and
- configure them as function pins.
- jz_gpio_bulk_request can be used to ease this process.
- Usually one would do something like:
-
- static const struct jz_gpio_bulk_request i2c_pins[] = {
- JZ_GPIO_BULK_PIN(I2C_SDA),
- JZ_GPIO_BULK_PIN(I2C_SCK),
- };
-
- inside the probe function:
-
- ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
- if (ret) {
- ...
-
- inside the remove function:
-
- jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
-
-*/
-
-struct jz_gpio_bulk_request {
- int gpio;
- const char *name;
- enum jz_gpio_function function;
-};
-
-#define JZ_GPIO_BULK_PIN(pin) { \
- .gpio = JZ_GPIO_ ## pin, \
- .name = #pin, \
- .function = JZ_GPIO_FUNC_ ## pin \
-}
-
-int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
-void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
-void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num);
-void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num);
-void jz_gpio_enable_pullup(unsigned gpio);
-void jz_gpio_disable_pullup(unsigned gpio);
-int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
-
-int jz_gpio_port_direction_input(int port, uint32_t mask);
-int jz_gpio_port_direction_output(int port, uint32_t mask);
-void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
-uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
-
#define JZ_GPIO_PORTA(x) ((x) + 32 * 0)
#define JZ_GPIO_PORTB(x) ((x) + 32 * 1)
#define JZ_GPIO_PORTC(x) ((x) + 32 * 2)
#define JZ_GPIO_PORTD(x) ((x) + 32 * 3)
-/* Port A function pins */
-#define JZ_GPIO_MEM_DATA0 JZ_GPIO_PORTA(0)
-#define JZ_GPIO_MEM_DATA1 JZ_GPIO_PORTA(1)
-#define JZ_GPIO_MEM_DATA2 JZ_GPIO_PORTA(2)
-#define JZ_GPIO_MEM_DATA3 JZ_GPIO_PORTA(3)
-#define JZ_GPIO_MEM_DATA4 JZ_GPIO_PORTA(4)
-#define JZ_GPIO_MEM_DATA5 JZ_GPIO_PORTA(5)
-#define JZ_GPIO_MEM_DATA6 JZ_GPIO_PORTA(6)
-#define JZ_GPIO_MEM_DATA7 JZ_GPIO_PORTA(7)
-#define JZ_GPIO_MEM_DATA8 JZ_GPIO_PORTA(8)
-#define JZ_GPIO_MEM_DATA9 JZ_GPIO_PORTA(9)
-#define JZ_GPIO_MEM_DATA10 JZ_GPIO_PORTA(10)
-#define JZ_GPIO_MEM_DATA11 JZ_GPIO_PORTA(11)
-#define JZ_GPIO_MEM_DATA12 JZ_GPIO_PORTA(12)
-#define JZ_GPIO_MEM_DATA13 JZ_GPIO_PORTA(13)
-#define JZ_GPIO_MEM_DATA14 JZ_GPIO_PORTA(14)
-#define JZ_GPIO_MEM_DATA15 JZ_GPIO_PORTA(15)
-#define JZ_GPIO_MEM_DATA16 JZ_GPIO_PORTA(16)
-#define JZ_GPIO_MEM_DATA17 JZ_GPIO_PORTA(17)
-#define JZ_GPIO_MEM_DATA18 JZ_GPIO_PORTA(18)
-#define JZ_GPIO_MEM_DATA19 JZ_GPIO_PORTA(19)
-#define JZ_GPIO_MEM_DATA20 JZ_GPIO_PORTA(20)
-#define JZ_GPIO_MEM_DATA21 JZ_GPIO_PORTA(21)
-#define JZ_GPIO_MEM_DATA22 JZ_GPIO_PORTA(22)
-#define JZ_GPIO_MEM_DATA23 JZ_GPIO_PORTA(23)
-#define JZ_GPIO_MEM_DATA24 JZ_GPIO_PORTA(24)
-#define JZ_GPIO_MEM_DATA25 JZ_GPIO_PORTA(25)
-#define JZ_GPIO_MEM_DATA26 JZ_GPIO_PORTA(26)
-#define JZ_GPIO_MEM_DATA27 JZ_GPIO_PORTA(27)
-#define JZ_GPIO_MEM_DATA28 JZ_GPIO_PORTA(28)
-#define JZ_GPIO_MEM_DATA29 JZ_GPIO_PORTA(29)
-#define JZ_GPIO_MEM_DATA30 JZ_GPIO_PORTA(30)
-#define JZ_GPIO_MEM_DATA31 JZ_GPIO_PORTA(31)
-
-#define JZ_GPIO_FUNC_MEM_DATA0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA4 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA5 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA6 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA7 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA8 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA9 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA10 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA11 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA12 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA13 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA14 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA15 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA16 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA17 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA18 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA19 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA20 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA21 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA22 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA23 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA24 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA25 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA26 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA27 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA28 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA29 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA30 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA31 JZ_GPIO_FUNC1
-
-/* Port B function pins */
-#define JZ_GPIO_MEM_ADDR0 JZ_GPIO_PORTB(0)
-#define JZ_GPIO_MEM_ADDR1 JZ_GPIO_PORTB(1)
-#define JZ_GPIO_MEM_ADDR2 JZ_GPIO_PORTB(2)
-#define JZ_GPIO_MEM_ADDR3 JZ_GPIO_PORTB(3)
-#define JZ_GPIO_MEM_ADDR4 JZ_GPIO_PORTB(4)
-#define JZ_GPIO_MEM_ADDR5 JZ_GPIO_PORTB(5)
-#define JZ_GPIO_MEM_ADDR6 JZ_GPIO_PORTB(6)
-#define JZ_GPIO_MEM_ADDR7 JZ_GPIO_PORTB(7)
-#define JZ_GPIO_MEM_ADDR8 JZ_GPIO_PORTB(8)
-#define JZ_GPIO_MEM_ADDR9 JZ_GPIO_PORTB(9)
-#define JZ_GPIO_MEM_ADDR10 JZ_GPIO_PORTB(10)
-#define JZ_GPIO_MEM_ADDR11 JZ_GPIO_PORTB(11)
-#define JZ_GPIO_MEM_ADDR12 JZ_GPIO_PORTB(12)
-#define JZ_GPIO_MEM_ADDR13 JZ_GPIO_PORTB(13)
-#define JZ_GPIO_MEM_ADDR14 JZ_GPIO_PORTB(14)
-#define JZ_GPIO_MEM_ADDR15 JZ_GPIO_PORTB(15)
-#define JZ_GPIO_MEM_ADDR16 JZ_GPIO_PORTB(16)
-#define JZ_GPIO_LCD_CLS JZ_GPIO_PORTB(17)
-#define JZ_GPIO_LCD_SPL JZ_GPIO_PORTB(18)
-#define JZ_GPIO_MEM_DCS JZ_GPIO_PORTB(19)
-#define JZ_GPIO_MEM_RAS JZ_GPIO_PORTB(20)
-#define JZ_GPIO_MEM_CAS JZ_GPIO_PORTB(21)
-#define JZ_GPIO_MEM_SDWE JZ_GPIO_PORTB(22)
-#define JZ_GPIO_MEM_CKE JZ_GPIO_PORTB(23)
-#define JZ_GPIO_MEM_CKO JZ_GPIO_PORTB(24)
-#define JZ_GPIO_MEM_CS0 JZ_GPIO_PORTB(25)
-#define JZ_GPIO_MEM_CS1 JZ_GPIO_PORTB(26)
-#define JZ_GPIO_MEM_CS2 JZ_GPIO_PORTB(27)
-#define JZ_GPIO_MEM_CS3 JZ_GPIO_PORTB(28)
-#define JZ_GPIO_MEM_RD JZ_GPIO_PORTB(29)
-#define JZ_GPIO_MEM_WR JZ_GPIO_PORTB(30)
-#define JZ_GPIO_MEM_WE0 JZ_GPIO_PORTB(31)
-
-#define JZ_GPIO_FUNC_MEM_ADDR0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR4 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR5 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR6 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR7 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR8 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR9 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR10 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR11 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR12 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR13 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_CLS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_SPL JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CAS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_SDWE JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CKE JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CKO JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CS0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CS1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CS2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CS3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_RD JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WR JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WE0 JZ_GPIO_FUNC1
-
-
-#define JZ_GPIO_MEM_ADDR21 JZ_GPIO_PORTB(17)
-#define JZ_GPIO_MEM_ADDR22 JZ_GPIO_PORTB(18)
-
-#define JZ_GPIO_FUNC_MEM_ADDR21 JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_ADDR22 JZ_GPIO_FUNC2
-
-/* Port C function pins */
-#define JZ_GPIO_LCD_DATA0 JZ_GPIO_PORTC(0)
-#define JZ_GPIO_LCD_DATA1 JZ_GPIO_PORTC(1)
-#define JZ_GPIO_LCD_DATA2 JZ_GPIO_PORTC(2)
-#define JZ_GPIO_LCD_DATA3 JZ_GPIO_PORTC(3)
-#define JZ_GPIO_LCD_DATA4 JZ_GPIO_PORTC(4)
-#define JZ_GPIO_LCD_DATA5 JZ_GPIO_PORTC(5)
-#define JZ_GPIO_LCD_DATA6 JZ_GPIO_PORTC(6)
-#define JZ_GPIO_LCD_DATA7 JZ_GPIO_PORTC(7)
-#define JZ_GPIO_LCD_DATA8 JZ_GPIO_PORTC(8)
-#define JZ_GPIO_LCD_DATA9 JZ_GPIO_PORTC(9)
-#define JZ_GPIO_LCD_DATA10 JZ_GPIO_PORTC(10)
-#define JZ_GPIO_LCD_DATA11 JZ_GPIO_PORTC(11)
-#define JZ_GPIO_LCD_DATA12 JZ_GPIO_PORTC(12)
-#define JZ_GPIO_LCD_DATA13 JZ_GPIO_PORTC(13)
-#define JZ_GPIO_LCD_DATA14 JZ_GPIO_PORTC(14)
-#define JZ_GPIO_LCD_DATA15 JZ_GPIO_PORTC(15)
-#define JZ_GPIO_LCD_DATA16 JZ_GPIO_PORTC(16)
-#define JZ_GPIO_LCD_DATA17 JZ_GPIO_PORTC(17)
-#define JZ_GPIO_LCD_PCLK JZ_GPIO_PORTC(18)
-#define JZ_GPIO_LCD_HSYNC JZ_GPIO_PORTC(19)
-#define JZ_GPIO_LCD_VSYNC JZ_GPIO_PORTC(20)
-#define JZ_GPIO_LCD_DE JZ_GPIO_PORTC(21)
-#define JZ_GPIO_LCD_PS JZ_GPIO_PORTC(22)
-#define JZ_GPIO_LCD_REV JZ_GPIO_PORTC(23)
-#define JZ_GPIO_MEM_WE1 JZ_GPIO_PORTC(24)
-#define JZ_GPIO_MEM_WE2 JZ_GPIO_PORTC(25)
-#define JZ_GPIO_MEM_WE3 JZ_GPIO_PORTC(26)
-#define JZ_GPIO_MEM_WAIT JZ_GPIO_PORTC(27)
-#define JZ_GPIO_MEM_FRE JZ_GPIO_PORTC(28)
-#define JZ_GPIO_MEM_FWE JZ_GPIO_PORTC(29)
-
-#define JZ_GPIO_FUNC_LCD_DATA0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA4 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA5 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA6 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA7 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA8 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA9 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA10 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA11 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA12 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA13 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA14 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA15 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA16 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA17 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_PCLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_VSYNC JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_HSYNC JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DE JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_PS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_REV JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WE1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WE2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WE3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WAIT JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_FRE JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_FWE JZ_GPIO_FUNC1
-
-
-#define JZ_GPIO_MEM_ADDR19 JZ_GPIO_PORTB(22)
-#define JZ_GPIO_MEM_ADDR20 JZ_GPIO_PORTB(23)
-
-#define JZ_GPIO_FUNC_MEM_ADDR19 JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_ADDR20 JZ_GPIO_FUNC2
-
-/* Port D function pins */
-#define JZ_GPIO_CIM_DATA0 JZ_GPIO_PORTD(0)
-#define JZ_GPIO_CIM_DATA1 JZ_GPIO_PORTD(1)
-#define JZ_GPIO_CIM_DATA2 JZ_GPIO_PORTD(2)
-#define JZ_GPIO_CIM_DATA3 JZ_GPIO_PORTD(3)
-#define JZ_GPIO_CIM_DATA4 JZ_GPIO_PORTD(4)
-#define JZ_GPIO_CIM_DATA5 JZ_GPIO_PORTD(5)
-#define JZ_GPIO_CIM_DATA6 JZ_GPIO_PORTD(6)
-#define JZ_GPIO_CIM_DATA7 JZ_GPIO_PORTD(7)
-#define JZ_GPIO_MSC_CMD JZ_GPIO_PORTD(8)
-#define JZ_GPIO_MSC_CLK JZ_GPIO_PORTD(9)
-#define JZ_GPIO_MSC_DATA0 JZ_GPIO_PORTD(10)
-#define JZ_GPIO_MSC_DATA1 JZ_GPIO_PORTD(11)
-#define JZ_GPIO_MSC_DATA2 JZ_GPIO_PORTD(12)
-#define JZ_GPIO_MSC_DATA3 JZ_GPIO_PORTD(13)
-#define JZ_GPIO_CIM_MCLK JZ_GPIO_PORTD(14)
-#define JZ_GPIO_CIM_PCLK JZ_GPIO_PORTD(15)
-#define JZ_GPIO_CIM_VSYNC JZ_GPIO_PORTD(16)
-#define JZ_GPIO_CIM_HSYNC JZ_GPIO_PORTD(17)
-#define JZ_GPIO_SPI_CLK JZ_GPIO_PORTD(18)
-#define JZ_GPIO_SPI_CE0 JZ_GPIO_PORTD(19)
-#define JZ_GPIO_SPI_DT JZ_GPIO_PORTD(20)
-#define JZ_GPIO_SPI_DR JZ_GPIO_PORTD(21)
-#define JZ_GPIO_SPI_CE1 JZ_GPIO_PORTD(22)
-#define JZ_GPIO_PWM0 JZ_GPIO_PORTD(23)
-#define JZ_GPIO_PWM1 JZ_GPIO_PORTD(24)
-#define JZ_GPIO_PWM2 JZ_GPIO_PORTD(25)
-#define JZ_GPIO_PWM3 JZ_GPIO_PORTD(26)
-#define JZ_GPIO_PWM4 JZ_GPIO_PORTD(27)
-#define JZ_GPIO_PWM5 JZ_GPIO_PORTD(28)
-#define JZ_GPIO_PWM6 JZ_GPIO_PORTD(30)
-#define JZ_GPIO_PWM7 JZ_GPIO_PORTD(31)
-
-#define JZ_GPIO_FUNC_CIM_DATA JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_DATA0 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA1 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA2 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA3 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA4 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA5 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA6 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA7 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_MSC_CMD JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MSC_CLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MSC_DATA JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MSC_DATA0 JZ_GPIO_FUNC_MSC_DATA
-#define JZ_GPIO_FUNC_MSC_DATA1 JZ_GPIO_FUNC_MSC_DATA
-#define JZ_GPIO_FUNC_MSC_DATA2 JZ_GPIO_FUNC_MSC_DATA
-#define JZ_GPIO_FUNC_MSC_DATA3 JZ_GPIO_FUNC_MSC_DATA
-#define JZ_GPIO_FUNC_CIM_MCLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_PCLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_VSYNC JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_HSYNC JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_CLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_CE0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_DT JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_DR JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_CE1 JZ_GPIO_FUNC1
-
-#define JZ_GPIO_FUNC_PWM JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_PWM0 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM1 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM2 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM3 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM4 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM5 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM6 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM7 JZ_GPIO_FUNC_PWM
-
-#define JZ_GPIO_MEM_SCLK_RSTN JZ_GPIO_PORTD(18)
-#define JZ_GPIO_MEM_BCLK JZ_GPIO_PORTD(19)
-#define JZ_GPIO_MEM_SDATO JZ_GPIO_PORTD(20)
-#define JZ_GPIO_MEM_SDATI JZ_GPIO_PORTD(21)
-#define JZ_GPIO_MEM_SYNC JZ_GPIO_PORTD(22)
-#define JZ_GPIO_I2C_SDA JZ_GPIO_PORTD(23)
-#define JZ_GPIO_I2C_SCK JZ_GPIO_PORTD(24)
-#define JZ_GPIO_UART0_TXD JZ_GPIO_PORTD(25)
-#define JZ_GPIO_UART0_RXD JZ_GPIO_PORTD(26)
-#define JZ_GPIO_MEM_ADDR17 JZ_GPIO_PORTD(27)
-#define JZ_GPIO_MEM_ADDR18 JZ_GPIO_PORTD(28)
-#define JZ_GPIO_UART0_CTS JZ_GPIO_PORTD(30)
-#define JZ_GPIO_UART0_RTS JZ_GPIO_PORTD(31)
-
-#define JZ_GPIO_FUNC_MEM_SCLK_RSTN JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_BCLK JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_SDATO JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_SDATI JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_SYNC JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_I2C_SDA JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_I2C_SCK JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_UART0_TXD JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_UART0_RXD JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_ADDR17 JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_ADDR18 JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_UART0_CTS JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_UART0_RTS JZ_GPIO_FUNC2
-
-#define JZ_GPIO_UART1_RXD JZ_GPIO_PORTD(30)
-#define JZ_GPIO_UART1_TXD JZ_GPIO_PORTD(31)
-
-#define JZ_GPIO_FUNC_UART1_RXD JZ_GPIO_FUNC3
-#define JZ_GPIO_FUNC_UART1_TXD JZ_GPIO_FUNC3
-
#endif
diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile
index 39d70bde8cfe..6b9c1f7c31c9 100644
--- a/arch/mips/jz4740/Makefile
+++ b/arch/mips/jz4740/Makefile
@@ -7,8 +7,6 @@
obj-y += prom.o time.o reset.o setup.o \
platform.o timer.o
-obj-$(CONFIG_MACH_JZ4740) += gpio.o
-
CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
# board specific support
diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c
deleted file mode 100644
index b765773ab8aa..000000000000
--- a/arch/mips/jz4740/gpio.c
+++ /dev/null
@@ -1,519 +0,0 @@
-/*
- * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 platform GPIO support
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include <linux/io.h>
-#include <linux/gpio/driver.h>
-/* FIXME: needed for gpio_request(), try to remove consumer API from driver */
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/irqchip/ingenic.h>
-#include <linux/bitops.h>
-
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-
-#include <asm/mach-jz4740/base.h>
-#include <asm/mach-jz4740/gpio.h>
-
-#define JZ4740_GPIO_BASE_A (32*0)
-#define JZ4740_GPIO_BASE_B (32*1)
-#define JZ4740_GPIO_BASE_C (32*2)
-#define JZ4740_GPIO_BASE_D (32*3)
-
-#define JZ4740_GPIO_NUM_A 32
-#define JZ4740_GPIO_NUM_B 32
-#define JZ4740_GPIO_NUM_C 31
-#define JZ4740_GPIO_NUM_D 32
-
-#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
-#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
-#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
-#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
-
-#define JZ_REG_GPIO_PIN 0x00
-#define JZ_REG_GPIO_DATA 0x10
-#define JZ_REG_GPIO_DATA_SET 0x14
-#define JZ_REG_GPIO_DATA_CLEAR 0x18
-#define JZ_REG_GPIO_MASK 0x20
-#define JZ_REG_GPIO_MASK_SET 0x24
-#define JZ_REG_GPIO_MASK_CLEAR 0x28
-#define JZ_REG_GPIO_PULL 0x30
-#define JZ_REG_GPIO_PULL_SET 0x34
-#define JZ_REG_GPIO_PULL_CLEAR 0x38
-#define JZ_REG_GPIO_FUNC 0x40
-#define JZ_REG_GPIO_FUNC_SET 0x44
-#define JZ_REG_GPIO_FUNC_CLEAR 0x48
-#define JZ_REG_GPIO_SELECT 0x50
-#define JZ_REG_GPIO_SELECT_SET 0x54
-#define JZ_REG_GPIO_SELECT_CLEAR 0x58
-#define JZ_REG_GPIO_DIRECTION 0x60
-#define JZ_REG_GPIO_DIRECTION_SET 0x64
-#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
-#define JZ_REG_GPIO_TRIGGER 0x70
-#define JZ_REG_GPIO_TRIGGER_SET 0x74
-#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
-#define JZ_REG_GPIO_FLAG 0x80
-#define JZ_REG_GPIO_FLAG_CLEAR 0x14
-
-#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
-#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
-#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
-
-struct jz_gpio_chip {
- unsigned int irq;
- unsigned int irq_base;
- uint32_t edge_trigger_both;
-
- void __iomem *base;
-
- struct gpio_chip gpio_chip;
-};
-
-static struct jz_gpio_chip jz4740_gpio_chips[];
-
-static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
-{
- return &jz4740_gpio_chips[gpio >> 5];
-}
-
-static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gc)
-{
- return gpiochip_get_data(gc);
-}
-
-static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data)
-{
- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
- return gc->private;
-}
-
-static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
-{
- writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
-}
-
-int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
-{
- if (function == JZ_GPIO_FUNC_NONE) {
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
- } else {
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
- switch (function) {
- case JZ_GPIO_FUNC1:
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
- break;
- case JZ_GPIO_FUNC3:
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
- case JZ_GPIO_FUNC2: /* Falltrough */
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
- break;
- default:
- BUG();
- break;
- }
- }
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(jz_gpio_set_function);
-
-int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
-{
- size_t i;
- int ret;
-
- for (i = 0; i < num; ++i, ++request) {
- ret = gpio_request(request->gpio, request->name);
- if (ret)
- goto err;
- jz_gpio_set_function(request->gpio, request->function);
- }
-
- return 0;
-
-err:
- for (--request; i > 0; --i, --request) {
- gpio_free(request->gpio);
- jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
- }
-
- return ret;
-}
-EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
-
-void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
-{
- size_t i;
-
- for (i = 0; i < num; ++i, ++request) {
- gpio_free(request->gpio);
- jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
- }
-
-}
-EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
-
-void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
-{
- size_t i;
-
- for (i = 0; i < num; ++i, ++request) {
- jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
- jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
- }
-}
-EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
-
-void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
-{
- size_t i;
-
- for (i = 0; i < num; ++i, ++request)
- jz_gpio_set_function(request->gpio, request->function);
-}
-EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
-
-void jz_gpio_enable_pullup(unsigned gpio)
-{
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
-}
-EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
-
-void jz_gpio_disable_pullup(unsigned gpio)
-{
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
-}
-EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
-
-static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
-{
- return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
-}
-
-static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-{
- uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
- reg += !value;
- writel(BIT(gpio), reg);
-}
-
-static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
- int value)
-{
- writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
- jz_gpio_set_value(chip, gpio, value);
-
- return 0;
-}
-
-static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
- writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
-
- return 0;
-}
-
-static int jz_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
-{
- struct jz_gpio_chip *jz_gpio = gpiochip_get_data(chip);
-
- return jz_gpio->irq_base + gpio;
-}
-
-int jz_gpio_port_direction_input(int port, uint32_t mask)
-{
- writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
-
- return 0;
-}
-EXPORT_SYMBOL(jz_gpio_port_direction_input);
-
-int jz_gpio_port_direction_output(int port, uint32_t mask)
-{
- writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
-
- return 0;
-}
-EXPORT_SYMBOL(jz_gpio_port_direction_output);
-
-void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
-{
- writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
- writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
-}
-EXPORT_SYMBOL(jz_gpio_port_set_value);
-
-uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
-{
- uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
-
- return value & mask;
-}
-EXPORT_SYMBOL(jz_gpio_port_get_value);
-
-#define IRQ_TO_BIT(irq) BIT((irq - JZ4740_IRQ_GPIO(0)) & 0x1f)
-
-static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
-{
- uint32_t value;
- void __iomem *reg;
- uint32_t mask = IRQ_TO_BIT(irq);
-
- if (!(chip->edge_trigger_both & mask))
- return;
-
- reg = chip->base;
-
- value = readl(chip->base + JZ_REG_GPIO_PIN);
- if (value & mask)
- reg += JZ_REG_GPIO_DIRECTION_CLEAR;
- else
- reg += JZ_REG_GPIO_DIRECTION_SET;
-
- writel(mask, reg);
-}
-
-static void jz_gpio_irq_demux_handler(struct irq_desc *desc)
-{
- uint32_t flag;
- unsigned int gpio_irq;
- struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
-
- flag = readl(chip->base + JZ_REG_GPIO_FLAG);
- if (!flag)
- return;
-
- gpio_irq = chip->irq_base + __fls(flag);
-
- jz_gpio_check_trigger_both(chip, gpio_irq);
-
- generic_handle_irq(gpio_irq);
-};
-
-static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
-{
- struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
- writel(IRQ_TO_BIT(data->irq), chip->base + reg);
-}
-
-static void jz_gpio_irq_unmask(struct irq_data *data)
-{
- struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
-
- jz_gpio_check_trigger_both(chip, data->irq);
- irq_gc_unmask_enable_reg(data);
-};
-
-/* TODO: Check if function is gpio */
-static unsigned int jz_gpio_irq_startup(struct irq_data *data)
-{
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
- jz_gpio_irq_unmask(data);
- return 0;
-}
-
-static void jz_gpio_irq_shutdown(struct irq_data *data)
-{
- irq_gc_mask_disable_reg(data);
-
- /* Set direction to input */
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
-}
-
-static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
-{
- struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
- unsigned int irq = data->irq;
-
- if (flow_type == IRQ_TYPE_EDGE_BOTH) {
- uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
- if (value & IRQ_TO_BIT(irq))
- flow_type = IRQ_TYPE_EDGE_FALLING;
- else
- flow_type = IRQ_TYPE_EDGE_RISING;
- chip->edge_trigger_both |= IRQ_TO_BIT(irq);
- } else {
- chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
- }
-
- switch (flow_type) {
- case IRQ_TYPE_EDGE_RISING:
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
- break;
- case IRQ_TYPE_EDGE_FALLING:
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
- break;
- case IRQ_TYPE_LEVEL_HIGH:
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
- break;
- case IRQ_TYPE_LEVEL_LOW:
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
-{
- struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
-
- irq_gc_set_wake(data, on);
- irq_set_irq_wake(chip->irq, on);
-
- return 0;
-}
-
-#define JZ4740_GPIO_CHIP(_bank) { \
- .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
- .gpio_chip = { \
- .label = "Bank " # _bank, \
- .owner = THIS_MODULE, \
- .set = jz_gpio_set_value, \
- .get = jz_gpio_get_value, \
- .direction_output = jz_gpio_direction_output, \
- .direction_input = jz_gpio_direction_input, \
- .to_irq = jz_gpio_to_irq, \
- .base = JZ4740_GPIO_BASE_ ## _bank, \
- .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
- }, \
-}
-
-static struct jz_gpio_chip jz4740_gpio_chips[] = {
- JZ4740_GPIO_CHIP(A),
- JZ4740_GPIO_CHIP(B),
- JZ4740_GPIO_CHIP(C),
- JZ4740_GPIO_CHIP(D),
-};
-
-static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
-{
- struct irq_chip_generic *gc;
- struct irq_chip_type *ct;
-
- chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
-
- chip->irq = JZ4740_IRQ_INTC_GPIO(id);
- irq_set_chained_handler_and_data(chip->irq,
- jz_gpio_irq_demux_handler, chip);
-
- gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base,
- chip->base, handle_level_irq);
-
- gc->wake_enabled = IRQ_MSK(chip->gpio_chip.ngpio);
- gc->private = chip;
-
- ct = gc->chip_types;
- ct->regs.enable = JZ_REG_GPIO_MASK_CLEAR;
- ct->regs.disable = JZ_REG_GPIO_MASK_SET;
- ct->regs.ack = JZ_REG_GPIO_FLAG_CLEAR;
-
- ct->chip.name = "GPIO";
- ct->chip.irq_mask = irq_gc_mask_disable_reg;
- ct->chip.irq_unmask = jz_gpio_irq_unmask;
- ct->chip.irq_ack = irq_gc_ack_set_bit;
- ct->chip.irq_suspend = ingenic_intc_irq_suspend;
- ct->chip.irq_resume = ingenic_intc_irq_resume;
- ct->chip.irq_startup = jz_gpio_irq_startup;
- ct->chip.irq_shutdown = jz_gpio_irq_shutdown;
- ct->chip.irq_set_type = jz_gpio_irq_set_type;
- ct->chip.irq_set_wake = jz_gpio_irq_set_wake;
- ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
-
- irq_setup_generic_chip(gc, IRQ_MSK(chip->gpio_chip.ngpio),
- IRQ_GC_INIT_NESTED_LOCK, 0, IRQ_NOPROBE | IRQ_LEVEL);
-
- gpiochip_add_data(&chip->gpio_chip, chip);
-}
-
-static int __init jz4740_gpio_init(void)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
- jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
-
- printk(KERN_INFO "JZ4740 GPIO initialized\n");
-
- return 0;
-}
-arch_initcall(jz4740_gpio_init);
-
-#ifdef CONFIG_DEBUG_FS
-
-static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
- const char *name, unsigned int reg)
-{
- seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
-}
-
-static int gpio_regs_show(struct seq_file *s, void *unused)
-{
- struct jz_gpio_chip *chip = jz4740_gpio_chips;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
- seq_printf(s, "==GPIO %d==\n", i);
- gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
- gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
- gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
- gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
- gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
- gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
- gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
- gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
- gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
- }
-
- return 0;
-}
-
-static int gpio_regs_open(struct inode *inode, struct file *file)
-{
- return single_open(file, gpio_regs_show, NULL);
-}
-
-static const struct file_operations gpio_regs_operations = {
- .open = gpio_regs_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init gpio_debugfs_init(void)
-{
- (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
- NULL, NULL, &gpio_regs_operations);
- return 0;
-}
-subsys_initcall(gpio_debugfs_init);
-
-#endif
--
2.11.0
^ permalink raw reply related
* Re: [PATCH] iio:temperature:Add irq and threshold events support for TI TMP007 sensor
From: Mani Sadhasivam @ 2017-01-22 15:09 UTC (permalink / raw)
To: Peter Meerwald-Stadler
Cc: jic23-DgEjT+Ai2ygdnm+yROfE0A, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <alpine.DEB.2.02.1701221002030.31271-jW+XmwGofnusTnJN9+BGXg@public.gmane.org>
Thanks Peter for your suggestions.
On January 22, 2017 2:49:06 PM GMT+05:30, Peter Meerwald-Stadler <pmeerw@pmeerw.net> wrote:
>
>I'd prefer subject "iio:temperature:tmp007: Add irq and threshold
>events support"
>
ACK
>> This patch adds support for ALERT irq and limit threshold events for
>TI TMP007 - 16 bit IR thermopile sensor
>> with integrated math engine.
>>
>> Following threshold events are supported:
>> 1. TObj high limit
>> 2. TObj low limit
>> 3. TDie high limit
>> 4. TDie low limit
>
>comments below
>I suggest to separate clearup from actually adding events support, so
>two
>patches
Sure. I'll create a separate patch for cleanup later on.
>it would be nice if the driver can operate without irq also (irq is
>optional in DT...)
>
I think the driver can work without interrupt.
>> Signed-off-by: Manivannan Sadhasivam <manivannanece23@gmail.com>
>> ---
>
>note: this applies on top of patch...
>
>> .../devicetree/bindings/iio/temperature/tmp007.txt | 8 +
>> drivers/iio/temperature/tmp007.c | 334
>++++++++++++++++++---
>> 2 files changed, 304 insertions(+), 38 deletions(-)
>>
>> diff --git
>a/Documentation/devicetree/bindings/iio/temperature/tmp007.txt
>b/Documentation/devicetree/bindings/iio/temperature/tmp007.txt
>> index 3b8f41f..07c1658 100644
>> --- a/Documentation/devicetree/bindings/iio/temperature/tmp007.txt
>> +++ b/Documentation/devicetree/bindings/iio/temperature/tmp007.txt
>> @@ -18,10 +18,18 @@ Required properties:
>> 1 SDA 0x46
>> 1 SCL 0x47
>>
>> +Optional properties:
>> +
>> + - interrupt-parent: should be the phandle for the interrupt
>controller
>> +
>> + - interrupts: interrupt mapping for GPIO IRQ
>> +
>> Example:
>>
>> tmp007@40 {
>> compatible = "ti,tmp007";
>> reg = <0x40>;
>> + interrupt-parent = <&gpio0>;
>> + interrupts = <5 8>;
>
>why are there two GPIOs?
>
Ahh. I wanted to specify level triggering there. But not needed as it is being specified in probe itself.
Acked.
>> };
>>
>> diff --git a/drivers/iio/temperature/tmp007.c
>b/drivers/iio/temperature/tmp007.c
>> index 24c6c16..73b5b8d 100644
>> --- a/drivers/iio/temperature/tmp007.c
>> +++ b/drivers/iio/temperature/tmp007.c
>> @@ -11,9 +11,10 @@
>> *
>> * (7-bit I2C slave address (0x40 - 0x47), changeable via ADR pins)
>> *
>> - * Note: This driver assumes that the sensor has been calibrated
>beforehand
>> - *
>> - * TODO: ALERT irq, limit threshold events
>> + * Note:
>> + * 1. This driver assumes that the sensor has been calibrated
>beforehand
>> + * 2. Limit threshold events are enabled at the start
>> + * 3. Operating mode: INT
>> *
>> */
>>
>> @@ -24,35 +25,49 @@
>> #include <linux/pm.h>
>> #include <linux/bitops.h>
>> #include <linux/of.h>
>> +#include <linux/irq.h>
>> +#include <linux/interrupt.h>
>>
>> #include <linux/iio/iio.h>
>> #include <linux/iio/sysfs.h>
>> -
>> -#define TMP007_TDIE 0x01
>> -#define TMP007_CONFIG 0x02
>> -#define TMP007_TOBJECT 0x03
>> -#define TMP007_STATUS 0x04
>> -#define TMP007_STATUS_MASK 0x05
>> -#define TMP007_MANUFACTURER_ID 0x1e
>> -#define TMP007_DEVICE_ID 0x1f
>> -
>> -#define TMP007_CONFIG_CONV_EN BIT(12)
>> -#define TMP007_CONFIG_COMP_EN BIT(5)
>> -#define TMP007_CONFIG_TC_EN BIT(6)
>> -#define TMP007_CONFIG_CR_MASK GENMASK(11, 9)
>> -#define TMP007_CONFIG_CR_SHIFT 9
>> -
>> -#define TMP007_STATUS_CONV_READY BIT(14)
>> -#define TMP007_STATUS_DATA_VALID BIT(9)
>> -
>> -#define TMP007_MANUFACTURER_MAGIC 0x5449
>> -#define TMP007_DEVICE_MAGIC 0x0078
>> -
>> -#define TMP007_TEMP_SHIFT 2
>> +#include <linux/iio/events.h>
>> +
>> +#define TMP007_TDIE 0x01
>
>this has a lot of clutter; the patch also reformats the #defines by
>adding
>whitespace; don't do this in the same patch
>
Ack
>> +#define TMP007_CONFIG 0x02
>> +#define TMP007_TOBJECT 0x03
>> +#define TMP007_STATUS 0x04
>> +#define TMP007_STATUS_MASK 0x05
>> +#define TMP007_TOBJ_HIGH_LIMIT 0x06
>> +#define TMP007_TOBJ_LOW_LIMIT 0x07
>> +#define TMP007_TDIE_HIGH_LIMIT 0x08
>> +#define TMP007_TDIE_LOW_LIMIT 0x09
>> +#define TMP007_MANUFACTURER_ID 0x1e
>> +#define TMP007_DEVICE_ID 0x1f
>> +
>> +#define TMP007_CONFIG_CONV_EN BIT(12)
>> +#define TMP007_CONFIG_TC_EN BIT(6)
>> +#define TMP007_CONFIG_CR_MASK GENMASK(11, 9)
>> +#define TMP007_CONFIG_ALERT_EN BIT(8)
>> +#define TMP007_CONFIG_CR_SHIFT 9
>> +
>> +/* Status register flags */
>> +#define TMP007_STATUS_ALERT BIT(15)
>> +#define TMP007_STATUS_CONV_READY BIT(14)
>> +#define TMP007_STATUS_OHF BIT(13)
>> +#define TMP007_STATUS_OLF BIT(12)
>> +#define TMP007_STATUS_LHF BIT(11)
>> +#define TMP007_STATUS_LLF BIT(10)
>> +#define TMP007_STATUS_DATA_VALID BIT(9)
>> +
>> +#define TMP007_MANUFACTURER_MAGIC 0x5449
>> +#define TMP007_DEVICE_MAGIC 0x0078
>> +
>> +#define TMP007_TEMP_SHIFT 2
>>
>> struct tmp007_data {
>> struct i2c_client *client;
>> u16 config;
>> + u16 status_mask;
>> };
>>
>> static const int tmp007_avgs[5][2] = { {4, 0}, {2, 0}, {1, 0},
>> @@ -70,7 +85,7 @@ static int tmp007_read_temperature(struct
>tmp007_data *data, u8 reg)
>> return ret;
>> if ((ret & TMP007_STATUS_CONV_READY) &&
>> !(ret & TMP007_STATUS_DATA_VALID))
>> - break;
>
>another unrelated cleanup
Ack
>
>> + break;
>> msleep(100);
>> }
>>
>> @@ -156,6 +171,185 @@ static int tmp007_write_raw(struct iio_dev
>*indio_dev,
>> return -EINVAL;
>> }
>>
>> +static irqreturn_t tmp007_interrupt_handler(int irq, void *private)
>> +{
>> + struct iio_dev *indio_dev = private;
>> + struct tmp007_data *data = iio_priv(indio_dev);
>> + int ret;
>> +
>> + ret = i2c_smbus_read_word_swapped(data->client, TMP007_STATUS);
>> + if (ret < 0)
>
>|| !(ret & (_STATUSS_OHF | STATUS_OLF | ..))
>
Ack
>> + return IRQ_NONE;
>> +
>> + if (ret & TMP007_STATUS_OHF)
>> + iio_push_event(indio_dev,
>> + IIO_MOD_EVENT_CODE(IIO_TEMP, 0,
>> + IIO_MOD_TEMP_OBJECT,
>> + IIO_EV_TYPE_THRESH,
>> + IIO_EV_DIR_RISING),
>> + iio_get_time_ns(indio_dev));
>> +
>> + if (ret & TMP007_STATUS_OLF)
>> + iio_push_event(indio_dev,
>> + IIO_MOD_EVENT_CODE(IIO_TEMP, 0,
>> + IIO_MOD_TEMP_OBJECT,
>> + IIO_EV_TYPE_THRESH,
>> + IIO_EV_DIR_FALLING),
>> + iio_get_time_ns(indio_dev));
>> +
>> + if (ret & TMP007_STATUS_LHF)
>> + iio_push_event(indio_dev,
>> + IIO_MOD_EVENT_CODE(IIO_TEMP, 0,
>> + IIO_MOD_TEMP_AMBIENT,
>> + IIO_EV_TYPE_THRESH,
>> + IIO_EV_DIR_RISING),
>> + iio_get_time_ns(indio_dev));
>> +
>> + if (ret & TMP007_STATUS_LLF)
>> + iio_push_event(indio_dev,
>> + IIO_MOD_EVENT_CODE(IIO_TEMP, 0,
>> + IIO_MOD_TEMP_AMBIENT,
>> + IIO_EV_TYPE_THRESH,
>> + IIO_EV_DIR_FALLING),
>> + iio_get_time_ns(indio_dev));
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static int tmp007_write_event_config(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan, enum iio_event_type type,
>> + enum iio_event_direction dir, int state)
>> +{
>> + struct tmp007_data *data = iio_priv(indio_dev);
>> + unsigned int status_mask;
>> + int ret;
>> +
>> + switch (chan->channel2) {
>> + case IIO_MOD_TEMP_AMBIENT:
>> + if (dir == IIO_EV_DIR_RISING)
>> + status_mask = TMP007_STATUS_LHF;
>> + else
>> + status_mask = TMP007_STATUS_LLF;
>> + break;
>> + case IIO_MOD_TEMP_OBJECT:
>> + if (dir == IIO_EV_DIR_RISING)
>> + status_mask = TMP007_STATUS_OHF;
>> + else
>> + status_mask = TMP007_STATUS_OLF;
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> +
>
>mutex around this?
Ack
>
>> + ret = i2c_smbus_read_word_swapped(data->client,
>TMP007_STATUS_MASK);
>> + if (ret < 0)
>> + return ret;
>> +
>> + if (state)
>> + ret |= status_mask;
>> + else
>> + ret &= ~status_mask;
>> +
>> + return i2c_smbus_write_word_swapped(data->client,
>TMP007_STATUS_MASK,
>> + data->status_mask = ret);
>> +}
>> +
>> +static int tmp007_read_event_config(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan, enum iio_event_type type,
>> + enum iio_event_direction dir)
>> +{
>> + struct tmp007_data *data = iio_priv(indio_dev);
>> + unsigned int mask;
>> +
>> + switch (chan->channel2) {
>> + case IIO_MOD_TEMP_AMBIENT:
>> + if (dir == IIO_EV_DIR_RISING)
>> + mask = TMP007_STATUS_LHF;
>> + else
>> + mask = TMP007_STATUS_LLF;
>> + break;
>> + case IIO_MOD_TEMP_OBJECT:
>> + if (dir == IIO_EV_DIR_RISING)
>> + mask = TMP007_STATUS_OHF;
>> + else
>> + mask = TMP007_STATUS_OLF;
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> +
>> + return (bool)(data->status_mask & mask);
>
>return type is int, maybe use !! to force to 0/1
>
>return !!(data->status_mask & mask);
Ack
>
>> +}
>> +
>> +static int tmp007_read_thresh(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan, enum iio_event_type type,
>> + enum iio_event_direction dir, enum iio_event_info info,
>> + int *val, int *val2)
>> +{
>> + struct tmp007_data *data = iio_priv(indio_dev);
>> + int ret;
>> + u8 reg;
>> +
>> + switch (chan->channel2) {
>> + case IIO_MOD_TEMP_AMBIENT: /* LSB: 0.5 degree Celsius */
>> + if (dir == IIO_EV_DIR_RISING)
>> + reg = TMP007_TDIE_HIGH_LIMIT;
>> + else
>> + reg = TMP007_TDIE_LOW_LIMIT;
>> + break;
>> + case IIO_MOD_TEMP_OBJECT:
>> + if (dir == IIO_EV_DIR_RISING)
>> + reg = TMP007_TOBJ_HIGH_LIMIT;
>> + else
>> + reg = TMP007_TOBJ_LOW_LIMIT;
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> +
>> + ret = i2c_smbus_read_word_swapped(data->client, reg);
>> + if (ret < 0)
>> + return ret;
>> +
>> + /* Shift length 7 bits = 6(15:6) + 1(0.5 LSB) */
>> + *val = sign_extend32(ret, 15) >> 7;
>> +
>> + return IIO_VAL_INT;
>> +}
>> +
>> +static int tmp007_write_thresh(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan, enum iio_event_type type,
>> + enum iio_event_direction dir, enum iio_event_info info,
>> + int val, int val2)
>> +{
>> + struct tmp007_data *data = iio_priv(indio_dev);
>> + u8 reg;
>> +
>> + switch (chan->channel2) {
>> + case IIO_MOD_TEMP_AMBIENT:
>> + if (dir == IIO_EV_DIR_RISING)
>> + reg = TMP007_TDIE_HIGH_LIMIT;
>> + else
>> + reg = TMP007_TDIE_LOW_LIMIT;
>> + break;
>> + case IIO_MOD_TEMP_OBJECT:
>> + if (dir == IIO_EV_DIR_RISING)
>> + reg = TMP007_TOBJ_HIGH_LIMIT;
>> + else
>> + reg = TMP007_TOBJ_LOW_LIMIT;
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> +
>> + /* Full scale value is +/- 256 degree Celsius */
>
>I guess we want to specify milli degree Celsius according to
>sysfs-bus-iio
>for in_temp_raw
>
I didn't get what your are suggesting. Could you please explain?
>> + if (val < -256 || val > 255)
>> + return -EINVAL;
>> +
>> + /* Shift length 7 bits = 6(15:6) + 1(0.5 LSB) */
>> + return i2c_smbus_write_word_swapped(data->client, reg, (val << 7));
>> +}
>> +
>> static IIO_CONST_ATTR(sampling_frequency_available, "4 2 1 0.5
>0.25");
>>
>> static struct attribute *tmp007_attributes[] = {
>> @@ -167,6 +361,36 @@ static const struct attribute_group
>tmp007_attribute_group = {
>> .attrs = tmp007_attributes,
>> };
>>
>> +static const struct iio_event_spec tmp007_obj_event[] = {
>> + {
>> + .type = IIO_EV_TYPE_THRESH,
>> + .dir = IIO_EV_DIR_RISING,
>> + .mask_separate = BIT(IIO_EV_INFO_VALUE) |
>> + BIT(IIO_EV_INFO_ENABLE),
>> + },
>> + {
>> + .type = IIO_EV_TYPE_THRESH,
>> + .dir = IIO_EV_DIR_FALLING,
>> + .mask_separate = BIT(IIO_EV_INFO_VALUE) |
>> + BIT(IIO_EV_INFO_ENABLE),
>> + },
>> +};
>> +
>> +static const struct iio_event_spec tmp007_die_event[] = {
>> + {
>> + .type = IIO_EV_TYPE_THRESH,
>> + .dir = IIO_EV_DIR_RISING,
>> + .mask_separate = BIT(IIO_EV_INFO_VALUE) |
>> + BIT(IIO_EV_INFO_ENABLE),
>> + },
>> + {
>> + .type = IIO_EV_TYPE_THRESH,
>> + .dir = IIO_EV_DIR_FALLING,
>> + .mask_separate = BIT(IIO_EV_INFO_VALUE) |
>> + BIT(IIO_EV_INFO_ENABLE),
>> + },
>> +};
>> +
>> static const struct iio_chan_spec tmp007_channels[] = {
>> {
>> .type = IIO_TEMP,
>> @@ -175,6 +399,8 @@ static const struct iio_chan_spec
>tmp007_channels[] = {
>> .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
>> BIT(IIO_CHAN_INFO_SCALE),
>> .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
>> + .event_spec = tmp007_die_event,
>> + .num_event_specs = ARRAY_SIZE(tmp007_die_event),
>> },
>> {
>> .type = IIO_TEMP,
>> @@ -183,12 +409,18 @@ static const struct iio_chan_spec
>tmp007_channels[] = {
>> .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
>> BIT(IIO_CHAN_INFO_SCALE),
>> .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
>> - }
>> + .event_spec = tmp007_obj_event,
>> + .num_event_specs = ARRAY_SIZE(tmp007_obj_event),
>> + },
>> };
>>
>> static const struct iio_info tmp007_info = {
>> - .read_raw = tmp007_read_raw,
>> - .write_raw = tmp007_write_raw,
>> + .read_raw = &tmp007_read_raw,
>> + .write_raw = &tmp007_write_raw,
>
>unrelated change, no need for & for a function
Ack
>
>> + .read_event_config = &tmp007_read_event_config,
>> + .write_event_config = &tmp007_write_event_config,
>> + .read_event_value = &tmp007_read_thresh,
>> + .write_event_value = &tmp007_write_thresh,
>> .attrs = &tmp007_attribute_group,
>> .driver_module = THIS_MODULE,
>> };
>> @@ -214,7 +446,6 @@ static int tmp007_probe(struct i2c_client
>*client,
>> struct tmp007_data *data;
>> struct iio_dev *indio_dev;
>> int ret;
>> - u16 status;
>>
>> if (!i2c_check_functionality(client->adapter,
>I2C_FUNC_SMBUS_WORD_DATA))
>> return -EOPNOTSUPP;
>> @@ -243,8 +474,8 @@ static int tmp007_probe(struct i2c_client
>*client,
>> /*
>> * Set Configuration register:
>> * 1. Conversion ON
>> - * 2. Comparator mode
>> - * 3. Transient correction enable
>> + * 2. Transient correction enable
>> + * 3. ALERT enable
>> */
>>
>> ret = i2c_smbus_read_word_swapped(data->client, TMP007_CONFIG);
>> @@ -252,7 +483,7 @@ static int tmp007_probe(struct i2c_client
>*client,
>> return ret;
>>
>> data->config = ret;
>> - data->config |= (TMP007_CONFIG_CONV_EN | TMP007_CONFIG_COMP_EN |
>TMP007_CONFIG_TC_EN);
>> + data->config |= (TMP007_CONFIG_CONV_EN | TMP007_CONFIG_TC_EN |
>TMP007_CONFIG_ALERT_EN);
>>
>> ret = i2c_smbus_write_word_swapped(data->client, TMP007_CONFIG,
>> data->config);
>> @@ -260,22 +491,39 @@ static int tmp007_probe(struct i2c_client
>*client,
>> return ret;
>>
>> /*
>> + * Only the following flags can activate ALERT pin. Data
>conversion/validity flags
>> + * flags can still be polled for getting temperature data
>> + *
>> * Set Status Mask register:
>> - * 1. Conversion ready enable
>> - * 2. Data valid enable
>> + * 1. Object temperature high limit enable
>> + * 2. Object temperature low limit enable
>> + * 3. TDIE temperature high limit enable
>> + * 4. TDIE temperature low limit enable
>> */
>>
>> ret = i2c_smbus_read_word_swapped(data->client,
>TMP007_STATUS_MASK);
>> if (ret < 0)
>> goto error_powerdown;
>>
>> - status = ret;
>> - status |= (TMP007_STATUS_CONV_READY | TMP007_STATUS_DATA_VALID);
>> + data->status_mask = ret;
>> + data->status_mask |= (TMP007_STATUS_OHF | TMP007_STATUS_OLF
>> + | TMP007_STATUS_LHF | TMP007_STATUS_LLF);
>>
>> - ret = i2c_smbus_write_word_swapped(data->client,
>TMP007_STATUS_MASK, status);
>> + ret = i2c_smbus_write_word_swapped(data->client,
>TMP007_STATUS_MASK, data->status_mask);
>> if (ret < 0)
>> goto error_powerdown;
>>
>> + if (client->irq) {
>> + ret = devm_request_threaded_irq(&client->dev, client->irq,
>> + NULL, tmp007_interrupt_handler,
>> + IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
>> + tmp007_id->name, indio_dev);
>> + if (ret) {
>> + dev_err(&client->dev, "irq request error %d\n", -ret);
>> + goto error_powerdown;
>> + }
>> + }
>
>what happens when there is no IRQ? it would be nice to still use the
>driver (without event capability)
>
I guess if (client->irq) checks for it. And believe it works without interrupt as well. Correct me if I'm wrong.
>> +
>> return iio_device_register(indio_dev);
>>
>> error_powerdown:
>> @@ -312,6 +560,16 @@ static int tmp007_resume(struct device *dev)
>> return i2c_smbus_write_word_swapped(data->client, TMP007_CONFIG,
>> data->config | TMP007_CONFIG_CONV_EN);
>> }
>> +#else
>
>this seems to be unrelated to the patch
>
Ack
>> +static int tmp007_suspend(struct device *dev)
>> +{
>> + return 0;
>> +}
>> +
>> +static int tmp007_resume(struct device *dev)
>> +{
>> + return 0;
>> +}
>> #endif
>>
>> static SIMPLE_DEV_PM_OPS(tmp007_pm_ops, tmp007_suspend,
>tmp007_resume);
>>
--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
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^ permalink raw reply
* Re: [PATCH 1/2] iio: imu: st_lsm6dsx: add possibility to select drdy pin
From: Lorenzo Bianconi @ 2017-01-22 15:20 UTC (permalink / raw)
To: Jonathan Cameron
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, lorenzo.bianconi-qxv4g6HH51o
In-Reply-To: <3ca71ff6-fa9e-449a-8a21-7607ca2c2c55-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Hi Jonathan,
thanks for the review :)
> On 22/01/17 10:30, Lorenzo Bianconi wrote:
> > Add capability to route data ready signal on pin 1 or pin 2 of the package
> >
> > Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi-qxv4g6HH51o@public.gmane.org>
> > ---
> > drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 66 +++++++++++++++++++++++++---
> > 1 file changed, 60 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
> > index f869dfa..bc50164 100644
> > --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
> > +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
> > @@ -37,11 +37,14 @@
> > #include <linux/iio/iio.h>
> > #include <linux/iio/sysfs.h>
> >
> > +#include <linux/platform_data/st_sensors_pdata.h>
> > +
> > #include "st_lsm6dsx.h"
> >
> > #define ST_LSM6DSX_REG_ACC_DEC_MASK GENMASK(2, 0)
> > #define ST_LSM6DSX_REG_GYRO_DEC_MASK GENMASK(5, 3)
> > #define ST_LSM6DSX_REG_INT1_ADDR 0x0d
> > +#define ST_LSM6DSX_REG_INT2_ADDR 0x0e
> > #define ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK BIT(3)
> > #define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f
> > #define ST_LSM6DSX_REG_RESET_ADDR 0x12
> > @@ -532,10 +535,63 @@ static const struct iio_info st_lsm6dsx_gyro_info = {
> >
> > static const unsigned long st_lsm6dsx_available_scan_masks[] = {0x7, 0x0};
> >
> > +#ifdef CONFIG_OF
> Perhaps rely on the -ENOSYS return from
> of_property_read_u32 stub instead of having the ifdefs around something so
> simple.
ack, will do in v2
>
> > +static int st_lsm6dsx_of_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin)
> > +{
> > + struct device_node *np = hw->dev->of_node;
> > + int err;
> > +
> > + if (!np)
> > + return -EINVAL;
> > +
> > + err = of_property_read_u32(np, "st,drdy-int-pin", drdy_pin);
> > + if (err == -ENODATA) {
> > + /* if the property has not been specified use default value */
> > + *drdy_pin = 1;
> > + err = 0;
> > + }
> > +
> > + return err;
> > +}
> > +#else
> > +static int st_lsm6dsx_of_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin)
> > +{
> > + return -EINVAL;
> > +}
> > +#endif /* CONFIG_OF */
> > +
> > +static int st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, u8 *drdy_reg)
> > +{
> > + int err = 0, drdy_pin;
> > +
> > + if (st_lsm6dsx_of_get_drdy_pin(hw, &drdy_pin) < 0) {
> > + struct st_sensors_platform_data *pdata;
> > + struct device *dev = hw->dev;
> > +
> > + pdata = (struct st_sensors_platform_data *)dev->platform_data;
> > + drdy_pin = pdata ? pdata->drdy_int_pin : 1;
> > + }
> > +
> > + switch (drdy_pin) {
> > + case 1:
> > + *drdy_reg = ST_LSM6DSX_REG_INT1_ADDR;
> > + break;
> > + case 2:
> > + *drdy_reg = ST_LSM6DSX_REG_INT2_ADDR;
> > + break;
> > + default:
> > + dev_err(hw->dev, "unsupported data ready pin\n");
> > + err = -EINVAL;
> > + break;
> > + }
> > +
> > + return err;
> > +}
> > +
> > static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw)
> > {
> > + u8 data, drdy_int_reg;
> > int err;
> > - u8 data;
> >
> > data = ST_LSM6DSX_REG_RESET_MASK;
> > err = hw->tf->write(hw->dev, ST_LSM6DSX_REG_RESET_ADDR, sizeof(data),
> > @@ -563,14 +619,12 @@ static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw)
> > return err;
> >
> > /* enable FIFO watermak interrupt */
> > - err = st_lsm6dsx_write_with_mask(hw, ST_LSM6DSX_REG_INT1_ADDR,
> > - ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK, 1);
> > + err = st_lsm6dsx_get_drdy_reg(hw, &drdy_int_reg);
> > if (err < 0)
> > return err;
> >
> > - /* redirect INT2 on INT1 */
> > - return st_lsm6dsx_write_with_mask(hw, ST_LSM6DSX_REG_INT2_ON_INT1_ADDR,
> > - ST_LSM6DSX_REG_INT2_ON_INT1_MASK, 1);
> Does removing this potentially break existing setups?
>
No, it doesn't since INT2 was not configured yet
> > + return st_lsm6dsx_write_with_mask(hw, drdy_int_reg,
> > + ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK, 1);
> > }
> >
> > static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw,
> >
>
Regards,
Lorenzo
--
UNIX is Sexy: who | grep -i blonde | talk; cd ~; wine; talk; touch; unzip; touch; strip; gasp; finger; gasp; mount; fsck; more; yes; gasp; umount; make clean; sleep
^ permalink raw reply
* [PATCH v2 1/6] ARM: tegra: nyan: Use proper IRQ type definitions
From: Paul Kocialkowski @ 2017-01-22 15:47 UTC (permalink / raw)
To: linux-tegra-u79uwXL29TY76Z2rM5mHXA
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Jon Hunter, Stephen Warren,
Thierry Reding, Alexandre Courbot, Mikko Perttunen, Peter Rosin,
Paul Kocialkowski
This switches a few interrupt definitions that were using
GPIO_ACTIVE_HIGH as IRQ type, which is invalid.
This is mostly a cosmetic change, that doesn't affect any driver.
Signed-off-by: Paul Kocialkowski <contact-W9ppeneeCTY@public.gmane.org>
---
arch/arm/boot/dts/tegra124-nyan.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index eabfa655a3cd..ef430aa30152 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -65,7 +65,7 @@
compatible = "maxim,max98090";
reg = <0x10>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+ interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
};
temperature-sensor@4c {
@@ -331,7 +331,7 @@
reg = <0x9>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(J, 0)
- GPIO_ACTIVE_HIGH>;
+ IRQ_TYPE_EDGE_BOTH>;
ti,ac-detect-gpios = <&gpio
TEGRA_GPIO(J, 0)
GPIO_ACTIVE_HIGH>;
--
2.11.0
--
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^ permalink raw reply related
* [PATCH v2 2/6] ARM: tegra: nyan: Use external control for bq24735 charger
From: Paul Kocialkowski @ 2017-01-22 15:47 UTC (permalink / raw)
To: linux-tegra-u79uwXL29TY76Z2rM5mHXA
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Jon Hunter, Stephen Warren,
Thierry Reding, Alexandre Courbot, Mikko Perttunen, Peter Rosin,
Paul Kocialkowski
In-Reply-To: <20170122154753.31942-1-contact-W9ppeneeCTY@public.gmane.org>
Nyan boards come with an embedded controller that controls when to
enable and disable the charge. Thus, it should not be left up to the
kernel to handle that.
Using the ti,external-control property allows specifying this use-case.
Signed-off-by: Paul Kocialkowski <contact-W9ppeneeCTY@public.gmane.org>
---
arch/arm/boot/dts/tegra124-nyan.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index ef430aa30152..5cf987b5401e 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -335,6 +335,7 @@
ti,ac-detect-gpios = <&gpio
TEGRA_GPIO(J, 0)
GPIO_ACTIVE_HIGH>;
+ ti,external-control;
};
battery: sbs-battery@b {
--
2.11.0
--
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^ permalink raw reply related
* [PATCH v2 3/6] ARM: tegra: nyan-big: Include compatible revisions for proper detection
From: Paul Kocialkowski @ 2017-01-22 15:47 UTC (permalink / raw)
To: linux-tegra
Cc: linux-kernel, linux-arm-kernel, devicetree, Jon Hunter,
Stephen Warren, Thierry Reding, Alexandre Courbot,
Mikko Perttunen, Peter Rosin, Paul Kocialkowski
In-Reply-To: <20170122154753.31942-1-contact@paulk.fr>
Depthcharge (the payload used with cros devices) will attempt to detect
boards using their revision. This includes all the known revisions for
the nyan-big board so that the dtb can be selected preferably.
Defining compatibly revisions allows depthcharge to select the kernel
via the revision it detects instead of using the default kernel. This
allows having a FIT image with multiple kernels for multiple devices.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
arch/arm/boot/dts/tegra124-nyan-big.dts | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
index 67d7cfb32541..f12ece9b76a6 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -6,7 +6,12 @@
/ {
model = "Acer Chromebook 13 CB5-311";
- compatible = "google,nyan-big", "nvidia,tegra124";
+ compatible = "google,nyan-big-rev7", "google,nyan-big-rev6",
+ "google,nyan-big-rev5", "google,nyan-big-rev4",
+ "google,nyan-big-rev3", "google,nyan-big-rev2",
+ "google,nyan-big-rev5", "google,nyan-big-rev4",
+ "google,nyan-big-rev1", "google,nyan-big-rev0",
+ "google,nyan-big", "google,nyan", "nvidia,tegra124";
panel: panel {
compatible = "auo,b133xtn01";
--
2.11.0
^ permalink raw reply related
* [PATCH v2 4/6] ARM: tegra: nyan-blaze: Include compatible revisions for proper detection
From: Paul Kocialkowski @ 2017-01-22 15:47 UTC (permalink / raw)
To: linux-tegra-u79uwXL29TY76Z2rM5mHXA
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Jon Hunter, Stephen Warren,
Thierry Reding, Alexandre Courbot, Mikko Perttunen, Peter Rosin,
Paul Kocialkowski
In-Reply-To: <20170122154753.31942-1-contact-W9ppeneeCTY@public.gmane.org>
Depthcharge (the payload used with cros devices) will attempt to detect
boards using their revision. This includes all the known revisions for
the nyan-blaze board so that the dtb can be selected preferably.
Defining compatibly revisions allows depthcharge to select the kernel
via the revision it detects instead of using the default kernel. This
allows having a FIT image with multiple kernels for multiple devices.
Signed-off-by: Paul Kocialkowski <contact-W9ppeneeCTY@public.gmane.org>
---
arch/arm/boot/dts/tegra124-nyan-blaze.dts | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
index c9582361c26e..aca0828115eb 100644
--- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
@@ -6,7 +6,13 @@
/ {
model = "HP Chromebook 14";
- compatible = "google,nyan-blaze", "google,nyan", "nvidia,tegra124";
+ compatible = "google,nyan-blaze-rev10", "google,nyan-blaze-rev9",
+ "google,nyan-blaze-rev8", "google,nyan-blaze-rev7",
+ "google,nyan-blaze-rev6", "google,nyan-blaze-rev5",
+ "google,nyan-blaze-rev4", "google,nyan-blaze-rev3",
+ "google,nyan-blaze-rev2", "google,nyan-blaze-rev1",
+ "google,nyan-blaze-rev0", "google,nyan-blaze",
+ "google,nyan", "nvidia,tegra124";
panel: panel {
compatible = "samsung,ltn140at29-301";
--
2.11.0
^ permalink raw reply related
* [PATCH v2 5/6] ARM: tegra: nyan-big: Proper pinmux for TPM i2c
From: Paul Kocialkowski @ 2017-01-22 15:47 UTC (permalink / raw)
To: linux-tegra
Cc: linux-kernel, linux-arm-kernel, devicetree, Jon Hunter,
Stephen Warren, Thierry Reding, Alexandre Courbot,
Mikko Perttunen, Peter Rosin, Paul Kocialkowski
In-Reply-To: <20170122154753.31942-1-contact@paulk.fr>
This corrects the pinmux for accessing the TPM over the i2c line.
Thus, it allows correctly probing the module, that previously failed with i2c
errors.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
arch/arm/boot/dts/tegra124-nyan-big.dts | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
index f12ece9b76a6..03eedf86dc48 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -1103,19 +1103,19 @@
};
cam_i2c_scl_pbb1 {
nvidia,pins = "cam_i2c_scl_pbb1";
- nvidia,function = "rsvd3";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
cam_i2c_sda_pbb2 {
nvidia,pins = "cam_i2c_sda_pbb2";
- nvidia,function = "rsvd3";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
pbb3 {
nvidia,pins = "pbb3";
--
2.11.0
^ permalink raw reply related
* [PATCH v2 6/6] ARM: tegra: nyan-blaze: Proper pinmux for TPM i2c
From: Paul Kocialkowski @ 2017-01-22 15:47 UTC (permalink / raw)
To: linux-tegra
Cc: linux-kernel, linux-arm-kernel, devicetree, Jon Hunter,
Stephen Warren, Thierry Reding, Alexandre Courbot,
Mikko Perttunen, Peter Rosin, Jerome Coste
In-Reply-To: <20170122154753.31942-1-contact@paulk.fr>
From: Jerome Coste <jerome.coste@etu.utc.fr>
This corrects the pinmux for accessing the TPM over the i2c line.
Thus, it allows correctly probing the module, that previously failed with i2c
errors.
---
arch/arm/boot/dts/tegra124-nyan-blaze.dts | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
index aca0828115eb..9df25ca5ab83 100644
--- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
@@ -1100,19 +1100,19 @@
};
cam_i2c_scl_pbb1 {
nvidia,pins = "cam_i2c_scl_pbb1";
- nvidia,function = "rsvd3";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
cam_i2c_sda_pbb2 {
nvidia,pins = "cam_i2c_sda_pbb2";
- nvidia,function = "rsvd3";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
pbb3 {
nvidia,pins = "pbb3";
--
2.11.0
^ permalink raw reply related
* Re: [PATCH 1/2] iio: imu: st_lsm6dsx: add possibility to select drdy pin
From: Jonathan Cameron @ 2017-01-22 15:54 UTC (permalink / raw)
To: Lorenzo Bianconi
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, lorenzo.bianconi-qxv4g6HH51o
In-Reply-To: <20170122152033.o5crgdbsemdmv6rk-iOgT3W1YzDsjz3NcCDvlmNHuzzzSOjJt@public.gmane.org>
On 22/01/17 15:20, Lorenzo Bianconi wrote:
> Hi Jonathan,
>
> thanks for the review :)
>
>> On 22/01/17 10:30, Lorenzo Bianconi wrote:
>>> Add capability to route data ready signal on pin 1 or pin 2 of the package
>>>
>>> Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi-qxv4g6HH51o@public.gmane.org>
>>> ---
>>> drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 66 +++++++++++++++++++++++++---
>>> 1 file changed, 60 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
>>> index f869dfa..bc50164 100644
>>> --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
>>> +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
>>> @@ -37,11 +37,14 @@
>>> #include <linux/iio/iio.h>
>>> #include <linux/iio/sysfs.h>
>>>
>>> +#include <linux/platform_data/st_sensors_pdata.h>
>>> +
>>> #include "st_lsm6dsx.h"
>>>
>>> #define ST_LSM6DSX_REG_ACC_DEC_MASK GENMASK(2, 0)
>>> #define ST_LSM6DSX_REG_GYRO_DEC_MASK GENMASK(5, 3)
>>> #define ST_LSM6DSX_REG_INT1_ADDR 0x0d
>>> +#define ST_LSM6DSX_REG_INT2_ADDR 0x0e
>>> #define ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK BIT(3)
>>> #define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f
>>> #define ST_LSM6DSX_REG_RESET_ADDR 0x12
>>> @@ -532,10 +535,63 @@ static const struct iio_info st_lsm6dsx_gyro_info = {
>>>
>>> static const unsigned long st_lsm6dsx_available_scan_masks[] = {0x7, 0x0};
>>>
>>> +#ifdef CONFIG_OF
>> Perhaps rely on the -ENOSYS return from
>> of_property_read_u32 stub instead of having the ifdefs around something so
>> simple.
>
> ack, will do in v2
>
>>
>>> +static int st_lsm6dsx_of_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin)
>>> +{
>>> + struct device_node *np = hw->dev->of_node;
>>> + int err;
>>> +
>>> + if (!np)
>>> + return -EINVAL;
>>> +
>>> + err = of_property_read_u32(np, "st,drdy-int-pin", drdy_pin);
>>> + if (err == -ENODATA) {
>>> + /* if the property has not been specified use default value */
>>> + *drdy_pin = 1;
>>> + err = 0;
>>> + }
>>> +
>>> + return err;
>>> +}
>>> +#else
>>> +static int st_lsm6dsx_of_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin)
>>> +{
>>> + return -EINVAL;
>>> +}
>>> +#endif /* CONFIG_OF */
>>> +
>>> +static int st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, u8 *drdy_reg)
>>> +{
>>> + int err = 0, drdy_pin;
>>> +
>>> + if (st_lsm6dsx_of_get_drdy_pin(hw, &drdy_pin) < 0) {
>>> + struct st_sensors_platform_data *pdata;
>>> + struct device *dev = hw->dev;
>>> +
>>> + pdata = (struct st_sensors_platform_data *)dev->platform_data;
>>> + drdy_pin = pdata ? pdata->drdy_int_pin : 1;
>>> + }
>>> +
>>> + switch (drdy_pin) {
>>> + case 1:
>>> + *drdy_reg = ST_LSM6DSX_REG_INT1_ADDR;
>>> + break;
>>> + case 2:
>>> + *drdy_reg = ST_LSM6DSX_REG_INT2_ADDR;
>>> + break;
>>> + default:
>>> + dev_err(hw->dev, "unsupported data ready pin\n");
>>> + err = -EINVAL;
>>> + break;
>>> + }
>>> +
>>> + return err;
>>> +}
>>> +
>>> static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw)
>>> {
>>> + u8 data, drdy_int_reg;
>>> int err;
>>> - u8 data;
>>>
>>> data = ST_LSM6DSX_REG_RESET_MASK;
>>> err = hw->tf->write(hw->dev, ST_LSM6DSX_REG_RESET_ADDR, sizeof(data),
>>> @@ -563,14 +619,12 @@ static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw)
>>> return err;
>>>
>>> /* enable FIFO watermak interrupt */
>>> - err = st_lsm6dsx_write_with_mask(hw, ST_LSM6DSX_REG_INT1_ADDR,
>>> - ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK, 1);
>>> + err = st_lsm6dsx_get_drdy_reg(hw, &drdy_int_reg);
>>> if (err < 0)
>>> return err;
>>>
>>> - /* redirect INT2 on INT1 */
>>> - return st_lsm6dsx_write_with_mask(hw, ST_LSM6DSX_REG_INT2_ON_INT1_ADDR,
>>> - ST_LSM6DSX_REG_INT2_ON_INT1_MASK, 1);
>> Does removing this potentially break existing setups?
>>
>
> No, it doesn't since INT2 was not configured yet
ah. So this was previously effectively a noop.
Thanks.
>
>>> + return st_lsm6dsx_write_with_mask(hw, drdy_int_reg,
>>> + ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK, 1);
>>> }
>>>
>>> static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw,
>>>
>>
>
> Regards,
> Lorenzo
>
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* Re: [PATCH v2 04/14] GPIO: Add gpio-ingenic driver
From: kbuild test robot @ 2017-01-22 16:21 UTC (permalink / raw)
Cc: kbuild-all-JC7UmRfGjtg, Linus Walleij, Rob Herring, Mark Rutland,
Ralf Baechle, Ulf Hansson, Boris Brezillon, Thierry Reding,
Bartlomiej Zolnierkiewicz, Maarten ter Huurne, Lars-Peter Clausen,
Paul Burton, linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA,
james.hogan-1AXoQHu6uovQT0dZR+AlfA, Paul Cercueil
In-Reply-To: <20170122144947.16158-5-paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 2198 bytes --]
Hi Paul,
[auto build test ERROR on linus/master]
[also build test ERROR on v4.10-rc4 next-20170120]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Paul-Cercueil/Ingenic-JZ4740-JZ4780-pinctrl-driver/20170122-232326
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 6.2.0
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=ia64
All errors (new ones prefixed by >>):
drivers/gpio/gpio-ingenic.c: In function 'ingenic_gpio_direction_input':
>> drivers/gpio/gpio-ingenic.c:253:9: error: implicit declaration of function 'pinctrl_gpio_direction_input' [-Werror=implicit-function-declaration]
return pinctrl_gpio_direction_input(gc->base + offset);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpio/gpio-ingenic.c: In function 'ingenic_gpio_direction_output':
>> drivers/gpio/gpio-ingenic.c:260:9: error: implicit declaration of function 'pinctrl_gpio_direction_output' [-Werror=implicit-function-declaration]
return pinctrl_gpio_direction_output(gc->base + offset);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/pinctrl_gpio_direction_input +253 drivers/gpio/gpio-ingenic.c
247 return (int) gpio_get_value(jzgc, offset);
248 }
249
250 static int ingenic_gpio_direction_input(struct gpio_chip *gc,
251 unsigned int offset)
252 {
> 253 return pinctrl_gpio_direction_input(gc->base + offset);
254 }
255
256 static int ingenic_gpio_direction_output(struct gpio_chip *gc,
257 unsigned int offset, int value)
258 {
259 ingenic_gpio_set(gc, offset, value);
> 260 return pinctrl_gpio_direction_output(gc->base + offset);
261 }
262
263 static const struct of_device_id ingenic_gpio_of_match[] = {
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 45837 bytes --]
^ permalink raw reply
* [PATCH] Documentation: net: phy: improve explanation when to specify the PHY ID
From: Martin Blumenstingl @ 2017-01-22 16:41 UTC (permalink / raw)
To: andrew-g2DYL2Zd6BY, devicetree-u79uwXL29TY76Z2rM5mHXA,
netdev-u79uwXL29TY76Z2rM5mHXA, davem-fT/PcQaiUtIeIZ0/mPfg9Q,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w
Cc: mark.rutland-5wv7dgnIgG8, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
Martin Blumenstingl
The old description basically read like "ethernet-phy-idAAAA.BBBB" can
be specified when you know the actual PHY ID. However, specifying this
has a side-effect: it forces Linux to bind to a certain PHY driver (the
one that matches the ID given in the compatible string), ignoring the ID
which is reported by the actual PHY.
Whenever a device is shipped with (multiple) different PHYs during it's
production lifetime then explicitly specifying
"ethernet-phy-idAAAA.BBBB" could break certain revisions of that device.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
Thanks to Andrew Lunn for pointing the documentation issue out to me in:
http://lists.infradead.org/pipermail/linux-amlogic/2017-January/002141.html
Documentation/devicetree/bindings/net/phy.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt
index ff1bc4b1bb3b..fb5056b22685 100644
--- a/Documentation/devicetree/bindings/net/phy.txt
+++ b/Documentation/devicetree/bindings/net/phy.txt
@@ -19,8 +19,9 @@ Optional Properties:
specifications. If neither of these are specified, the default is to
assume clause 22.
- If the phy's identifier is known then the list may contain an entry
- of the form: "ethernet-phy-idAAAA.BBBB" where
+ If the PHY reports an incorrect ID (or none at all) then the
+ "compatible" list may contain an entry with the correct PHY ID in the
+ form: "ethernet-phy-idAAAA.BBBB" where
AAAA - The value of the 16 bit Phy Identifier 1 register as
4 hex digits. This is the chip vendor OUI bits 3:18
BBBB - The value of the 16 bit Phy Identifier 2 register as
--
2.11.0
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^ permalink raw reply related
* Re: [PATCH v3 2/9] ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
From: Martin Blumenstingl @ 2017-01-22 16:48 UTC (permalink / raw)
To: Andrew Lunn
Cc: linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
khilman-rdvid1DuHRBWk0Htik3J/w, carlo-KA+7E9HrN00dnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
narmstrong-rdvid1DuHRBWk0Htik3J/w, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
jbrunet-rdvid1DuHRBWk0Htik3J/w
In-Reply-To: <20170120174658.GG25907-g2DYL2Zd6BY@public.gmane.org>
On Fri, Jan 20, 2017 at 6:46 PM, Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org> wrote:
> On Fri, Jan 20, 2017 at 06:07:20PM +0100, Martin Blumenstingl wrote:
>> I though that this is good practice - the documentation doesn't say
>> that it should only be added in specific cases: [0]
>
> Agreed, the text should be better, listing when it is appropriate to
> use.
>
>> my intention behind adding the PHY ID was to make it easier to see
>> which devices uses which PHY. this is especially useful for devices
>> with RTL8211F PHY (basically all devices with RGMII PHY except the
>> P200) as these may need similar fixes than [1]
>
> I would not say it is wrong to list the PHY ID, it just has
> consequences if the PHY ever changes.
thanks for pointing this out again, I'll re-spin this series and
remove the PHY's "compatible" property from all patches.
I also sent a patch which hopefully makes the documentation a bit more
clear: [0]
Regards,
Martin
[0] http://marc.info/?l=linux-netdev&m=148510331812986&w=2
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^ permalink raw reply
* Re: [PATCH] Documentation: net: phy: improve explanation when to specify the PHY ID
From: Andrew Lunn @ 2017-01-22 16:57 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, netdev-u79uwXL29TY76Z2rM5mHXA,
davem-fT/PcQaiUtIeIZ0/mPfg9Q, f.fainelli-Re5JQEeQqe8AvxtiuMwx3w,
mark.rutland-5wv7dgnIgG8, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <20170122164132.13967-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
On Sun, Jan 22, 2017 at 05:41:32PM +0100, Martin Blumenstingl wrote:
> The old description basically read like "ethernet-phy-idAAAA.BBBB" can
> be specified when you know the actual PHY ID. However, specifying this
> has a side-effect: it forces Linux to bind to a certain PHY driver (the
> one that matches the ID given in the compatible string), ignoring the ID
> which is reported by the actual PHY.
> Whenever a device is shipped with (multiple) different PHYs during it's
> production lifetime then explicitly specifying
> "ethernet-phy-idAAAA.BBBB" could break certain revisions of that device.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
Thanks
Andrew
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^ permalink raw reply
* [PATCH v2 4/5] regulator: axp20x: Add support for the AXP808 PMIC
From: Rask Ingemann Lambertsen @ 2017-01-22 17:33 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard, Lee Jones, Mark Brown, Rob Herring,
Mark Rutland, Liam Girdwood
Cc: devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.1486592470.git.rask@formelder.dk>
The regulators are the same as on the AXP806.
Signed-off-by: Rask Ingemann Lambertsen <rask@formelder.dk>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
No changes in v2.
drivers/regulator/axp20x-regulator.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
index a3ade9e..034dce8 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -370,6 +370,7 @@ static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
step = 75;
break;
case AXP806_ID:
+ case AXP808_ID:
/*
* AXP806 DCDC work frequency setting has the same range and
* step as AXP22X, but at a different register.
@@ -459,6 +460,7 @@ static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 work
break;
case AXP806_ID:
+ case AXP808_ID:
reg = AXP806_DCDC_MODE_CTRL2;
/*
* AXP806 DCDC regulator IDs have the same range as AXP22X.
@@ -492,8 +494,8 @@ static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
{
u32 reg = 0;
- /* Only AXP806 has poly-phase outputs */
- if (axp20x->variant != AXP806_ID)
+ /* Only AXP806 and AXP808 have poly-phase outputs */
+ if (axp20x->variant != AXP806_ID && axp20x->variant != AXP808_ID)
return false;
regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, ®);
@@ -541,6 +543,7 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
"x-powers,drive-vbus-en");
break;
case AXP806_ID:
+ case AXP808_ID:
regulators = axp806_regulators;
nregulators = AXP806_REG_ID_MAX;
break;
--
2.10.2
^ permalink raw reply related
* Re: [PATCH v2 04/14] GPIO: Add gpio-ingenic driver
From: kbuild test robot @ 2017-01-22 17:49 UTC (permalink / raw)
Cc: kbuild-all, Linus Walleij, Rob Herring, Mark Rutland,
Ralf Baechle, Ulf Hansson, Boris Brezillon, Thierry Reding,
Bartlomiej Zolnierkiewicz, Maarten ter Huurne, Lars-Peter Clausen,
Paul Burton, linux-gpio, devicetree, linux-kernel, linux-mips,
linux-mmc, linux-mtd, linux-pwm, linux-fbdev, james.hogan,
Paul Cercueil
In-Reply-To: <20170122144947.16158-5-paul@crapouillou.net>
Hi Paul,
[auto build test WARNING on linus/master]
[also build test WARNING on v4.10-rc4 next-20170120]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Paul-Cercueil/Ingenic-JZ4740-JZ4780-pinctrl-driver/20170122-232326
coccinelle warnings: (new ones prefixed by >>)
>> drivers/gpio/gpio-ingenic.c:101:2-3: Unneeded semicolon
Please review and possibly fold the followup patch.
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply
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