* [PATCH v3 7/7] arm: dts: genmai: Add user led device nodes
From: Jacopo Mondi @ 2017-03-24 15:22 UTC (permalink / raw)
To: geert+renesas, laurent.pinchart, chris.brandt, linus.walleij,
robh+dt, mark.rutland, linux
Cc: linux-renesas-soc, linux-gpio, devicetree, linux-kernel
In-Reply-To: <1490368934-12494-1-git-send-email-jacopo+renesas@jmondi.org>
Add device nodes for user leds on Genmai board.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r7s72100-genmai.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 30992b1..94b9ab7 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -11,6 +11,7 @@
/dts-v1/;
#include "r7s72100.dtsi"
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
/ {
@@ -35,6 +36,19 @@
#address-cells = <1>;
#size-cells = <1>;
};
+
+ leds {
+ status = "okay";
+ compatible = "gpio-leds";
+
+ led1 {
+ gpios = <&port4 10 GPIO_ACTIVE_LOW>;
+ };
+
+ led2 {
+ gpios = <&port4 11 GPIO_ACTIVE_LOW>;
+ };
+ };
};
&pinctrl {
--
2.7.4
^ permalink raw reply related
* [PATCH v3 6/7] arm: dts: genmai: Add RIIC2 pin group
From: Jacopo Mondi @ 2017-03-24 15:22 UTC (permalink / raw)
To: geert+renesas, laurent.pinchart, chris.brandt, linus.walleij,
robh+dt, mark.rutland, linux
Cc: linux-renesas-soc, linux-gpio, devicetree, linux-kernel
In-Reply-To: <1490368934-12494-1-git-send-email-jacopo+renesas@jmondi.org>
Add pin configuration subnode for RIIC2 interface.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r7s72100-genmai.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 569c86a..30992b1 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -44,6 +44,12 @@
renesas,pins = <PIN(3, 0) 6>,
<PIN(3, 2) 4>;
};
+
+ i2c2_pins: i2c2 {
+ /* RIIC2: P1_4 as SCL, P1_5 as SDA */
+ renesas,pins = <PIN(1, 4) (1 | BI_DIR)>,
+ <PIN(1, 5) (1 | BI_DIR)>;
+ };
};
&extal_clk {
@@ -62,6 +68,9 @@
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
eeprom@50 {
compatible = "renesas,24c128";
reg = <0x50>;
--
2.7.4
^ permalink raw reply related
* [PATCH v3 5/7] arm: dts: genmai: Add SCIF2 pin group
From: Jacopo Mondi @ 2017-03-24 15:22 UTC (permalink / raw)
To: geert+renesas, laurent.pinchart, chris.brandt, linus.walleij,
robh+dt, mark.rutland, linux
Cc: linux-renesas-soc, linux-gpio, devicetree, linux-kernel
In-Reply-To: <1490368934-12494-1-git-send-email-jacopo+renesas@jmondi.org>
Add pin configuration subnode for SCIF2 serial debug interface.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r7s72100-genmai.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 118a8e2..569c86a 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -11,6 +11,7 @@
/dts-v1/;
#include "r7s72100.dtsi"
+#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
/ {
model = "Genmai";
@@ -36,6 +37,15 @@
};
};
+&pinctrl {
+
+ scif2_pins: serial2 {
+ /* P3_0 as TxD2; P3_2 as RxD2 */
+ renesas,pins = <PIN(3, 0) 6>,
+ <PIN(3, 2) 4>;
+ };
+};
+
&extal_clk {
clock-frequency = <13330000>;
};
@@ -60,6 +70,9 @@
};
&scif2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&scif2_pins>;
+
status = "okay";
};
--
2.7.4
^ permalink raw reply related
* [PATCH v3 4/7] arm: dts: r7s72100: Add pin controller node
From: Jacopo Mondi @ 2017-03-24 15:22 UTC (permalink / raw)
To: geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw,
chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-I+IVW8TIWO2tmTQ+vhA3Yw
Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1490368934-12494-1-git-send-email-jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
Add pin controller node with 12 gpio controller sub-nodes to
r7s72100 dtsi.
Signed-off-by: Jacopo Mondi <jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
arch/arm/boot/dts/r7s72100.dtsi | 80 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index b8aa256..83e8f27 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -180,6 +180,86 @@
};
};
+ pinctrl: pinctrl@fcfe3000 {
+ compatible = "renesas,r7s72100-ports";
+
+ #pinctrl-cells = <1>;
+
+ reg = <0xfcfe3000 0x42C0>;
+
+ port0: gpio-0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 6>;
+ };
+
+ port1: gpio-1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ port2: gpio-2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ port3: gpio-3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ port4: gpio-4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ port5: gpio-5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 80 11>;
+ };
+
+ port6: gpio-6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ port7: gpio-7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ port8: gpio-8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ port9: gpio-9 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 144 8>;
+ };
+
+ port10: gpio-10 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 160 16>;
+ };
+
+ port11: gpio-11 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 176 16>;
+ };
+ };
+
scif0: serial@e8007000 {
compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8007000 64>;
--
2.7.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v3 3/7] arm: dts: dt-bindings: Add Renesas RZ pinctrl header
From: Jacopo Mondi @ 2017-03-24 15:22 UTC (permalink / raw)
To: geert+renesas, laurent.pinchart, chris.brandt, linus.walleij,
robh+dt, mark.rutland, linux
Cc: linux-renesas-soc, linux-gpio, devicetree, linux-kernel
In-Reply-To: <1490368934-12494-1-git-send-email-jacopo+renesas@jmondi.org>
Add dt-bindings for Renesas r7s72100 pin controller header file.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
include/dt-bindings/pinctrl/r7s72100-pinctrl.h | 36 ++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 include/dt-bindings/pinctrl/r7s72100-pinctrl.h
diff --git a/include/dt-bindings/pinctrl/r7s72100-pinctrl.h b/include/dt-bindings/pinctrl/r7s72100-pinctrl.h
new file mode 100644
index 0000000..170338b
--- /dev/null
+++ b/include/dt-bindings/pinctrl/r7s72100-pinctrl.h
@@ -0,0 +1,36 @@
+/*
+ * Defines macros and constants for Renesas RZ/A1 pin controller pin
+ * muxing functions.
+ */
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
+#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
+
+#define RZA1_PINS_PER_PORT 16
+
+/* Create the pin index from its bank and position numbers */
+#define PIN(b, p) ((b) * RZA1_PINS_PER_PORT + (p))
+
+/*
+ * Flags to apply to alternate function configuration
+ * All of the following are mutually exclusive.
+ */
+
+/*
+ * Pin is bi-directional.
+ * An alternate function that needs both input/output functionalities shall
+ * be configured as bidirectional.
+ * Eg. SDA/SCL pins of an I2c interface.
+ */
+#define BI_DIR (1 << 3)
+
+/*
+ * Flags used to ask software to drive the pin I/O direction overriding the
+ * alternate function configuration.
+ * Some alternate functions require software to force I/O direction of a pin,
+ * overriding the designated one.
+ * Refer to the HW manual to know when this flag shall be used.
+ */
+#define SWIO_IN (1 << 4)
+#define SWIO_OUT (1 << 5)
+
+#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v3 2/7] dt-bindings: pinctrl: Add RZ/A1 bindings doc
From: Jacopo Mondi @ 2017-03-24 15:22 UTC (permalink / raw)
To: geert+renesas, laurent.pinchart, chris.brandt, linus.walleij,
robh+dt, mark.rutland, linux
Cc: linux-renesas-soc, linux-gpio, devicetree, linux-kernel
In-Reply-To: <1490368934-12494-1-git-send-email-jacopo+renesas@jmondi.org>
Add device tree bindings documentation for Renesas RZ/A1 gpio and pin
controller.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
.../bindings/pinctrl/renesas,rza1-pinctrl.txt | 143 +++++++++++++++++++++
1 file changed, 143 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
new file mode 100644
index 0000000..69aafd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
@@ -0,0 +1,143 @@
+Renesas RZ/A1 combined Pin and GPIO controller
+
+The Renesas SoCs of RZ/A1 family feature a combined Pin and GPIO controller
+hardware controller, named "Ports" in the hardware reference manual.
+Pin multiplexing and GPIO configuration is performed on a per-pin basis
+writing configuration values to per-port register sets.
+Each "port" features up to 16 pins, each of them configurable for GPIO
+function (port mode) or in alternate function mode.
+Up to 8 different alternate function modes exist for each single pin.
+
+Pin controller node
+-------------------
+
+Required properties:
+ - compatible
+ this shall be "renesas,r7s72100-ports".
+
+ - #pinctrl-cells
+ as defined by pinctrl-bindings.txt, this is the number
+ of cells (in addition to pin index) required to configure a single pin.
+ Shall be set to 1.
+
+ - reg
+ address base and length of the memory area where pin controller
+ hardware is mapped to.
+
+Example:
+Pin controller node for RZ/A1H SoC (r7s72100)
+
+pinctrl: pinctrl@fcfe3000 {
+ compatible = "renesas,r7s72100-ports";
+
+ #pinctrl-cells = <1>;
+
+ reg = <0xfcfe3000 0x4230>;
+};
+
+Sub-nodes
+---------
+
+The child nodes of the pin controller node describe a pin multiplexing
+function or a gpio controller alternatively.
+
+- Pin multiplexing sub-nodes:
+ A pin multiplexing sub-node describes how to configure a set of
+ (or a single) pin in some desired alternate function mode.
+ A single sub-node may define several pin configurations groups.
+
+ Required properties:
+ - renesas,pins
+ describes an array of pin multiplexing configurations.
+ When a pin has to be configured in alternate function mode, use this
+ property to identify the pin by its global index, and provide its
+ alternate function configuration description along with it.
+ When multiple pins are required to be configured as part of the same
+ alternate function (odds are single-pin alternate functions exist) they
+ shall be specified as members of the same argument list of a single
+ "renesas-pins" property.
+ Helper macros to ease calculating the pin index from its position
+ (port where it sits on and pin offset), and alternate function
+ configuration options are provided in the pin controller header file at:
+ include/dt-bindings/pinctrl/r7s72100-pinctrl.h
+
+ Example:
+ A serial communication interface with a TX output pin and an RX input pin.
+
+ &pinctrl {
+ scif2_pins: serial2 {
+ renesas,pins = <PIN(3, 0) 6>, <PIN(3, 2) 4>;
+ };
+ }
+
+ Pin #0 on port #3 is configured as alternate function #6.
+ Pin #2 on port #3 is configured as alternate function #4.
+
+ Example 2:
+ I2c master: both SDA and SCL pins need bi-directional operations
+
+ &pinctrl {
+ i2c2_pins: i2c2 {
+ renesas,pins = <PIN(1, 4) (1 | BI_DIR)>,
+ <PIN(1, 5) (1 | BI_DIR)>;
+ };
+ }
+
+ Pin #4 on port #1 is configured as alternate function #1.
+ Pin #5 on port #1 is configured as alternate function #1.
+ Both need to work in bi-directional mode.
+
+ Example 3:
+ Multi-function timer input and output compare pins.
+ The hardware manual prescribes this pins to have input/output direction
+ specified by software. Configure TIOC0A as input and TIOC0B as output.
+
+ &pinctrl {
+ tioc0_pins: tioc0 {
+ renesas,pins = <PIN(4, 0) (2 | SWIO_IN)>,
+ <PIN(4, 1) (2 | SWIO_OUT)>;
+ };
+ }
+
+ Pin #0 on port #4 is configured as alternate function #2 with IO direction
+ specified by software as input.
+ Pin #1 on port #4 is configured as alternate function #1 with IO direction
+ specified by software as output.
+
+- GPIO controller sub-nodes:
+ Each port of the r7s72100 pin controller hardware is itself a gpio controller.
+ Different SoCs have different number of available pins per port, but
+ generally speaking, each of them can be configured in GPIO ("port") mode
+ on this hardware.
+ Describe gpio-controllers using sub-nodes with the following properties.
+
+ Required properties:
+ - gpio-controller
+ empty property as defined by the gpio bindings documentation.
+ - #gpio-cells
+ number of cells required to identify and configure a GPIO.
+ Shall be 2.
+ - gpio-ranges
+ Describes a gpio controller specifying its specific pin base, the pin
+ base in the global pin numbering space, and the number of controlled
+ pins, as defined by the gpio bindings documentation. Refer to this file
+ for a more detailed description.
+
+ Example:
+ A gpio controller node, controlling 16 pins indexed from 0.
+ The gpio controller base in the global pin indexing space is pin 48, thus
+ pins [0 - 15] on this controller map to pins [48 - 63] in the global pin
+ indexing space.
+
+ port3: gpio-3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ A device node willing to use pins controlled by this gpio controller, shall
+ refer to it as follows:
+
+ led1 {
+ gpios = <&port3 10 GPIO_ACTIVE_LOW>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH v3 1/7] pinctrl: Renesas RZ/A1 pin and gpio controller
From: Jacopo Mondi @ 2017-03-24 15:22 UTC (permalink / raw)
To: geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw,
chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-I+IVW8TIWO2tmTQ+vhA3Yw
Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1490368934-12494-1-git-send-email-jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
Add combined gpio and pin controller driver for Renesas RZ/A1
r7s72100 SoC.
Signed-off-by: Jacopo Mondi <jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
---
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-rza1.c | 961 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 972 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-rza1.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8f8c2af..c9b55b9 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -163,6 +163,16 @@ config PINCTRL_ROCKCHIP
select GENERIC_IRQ_CHIP
select MFD_SYSCON
+config PINCTRL_RZA1
+ bool "Renesas RZ/A1 gpio and pinctrl driver"
+ depends on OF
+ depends on ARCH_R7S72100 || COMPILE_TEST
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ help
+ This selects pinctrl driver for Renesas RZ/A1 platforms.
+
config PINCTRL_SINGLE
tristate "One-register-per-pin type device tree based pinctrl driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a251f43..0c2328d2 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
+obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c
new file mode 100644
index 0000000..0a4fc41
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-rza1.c
@@ -0,0 +1,961 @@
+/*
+ * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
+ *
+ * Copyright (C) 2017 Jacopo Mondi
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/*
+ * This pincontroller/gpio combined driver support Renesas devices of RZ/A1
+ * family.
+ * This includes SoCs which are sub- or super- sets of this particular line,
+ * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020) are.
+ */
+
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/gpio/driver.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/slab.h>
+
+#include "core.h"
+#include "devicetree.h"
+#include "pinmux.h"
+
+#define DRIVER_NAME "pinctrl-rza1"
+
+#define RZA1_PINMUX_OF_ARGS 2
+
+#define P_REG 0x0000
+#define PPR_REG 0x0200
+#define PM_REG 0x0300
+#define PMC_REG 0x0400
+#define PFC_REG 0x0500
+#define PFCE_REG 0x0600
+#define PFCEA_REG 0x0a00
+#define PIBC_REG 0x4000
+#define PBDC_REG 0x4100
+#define PIPC_REG 0x4200
+#define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4))
+
+#define RZA1_NPORTS 12
+#define RZA1_PINS_PER_PORT 16
+#define RZA1_NPINS (RZA1_PINS_PER_PORT * RZA1_NPORTS)
+#define RZA1_PIN_TO_PORT(pin) ((pin) / RZA1_PINS_PER_PORT)
+#define RZA1_PIN_TO_OFFSET(pin) ((pin) % RZA1_PINS_PER_PORT)
+
+/*
+ * Be careful here: the pin configuration subnodes in device tree enumerate
+ * alternate functions from 1 to 8; subtract 1 before using macros so to match
+ * register configuration which expects numbers from 0 to 7 instead.
+ */
+#define MUX_FUNC_OFFS 3
+#define MUX_FUNC_MASK (BIT(MUX_FUNC_OFFS) - 1)
+#define MUX_FUNC_PFC_MASK BIT(0)
+#define MUX_FUNC_PFCE_MASK BIT(1)
+#define MUX_FUNC_PFCEA_MASK BIT(2)
+#define MUX_CONF_BIDIR BIT(0)
+#define MUX_CONF_SWIO_INPUT BIT(1)
+#define MUX_CONF_SWIO_OUTPUT BIT(2)
+
+/**
+ * rza1_pin_conf - describes a pin position, id, mux config and output value
+ *
+ * @id: the pin identifier from 0 to RZA1_NPINS
+ * @port: the port where pin sits on
+ * @offset: pin offset in the port
+ * @mux: alternate function configuration settings
+ * @value: output value to set the pin to
+ */
+struct rza1_pin_conf {
+ u16 id;
+ u8 port;
+ u8 offset;
+ u8 mux_conf;
+ u8 value;
+};
+
+/**
+ * rza1_port - describes a pin port
+ *
+ * This is mostly useful to lock register writes per-bank and not globally.
+ *
+ * @lock: protect access to HW registers
+ * @id: port number
+ * @base: logical address base
+ * @pins: pins sitting on this port
+ */
+struct rza1_port {
+ spinlock_t lock;
+ unsigned int id;
+ void __iomem *base;
+ struct pinctrl_pin_desc *pins;
+};
+
+/**
+ * rza1_pinctrl - RZ pincontroller device
+ *
+ * @dev: parent device structure
+ * @mutex: protect [pinctrl|pinmux]_generic functions
+ * @base: logical address base
+ * @nports: number of pin controller ports
+ * @ports: pin controller banks
+ * @ngpiochips: number of gpio chips
+ * @gpio_ranges: gpio ranges for pinctrl core
+ * @pins: pin array for pinctrl core
+ * @desc: pincontroller desc for pinctrl core
+ * @pctl: pinctrl device
+ */
+struct rza1_pinctrl {
+ struct device *dev;
+
+ struct mutex mutex;
+
+ void __iomem *base;
+
+ unsigned int nport;
+ struct rza1_port *ports;
+
+ unsigned int ngpiochips;
+
+ struct pinctrl_gpio_range *gpio_ranges;
+ struct pinctrl_pin_desc *pins;
+ struct pinctrl_desc desc;
+ struct pinctrl_dev *pctl;
+};
+
+/* ----------------------------------------------------------------------------
+ * RZ/A1 SoC operations
+ */
+
+/**
+ * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
+ * registers
+ */
+static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg,
+ unsigned int bit, bool set)
+{
+ void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
+ u16 val = ioread16(mem);
+
+ if (set)
+ val |= BIT(bit);
+ else
+ val &= ~BIT(bit);
+
+ iowrite16(val, mem);
+}
+
+static inline int rza1_get_bit(struct rza1_port *port, unsigned int reg,
+ unsigned int bit)
+{
+ void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
+
+ return ioread16(mem) & BIT(bit);
+}
+
+/**
+ * rza1_pin_reset() - reset a pin to default initial state
+ *
+ * Reset pin state disabling input buffer and bi-directional control,
+ * and configure it as input port.
+ * Note that pin is now configured with direction as input but with input
+ * buffer disabled. This implies the pin value cannot be read in this state.
+ *
+ * @port: port where pin sits on
+ * @pin: pin offset
+ */
+static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
+{
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&port->lock, irqflags);
+ rza1_set_bit(port, PIBC_REG, pin, 0);
+ rza1_set_bit(port, PBDC_REG, pin, 0);
+
+ rza1_set_bit(port, PM_REG, pin, 1);
+ rza1_set_bit(port, PMC_REG, pin, 0);
+ rza1_set_bit(port, PIPC_REG, pin, 0);
+ spin_unlock_irqrestore(&port->lock, irqflags);
+}
+
+static inline int rza1_pin_get_direction(struct rza1_port *port,
+ unsigned int pin)
+{
+ unsigned long irqflags;
+ int input;
+
+ spin_lock_irqsave(&port->lock, irqflags);
+ input = rza1_get_bit(port, PM_REG, pin);
+ spin_unlock_irqrestore(&port->lock, irqflags);
+
+ return input;
+}
+
+/**
+ * rza1_pin_set_direction() - set I/O direction on a pin in port mode
+ *
+ * When running in output port mode keep PBDC enabled to allow reading the
+ * pin value from PPR.
+ *
+ * @port: port where pin sits on
+ * @pin: pin offset
+ * @input: input enable/disable flag
+ */
+static inline void rza1_pin_set_direction(struct rza1_port *port,
+ unsigned int pin, bool input)
+{
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&port->lock, irqflags);
+
+ rza1_set_bit(port, PIBC_REG, pin, 1);
+ if (input) {
+ rza1_set_bit(port, PM_REG, pin, 1);
+ rza1_set_bit(port, PBDC_REG, pin, 0);
+ } else {
+ rza1_set_bit(port, PM_REG, pin, 0);
+ rza1_set_bit(port, PBDC_REG, pin, 1);
+ }
+
+ spin_unlock_irqrestore(&port->lock, irqflags);
+}
+
+static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
+ unsigned int value)
+{
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&port->lock, irqflags);
+ rza1_set_bit(port, P_REG, pin, !!value);
+ spin_unlock_irqrestore(&port->lock, irqflags);
+}
+
+static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
+{
+ unsigned long irqflags;
+ int val;
+
+ spin_lock_irqsave(&port->lock, irqflags);
+ val = rza1_get_bit(port, PPR_REG, pin);
+ spin_unlock_irqrestore(&port->lock, irqflags);
+
+ return val;
+}
+
+/**
+ * rza1_alternate_function_conf() - configure pin in alternate function mode
+ *
+ * @pinctrl: RZ/A1 pin controller device
+ * @pin_conf: single pin configuration descriptor
+ */
+static int rza1_alternate_function_conf(struct rza1_pinctrl *rza1_pctl,
+ struct rza1_pin_conf *pin_conf)
+{
+ struct rza1_port *port = &rza1_pctl->ports[pin_conf->port];
+ u8 mux_mode = (pin_conf->mux_conf - 1) & MUX_FUNC_MASK;
+ u8 mux_conf = pin_conf->mux_conf >> MUX_FUNC_OFFS;
+ bool swio_out = !!(mux_conf & MUX_CONF_SWIO_OUTPUT);
+ bool swio_in = !!(mux_conf & MUX_CONF_SWIO_INPUT);
+ bool bidir_en = !!(mux_conf & MUX_CONF_BIDIR);
+ unsigned int offset = pin_conf->offset;
+
+ /* Make sure a single bit is set in mux_conf mask. */
+ if (ffs(mux_conf) != fls(mux_conf)) {
+ dev_err(rza1_pctl->dev,
+ "Invalid pin configuration for pin %u:%u",
+ port->id, offset);
+ return -EINVAL;
+ }
+
+ rza1_pin_reset(port, offset);
+
+ if (bidir_en)
+ rza1_set_bit(port, PBDC_REG, offset, 1);
+
+ /*
+ * Enable alternate function mode and select it.
+ *
+ * ----------------------------------------------------
+ * Alternate mode selection table:
+ *
+ * PMC PFC PFCE PFCAE mux_mode
+ * 1 0 0 0 0
+ * 1 1 0 0 1
+ * 1 0 1 0 2
+ * 1 1 1 0 3
+ * 1 0 0 1 4
+ * 1 1 0 1 5
+ * 1 0 1 1 6
+ * 1 1 1 1 7
+ * ----------------------------------------------------
+ */
+ rza1_set_bit(port, PFC_REG, offset, mux_mode & MUX_FUNC_PFC_MASK);
+ rza1_set_bit(port, PFCE_REG, offset, mux_mode & MUX_FUNC_PFCE_MASK);
+ rza1_set_bit(port, PFCEA_REG, offset, mux_mode & MUX_FUNC_PFCEA_MASK);
+
+ /*
+ * All alternate functions except a few (4) need PIPCn = 1.
+ * If PIPCn has to stay disabled (SW IO mode), configure PMn according
+ * to I/O direction specified by pin configuration -after- PMC has been
+ * set to one.
+ */
+ if (!(swio_in || swio_out))
+ rza1_set_bit(port, PIPC_REG, offset, 1);
+
+ rza1_set_bit(port, PMC_REG, offset, 1);
+ rza1_set_bit(port, PM_REG, offset, swio_in);
+
+ return 0;
+}
+
+/* ----------------------------------------------------------------------------
+ * pinctrl operations
+ */
+
+/**
+ * rza1_dt_node_to_map() - map a node to a function/group map
+ *
+ * Functions and groups are collected and registered to pinctrl_generic
+ * during DT parsing routine.
+ *
+ * @pctldev: pin controller device
+ * @np: device tree node to parse
+ * @map: pointer to pin map (output)
+ * @num_maps: number of collected maps (output)
+ */
+static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map,
+ unsigned int *num_maps)
+{
+ struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct group_desc *grp;
+ unsigned int grp_sel;
+
+ /*
+ * Find the group of this node and check if we need create
+ * config maps for pins.
+ */
+ grp_sel = pinctrl_get_group_selector(pctldev, np->name);
+ if (grp_sel < 0) {
+ dev_err(rza1_pctl->dev, "unable to find group for node %s\n",
+ np->name);
+ return -EINVAL;
+ }
+
+ grp = pinctrl_generic_get_group(pctldev, grp_sel);
+ if (!grp) {
+ dev_err(rza1_pctl->dev, "unable to find group for node %s\n",
+ np->name);
+ return -EINVAL;
+ }
+
+ *num_maps = 0;
+ *map = kzalloc(sizeof(**map), GFP_KERNEL);
+ if (!*map)
+ return -ENOMEM;
+
+ (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
+ (*map)->data.mux.group = np->name;
+ (*map)->data.mux.function = np->name;
+ *num_maps = 1;
+
+ return 0;
+}
+
+static void rza1_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned int num_maps)
+{
+ kfree(map);
+}
+
+static const struct pinctrl_ops rza1_pinctrl_ops = {
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+ .dt_node_to_map = rza1_dt_node_to_map,
+ .dt_free_map = rza1_dt_free_map,
+};
+
+/* ----------------------------------------------------------------------------
+ * gpio operations
+ */
+
+/**
+ * rza1_gpio_request() - configure pin in port mode
+ *
+ * Configure a pin as gpio (port mode).
+ * After reset, the pin is in input mode with input buffer disabled.
+ * To use the pin as input or output, set_direction shall be called first
+ *
+ * @chip: gpio chip where the gpio sits on
+ * @gpio: gpio offset
+ */
+static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ rza1_pin_reset(port, gpio);
+
+ return 0;
+}
+
+/**
+ * rza1_gpio_disable_free() - reset a pin
+ *
+ * Surprisingly, disable_free a gpio, is equivalent to request it.
+ * Reset pin to port mode, with input buffer disabled. This overwrites all
+ * port direction settings applied with set_direction
+ *
+ * @chip: gpio chip where the gpio sits on
+ * @gpio: gpio offset
+ */
+static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ rza1_pin_reset(port, gpio);
+}
+
+static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ return rza1_pin_get_direction(port, offset);
+}
+
+static int rza1_gpio_direction_input(struct gpio_chip *chip,
+ unsigned int offset)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ rza1_pin_set_direction(port, offset, true);
+
+ return 0;
+}
+
+static int rza1_gpio_direction_output(struct gpio_chip *chip,
+ unsigned int offset,
+ int value)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ /* Set value before driving pin direction */
+ rza1_pin_set(port, offset, value);
+ rza1_pin_set_direction(port, offset, false);
+
+ return 0;
+}
+
+/**
+ * rza1_gpio_get() - read a gpio pin value
+ *
+ * Read gpio pin value through PPR register.
+ * Requires bi-directional mode to work when reading the value of a pin
+ * in output mode
+ *
+ * @chip: gpio chip where the gpio sits on
+ * @gpio: gpio offset
+ */
+static int rza1_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ return rza1_pin_get(port, offset);
+}
+
+static void rza1_gpio_set(struct gpio_chip *chip, unsigned int offset,
+ int value)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ rza1_pin_set(port, offset, value);
+}
+
+struct gpio_chip rza1_gpiochip_template = {
+ .request = rza1_gpio_request,
+ .free = rza1_gpio_free,
+ .get_direction = rza1_gpio_get_direction,
+ .direction_input = rza1_gpio_direction_input,
+ .direction_output = rza1_gpio_direction_output,
+ .get = rza1_gpio_get,
+ .set = rza1_gpio_set,
+};
+
+/* ----------------------------------------------------------------------------
+ * pinmux operations
+ */
+
+/**
+ * rza1_pinmux_set() - retrieve pins from a group and apply their mux settings
+ *
+ * @pctldev: pin controller device
+ * @selector: function selector
+ * @group: group selector
+ */
+static int rza1_pinmux_set(struct pinctrl_dev *pctldev, unsigned int selector,
+ unsigned int group)
+{
+ struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct rza1_pin_conf *pin_confs;
+ struct function_desc *func;
+ struct group_desc *grp;
+ int i;
+
+ grp = pinctrl_generic_get_group(pctldev, group);
+ if (!grp)
+ return -EINVAL;
+
+ func = pinmux_generic_get_function(pctldev, selector);
+ if (!func)
+ return -EINVAL;
+
+ pin_confs = (struct rza1_pin_conf *)func->data;
+ for (i = 0; i < grp->num_pins; ++i) {
+ int ret;
+
+ ret = rza1_alternate_function_conf(rza1_pctl, &pin_confs[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+struct pinmux_ops rza1_pinmux_ops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = rza1_pinmux_set,
+ .strict = true,
+};
+
+/* ----------------------------------------------------------------------------
+ * RZ/A1 pin controller driver operations
+ */
+
+static unsigned int rza1_count_gpio_chips(struct device_node *np)
+{
+ struct device_node *child;
+ unsigned int count = 0;
+
+ for_each_child_of_node(np, child) {
+ if (!of_property_read_bool(child, "gpio-controller"))
+ continue;
+
+ count++;
+ }
+
+ return count;
+}
+
+/**
+ * rza1_parse_pmx_function() - parse and register a pin mux function
+ *
+ * Pins for RZ SoC pin controller described by "renesas-pins" property.
+ *
+ * First argument in the list identifies the pin, while the second one
+ * describes the requested alternate function number and additional
+ * configuration parameter to be applied to the selected function.
+ *
+ * @rza1_pctl: RZ/A1 pin controller device
+ * @np: of pmx sub-node
+ */
+static int rza1_parse_pmx_function(struct rza1_pinctrl *rza1_pctl,
+ struct device_node *np)
+{
+ struct pinctrl_dev *pctldev = rza1_pctl->pctl;
+ char const *prop_name = "renesas,pins";
+ struct rza1_pin_conf *pin_confs;
+ unsigned int *grpins;
+ const char *grpname;
+ const char **fngrps;
+ unsigned int i;
+ int of_npins;
+ int ret;
+
+ of_npins = pinctrl_count_index_with_args(np, prop_name);
+ if (of_npins <= 0) {
+ dev_err(rza1_pctl->dev, "Missing %s property\n", prop_name);
+ return -ENOENT;
+ }
+
+ /*
+ * Functions are made of 1 group only;
+ * in fact, functions and groups are identical for this pin controller
+ * except that functions carry an array of per-pin configuration
+ * settings.
+ */
+ pin_confs = devm_kcalloc(rza1_pctl->dev, of_npins, sizeof(*pin_confs),
+ GFP_KERNEL);
+ grpins = devm_kcalloc(rza1_pctl->dev, of_npins, sizeof(*grpins),
+ GFP_KERNEL);
+ fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL);
+
+ if (!pin_confs || !grpins || !fngrps)
+ return -ENOMEM;
+
+ /* Collect pin positions and mux settings to store them in function */
+ for (i = 0; i < of_npins; ++i) {
+ struct rza1_pin_conf *pin_conf = &pin_confs[i];
+ struct of_phandle_args of_npins_args;
+
+ ret = pinctrl_parse_index_with_args(np, prop_name, i,
+ &of_npins_args);
+ if (ret)
+ return ret;
+
+ if (of_npins_args.args_count < RZA1_PINMUX_OF_ARGS) {
+ dev_err(rza1_pctl->dev,
+ "Wrong number of arguments for %s property\n",
+ prop_name);
+ return -EINVAL;
+ }
+
+ /*
+ * This new pins configuration will be associated with a new
+ * function, and later used to set-up pin muxing
+ */
+ pin_conf->id = of_npins_args.args[0];
+ pin_conf->port = RZA1_PIN_TO_PORT(pin_conf->id);
+ pin_conf->offset = RZA1_PIN_TO_OFFSET(pin_conf->id);
+ pin_conf->mux_conf = of_npins_args.args[1];
+
+ if (pin_conf->port >= RZA1_NPORTS ||
+ pin_conf->offset >= RZA1_PINS_PER_PORT) {
+ dev_err(rza1_pctl->dev,
+ "Wrong port %u pin %u for %s property\n",
+ pin_conf->port, pin_conf->offset, prop_name);
+ return -EINVAL;
+ }
+
+ grpins[i] = pin_conf->id;
+ }
+
+ grpname = np->name;
+ fngrps[0] = grpname;
+
+ mutex_lock(&rza1_pctl->mutex);
+ ret = pinctrl_generic_add_group(pctldev, grpname, grpins, of_npins,
+ NULL);
+ if (ret) {
+ mutex_unlock(&rza1_pctl->mutex);
+ return ret;
+ }
+
+ ret = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
+ pin_confs);
+ if (ret)
+ goto remove_group;
+ mutex_unlock(&rza1_pctl->mutex);
+
+ dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",
+ grpname, of_npins);
+
+ return 0;
+
+remove_group:
+ dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",
+ grpname);
+ pinctrl_generic_remove_last_group(pctldev);
+ mutex_unlock(&rza1_pctl->mutex);
+
+ return ret;
+}
+
+/**
+ * rza1_remove_pmx_functions() - un-register pmx functions and groups
+ *
+ * @rza1_pctl: RZ/A1 pin controller device
+ */
+static void rza1_remove_pmx_functions(struct rza1_pinctrl *rza1_pctl)
+{
+ struct pinctrl_dev *pctldev = rza1_pctl->pctl;
+
+ mutex_lock(&rza1_pctl->mutex);
+ pinmux_generic_free_functions(pctldev);
+ mutex_unlock(&rza1_pctl->mutex);
+}
+
+/**
+ * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
+ *
+ * The gpio controller subnode shall provide a "gpio-ranges" list property as
+ * defined by gpio device tree binding documentation.
+ * Gpio chips and pin ranges are here collected, but ranges are registered
+ * later, after the pin controller has been registered too. Only gpiochips are
+ * registered here.
+ *
+ * @rza1_pctl: RZ/A1 pin controller device
+ * @np: of gpio-controller node
+ * @chip: gpio chip to register to gpiolib
+ * @range: pin range to register to pinctrl core
+ */
+static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
+ struct device_node *np,
+ struct gpio_chip *chip,
+ struct pinctrl_gpio_range *range)
+{
+ const char *list_name = "gpio-ranges";
+ struct of_phandle_args of_args;
+ unsigned int gpioport;
+ u32 pinctrl_base;
+ int ret;
+
+ ret = of_parse_phandle_with_fixed_args(np, list_name, 3, 0, &of_args);
+ if (ret) {
+ dev_err(rza1_pctl->dev, "Unable to parse %s list property\n",
+ list_name);
+ return ret;
+ }
+
+ /*
+ * Find out on which port this gpio-chip maps to by inspecting the
+ * second argument of the "gpio-ranges" property.
+ */
+ pinctrl_base = of_args.args[1];
+ gpioport = RZA1_PIN_TO_PORT(pinctrl_base);
+ if (gpioport > RZA1_NPORTS) {
+ dev_err(rza1_pctl->dev,
+ "Invalid values in property %s\n", list_name);
+ return -EINVAL;
+ }
+
+ *chip = rza1_gpiochip_template;
+ chip->base = -1;
+ chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%s-%u",
+ np->name, gpioport);
+ chip->ngpio = of_args.args[2];
+ chip->of_node = np;
+ chip->parent = rza1_pctl->dev;
+
+ range->id = gpioport;
+ range->name = chip->label;
+ range->pin_base = range->base = pinctrl_base;
+ range->npins = of_args.args[2];
+ range->gc = chip;
+
+ ret = devm_gpiochip_add_data(rza1_pctl->dev, chip,
+ &rza1_pctl->ports[gpioport]);
+ if (ret)
+ return ret;
+
+ dev_info(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
+ chip->label, chip->ngpio);
+
+ return 0;
+}
+
+/**
+ * rza1_parse_dt() - parse DT to collect gpiochips and pmx functions
+ *
+ * @rza1_pctl: RZ/A1 pin controller device
+ */
+static int rza1_parse_dt(struct rza1_pinctrl *rza1_pctl)
+{
+ struct device_node *np = rza1_pctl->dev->of_node;
+ struct pinctrl_gpio_range *gpio_ranges;
+ struct gpio_chip *gpio_chips;
+ struct device_node *child;
+ unsigned int ngpiochips;
+ unsigned int npmxfuncs;
+ unsigned int i;
+ int ret;
+
+ ngpiochips = rza1_count_gpio_chips(np);
+ if (ngpiochips) {
+ dev_info(rza1_pctl->dev, "Registering %u gpio chips\n",
+ ngpiochips);
+
+ gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips,
+ sizeof(*gpio_chips), GFP_KERNEL);
+ gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips,
+ sizeof(*gpio_ranges), GFP_KERNEL);
+ if (!gpio_chips || !gpio_ranges)
+ return -ENOMEM;
+ } else {
+ dev_dbg(rza1_pctl->dev, "No gpiochip registered\n");
+ gpio_ranges = NULL;
+ }
+
+ rza1_pctl->gpio_ranges = gpio_ranges;
+
+ i = 0;
+ npmxfuncs = 0;
+ for_each_child_of_node(np, child) {
+ if (of_property_read_bool(child, "gpio-controller")) {
+ /* Never get here if ngpiochips == 0 */
+ ret = rza1_parse_gpiochip(rza1_pctl, child,
+ &gpio_chips[i],
+ &gpio_ranges[i]);
+ if (ret)
+ goto gpio_pmx_unregister;
+
+ ++i;
+ } else {
+ ret = rza1_parse_pmx_function(rza1_pctl, child);
+ if (ret)
+ goto gpio_pmx_unregister;
+
+ ++npmxfuncs;
+ }
+ }
+
+ rza1_pctl->ngpiochips = i;
+
+ dev_info(rza1_pctl->dev,
+ "Registered %u gpio controllers and %u pin mux functions\n",
+ rza1_pctl->ngpiochips, npmxfuncs);
+
+ return 0;
+
+gpio_pmx_unregister:
+ for (; i > 0; i--)
+ devm_gpiochip_remove(rza1_pctl->dev, &gpio_chips[i - 1]);
+
+ rza1_remove_pmx_functions(rza1_pctl);
+
+ return ret;
+}
+
+/**
+ * rza1_pinctrl_register() - Enumerate pins, ports, gpiochips, pmx functions
+ * and register to pinctrl and gpio cores
+ *
+ * @rza1_pctl: RZ/A1 pin controller device
+ */
+static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
+{
+ struct pinctrl_pin_desc *pins;
+ struct rza1_port *ports;
+ unsigned int i;
+ int ret;
+
+ pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins),
+ GFP_KERNEL);
+ ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports),
+ GFP_KERNEL);
+ if (!pins || !ports)
+ return -ENOMEM;
+
+ rza1_pctl->pins = pins;
+ rza1_pctl->desc.pins = pins;
+ rza1_pctl->desc.npins = RZA1_NPINS;
+ rza1_pctl->ports = ports;
+
+ for (i = 0; i < RZA1_NPINS; ++i) {
+ unsigned int offset = RZA1_PIN_TO_OFFSET(i);
+ unsigned int port = RZA1_PIN_TO_PORT(i);
+
+ pins[i].number = i;
+ pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,
+ "P%u-%u", port, offset);
+
+ if (i % RZA1_PINS_PER_PORT == 0) {
+ /*
+ * Setup ports;
+ * they provide per-port lock and logical base address.
+ */
+ unsigned int port_id = RZA1_PIN_TO_PORT(i);
+
+ ports[port_id].id = port_id;
+ ports[port_id].base = rza1_pctl->base;
+ ports[port_id].pins = &pins[i];
+ spin_lock_init(&ports[port_id].lock);
+ }
+ }
+
+ ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc,
+ rza1_pctl, &rza1_pctl->pctl);
+ if (ret) {
+ dev_err(rza1_pctl->dev,
+ "RZ/A1 pin controller registration failed\n");
+ return ret;
+ }
+
+ ret = rza1_parse_dt(rza1_pctl);
+ if (ret) {
+ dev_err(rza1_pctl->dev, "RZ/A1 DT parsing failed\n");
+ return ret;
+ }
+
+ for (i = 0; i < rza1_pctl->ngpiochips; i++)
+ pinctrl_add_gpio_range(rza1_pctl->pctl,
+ &rza1_pctl->gpio_ranges[i]);
+
+ return 0;
+}
+
+static int rza1_pinctrl_probe(struct platform_device *pdev)
+{
+ struct rza1_pinctrl *rza1_pctl;
+ struct resource *res;
+ int ret;
+
+ rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
+ if (!rza1_pctl)
+ return -ENOMEM;
+
+ rza1_pctl->dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (ret)
+ return -ENODEV;
+
+ rza1_pctl->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(rza1_pctl->base))
+ return PTR_ERR(rza1_pctl->base);
+
+ mutex_init(&rza1_pctl->mutex);
+
+ platform_set_drvdata(pdev, rza1_pctl);
+
+ rza1_pctl->desc.name = DRIVER_NAME;
+ rza1_pctl->desc.pctlops = &rza1_pinctrl_ops;
+ rza1_pctl->desc.pmxops = &rza1_pinmux_ops;
+ rza1_pctl->desc.owner = THIS_MODULE;
+
+ ret = rza1_pinctrl_register(rza1_pctl);
+ if (ret)
+ return ret;
+
+ dev_info(&pdev->dev,
+ "RZ/A1 pin controller and gpio successfully registered\n");
+
+ return 0;
+}
+
+static const struct of_device_id rza1_pinctrl_of_match[] = {
+ { .compatible = "renesas,r7s72100-ports", },
+ { }
+};
+
+static struct platform_driver rza1_pinctrl_driver = {
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = rza1_pinctrl_of_match,
+ },
+ .probe = rza1_pinctrl_probe,
+};
+
+static int __init rza1_pinctrl_init(void)
+{
+ return platform_driver_register(&rza1_pinctrl_driver);
+}
+core_initcall(rza1_pinctrl_init);
+
+MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org");
+MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");
+MODULE_LICENSE("GPL v2");
--
2.7.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v3 0/8] Renesas RZ/A1 pin and gpio controller
From: Jacopo Mondi @ 2017-03-24 15:22 UTC (permalink / raw)
To: geert+renesas, laurent.pinchart, chris.brandt, linus.walleij,
robh+dt, mark.rutland, linux
Cc: linux-renesas-soc, linux-gpio, devicetree, linux-kernel
Hello!
Third round for Renesas RZ/A1 PFC gpio and pin controller.
V3 fixes review comments on grammar and spelling by Geert.
Some other fixes from Geert's review as update of function argument names
to reflect the function purpose (s/offset/[pin|bit]), use irqsave/irqrestore
version of spinlocks locking/unlocking methods and other style fixes.
Still an open question on the use of "pins" or "renesas,pins" property in
device tree bindings:
https://www.spinics.net/lists/linux-renesas-soc/msg12765.html
Tested on Genmai and RSK boards with SCIF, I2c and GPIO (genmai) and SCIF, I2c,
SDHI and ethernet on RSK (thanks Chris).
Thanks
j
v1 -> v2:
- change pin configuration flags as suggested by Chris
- gpio set direction function fixed as suggested by Chris
- add some more example on pin configuration flag usage to dt-binding doc
- fix gpio-controller names to remove unit address as suggested by Geert
- some comments chopped here and there to make the driver less verbose
v2 -> v3:
- fix grammar and syntax in comment and documentation
- fix code style (reverse xmas tree ordering in variable declaration)
- use irqsave/irqrestore in spinlock lock/unlock
- use devm_ version of kasprintf (memory returned was not properly free)
- use bitops.h operation ffs and fls to make sure a single bit is set in pmx
mask
- Add Geert's reviewed-by to DTS patches
Jacopo Mondi (8):
pinctrl: Renesas RZ/A1 pin and gpio controller
dt-bindings: pinctrl: Add RZ/A1 bindings doc
arm: dts: dt-bindings: Add Renesas RZ pinctrl header
arm: dts: r7s72100: Add pin controller node
arm: dts: genmai: Add SCIF2 pin group
arm: dts: genmai: Add RIIC2 pin group
arm: dts: genmai: Add user led device nodes
arm: dts: genmai: Add ethernet pin group
.../bindings/pinctrl/renesas,rza1-pinctrl.txt | 143 +++
arch/arm/boot/dts/r7s72100-genmai.dts | 68 ++
arch/arm/boot/dts/r7s72100.dtsi | 80 ++
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-rza1.c | 961 +++++++++++++++++++++
include/dt-bindings/pinctrl/r7s72100-pinctrl.h | 36 +
7 files changed, 1299 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-rza1.c
create mode 100644 include/dt-bindings/pinctrl/r7s72100-pinctrl.h
--
2.7.4
^ permalink raw reply
* Re: [PATCH 1/3] device property: Move FW type specific functionality to FW specific files
From: Rafael J. Wysocki @ 2017-03-24 15:21 UTC (permalink / raw)
To: Sakari Ailus
Cc: Sakari Ailus, linux-acpi, devicetree, robh, sudeep.holla,
lorenzo.pieralisi, mika.westerberg, rafael, mark.rutland, broonie,
ahs3, frowand.list
In-Reply-To: <20170324114212.GA16657@valkosipuli.retiisi.org.uk>
On Friday, March 24, 2017 01:42:13 PM Sakari Ailus wrote:
> On Fri, Mar 24, 2017 at 01:03:50PM +0200, Sakari Ailus wrote:
> > The device and fwnode property API supports Devicetree, ACPI and pset
> > properties. The implementation of this functionality for each firmware
> > type was embedded in the fwnode property core. Move it out to firmware
> > type specific locations, making it easier to maintain.
> >
> > Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
>
> Oh, this escaped me a bit early.
>
> This set is the other part split off from the earlier "Move firmware
> specific code to firmware specific locations" set. It depends on my earlier
> the fwnode fixes, ACPI graph support patchsets and patch "device property:
> Read strings using string array reading functions" that are intended for the
> PM tree. They also depend on patch "of: Move OF property and graph API from
> base.c to property.c" which is intended for the DT tree --- this patch
> additionally depends on the patches on DT tree.
>
> The only change in the patches from the previous set is rebase, and a new
> patch adding support for fwnode_graph_get_remote_node() has been added. The
> last patch is currently untested. I'll test it in the near future; this set
> is not mergeable for a while until the dependent patches have been merged to
> the respective trees and a new rc1 release is available.
>
> I'm uploading the patches to the two branches here:
>
> Fwnode fixes + ACPI graph support + "device property:
> Read strings using string array reading functions":
>
> <URL:https://git.linuxtv.org/sailus/media_tree.git/log/?h=acpi-graph-all>
>
> The previous patches on Rob H's for-next branch + "of: Move OF property
> and graph API from base.c to property.c" + this patchset:
>
> <URL:https://git.linuxtv.org/sailus/media_tree.git/log/?h=acpi-graph-cleaned-on-next>
>
> It may still take a while until the patches get there.
I'd prefer to see them in Patchwork, though.
Can you please repost all stuff you want to go into 4.12 that has no
dependencies in other trees afresh?
Thanks,
Rafael
^ permalink raw reply
* Re: [PATCH v3 10/12] dt-bindings: mediatek: add MT6797 power dt-bindings
From: Rob Herring @ 2017-03-24 15:20 UTC (permalink / raw)
To: Mars Cheng
Cc: Matthias Brugger, Marc Zyngier, Michael Turquette, Stephen Boyd,
CC Hwang, Loda Chou, Miles Chen, Jades Shih, Yingjoe Chen,
My Chuang, linux-kernel, linux-mediatek, devicetree, wsd_upstream,
linux-clk, Kevin-CW Chen
In-Reply-To: <1489937193-2953-11-git-send-email-mars.cheng@mediatek.com>
On Sun, Mar 19, 2017 at 11:26:31PM +0800, Mars Cheng wrote:
> This adds scpsys dt-bindings for MT6797
>
> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> Signed-off-by: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
> ---
> .../devicetree/bindings/soc/mediatek/scpsys.txt | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v3 01/12] dt-bindings: mediatek: multiple bases support for sysirq
From: Rob Herring @ 2017-03-24 15:20 UTC (permalink / raw)
To: Mars Cheng
Cc: Matthias Brugger, Marc Zyngier, Michael Turquette, Stephen Boyd,
CC Hwang, Loda Chou, Miles Chen, Jades Shih, Yingjoe Chen,
My Chuang, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
wsd_upstream-NuS5LvNUpcJWk0Htik3J/w,
linux-clk-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1489937193-2953-2-git-send-email-mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Sun, Mar 19, 2017 at 11:26:22PM +0800, Mars Cheng wrote:
> This describes how to specify multiple base addresses for sysirq
> in mediatek platforms.
>
> Signed-off-by: Mars Cheng <mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> .../interrupt-controller/mediatek,sysirq.txt | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: thermal: add support for Broadcom's Northstar thermal
From: Rob Herring @ 2017-03-24 15:19 UTC (permalink / raw)
To: Rafał Miłecki
Cc: Zhang Rui, Eduardo Valentin, Mark Rutland, linux-pm, devicetree,
bcm-kernel-feedback-list, Rafał Miłecki
In-Reply-To: <20170318155632.18099-1-zajec5@gmail.com>
On Sat, Mar 18, 2017 at 04:56:31PM +0100, Rafał Miłecki wrote:
> From: Rafał Miłecki <rafal@milecki.pl>
>
> This commit documents binding for thermal used in Northstar family SoCs.
>
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
> ---
> .../devicetree/bindings/thermal/brcm,ns-thermal | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/thermal/brcm,ns-thermal
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 1/4] gpio: mvebu: Add limited PWM support
From: Rob Herring @ 2017-03-24 15:18 UTC (permalink / raw)
To: Ralph Sennhauser
Cc: linux-gpio, Andrew Lunn, Imre Kaloz, Thierry Reding,
Linus Walleij, Alexandre Courbot, Mark Rutland,
Greg Kroah-Hartman, David S. Miller, Geert Uytterhoeven,
Mauro Carvalho Chehab, Guenter Roeck, open list:PWM SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20170318154305.28348-2-ralph.sennhauser@gmail.com>
On Sat, Mar 18, 2017 at 04:43:01PM +0100, Ralph Sennhauser wrote:
> From: Andrew Lunn <andrew@lunn.ch>
>
> Armada 370/XP devices can 'blink' gpio lines with a configurable on
> and off period. This can be modelled as a PWM.
>
> However, there are only two sets of PWM configuration registers for
> all the gpio lines. This driver simply allows a single gpio line per
> gpio chip of 32 lines to be used as a PWM. Attempts to use more return
> EBUSY.
>
> Due to the interleaving of registers it is not simple to separate the
> PWM driver from the gpio driver. Thus the gpio driver has been
> extended with a PWM driver.
>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> URL: https://patchwork.ozlabs.org/patch/427287/
> URL: https://patchwork.ozlabs.org/patch/427295/
> [Ralph Sennhauser:
> * port forward
> * merge pwm portion into gpio-mvebu.c
> * merge documentation patch
> * update MAINTAINERS]
> Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
> ---
> .../devicetree/bindings/gpio/gpio-mvebu.txt | 31 +++
> MAINTAINERS | 2 +
> drivers/gpio/gpio-mvebu.c | 291 +++++++++++++++++++--
> 3 files changed, 307 insertions(+), 17 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> index a6f3bec..86932e3 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> @@ -38,6 +38,23 @@ Required properties:
> - #gpio-cells: Should be two. The first cell is the pin number. The
> second cell is reserved for flags, unused at the moment.
>
> +Optional properties:
> +
> +In order to use the gpio lines in PWM mode, some additional optional
> +properties are required. Only Armada 370 and XP support these properties.
> +
> +- reg: an additional register set is needed, for the GPIO Blink
> + Counter on/off registers.
> +
> +- reg-names: Must contain an entry "pwm" corresponding to the
> + additional register range needed for pwm operation.
> +
> +- #pwm-cells: Should be two. The first cell is the pin number. The
s/pin number/gpio line/ ?
> + second cell is reserved for flags and should be set to 0, so it has a
> + known value. It then becomes possible to use it in the future.
> +
> +- clocks: Must be a phandle to the clock for the gpio controller.
> +
> Example:
>
> gpio0: gpio@d0018100 {
> @@ -51,3 +68,17 @@ Example:
> #interrupt-cells = <2>;
> interrupts = <16>, <17>, <18>, <19>;
> };
> +
> + gpio1: gpio@18140 {
> + compatible = "marvell,orion-gpio";
If only 370 and XP support this, I'd expect a compatible string for one
of them here.
> + reg = <0x18140 0x40>, <0x181c8 0x08>;
> + reg-names = "gpio", "pwm";
> + ngpios = <17>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + #pwm-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <87>, <88>, <89>;
> + clocks = <&coreclk 0>;
> + };
^ permalink raw reply
* Re: [PATCH 3/9] arm64: mm: install SError abort handler
From: Mark Rutland @ 2017-03-24 15:16 UTC (permalink / raw)
To: Doug Berger
Cc: catalin.marinas-5wv7dgnIgG8, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
will.deacon-5wv7dgnIgG8, computersforpeace-Re5JQEeQqe8AvxtiuMwx3w,
gregory.0xf0-Re5JQEeQqe8AvxtiuMwx3w,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
wangkefeng.wang-hv44wF8Li93QT0dZR+AlfA, james.morse-5wv7dgnIgG8,
vladimir.murzin-5wv7dgnIgG8, panand-H+wXaHxf7aLQT0dZR+AlfA,
andre.przywara-5wv7dgnIgG8, cmetcalf-VPRAkNaXOzVWk0Htik3J/w,
mingo-DgEjT+Ai2ygdnm+yROfE0A,
sandeepa.s.prabhu-Re5JQEeQqe8AvxtiuMwx3w,
shijie.huang-5wv7dgnIgG8, linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
treding-DDmLM1+adcrQT0dZR+AlfA, jonathanh-DDmLM1+adcrQT0dZR+AlfA,
olof-nZhT3qVonbNeoWH0uzbU5w, mirza.krak-Re5JQEeQqe8AvxtiuMwx3w,
suzuki.poulose-5wv7dgnIgG8, bgolaszewski-rdvid1DuHRBWk0Htik3J/w,
horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170324144632.5896-4-opendmb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Fri, Mar 24, 2017 at 07:46:26AM -0700, Doug Berger wrote:
> This commit adds support for minimal handling of SError aborts and
> allows them to be hooked by a driver or other part of the kernel to
> install a custom SError abort handler. The hook function returns
> the previously registered handler so that handlers may be chained if
> desired.
>
> The handler should return the value 0 if the error has been handled,
> otherwise the handler should either call the next handler in the
> chain or return a non-zero value.
... so the order these get calls is completely dependent on probe
order...
> Since the Instruction Specific Syndrome value for SError aborts is
> implementation specific the registerred handlers must implement
> their own parsing of the syndrome.
... and drivers have to be intimately familiar with the CPU, in order to
be able to parse its IMPLEMENTATION DEFINED ESR_ELx.ISS value.
Even then, there's no guarantee there's anything useful there, since it
is IMPLEMENTATION DEFINED and could simply be RES0 or UNKNOWN in all
cases.
I do not think it is a good idea to allow arbitrary drivers to hook
this fault in this manner.
> + .align 6
> +el0_error:
> + kernel_entry 0
> +el0_error_naked:
> + mrs x25, esr_el1 // read the syndrome register
> + lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
> + cmp x24, #ESR_ELx_EC_SERROR // SError exception in EL0
> + b.ne el0_error_inv
> +el0_serr:
> + mrs x26, far_el1
> + // enable interrupts before calling the main handler
> + enable_dbg_and_irq
... why?
We don't do this for inv_entry today.
> + ct_user_exit
> + bic x0, x26, #(0xff << 56)
> + mov x1, x25
> + mov x2, sp
> + bl do_serr_abort
> + b ret_to_user
> +el0_error_inv:
> + enable_dbg
> + mov x0, sp
> + mov x1, #BAD_ERROR
> + mov x2, x25
> + b bad_mode
> +ENDPROC(el0_error)
Clearly you expect these to be delivered at arbitrary times during
execution. What if a KVM guest is executing at the time the SError is
delivered?
To be quite frank, I don't believe that we can reliably and safely
handle this misfeature in the kernel, and this infrastructure only
provides the illusion that we can.
I do not think it makes sense to do this.
Thanks,
Mark.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH] ARM: dts: am335x-baltos: add LED support
From: yegorslists-gM/Ye1E23mwN+BqQ9rBEUg @ 2017-03-24 15:15 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, tony-4v6yS6AI5VpBDgjK7y7TUQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Yegor Yefremov
From: Yegor Yefremov <yegorslists-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
All three devices provide GPIO based LEDs named power,
wlan and app.
Place the same definition in all three DTS files, as
there are other devices (not currently upstreamed), that
use am335x-baltos.dtsi but use different GPIOs for these
LEDs.
Signed-off-by: Yegor Yefremov <yegorslists-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
arch/arm/boot/dts/am335x-baltos-ir2110.dts | 32 ++++++++++++++++++++++++++++
arch/arm/boot/dts/am335x-baltos-ir3220.dts | 32 ++++++++++++++++++++++++++++
arch/arm/boot/dts/am335x-baltos-ir5221.dts | 34 ++++++++++++++++++++++++++++--
3 files changed, 96 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
index 501c752..e9b5544 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
@@ -17,9 +17,41 @@
/ {
model = "OnRISC Baltos iR 2110";
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds>;
+
+ compatible = "gpio-leds";
+
+ power {
+ label = "onrisc:red:power";
+ linux,default-trigger = "default-on";
+ gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ wlan {
+ label = "onrisc:blue:wlan";
+ gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ app {
+ label = "onrisc:green:app";
+ gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
};
&am33xx_pinmux {
+ user_leds: pinmux_user_leds {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_col.gpio3_0 PWR LED */
+ AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_txd3.gpio0_16 WLAN LED */
+ AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_txd2.gpio0_17 APP LED */
+ >;
+ };
+
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */
diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
index 19f53b8..0878379 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
@@ -17,9 +17,41 @@
/ {
model = "OnRISC Baltos iR 3220";
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds>;
+
+ compatible = "gpio-leds";
+
+ power {
+ label = "onrisc:red:power";
+ linux,default-trigger = "default-on";
+ gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ wlan {
+ label = "onrisc:blue:wlan";
+ gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ app {
+ label = "onrisc:green:app";
+ gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
};
&am33xx_pinmux {
+ user_leds: pinmux_user_leds {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_col.gpio3_0 PWR LED */
+ AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_txd3.gpio0_16 WLAN LED */
+ AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_txd2.gpio0_17 APP LED */
+ >;
+ };
+
tca6416_pins: pinmux_tca6416_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */
diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
index 2b9d7f4..e2da0aa 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
@@ -17,16 +17,47 @@
/ {
model = "OnRISC Baltos iR 5221";
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds>;
+
+ compatible = "gpio-leds";
+
+ power {
+ label = "onrisc:red:power";
+ linux,default-trigger = "default-on";
+ gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ wlan {
+ label = "onrisc:blue:wlan";
+ gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ app {
+ label = "onrisc:green:app";
+ gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
};
&am33xx_pinmux {
+ user_leds: pinmux_user_leds {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_col.gpio3_0 PWR LED */
+ AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_txd3.gpio0_16 WLAN LED */
+ AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_txd2.gpio0_17 APP LED */
+ >;
+ };
+
tca6416_pins: pinmux_tca6416_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */
>;
};
-
dcan1_pins: pinmux_dcan1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */
@@ -61,7 +92,6 @@
AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
>;
};
-
};
&uart1 {
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH 2/4 v5] PCI: add driver for Faraday Technology Host Bridge
From: Linus Walleij @ 2017-03-24 15:14 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Hans Ulli Kroll, Florian Fainelli, Rob Herring,
devicetree@vger.kernel.org, Bjorn Helgaas, Arnd Bergmann,
openwrt-devel, Feng-Hsin Chiang, Paulius Zaleckas, linux-pci,
Greentime Hu, Janos Laube, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20170324150753.GC25380@bhelgaas-glaptop.roam.corp.google.com>
On Fri, Mar 24, 2017 at 4:07 PM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Thanks!
> I don't know enough to review the DT patch, but you have Rob's ack
> already.
>
> Not sure how you want to merge these; if you want to feed the whole
> thing via ARM SoC, that's fine with me. Otherwise, let me know if
> you'd like me to take anything.
It'd be perfect if you could merge patches 1+2 into the PCI tree,
there are no dependencies to the ARM tree.
> Noticed one trivial typo below.
>
>> + * Special configuration registers directly in the first few words
>> + * in he I/O space.
>
> s/he//
Can you fix it when applying or do you want me to resend it with
this fixed?
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 1/5] iio: xoadc: augment DT bindings a bit
From: Rob Herring @ 2017-03-24 15:12 UTC (permalink / raw)
To: Linus Walleij
Cc: Jonathan Cameron, linux-iio-u79uwXL29TY76Z2rM5mHXA,
Bjorn Andersson, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170318133358.22314-1-linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Sat, Mar 18, 2017 at 02:33:58PM +0100, Linus Walleij wrote:
> In order to accommodate in a logical manner for the premuxed channels
> in PM8921 and the similarly addressed channels in later PMICs, we
> need a twocell arrangement with premux and analog mux setting as
> a tuple to uniquely identify a hardware channel.
>
> These bindings are not yet in use, so it should be find to augment
> them before we actually start using it in drivers and device trees.
>
> This scheme came out of lengthy discussions and reverse-engineering
> and reading of the few information sources we have.
>
> Suggested-by: Björn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> .../bindings/iio/adc/qcom,pm8xxx-xoadc.txt | 117 ++++++++++++---------
> 1 file changed, 69 insertions(+), 48 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt
> index 53cd146d8096..680bb7a29dd5 100644
> --- a/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt
> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt
> @@ -19,32 +19,42 @@ Required properties:
> with PMIC variant but is typically something like 2.2 or 1.8V.
>
> The following required properties are standard for IO channels, see
> -iio-bindings.txt for more details:
> +iio-bindings.txt for more details, but noitice that this particular
> +ADC has a special adressing scheme that require two cells for
> +identifying each ADC channel:
>
> -- #address-cells: should be set to <1>
> +- #address-cells: should be set to <2>, the first cell is the
> + prescaler (on PM8058) or premux (on PM8921) with two valid bits
> + so legal values are 0x00, 0x01 or 0x02. The second cell
> + is the main analog mux setting (0x00..0x0f). The combination
> + of prescaler/premux and analog mux uniquely addresses a hardware
> + channel on all systems.
64-bits to describe 48 possible combinations... I'd just combine these
into 1 cell.
> - #size-cells: should be set to <0>
>
> -- #io-channel-cells: should be set to <1>
> +- #io-channel-cells: should be set to <2>, again the cells are
> + precaler or premux followed by the analog muxing line.
>
> - interrupts: should refer to the parent PMIC interrupt controller
> and reference the proper ADC interrupt.
>
> Required subnodes:
>
> -The ADC channels are configured as subnodes of the ADC. Since some of
> -them are used for calibrating the ADC, these nodes are compulsory:
> +The ADC channels are configured as subnodes of the ADC.
>
> -adc-channel@c {
> - reg = <0x0c>;
> +Since some of them are used for calibrating the ADC, these nodes are
> +compulsory:
> +
> +adc-channel@0c {
> + reg = <0x00 0x0c>;
> };
>
> -adc-channel@d {
> - reg = <0x0d>;
> +adc-channel@0d {
> + reg = <0x00 0x0d>;
> };
>
> -adc-channel@f {
> - reg = <0x0f>;
> +adc-channel@0f {
> + reg = <0x00 0x0f>;
> };
>
> These three nodes are used for absolute and ratiometric calibration
> @@ -52,13 +62,26 @@ and only need to have these reg values: they are by hardware definition
> 1:1 ratio converters that sample 625, 1250 and 0 milliV and create
> an interpolation calibration for all other ADCs.
>
> -Optional subnodes: any channels other than channel 0x0c, 0x0d and
> -0x0f are optional.
> +Optional subnodes: any channels other than channels [0x00 0x0c],
> +[0x00 0x0d] and [0x00 0x0f] are optional.
>
> Required channel node properties:
>
> - reg: should contain the hardware channel number in the range
> - 0 .. 0x0f (4 bits). The hardware only supports 16 channels.
> + 0 .. 0xff (8 bits).
> +
> + On PM8058 the hardware only supports 16 channels, but we get the same
> + channels repeating with its input divided down by 1 or 3. Channels 00,
> + 10, 20, ... f0 are the raw values, 04, 14, 24 .. f4 are "unity" channels
> + divided by 1, and 08, 18, 28 .. f8 are channels divided by 3. Bits 0
> + and 1 of the channel index should always be 0.
> +
> + On PM8921 the hardware supports more than 16 channels through a complex
> + routing matrix using a premux, so 00, 10, 20 .. f0 are the basic raw
> + channels while another set of channels appear for 04, 14, 24 .. f4,
> + and again some of the same channels appear again divided down by 3
> + in 08, 18, 28 .. f8. Again bits 0 and 1 of the channel index should
> + always be 0.
Now I'm lost...
Rob
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 2/4 v5] PCI: add driver for Faraday Technology Host Bridge
From: Bjorn Helgaas @ 2017-03-24 15:07 UTC (permalink / raw)
To: Linus Walleij
Cc: Hans Ulli Kroll, Florian Fainelli, Rob Herring,
devicetree-u79uwXL29TY76Z2rM5mHXA, Bjorn Helgaas, Arnd Bergmann,
openwrt-devel-p3rKhJxN3npAfugRpC6u6w, Feng-Hsin Chiang,
Paulius Zaleckas, linux-pci-u79uwXL29TY76Z2rM5mHXA, Greentime Hu,
Janos Laube, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170312222403.2473-1-linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Sun, Mar 12, 2017 at 11:24:03PM +0100, Linus Walleij wrote:
> This adds a host bridge driver for the Faraday Technology
> FPPCI100 host bridge, used for Cortina Systems Gemini SoC
> (SL3516) PCI Host Bridge.
>
> This code is inspired by the out-of-tree OpenWRT patch and
> then extensively rewritten for device tree and using the modern
> helpers to cut down and modernize the code to all new PCI
> frameworks. A driver exists in U-Boot as well.
>
> Tested on the ITian Square One SQ201 NAS with the following
> result in the boot log (trimmed to relevant parts):
>
> OF: PCI: host bridge /soc/pci@50000000 ranges:
> OF: PCI: IO 0x50000000..0x500fffff -> 0x00000000
> OF: PCI: MEM 0x58000000..0x5fffffff -> 0x58000000
> ftpci100 50000000.pci: PCI host bridge to bus 0000:00
> pci_bus 0000:00: root bus resource [bus 00-ff]
> pci_bus 0000:00: root bus resource [io 0x0000-0xfffff]
> pci_bus 0000:00: root bus resource [mem 0x58000000-0x5fffffff]
> ftpci100 50000000.pci:
> DMA MEM1 BASE: 0x0000000000000000 -> 0x0000000007ffffff config 00070000
> ftpci100 50000000.pci:
> DMA MEM2 BASE: 0x0000000000000000 -> 0x0000000003ffffff config 00060000
> ftpci100 50000000.pci:
> DMA MEM3 BASE: 0x0000000000000000 -> 0x0000000003ffffff config 00060000
> PCI: bus0: Fast back to back transfers disabled
> pci 0000:00:00.0: of_irq_parse_pci() failed with rc=-22
> pci 0000:00:0c.0: BAR 0: assigned [mem 0x58000000-0x58007fff]
> pci 0000:00:09.2: BAR 0: assigned [mem 0x58008000-0x580080ff]
> pci 0000:00:09.0: BAR 4: assigned [io 0x1000-0x101f]
> pci 0000:00:09.1: BAR 4: assigned [io 0x1020-0x103f]
> pci 0000:00:09.0: enabling device (0140 -> 0141)
> pci 0000:00:09.0: HCRESET not completed yet!
> pci 0000:00:09.1: enabling device (0140 -> 0141)
> pci 0000:00:09.1: HCRESET not completed yet!
> pci 0000:00:09.2: enabling device (0140 -> 0142)
> rt61pci 0000:00:0c.0: enabling device (0140 -> 0142)
> ieee80211 phy0: rt2x00_set_chip: Info - Chipset detected -
> rt: 2561, rf: 0003, rev: 000c
> ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
> ehci-pci: EHCI PCI platform driver
> ehci-pci 0000:00:09.2: EHCI Host Controller
> ehci-pci 0000:00:09.2: new USB bus registered, assigned bus number 1
> ehci-pci 0000:00:09.2: irq 125, io mem 0x58008000
> ehci-pci 0000:00:09.2: USB 2.0 started, EHCI 1.00
> hub 1-0:1.0: USB hub found
> hub 1-0:1.0: 4 ports detected
> uhci_hcd: USB Universal Host Controller Interface driver
> uhci_hcd 0000:00:09.0: UHCI Host Controller
> uhci_hcd 0000:00:09.0: new USB bus registered, assigned bus number 2
> uhci_hcd 0000:00:09.0: HCRESET not completed yet!
> uhci_hcd 0000:00:09.0: irq 123, io base 0x00001000
> hub 2-0:1.0: USB hub found
> hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
> uhci_hcd 0000:00:09.1: UHCI Host Controller
> uhci_hcd 0000:00:09.1: new USB bus registered, assigned bus number 3
> uhci_hcd 0000:00:09.1: HCRESET not completed yet!
> uhci_hcd 0000:00:09.1: irq 124, io base 0x00001020
> hub 3-0:1.0: USB hub found
> hub 3-0:1.0: config failed, hub doesn't have any ports! (err -19)
> scsi 0:0:0:0: Direct-Access USB Flash Disk 1.00 PQ: 0 ANSI: 2
> sd 0:0:0:0: [sda] 7900336 512-byte logical blocks: (4.04 GB/3.77 GiB)
> sd 0:0:0:0: [sda] Write Protect is off
> sd 0:0:0:0: [sda] No Caching mode page found
> sd 0:0:0:0: [sda] Assuming drive cache: write through
> sda: sda1 sda2 sda3
> sd 0:0:0:0: [sda] Attached SCSI removable disk
> ieee80211 phy0: rt2x00lib_request_firmware: Info -
> Loading firmware file 'rt2561s.bin'
> ieee80211 phy0: rt2x00lib_request_firmware: Info -
> Firmware detected - version: 0.8
> IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready
>
> $ lspci
> 00:00.0 Class 0600: 159b:4321
> 00:09.2 Class 0c03: 1106:3104
> 00:09.0 Class 0c03: 1106:3038
> 00:09.1 Class 0c03: 1106:3038
> 00:0c.0 Class 0280: 1814:0301
>
> cat /proc/interrupts
> CPU0
> 123: 0 PCI 0 Edge uhci_hcd:usb2
> 124: 0 PCI 1 Edge uhci_hcd:usb3
> 125: 159 PCI 2 Edge ehci_hcd:usb1
> 126: 1082 PCI 3 Edge rt61pci
>
> cat /proc/iomem
> 50000000-500000ff : /soc/pci@50000000
> 58000000-5fffffff : Gemini PCI MEM
> 58000000-58007fff : 0000:00:0c.0
> 58000000-58007fff : 0000:00:0c.0
> 58008000-580080ff : 0000:00:09.2
> 58008000-580080ff : ehci_hcd
>
> The EHCI USB hub works fine, I can mount and manage
> files and the IRQs just keep ticking up. I can issue
> iwlist wlan0 scanning and see all the WLANs here, I don't have
> wpa_supplicant so have not tried connecting to them.
>
> Cc: Janos Laube <janos.dev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Paulius Zaleckas <paulius.zaleckas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Hans Ulli Kroll <ulli.kroll-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> Cc: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Feng-Hsin Chiang <john453-w0jeGXs5+AWXmMXjJBpWqg@public.gmane.org>
> Cc: Greentime Hu <green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Acked-by: Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
I don't know enough to review the DT patch, but you have Rob's ack
already.
Not sure how you want to merge these; if you want to feed the whole
thing via ARM SoC, that's fine with me. Otherwise, let me know if
you'd like me to take anything.
Noticed one trivial typo below.
> + * Special configuration registers directly in the first few words
> + * in he I/O space.
s/he//
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 2/3] firmware: qcom: scm: Expose download-mode control
From: Rob Herring @ 2017-03-24 15:06 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Stephen Boyd, Mark Rutland, David Brown,
Srinivas Kandagatla, linux-kernel, linux-arm-msm, linux-soc,
devicetree
In-Reply-To: <20170318041523.29757-2-bjorn.andersson@linaro.org>
On Fri, Mar 17, 2017 at 09:15:22PM -0700, Bjorn Andersson wrote:
> In order to aid post-mortem debugging the Qualcomm platforms provides a
> "memory download mode", where the boot loader will provide an interface
> for custom tools to "download" the content of RAM to a host machine.
>
> The mode is triggered by writing a magic value somehwere in RAM, that is
> read in the boot code path after a warm-restart. Two mechanism for
> setting this magic value are supported in modern platforms; a direct SCM
> call to enable the mode or through a secure io write of a magic value.
>
> In order for a normal reboot not to trigger "download mode" the magic
> must be cleared during a clean reboot.
>
> Download mode has to be enabled by including qcom_scm.download_mode=1 on
> the command line.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> .../devicetree/bindings/firmware/qcom,scm.txt | 1 +
> drivers/firmware/qcom_scm-32.c | 6 ++++
> drivers/firmware/qcom_scm-64.c | 16 +++++++++
> drivers/firmware/qcom_scm.c | 42 ++++++++++++++++++++++
> drivers/firmware/qcom_scm.h | 2 ++
> 5 files changed, 67 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
> index 20f26fbce875..8467a181f22c 100644
> --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
> +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
> @@ -18,6 +18,7 @@ Required properties:
> * Core, iface, and bus clocks required for "qcom,scm"
> - clock-names: Must contain "core" for the core clock, "iface" for the interface
> clock and "bus" for the bus clock per the requirements of the compatible.
> +- qcom,dload-mode-addr: Specifies the address for the download mode magic (optional)
Size? 1 cell, 2 cell(, red cell, blue cell) or follows #addr-cells?
Rob
^ permalink raw reply
* Re: [PATCH 0/9] bus: brcmstb_gisb: add support for GISBv7 arbiter
From: Mark Rutland @ 2017-03-24 15:03 UTC (permalink / raw)
To: Doug Berger
Cc: catalin.marinas, robh+dt, will.deacon, computersforpeace,
gregory.0xf0, f.fainelli, bcm-kernel-feedback-list,
wangkefeng.wang, james.morse, vladimir.murzin, panand,
andre.przywara, cmetcalf, mingo, sandeepa.s.prabhu, shijie.huang,
linus.walleij, treding, jonathanh, olof, mirza.krak,
suzuki.poulose, bgolaszewski, horms+renesas, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20170324144632.5896-1-opendmb@gmail.com>
On Fri, Mar 24, 2017 at 07:46:23AM -0700, Doug Berger wrote:
> This patch set contains changes to enable the GISB arbiter driver
> on the latest ARM64 architecture Set-Top Box chips from Broadcom.
>
> This driver relies on being able to hook the abort handlers of
> the processor core that are triggered by bus error signals
> generated by the GISB bus arbiter hardware found in BCM7XXX chips.
Ugh; hardware generating asynchonous exceptions is hideous. I had hoped
that such hardware was a thing of the past.
Under what circumstances does the GISB bus arbiter generate these
aborts?
Mark.
> The first three patches are based on the arm64/for-next/core
> branch to enable this functionality for the arm64 architecture.
>
> The remaining patches correct some issues with the existing driver,
> add the ARM64 architecture specific support to the driver, and
> finally add the new register map for the GISBv7 hardware first
> appearing in the BCM7278 device.
>
> Doug Berger (7):
> arm64: mm: mark fault_info __ro_after_init
> arm64: mm: install SError abort handler
> bus: brcmstb_gisb: Use register offsets with writes too
> bus: brcmstb_gisb: Correct hooking of ARM aborts
> bus: brcmstb_gisb: correct support for 64-bit address output
> bus: brcmstb_gisb: add ARM64 SError support
> bus: brcmstb_gisb: update to support new revision
>
> Florian Fainelli (2):
> arm64: mm: Allow installation of memory abort handlers
> bus: brcmstb_gisb: Add ARM64 support
>
> .../devicetree/bindings/bus/brcm,gisb-arb.txt | 3 +-
> arch/arm64/include/asm/system_misc.h | 5 +
> arch/arm64/kernel/entry.S | 69 ++++++++++++--
> arch/arm64/mm/fault.c | 48 +++++++++-
> drivers/bus/Kconfig | 2 +-
> drivers/bus/brcmstb_gisb.c | 106 ++++++++++++++++-----
> 6 files changed, 197 insertions(+), 36 deletions(-)
>
> --
> 2.12.0
>
^ permalink raw reply
* Re: [PATCH v3 1/2] doc: Add bindings document for Xilinx LogiCore PR Decoupler
From: Rob Herring @ 2017-03-24 14:59 UTC (permalink / raw)
To: Moritz Fischer
Cc: linux-fpga-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, Michal Simek,
Sören Brinkmann, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1489781473-30772-1-git-send-email-mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
On Fri, Mar 17, 2017 at 01:11:12PM -0700, Moritz Fischer wrote:
> This adds the binding documentation for the Xilinx LogiCORE PR
> Decoupler soft core.
>
> Signed-off-by: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> Cc: Sören Brinkmann <soren.brinkmann-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>
> Changes from v2:
> - Added refence to generic fpga-region bindings
> - Fixed up reg property in example
> - Added fallback to "xlnx,pr-decoupler" without version
>
> Changes from v1:
> - Added clock names & clock to example
> - Merged some of the description from Michal's version
>
> ---
> .../bindings/fpga/xilinx-pr-decoupler.txt | 35 ++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
> new file mode 100644
> index 0000000..16141bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
> @@ -0,0 +1,35 @@
> +Xilinx LogiCORE Partial Reconfig Decoupler Softcore
> +
> +The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
> +decouplers / fpga bridges.
> +The controller can decouple/disable the bridges which prevents signal
> +changes from passing through the bridge. The controller can also
> +couple / enable the bridges which allows traffic to pass through the
> +bridge normally.
> +
> +The Driver supports only MMIO handling. A PR region can have multiple
> +PR Decouples which can bhe handled independently or chaines via decouple/
s/chaines/chains/
> +decouple_status signals.
> +
> +Required properties:
> +- compatible : Should contain "xlnx,pr-decoupler-1.00"
> +- regs : base address and size for decoupler module
> +- clocks : input clock to IP
> +- clock-names : should contain "aclk"
> +
> +Optional properties:
> +- bridge-enable : 0 if driver should disable bridge at startup
> + 1 if driver should enable bridge at startup
> + Default is to leave bridge in current state.
This is common and should move into a common doc. Maybe fpga-region.txt
works?
> +
> +See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
> +
> +Example:
> + fpga-bridge@100000450 {
> + compatible = "xlnx,pr-decoupler-1.00",
> + "xlnx-pr-decoupler";
> + regs = <0x10000045 0x10>;
> + clocks = <&clkc 15>;
> + clock-names = "aclk";
> + bridge-enable = <0>;
> + };
> --
> 2.7.4
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v4 1/7] coresight: bindings for CPU debug module
From: Rob Herring @ 2017-03-24 14:54 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Leo Yan, Mark Rutland, Wei Xu, Catalin Marinas, Will Deacon,
Andy Gross, David Brown, Michael Turquette, Stephen Boyd,
Guodong Xu, John Stultz, Greg Kroah-Hartman, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc,
linux-clk, mike.leach, Suzuki.Poulose, sudeep.holla
In-Reply-To: <20170317161335.GB20435@linaro.org>
On Fri, Mar 17, 2017 at 10:13:35AM -0600, Mathieu Poirier wrote:
> On Fri, Mar 17, 2017 at 11:02:17PM +0800, Leo Yan wrote:
> > According to ARMv8 architecture reference manual (ARM DDI 0487A.k)
> > Chapter 'Part H: External debug', the CPU can integrate debug module
> > and it can support self-hosted debug and external debug. Especially
> > for supporting self-hosted debug, this means the program can access
> > the debug module from mmio region; and usually the mmio region is
> > integrated with coresight.
> >
> > So add document for binding debug component, includes binding to APB
> > clock; and also need specify the CPU node which the debug module is
> > dedicated to specific CPU.
> >
> > Suggested-by: Mike Leach <mike.leach@linaro.org>
> > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Signed-off-by: Leo Yan <leo.yan@linaro.org>
> > ---
> > .../bindings/arm/coresight-cpu-debug.txt | 46 ++++++++++++++++++++++
> > 1 file changed, 46 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
> >
> > diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
> > new file mode 100644
> > index 0000000..f6855c3
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
> > @@ -0,0 +1,46 @@
> > +* CoreSight CPU Debug Component:
> > +
> > +CoreSight cpu debug component are compliant with the ARMv8 architecture
> > +reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
> > +external debug module is mainly used for two modes: self-hosted debug and
> > +external debug, and it can be accessed from mmio region from Coresight
> > +and eventually the debug module connects with CPU for debugging. And the
> > +debug module provides sample-based profiling extension, which can be used
> > +to sample CPU program counter, secure state and exception level, etc;
> > +usually every CPU has one dedicated debug module to be connected.
> > +
> > +Required properties:
> > +
> > +- compatible : should be
> > + * "arm,coresight-cpu-debug"; supplemented with "arm,primecell"
> > + since this driver is using the AMBA bus interface.
>
> This description needs to be refactored - see my comment from an earlier post
> for more details.
>
> > +
> > +- reg : physical base address and length of the register set.
> > +
> > +- clocks : the clock associated to this component.
> > +
> > +- clock-names : the name of the clock referenced by the code. Since we are
> > + using the AMBA framework, the name of the clock providing
> > + the interconnect should be "apb_pclk" and the clock is
> > + mandatory. The interface between the debug logic and the
> > + processor core is clocked by the internal CPU clock, so it
> > + is enabled with CPU clock by default.
> > +
> > +- cpu : the cpu phandle the debug module is affined to. When omitted
> > + the module is considered to belong to CPU0.
> > +
> > +Optional properties:
>
> s/properties/property
I prefer it as-is. Then it doesn't need to be changed if we add
properties.
Rob
^ permalink raw reply
* Re: [PATCH v3 10/11] ASoC: add bindings for stm32 DFSDM filter
From: Rob Herring @ 2017-03-24 14:52 UTC (permalink / raw)
To: Arnaud Pouliquen
Cc: Mark Rutland, devicetree, alsa-devel, Lars-Peter Clausen,
olivier moysan, kernel, Liam Girdwood, linux-iio, Takashi Iwai,
Maxime Coquelin, Mark Brown, linux-arm-kernel,
Peter Meerwald-Stadler, Hartmut Knaack, Jonathan Cameron,
Alexandre Torgue
In-Reply-To: <1489759704-30217-11-git-send-email-arnaud.pouliquen@st.com>
On Fri, Mar 17, 2017 at 03:08:23PM +0100, Arnaud Pouliquen wrote:
> Add bindings that describes audio settings to support
> Digital Filter for pulse density modulation(PDM) microphone.
>
> Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
> ---
> V2->V3:
> Fixes based on V2 comments
>
> .../devicetree/bindings/sound/st,stm32-adfsdm.txt | 41 ++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt
>
> diff --git a/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt b/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt
> new file mode 100644
> index 0000000..ab610bc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt
> @@ -0,0 +1,40 @@
> +STMicroelectronics audio DFSDM DT bindings
> +
> +This driver supports audio PDM microphone capture through Digital Filter format
> +Sigma Delta modulators (DFSDM).
> +
> +Required properties:
> + - compatible: "st,stm32h7-adfsdm".
> +
> + - #sound-dai-cells : Must be equal to 0
> +
> + - io-channels : phandle to iio dfsdm instance node.
> +
> +
> +Example of a simple sound card using audio DFSDM node.
> +
> + dmic0: dmic_@0 {
Drop the '_' and unit address.
> + compatible = "dmic-codec";
> + #sound-dai-cells = <0>;
> + };
> +
> + asoc-pdm@0 {
asoc is a Linux term. Drop the unit address.
> + compatible = "st,stm32h7-adfsdm";
Is this a separate block from the ADC? A drawing of the h/w blocks and
connections would help.
> + #sound-dai-cells = <0>;
> + io-channels = <&dfsdm_adc0 0>;
> + };
> +
> + sound_dfsdm_pdm {
sound-card {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "dfsdm_pdm";
> +
> + dfsdm0_mic0: simple-audio-card,dai-link@0 {
I'd suggest moving to the graph card.
> + format = "pdm";
> + cpu {
> + sound-dai = <&asoc_pdm1>;
This phandle doesn't point to anything.
> + };
> + dmic0_codec: codec {
> + sound-dai = <&dmic0>;
> + };
> + };
> + };
> \ No newline at end of file
^^^
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH 2/2] MIPS: NI 169445 board support
From: Nathan Sullivan @ 2017-03-24 14:46 UTC (permalink / raw)
To: Rob Herring
Cc: linus.walleij, gnurou, mark.rutland, devicetree, ralf,
linux-kernel, linux-gpio, linux-mips
In-Reply-To: <20170323222945.bxz4qa6ydicrh4q6@rob-hp-laptop>
On Thu, Mar 23, 2017 at 05:29:45PM -0500, Rob Herring wrote:
> On Tue, Mar 14, 2017 at 11:13:23AM -0500, Nathan Sullivan wrote:
> > Support the National Instruments 169445 board.
> >
> > Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
> > ---
> > Documentation/devicetree/bindings/mips/ni.txt | 7 ++
> > MAINTAINERS | 8 ++
> > arch/mips/boot/dts/Makefile | 1 +
> > arch/mips/boot/dts/ni/169445.dts | 100 ++++++++++++++++++++++++
> > arch/mips/boot/dts/ni/Makefile | 7 ++
> > arch/mips/configs/generic/board-ni169445.config | 27 +++++++
> > arch/mips/generic/Kconfig | 6 ++
> > arch/mips/generic/vmlinux.its.S | 25 ++++++
> > 8 files changed, 181 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mips/ni.txt
> > create mode 100644 arch/mips/boot/dts/ni/169445.dts
> > create mode 100644 arch/mips/boot/dts/ni/Makefile
> > create mode 100644 arch/mips/configs/generic/board-ni169445.config
> >
> > diff --git a/Documentation/devicetree/bindings/mips/ni.txt b/Documentation/devicetree/bindings/mips/ni.txt
> > new file mode 100644
> > index 0000000..722bf2d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mips/ni.txt
> > @@ -0,0 +1,7 @@
> > +National Instruments MIPS platforms
> > +
> > +required root node properties:
> > + - compatible: must be "ni,169445"
> > +
> > +CPU Nodes
> > + - compatible: must be "mti,mips14KEc"
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index c265a5f..b72f059 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -8887,6 +8887,14 @@ F: include/linux/sunrpc/
> > F: include/uapi/linux/nfs*
> > F: include/uapi/linux/sunrpc/
> >
> > +NI169445 MIPS ARCHITECTURE
> > +M: Nathan Sullivan <nathan.sullivan@ni.com>
> > +L: linux-mips@linux-mips.org
> > +S: Maintained
> > +F: arch/mips/boot/dts/ni/
> > +F: arch/mips/configs/generic/board-ni169445.config
> > +F: Documentation/devicetree/bindings/mips/ni.txt
> > +
> > NILFS2 FILESYSTEM
> > M: Ryusuke Konishi <konishi.ryusuke@lab.ntt.co.jp>
> > L: linux-nilfs@vger.kernel.org
> > diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
> > index b9db492..27b0f37 100644
> > --- a/arch/mips/boot/dts/Makefile
> > +++ b/arch/mips/boot/dts/Makefile
> > @@ -4,6 +4,7 @@ dts-dirs += img
> > dts-dirs += ingenic
> > dts-dirs += lantiq
> > dts-dirs += mti
> > +dts-dirs += ni
> > dts-dirs += netlogic
> > dts-dirs += pic32
> > dts-dirs += qca
> > diff --git a/arch/mips/boot/dts/ni/169445.dts b/arch/mips/boot/dts/ni/169445.dts
> > new file mode 100644
> > index 0000000..9746576
> > --- /dev/null
> > +++ b/arch/mips/boot/dts/ni/169445.dts
> > @@ -0,0 +1,100 @@
> > +/dts-v1/;
> > +
> > +/ {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "ni,169445";
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + cpu@0 {
> > + device_type = "cpu";
> > + compatible = "mti,mips14KEc";
> > + clocks = <&baseclk>;
> > + reg = <0>;
> > + };
> > + };
> > +
> > + memory@0 {
> > + device_type = "memory";
> > + reg = <0x0 0x10000000>;
> > + };
> > +
> > + baseclk: baseclock {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <50000000>;
> > + };
> > +
> > + cpu_intc: cpu_intc {
>
> interrupt-controller {
>
> > + #address-cells = <0>;
> > + compatible = "mti,cpu-interrupt-controller";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > +
> > + ahb@0 {
>
> ahb@1f300000
>
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x0 0x1f300000 0x80FFF>;
> > +
> > + gpio1:gpio-controller@1f300010 {
> ^ space
>
> 'gpio' is the standard node name, so
>
> gpio@...
>
> > + compatible = "ni,169445-nand-gpio";
> > + reg = <0x10 0x4>;
> > + reg-names = "dat";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + };
> > +
> > + gpio2:gpio-controller@1f300014 {
>
> ditto
>
> > + compatible = "ni,169445-nand-gpio";
> > + reg = <0x14 0x4>;
> > + reg-names = "dat";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + no-output;
> > + };
> > +
> > + nand@1f300000 {
> > + compatible = "gpio-control-nand";
> > + nand-on-flash-bbt;
> > + nand-ecc-mode = "soft_bch";
> > + nand-ecc-step-size = <512>;
> > + nand-ecc-strength = <4>;
> > + reg = <0x0 4>;
> > + gpios = <&gpio2 0 0>, /* rdy */
> > + <&gpio1 1 0>, /* nce */
> > + <&gpio1 2 0>, /* ale */
> > + <&gpio1 3 0>, /* cle */
> > + <&gpio1 4 0>; /* nwp */
> > + };
> > +
> > + serial@1f380000 {
> > + compatible = "ns16550a";
> > + reg = <0x80000 0x1000>;
> > + interrupt-parent = <&cpu_intc>;
> > + interrupts = <6>;
> > + clocks = <&baseclk>;
> > + reg-shift = <0>;
> > + };
> > +
> > + ethernet@1f340000 {
> > + compatible = "snps,dwmac-4.10a";
> > + interrupt-parent = <&cpu_intc>;
> > + interrupts = <5>;
> > + interrupt-names = "macirq";
> > + reg = <0x40000 0x2000>;
> > + clock-names = "stmmaceth", "pclk";
> > + clocks = <&baseclk>, <&baseclk>;
> > +
> > + phy-mode = "rgmii";
> > +
> > + fixed-link {
> > + speed = <1000>;
> > + full-duplex;
> > + };
> > + };
> > + };
> > +};
> > diff --git a/arch/mips/boot/dts/ni/Makefile b/arch/mips/boot/dts/ni/Makefile
> > new file mode 100644
> > index 0000000..66cfdff
> > --- /dev/null
> > +++ b/arch/mips/boot/dts/ni/Makefile
> > @@ -0,0 +1,7 @@
> > +dtb-$(CONFIG_FIT_IMAGE_FDT_NI169445) += 169445.dtb
> > +
> > +# Force kbuild to make empty built-in.o if necessary
> > +obj- += dummy.o
> > +
> > +always := $(dtb-y)
> > +clean-files := *.dtb *.dtb.S
> > diff --git a/arch/mips/configs/generic/board-ni169445.config b/arch/mips/configs/generic/board-ni169445.config
> > new file mode 100644
> > index 0000000..0bae1f8
> > --- /dev/null
> > +++ b/arch/mips/configs/generic/board-ni169445.config
> > @@ -0,0 +1,27 @@
> > +CONFIG_FIT_IMAGE_FDT_NI169445=y
> > +
> > +CONFIG_SERIAL_8250=y
> > +CONFIG_SERIAL_8250_CONSOLE=y
> > +CONFIG_SERIAL_OF_PLATFORM=y
> > +
> > +CONFIG_GPIOLIB=y
> > +CONFIG_GPIO_SYSFS=y
> > +CONFIG_GPIO_GENERIC_PLATFORM=y
> > +
> > +CONFIG_MTD=y
> > +CONFIG_MTD_BLOCK=y
> > +CONFIG_MTD_CMDLINE_PARTS=y
> > +
> > +CONFIG_MTD_NAND_ECC=y
> > +CONFIG_MTD_NAND_ECC_BCH=y
> > +CONFIG_MTD_NAND=y
> > +CONFIG_MTD_NAND_GPIO=y
> > +CONFIG_MTD_NAND_IDS=y
> > +
> > +CONFIG_MTD_UBI=y
> > +CONFIG_MTD_UBI_BLOCK=y
> > +
> > +CONFIG_NETDEVICES=y
> > +CONFIG_STMMAC_ETH=y
> > +CONFIG_STMMAC_PLATFORM=y
> > +CONFIG_DWMAC_GENERIC=y
> > diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
> > index a606b3f..fbf0813 100644
> > --- a/arch/mips/generic/Kconfig
> > +++ b/arch/mips/generic/Kconfig
> > @@ -16,4 +16,10 @@ config LEGACY_BOARD_SEAD3
> > Enable this to include support for booting on MIPS SEAD-3 FPGA-based
> > development boards, which boot using a legacy boot protocol.
> >
> > +config FIT_IMAGE_FDT_NI169445
> > + bool "Include FDT for NI 169445"
> > + help
> > + Enable this to include the FDT for the 169445 platform from
> > + National Instruments in the FIT kernel image.
> > +
> > endif
> > diff --git a/arch/mips/generic/vmlinux.its.S b/arch/mips/generic/vmlinux.its.S
> > index f67fbf1..de851f7 100644
> > --- a/arch/mips/generic/vmlinux.its.S
> > +++ b/arch/mips/generic/vmlinux.its.S
> > @@ -29,3 +29,28 @@
> > };
> > };
> > };
> > +
> > +#ifdef CONFIG_FIT_IMAGE_FDT_NI169445
> > +/ {
>
> IMO, this shouldn't be in the kernel. Is the kernel supposed to
> create board specific images for every bootloaders custom format? It
> doesn't scale.
>
This is how the linux MIPS tree is doing generic kernels. Ralf, care to
elaborate?
The format is the same for each board, just with different trees and
configurations. It's a little odd with just one board right now, the
linux-mti tree has a bigger set.
> > + images {
> > + fdt@ni169445 {
> > + description = "NI 169445 device tree";
> > + data = /incbin/("boot/dts/ni/169445.dtb");
> > + type = "flat_dt";
> > + arch = "mips";
> > + compression = "none";
> > + hash@0 {
> > + algo = "sha1";
> > + };
> > + };
> > + };
> > +
> > + configurations {
> > + conf@ni169445 {
> > + description = "NI 169445 Linux Kernel";
> > + kernel = "kernel@0";
> > + fdt = "fdt@ni169445";
> > + };
> > + };
> > +};
> > +#endif
> > --
> > 2.1.4
> >
^ permalink raw reply
* [PATCH 9/9] bus: brcmstb_gisb: update to support new revision
From: Doug Berger @ 2017-03-24 14:46 UTC (permalink / raw)
To: catalin.marinas
Cc: robh+dt, mark.rutland, will.deacon, computersforpeace,
gregory.0xf0, f.fainelli, bcm-kernel-feedback-list,
wangkefeng.wang, james.morse, vladimir.murzin, panand,
andre.przywara, cmetcalf, mingo, sandeepa.s.prabhu, shijie.huang,
linus.walleij, treding, jonathanh, olof, mirza.krak,
suzuki.poulose, bgolaszewski, horms+renesas, devicetree,
linux-kernel, linux-arm-kernel, opendmb
In-Reply-To: <20170324144632.5896-1-opendmb@gmail.com>
The 7278 introduces a new version of this core. This
commit adds support for that revision.
Signed-off-by: Doug Berger <opendmb@gmail.com>
---
Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt | 3 ++-
drivers/bus/brcmstb_gisb.c | 10 ++++++++++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
index 1eceefb20f01..8a6c3c2e58fe 100644
--- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
+++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
@@ -3,7 +3,8 @@ Broadcom GISB bus Arbiter controller
Required properties:
- compatible:
- "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for 28nm chips
+ "brcm,bcm7278-gisb-arb" for V7 28nm chips
+ "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips
"brcm,bcm7435-gisb-arb" for newer 40nm chips
"brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
"brcm,bcm7038-gisb-arb" for 130nm chips
diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c
index 52b5d96081eb..a91c4ae63e74 100644
--- a/drivers/bus/brcmstb_gisb.c
+++ b/drivers/bus/brcmstb_gisb.c
@@ -63,6 +63,15 @@ static const int gisb_offsets_bcm7038[] = {
[ARB_ERR_CAP_MASTER] = -1,
};
+static const int gisb_offsets_bcm7278[] = {
+ [ARB_TIMER] = 0x008,
+ [ARB_ERR_CAP_CLR] = 0x7f8,
+ [ARB_ERR_CAP_HI_ADDR] = -1,
+ [ARB_ERR_CAP_ADDR] = 0x7e0,
+ [ARB_ERR_CAP_STATUS] = 0x7f0,
+ [ARB_ERR_CAP_MASTER] = 0x7f4,
+};
+
static const int gisb_offsets_bcm7400[] = {
[ARB_TIMER] = 0x00c,
[ARB_ERR_CAP_CLR] = 0x0c8,
@@ -329,6 +338,7 @@ static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
{ .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 },
{ .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 },
{ .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
+ { .compatible = "brcm,bcm7278-gisb-arb", .data = gisb_offsets_bcm7278 },
{ .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
{ },
};
--
2.12.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox