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* Re: [RFC PATCH] of: Fix DMA configuration for non-DT masters
From: Oza Oza via iommu @ 2017-03-30 10:12 UTC (permalink / raw)
  To: Robin Murphy
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Linux IOMMU,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <CAMSpPPfw3+vDoD_rJD9Ny=kUtXf2v6Fm6Qksi=K=OEhfVNYy1Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

On Thu, Mar 30, 2017 at 8:51 AM, Oza Oza <oza.oza-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote:
> On Wed, Mar 29, 2017 at 11:12 PM, Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> wrote:
>> On 29/03/17 06:46, Oza Oza wrote:
>>> On Wed, Mar 29, 2017 at 10:23 AM, Oza Oza <oza.oza-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote:
>>>> On Wed, Mar 29, 2017 at 12:27 AM, Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> wrote:
>>>>> For PCI masters not represented in DT, we pass the OF node of their
>>>>> associated host bridge to of_dma_configure(), such that they can inherit
>>>>> the appropriate DMA configuration from whatever is described there.
>>>>> Unfortunately, whilst this has worked for the "dma-coherent" property,
>>>>> it turns out to miss the case where the host bridge node has a non-empty
>>>>> "dma-ranges", since nobody is expecting the 'device' to be a bus itself.
>>>>>
>>>>> It transpires, though, that the de-facto interface since the prototype
>>>>> change in 1f5c69aa51f9 ("of: Move of_dma_configure() to device.c to help
>>>>> re-use") is very clear-cut: either the master_np argument is redundant
>>>>> with dev->of_node, or dev->of_node is NULL and master_np is the relevant
>>>>> parent bus. Let's ratify that behaviour, then teach the whole
>>>>> of_dma_configure() pipeline to cope with both cases properly.
>>>>>
>>>>> Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
>>
>> [...]
>>
>>>>
>>>> pci and memory mapped device world is different.
>>
>> ???
>>
>> No they aren't. There is nothing magic about PCI. PCI *is* a
>> memory-mapped bus.
>>
>> The only PCI-specific aspect here is the Linux code path which passes a
>> host controller node into of_dma_configure() where the latter expects a
>> node for the actual endpoint device. It managed to work for
>> "dma-coherent", because that may appear either directly on a device node
>> or on any of its parent buses, but "dma-ranges" is *only* valid for DT
>> nodes representing buses, thus reveals that using a parent bus to stand
>> in for a device isn't actually correct. I only posted that horrible hack
>> patch to prove the point that having a child node to represent the
>> actual device is indeed sufficient to make of_dma_configure() work
>> correctly for PCI masters as-is (modulo the other issues).
>>
>>> of course if you talk
>>>> from iommu perspective, all the master are same for IOMMU
>>
>> I don't understand what you mean by that. There's nothing about IOMMUs
>> here, it's purely about parsing DT properties correctly.
>>
>>>> but the original intention of the patch is to try to solve 2 problems.
>>>> please refer to https://lkml.org/lkml/2017/3/29/10
>>
>> One patch should not solve two separate problems anyway. Taking a step
>> back, there are at least 3 things that this discussion has brought up:
>>
>> 1) The way in which we call of_dma_configure() for PCI devices causes
>> the "dma-ranges" property on PCI host controllers to be ignored.
>>
>> 2) of_dma_get_range() only considers the first entry in any "dma-ranges"
>> property.
>>
>> 3) When of_dma_configure() does set a DMA mask, there is nothing on
>> arm64 and other architectures to prevent drivers overriding that with a
>> wider mask later.
>>
>> Those are 3 separate problems, to solve with 3 or more separate patches,
>> and I have deliberately put the second and third to one side for the
>> moment. This patch fixes problem 1.
>>
>>>> 1) expose generic API for pci world clients to configure their
>>>> dma-ranges. right now there is none.
>>>> 2) same API can be used by IOMMU to derive dma_mask.
>>>>
>>>> while the current patch posted to handle dma-ranges for both memory
>>>> mapped and pci devices, which I think is overdoing.
>>
>> No, of_dma_configure() handles the "dma-ranges" property as it is
>> defined in the DT spec to describe the mapping between a child bus
>> address space and a parent bus address space. Whether those
>> memory-mapped parent and child buses are PCI, ISA, AMBA, HyperTransport,
>> or anything else is irrelevant other than for the encoding of the
>> address specifiers. All this patch does is sort out the cases where we
>> have a real device node to start at, from the cases where we don't and
>> so start directly at the device's parent bus node instead.
>>
>>>> besides we have different configuration of dma-ranges based on iommu
>>>> is enabled or not enabled.
>>
>> That doesn't sound right, unless you mean the firmware actually programs
>> the host controller's AXI bridge differently for system configurations
>> where the IOMMU is expected to be used or not? (and even then, I don't
>> really see why it would be necessary to do that...)
>>
>>>>  #define PCIE_DMA_RANGES dma-ranges = <0x43000000 0x00 0x80000000 0x00
>>>> 0x80000000 0x00 0x80000000 \
>>>>                                       0x43000000 0x08 0x00000000 0x08
>>>> 0x00000000 0x08 0x00000000 \
>>>>                                       0x43000000 0x80 0x00000000 0x80
>>>> 0x00000000 0x40 0x00000000>;
>>>> Not sure if this patch will consider above dma-ranges.
>>>>
>>>> my suggestion is to leave existing of_dma_get_range as is, and have
>>>> new function for pci world as discussed in
>>>> please refer to https://lkml.org/lkml/2017/3/29/10
>>
>> And then we keep adding new functions to do the exact same thing for
>> every other discoverable bus type whose bridge is be described in DT? I
>> fail to see how that is in any way better than simply fixing the
>> existing code to work as it was intended to.
>>
>> of_dma_get_ranges() uses of_translate_dma_address() just the same way as
>> existing PowerPC PCI code does, which further disproves your assertion
>> that parsing PCI addresses is somehow special - it's really only a
>> matter of getting the right number of address cells in order to to read
>> a child address to give to of_translate_dma_address() in the first
>> place. Incidentally, I now notice that the proposed
>> of_pci_get_dma_ranges() is incomplete as it doesn't use
>> of_translate_dma_address() or otherwise traverse upwards through the
>> dma-ranges of any further parent buses.
>>
>>>>
>>>> Regards,
>>>> Oza.
>>>
>>> also I see that, in case of multiple ranges of_dma_get_range doesnt handle that.
>>> and also it is not meant to handle.
>>
>> Yes, the existing code doesn't handle multiple dma-ranges entries,
>> because nobody's had the need to implement that so far, and this patch
>> does not change that because it's fixing a separate problem.
>>
>> Now, of course of_dma_get_range() *should* be capable of handling
>> multiple entries regardless of this patch, and I'm going to write *that*
>> patch right now (it's going to be a case of adding a handful of lines
>> which probably won't even conflict with this one at all). If we had a
>> bunch of different range parsing functions, we'd then have to duplicate
>> the equivalent logic across all of them, which is clearly undesirable
>> when it can easily be avoided altogether.
>>
>> Robin.
>>
>>> so with this patch will return wrong size and hence wrong dma_mask.
>>> having said, I think it is better to separate pci world dma-ranges
>>> function on of_pci.c
>>>
>>> for which my discussion with Rob already, (same thread)
>>> https://lkml.org/lkml/2017/3/29/10
>>> Waiting for Rob's viewpoint on this.
>>>
>>>
>>> Regards,
>>> Oza.
>>>
>>
>
> In my opinion NAKing to this, because
>
> 1) some reasons already mentioned in https://lkml.org/lkml/2017/3/29/10
>
> 2) also of_dma_get_range is supposed to handle traditional dma-ranges
> (not pci one)
>
> 3) we need separate function for pci users such as iproc or rcar SOCs
> to have their dma-ranges parsed,
> which can be extended later for e.g. pci flags have some meanings.
>
> besides of_dma_configure is written to pass only single out parameter
> (..., *dma_addr, *size)
> handling multiple ranges here, and passing only one range out is not desirable.
>
> also you would not like to handle pci flags (the first portion of DT
> entry) in this function if required in future.
>
> this new function will be similar to of_pci_get_host_bridge_resources
> https://lkml.org/lkml/2017/3/29/10
> which I am writing/improving right now..
>
>
> Regards,
> Oza.


Hi Robin,

Gentle request to have a look at following approach and patch.

[RFC PATCH 2/2] of/pci: call pci specific dma-ranges instead of memory-mapped.
[RFC PATCH 1/2] of/pci: implement inbound dma-ranges for PCI

I have tested this on our platform, with and without iommu, and seems to work.

of course it requires your "in discussion" iommu dma_mask" changes to work.
which I believe you will take it ahead. so I have removed all the
iommu related changes now.
and this addresses purely pci world now.

let me know your view on this.

Regards,
Oza.

^ permalink raw reply

* Re: [PATCH V1 1/1] mtd: mtk-nor: set controller to 4B mode with large capacity flash
From: Marek Vasut @ 2017-03-30 10:00 UTC (permalink / raw)
  To: Guochun Mao, Boris Brezillon
  Cc: David Woodhouse, Richard Weinberger, Cyrille Pitchen, Rob Herring,
	Mark Rutland, Matthias Brugger, Russell King, linux-mtd,
	devicetree, linux-arm-kernel, linux-mediatek, linux-kernel
In-Reply-To: <1490862222-723-2-git-send-email-guochun.mao@mediatek.com>

On 03/30/2017 10:23 AM, Guochun Mao wrote:
> when nor's size larger than 16MByte, nor and controller should
> enter 4Byte mode simultaneously.
> 
> Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
> ---
>  drivers/mtd/spi-nor/mtk-quadspi.c |    7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/mtk-quadspi.c b/drivers/mtd/spi-nor/mtk-quadspi.c
> index e661877..05cd8a8 100644
> --- a/drivers/mtd/spi-nor/mtk-quadspi.c
> +++ b/drivers/mtd/spi-nor/mtk-quadspi.c
> @@ -369,6 +369,13 @@ static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
>  		/* We only handle 1 byte */
>  		ret = mt8173_nor_wr_sr(mt8173_nor, *buf);
>  		break;
> +	case SPINOR_OP_EN4B:
> +		/* Set nor controller to 4-byte address mode,
> +		 * and simultaneously set nor flash.
> +		 * This case should cooperate with default operation.
> +		 */
> +		writeb(readb(mt8173_nor->base + MTK_NOR_DUAL_REG) | 0x10,
> +				mt8173_nor->base + MTK_NOR_DUAL_REG);

And what happens on READ then ? Who clears that bit when protocol
changes ? You probably want something like cqspi_set_protocol()
instead, which is invoked from {read,write}{,_reg}() and erase().

>  	default:
>  		ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0);
>  		if (ret)
> 


-- 
Best regards,
Marek Vasut

^ permalink raw reply

* [RFC PATCH 2/2] of/pci: call pci specific dma-ranges instead of memory-mapped.
From: Oza Pawandeep via iommu @ 2017-03-30  9:59 UTC (permalink / raw)
  To: Joerg Roedel, Robin Murphy
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Oza Pawandeep,
	linux-pci-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
	bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1490867986-5675-1-git-send-email-oza.oza-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>

it is possible that PCI device supports 64-bit DMA addressing,
and thus it's driver sets device's dma_mask to DMA_BIT_MASK(64),
however PCI host bridge may have limitations on the inbound
transaction addressing. As an example, consider NVME SSD device
connected to iproc-PCIe controller.

Currently, the IOMMU DMA ops only considers PCI device dma_mask
when allocating an IOVA. This is particularly problematic on
ARM/ARM64 SOCs where the IOMMU (i.e. SMMU) translates IOVA to
PA for in-bound transactions only after PCI Host has forwarded
these transactions on SOC IO bus. This means on such ARM/ARM64
SOCs the IOVA of in-bound transactions has to honor the addressing
restrictions of the PCI Host.

this patch calls pci specific of_pci_dma_get_ranges, instead of
calling memory-mapped one, which returns wrong size and also
not meant for PCI world.

with this, it gets accurate resources back, and largest possible
inbound window size. with that largest possible dma_mask can be
generated.

Signed-off-by: Oza Pawandeep <oza.oza-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>

diff --git a/drivers/of/device.c b/drivers/of/device.c
index b1e6beb..d6a8dde 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -9,6 +9,7 @@
 #include <linux/module.h>
 #include <linux/mod_devicetable.h>
 #include <linux/slab.h>
+#include <linux/of_pci.h>
 
 #include <asm/errno.h>
 #include "of_private.h"
@@ -89,6 +90,8 @@ void of_dma_configure(struct device *dev, struct device_node *np)
 	bool coherent;
 	unsigned long offset;
 	const struct iommu_ops *iommu;
+	struct resource_entry *window;
+	LIST_HEAD(res);
 
 	/*
 	 * Set default coherent_dma_mask to 32 bit.  Drivers are expected to
@@ -104,7 +107,24 @@ void of_dma_configure(struct device *dev, struct device_node *np)
 	if (!dev->dma_mask)
 		dev->dma_mask = &dev->coherent_dma_mask;
 
-	ret = of_dma_get_range(np, &dma_addr, &paddr, &size);
+	if (dev_is_pci(dev)) {
+		size = 0;
+		ret = of_pci_get_dma_ranges(np, &res);
+		if (!ret) {
+			resource_list_for_each_entry(window, &res) {
+				struct resource *res_dma = window->res;
+				if (size < resource_size(res_dma)) {
+					dma_addr = res_dma->start - window->offset;
+					paddr = res_dma->start;
+					size = resource_size(res_dma);
+				}
+			}
+		}
+		pci_free_resource_list(&res);
+	}
+	else
+		ret = of_dma_get_range(np, &dma_addr, &paddr, &size);
+
 	if (ret < 0) {
 		dma_addr = offset = 0;
 		size = dev->coherent_dma_mask + 1;
-- 
1.9.1

^ permalink raw reply related

* [RFC PATCH 1/2] of/pci: implement inbound dma-ranges for PCI
From: Oza Pawandeep via iommu @ 2017-03-30  9:59 UTC (permalink / raw)
  To: Joerg Roedel, Robin Murphy
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Oza Pawandeep,
	linux-pci-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
	bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

current device frmework and of framework integration assumes dma-ranges
in a way where memory-mapped devices define their dma-ranges.
dma-ranges: (child-bus-address, parent-bus-address, length).

but iproc based SOCs and other SOCs(rcar) have PCI world dma-ranges.
dma-ranges = <0x43000000 0x00 0x00 0x00 0x00 0x80 0x00>;

of_dma_configure is specifically witten to take care of memory mapped devices.
but no implementation exists for pci to take care of pcie based memory ranges.
in fact pci world doesnt seem to define standard dma-ranges

this exposes intrface not only to the pci host driver, but also
it aims to provide an interface to callers such as of_dma_configure.
so then the returned size get best possible (largest) dma_mask.
for e.g.
dma-ranges = <0x43000000 0x00 0x00 0x00 0x00 0x80 0x00>;
we should get dev->coherent_dma_mask=0x7fffffffff.

also this patch intends to handle multiple inbound windows and dma-ranges.
it is left to the caller, how it wants to use them.

Signed-off-by: Oza Pawandeep <oza.oza-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>

diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 0ee42c3..5299438 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -283,6 +283,80 @@ int of_pci_get_host_bridge_resources(struct device_node *dev,
 	return err;
 }
 EXPORT_SYMBOL_GPL(of_pci_get_host_bridge_resources);
+
+/**
+ * of_pci_get_dma_ranges - Parse PCI host bridge inbound resources from DT
+ * @np: device node of the host bridge having the dma-ranges property
+ * @resources: list where the range of resources will be added after DT parsing
+ *
+ * It is the caller's job to free the @resources list.
+ *
+ * This function will parse the "dma-ranges" property of a PCI host bridge device
+ * node and setup the resource mapping based on its content.
+ *
+ * It returns zero if the range parsing has been successful or a standard error
+ * value if it failed.
+ */
+
+int of_pci_get_dma_ranges(struct device_node *np, struct list_head *resources)
+{
+	struct device_node *node = of_node_get(np);
+	int rlen;
+	int ret = 0;
+	const int na = 3, ns = 2;
+	struct resource *res;
+	struct of_pci_range_parser parser;
+	struct of_pci_range range;
+
+	if (!node)
+		return -EINVAL;
+
+	parser.node = node;
+	parser.pna = of_n_addr_cells(node);
+	parser.np = parser.pna + na + ns;
+
+	parser.range = of_get_property(node, "dma-ranges", &rlen);
+
+	if (!parser.range) {
+		pr_debug("pcie device has no dma-ranges defined for node(%s)\n", np->full_name);
+		ret = -ENODEV;
+		goto out;
+	}
+
+	parser.end = parser.range + rlen / sizeof(__be32);
+
+	for_each_of_pci_range(&parser, &range) {
+		/*
+		 * If we failed translation or got a zero-sized region
+		 * then skip this range
+		 */
+		if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
+			continue;
+
+		res = kzalloc(sizeof(struct resource), GFP_KERNEL);
+		if (!res) {
+			ret = -ENOMEM;
+			goto parse_failed;
+		}
+
+		ret = of_pci_range_to_resource(&range, np, res);
+		if (ret) {
+			kfree(res);
+			continue;
+		}
+
+		pci_add_resource_offset(resources, res,	res->start - range.pci_addr);
+        }
+
+	return ret;
+
+parse_failed:
+	pci_free_resource_list(resources);
+out:
+	of_node_put(node);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(of_pci_get_dma_ranges);
 #endif /* CONFIG_OF_ADDRESS */
 
 #ifdef CONFIG_PCI_MSI
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index 0e0974e..8509e3d 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -76,6 +76,7 @@ static inline void of_pci_check_probe_only(void) { }
 int of_pci_get_host_bridge_resources(struct device_node *dev,
 			unsigned char busno, unsigned char bus_max,
 			struct list_head *resources, resource_size_t *io_base);
+int of_pci_get_dma_ranges(struct device_node *np, struct list_head *resources);
 #else
 static inline int of_pci_get_host_bridge_resources(struct device_node *dev,
 			unsigned char busno, unsigned char bus_max,
@@ -83,6 +84,11 @@ static inline int of_pci_get_host_bridge_resources(struct device_node *dev,
 {
 	return -EINVAL;
 }
+
+static inline int of_pci_get_dma_ranges(struct device_node *np, struct list_head *resources)
+{
+	return -EINVAL;
+}
 #endif
 
 #if defined(CONFIG_OF) && defined(CONFIG_PCI_MSI)
-- 
1.9.1

^ permalink raw reply related

* [PATCH 2/2] ARM: dts: cros-ec-keyboard: Enable as wakeup source
From: Jeffy Chen @ 2017-03-30  9:50 UTC (permalink / raw)
  To: linux-kernel
  Cc: briannorris, dmitry.torokhov, dbasehore, dianders, Jeffy Chen,
	devicetree, Rob Herring, Mark Rutland, Russell King,
	linux-arm-kernel
In-Reply-To: <1490867450-31765-1-git-send-email-jeffy.chen@rock-chips.com>

Enable cros-ec-keyboard as a wakeup source.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
---

 arch/arm/boot/dts/cros-ec-keyboard.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/cros-ec-keyboard.dtsi b/arch/arm/boot/dts/cros-ec-keyboard.dtsi
index c0451051..3168a5e 100644
--- a/arch/arm/boot/dts/cros-ec-keyboard.dtsi
+++ b/arch/arm/boot/dts/cros-ec-keyboard.dtsi
@@ -16,6 +16,7 @@
 		keypad,num-rows = <8>;
 		keypad,num-columns = <13>;
 		google,needs-ghost-filter;
+		wakeup-source;
 
 		linux,keymap = <
 			MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
-- 
2.1.4

^ permalink raw reply related

* [PATCH 0/2] This patches set cros_ec_keyb as a wakeup source, so the chromeos's powerd
From: Jeffy Chen @ 2017-03-30  9:50 UTC (permalink / raw)
  To: linux-kernel-u79uwXL29TY76Z2rM5mHXA
  Cc: briannorris-F7+t8E8rja9g9hUCZPvPmw,
	dmitry.torokhov-Re5JQEeQqe8AvxtiuMwx3w,
	dbasehore-hpIqsD4AKlfQT0dZR+AlfA, dianders-F7+t8E8rja9g9hUCZPvPmw,
	Jeffy Chen, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	Gwendal Grignou, Vic Yang, Enric Balletbo Serra,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Lee Jones, Rob Herring,
	Mark Rutland, linux-input-u79uwXL29TY76Z2rM5mHXA, Russell King

can control the keyboard's wakeup ability along with other ec event sources.


Jeffy Chen (2):
  input: cros_ec_keyb: Report wakeup events
  ARM: dts: cros-ec-keyboard: Enable as wakeup source

 arch/arm/boot/dts/cros-ec-keyboard.dtsi | 1 +
 drivers/input/keyboard/cros_ec_keyb.c   | 9 +++++++++
 2 files changed, 10 insertions(+)

-- 
2.1.4


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^ permalink raw reply

* Re: [PATCH 1/2] drm/bridge: ti-tfp410: support hpd via gpio
From: Archit Taneja @ 2017-03-30  9:49 UTC (permalink / raw)
  To: Jyri Sarha, Christopher Spinrath
  Cc: Mark Rutland, devicetree@vger.kernel.org, Shawn Guo,
	Russell King - ARM Linux, DRI mailing list, robh+dt@kernel.org,
	Igor Grinberg, Sascha Hauer, Fabio Estevam,
	linux-arm-kernel@lists.infradead.org
In-Reply-To: <f87195b3-bd89-d698-c935-4e3aa97c01e2@ti.com>



On 03/28/2017 07:02 PM, Jyri Sarha wrote:
> On 03/27/17 08:58, Archit Taneja wrote:
>> Hi,
>>
>> On 03/07/2017 03:21 AM, Christopher Spinrath wrote:
>>> Hi Fabio,
>>>
>>> On 03/06/2017 10:46 PM, Fabio Estevam wrote:
>>>> Hi Christopher,
>>>>
>>>> On Mon, Mar 6, 2017 at 6:40 PM,
>>>> <christopher.spinrath@rwth-aachen.de> wrote:
>>>>> From: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
>>>>>
>>>>> On some boards the hpd pin of a hdmi connector is wired up to a gpio
>>>>> pin. Since in the DRM world the tfp410 driver is responsible for
>>>>> handling the connector, add support for hpd gpios in this very driver.
>>>>>
>>>>> Signed-off-by: Christopher Spinrath
>>>>> <christopher.spinrath@rwth-aachen.de>
>>>>> ---
>>>>>  drivers/gpu/drm/bridge/ti-tfp410.c | 72
>>>>> ++++++++++++++++++++++++++++++++++++--
>>>>
> ...
>>>
>>
>> The patch looks good to me.
>>
>> Jyri,
>>
>> Is it possible for you to verify this on Beaglebone platform?
>>
>
> If I read my BeagleBone DVI-D Cape docs right, it does not have the HPD
> pin connected. At least it does not mention any gpio that could be used
> for the purpose. So I can not easily test this patch in real world
> situation. For what it is worth the patch looks ok to me too.

Thanks for the review. I looked at the tfp410 data sheet[1], there isn't
a HPD pin on the chip at all. My guess is that boards using tfp410 most
likely have the HPD pin routed to the SoC from the HDMI connector
(with a level shifter/shield in between).

We would eventually need to move the both ddc and hpd stuff to
a generic hdmi connector driver later on. I've queued this to
drm-misc-next.

[1]: http://www.ti.com/lit/ds/symlink/tfp410.pdf

Archit

>
> Best regards,
> Jyri
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

-- 
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a Linux Foundation Collaborative Project
_______________________________________________
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^ permalink raw reply

* Re: [PATCHv5 11/11] arm: sti: update sti-cec for CEC notifier support
From: Hans Verkuil @ 2017-03-30  9:32 UTC (permalink / raw)
  To: Patrice CHOTARD, Benjamin Gaignard, Hans Verkuil
  Cc: linux-media@vger.kernel.org, Daniel Vetter, Russell King,
	dri-devel@lists.freedesktop.org,
	moderated list:ARM/S5P EXYNOS AR..., Krzysztof Kozlowski,
	Inki Dae, Marek Szyprowski, Javier Martinez Canillas,
	Hans Verkuil, devicetree@vger.kernel.org
In-Reply-To: <c29adefb-13e6-e723-eb96-3b0049b39ddd@st.com>

On 03/30/2017 11:30 AM, Patrice CHOTARD wrote:
> Hi Benjamin
> 
> On 03/30/2017 09:41 AM, Benjamin Gaignard wrote:
>> + Patrice for sti DT
> 
> In order to be coherent with all previous STi DT patches,
> 
> can you update the commit message with "ARM: dts: STiH410: update 
> sti-cec for CEC notifier support"

Done.

Regards,

	Hans

> 
> Thanks
> 
> Patrice
> 
>>
>> 2017-03-29 16:15 GMT+02:00 Hans Verkuil <hverkuil@xs4all.nl>:
>>> From: Benjamin Gaignard <benjamin.gaignard@linaro.org>
>>>
>>> To use CEC notifier sti CEC driver needs to get phandle
>>> of the hdmi device.
>>>
>>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
>>> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
>>> CC: devicetree@vger.kernel.org
>>> ---
>>>  arch/arm/boot/dts/stih407-family.dtsi | 12 ------------
>>>  arch/arm/boot/dts/stih410.dtsi        | 13 +++++++++++++
>>>  2 files changed, 13 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
>>> index d753ac36788f..044184580326 100644
>>> --- a/arch/arm/boot/dts/stih407-family.dtsi
>>> +++ b/arch/arm/boot/dts/stih407-family.dtsi
>>> @@ -742,18 +742,6 @@
>>>                                  <&clk_s_c0_flexgen CLK_ETH_PHY>;
>>>                 };
>>>
>>> -               cec: sti-cec@094a087c {
>>> -                       compatible = "st,stih-cec";
>>> -                       reg = <0x94a087c 0x64>;
>>> -                       clocks = <&clk_sysin>;
>>> -                       clock-names = "cec-clk";
>>> -                       interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
>>> -                       interrupt-names = "cec-irq";
>>> -                       pinctrl-names = "default";
>>> -                       pinctrl-0 = <&pinctrl_cec0_default>;
>>> -                       resets = <&softreset STIH407_LPM_SOFTRESET>;
>>> -               };
>>> -
>>>                 rng10: rng@08a89000 {
>>>                         compatible      = "st,rng";
>>>                         reg             = <0x08a89000 0x1000>;
>>> diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
>>> index 3c9672c5b09f..21fe72b183d8 100644
>>> --- a/arch/arm/boot/dts/stih410.dtsi
>>> +++ b/arch/arm/boot/dts/stih410.dtsi
>>> @@ -281,5 +281,18 @@
>>>                                  <&clk_s_c0_flexgen CLK_ST231_DMU>,
>>>                                  <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
>>>                 };
>>> +
>>> +               sti-cec@094a087c {
>>> +                       compatible = "st,stih-cec";
>>> +                       reg = <0x94a087c 0x64>;
>>> +                       clocks = <&clk_sysin>;
>>> +                       clock-names = "cec-clk";
>>> +                       interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
>>> +                       interrupt-names = "cec-irq";
>>> +                       pinctrl-names = "default";
>>> +                       pinctrl-0 = <&pinctrl_cec0_default>;
>>> +                       resets = <&softreset STIH407_LPM_SOFTRESET>;
>>> +                       hdmi-phandle = <&sti_hdmi>;
>>> +               };
>>>         };
>>>  };
>>> --
>>> 2.11.0
>>>
>>
>>
>>
> 

^ permalink raw reply

* Re: [PATCHv5 11/11] arm: sti: update sti-cec for CEC notifier support
From: Patrice CHOTARD @ 2017-03-30  9:30 UTC (permalink / raw)
  To: Benjamin Gaignard, Hans Verkuil
  Cc: linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Daniel Vetter, Russell King,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	moderated list:ARM/S5P EXYNOS AR..., Krzysztof Kozlowski,
	Inki Dae, Marek Szyprowski, Javier Martinez Canillas,
	Hans Verkuil, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CA+M3ks442wftNR8+dctdSkKMCPSw9Rd2CH5UG-VEP7XySGjCjw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

Hi Benjamin

On 03/30/2017 09:41 AM, Benjamin Gaignard wrote:
> + Patrice for sti DT

In order to be coherent with all previous STi DT patches,

can you update the commit message with "ARM: dts: STiH410: update 
sti-cec for CEC notifier support"

Thanks

Patrice

>
> 2017-03-29 16:15 GMT+02:00 Hans Verkuil <hverkuil@xs4all.nl>:
>> From: Benjamin Gaignard <benjamin.gaignard@linaro.org>
>>
>> To use CEC notifier sti CEC driver needs to get phandle
>> of the hdmi device.
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
>> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
>> CC: devicetree@vger.kernel.org
>> ---
>>  arch/arm/boot/dts/stih407-family.dtsi | 12 ------------
>>  arch/arm/boot/dts/stih410.dtsi        | 13 +++++++++++++
>>  2 files changed, 13 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
>> index d753ac36788f..044184580326 100644
>> --- a/arch/arm/boot/dts/stih407-family.dtsi
>> +++ b/arch/arm/boot/dts/stih407-family.dtsi
>> @@ -742,18 +742,6 @@
>>                                  <&clk_s_c0_flexgen CLK_ETH_PHY>;
>>                 };
>>
>> -               cec: sti-cec@094a087c {
>> -                       compatible = "st,stih-cec";
>> -                       reg = <0x94a087c 0x64>;
>> -                       clocks = <&clk_sysin>;
>> -                       clock-names = "cec-clk";
>> -                       interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
>> -                       interrupt-names = "cec-irq";
>> -                       pinctrl-names = "default";
>> -                       pinctrl-0 = <&pinctrl_cec0_default>;
>> -                       resets = <&softreset STIH407_LPM_SOFTRESET>;
>> -               };
>> -
>>                 rng10: rng@08a89000 {
>>                         compatible      = "st,rng";
>>                         reg             = <0x08a89000 0x1000>;
>> diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
>> index 3c9672c5b09f..21fe72b183d8 100644
>> --- a/arch/arm/boot/dts/stih410.dtsi
>> +++ b/arch/arm/boot/dts/stih410.dtsi
>> @@ -281,5 +281,18 @@
>>                                  <&clk_s_c0_flexgen CLK_ST231_DMU>,
>>                                  <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
>>                 };
>> +
>> +               sti-cec@094a087c {
>> +                       compatible = "st,stih-cec";
>> +                       reg = <0x94a087c 0x64>;
>> +                       clocks = <&clk_sysin>;
>> +                       clock-names = "cec-clk";
>> +                       interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
>> +                       interrupt-names = "cec-irq";
>> +                       pinctrl-names = "default";
>> +                       pinctrl-0 = <&pinctrl_cec0_default>;
>> +                       resets = <&softreset STIH407_LPM_SOFTRESET>;
>> +                       hdmi-phandle = <&sti_hdmi>;
>> +               };
>>         };
>>  };
>> --
>> 2.11.0
>>
>
>
>

^ permalink raw reply

* [PATCH v2] arm64: tegra: Add GPU node for Tegra 186
From: Alexandre Courbot @ 2017-03-30  9:28 UTC (permalink / raw)
  To: Thierry Reding, Jonathan Hunter, Rob Herring, Mark Rutland
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA, gnurou-Re5JQEeQqe8AvxtiuMwx3w,
	Alexandre Courbot
In-Reply-To: <20170330091831.18322-2-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Add the DT node for the GP10B GPU on Tegra 186.

Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index b4c71b519289..9ee6c439fb02 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -660,6 +660,24 @@
 		};
 	};
 
+	gpu@17000000 {
+		compatible = "nvidia,gp10b";
+		reg = <0x0 0x17000000 0x0 0x1000000>,
+		      <0x0 0x18000000 0x0 0x1000000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "stall", "nonstall";
+
+		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
+			 <&bpmp TEGRA186_CLK_GPU>;
+		clock-names = "gpu", "pwr";
+		resets = <&bpmp TEGRA186_RESET_GPU>;
+		reset-names = "gpu";
+		status = "disabled";
+
+		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
+	};
+
 	sysram@30000000 {
 		compatible = "nvidia,tegra186-sysram", "mmio-sram";
 		reg = <0x0 0x30000000 0x0 0x50000>;
-- 
2.12.0

^ permalink raw reply related

* [PATCH v2] dt-bindings: Add documentation for GP10B GPU
From: Alexandre Courbot @ 2017-03-30  9:26 UTC (permalink / raw)
  To: Thierry Reding, Jonathan Hunter, Rob Herring, Mark Rutland
  Cc: devicetree, linux-kernel, linux-arm-kernel, linux-tegra, gnurou,
	Alexandre Courbot
In-Reply-To: <20170330091831.18322-2-acourbot@nvidia.com>

GP10B's definition is mostly similar to GK20A's and GM20B's. The only
noticeable difference is the use of power domains instead of a regulator
for power supply.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
Changes since v1:
- It's much better when it compiles.

 .../devicetree/bindings/gpu/nvidia,gk20a.txt       | 25 +++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
index ff3db65e50de..b7e4c7444510 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
@@ -5,6 +5,7 @@ Required properties:
   Currently recognized values:
   - nvidia,gk20a
   - nvidia,gm20b
+  - nvidia,gp10b
 - reg: Physical base address and length of the controller's registers.
   Must contain two entries:
   - first entry for bar0
@@ -14,7 +15,8 @@ Required properties:
 - interrupt-names: Must include the following entries:
   - stall
   - nonstall
-- vdd-supply: regulator for supply voltage.
+- vdd-supply: regulator for supply voltage. Only required for GPUs not using
+  power domains.
 - clocks: Must contain an entry for each entry in clock-names.
   See ../clocks/clock-bindings.txt for details.
 - clock-names: Must include the following entries:
@@ -27,6 +29,8 @@ is also required:
   See ../reset/reset.txt for details.
 - reset-names: Must include the following entries:
   - gpu
+- power-domains: GPUs that make use of power domains can define this property
+  instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
 
 Optional properties:
 - iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
@@ -68,3 +72,22 @@ Example for GM20B:
 		iommus = <&mc TEGRA_SWGROUP_GPU>;
 		status = "disabled";
 	};
+
+Example for GP10B:
+
+	gpu@17000000 {
+		compatible = "nvidia,gp10b";
+		reg = <0x0 0x17000000 0x0 0x1000000>,
+		      <0x0 0x18000000 0x0 0x1000000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "stall", "nonstall";
+		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
+			 <&bpmp TEGRA186_CLK_GPU>;
+		clock-names = "gpu", "pwr";
+		resets = <&bpmp TEGRA186_RESET_GPU>;
+		reset-names = "gpu";
+		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
+		iommus = <&smmu TEGRA186_SID_GPU>;
+		status = "disabled";
+	};
-- 
2.12.0

^ permalink raw reply related

* Re: [PATCH v7 0/7] Implement clocksource for rockchip SoC using rockchip timer
From: Daniel Lezcano @ 2017-03-30  9:26 UTC (permalink / raw)
  To: Alexander Kochetkov, Heiko Stuebner,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
  Cc: Thomas Gleixner, Mark Rutland, Rob Herring, Russell King,
	Caesar Wang, Huang Tao
In-Reply-To: <DAFDD95C-3244-4217-B3A4-E9FB176AE989-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

On 29/03/2017 15:22, Alexander Kochetkov wrote:
> Hello, Daniel.

Hi Alexander,

> Due to recent comments from Mark[1], may be is better to apply v6[2] series instead of v7[3]?
> Because my main goal was to fix wall time on rk3188. And I did it the same way how that was
> already done for other timer drivers (one of possible solution).
> 
> You can rename CLOCKSOURCE_OF to TIMER_OF later. I can help with that, but I don’t
> think it is good idea to combine my changes and timer framework cleanups/improvements
> into single series.
> 
> And I thinks, that probably is is better to drop [3] and [4] and revert 0c8893c9095d ("clockevents: Add a
> clkevt-of mechanism like clksrc-of»).
> 
> What do you think?

I share your opinion.

  -- Daniel


> [1] https://lkml.org/lkml/2017/3/29/286
> [2] https://lkml.org/lkml/2017/1/31/401
> [3] https://lkml.org/lkml/2017/3/22/508
> [4] https://lkml.org/lkml/2017/3/22/420
> [5] https://lkml.org/lkml/2017/3/22/426
> 
>> 22 марта 2017 г., в 18:48, Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> написал(а):
>>
>> Hello, Daniel, Heiko.
>>
>> Here is try 7 :) Could you please take a look into it?
>>
>> rockchip_timer init code implemented using CLOCKEVENT_OF_DECLARE()
>> introduced in commit 0c8893c9095d ("clockevents: Add a clkevt-of
>> mechanism like clksrc-of")
>>
>> There is change in the arch/arm/mach-rockchip/rockchip.c.
>>
>> This series should be applied after the commit:
>> https://lkml.org/lkml/2017/3/22/426
>>
>> As without the commit, you will get linker error ("clkevt-probe.c:63:
>> undefined reference to `__clkevt_of_table’")
>>
>> Regards,
>> Alexander.
>>
>>
>> Alexander Kochetkov (6):
>>  dt-bindings: clarify compatible property for rockchip timers
>>  ARM: dts: rockchip: update compatible property for rk322x timer
>>  ARM: dts: rockchip: add clockevent attribute to rockchip timers
>>  clocksource/drivers/rockchip_timer: implement clocksource timer
>>  ARM: dts: rockchip: add timer entries to rk3188 SoC
>>  ARM: dts: rockchip: disable arm-global-timer for rk3188
>>
>> Daniel Lezcano (1):
>>  clocksource/drivers/clksrc-evt-probe: Describe with the DT both the
>>    clocksource and the clockevent
>>
>> .../bindings/timer/rockchip,rk-timer.txt           |   12 +-
>> Documentation/devicetree/bindings/timer/timer.txt  |   38 ++++
>> arch/arm/boot/dts/rk3036.dtsi                      |    1 +
>> arch/arm/boot/dts/rk3188.dtsi                      |   19 ++
>> arch/arm/boot/dts/rk322x.dtsi                      |    3 +-
>> arch/arm/boot/dts/rk3288.dtsi                      |    1 +
>> arch/arm/mach-rockchip/rockchip.c                  |    2 +
>> arch/arm64/boot/dts/rockchip/rk3368.dtsi           |    1 +
>> drivers/clocksource/Kconfig                        |    2 +
>> drivers/clocksource/clkevt-probe.c                 |    7 +
>> drivers/clocksource/clksrc-probe.c                 |    7 +
>> drivers/clocksource/rockchip_timer.c               |  215 ++++++++++++++------
>> 12 files changed, 241 insertions(+), 67 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/timer/timer.txt
>>
>> -- 
>> 1.7.9.5
>>
> 


-- 
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^ permalink raw reply

* [PATCH 2/2] arm64: tegra: Add GPU node for Tegra 186
From: Alexandre Courbot @ 2017-03-30  9:18 UTC (permalink / raw)
  To: Thierry Reding, Jonathan Hunter, Rob Herring, Mark Rutland
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA, gnurou-Re5JQEeQqe8AvxtiuMwx3w,
	Alexandre Courbot
In-Reply-To: <20170330091831.18322-1-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Add the DT node for the GP10B GPU on Tegra 186.

Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index b4c71b519289..7ada0c5b0581 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -660,6 +660,24 @@
 		};
 	};
 
+	gpu@17000000 {
+		compatible = "nvidia,gp10b";
+		reg = <0x0 0x17000000 0x0 0x1000000>
+		      <0x0 0x18000000 0x0 0x1000000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "stall", "nonstall";
+
+		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
+			 <&bpmp TEGRA186_CLK_GPU>;
+		clock-names = "gpu", "pwr";
+		resets = <&bpmp TEGRA186_RESET_GPU>;
+		reset-names = "gpu";
+		status = "disabled";
+
+		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
+	};
+
 	sysram@30000000 {
 		compatible = "nvidia,tegra186-sysram", "mmio-sram";
 		reg = <0x0 0x30000000 0x0 0x50000>;
-- 
2.12.0

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^ permalink raw reply related

* [PATCH 1/2] dt-bindings: Add documentation for GP10B GPU
From: Alexandre Courbot @ 2017-03-30  9:18 UTC (permalink / raw)
  To: Thierry Reding, Jonathan Hunter, Rob Herring, Mark Rutland
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA, gnurou-Re5JQEeQqe8AvxtiuMwx3w,
	Alexandre Courbot

GP10B's definition is mostly similar to GK20A's and GM20B's. The only
noticeable difference is the use of power domains instead of a regulator
for power supply.

Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/gpu/nvidia,gk20a.txt       | 25 +++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
index ff3db65e50de..b7e4c7444510 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
@@ -5,6 +5,7 @@ Required properties:
   Currently recognized values:
   - nvidia,gk20a
   - nvidia,gm20b
+  - nvidia,gp10b
 - reg: Physical base address and length of the controller's registers.
   Must contain two entries:
   - first entry for bar0
@@ -14,7 +15,8 @@ Required properties:
 - interrupt-names: Must include the following entries:
   - stall
   - nonstall
-- vdd-supply: regulator for supply voltage.
+- vdd-supply: regulator for supply voltage. Only required for GPUs not using
+  power domains.
 - clocks: Must contain an entry for each entry in clock-names.
   See ../clocks/clock-bindings.txt for details.
 - clock-names: Must include the following entries:
@@ -27,6 +29,8 @@ is also required:
   See ../reset/reset.txt for details.
 - reset-names: Must include the following entries:
   - gpu
+- power-domains: GPUs that make use of power domains can define this property
+  instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
 
 Optional properties:
 - iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
@@ -68,3 +72,22 @@ Example for GM20B:
 		iommus = <&mc TEGRA_SWGROUP_GPU>;
 		status = "disabled";
 	};
+
+Example for GP10B:
+
+	gpu@17000000 {
+		compatible = "nvidia,gp10b";
+		reg = <0x0 0x17000000 0x0 0x1000000>,
+		      <0x0 0x18000000 0x0 0x1000000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "stall", "nonstall";
+		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
+			 <&bpmp TEGRA186_CLK_GPU>;
+		clock-names = "gpu", "pwr";
+		resets = <&bpmp TEGRA186_RESET_GPU>;
+		reset-names = "gpu";
+		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
+		iommus = <&smmu TEGRA186_SID_GPU>;
+		status = "disabled";
+	};
-- 
2.12.0

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* Re: [PATCH v5 6/9] coresight: add support for CPU debug module
From: Suzuki K Poulose @ 2017-03-30  9:00 UTC (permalink / raw)
  To: Leo Yan, Mike Leach
  Cc: Mark Rutland, devicetree, Sudeep Holla, Guodong Xu,
	Mathieu Poirier, Jonathan Corbet, Catalin Marinas,
	Michael Turquette, linux-doc, Will Deacon, linux-kernel, Wei Xu,
	linux-clk, David Brown, Rob Herring, John Stultz, linux-arm-msm,
	Andy Gross, linux-soc, Stephen Boyd, linux-arm-kernel
In-Reply-To: <20170330010343.GA31843@leoy-linaro>

On 30/03/17 02:03, Leo Yan wrote:
> On Wed, Mar 29, 2017 at 03:56:23PM +0100, Mike Leach wrote:
>
> [...]
>
>>>>> +   /*
>>>>> +    * Unfortunately the CPU cannot be powered up, so return
>>>>> +    * back and later has no permission to access other
>>>>> +    * registers. For this case, should set 'idle_constraint'
>>>>> +    * to ensure CPU power domain is enabled!
>>>>> +    */
>>>>> +   if (!(drvdata->edprsr & EDPRSR_PU)) {
>>>>> +           pr_err("%s: power up request for CPU%d failed\n",
>>>>> +                   __func__, drvdata->cpu);
>>>>> +           goto out;
>>>>> +   }
>>>>> +
>>>>> +out_powered_up:
>>>>> +   debug_os_unlock(drvdata);
>>>>> +
>>>>> +   /*
>>>>> +    * At this point the CPU is powered up, so set the no powerdown
>>>>> +    * request bit so we don't lose power and emulate power down.
>>>>> +    */
>>>>> +   drvdata->edprsr = readl(drvdata->base + EDPRCR);
>>>>> +   drvdata->edprsr |= EDPRCR_COREPURQ | EDPRCR_CORENPDRQ;
>>>>
>>>> If we are here the core is already up.  Shouldn't we need to set
>>>> EDPRCR_CORENPDRQ only?
>>>
>>> Yeah. Will fix.
>>
>> No - EDPRCR_COREPURQ and EDPRCR_CORENPDRQ have different semantics and purposes
>>
>> EDPRCR_COREPURQ is in the debug power domain an is tied to an external
>> debug request that should be an input to the external (to the PE)
>> system power controller.
>> The requirement is that the system power controller powers up the core
>> domain and does not power it down while it remains asserted.
>>
>> EDPRCR_CORENPDRQ is in the core power domain and thus to the specific
>> core only. This ensures that any power control software running on
>> that core should emulate a power down if this is set to one.
>
> I'm curious the exact meaning for "power control software".
>
> Does it mean EDPRCR_CORENPDRQ should be checked by kernel or PSCI
> liked code in ARM trusted firmware to avoid to run CPU power off flow?
>
> Or will EDPRCR_CORENPDRQ assert CPU external signal to notify power
> controller so power controller emulate a power down?
>
>> We cannot know the power control design of the system, so the safe
>> solution is to set both bits.
>
> Thanks a lot for the suggestion. Will set both bits.

Leo,

Also, it would be good to restore the PRCR register back to the original state
after we read the registers (if we changed them). I am exploring ways to make
use of this feature on demand (e.g, tie it to sysrq-t or sysrq-l) and not just
at panic time. So it would be good to have the state restored to not affect the
normal functioning even after dumping the registers.

PS: I have a small hack to hook this into a sysrq-x at runtime, but on a second thought
it is better not to consume the key and rather tie it to something which already exist,
as mentioned above.

Thanks
Suzuki

>
> Thanks,
> Leo Yan
>

^ permalink raw reply

* Re: [PATCH v1 2/8] [media] stm32-dcmi: STM32 DCMI camera interface driver
From: kbuild test robot @ 2017-03-30  8:55 UTC (permalink / raw)
  Cc: Mark Rutland, devicetree, Benjamin Gaignard, Alexandre Torgue,
	linux-kernel, Hans Verkuil, Rob Herring, kbuild-all,
	Maxime Coquelin, Hugues Fruchet, Mauro Carvalho Chehab,
	Yannick Fertre, linux-arm-kernel, linux-media
In-Reply-To: <1490793926-6477-3-git-send-email-hugues.fruchet@st.com>

[-- Attachment #1: Type: text/plain, Size: 2030 bytes --]

Hi Hugues,

[auto build test WARNING on robh/for-next]
[also build test WARNING on v4.11-rc4 next-20170329]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Hugues-Fruchet/Add-support-for-DCMI-camera-interface-of-STMicroelectronics-STM32-SoC-series/20170330-140726
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

Note: it may well be a FALSE warning. FWIW you are at least aware of it now.
http://gcc.gnu.org/wiki/Better_Uninitialized_Warnings

All warnings (new ones prefixed by >>):

   drivers/media/platform/stm32/stm32-dcmi.c: In function 'dcmi_probe':
>> drivers/media/platform/stm32/stm32-dcmi.c:1386:9: warning: 'ret' may be used uninitialized in this function [-Wmaybe-uninitialized]
     return ret;
            ^~~

vim +/ret +1386 drivers/media/platform/stm32/stm32-dcmi.c

  1370		dev_info(&pdev->dev, "Probe done\n");
  1371	
  1372		platform_set_drvdata(pdev, dcmi);
  1373		return 0;
  1374	
  1375	err_reset_control_put:
  1376		reset_control_put(dcmi->rstc);
  1377	err_device_release:
  1378		video_device_release(dcmi->vdev);
  1379	err_device_unregister:
  1380		v4l2_device_unregister(&dcmi->v4l2_dev);
  1381	err_clk_unprepare:
  1382		clk_unprepare(dcmi->mclk);
  1383	err_dma_release:
  1384		dma_release_channel(dcmi->dma_chan);
  1385	
> 1386		return ret;
  1387	}
  1388	
  1389	static int dcmi_remove(struct platform_device *pdev)
  1390	{
  1391		struct stm32_dcmi *dcmi = platform_get_drvdata(pdev);
  1392	
  1393		v4l2_async_notifier_unregister(&dcmi->notifier);
  1394		v4l2_device_unregister(&dcmi->v4l2_dev);

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 58859 bytes --]

[-- Attachment #3: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH v3 7/7] ARM: dts: rskrza1: add rtc DT support
From: Geert Uytterhoeven @ 2017-03-30  8:47 UTC (permalink / raw)
  To: Chris Brandt
  Cc: Alessandro Zummo, Alexandre Belloni, Rob Herring, Mark Rutland,
	Simon Horman, RTCLINUX,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Linux-Renesas
In-Reply-To: <20170329173035.67477-8-chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>

On Wed, Mar 29, 2017 at 7:30 PM, Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org> wrote:
> Enable the realtime clock.
>
> Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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^ permalink raw reply

* Re: [PATCH v3 6/7] ARM: dts: rskrza1: set rtc_x1 clock value
From: Geert Uytterhoeven @ 2017-03-30  8:47 UTC (permalink / raw)
  To: Chris Brandt
  Cc: Alessandro Zummo, Alexandre Belloni, Rob Herring, Mark Rutland,
	Simon Horman, RTCLINUX,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Linux-Renesas
In-Reply-To: <20170329173035.67477-7-chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>

On Wed, Mar 29, 2017 at 7:30 PM, Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org> wrote:
> Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to
> non-zero.
>
> Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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^ permalink raw reply

* Re: [PATCH v3 4/7] ARM: dts: r7s72100: add RTC_X clock inputs to device tree
From: Geert Uytterhoeven @ 2017-03-30  8:46 UTC (permalink / raw)
  To: Chris Brandt
  Cc: Alessandro Zummo, Alexandre Belloni, Rob Herring, Mark Rutland,
	Simon Horman, RTCLINUX,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Linux-Renesas
In-Reply-To: <20170329173035.67477-5-chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>

On Wed, Mar 29, 2017 at 7:30 PM, Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org> wrote:
> Add the RTC clocks to device tree. The frequencies must be fixed values
> according to the hardware manual.
>
> Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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^ permalink raw reply

* Re: [PATCH v3 3/7] arm: dts: dt-bindings: Add Renesas RZ pinctrl header
From: Linus Walleij @ 2017-03-30  8:33 UTC (permalink / raw)
  To: jacopo
  Cc: Jacopo Mondi, Bjorn Andersson, Geert Uytterhoeven,
	Laurent Pinchart, Chris Brandt, Rob Herring, Mark Rutland,
	Russell King, Linux-Renesas, linux-gpio@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <20170329155654.GD6247@w540>

On Wed, Mar 29, 2017 at 5:56 PM, jacopo <jacopo@jmondi.org> wrote:

> I can try to give you a few reasons why I don't see those flags fit in
> the pin configuration flags definition.
>
> *) those flags are used during pin multiplexing procedure only and that
> procedure has a specific order to be respected:
>
> You can have a look here:
> https://www.spinics.net/lists/linux-renesas-soc/msg12793.html
> In "rza1_alternate_function_conf()" function, we need to set bidir
> before setting every other register.
> The same applies some lines below:, the PIPC, PMC and PM register set order
> has to be respected, and depends on those BIDIR and SWIO_* parameters.
> This implies those configuration cannot be applied after pin muxing,
> certainly not in pin_config[_group]_set() whose invocation time
> is independent from pin_mux_set()'s one.

But now you are mixing up syntax and semantics.

You are describing what steps are necessary on this hardware to
apply a certain setting. That is fine, if you didn't need any specific
semantics there, you could be using pinctrl-single which will just
hammer stuff into registers, one register per pin. You have a pin
controller driver exactly beacause your hardware has semantics.

How this is described in the device tree or a board file is a different
thing from how you write your driver.

I understand why i makes for easier code, but does it make for more
generic and understandable device trees for people maintaining
several systems? I don't think so.

> One way forward would be, every time we mux a pin, look for a pinconf group
> that includes the pin we're muxing. That would happen for each pin,
> for no added benefits imo.

The benefit is clearly abstraction, standardization and readability of the
device tree. I, as developer, understand what is going on electrically,
having seen this on other systems, and being able to access generic
documentation on generic pin config properties.

> *) as Geert already pointed out, we may need dedicated subnodes to
> specify those pin configuration flags, not only because of what Chris
> said, but because pinconf_generic_dt_subnode_to_map() wants "pins" or
> "groups" to be there in the subnode, and in our pin multiplexing
> sub-nodes we only have "pinmux" property (say: we cannot specify
> pin_conf flags in the same sub-node where we describe pin
> multiplexing, we always need a dedicated sub-node).
> Chris and Geert gave some examples in their replies on how that would
> like, and how it makes the bindings a little more complex.

Very little more complex, and actually it could be argued that this
is exactly why subnodes exist: to be able to have different pin config
on pins. I think it is very readable.

> *) those flags, according to Chris, won't be used in RZ/A2, and
> reasonably not in any other RZ device. Do we want to add them to the
> generic bindings, being them so specific to this hardware platform?

I have seen so much stuff that people say is "necessarily different"
for their platform. It turns our that silicon IO and solid state physics
isn't that much different between systems. The same things invariably
pop up in several chips.

Hell this was what people said about this whole subsystem from the
beginning: pin control is so necessarily different that there is no point
in trying to create an abstraction for it.

If I had listened to that kind of advice we wouldn't be where we are today.

And that said, I have already pointed out that two of them already
exist in the pin control subsystem (PIN_CONFIG*). Because other SoCs
are doing similar things.

> One thing I suggest considering is to get rid of those flags, at
> least in bindings, and introduce 3 variants for each pin multiplexing
> function identifier.
>
> Say:
> include/dt-bindings/pinctrl/r7s72100-pinctrl.h:
> #define MUX_1               (1 << 16)
> #define MUX_1_BIDIR         (1 << 16 | 1 << 24)
> #define MUX_1_SWIO_IN       (1 << 16 | 2 << 24)
> #define MUX_1_SWIO_OUT      (1 << 16 | 3 << 24)
> ...
> #define MUX_8               (8 << 16)
> #define MUX_8_BIDIR         (8 << 16 | 1 << 24)
> ....

I understand they can be made more beautiful, but in my view
that is putting make up on a pig, I want generic pin config for these
things.


>> What is wrong in doing this with generic pin config using
>> PIN_CONFIG_INPUT_ENABLE and PIN_CONFIG_OUTPUT
>> (ignoring the argument)?
>>
>> In the device tree use input-enable and add a new output-enable
>> (with unspecified value) with proper description and DT bindings?
>>
>> And if you think these have no general applicability, by the end
>> of the day they are *still* pin config, not magic flags we can choose to
>> toss in with the muxing, so you can do what the Qualcomm driver
>> does and add custom pin configurations extending the generic
>> pin config, see drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
>> qcom,pull-up-strength etc.
>>
>
> I see, but that custom pin configuration flag can be applied
> independently from pin muxing procedure and it can be applied to pins
> while they're configured in GPIO mode.

See "GPIO mode pitfalls" in Documentation/pinctrl.txt
I've been over this hardware lingo so many times already.

It is not about "GPIO" at all, it is about pin configuration. The
generic pin config was not invented for GPIO, it was just recently
that we started to provide pin config back-ends for GPIO. Only
Intel do that so far.

> Our "flags" are not of that nature, and only apply to some register
> setting during pinmux, as I hopefully tried to clarify above.

And that is a driver semantic. Or even a subsystem semantic. No
big deal, accumulate such writes in the driver and apply it all when you have
it all available no matter if pin multiplexing or pin config happens first?
Surely this is just a hardware pecularity, then it warrants some special
driver code.

If you definately feel you must get a call from the pin control core setting
up muxing and config at the same time we need to think of a way to
augment the pin control core if necessary?

The fact that Linux pin control subsystem semantics you don't
like does not affect the relevant device tree bindings.

Yours,
Linus Walleij

^ permalink raw reply

* [PATCH V1 1/1] mtd: mtk-nor: set controller to 4B mode with large capacity flash
From: Guochun Mao @ 2017-03-30  8:23 UTC (permalink / raw)
  To: Boris Brezillon, Marek Vasut
  Cc: Mark Rutland, devicetree, Guochun Mao, Richard Weinberger,
	Russell King, linux-kernel, Rob Herring, linux-mtd,
	Matthias Brugger, linux-mediatek, Cyrille Pitchen,
	David Woodhouse, linux-arm-kernel
In-Reply-To: <1490862222-723-1-git-send-email-guochun.mao@mediatek.com>

when nor's size larger than 16MByte, nor and controller should
enter 4Byte mode simultaneously.

Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
---
 drivers/mtd/spi-nor/mtk-quadspi.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/mtd/spi-nor/mtk-quadspi.c b/drivers/mtd/spi-nor/mtk-quadspi.c
index e661877..05cd8a8 100644
--- a/drivers/mtd/spi-nor/mtk-quadspi.c
+++ b/drivers/mtd/spi-nor/mtk-quadspi.c
@@ -369,6 +369,13 @@ static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
 		/* We only handle 1 byte */
 		ret = mt8173_nor_wr_sr(mt8173_nor, *buf);
 		break;
+	case SPINOR_OP_EN4B:
+		/* Set nor controller to 4-byte address mode,
+		 * and simultaneously set nor flash.
+		 * This case should cooperate with default operation.
+		 */
+		writeb(readb(mt8173_nor->base + MTK_NOR_DUAL_REG) | 0x10,
+				mt8173_nor->base + MTK_NOR_DUAL_REG);
 	default:
 		ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0);
 		if (ret)
-- 
1.7.9.5

^ permalink raw reply related

* [PATCH V1] mtd: mtk-nor: set controller to 4B mode with large capacity flash
From: Guochun Mao @ 2017-03-30  8:23 UTC (permalink / raw)
  To: Boris Brezillon, Marek Vasut
  Cc: Mark Rutland, devicetree, Richard Weinberger, Russell King,
	linux-kernel, Rob Herring, linux-mtd, Matthias Brugger,
	linux-mediatek, Cyrille Pitchen, David Woodhouse,
	linux-arm-kernel

Guochun Mao (1):
  mtd: mtk-nor: set controller to 4B mode with large capacity flash

 drivers/mtd/spi-nor/mtk-quadspi.c | 7 +++++++
 1 file changed, 7 insertions(+)

-- 
1.9.1 

^ permalink raw reply

* Re: [PATCH 2/2] soc/imx: add workaround for i.MX6QP to the GPC PD driver
From: Lucas Stach @ 2017-03-30  8:22 UTC (permalink / raw)
  To: Lothar Waßmann
  Cc: A.S. Dong, devicetree@vger.kernel.org,
	patchwork-lst@pengutronix.de, kernel@pengutronix.de,
	Fabio Estevam, Shawn Guo, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20170330090833.09ac3c33@ipc1.ka-ro>

Am Donnerstag, den 30.03.2017, 09:08 +0200 schrieb Lothar Waßmann:
> Hi,
> 
> On Wed, 29 Mar 2017 18:13:46 +0200 Lucas Stach wrote:
> > Am Mittwoch, den 29.03.2017, 16:08 +0000 schrieb A.S. Dong:
> > > Hi Lucas,
> > > 
> > > > -----Original Message-----
> > > > From: Lucas Stach [mailto:l.stach@pengutronix.de]
> > > > Sent: Thursday, March 23, 2017 10:44 PM
> > > > To: Shawn Guo
> > > > Cc: Fabio Estevam; A.S. Dong; devicetree@vger.kernel.org; linux-arm-
> > > > kernel@lists.infradead.org; kernel@pengutronix.de; patchwork-
> > > > lst@pengutronix.de
> > > > Subject: [PATCH 2/2] soc/imx: add workaround for i.MX6QP to the GPC PD
> > > > driver
> > > > 
> > > > On i.MX6QP, due to hardware erratum ERR009619, the PRE clocks may be
> > > > stalled during the power up sequencing of the PU power domain. As this may
> > > > lead to a complete loss of display output, the recommended workaround is
> > > > to keep the PU domain enabled during normal system operation.
> > > > 
> > > > Implement this by rejecting the domain power down request on the affected
> > > > SoC.
> > > > 
> > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > > ---
> > > >  drivers/soc/imx/gpc.c | 19 +++++++++++++++++++
> > > >  1 file changed, 19 insertions(+)
> > > > 
> > > > diff --git a/drivers/soc/imx/gpc.c b/drivers/soc/imx/gpc.c index
> > > > 4294287e5f6c..599e1e46f694 100644
> > > > --- a/drivers/soc/imx/gpc.c
> > > > +++ b/drivers/soc/imx/gpc.c
> > > > @@ -45,6 +45,7 @@ struct imx_pm_domain {
> > > >  	unsigned int reg_offs;
> > > >  	signed char cntr_pdn_bit;
> > > >  	unsigned int ipg_rate_mhz;
> > > > +	bool allow_dynamic_pd;
> > > >  };
> > > > 
> > > >  static inline struct imx_pm_domain *
> > > > @@ -59,6 +60,9 @@ static int imx6_pm_domain_power_off(struct
> > > > generic_pm_domain *genpd)
> > > >  	int iso, iso2sw;
> > > >  	u32 val;
> > > > 
> > > > +	if (!pd->allow_dynamic_pd)
> > > > +		return -EBUSY;
> > > > +
> > > >  	/* Read ISO and ISO2SW power down delays */
> > > >  	regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
> > > >  	iso = val & 0x3f;
> > > > @@ -255,6 +259,7 @@ static struct imx_pm_domain imx_gpc_domains[] = {
> > > >  		},
> > > >  		.reg_offs = 0x260,
> > > >  		.cntr_pdn_bit = 0,
> > > > +		.allow_dynamic_pd = true,
> > > >  	}, {
> > > >  		.base = {
> > > >  			.name = "DISPLAY",
> > > > @@ -263,23 +268,33 @@ static struct imx_pm_domain imx_gpc_domains[] = {
> > > >  		},
> > > >  		.reg_offs = 0x240,
> > > >  		.cntr_pdn_bit = 4,
> > > > +		.allow_dynamic_pd = true,
> > > 
> > > Just a Nitpick, besides shawn's comment in another mail,
> > > if we use a domain flag like IMX_PD_ALWAYS_ON set by SoC errata flag,
> > > then probably we can save all the default allow_dynamic_pd lines.
> > > This also release the life when adding new domains.
> > 
> > If other things like that show up we can certainly switch to a flags
> > field. In the meantime I like that the current style is more explicit
> > about it.
> > 
> Since the purpose of the driver is all about dynamic power management,
> I would rather add a 'disable_dynamic_pd' for the case(s) where it's
> not allowed, rather than having to state the obvious over and over
> again.

Convincing argument. I'll change that in v2.

Regards,
Lucas



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH 1/5 v3] iio: xoadc: augment DT bindings a bit
From: Peter Meerwald-Stadler @ 2017-03-30  8:18 UTC (permalink / raw)
  To: Linus Walleij
  Cc: Jonathan Cameron, linux-iio-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
	devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170330080541.4065-1-linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

[-- Attachment #1: Type: text/plain, Size: 6134 bytes --]


> In order to accommodate in a logical manner for the premuxed channels
> in PM8921 and the similarly addressed channels in later PMICs, we
> need a twocell arrangement with premux and analog mux setting as
> a tuple to uniquely identify a hardware channel.
> 
> These bindings are not yet in use, so it should be fine to augment
> them before we actually start using it in drivers and device trees.

nitpicking below
 
> This scheme came out of lengthy discussions and reverse-engineering
> and reading of the few information sources we have.
> 
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Suggested-by: Björn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> ChangeLog v2->v3:
> - Drop leading zeroes on unit addresses.
> ChangeLog v1->v2:
> - Name nodes with <01 02> in a foo@0102 pattern.
> - Minor spelling nits.
> - Delete flimsy leftover docs from an interrim development path.
> ---
>  .../bindings/iio/adc/qcom,pm8xxx-xoadc.txt         | 76 ++++++++++++----------
>  1 file changed, 42 insertions(+), 34 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt
> index 53cd146d8096..69c404112df1 100644
> --- a/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt
> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt
> @@ -19,32 +19,42 @@ Required properties:
>    with PMIC variant but is typically something like 2.2 or 1.8V.
>  
>  The following required properties are standard for IO channels, see
> -iio-bindings.txt for more details:
> +iio-bindings.txt for more details, but noitice that this particular

notice

> +ADC has a special adressing scheme that require two cells for

addressing

> +identifying each ADC channel:
>  
> -- #address-cells: should be set to <1>
> +- #address-cells: should be set to <2>, the first cell is the
> +  prescaler (on PM8058) or premux (on PM8921) with two valid bits
> +  so legal values are 0x00, 0x01 or 0x02. The second cell
> +  is the main analog mux setting (0x00..0x0f). The combination
> +  of prescaler/premux and analog mux uniquely addresses a hardware
> +  channel on all systems.
>  
>  - #size-cells: should be set to <0>
>  
> -- #io-channel-cells: should be set to <1>
> +- #io-channel-cells: should be set to <2>, again the cells are
> +  precaler or premux followed by the analog muxing line.
>  
>  - interrupts: should refer to the parent PMIC interrupt controller
>    and reference the proper ADC interrupt.
>  
>  Required subnodes:
>  
> -The ADC channels are configured as subnodes of the ADC. Since some of
> -them are used for calibrating the ADC, these nodes are compulsory:
> +The ADC channels are configured as subnodes of the ADC.
> +
> +Since some of them are used for calibrating the ADC, these nodes are
> +compulsory:
>  
>  adc-channel@c {
> -	reg = <0x0c>;
> +	reg = <0x00 0x0c>;
>  };
>  
>  adc-channel@d {
> -	reg = <0x0d>;
> +	reg = <0x00 0x0d>;
>  };
>  
>  adc-channel@f {
> -	reg = <0x0f>;
> +	reg = <0x00 0x0f>;
>  };
>  
>  These three nodes are used for absolute and ratiometric calibration
> @@ -52,13 +62,13 @@ and only need to have these reg values: they are by hardware definition
>  1:1 ratio converters that sample 625, 1250 and 0 milliV and create
>  an interpolation calibration for all other ADCs.
>  
> -Optional subnodes: any channels other than channel 0x0c, 0x0d and
> -0x0f are optional.
> +Optional subnodes: any channels other than channels [0x00 0x0c],
> +[0x00 0x0d] and [0x00 0x0f] are optional.
>  
>  Required channel node properties:
>  
>  - reg: should contain the hardware channel number in the range
> -  0 .. 0x0f (4 bits). The hardware only supports 16 channels.
> +  0 .. 0xff (8 bits).
>  
>  Optional channel node properties:
>  
> @@ -94,56 +104,54 @@ Example:
>  xoadc: xoadc@197 {
>  	compatible = "qcom,pm8058-adc";
>  	reg = <0x197>;
> -	interrupt-parent = <&pm8058>;
> -	interrupts = <76 1>;
> -	#address-cells = <1>;
> +	interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
> +	#address-cells = <2>;
>  	#size-cells = <0>;
> -	#io-channel-cells = <1>;
> +	#io-channel-cells = <2>;
>  
>  	vcoin: adc-channel@0 {
> -		reg = <0x00>;
> +		reg = <0x00 0x00>;
>  	};
>  	vbat: adc-channel@1 {
> -		reg = <0x01>;
> +		reg = <0x00 0x01>;
>  	};
>  	dcin: adc-channel@2 {
> -		reg = <0x02>;
> +		reg = <0x00 0x02>;
>  	};
>  	ichg: adc-channel@3 {
> -		reg = <0x03>;
> +		reg = <0x00 0x03>;
>  	};
>  	vph_pwr: adc-channel@4 {
> -		reg = <0x04>;
> +		reg = <0x00 0x04>;
>  	};
>  	usb_vbus: adc-channel@a {
> -		reg = <0x0a>;
> +		reg = <0x00 0x0a>;
>  	};
>  	die_temp: adc-channel@b {
> -		reg = <0x0b>;
> +		reg = <0x00 0x0b>;
>  	};
>  	ref_625mv: adc-channel@c {
> -		reg = <0x0c>;
> +		reg = <0x00 0x0c>;
>  	};
>  	ref_1250mv: adc-channel@d {
> -		reg = <0x0d>;
> +		reg = <0x00 0x0d>;
>  	};
>  	ref_325mv: adc-channel@e {
> -		reg = <0x0e>;
> +		reg = <0x00 0x0e>;
>  	};
>  	ref_muxoff: adc-channel@f {
> -		reg = <0x0f>;
> +		reg = <0x00 0x0f>;
>  	};
>  };
>  
> -
>  /* IIO client node */
>  iio-hwmon {
>  	compatible = "iio-hwmon";
> -	io-channels = <&xoadc 0x01>, /* Battery */
> -		    <&xoadc 0x02>, /* DC in (charger) */
> -		    <&xoadc 0x04>, /* VPH the main system voltage */
> -		    <&xoadc 0x0b>, /* Die temperature */
> -		    <&xoadc 0x0c>, /* Reference voltage 1.25V */
> -		    <&xoadc 0x0d>, /* Reference voltage 0.625V */
> -		    <&xoadc 0x0e>; /* Reference voltage 0.325V */
> +	io-channels = <&xoadc 0x00 0x01>, /* Battery */
> +		    <&xoadc 0x00 0x02>, /* DC in (charger) */
> +		    <&xoadc 0x00 0x04>, /* VPH the main system voltage */
> +		    <&xoadc 0x00 0x0b>, /* Die temperature */
> +		    <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
> +		    <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
> +		    <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
>  };
> 

-- 

Peter Meerwald-Stadler
Mobile: +43 664 24 44 418

^ permalink raw reply

* Re: [PATCH v1 0/8] clk: meson: gxbb: more clock controller update for audio support
From: Neil Armstrong @ 2017-03-30  8:15 UTC (permalink / raw)
  To: Michael Turquette, Jerome Brunet, Stephen Boyd, Kevin Hilman,
	Carlo Caione
  Cc: linux-clk, linux-amlogic, linux-kernel, devicetree
In-Reply-To: <149082017390.31513.12254031076684821992@resonance>

On 03/29/2017 10:42 PM, Michael Turquette wrote:
> Hi Jerome,
> 
> Adding Neil Armstong to Cc.
> 
> Quoting Jerome Brunet (2017-03-28 07:45:57)
>> The patchset is the 2nd round of update to the meson gxbb clock controller
>> to add initial audio support. The patchset is based on clk-next.
>>
>> There is not much out of the ordinary here (adding new clocks and exposing
>> them) except maybe for 2 patches:
>> Patch #2: Adds a safety check while registering clocks to protect against
>>           holes in clk_hw_onecell_data, if it ever happens. Same thing is
>>           done for the meson8b clock controller. 
>> Patch #3: Adds a new clock divider driver to implement the necessary
>>           policy for the i2s master clock (see patch changelog)
>>
>> This patchset has been test on the gxbb p200 and gxl p230.
> 
> First off, this series looks fine to me. Please add,
> 
> Acked-by: Michael Turquette <mturquette@baylibre.com>
> 
> Secondly, it seems the AmLogic clock drivers have mostly calmed down and
> things are in the "add new clocks when we need them" phase, which is
> nice. Since you and Neil are doing a lot of this work, might I suggest
> that you both start collecting patches for the AmLogic/meson clock
> drivers begin submitting pull requests to Stephen and myself?
> 
> As usual the rules are the same as always: all patches in the PR must
> first be posted for review on the list. PRs should correspond to signed
> tags. Stephen and I might ignore PRs sent after -rc4, and will
> definitely ignore PRs sent after -rc6 since we want some stabilization
> time before the merge window. Base your branch on -rc1, not on clk-next.
> 
> Also feel free to submit a patch to MAINTAINERS with either one or both
> of you maintaining the meson clk stuff, assuming that you're OK to
> review all of those patches and collect them into a PR.
> 
> Thoughts?

Thanks Mike, I'll be glad to co-maintain this with jerome !

Neil

> 
> If it sounds good to you then I suggest grabbing the clk-meson branch
> from the clk tree and using that as a baseline for your first PR. In the
> future you'll just Linus' -rc1, but I have already created a branch for
> this cycle. You can apply these 8 patches with my Ack and send a PR by
> -rc6 (possibly with other stuff collected from Martin, etc).

Acked !

> 
> Thanks,
> Mike
> 
>>
>> Jerome Brunet (8):
>>   dt-bindings: clock: gxbb: expose spdif clock gates
>>   clk: meson: gxbb: protect against holes in the onecell_data array
>>   clk: meson: add audio clock divider support
>>   clk: meson: gxbb: add cts_amclk
>>   clk: meson: gxbb: add cts_mclk_i958
>>   clk: meson: gxbb: add cts_i958 clock
>>   dt-bindings: clock: gxbb: expose i2s master clock
>>   dt-bindings: clock: gxbb: expose spdif master clock
>>
>>  drivers/clk/meson/Makefile            |   2 +-
>>  drivers/clk/meson/clk-audio-divider.c | 149 ++++++++++++++++++++++++++++++++++
>>  drivers/clk/meson/clkc.h              |  10 +++
>>  drivers/clk/meson/gxbb.c              | 144 ++++++++++++++++++++++++++++++++
>>  drivers/clk/meson/gxbb.h              |  13 ++-
>>  include/dt-bindings/clock/gxbb-clkc.h |   5 ++
>>  6 files changed, 319 insertions(+), 4 deletions(-)
>>  create mode 100644 drivers/clk/meson/clk-audio-divider.c
>>
>> -- 
>> 2.9.3
>>

^ permalink raw reply


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