* [PATCH v7 08/13] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC
From: Gregory CLEMENT @ 2017-03-30 15:23 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, linux-mmc
Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Gregory CLEMENT,
Thomas Petazzoni, linux-arm-kernel, Mike Turquette, Stephen Boyd,
linux-clk, linux-kernel, Rob Herring, devicetree, Ziji Hu,
Jimmy Xu, Jisheng Zhang, Nadav Haklai, Ryan Gao, Doug Jones,
Victor Gu, Wei(SOCP) Liu, Wilson Ding, Yehuda
In-Reply-To: <cover.51071caa64e5df81264a91b9a81ed1e94f47d2c4.1490886907.git-series.gregory.clement@free-electrons.com>
From: Hu Ziji <huziji@marvell.com>
Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY.
Multiple types of PHYs are supported.
Add support to multiple types of PHYs init and configuration.
Add register definitions of PHYs.
Xenon PHY cannot fit in kernel common PHY framework.
Xenon SDHC PHY register is a part of Xenon SDHC register set.
Besides, MMC initialization has to call several PHY functions to
complete timing setting.
Those PHY setting functions have to access SDHC registers and know
current MMC setting, such as bus width, clock frequency and
speed mode.
As a result, implement Xenon PHY in MMC host directory.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/mmc/host/Makefile | 2 +-
drivers/mmc/host/sdhci-xenon-phy.c | 727 ++++++++++++++++++++++++++++++-
drivers/mmc/host/sdhci-xenon.c | 9 +-
drivers/mmc/host/sdhci-xenon.h | 39 ++-
4 files changed, 774 insertions(+), 3 deletions(-)
create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 014f0548ea86..9e4a94592e30 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -86,4 +86,4 @@ ifeq ($(CONFIG_CB710_DEBUG),y)
endif
obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o
-sdhci-xenon-driver-y += sdhci-xenon.o
+sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy.o
diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c
new file mode 100644
index 000000000000..b14544e91b65
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon-phy.c
@@ -0,0 +1,727 @@
+/*
+ * PHY support for Xenon SDHC
+ *
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author: Hu Ziji <huziji@marvell.com>
+ * Date: 2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ */
+
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/ktime.h>
+#include <linux/of_address.h>
+
+#include "sdhci-pltfm.h"
+#include "sdhci-xenon.h"
+
+/* Register base for eMMC PHY 5.0 Version */
+#define XENON_EMMC_5_0_PHY_REG_BASE 0x0160
+/* Register base for eMMC PHY 5.1 Version */
+#define XENON_EMMC_PHY_REG_BASE 0x0170
+
+#define XENON_EMMC_PHY_TIMING_ADJUST XENON_EMMC_PHY_REG_BASE
+#define XENON_EMMC_5_0_PHY_TIMING_ADJUST XENON_EMMC_5_0_PHY_REG_BASE
+#define XENON_TIMING_ADJUST_SLOW_MODE BIT(29)
+#define XENON_TIMING_ADJUST_SDIO_MODE BIT(28)
+#define XENON_SAMPL_INV_QSP_PHASE_SELECT BIT(18)
+#define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18
+#define XENON_PHY_INITIALIZAION BIT(31)
+#define XENON_WAIT_CYCLE_BEFORE_USING_MASK 0xF
+#define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT 12
+#define XENON_FC_SYNC_EN_DURATION_MASK 0xF
+#define XENON_FC_SYNC_EN_DURATION_SHIFT 8
+#define XENON_FC_SYNC_RST_EN_DURATION_MASK 0xF
+#define XENON_FC_SYNC_RST_EN_DURATION_SHIFT 4
+#define XENON_FC_SYNC_RST_DURATION_MASK 0xF
+#define XENON_FC_SYNC_RST_DURATION_SHIFT 0
+
+#define XENON_EMMC_PHY_FUNC_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x4)
+#define XENON_EMMC_5_0_PHY_FUNC_CONTROL \
+ (XENON_EMMC_5_0_PHY_REG_BASE + 0x4)
+#define XENON_ASYNC_DDRMODE_MASK BIT(23)
+#define XENON_ASYNC_DDRMODE_SHIFT 23
+#define XENON_CMD_DDR_MODE BIT(16)
+#define XENON_DQ_DDR_MODE_SHIFT 8
+#define XENON_DQ_DDR_MODE_MASK 0xFF
+#define XENON_DQ_ASYNC_MODE BIT(4)
+
+#define XENON_EMMC_PHY_PAD_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x8)
+#define XENON_EMMC_5_0_PHY_PAD_CONTROL \
+ (XENON_EMMC_5_0_PHY_REG_BASE + 0x8)
+#define XENON_REC_EN_SHIFT 24
+#define XENON_REC_EN_MASK 0xF
+#define XENON_FC_DQ_RECEN BIT(24)
+#define XENON_FC_CMD_RECEN BIT(25)
+#define XENON_FC_QSP_RECEN BIT(26)
+#define XENON_FC_QSN_RECEN BIT(27)
+#define XENON_OEN_QSN BIT(28)
+#define XENON_AUTO_RECEN_CTRL BIT(30)
+#define XENON_FC_ALL_CMOS_RECEIVER 0xF000
+
+#define XENON_EMMC5_FC_QSP_PD BIT(18)
+#define XENON_EMMC5_FC_QSP_PU BIT(22)
+#define XENON_EMMC5_FC_CMD_PD BIT(17)
+#define XENON_EMMC5_FC_CMD_PU BIT(21)
+#define XENON_EMMC5_FC_DQ_PD BIT(16)
+#define XENON_EMMC5_FC_DQ_PU BIT(20)
+
+#define XENON_EMMC_PHY_PAD_CONTROL1 (XENON_EMMC_PHY_REG_BASE + 0xC)
+#define XENON_EMMC5_1_FC_QSP_PD BIT(9)
+#define XENON_EMMC5_1_FC_QSP_PU BIT(25)
+#define XENON_EMMC5_1_FC_CMD_PD BIT(8)
+#define XENON_EMMC5_1_FC_CMD_PU BIT(24)
+#define XENON_EMMC5_1_FC_DQ_PD 0xFF
+#define XENON_EMMC5_1_FC_DQ_PU (0xFF << 16)
+
+#define XENON_EMMC_PHY_PAD_CONTROL2 (XENON_EMMC_PHY_REG_BASE + 0x10)
+#define XENON_EMMC_5_0_PHY_PAD_CONTROL2 \
+ (XENON_EMMC_5_0_PHY_REG_BASE + 0xC)
+#define XENON_ZNR_MASK 0x1F
+#define XENON_ZNR_SHIFT 8
+#define XENON_ZPR_MASK 0x1F
+/* Preferred ZNR and ZPR value vary between different boards.
+ * The specific ZNR and ZPR value should be defined here
+ * according to board actual timing.
+ */
+#define XENON_ZNR_DEF_VALUE 0xF
+#define XENON_ZPR_DEF_VALUE 0xF
+
+#define XENON_EMMC_PHY_DLL_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x14)
+#define XENON_EMMC_5_0_PHY_DLL_CONTROL \
+ (XENON_EMMC_5_0_PHY_REG_BASE + 0x10)
+#define XENON_DLL_ENABLE BIT(31)
+#define XENON_DLL_UPDATE_STROBE_5_0 BIT(30)
+#define XENON_DLL_REFCLK_SEL BIT(30)
+#define XENON_DLL_UPDATE BIT(23)
+#define XENON_DLL_PHSEL1_SHIFT 24
+#define XENON_DLL_PHSEL0_SHIFT 16
+#define XENON_DLL_PHASE_MASK 0x3F
+#define XENON_DLL_PHASE_90_DEGREE 0x1F
+#define XENON_DLL_FAST_LOCK BIT(5)
+#define XENON_DLL_GAIN2X BIT(3)
+#define XENON_DLL_BYPASS_EN BIT(0)
+
+#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST \
+ (XENON_EMMC_5_0_PHY_REG_BASE + 0x14)
+#define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18)
+#define XENON_LOGIC_TIMING_VALUE 0x00AA8977
+
+/*
+ * List offset of PHY registers and some special register values
+ * in eMMC PHY 5.0 or eMMC PHY 5.1
+ */
+struct xenon_emmc_phy_regs {
+ /* Offset of Timing Adjust register */
+ u16 timing_adj;
+ /* Offset of Func Control register */
+ u16 func_ctrl;
+ /* Offset of Pad Control register */
+ u16 pad_ctrl;
+ /* Offset of Pad Control register 2 */
+ u16 pad_ctrl2;
+ /* Offset of DLL Control register */
+ u16 dll_ctrl;
+ /* Offset of Logic Timing Adjust register */
+ u16 logic_timing_adj;
+ /* DLL Update Enable bit */
+ u32 dll_update;
+};
+
+static const char * const phy_types[] = {
+ "emmc 5.0 phy",
+ "emmc 5.1 phy"
+};
+
+enum xenon_phy_type_enum {
+ EMMC_5_0_PHY,
+ EMMC_5_1_PHY,
+ NR_PHY_TYPES
+};
+
+static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
+ .timing_adj = XENON_EMMC_5_0_PHY_TIMING_ADJUST,
+ .func_ctrl = XENON_EMMC_5_0_PHY_FUNC_CONTROL,
+ .pad_ctrl = XENON_EMMC_5_0_PHY_PAD_CONTROL,
+ .pad_ctrl2 = XENON_EMMC_5_0_PHY_PAD_CONTROL2,
+ .dll_ctrl = XENON_EMMC_5_0_PHY_DLL_CONTROL,
+ .logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST,
+ .dll_update = XENON_DLL_UPDATE_STROBE_5_0,
+};
+
+static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
+ .timing_adj = XENON_EMMC_PHY_TIMING_ADJUST,
+ .func_ctrl = XENON_EMMC_PHY_FUNC_CONTROL,
+ .pad_ctrl = XENON_EMMC_PHY_PAD_CONTROL,
+ .pad_ctrl2 = XENON_EMMC_PHY_PAD_CONTROL2,
+ .dll_ctrl = XENON_EMMC_PHY_DLL_CONTROL,
+ .logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
+ .dll_update = XENON_DLL_UPDATE,
+};
+
+/*
+ * eMMC PHY configuration and operations
+ */
+struct xenon_emmc_phy_params {
+ bool slow_mode;
+
+ u8 znr;
+ u8 zpr;
+
+ /* Nr of consecutive Sampling Points of a Valid Sampling Window */
+ u8 nr_tun_times;
+ /* Divider for calculating Tuning Step */
+ u8 tun_step_divider;
+};
+
+static int xenon_alloc_emmc_phy(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct xenon_emmc_phy_params *params;
+
+ params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL);
+ if (!params)
+ return -ENOMEM;
+
+ priv->phy_params = params;
+ if (priv->phy_type == EMMC_5_0_PHY)
+ priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs;
+ else
+ priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs;
+
+ return 0;
+}
+
+/*
+ * eMMC 5.0/5.1 PHY init/re-init.
+ * eMMC PHY init should be executed after:
+ * 1. SDCLK frequency changes.
+ * 2. SDCLK is stopped and re-enabled.
+ * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl
+ * are changed
+ */
+static int xenon_emmc_phy_init(struct sdhci_host *host)
+{
+ u32 reg;
+ u32 wait, clock;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+
+ reg = sdhci_readl(host, phy_regs->timing_adj);
+ reg |= XENON_PHY_INITIALIZAION;
+ sdhci_writel(host, reg, phy_regs->timing_adj);
+
+ /* Add duration of FC_SYNC_RST */
+ wait = ((reg >> XENON_FC_SYNC_RST_DURATION_SHIFT) &
+ XENON_FC_SYNC_RST_DURATION_MASK);
+ /* Add interval between FC_SYNC_EN and FC_SYNC_RST */
+ wait += ((reg >> XENON_FC_SYNC_RST_EN_DURATION_SHIFT) &
+ XENON_FC_SYNC_RST_EN_DURATION_MASK);
+ /* Add duration of asserting FC_SYNC_EN */
+ wait += ((reg >> XENON_FC_SYNC_EN_DURATION_SHIFT) &
+ XENON_FC_SYNC_EN_DURATION_MASK);
+ /* Add duration of waiting for PHY */
+ wait += ((reg >> XENON_WAIT_CYCLE_BEFORE_USING_SHIFT) &
+ XENON_WAIT_CYCLE_BEFORE_USING_MASK);
+ /* 4 additional bus clock and 4 AXI bus clock are required */
+ wait += 8;
+ wait <<= 20;
+
+ clock = host->clock;
+ if (!clock)
+ /* Use the possibly slowest bus frequency value */
+ clock = XENON_LOWEST_SDCLK_FREQ;
+ /* get the wait time */
+ wait /= clock;
+ wait++;
+ /* wait for host eMMC PHY init completes */
+ udelay(wait);
+
+ reg = sdhci_readl(host, phy_regs->timing_adj);
+ reg &= XENON_PHY_INITIALIZAION;
+ if (reg) {
+ dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n",
+ wait);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
+ * Enable eMMC PHY HW DLL
+ * DLL should be enabled and stable before HS200/SDR104 tuning,
+ * and before HS400 data strobe setting.
+ */
+static int xenon_emmc_phy_enable_dll(struct sdhci_host *host)
+{
+ u32 reg;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+ ktime_t timeout;
+
+ if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR))
+ return -EINVAL;
+
+ reg = sdhci_readl(host, phy_regs->dll_ctrl);
+ if (reg & XENON_DLL_ENABLE)
+ return 0;
+
+ /* Enable DLL */
+ reg = sdhci_readl(host, phy_regs->dll_ctrl);
+ reg |= (XENON_DLL_ENABLE | XENON_DLL_FAST_LOCK);
+
+ /*
+ * Set Phase as 90 degree, which is most common value.
+ * Might set another value if necessary.
+ * The granularity is 1 degree.
+ */
+ reg &= ~((XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL0_SHIFT) |
+ (XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL1_SHIFT));
+ reg |= ((XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL0_SHIFT) |
+ (XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL1_SHIFT));
+
+ reg &= ~XENON_DLL_BYPASS_EN;
+ reg |= phy_regs->dll_update;
+ if (priv->phy_type == EMMC_5_1_PHY)
+ reg &= ~XENON_DLL_REFCLK_SEL;
+ sdhci_writel(host, reg, phy_regs->dll_ctrl);
+
+ /* Wait max 32 ms */
+ timeout = ktime_add_ms(ktime_get(), 32);
+ while (!(sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) &
+ XENON_DLL_LOCK_STATE)) {
+ if (ktime_after(ktime_get(), timeout)) {
+ dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n");
+ return -ETIMEDOUT;
+ }
+ udelay(100);
+ }
+ return 0;
+}
+
+/*
+ * Config to eMMC PHY to prepare for tuning.
+ * Enable HW DLL and set the TUNING_STEP
+ */
+static int xenon_emmc_phy_config_tuning(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct xenon_emmc_phy_params *params = priv->phy_params;
+ u32 reg, tuning_step;
+ int ret;
+
+ if (host->clock <= MMC_HIGH_52_MAX_DTR)
+ return -EINVAL;
+
+ ret = xenon_emmc_phy_enable_dll(host);
+ if (ret)
+ return ret;
+
+ /* Achieve TUNING_STEP with HW DLL help */
+ reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL);
+ tuning_step = reg / params->tun_step_divider;
+ if (unlikely(tuning_step > XENON_TUNING_STEP_MASK)) {
+ dev_warn(mmc_dev(host->mmc),
+ "HS200 TUNING_STEP %d is larger than MAX value\n",
+ tuning_step);
+ tuning_step = XENON_TUNING_STEP_MASK;
+ }
+
+ /* Set TUNING_STEP for later tuning */
+ reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL);
+ reg &= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK <<
+ XENON_TUN_CONSECUTIVE_TIMES_SHIFT);
+ reg |= (params->nr_tun_times << XENON_TUN_CONSECUTIVE_TIMES_SHIFT);
+ reg &= ~(XENON_TUNING_STEP_MASK << XENON_TUNING_STEP_SHIFT);
+ reg |= (tuning_step << XENON_TUNING_STEP_SHIFT);
+ sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL);
+
+ return 0;
+}
+
+static void xenon_emmc_phy_disable_data_strobe(struct sdhci_host *host)
+{
+ u32 reg;
+
+ /* Disable SDHC Data Strobe */
+ reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
+ reg &= ~XENON_ENABLE_DATA_STROBE;
+ sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
+}
+
+/* Set HS400 Data Strobe */
+static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ u32 reg;
+
+ if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400))
+ return;
+
+ if (host->clock <= MMC_HIGH_52_MAX_DTR)
+ return;
+
+ dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n");
+
+ xenon_emmc_phy_enable_dll(host);
+
+ /* Enable SDHC Data Strobe */
+ reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
+ reg |= XENON_ENABLE_DATA_STROBE;
+ sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
+
+ /* Set Data Strobe Pull down */
+ if (priv->phy_type == EMMC_5_0_PHY) {
+ reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
+ reg |= XENON_EMMC5_FC_QSP_PD;
+ reg &= ~XENON_EMMC5_FC_QSP_PU;
+ sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
+ } else {
+ reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
+ reg |= XENON_EMMC5_1_FC_QSP_PD;
+ reg &= ~XENON_EMMC5_1_FC_QSP_PU;
+ sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
+ }
+}
+
+/*
+ * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
+ * in SDR mode, enable Slow Mode to bypass eMMC PHY.
+ * SDIO slower SDR mode also requires Slow Mode.
+ *
+ * If Slow Mode is enabled, return true.
+ * Otherwise, return false.
+ */
+static bool xenon_emmc_phy_slow_mode(struct sdhci_host *host,
+ unsigned char timing)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct xenon_emmc_phy_params *params = priv->phy_params;
+ struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+ u32 reg;
+ int ret;
+
+ if (host->clock > MMC_HIGH_52_MAX_DTR)
+ return false;
+
+ reg = sdhci_readl(host, phy_regs->timing_adj);
+ /* When in slower SDR mode, enable Slow Mode for SDIO
+ * or when Slow Mode flag is set
+ */
+ switch (timing) {
+ case MMC_TIMING_LEGACY:
+ /*
+ * If Slow Mode is required, enable Slow Mode by default
+ * in early init phase to avoid any potential issue.
+ */
+ if (params->slow_mode) {
+ reg |= XENON_TIMING_ADJUST_SLOW_MODE;
+ ret = true;
+ } else {
+ reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
+ ret = false;
+ }
+ break;
+ case MMC_TIMING_UHS_SDR25:
+ case MMC_TIMING_UHS_SDR12:
+ case MMC_TIMING_SD_HS:
+ case MMC_TIMING_MMC_HS:
+ if ((priv->init_card_type == MMC_TYPE_SDIO) ||
+ params->slow_mode) {
+ reg |= XENON_TIMING_ADJUST_SLOW_MODE;
+ ret = true;
+ break;
+ }
+ default:
+ reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
+ ret = false;
+ }
+
+ sdhci_writel(host, reg, phy_regs->timing_adj);
+ return ret;
+}
+
+/*
+ * Set-up eMMC 5.0/5.1 PHY.
+ * Specific configuration depends on the current speed mode in use.
+ */
+static void xenon_emmc_phy_set(struct sdhci_host *host,
+ unsigned char timing)
+{
+ u32 reg;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct xenon_emmc_phy_params *params = priv->phy_params;
+ struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+
+ dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n");
+
+ /* Setup pad, set bit[28] and bits[26:24] */
+ reg = sdhci_readl(host, phy_regs->pad_ctrl);
+ reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |
+ XENON_FC_QSP_RECEN | XENON_OEN_QSN);
+ /* All FC_XX_RECEIVCE should be set as CMOS Type */
+ reg |= XENON_FC_ALL_CMOS_RECEIVER;
+ sdhci_writel(host, reg, phy_regs->pad_ctrl);
+
+ /* Set CMD and DQ Pull Up */
+ if (priv->phy_type == EMMC_5_0_PHY) {
+ reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
+ reg |= (XENON_EMMC5_FC_CMD_PU | XENON_EMMC5_FC_DQ_PU);
+ reg &= ~(XENON_EMMC5_FC_CMD_PD | XENON_EMMC5_FC_DQ_PD);
+ sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
+ } else {
+ reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
+ reg |= (XENON_EMMC5_1_FC_CMD_PU | XENON_EMMC5_1_FC_DQ_PU);
+ reg &= ~(XENON_EMMC5_1_FC_CMD_PD | XENON_EMMC5_1_FC_DQ_PD);
+ sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
+ }
+
+ if (timing == MMC_TIMING_LEGACY) {
+ xenon_emmc_phy_slow_mode(host, timing);
+ goto phy_init;
+ }
+
+ /*
+ * If SDIO card, set SDIO Mode
+ * Otherwise, clear SDIO Mode
+ */
+ reg = sdhci_readl(host, phy_regs->timing_adj);
+ if (priv->init_card_type == MMC_TYPE_SDIO)
+ reg |= XENON_TIMING_ADJUST_SDIO_MODE;
+ else
+ reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;
+ sdhci_writel(host, reg, phy_regs->timing_adj);
+
+ if (xenon_emmc_phy_slow_mode(host, timing))
+ goto phy_init;
+
+ /*
+ * Set preferred ZNR and ZPR value
+ * The ZNR and ZPR value vary between different boards.
+ * Define them both in sdhci-xenon-emmc-phy.h.
+ */
+ reg = sdhci_readl(host, phy_regs->pad_ctrl2);
+ reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);
+ reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr);
+ sdhci_writel(host, reg, phy_regs->pad_ctrl2);
+
+ /*
+ * When setting EMMC_PHY_FUNC_CONTROL register,
+ * SD clock should be disabled
+ */
+ reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+ reg &= ~SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
+
+ reg = sdhci_readl(host, phy_regs->func_ctrl);
+ switch (timing) {
+ case MMC_TIMING_MMC_HS400:
+ reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
+ XENON_CMD_DDR_MODE;
+ reg &= ~XENON_DQ_ASYNC_MODE;
+ break;
+ case MMC_TIMING_UHS_DDR50:
+ case MMC_TIMING_MMC_DDR52:
+ reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
+ XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE;
+ break;
+ default:
+ reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
+ XENON_CMD_DDR_MODE);
+ reg |= XENON_DQ_ASYNC_MODE;
+ }
+ sdhci_writel(host, reg, phy_regs->func_ctrl);
+
+ /* Enable bus clock */
+ reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+ reg |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
+
+ if (timing == MMC_TIMING_MMC_HS400)
+ /* Hardware team recommend a value for HS400 */
+ sdhci_writel(host, XENON_LOGIC_TIMING_VALUE,
+ phy_regs->logic_timing_adj);
+ else
+ xenon_emmc_phy_disable_data_strobe(host);
+
+phy_init:
+ xenon_emmc_phy_init(host);
+
+ dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
+}
+
+static int xenon_emmc_phy_parse_param_dt(struct sdhci_host *host,
+ struct device_node *np,
+ struct xenon_emmc_phy_params *params)
+{
+ u32 value;
+
+ params->slow_mode = false;
+ if (of_property_read_bool(np, "marvell,xenon-phy-slow-mode"))
+ params->slow_mode = true;
+
+ params->znr = XENON_ZNR_DEF_VALUE;
+ if (!of_property_read_u32(np, "marvell,xenon-phy-znr", &value))
+ params->znr = value & XENON_ZNR_MASK;
+
+ params->zpr = XENON_ZPR_DEF_VALUE;
+ if (!of_property_read_u32(np, "marvell,xenon-phy-zpr", &value))
+ params->zpr = value & XENON_ZPR_MASK;
+
+ params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES;
+ if (!of_property_read_u32(np, "marvell,xenon-phy-nr-success-tun",
+ &value))
+ params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK;
+
+ params->tun_step_divider = XENON_TUNING_STEP_DIVIDER;
+ if (!of_property_read_u32(np, "marvell,xenon-phy-tun-step-divider",
+ &value))
+ params->tun_step_divider = value & 0xFF;
+
+ return 0;
+}
+
+/*
+ * Setting PHY when card is working in High Speed Mode.
+ * HS400 set data strobe line.
+ * HS200/SDR104 set tuning config to prepare for tuning.
+ */
+static int xenon_hs_delay_adj(struct sdhci_host *host)
+{
+ int ret = 0;
+
+ if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ))
+ return -EINVAL;
+
+ switch (host->timing) {
+ case MMC_TIMING_MMC_HS400:
+ xenon_emmc_phy_strobe_delay_adj(host);
+ return 0;
+ case MMC_TIMING_MMC_HS200:
+ case MMC_TIMING_UHS_SDR104:
+ return xenon_emmc_phy_config_tuning(host);
+ case MMC_TIMING_MMC_DDR52:
+ case MMC_TIMING_UHS_DDR50:
+ /*
+ * DDR Mode requires driver to scan Sampling Fixed Delay Line,
+ * to find out a perfect operation sampling point.
+ * It is hard to implement such a scan in host driver
+ * since initiating commands by host driver is not safe.
+ * Thus so far just keep PHY Sampling Fixed Delay in
+ * default value of DDR mode.
+ *
+ * If any timing issue occurs in DDR mode on Marvell products,
+ * please contact maintainer for internal support in Marvell.
+ */
+ dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n");
+ return 0;
+ }
+
+ return ret;
+}
+
+/*
+ * Adjust PHY setting.
+ * PHY setting should be adjusted when SDCLK frequency, Bus Width
+ * or Speed Mode is changed.
+ * Additional config are required when card is working in High Speed mode,
+ * after leaving Legacy Mode.
+ */
+int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ int ret = 0;
+
+ if (!host->clock) {
+ priv->clock = 0;
+ return 0;
+ }
+
+ /*
+ * The timing, frequency or bus width is changed,
+ * better to set eMMC PHY based on current setting
+ * and adjust Xenon SDHC delay.
+ */
+ if ((host->clock == priv->clock) &&
+ (ios->bus_width == priv->bus_width) &&
+ (ios->timing == priv->timing))
+ return 0;
+
+ xenon_emmc_phy_set(host, ios->timing);
+
+ /* Update the record */
+ priv->bus_width = ios->bus_width;
+
+ priv->timing = ios->timing;
+ priv->clock = host->clock;
+
+ /* Legacy mode is a special case */
+ if (ios->timing == MMC_TIMING_LEGACY)
+ return 0;
+
+ if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
+ ret = xenon_hs_delay_adj(host);
+ return ret;
+}
+
+void xenon_clean_phy(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+ kfree(priv->phy_params);
+}
+
+static int xenon_add_phy(struct device_node *np, struct sdhci_host *host,
+ const char *phy_name)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ int i, ret;
+
+ for (i = 0; i < NR_PHY_TYPES; i++) {
+ if (!strcmp(phy_name, phy_types[i])) {
+ priv->phy_type = i;
+ break;
+ }
+ }
+ if (i == NR_PHY_TYPES) {
+ dev_err(mmc_dev(host->mmc),
+ "Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n",
+ phy_name);
+ priv->phy_type = EMMC_5_1_PHY;
+ }
+
+ ret = xenon_alloc_emmc_phy(host);
+ if (ret)
+ return ret;
+
+ ret = xenon_emmc_phy_parse_param_dt(host, np, priv->phy_params);
+ if (ret)
+ xenon_clean_phy(host);
+
+ return ret;
+}
+
+int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host)
+{
+ const char *phy_type = NULL;
+
+ if (!of_property_read_string(np, "marvell,xenon-phy-type", &phy_type))
+ return xenon_add_phy(np, host, phy_type);
+
+ return xenon_add_phy(np, host, "emmc 5.1 phy");
+}
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
index b3f2b018fe3d..36e22bd2b8cc 100644
--- a/drivers/mmc/host/sdhci-xenon.c
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -257,6 +257,7 @@ static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
}
sdhci_set_ios(mmc, ios);
+ xenon_phy_adj(host, ios);
if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
@@ -401,7 +402,7 @@ static int xenon_probe_dt(struct platform_device *pdev)
}
priv->tuning_count = tuning_count;
- return 0;
+ return xenon_phy_parse_dt(np, host);
}
static int xenon_sdhc_prepare(struct sdhci_host *host)
@@ -483,7 +484,7 @@ static int xenon_probe(struct platform_device *pdev)
err = xenon_sdhc_prepare(host);
if (err)
- goto err_clk;
+ goto clean_phy_param;
err = sdhci_add_host(host);
if (err)
@@ -493,6 +494,8 @@ static int xenon_probe(struct platform_device *pdev)
remove_sdhc:
xenon_sdhc_unprepare(host);
+clean_phy_param:
+ xenon_clean_phy(host);
err_clk:
clk_disable_unprepare(pltfm_host->clk);
free_pltfm:
@@ -505,6 +508,8 @@ static int xenon_remove(struct platform_device *pdev)
struct sdhci_host *host = platform_get_drvdata(pdev);
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ xenon_clean_phy(host);
+
xenon_sdhc_unprepare(host);
sdhci_remove_host(host, 0);
diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
index 813585b45e8d..b29d45358de8 100644
--- a/drivers/mmc/host/sdhci-xenon.h
+++ b/drivers/mmc/host/sdhci-xenon.h
@@ -24,15 +24,32 @@
#define XENON_SYS_EXT_OP_CTRL 0x010C
#define XENON_MASK_CMD_CONFLICT_ERR BIT(8)
+#define XENON_SLOT_OP_STATUS_CTRL 0x0128
+#define XENON_TUN_CONSECUTIVE_TIMES_SHIFT 16
+#define XENON_TUN_CONSECUTIVE_TIMES_MASK 0x7
+#define XENON_TUN_CONSECUTIVE_TIMES 0x4
+#define XENON_TUNING_STEP_SHIFT 12
+#define XENON_TUNING_STEP_MASK 0xF
+#define XENON_TUNING_STEP_DIVIDER BIT(6)
+
+#define XENON_SLOT_EMMC_CTRL 0x0130
+#define XENON_ENABLE_DATA_STROBE BIT(24)
+
#define XENON_SLOT_RETUNING_REQ_CTRL 0x0144
/* retuning compatible */
#define XENON_RETUNING_COMPATIBLE 0x1
+#define XENON_SLOT_EXT_PRESENT_STATE 0x014C
+#define XENON_DLL_LOCK_STATE 0x1
+
+#define XENON_SLOT_DLL_CUR_DLY_VAL 0x0150
+
/* Tuning Parameter */
#define XENON_TMR_RETUN_NO_PRESENT 0xF
#define XENON_DEF_TUNING_COUNT 0x9
#define XENON_DEFAULT_SDCLK_FREQ 400000
+#define XENON_LOWEST_SDCLK_FREQ 100000
/* Xenon specific Mode Select value */
#define XENON_CTRL_HS200 0x5
@@ -55,6 +72,28 @@ struct xenon_priv {
* initialization completes.
*/
unsigned int init_card_type;
+
+ /*
+ * The bus_width, timing, and clock fields in below
+ * record the current ios setting of Xenon SDHC.
+ * Driver will adjust PHY setting if any change to
+ * ios affects PHY timing.
+ */
+ unsigned char bus_width;
+ unsigned char timing;
+ unsigned int clock;
+
+ int phy_type;
+ /*
+ * Contains board-specific PHY parameters
+ * passed from device tree.
+ */
+ void *phy_params;
+ struct xenon_emmc_phy_regs *emmc_phy_regs;
};
+int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
+void xenon_clean_phy(struct sdhci_host *host);
+int xenon_phy_parse_dt(struct device_node *np,
+ struct sdhci_host *host);
#endif
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH v7 07/13] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality
From: Gregory CLEMENT @ 2017-03-30 15:22 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, linux-mmc
Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Gregory CLEMENT,
Thomas Petazzoni, linux-arm-kernel, Mike Turquette, Stephen Boyd,
linux-clk, linux-kernel, Rob Herring, devicetree, Ziji Hu,
Jimmy Xu, Jisheng Zhang, Nadav Haklai, Ryan Gao, Doug Jones,
Victor Gu, Wei(SOCP) Liu, Wilson Ding, Yehuda
In-Reply-To: <cover.51071caa64e5df81264a91b9a81ed1e94f47d2c4.1490886907.git-series.gregory.clement@free-electrons.com>
From: Hu Ziji <huziji@marvell.com>
Add Xenon eMMC/SD/SDIO host controller core functionality.
Add Xenon specific initialization process.
Add Xenon specific mmc_host_ops APIs.
Add Xenon specific register definitions.
Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig.
Marvell Xenon SDHC conforms to SD Physical Layer Specification
Version 3.01 and is designed according to the guidelines provided
in the SD Host Controller Standard Specification Version 3.00.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/mmc/host/Kconfig | 8 +-
drivers/mmc/host/Makefile | 3 +-
drivers/mmc/host/sdhci-xenon.c | 541 ++++++++++++++++++++++++++++++++++-
drivers/mmc/host/sdhci-xenon.h | 60 ++++-
4 files changed, 612 insertions(+)
create mode 100644 drivers/mmc/host/sdhci-xenon.c
create mode 100644 drivers/mmc/host/sdhci-xenon.h
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index a638cd0d80be..f36f8ff9296d 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -842,3 +842,11 @@ config MMC_SDHCI_BRCMSTB
Broadcom STB SoCs.
If unsure, say Y.
+
+config MMC_SDHCI_XENON
+ tristate "Marvell Xenon eMMC/SD/SDIO SDHCI driver"
+ depends on MMC_SDHCI_PLTFM
+ help
+ This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
+ If you have a controller with this interface, say Y or M here.
+ If unsure, say N.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index bc2c2e2c68c0..014f0548ea86 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -84,3 +84,6 @@ obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o
ifeq ($(CONFIG_CB710_DEBUG),y)
CFLAGS-cb710-mmc += -DDEBUG
endif
+
+obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o
+sdhci-xenon-driver-y += sdhci-xenon.o
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
new file mode 100644
index 000000000000..b3f2b018fe3d
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -0,0 +1,541 @@
+/*
+ * Driver for Marvell Xenon SDHC as a platform device
+ *
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author: Hu Ziji <huziji@marvell.com>
+ * Date: 2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * Inspired by Jisheng Zhang <jszhang@marvell.com>
+ * Special thanks to Video BG4 project team.
+ */
+
+#include <linux/delay.h>
+#include <linux/ktime.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include "sdhci-pltfm.h"
+#include "sdhci-xenon.h"
+
+static int xenon_enable_internal_clk(struct sdhci_host *host)
+{
+ u32 reg;
+ ktime_t timeout;
+
+ reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+ reg |= SDHCI_CLOCK_INT_EN;
+ sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
+ /* Wait max 20 ms */
+ timeout = ktime_add_ms(ktime_get(), 20);
+ while (!((reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
+ & SDHCI_CLOCK_INT_STABLE)) {
+ if (ktime_after(ktime_get(), timeout)) {
+ dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n");
+ return -ETIMEDOUT;
+ }
+ usleep_range(900, 1100);
+ }
+
+ return 0;
+}
+
+/* Set SDCLK-off-while-idle */
+static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
+ unsigned char sdhc_id, bool enable)
+{
+ u32 reg;
+ u32 mask;
+
+ reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+ /* Get the bit shift basing on the SDHC index */
+ mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+
+ sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+}
+
+/* Enable/Disable the Auto Clock Gating function */
+static void xenon_set_acg(struct sdhci_host *host, bool enable)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+ if (enable)
+ reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK;
+ else
+ reg |= XENON_AUTO_CLKGATE_DISABLE_MASK;
+ sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+}
+
+/* Enable this SDHC */
+static void xenon_enable_sdhc(struct sdhci_host *host,
+ unsigned char sdhc_id)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+ reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
+ sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+
+ host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
+ /*
+ * Force to clear BUS_TEST to
+ * skip bus_test_pre and bus_test_post
+ */
+ host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
+}
+
+/* Disable this SDHC */
+static void xenon_disable_sdhc(struct sdhci_host *host,
+ unsigned char sdhc_id)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+ reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
+ sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+}
+
+/* Enable Parallel Transfer Mode */
+static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
+ unsigned char sdhc_id)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
+ reg |= BIT(sdhc_id);
+ sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
+}
+
+/* Mask command conflict error */
+static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
+ reg |= XENON_MASK_CMD_CONFLICT_ERR;
+ sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
+}
+
+static void xenon_retune_setup(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ u32 reg;
+
+ /* Disable the Re-Tuning Request functionality */
+ reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL);
+ reg &= ~XENON_RETUNING_COMPATIBLE;
+ sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL);
+
+ /* Disable the Re-tuning Interrupt */
+ reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
+ reg &= ~SDHCI_INT_RETUNE;
+ sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
+ reg = sdhci_readl(host, SDHCI_INT_ENABLE);
+ reg &= ~SDHCI_INT_RETUNE;
+ sdhci_writel(host, reg, SDHCI_INT_ENABLE);
+
+ /* Force to use Tuning Mode 1 */
+ host->tuning_mode = SDHCI_TUNING_MODE_1;
+ /* Set re-tuning period */
+ host->tuning_count = 1 << (priv->tuning_count - 1);
+}
+
+/*
+ * Operations inside struct sdhci_ops
+ */
+/* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
+static void xenon_reset_exit(struct sdhci_host *host,
+ unsigned char sdhc_id, u8 mask)
+{
+ /* Only SOFTWARE RESET ALL will clear the register setting */
+ if (!(mask & SDHCI_RESET_ALL))
+ return;
+
+ /* Disable tuning request and auto-retuning again */
+ xenon_retune_setup(host);
+
+ xenon_set_acg(host, true);
+
+ xenon_set_sdclk_off_idle(host, sdhc_id, false);
+
+ xenon_mask_cmd_conflict_err(host);
+}
+
+static void xenon_reset(struct sdhci_host *host, u8 mask)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+ sdhci_reset(host, mask);
+ xenon_reset_exit(host, priv->sdhc_id, mask);
+}
+
+/*
+ * Xenon defines different values for HS200 and HS400
+ * in Host_Control_2
+ */
+static void xenon_set_uhs_signaling(struct sdhci_host *host,
+ unsigned int timing)
+{
+ u16 ctrl_2;
+
+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ /* Select Bus Speed Mode for host */
+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+ if (timing == MMC_TIMING_MMC_HS200)
+ ctrl_2 |= XENON_CTRL_HS200;
+ else if (timing == MMC_TIMING_UHS_SDR104)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
+ else if (timing == MMC_TIMING_UHS_SDR12)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+ else if (timing == MMC_TIMING_UHS_SDR25)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+ else if (timing == MMC_TIMING_UHS_SDR50)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
+ else if ((timing == MMC_TIMING_UHS_DDR50) ||
+ (timing == MMC_TIMING_MMC_DDR52))
+ ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
+ else if (timing == MMC_TIMING_MMC_HS400)
+ ctrl_2 |= XENON_CTRL_HS400;
+ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+}
+
+static const struct sdhci_ops sdhci_xenon_ops = {
+ .set_clock = sdhci_set_clock,
+ .set_bus_width = sdhci_set_bus_width,
+ .reset = xenon_reset,
+ .set_uhs_signaling = xenon_set_uhs_signaling,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+};
+
+static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
+ .ops = &sdhci_xenon_ops,
+ .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
+ SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+};
+
+/*
+ * Xenon Specific Operations in mmc_host_ops
+ */
+static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ u32 reg;
+
+ /*
+ * HS400/HS200/eMMC HS doesn't have Preset Value register.
+ * However, sdhci_set_ios will read HS400/HS200 Preset register.
+ * Disable Preset Value register for HS400/HS200.
+ * eMMC HS with preset_enabled set will trigger a bug in
+ * get_preset_value().
+ */
+ if ((ios->timing == MMC_TIMING_MMC_HS400) ||
+ (ios->timing == MMC_TIMING_MMC_HS200) ||
+ (ios->timing == MMC_TIMING_MMC_HS)) {
+ host->preset_enabled = false;
+ host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
+ host->flags &= ~SDHCI_PV_ENABLED;
+
+ reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
+ sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+ } else {
+ host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
+ }
+
+ sdhci_set_ios(mmc, ios);
+
+ if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
+ xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
+}
+
+static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+
+ /*
+ * Before SD/SDIO set signal voltage, SD bus clock should be
+ * disabled. However, sdhci_set_clock will also disable the Internal
+ * clock in mmc_set_signal_voltage().
+ * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
+ * Thus here manually enable internal clock.
+ *
+ * After switch completes, it is unnecessary to disable internal clock,
+ * since keeping internal clock active obeys SD spec.
+ */
+ xenon_enable_internal_clk(host);
+
+ /*
+ * If Vqmmc is fixed on platform, vqmmc regulator should be unavailable.
+ * Thus SDHCI_CTRL_VDD_180 bit might not work then.
+ * Skip the standard voltage switch to avoid any issue.
+ */
+ if (PTR_ERR(mmc->supply.vqmmc) == -ENODEV)
+ return 0;
+
+ return sdhci_start_signal_voltage_switch(mmc, ios);
+}
+
+/*
+ * Update card type.
+ * priv->init_card_type will be used in PHY timing adjustment.
+ */
+static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+ /* Update card type*/
+ priv->init_card_type = card->type;
+}
+
+static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+
+ if (host->timing == MMC_TIMING_UHS_DDR50)
+ return 0;
+
+ /*
+ * Currently force Xenon driver back to support mode 1 only,
+ * even though Xenon might claim to support mode 2 or mode 3.
+ * It requires more time to test mode 2/mode 3 on more platforms.
+ */
+ if (host->tuning_mode != SDHCI_TUNING_MODE_1)
+ xenon_retune_setup(host);
+
+ return sdhci_execute_tuning(mmc, opcode);
+}
+
+static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ u32 reg;
+ u8 sdhc_id = priv->sdhc_id;
+
+ sdhci_enable_sdio_irq(mmc, enable);
+
+ if (enable) {
+ /*
+ * Set SDIO Card Inserted indication
+ * to enable detecting SDIO async irq.
+ */
+ reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
+ reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
+ sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
+ } else {
+ /* Clear SDIO Card Inserted indication */
+ reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
+ reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
+ sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
+ }
+}
+
+static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
+{
+ host->mmc_host_ops.set_ios = xenon_set_ios;
+ host->mmc_host_ops.start_signal_voltage_switch =
+ xenon_start_signal_voltage_switch;
+ host->mmc_host_ops.init_card = xenon_init_card;
+ host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
+ host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
+}
+
+/*
+ * Parse Xenon specific DT properties:
+ * sdhc-id: the index of current SDHC.
+ * Refer to XENON_SYS_CFG_INFO register
+ * tun-count: the interval between re-tuning
+ */
+static int xenon_probe_dt(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+ struct mmc_host *mmc = host->mmc;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ u32 sdhc_id, nr_sdhc;
+ u32 tuning_count;
+
+ /* Disable HS200 on Armada AP806 */
+ if (of_device_is_compatible(np, "marvell,armada-ap806-sdhci"))
+ host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
+
+ sdhc_id = 0x0;
+ if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) {
+ nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO);
+ nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK;
+ if (unlikely(sdhc_id > nr_sdhc)) {
+ dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
+ sdhc_id, nr_sdhc);
+ return -EINVAL;
+ }
+ }
+ priv->sdhc_id = sdhc_id;
+
+ tuning_count = XENON_DEF_TUNING_COUNT;
+ if (!of_property_read_u32(np, "marvell,xenon-tun-count",
+ &tuning_count)) {
+ if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) {
+ dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
+ XENON_DEF_TUNING_COUNT);
+ tuning_count = XENON_DEF_TUNING_COUNT;
+ }
+ }
+ priv->tuning_count = tuning_count;
+
+ return 0;
+}
+
+static int xenon_sdhc_prepare(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ u8 sdhc_id = priv->sdhc_id;
+
+ /* Enable SDHC */
+ xenon_enable_sdhc(host, sdhc_id);
+
+ /* Enable ACG */
+ xenon_set_acg(host, true);
+
+ /* Enable Parallel Transfer Mode */
+ xenon_enable_sdhc_parallel_tran(host, sdhc_id);
+
+ /* Disable SDCLK-Off-While-Idle before card init */
+ xenon_set_sdclk_off_idle(host, sdhc_id, false);
+
+ xenon_mask_cmd_conflict_err(host);
+
+ return 0;
+}
+
+static void xenon_sdhc_unprepare(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ u8 sdhc_id = priv->sdhc_id;
+
+ /* disable SDHC */
+ xenon_disable_sdhc(host, sdhc_id);
+}
+
+static int xenon_probe(struct platform_device *pdev)
+{
+ struct sdhci_pltfm_host *pltfm_host;
+ struct sdhci_host *host;
+ struct xenon_priv *priv;
+ int err;
+
+ host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
+ sizeof(struct xenon_priv));
+ if (IS_ERR(host))
+ return PTR_ERR(host);
+
+ pltfm_host = sdhci_priv(host);
+ priv = sdhci_pltfm_priv(pltfm_host);
+
+ /*
+ * Link Xenon specific mmc_host_ops function,
+ * to replace standard ones in sdhci_ops.
+ */
+ xenon_replace_mmc_host_ops(host);
+
+ pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(pltfm_host->clk)) {
+ err = PTR_ERR(pltfm_host->clk);
+ dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err);
+ goto free_pltfm;
+ }
+ err = clk_prepare_enable(pltfm_host->clk);
+ if (err)
+ goto free_pltfm;
+
+ err = mmc_of_parse(host->mmc);
+ if (err)
+ goto err_clk;
+
+ sdhci_get_of_property(pdev);
+
+ xenon_set_acg(host, false);
+
+ /* Xenon specific dt parse */
+ err = xenon_probe_dt(pdev);
+ if (err)
+ goto err_clk;
+
+ err = xenon_sdhc_prepare(host);
+ if (err)
+ goto err_clk;
+
+ err = sdhci_add_host(host);
+ if (err)
+ goto remove_sdhc;
+
+ return 0;
+
+remove_sdhc:
+ xenon_sdhc_unprepare(host);
+err_clk:
+ clk_disable_unprepare(pltfm_host->clk);
+free_pltfm:
+ sdhci_pltfm_free(pdev);
+ return err;
+}
+
+static int xenon_remove(struct platform_device *pdev)
+{
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+ xenon_sdhc_unprepare(host);
+
+ sdhci_remove_host(host, 0);
+
+ clk_disable_unprepare(pltfm_host->clk);
+
+ sdhci_pltfm_free(pdev);
+
+ return 0;
+}
+
+static const struct of_device_id sdhci_xenon_dt_ids[] = {
+ { .compatible = "marvell,armada-ap806-sdhci",},
+ { .compatible = "marvell,armada-cp110-sdhci",},
+ { .compatible = "marvell,armada-3700-sdhci",},
+ {}
+};
+MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
+
+static struct platform_driver sdhci_xenon_driver = {
+ .driver = {
+ .name = "xenon-sdhci",
+ .of_match_table = sdhci_xenon_dt_ids,
+ .pm = &sdhci_pltfm_pmops,
+ },
+ .probe = xenon_probe,
+ .remove = xenon_remove,
+};
+
+module_platform_driver(sdhci_xenon_driver);
+
+MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
+MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
new file mode 100644
index 000000000000..813585b45e8d
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author: Hu Ziji <huziji@marvell.com>
+ * Date: 2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ */
+#ifndef SDHCI_XENON_H_
+#define SDHCI_XENON_H_
+
+/* Register Offset of Xenon SDHC self-defined register */
+#define XENON_SYS_CFG_INFO 0x0104
+#define XENON_SLOT_TYPE_SDIO_SHIFT 24
+#define XENON_NR_SUPPORTED_SLOT_MASK 0x7
+
+#define XENON_SYS_OP_CTRL 0x0108
+#define XENON_AUTO_CLKGATE_DISABLE_MASK BIT(20)
+#define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT 8
+#define XENON_SLOT_ENABLE_SHIFT 0
+
+#define XENON_SYS_EXT_OP_CTRL 0x010C
+#define XENON_MASK_CMD_CONFLICT_ERR BIT(8)
+
+#define XENON_SLOT_RETUNING_REQ_CTRL 0x0144
+/* retuning compatible */
+#define XENON_RETUNING_COMPATIBLE 0x1
+
+/* Tuning Parameter */
+#define XENON_TMR_RETUN_NO_PRESENT 0xF
+#define XENON_DEF_TUNING_COUNT 0x9
+
+#define XENON_DEFAULT_SDCLK_FREQ 400000
+
+/* Xenon specific Mode Select value */
+#define XENON_CTRL_HS200 0x5
+#define XENON_CTRL_HS400 0x6
+
+struct xenon_priv {
+ unsigned char tuning_count;
+ /* idx of SDHC */
+ u8 sdhc_id;
+
+ /*
+ * eMMC/SD/SDIO require different register settings.
+ * Xenon driver has to recognize card type
+ * before mmc_host->card is not available.
+ * This field records the card type during init.
+ * It is updated in xenon_init_card().
+ *
+ * It is only valid during initialization after it is updated.
+ * Do not access this variable in normal transfers after
+ * initialization completes.
+ */
+ unsigned int init_card_type;
+};
+
+#endif
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH v7 06/13] dt: bindings: Add bindings for Marvell Xenon SD Host Controller
From: Gregory CLEMENT @ 2017-03-30 15:22 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, linux-mmc
Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Gregory CLEMENT,
Thomas Petazzoni, linux-arm-kernel, Mike Turquette, Stephen Boyd,
linux-clk, linux-kernel, Rob Herring, devicetree, Ziji Hu,
Jimmy Xu, Jisheng Zhang, Nadav Haklai, Ryan Gao, Doug Jones,
Victor Gu, Wei(SOCP) Liu, Wilson Ding, Yehuda
In-Reply-To: <cover.51071caa64e5df81264a91b9a81ed1e94f47d2c4.1490886907.git-series.gregory.clement@free-electrons.com>
From: Hu Ziji <huziji@marvell.com>
Marvell Xenon SDHC can support eMMC/SD/SDIO.
Add Xenon-specific properties.
Also add properties for Xenon PHY setting.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 170 +++++++-
1 file changed, 170 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
new file mode 100644
index 000000000000..b878a1e305af
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
@@ -0,0 +1,170 @@
+Marvell Xenon SDHCI Controller device tree bindings
+This file documents differences between the core mmc properties
+described by mmc.txt and the properties used by the Xenon implementation.
+
+Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
+Each SDHC is independent and owns independent resources, such as register sets,
+clock and PHY.
+Each SDHC should have an independent device tree node.
+
+Required Properties:
+- compatible: should be one of the following
+ - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
+ Must provide a second register area and marvell,pad-type.
+ - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
+ - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
+
+- clocks:
+ Array of clocks required for SDHC.
+ Require at least input clock for Xenon IP core.
+
+- clock-names:
+ Array of names corresponding to clocks property.
+ The input clock for Xenon IP core should be named as "core".
+
+- reg:
+ * For "marvell,armada-3700-sdhci", two register areas.
+ The first one for Xenon IP register. The second one for the Armada 3700 SoC
+ PHY PAD Voltage Control register.
+ Please follow the examples with compatible "marvell,armada-3700-sdhci"
+ in below.
+ Please also check property marvell,pad-type in below.
+
+ * For other compatible strings, one register area for Xenon IP.
+
+Optional Properties:
+- marvell,xenon-sdhc-id:
+ Indicate the corresponding bit index of current SDHC in
+ SDHC System Operation Control Register Bit[7:0].
+ Set/clear the corresponding bit to enable/disable current SDHC.
+ If Xenon IP contains only one SDHC, this property is optional.
+
+- marvell,xenon-phy-type:
+ Xenon support multiple types of PHYs.
+ To select eMMC 5.1 PHY, set:
+ marvell,xenon-phy-type = "emmc 5.1 phy"
+ eMMC 5.1 PHY is the default choice if this property is not provided.
+ To select eMMC 5.0 PHY, set:
+ marvell,xenon-phy-type = "emmc 5.0 phy"
+
+ All those types of PHYs can support eMMC, SD and SDIO.
+ Please note that this property only presents the type of PHY.
+ It doesn't stand for the entire SDHC type or property.
+ For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only
+ supports eMMC 5.1.
+
+- marvell,xenon-phy-znr:
+ Set PHY ZNR value.
+ Only available for eMMC PHY.
+ Valid range = [0:0x1F].
+ ZNR is set as 0xF by default if this property is not provided.
+
+- marvell,xenon-phy-zpr:
+ Set PHY ZPR value.
+ Only available for eMMC PHY.
+ Valid range = [0:0x1F].
+ ZPR is set as 0xF by default if this property is not provided.
+
+- marvell,xenon-phy-nr-success-tun:
+ Set the number of required consecutive successful sampling points
+ used to identify a valid sampling window, in tuning process.
+ Valid range = [1:7].
+ Set as 0x4 by default if this property is not provided.
+
+- marvell,xenon-phy-tun-step-divider:
+ Set the divider for calculating TUN_STEP.
+ Set as 64 by default if this property is not provided.
+
+- marvell,xenon-phy-slow-mode:
+ If this property is selected, transfers will bypass PHY.
+ Only available when bus frequency lower than 55MHz in SDR mode.
+ Disabled by default. Please only try this property if timing issues
+ always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
+ SD Default Speed and HS mode and eMMC legacy speed mode.
+
+- marvell,xenon-tun-count:
+ Xenon SDHC SoC usually doesn't provide re-tuning counter in
+ Capabilities Register 3 Bit[11:8].
+ This property provides the re-tuning counter.
+ If this property is not set, default re-tuning counter will
+ be set as 0x9 in driver.
+
+- marvell,pad-type:
+ Type of Armada 3700 SoC PHY PAD Voltage Controller register.
+ Only valid when "marvell,armada-3700-sdhci" is selected.
+ Two types: "sd" and "fixed-1-8v".
+ If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning and is
+ switched to 1.8V when later in higher speed mode.
+ If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for eMMC.
+ Please follow the examples with compatible "marvell,armada-3700-sdhci"
+ in below.
+
+Example:
+- For eMMC:
+
+ sdhci@aa0000 {
+ compatible = "marvell,armada-ap806-sdhci";
+ reg = <0xaa0000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
+ clocks = <&emmc_clk>;
+ clock-names = "core";
+ bus-width = <4>;
+ marvell,xenon-phy-slow-mode;
+ marvell,xenon-tun-count = <11>;
+ non-removable;
+ no-sd;
+ no-sdio;
+
+ /* Vmmc and Vqmmc are both fixed */
+ };
+
+- For SD/SDIO:
+
+ sdhci@ab0000 {
+ compatible = "marvell,armada-cp110-sdhci";
+ reg = <0xab0000 0x1000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
+ vqmmc-supply = <&sd_vqmmc_regulator>;
+ vmmc-supply = <&sd_vmmc_regulator>;
+ clocks = <&sdclk>;
+ clock-names = "core";
+ bus-width = <4>;
+ marvell,xenon-tun-count = <9>;
+ };
+
+- For eMMC with compatible "marvell,armada-3700-sdhci":
+
+ sdhci@aa0000 {
+ compatible = "marvell,armada-3700-sdhci";
+ reg = <0xaa0000 0x1000>,
+ <phy_addr 0x4>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
+ clocks = <&emmcclk>;
+ clock-names = "core";
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sd;
+ no-sdio;
+
+ /* Vmmc and Vqmmc are both fixed */
+
+ marvell,pad-type = "fixed-1-8v";
+ };
+
+- For SD/SDIO with compatible "marvell,armada-3700-sdhci":
+
+ sdhci@ab0000 {
+ compatible = "marvell,armada-3700-sdhci";
+ reg = <0xab0000 0x1000>,
+ <phy_addr 0x4>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
+ vqmmc-supply = <&sd_regulator>;
+ /* Vmmc is fixed */
+ clocks = <&sdclk>;
+ clock-names = "core";
+ bus-width = <4>;
+
+ marvell,pad-type = "sd";
+ };
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH v7 05/13] mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.c
From: Gregory CLEMENT @ 2017-03-30 15:22 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, linux-mmc
Cc: Jimmy Xu, Andrew Lunn, Mike Turquette, Nadav Haklai, Ziji Hu,
Victor Gu, Doug Jones, linux-clk, Jisheng Zhang, Yehuda Yitschak,
Marcin Wojtas, Kostya Porotchkin, Hanna Hawa,
Sebastian Hesselbarth, devicetree, Jason Cooper, Rob Herring,
Ryan Gao, Gregory CLEMENT, Wei(SOCP) Liu, linux-arm-kernel,
Thomas Petazzoni, Stephen Boyd, linux-kernel, Wilson
In-Reply-To: <cover.51071caa64e5df81264a91b9a81ed1e94f47d2c4.1490886907.git-series.gregory.clement@free-electrons.com>
From: Hu Ziji <huziji@marvell.com>
Export sdhci_enable_sdio_irq() from sdhci.c.
Thus vendor SDHC driver can implement its specific SDIO irq
control.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index cc5bb9fb7706..5e090227c6c7 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1832,7 +1832,7 @@ static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
}
}
-static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
{
struct sdhci_host *host = mmc_priv(mmc);
unsigned long flags;
@@ -1846,6 +1846,7 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
sdhci_enable_sdio_irq_nolock(host, enable);
spin_unlock_irqrestore(&host->lock, flags);
}
+EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
struct mmc_ios *ios)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index a741d8da6227..78437f82609e 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -706,6 +706,7 @@ int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
struct mmc_ios *ios);
+void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
#ifdef CONFIG_PM
int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH v7 04/13] mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c
From: Gregory CLEMENT @ 2017-03-30 15:22 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, linux-mmc
Cc: Jimmy Xu, Andrew Lunn, Mike Turquette, Nadav Haklai, Ziji Hu,
Victor Gu, Doug Jones, linux-clk, Jisheng Zhang, Yehuda Yitschak,
Marcin Wojtas, Kostya Porotchkin, Hanna Hawa,
Sebastian Hesselbarth, devicetree, Jason Cooper, Rob Herring,
Ryan Gao, Gregory CLEMENT, Wei(SOCP) Liu, linux-arm-kernel,
Thomas Petazzoni, Stephen Boyd, linux-kernel, Wilson
In-Reply-To: <cover.51071caa64e5df81264a91b9a81ed1e94f47d2c4.1490886907.git-series.gregory.clement@free-electrons.com>
From: Hu Ziji <huziji@marvell.com>
Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci.c | 5 +++--
drivers/mmc/host/sdhci.h | 2 ++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index d5bca886419d..cc5bb9fb7706 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1847,8 +1847,8 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
spin_unlock_irqrestore(&host->lock, flags);
}
-static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
- struct mmc_ios *ios)
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
u16 ctrl;
@@ -1940,6 +1940,7 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
return 0;
}
}
+EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
static int sdhci_card_busy(struct mmc_host *mmc)
{
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index b0cb805937c0..a741d8da6227 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -704,6 +704,8 @@ void sdhci_reset(struct sdhci_host *host, u8 mask);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios);
#ifdef CONFIG_PM
int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH v7 03/13] mmc: sdhci: Export sdhci_set_ios() from sdhci.c
From: Gregory CLEMENT @ 2017-03-30 15:22 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, linux-mmc
Cc: Jimmy Xu, Andrew Lunn, Mike Turquette, Nadav Haklai, Ziji Hu,
Victor Gu, Doug Jones, linux-clk, Jisheng Zhang, Yehuda Yitschak,
Marcin Wojtas, Kostya Porotchkin, Hanna Hawa,
Sebastian Hesselbarth, devicetree, Jason Cooper, Rob Herring,
Ryan Gao, Gregory CLEMENT, Wei(SOCP) Liu, linux-arm-kernel,
Thomas Petazzoni, Stephen Boyd, linux-kernel, Wilson
In-Reply-To: <cover.51071caa64e5df81264a91b9a81ed1e94f47d2c4.1490886907.git-series.gregory.clement@free-electrons.com>
From: Hu Ziji <huziji@marvell.com>
Export sdhci_set_ios() in sdhci.c.
Thus vendor sdhci driver can implement its own set_ios() routine.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 811981394e6e..d5bca886419d 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1583,7 +1583,7 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
}
EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
-static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
u8 ctrl;
@@ -1738,6 +1738,7 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
mmiowb();
}
+EXPORT_SYMBOL_GPL(sdhci_set_ios);
static int sdhci_get_cd(struct mmc_host *mmc)
{
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index fdb5d7e1911f..b0cb805937c0 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -703,6 +703,7 @@ void sdhci_set_bus_width(struct sdhci_host *host, int width);
void sdhci_reset(struct sdhci_host *host, u8 mask);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
+void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
#ifdef CONFIG_PM
int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH v7 02/13] clk: apn806: Turn the eMMC clock as optional for dts backwards compatible
From: Gregory CLEMENT @ 2017-03-30 15:22 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, linux-mmc
Cc: Jimmy Xu, Andrew Lunn, Mike Turquette, Nadav Haklai, Ziji Hu,
Victor Gu, Doug Jones, linux-clk, Jisheng Zhang, Yehuda Yitschak,
Marcin Wojtas, Kostya Porotchkin, Hanna Hawa,
Sebastian Hesselbarth, devicetree, Jason Cooper, Rob Herring,
Ryan Gao, Gregory CLEMENT, Wei(SOCP) Liu, linux-arm-kernel,
Thomas Petazzoni, Stephen Boyd, linux-kernel, Wilson
In-Reply-To: <cover.51071caa64e5df81264a91b9a81ed1e94f47d2c4.1490886907.git-series.gregory.clement@free-electrons.com>
First version of the binding didn't have the eMMC clock. This patch
allows to not registering the eMMC clock if it is not present in the
device tree. Then the device tree can be backwards compatible.
Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/clk/mvebu/ap806-system-controller.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c
index 901d89c4ab4a..103fe18a3c29 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -136,13 +136,19 @@ static int ap806_syscon_clk_probe(struct platform_device *pdev)
}
/* eMMC Clock is fixed clock divided by 3 */
- of_property_read_string_index(np, "clock-output-names",
- 4, &name);
- ap806_clks[4] = clk_register_fixed_factor(NULL, name, fixedclk_name,
- 0, 1, 3);
- if (IS_ERR(ap806_clks[4])) {
- ret = PTR_ERR(ap806_clks[4]);
- goto fail4;
+ if (of_property_read_string_index(np, "clock-output-names",
+ 4, &name)) {
+ ap806_clk_data.clk_num--;
+ dev_warn(&pdev->dev,
+ "eMMC clock mising: update the device tree!\n");
+ } else {
+ ap806_clks[4] = clk_register_fixed_factor(NULL, name,
+ fixedclk_name,
+ 0, 1, 3);
+ if (IS_ERR(ap806_clks[4])) {
+ ret = PTR_ERR(ap806_clks[4]);
+ goto fail4;
+ }
}
of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH v7 01/13] clk: apn806: Add eMMC clock to system controller driver
From: Gregory CLEMENT @ 2017-03-30 15:22 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, linux-mmc
Cc: Jimmy Xu, Andrew Lunn, Mike Turquette, Nadav Haklai, Ziji Hu,
Victor Gu, Doug Jones, linux-clk, Jisheng Zhang, Yehuda Yitschak,
Marcin Wojtas, Kostya Porotchkin, Hanna Hawa,
Sebastian Hesselbarth, devicetree, Jason Cooper, Russell King,
Rob Herring, Ryan Gao, Gregory CLEMENT, Wei(SOCP) Liu,
linux-arm-kernel, Thomas Petazzoni, Stephen Boyd
In-Reply-To: <cover.51071caa64e5df81264a91b9a81ed1e94f47d2c4.1490886907.git-series.gregory.clement@free-electrons.com>
From: Konstantin Porotchkin <kostap@marvell.com>
Add fixed clock of 400MHz to system controller driver. This clock is
used as SD/eMMC clock source.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Omri Itach <omrii@marvell.com>
Reviewed-by: Hanna Hawa <hannah@marvell.com>
[fixed up conflicts, added error handling --rmk]
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 3 ++-
drivers/clk/mvebu/ap806-system-controller.c | 15 ++++++++++++++-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index a749ba2edec4..5019c8f4acd0 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -235,7 +235,8 @@
#clock-cells = <1>;
clock-output-names = "ap-cpu-cluster-0",
"ap-cpu-cluster-1",
- "ap-fixed", "ap-mss";
+ "ap-fixed", "ap-mss",
+ "ap-emmc";
reg = <0x6f4000 0x1000>;
};
};
diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c
index f17702107ac5..901d89c4ab4a 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -23,7 +23,7 @@
#define AP806_SAR_REG 0x400
#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f
-#define AP806_CLK_NUM 4
+#define AP806_CLK_NUM 5
static struct clk *ap806_clks[AP806_CLK_NUM];
@@ -135,6 +135,17 @@ static int ap806_syscon_clk_probe(struct platform_device *pdev)
goto fail3;
}
+ /* eMMC Clock is fixed clock divided by 3 */
+ of_property_read_string_index(np, "clock-output-names",
+ 4, &name);
+ ap806_clks[4] = clk_register_fixed_factor(NULL, name, fixedclk_name,
+ 0, 1, 3);
+ if (IS_ERR(ap806_clks[4])) {
+ ret = PTR_ERR(ap806_clks[4]);
+ goto fail4;
+ }
+
+ of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
if (ret)
goto fail_clk_add;
@@ -142,6 +153,8 @@ static int ap806_syscon_clk_probe(struct platform_device *pdev)
return 0;
fail_clk_add:
+ clk_unregister_fixed_factor(ap806_clks[4]);
+fail4:
clk_unregister_fixed_factor(ap806_clks[3]);
fail3:
clk_unregister_fixed_rate(ap806_clks[2]);
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH v7 00/13] mmc: Add support to Marvell Xenon SD Host Controller
From: Gregory CLEMENT @ 2017-03-30 15:22 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, linux-mmc
Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Gregory CLEMENT,
Thomas Petazzoni, linux-arm-kernel, Mike Turquette, Stephen Boyd,
linux-clk, linux-kernel, Rob Herring, devicetree, Ziji Hu,
Jimmy Xu, Jisheng Zhang, Nadav Haklai, Ryan Gao, Doug Jones,
Victor Gu, Wei(SOCP) Liu, Wilson Ding, Yehuda
Hello,
This the seventh version of the series adding support for the SDHCI
Xenon controller. It can be currently found on the Armada 37xx and the
Armada 7K/8K but will be also used in more Marvell SoC (and not only
the mvebu ones actually).
v6->v7:
- Add comments on vqmmc and vmmc in examples in dt binding doc.
- Fix all the issues pointed out by Ulf and Adrian:
- Align the prefix of function and variable names.
- Replace the if-else with switch statements when checking MMC_TIMING_*
- Remove the spinlocks in set_ios.
- Optimize the delay loop as Adrian patch does.
- Add release of phy params structures
- Add check of Vqmmc supply in Xenon signal voltage switch. If Vqmmc
regulator doesn't exist, skip standard SD signal voltage regulator
switch process.
- Remove parse of child node mmc-card. Wait for a better solution.
v5->v6:
- Add a generic "mmc-card" parse in core layer.
- Fix the spelling issues in Xenon dt binding doc and drivers.
- Remove descriptions to common mmc properties from Xenon dt binding
doc.
- Split compatible string "marvell,armada-8k-sdhci" into
"marvell,armada-ap806-sdhci" and "marvell,armada-cp110-sdhci".
- Also updates the example in Xenon dt binding doc.
- Remove unnecessary dependency on MMC_SDHCI from Xenon entry in
Kconfig.
- Move Xenon specific dt parse into a separate function.
- Adjust warnings and condition check in Xenon PHY setting, to remove
fragile hs200->hs400/hs400->hs200 sequence check function.
- Enable PHY Slow Mode in MMC_TIMING_LEGACY timing if PHY Slow Mode is
required in dts.
- Add a patch allowing dts backwards compatible for the clock
v4->v5:
- Remove the patch to export sdhci_execute_tuning(). It is already
exported in v4.10.
- Introduce a patch adding a missing clock for the sdhci controller
present on the CP master for A7K/A8K. There is no build dependency
but obviously this patch is need to use the sdhci controller present
on the CP part.
- Adjust Xenon return setup, to avoid being overwritten by
sdhci_add_host().
- Change Xenon register definition prefix to "XENON_".
- Fix typos in Xenon driver and dt-binding docs.
- Change compatible string "marvell,armada-7000-sdhci" to
"marvell,armada-8k-sdhci". Actually the Armada 7K SoCs are a subset
of the Armada 8K SoCs. Moreover, the use of the '000' is not
consistent with all the other compatible string already used for the
Armada 7K/8K family.
- Added the Tested-by from Russell King on an Armada 8K based board.
v3 -> v4:
For this version a few change have been done:
- fixes 2 bug reported by kbuild-bot
- remove extra of_node_put()
- convert 0 in false for function returning boolean
- add a device tree node for the sdhci controller present on the CP
master for A7K/A8K. It also led to rename the sdhci0 node on AP to
ap_sdhci0 to make a distinction with the one present on CP master.
v2 -> v3
I think that now most (if not all) the remarks had been taking into
account since the second version. According to Ziji Hu, here are the
following changes:
" Changes in V3:
Adjust and improve Xenon DT bindings. Move some caps setting from driver into
DT. Use mmc-card sub-node to represent eMMC type.
Remove PHY Sampling Fixed Delay Line scan in lower speed mode.
Improve Xenon probe and ->init_card() functions.
Export sdhci_enable_sdio_irq() and implement own SDIO IRQ control.
Split PHY patch into two smaller patches.
Temporarily remove AXI clock before its implementation is improved."
Besides this changes I also
- Removed the sdhci-xenon-phy.h and moved its content in the
shc-xenon-phy.c file.
- Fixed the tuning-count usage
- Managed the error case for clk_prepare_enable
For the record the change from v1 was:
" Changes in V2:
rebase on v4.9-rc2.
Re-write Xenon bindings. Ajust Xenon DT property naming.
Add a new DT property to indicate eMMC card type, instead of using
variable card_candidate.
Clear quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 in Xenon platform data
Add support to HS400 retuning."
Thanks,
Gregory
Gregory CLEMENT (4):
clk: apn806: Turn the eMMC clock as optional for dts backwards compatible
arm64: dts: marvell: add eMMC support for Armada 37xx
arm64: dts: marvell: add sdhci support for Armada 7K/8K
arm64: configs: enable SDHCI driver for Xenon
Hu Ziji (8):
mmc: sdhci: Export sdhci_set_ios() from sdhci.c
mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c
mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.c
dt: bindings: Add bindings for Marvell Xenon SD Host Controller
mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality
mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC
mmc: sdhci-xenon: Add SoC PHY PAD voltage control
MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers
Konstantin Porotchkin (1):
clk: apn806: Add eMMC clock to system controller driver
Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 170 +-
MAINTAINERS | 7 +-
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 9 +-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +-
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 +-
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 12 +-
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 14 +-
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 11 +-
arch/arm64/configs/defconfig | 1 +-
drivers/clk/mvebu/ap806-system-controller.c | 21 +-
drivers/mmc/host/Kconfig | 8 +-
drivers/mmc/host/Makefile | 3 +-
drivers/mmc/host/sdhci-xenon-phy.c | 835 +++++++-
drivers/mmc/host/sdhci-xenon.c | 548 +++++-
drivers/mmc/host/sdhci-xenon.h | 101 +-
drivers/mmc/host/sdhci.c | 11 +-
drivers/mmc/host/sdhci.h | 4 +-
17 files changed, 1774 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c
create mode 100644 drivers/mmc/host/sdhci-xenon.c
create mode 100644 drivers/mmc/host/sdhci-xenon.h
base-commit: a645cc1df4ff41ba54a2fb839962b8ff142121d9
--
git-series 0.9.1
^ permalink raw reply
* [PATCH v4 5/5] ARM: configs: stm32: Add watchdog support in STM32 defconfig
From: Yannick Fertre @ 2017-03-30 15:15 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Alexandre TORGUE,
Benjamin Gaignard, Yannick Fertre, Maxime Coquelin
Cc: linux-watchdog, linux-kernel, Philippe Cornu, Gabriel FERNANDEZ,
devicetree, linux-arm-kernel
In-Reply-To: <1490886926-20585-1-git-send-email-yannick.fertre@st.com>
This patch adds STM32 watchdog support in stm32_defconfig file
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
arch/arm/configs/stm32_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 29ac5a4..1fb901c 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -51,6 +51,7 @@ CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_STM32F4=y
# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_USB_SUPPORT is not set
--
1.9.1
^ permalink raw reply related
* [PATCH v4 4/5] ARM: dts: stm32: Add watchdog support for STM32F429 eval board
From: Yannick Fertre @ 2017-03-30 15:15 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Alexandre TORGUE,
Benjamin Gaignard, Yannick Fertre, Maxime Coquelin
Cc: linux-watchdog, linux-kernel, Philippe Cornu, Gabriel FERNANDEZ,
devicetree, linux-arm-kernel
In-Reply-To: <1490886926-20585-1-git-send-email-yannick.fertre@st.com>
This patch adds watchdog support for STM32x9I-Eval board.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
arch/arm/boot/dts/stm32429i-eval.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 6e4b42a..6eaa382 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -144,6 +144,10 @@
};
};
+&iwdg {
+ status = "okay";
+};
+
&adc {
pinctrl-names = "default";
pinctrl-0 = <&adc3_in8_pin>;
--
1.9.1
^ permalink raw reply related
* [PATCH v4 3/5] ARM: dts: stm32: Add watchdog support for STM32F429 SoC
From: Yannick Fertre @ 2017-03-30 15:15 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Alexandre TORGUE,
Benjamin Gaignard, Yannick Fertre, Maxime Coquelin
Cc: devicetree, linux-watchdog, Philippe Cornu, linux-kernel,
Gabriel FERNANDEZ, linux-arm-kernel
In-Reply-To: <1490886926-20585-1-git-send-email-yannick.fertre@st.com>
Add watchdog into DT for stm32f429 family.
Signed-off-by: Yannick FERTRE <yannick.fertre@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 89327d6..d84dd44 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -64,7 +64,7 @@
clock-frequency = <32768>;
};
- clk-lsi {
+ clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
@@ -306,6 +306,13 @@
status = "disabled";
};
+ iwdg: watchdog@40003000 {
+ compatible = "st,stm32-iwdg";
+ reg = <0x40003000 0x400>;
+ clocks = <&clk_lsi>;
+ status = "disabled";
+ };
+
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
--
1.9.1
^ permalink raw reply related
* [PATCH v4 2/5] drivers: watchdog: Add STM32 IWDG driver
From: Yannick Fertre @ 2017-03-30 15:15 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Alexandre TORGUE,
Benjamin Gaignard, Yannick Fertre, Maxime Coquelin
Cc: devicetree, linux-watchdog, Philippe Cornu, linux-kernel,
Gabriel FERNANDEZ, linux-arm-kernel
In-Reply-To: <1490886926-20585-1-git-send-email-yannick.fertre@st.com>
This patch adds IWDG (Independent WatchDoG) support for STM32 platform.
Signed-off-by: Yannick FERTRE <yannick.fertre@st.com>
---
drivers/watchdog/Kconfig | 12 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/stm32_iwdg.c | 260 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 273 insertions(+)
create mode 100644 drivers/watchdog/stm32_iwdg.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 52a70ee..d014deb 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -744,6 +744,18 @@ config ZX2967_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called zx2967_wdt.
+config STM32_WATCHDOG
+ tristate "STM32 Independent WatchDoG (IWDG) support"
+ depends on ARCH_STM32
+ select WATCHDOG_CORE
+ default y
+ help
+ Say Y here to include support for the watchdog timer
+ in stm32 SoCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called stm32_iwdg.
+
# AVR32 Architecture
config AT32AP700X_WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index a2126e2..a35e423 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_ATLAS7_WATCHDOG) += atlas7_wdt.o
obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
obj-$(CONFIG_ZX2967_WATCHDOG) += zx2967_wdt.o
+obj-$(CONFIG_STM32_WATCHDOG) += stm32_iwdg.o
# AVR32 Architecture
obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
diff --git a/drivers/watchdog/stm32_iwdg.c b/drivers/watchdog/stm32_iwdg.c
new file mode 100644
index 0000000..629c305
--- /dev/null
+++ b/drivers/watchdog/stm32_iwdg.c
@@ -0,0 +1,260 @@
+/*
+ * Driver for STM32 Independent Watchdog
+ *
+ * Copyright (C) Yannick Fertre 2017
+ * Author: Yannick Fertre <yannick.fertre@st.com>
+ *
+ * This driver is based on tegra_wdt.c
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/watchdog.h>
+
+/* watchdog trigger timeout, in seconds */
+#define WDT_MIN_TIMEOUT 1
+#define WDT_MAX_TIMEOUT 32
+#define WDT_DEFAULT_TIMEOUT 30
+
+/* IWDG registers */
+#define IWDG_KR 0x00 /* Key register */
+#define IWDG_PR 0x04 /* Prescaler Register */
+#define IWDG_RLR 0x08 /* ReLoad Register */
+#define IWDG_SR 0x0C /* Status Register */
+#define IWDG_WINR 0x10 /* Windows Register */
+
+/* IWDG_KR register bit mask */
+#define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
+#define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
+#define KR_KEY_EWA 0x5555 /* write access enable */
+#define KR_KEY_DWA 0x0000 /* write access disable */
+
+/* IWDG_PR register bit values */
+#define PR_4 0x00 /* prescaler set to 4 */
+#define PR_8 0x01 /* prescaler set to 8 */
+#define PR_16 0x02 /* prescaler set to 16 */
+#define PR_32 0x03 /* prescaler set to 32 */
+#define PR_64 0x04 /* prescaler set to 64 */
+#define PR_128 0x05 /* prescaler set to 128 */
+#define PR_256 0x06 /* prescaler set to 256 */
+
+/* IWDG_RLR register values */
+#define RLR_MAX 0xFFF /* max value supported by reload register */
+
+/* IWDG_SR register bit mask */
+#define FLAG_PVU BIT(0) /* Watchdog prescaler value update */
+#define FLAG_RVU BIT(1) /* Watchdog counter reload value update */
+
+/* set timeout to 100000 us */
+#define TIMEOUT_US 100000
+#define SLEEP_US 1000
+
+struct stm32_iwdg {
+ struct watchdog_device wdd;
+ void __iomem *regs;
+ struct clk *clk;
+ unsigned int rate;
+};
+
+static inline u32 reg_read(void __iomem *base, u32 reg)
+{
+ return readl_relaxed(base + reg);
+}
+
+static inline void reg_write(void __iomem *base, u32 reg, u32 val)
+{
+ writel_relaxed(val, base + reg);
+}
+
+static int stm32_iwdg_start(struct watchdog_device *wdd)
+{
+ struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
+ u32 val = FLAG_PVU | FLAG_RVU;
+ u32 reload;
+ int ret;
+
+ dev_dbg(wdd->parent, "%s\n", __func__);
+
+ /* enable watchdog */
+ reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
+ reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
+
+ /* prescaler fixed to 256 */
+ reload = (wdd->timeout * wdt->rate) / 256;
+ if (reload > RLR_MAX + 1)
+ reload = RLR_MAX + 1;
+
+ /* set prescaler & reload registers */
+ reg_write(wdt->regs, IWDG_PR, PR_256); /* prescaler fix to 256 */
+ reg_write(wdt->regs, IWDG_RLR, reload - 1);
+
+ /* wait for the registers to be updated (max 100ms) */
+ ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, val,
+ !(val & (FLAG_PVU | FLAG_RVU)),
+ SLEEP_US, TIMEOUT_US);
+ if (ret) {
+ dev_err(wdd->parent,
+ "Fail to set prescaler or reload registers\n");
+ return ret;
+ }
+
+ /* reload watchdog */
+ reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
+
+ return 0;
+}
+
+static int stm32_iwdg_ping(struct watchdog_device *wdd)
+{
+ struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
+
+ dev_dbg(wdd->parent, "%s\n", __func__);
+
+ /* reload watchdog */
+ reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
+
+ return 0;
+}
+
+static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
+ unsigned int timeout)
+{
+ dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
+
+ wdd->timeout = timeout;
+
+ if (watchdog_active(wdd))
+ return stm32_iwdg_start(wdd);
+
+ return 0;
+}
+
+static const struct watchdog_info stm32_iwdg_info = {
+ .options = WDIOF_SETTIMEOUT |
+ WDIOF_MAGICCLOSE |
+ WDIOF_KEEPALIVEPING,
+ .identity = "STM32 Independent Watchdog",
+};
+
+static struct watchdog_ops stm32_iwdg_ops = {
+ .owner = THIS_MODULE,
+ .start = stm32_iwdg_start,
+ .ping = stm32_iwdg_ping,
+ .set_timeout = stm32_iwdg_set_timeout,
+};
+
+static int stm32_iwdg_probe(struct platform_device *pdev)
+{
+ struct watchdog_device *wdd;
+ struct stm32_iwdg *wdt;
+ struct resource *res;
+ void __iomem *regs;
+ struct clk *clk;
+ int ret;
+
+ /* This is the timer base. */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(regs)) {
+ dev_err(&pdev->dev, "Could not get resource\n");
+ return PTR_ERR(regs);
+ }
+
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "Unable to get clock\n");
+ return PTR_ERR(clk);
+ }
+
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ dev_err(&pdev->dev, "Unable to prepare clock %p\n", clk);
+ return ret;
+ }
+
+ /*
+ * Allocate our watchdog driver data, which has the
+ * struct watchdog_device nested within it.
+ */
+ wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
+ if (!wdt) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ /* Initialize struct stm32_iwdg. */
+ wdt->regs = regs;
+ wdt->clk = clk;
+ wdt->rate = clk_get_rate(clk);
+
+ /* Initialize struct watchdog_device. */
+ wdd = &wdt->wdd;
+ wdd->info = &stm32_iwdg_info;
+ wdd->ops = &stm32_iwdg_ops;
+ wdd->min_timeout = WDT_MIN_TIMEOUT;
+ wdd->max_timeout = WDT_MAX_TIMEOUT;
+ wdd->max_hw_heartbeat_ms = WDT_MAX_TIMEOUT;
+ wdd->parent = &pdev->dev;
+
+ watchdog_set_drvdata(wdd, wdt);
+ watchdog_set_nowayout(wdd, true);
+
+ ret = watchdog_init_timeout(wdd, WDT_DEFAULT_TIMEOUT, &pdev->dev);
+ if (ret)
+ dev_warn(&pdev->dev,
+ "unable to set timeout value, using default\n");
+
+ ret = watchdog_register_device(wdd);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "failed to register watchdog device\n");
+ goto err;
+ }
+
+ platform_set_drvdata(pdev, wdt);
+
+ return 0;
+err:
+ clk_disable_unprepare(clk);
+
+ return ret;
+}
+
+static int stm32_iwdg_remove(struct platform_device *pdev)
+{
+ struct stm32_iwdg *wdt = platform_get_drvdata(pdev);
+
+ watchdog_unregister_device(&wdt->wdd);
+ clk_disable_unprepare(wdt->clk);
+
+ return 0;
+}
+
+static const struct of_device_id stm32_iwdg_of_match[] = {
+ { .compatible = "st,stm32-iwdg" },
+ { /* end node */ }
+};
+MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
+
+static struct platform_driver stm32_iwdg_driver = {
+ .probe = stm32_iwdg_probe,
+ .remove = stm32_iwdg_remove,
+ .driver = {
+ .name = "iwdg",
+ .of_match_table = stm32_iwdg_of_match,
+ },
+};
+module_platform_driver(stm32_iwdg_driver);
+
+MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1
^ permalink raw reply related
* [PATCH v4 1/5] dt-bindings: watchdog: Document STM32 IWDG bindings
From: Yannick Fertre @ 2017-03-30 15:15 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Alexandre TORGUE,
Benjamin Gaignard, Yannick Fertre, Maxime Coquelin
Cc: devicetree, linux-watchdog, Philippe Cornu, linux-kernel,
Gabriel FERNANDEZ, linux-arm-kernel
In-Reply-To: <1490886926-20585-1-git-send-email-yannick.fertre@st.com>
This adds documentation of device tree bindings for the STM32 IWDG
(Independent WatchDoG).
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Author: Yannick Fertre <yannick.fertre@st.com>
---
.../devicetree/bindings/watchdog/st,stm32-iwdg.txt | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.txt
diff --git a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.txt b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.txt
new file mode 100644
index 0000000..15fef87
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.txt
@@ -0,0 +1,15 @@
+STM32 Independent WatchDoG (IWDG)
+---------------------------------
+
+Required properties:
+- compatible: "st,stm32-iwdg"
+- reg: physical base address and length of the registers set for the device
+- clocks: must contain a single entry describing the clock input
+
+Example:
+
+iwdg: watchdog@40003000 {
+ compatible = "st,stm32-iwdg";
+ reg = <0x40003000 0x400>;
+ clocks = <&clk_lsi>;
+};
--
1.9.1
^ permalink raw reply related
* [PATCH v4 0/5] STM32 Independent watchdog
From: Yannick Fertre @ 2017-03-30 15:15 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Alexandre TORGUE,
Benjamin Gaignard, Yannick Fertre, Maxime Coquelin
Cc: devicetree, linux-watchdog, Philippe Cornu, linux-kernel,
Gabriel FERNANDEZ, linux-arm-kernel
Version 4:
- Update bindings (iwdg > watchdog)
- Update typo
- Update commit header
- remove gerrit tags
- Update driver (remove unnecessary tests) a add watchdog_init_timeout
Version 3:
- Update typo into bindings file
- Reorder node in devicetree (ordering by address)
- Remove unnecessary lines in commits
Version 2:
- Add commit messages
Version 1:
- Initial commit
The purpose of this set of patches is to add a new watchdog driver for
stm32f429.
This driver was developed and tested on evaluation board stm32429i.
Yannick Fertre (5):
dt-bindings: watchdog: Document STM32 IWDG bindings
drivers: watchdog: Add STM32 IWDG driver
ARM: dts: stm32: Add watchdog support for STM32F429 SoC
ARM: dts: stm32: Add watchdog support for STM32F429 eval board
ARM: configs: stm32: Add watchdog support in STM32 defconfig
.../devicetree/bindings/watchdog/st,stm32-iwdg.txt | 15 ++
arch/arm/boot/dts/stm32429i-eval.dts | 4 +
arch/arm/boot/dts/stm32f429.dtsi | 9 +-
arch/arm/configs/stm32_defconfig | 1 +
drivers/watchdog/Kconfig | 12 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/stm32_iwdg.c | 260 +++++++++++++++++++++
7 files changed, 301 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.txt
create mode 100644 drivers/watchdog/stm32_iwdg.c
--
1.9.1
^ permalink raw reply
* Re: [PATCH v3 2/5] drivers: watchdog: Add STM32 IWDG driver
From: Yannick FERTRE @ 2017-03-30 15:10 UTC (permalink / raw)
To: Guenter Roeck, Wim Van Sebroeck, Rob Herring, Alexandre TORGUE,
Benjamin GAIGNARD, Maxime Coquelin
Cc: linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Philippe CORNU, Gabriel FERNANDEZ,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <ac425e69-2d3c-2257-7183-115fbe9eb2b0-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
Hi Guenter,
Many thanks for your help, I will push corrections to V4.
Best regards
On 03/29/2017 05:15 AM, Guenter Roeck wrote:
> On 03/22/2017 08:04 AM, Yannick Fertre wrote:
>> This patch adds IWDG (Independent WatchDoG) support for STM32 platform.
>>
>> Change-Id: Iab218745fc25566f12558fae7f52e2f8c21db74e
>
> No gerrit tags, please.
>
>> Signed-off-by: Yannick FERTRE <yannick.fertre-qxv4g6HH51o@public.gmane.org>
>> ---
>> drivers/watchdog/Kconfig | 11 ++
>> drivers/watchdog/Makefile | 1 +
>> drivers/watchdog/stm32_iwdg.c | 289
>> ++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 301 insertions(+)
>> create mode 100644 drivers/watchdog/stm32_iwdg.c
>>
>> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
>> index 52a70ee..d9745a5 100644
>> --- a/drivers/watchdog/Kconfig
>> +++ b/drivers/watchdog/Kconfig
>> @@ -744,6 +744,17 @@ config ZX2967_WATCHDOG
>> To compile this driver as a module, choose M here: the
>> module will be called zx2967_wdt.
>>
>> +config STM32_WATCHDOG
>> + tristate "STM32 Independent WatchDoG (IWDG) support"
>> + depends on ARCH_STM32
>> + select WATCHDOG_CORE
>> + default y
>> + help
>> + Say Y here to include Watchdog timer support.
>
> ... for <pick your text>.
Ok done
>
>> +
>> + To compile this driver as a module, choose M here: the
>> + module will be called stm32_iwdg.
>> +
>> # AVR32 Architecture
>>
>> config AT32AP700X_WDT
>> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
>> index a2126e2..a35e423 100644
>> --- a/drivers/watchdog/Makefile
>> +++ b/drivers/watchdog/Makefile
>> @@ -84,6 +84,7 @@ obj-$(CONFIG_ATLAS7_WATCHDOG) += atlas7_wdt.o
>> obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
>> obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
>> obj-$(CONFIG_ZX2967_WATCHDOG) += zx2967_wdt.o
>> +obj-$(CONFIG_STM32_WATCHDOG) += stm32_iwdg.o
>>
>> # AVR32 Architecture
>> obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
>> diff --git a/drivers/watchdog/stm32_iwdg.c
>> b/drivers/watchdog/stm32_iwdg.c
>> new file mode 100644
>> index 0000000..507dfc4
>> --- /dev/null
>> +++ b/drivers/watchdog/stm32_iwdg.c
>> @@ -0,0 +1,289 @@
>> +/*
>> + * Driver for STM32 Independent Watchdog
>> + *
>> + * Copyright (C) Yannick Fertre 2017
>> + * Author: Yannick Fertre <yannick.fertre-qxv4g6HH51o@public.gmane.org>
>> + *
>> + * This driver is based on tegra_wdt.c
>> + *
>> + * License terms: GNU General Public License (GPL), version 2
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/watchdog.h>
>> +
>> +/* minimum watchdog trigger timeout, in seconds */
>> +#define MIN_WDT_TIMEOUT 1
>> +
>> +/* IWDG registers */
>> +#define IWDG_KR 0x00 /* Key register */
>> +#define IWDG_PR 0x04 /* Prescaler Register */
>> +#define IWDG_RLR 0x08 /* ReLoad Register */
>> +#define IWDG_SR 0x0C /* Status Register */
>> +#define IWDG_WINR 0x10 /* Windows Register */
>> +
>> +/* IWDG_KR register bit mask */
>> +#define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
>> +#define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
>> +#define KR_KEY_EWA 0x5555 /* write access enable */
>> +#define KR_KEY_DWA 0x0000 /* write access disable */
>> +
>> +/* IWDG_PR register bit values */
>> +#define PR_4 0x00 /* prescaler set to 4 */
>> +#define PR_8 0x01 /* prescaler set to 8 */
>> +#define PR_16 0x02 /* prescaler set to 16 */
>> +#define PR_32 0x03 /* prescaler set to 32 */
>> +#define PR_64 0x04 /* prescaler set to 64 */
>> +#define PR_128 0x05 /* prescaler set to 128 */
>> +#define PR_256 0x06 /* prescaler set to 256 */
>> +
>> +/* IWDG_RLR register values */
>> +#define RLR_MAX 0xFFF /* max value supported by reload
>> register */
>> +
>> +/* IWDG_SR register bit mask */
>> +#define FLAG_PVU BIT(0) /* Watchdog prescaler value update */
>> +#define FLAG_RVU BIT(1) /* Watchdog counter reload value update */
>> +
>> +/* set timeout to 100000 us */
>> +#define TIMEOUT_US 100000
>> +#define SLEEP_US 1000
>> +
>> +struct stm32_iwdg {
>> + struct watchdog_device wdd;
>> + struct device *dev;
>> + void __iomem *regs;
>> + struct clk *clk;
>> + unsigned int rate;
>> +};
>> +
>> +static int heartbeat = MIN_WDT_TIMEOUT;
>> +module_param(heartbeat, int, 0x0);
>> +MODULE_PARM_DESC(heartbeat,
>> + "Watchdog heartbeats in seconds. (default = "
>> + __MODULE_STRING(WDT_HEARTBEAT) ")");
>> +
>> +static inline u32 reg_read(void __iomem *base, u32 reg)
>> +{
>> + return readl_relaxed(base + reg);
>> +}
>> +
>> +static inline void reg_write(void __iomem *base, u32 reg, u32 val)
>> +{
>> + writel_relaxed(val, base + reg);
>> +}
>> +
>> +static int stm32_iwdg_start(struct watchdog_device *wdd)
>> +{
>> + struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
>> + u32 val = FLAG_PVU | FLAG_RVU;
>> + u32 reload;
>> + int ret;
>> +
>> + dev_dbg(wdt->dev, "%s\n", __func__);
>> +
>> + /* prescaler fixed to 256 */
>> + reload = (wdd->timeout * wdt->rate) / 256;
>> + if (reload > RLR_MAX + 1) {
>> + dev_err(wdt->dev,
>> + "Watchdog doesn't support reload value: %d\n", reload);
>> + return -EINVAL;
>> + }
>
> This should not happen if min_timeout and max_timeout are set properly.
>
Ok, I remove the test.
>> +
>> + /* enable watchdog */
>> + reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
>> +
>> + /* set prescaler & reload registers */
>> + reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
>> + reg_write(wdt->regs, IWDG_PR, PR_256); /* prescaler fix to 256 */
>> + reg_write(wdt->regs, IWDG_RLR, reload - 1);
>> +
>> + /* wait for the registers to be updated (max 100ms) */
>> + ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, val,
>> + !(val & (FLAG_PVU | FLAG_RVU)),
>> + SLEEP_US, TIMEOUT_US);
>> + if (ret) {
>> + dev_err(wdt->dev,
>> + "Fail to set prescaler or reload registers\n");
>> + return -EINVAL;
>
> Any reason for overriding the return value ?
>
Ok, done
>> + }
>> +
>> + /* reload watchdog */
>> + reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
>> +
>> + return 0;
>> +}
>> +
>> +static int stm32_iwdg_stop(struct watchdog_device *wdd)
>> +{
>> + struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
>> +
>> + if (watchdog_active(wdd)) {
>> + dev_err(wdt->dev,
>> + "Watchdog can't be stopped once started(no way out)\n");
>> + return -EPERM;
>
> The infrastructure takes care of this. Don't provide a stop function,
> and provide
> the maximum hardware timeout.
Ok, I remove stop function
>
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int stm32_iwdg_ping(struct watchdog_device *wdd)
>> +{
>> + struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
>> +
>> + dev_dbg(wdt->dev, "%s\n", __func__);
>> +
>> + reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
>> +
>> + return 0;
>> +}
>> +
>> +static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
>> + unsigned int timeout)
>> +{
>> + struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
>> +
>> + dev_dbg(wdt->dev, "%s timeout: %d sec\n", __func__, timeout);
>> +
>> + wdd->timeout = timeout;
>> +
>> + if (watchdog_active(wdd))
>> + return stm32_iwdg_start(wdd);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct watchdog_info stm32_iwdg_info = {
>> + .options = WDIOF_SETTIMEOUT |
>> + WDIOF_MAGICCLOSE |
>> + WDIOF_KEEPALIVEPING,
>> + .identity = "STM32 Independent Watchdog",
>> +};
>> +
>> +static struct watchdog_ops stm32_iwdg_ops = {
>> + .owner = THIS_MODULE,
>> + .start = stm32_iwdg_start,
>> + .stop = stm32_iwdg_stop,
>> + .ping = stm32_iwdg_ping,
>> + .set_timeout = stm32_iwdg_set_timeout,
>> +};
>> +
>> +static int stm32_iwdg_probe(struct platform_device *pdev)
>> +{
>> + struct watchdog_device *wdd;
>> + struct stm32_iwdg *wdt;
>> + struct resource *res;
>> + void __iomem *regs;
>> + struct clk *clk;
>> + int max_wdt_timeout;
>> + int ret;
>> +
>> + /* This is the timer base. */
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + regs = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(regs)) {
>> + dev_err(&pdev->dev, "Could not get resource\n");
>> + return PTR_ERR(regs);
>> + }
>> +
>> + clk = devm_clk_get(&pdev->dev, NULL);
>> + if (IS_ERR(clk)) {
>> + dev_err(&pdev->dev, "Unable to get clock\n");
>> + return PTR_ERR(clk);
>> + }
>> +
>> + ret = clk_prepare_enable(clk);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Unable to prepare clock %p\n", clk);
>> + return ret;
>> + }
>> +
>> + /*
>> + * Allocate our watchdog driver data, which has the
>> + * struct watchdog_device nested within it.
>> + */
>> + wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
>> + if (!wdt) {
>> + ret = -ENOMEM;
>> + goto err;
>> + }
>> +
>> + /* Initialize struct stm32_iwdg. */
>> + wdt->regs = regs;
>> + wdt->dev = &pdev->dev;
>> + wdt->clk = clk;
>> + /*
>> + * iwdg is clocked by its own dedicated low-speed clock (LSI)
>> + * at 32khz.
>> + */
>> + wdt->rate = 32 * 1024;
>
> Why not clk_get_rate() ?
Ok, done
>
>> +
>> + /* get max timeout & set heartbeat */
>> + max_wdt_timeout = ((RLR_MAX + 1) * 256) / wdt->rate;
>> + heartbeat = max_wdt_timeout;
>
> What is the value of overwriting this variable ? Why don't you just use
> max_wdt_timeout,
> and what is the point of making heartbeat configurable if you overwrite
> it anyway ?
>
> I would suggest to use watchdog_init_timeout() to set optional non-default
> timeout values, especially since this also enables getting the timeout
> value from
> devicetree.
>
Ok done
>> +
>> + /* Initialize struct watchdog_device. */
>> + wdd = &wdt->wdd;
>> + wdd->timeout = heartbeat;
>> + wdd->info = &stm32_iwdg_info;
>> + wdd->ops = &stm32_iwdg_ops;
>> + wdd->min_timeout = MIN_WDT_TIMEOUT;
>> + wdd->max_timeout = max_wdt_timeout;
>
> You might want to consider setting max_hw_heartbeat_ms instead and drop
> the stop function.
>
Ok, done
>> + watchdog_set_drvdata(wdd, wdt);
>> + watchdog_set_nowayout(wdd, true);
>> +
>> + ret = watchdog_register_device(wdd);
>> + if (ret) {
>> + dev_err(&pdev->dev,
>> + "failed to register watchdog device\n");
>> + goto err;
>> + }
>> +
>> + platform_set_drvdata(pdev, wdt);
>> +
>> + dev_info(&pdev->dev,
>> + "initialized (heartbeat = %d sec)\n", heartbeat);
>> + return 0;
>> +
>> +err:
>> + clk_disable_unprepare(clk);
>> + return ret;
>> +}
>> +
>> +static int stm32_iwdg_remove(struct platform_device *pdev)
>> +{
>> + struct stm32_iwdg *wdt = platform_get_drvdata(pdev);
>> +
>> + watchdog_unregister_device(&wdt->wdd);
>> + clk_disable_unprepare(wdt->clk);
>> +
>> + dev_info(&pdev->dev, "removed watchdog device\n");
>
> Is this message really useful ? I think it is just noise.
Ok, removed
>
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id stm32_iwdg_of_match[] = {
>> + { .compatible = "st,stm32-iwdg" },
>> + { /* end node */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
>> +
>> +static struct platform_driver stm32_iwdg_driver = {
>> + .probe = stm32_iwdg_probe,
>> + .remove = stm32_iwdg_remove,
>> + .driver = {
>> + .name = "iwdg",
>> + .of_match_table = stm32_iwdg_of_match,
>> + },
>> +};
>> +module_platform_driver(stm32_iwdg_driver);
>> +
>> +MODULE_AUTHOR("Yannick Fertre <yannick.fertre-qxv4g6HH51o@public.gmane.org>");
>> +MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog
>> Driver");
>> +MODULE_LICENSE("GPL v2");
>>
>--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 2/3] device property: Move fwnode graph ops to firmware specific locations
From: Sakari Ailus @ 2017-03-30 15:10 UTC (permalink / raw)
To: Mika Westerberg
Cc: Sakari Ailus, linux-acpi, devicetree, robh, sudeep.holla,
lorenzo.pieralisi, rafael, mark.rutland, broonie, ahs3,
frowand.list
In-Reply-To: <20170327115200.GB2957@lahna.fi.intel.com>
Hi Mika,
Thank you for the review.
On Mon, Mar 27, 2017 at 02:52:00PM +0300, Mika Westerberg wrote:
> On Fri, Mar 24, 2017 at 01:03:51PM +0200, Sakari Ailus wrote:
> > const struct fwnode_operations acpi_fwnode_ops = {
> > .property_present = acpi_fwnode_property_present,
> > .property_read_int_array = acpi_fwnode_property_read_int_array,
> > @@ -1193,4 +1248,9 @@ const struct fwnode_operations acpi_fwnode_ops = {
> > .get_parent = acpi_fwnode_get_parent,
> > .get_next_child_node = acpi_get_next_subnode,
> > .get_named_child_node = acpi_fwnode_get_named_child_node,
> > + .graph_get_next_endpoint = acpi_fwnode_graph_get_next_endpoint,
> > + .graph_get_remote_endpoint = acpi_fwnode_graph_get_remote_endpoint,
> > + .graph_get_remote_port = acpi_fwnode_graph_get_remote_port,
> > + .graph_get_remote_port_parent = acpi_fwnode_graph_get_remote_port_parent,
> > + .graph_parse_endpoint = acpi_fwnode_graph_parse_endpoint,
> > };
>
> Not sure if it is possible but it would be nice to have a single
> primitive implementation specific graph callback and then build
> everything else on top of that in generic code. Here you have 5
> callbacks just for graph support.
Getting the parent of the port in OF graph is OF specific, the port parent
is not necessarily a direct parent node of the port (in presence of the
"ports" node that contains all port nodes).
I could potentially remove graph_get_remote_port() and use
graph_get_remote_endpoint() and graph_get_parent() instead. I didn't
originally do that as I thought it could be better ot leave it up to the
implementation.
What do you think?
--
Regards,
Sakari Ailus
e-mail: sakari.ailus@iki.fi XMPP: sailus@retiisi.org.uk
^ permalink raw reply
* Re: [PATCH v4 0/6] initialize dtsi file and dts file for RK3328 SoCs
From: Wolfram Sang @ 2017-03-30 15:05 UTC (permalink / raw)
To: cl-TNX95d0MmH7DzftRWevZcw
Cc: heiko-4mtYJXux2i+zQB+pC5nmwQ, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, zhengxing-TNX95d0MmH7DzftRWevZcw,
andy.yan-TNX95d0MmH7DzftRWevZcw, jay.xu-TNX95d0MmH7DzftRWevZcw,
matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w,
paweljarosz3691-Re5JQEeQqe8AvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg, wxt-TNX95d0MmH7DzftRWevZcw,
david.wu-TNX95d0MmH7DzftRWevZcw, linux-iio-u79uwXL29TY76Z2rM5mHXA,
shawn.lin-TNX95d0MmH7DzftRWevZcw,
akpm-de/tnXTf+JLsfHDXvbKv3WD2FQJk+8+b,
dianders-F7+t8E8rja9g9hUCZPvPmw,
yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
afaerber-l3A5Bk7waGM, shawnguo-DgEjT+Ai2ygdnm+yROfE0A,
khilman-rdvid1DuHRBWk0Htik3J/w, arnd-r2nGTMty4D4,
fabio.estevam-3arQi8VN3Tc, zhangqing-TNX95d0MmH7DzftRWevZcw,
kever.yang
In-Reply-To: <1490607650-18650-1-git-send-email-cl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 970 bytes --]
On Mon, Mar 27, 2017 at 05:40:45PM +0800, cl-TNX95d0MmH7DzftRWevZcw@public.gmane.org wrote:
> From: Liang Chen <cl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>
> Changes in v4:
> Remove some assigned-clocks as they should be inited in their
> respective device nodes.
>
> Changes in v3:
> Adjust some descriptions in dtsi.
>
> Changes in v2:
> Remove RK_FUNC_* in dtsi as it dose not help understand things better.
> Adjust the order of description in dt-bindings.
>
> v1:
> These patchs depend on pinctrl patchs as below:
Why didn't you renumber the patches? I and probably others wondered
where and what patch 2 is and why it could be missing. I recall now that
I applied it already. Other maintainers don't have that knowledge. Also,
since I applied your patch, no need for me or the i2c-list to be on CC.
Please no "quick fixes" when sending out patch series. I know it is
tempting but it usually creates confusion.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* [PATCH 3/3] dts: arm64: add LS1046A DPAA QBMan nodes
From: Madalin Bucur @ 2017-03-30 14:37 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, shawnguo-DgEjT+Ai2ygdnm+yROfE0A,
Gang.Liu-3arQi8VN3Tc, Madalin Bucur, Roy Pledge
In-Reply-To: <1490884672-18294-1-git-send-email-madalin.bucur-3arQi8VN3Tc@public.gmane.org>
Add the QBMan device tree nodes for LS1046A devices.
Signed-off-by: Roy Pledge <roy.pledge-3arQi8VN3Tc@public.gmane.org>
Signed-off-by: Madalin Bucur <madalin.bucur-3arQi8VN3Tc@public.gmane.org>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 52 ++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 4a164b8..67e073a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -268,6 +268,30 @@
};
};
+ qman: qman@1880000 {
+ compatible = "fsl,qman";
+ reg = <0x00 0x1880000 0x0 0x10000>;
+ interrupts = <0 45 0x4>;
+ memory-region = <&qman_fqd &qman_pfdr>;
+
+ };
+
+ bman: bman@1890000 {
+ compatible = "fsl,bman";
+ reg = <0x00 0x1890000 0x0 0x10000>;
+ interrupts = <0 45 0x4>;
+ memory-region = <&bman_fbpr>;
+
+ };
+
+ qportals: qman-portals@500000000 {
+ ranges = <0x0 0x5 0x00000000 0x8000000>;
+ };
+
+ bportals: bman-portals@508000000 {
+ ranges = <0x0 0x5 0x08000000 0x8000000>;
+ };
+
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1046a-dcfg", "syscon";
reg = <0x0 0x1ee0000 0x0 0x10000>;
@@ -592,4 +616,32 @@
clocks = <&clockgen 4 1>;
};
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ bman_fbpr: bman-fbpr {
+ compatible = "shared-dma-pool";
+ size = <0 0x1000000>;
+ alignment = <0 0x1000000>;
+ no-map;
+ };
+ qman_fqd: qman-fqd {
+ compatible = "shared-dma-pool";
+ size = <0 0x800000>;
+ alignment = <0 0x800000>;
+ no-map;
+ };
+ qman_pfdr: qman-pfdr {
+ compatible = "shared-dma-pool";
+ size = <0 0x2000000>;
+ alignment = <0 0x2000000>;
+ no-map;
+ };
+ };
};
+
+#include "qoriq-qman1-portals.dtsi"
+#include "qoriq-bman1-portals.dtsi"
--
2.1.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 2/3] dts: arm64: add LS1043A DPAA QBMan nodes
From: Madalin Bucur @ 2017-03-30 14:37 UTC (permalink / raw)
To: robh+dt, mark.rutland, devicetree
Cc: linux-arm-kernel, linux-kernel, catalin.marinas, will.deacon,
shawnguo, Gang.Liu, Madalin Bucur, Roy Pledge
In-Reply-To: <1490884672-18294-1-git-send-email-madalin.bucur@nxp.com>
Add the DPAA 1.x QMan and BMan nodes in the LS1043A device tree.
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 52 ++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index ec13a6e..8434e89 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -106,6 +106,33 @@
/* DRAM space 1, size: 2GiB DRAM */
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ bman_fbpr: bman-fbpr {
+ compatible = "shared-dma-pool";
+ size = <0 0x1000000>;
+ alignment = <0 0x1000000>;
+ no-map;
+ };
+
+ qman_fqd: qman-fqd {
+ compatible = "shared-dma-pool";
+ size = <0 0x400000>;
+ alignment = <0 0x400000>;
+ no-map;
+ };
+
+ qman_pfdr: qman-pfdr {
+ compatible = "shared-dma-pool";
+ size = <0 0x2000000>;
+ alignment = <0 0x2000000>;
+ no-map;
+ };
+ };
+
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -333,6 +360,28 @@
};
};
+ qman: qman@1880000 {
+ compatible = "fsl,qman";
+ reg = <0x00 0x1880000 0x0 0x10000>;
+ interrupts = <0 45 0x4>;
+ memory-region = <&qman_fqd &qman_pfdr>;
+ };
+
+ bman: bman@1890000 {
+ compatible = "fsl,bman";
+ reg = <0x00 0x1890000 0x0 0x10000>;
+ interrupts = <0 45 0x4>;
+ memory-region = <&bman_fbpr>;
+ };
+
+ bportals: bman-portals@508000000 {
+ ranges = <0x0 0x5 0x08000000 0x8000000>;
+ };
+
+ qportals: qman-portals@500000000 {
+ ranges = <0x0 0x5 0x00000000 0x8000000>;
+ };
+
dspi0: dspi@2100000 {
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
@@ -686,3 +735,6 @@
};
};
+
+#include "qoriq-qman1-portals.dtsi"
+#include "qoriq-bman1-portals.dtsi"
--
2.1.0
^ permalink raw reply related
* [PATCH 1/3] dts: arm64: add DPAA QBMan portals
From: Madalin Bucur @ 2017-03-30 14:37 UTC (permalink / raw)
To: robh+dt, mark.rutland, devicetree
Cc: linux-arm-kernel, linux-kernel, catalin.marinas, will.deacon,
shawnguo, Gang.Liu, Madalin Bucur, Roy Pledge
In-Reply-To: <1490884672-18294-1-git-send-email-madalin.bucur@nxp.com>
Add the DPAA 1.x DPAA QMan and BMan portal nodes.
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
---
.../boot/dts/freescale/qoriq-bman1-portals.dtsi | 67 +++++++++++++++++++
.../boot/dts/freescale/qoriq-qman1-portals.dtsi | 76 ++++++++++++++++++++++
2 files changed, 143 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
diff --git a/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
new file mode 100644
index 0000000..b007344
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
@@ -0,0 +1,67 @@
+/*
+ * QorIQ BMan Portals device tree
+ *
+ * Copyright 2011-2016 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+&bportals {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+
+ bman-portal@0 {
+ compatible = "fsl,bman-portal";
+ reg = <0x0 0x4000 0x4000000 0x4000>;
+ interrupts = <0 173 0x4>;
+ };
+
+ bman-portal@10000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x10000 0x4000 0x4010000 0x4000>;
+ interrupts = <0 175 0x4>;
+ };
+
+ bman-portal@20000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x20000 0x4000 0x4020000 0x4000>;
+ interrupts = <0 177 0x4>;
+ };
+
+ bman-portal@30000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x30000 0x4000 0x4030000 0x4000>;
+ interrupts = <0 179 0x4>;
+ };
+
+ bman-portal@40000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x40000 0x4000 0x4040000 0x4000>;
+ interrupts = <0 181 0x4>;
+ };
+
+ bman-portal@50000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x50000 0x4000 0x4050000 0x4000>;
+ interrupts = <0 183 0x4>;
+ };
+
+ bman-portal@60000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x60000 0x4000 0x4060000 0x4000>;
+ interrupts = <0 185 0x4>;
+ };
+
+ bman-portal@70000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x70000 0x4000 0x4070000 0x4000>;
+ interrupts = <0 187 0x4>;
+ };
+
+ bman-portal@80000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x80000 0x4000 0x4080000 0x4000>;
+ interrupts = <0 189 0x4>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
new file mode 100644
index 0000000..4baec2c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
@@ -0,0 +1,76 @@
+/*
+ * QorIQ QMan Portals device tree
+ *
+ * Copyright 2011-2016 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+&qportals {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+
+ qportal0: qman-portal@0 {
+ compatible = "fsl,qman-portal";
+ reg = <0x0 0x4000 0x4000000 0x4000>;
+ interrupts = <0 172 0x4>;
+ cell-index = <0>;
+ };
+
+ qportal1: qman-portal@10000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x10000 0x4000 0x4010000 0x4000>;
+ interrupts = <0 174 0x4>;
+ cell-index = <1>;
+ };
+
+ qportal2: qman-portal@20000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x20000 0x4000 0x4020000 0x4000>;
+ interrupts = <0 176 0x4>;
+ cell-index = <2>;
+ };
+
+ qportal3: qman-portal@30000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x30000 0x4000 0x4030000 0x4000>;
+ interrupts = <0 178 0x4>;
+ cell-index = <3>;
+ };
+
+ qportal4: qman-portal@40000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x40000 0x4000 0x4040000 0x4000>;
+ interrupts = <0 180 0x4>;
+ cell-index = <4>;
+ };
+
+ qportal5: qman-portal@50000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x50000 0x4000 0x4050000 0x4000>;
+ interrupts = <0 182 0x4>;
+ cell-index = <5>;
+ };
+
+ qportal6: qman-portal@60000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x60000 0x4000 0x4060000 0x4000>;
+ interrupts = <0 184 0x4>;
+ cell-index = <6>;
+ };
+
+ qportal7: qman-portal@70000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x70000 0x4000 0x4070000 0x4000>;
+ interrupts = <0 186 0x4>;
+ cell-index = <7>;
+ };
+
+ qportal8: qman-portal@80000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x80000 0x4000 0x4080000 0x4000>;
+ interrupts = <0 188 0x4>;
+ cell-index = <8>;
+ };
+};
--
2.1.0
^ permalink raw reply related
* [PATCH 0/3] introduce QorIQ DPAA 1.x QBMan device tree nodes
From: Madalin Bucur @ 2017-03-30 14:37 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, shawnguo-DgEjT+Ai2ygdnm+yROfE0A,
Gang.Liu-3arQi8VN3Tc, Madalin Bucur
This patch set introduces the QorIQ Data Path Acceleration Arhitecture
(DPAA) Queue Manager and Buffer Manager device tree nodes for the ARM
based DPAA 1.x platforms.
Madalin Bucur (3):
dts: arm64: add DPAA QBMan portals
dts: arm64: add LS1043A DPAA QBMan nodes
dts: arm64: add LS1046A DPAA QBMan nodes
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 52 +++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 52 +++++++++++++++
.../boot/dts/freescale/qoriq-bman1-portals.dtsi | 67 +++++++++++++++++++
.../boot/dts/freescale/qoriq-qman1-portals.dtsi | 76 ++++++++++++++++++++++
4 files changed, 247 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
--
2.1.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [GIT PULL] generic TEE subsystem for v4.12
From: Arnd Bergmann @ 2017-03-30 14:32 UTC (permalink / raw)
To: Jens Wiklander
Cc: arm-DgEjT+Ai2ygdnm+yROfE0A, Olof Johansson, Greg Kroah-Hartman,
Andrew Morton, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Al Viro,
jean-michel.delorme-qxv4g6HH51o, emmanuel.michel-qxv4g6HH51o,
javier-5MUHepqpBA1BDgjK7y7TUQ, Jason Gunthorpe, Mark Rutland,
Michal Simek, Rob Herring, Will Deacon, Nishanth Menon,
Andrew F. Davis, broonie-DgEjT+Ai2ygdnm+yROfE0A,
scott.branden-dY08KVG/lbpWk0Htik3J/w, Loic PALLARDY,
Etienne CARRIERE, Benjamin GAIGNARD
In-Reply-To: <20170314145305.GA12937@jax>
On Tuesday, March 14, 2017 3:57:34 PM CEST Jens Wiklander wrote:
> Hi arm-soc maintainers,
>
> Please consider this pull request for v4.12
>
> This pull request contains version 16 of the generic TEE driver.
>
> The TEE subsystem will contain drivers for various TEE implementations.
> A TEE (Trusted Execution Environment) is a trusted OS running in some
> secure environment, for example, TrustZone on ARM CPUs, or a separate
> secure co-processor etc.
>
> The patch set has been reviewed by different people during the different
> versions. Now I think this has reached a state where it's mature enough
> to merge.
>
> The v16 cover letter containing detailed revision history can be found at
> https://lkml.org/lkml/2017/3/10/1277
>
> Thanks,
> Jens
>
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.linaro.org:/people/jens.wiklander/linux-tee.git tags/tee-drv-for-4.12
>
> for you to fetch changes up to 14e21cb8f811100a2104e952b8f5bc0326a5e213:
>
> arm64: dt: hikey: Add optee node (2017-03-10 14:51:58 +0100)
>
> ----------------------------------------------------------------
> Introduce generic TEE subsystem:
> - the TEE subsystem itself
> - an OP-TEE driver using the subsystem
> - optee bindings
> - optee node for hi6220-hikey.dts
(+Linus, FYI)
I've put this into a separate next/tee branch in arm-soc,
which means we will send this separately to Linus in the next
merge window for the introduction of a new kernel subsystem,
and I expect that future updates will get handled through the
next/drivers branch in arm-soc, like we do for reset controllers.
I have reviewed earlier versions in the past, and have reviewed
the latest version in person during Linaro Connect BUD17.
Here is my overall assessment of the subsystem:
* There is clearly demand for this, both for the generic
infrastructure and the specific OP-TEE implementation.
* The code has gone through a large number of reviews,
and the review comments have all been addressed, but
the reviews were not coming up with serious issues any more
and nobody volunteered to vouch for the quality.
* The user space ioctl interface is sufficient to work with the
OP-TEE driver, and it should in principle work with other
TEE implementations that follow the GlobalPlatform[1] standards,
but it might need to be extended in minor ways depending on
specific requirements of future TEE implementations
* The main downside of the API to me is how the user space
is tied to the TEE implementation in hardware or firmware,
but uses a generic way to communicate with it. This seems
to be an inherent problem with what it is trying to do,
and I could not come up with any better solution than what
is implemented here.
Arnd
[1] https://www.globalplatform.org/mediaguidetee.asp
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH] ARM: dts: am57xx-idk: Add DCAN support
From: Sekhar Nori @ 2017-03-30 14:23 UTC (permalink / raw)
To: Tony Lindgren
Cc: Mark Rutland, Device Tree Mailing List, Schuyler Patton,
Kishon Vijay Abraham I, Rob Herring, Franklin S Cooper Jr,
Linux OMAP Mailing List, Linux ARM Mailing List, Quadros, Roger
In-Reply-To: <20170306184113.GN20572@atomide.com>
Hi Tony,
On Tuesday 07 March 2017 12:11 AM, Tony Lindgren wrote:
> * Sekhar Nori <nsekhar@ti.com> [170221 02:13]:
>> On Tuesday 21 February 2017 03:30 PM, Sekhar Nori wrote:
>>> From: Schuyler Patton <spatton@ti.com>
>>>
>>> AM571x IDK and the AM572x IDK use CAN1 interface.
>>> This patch enables it for both boards.
>>>
>>> Tested on AM572x IDK using cansequence.
>>>
>>> Signed-off-by: Schuyler Patton <spatton@ti.com>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>> Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
>>> [nsekhar@ti.com: move to use DRA7XX_CORE_IOPAD())
>>> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
>>
>> I should have noted that although CAN does function on the IDK with this
>> patch, there are "omap_hwmod: dcan1: _wait_target_disable failed"
>> messages that come up due to lack of workaround for errata i893[1]
>>
>> Roger does have some patches to workaround that errata. If you want to
>> wait for those patches to be submitted and accepted first, it should be
>> fine as well.
>
> OK let's wait a bit on this then to avoid introducing extra warnings.
Now that Roger's hwmod patches for the DCAN errata are in linux-next,
this patch can be applied safely. Let me know if you need me to resend it.
Thanks,
Sekhar
^ permalink raw reply
* Re: [RFC PATCH 2/5] soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations
From: Robin Murphy @ 2017-03-30 14:09 UTC (permalink / raw)
To: roy.pledge-3arQi8VN3Tc, oss-fOR+EgIDQEHk1uMJSBkQmQ,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: madalin.bucur-3arQi8VN3Tc
In-Reply-To: <1490822037-6752-3-git-send-email-roy.pledge-3arQi8VN3Tc@public.gmane.org>
Hi Roy,
On 29/03/17 22:13, Roy Pledge wrote:
> Use the shared-memory-pool mechanism for frame queue descriptor and
> packed frame descriptor record area allocations.
Thanks for persevering with this - in my opinion it's now looking like
it was worth the effort :)
AFAICS the ioremap_wc() that this leads to does appear to give back
something non-cacheable on PPC (assuming "pgprot_noncached_wc" isn't
horrendously misnamed), and "no-map" should rule out any cacheable
linear map alias existing, so it would seem that this approach should
avert Scott's concerns about attribute mismatches.
> Signed-off-by: Roy Pledge <roy.pledge-3arQi8VN3Tc@public.gmane.org>
> ---
> drivers/soc/fsl/qbman/qman_ccsr.c | 119 +++++++++++++++++++++-----------------
> drivers/soc/fsl/qbman/qman_priv.h | 4 +-
> drivers/soc/fsl/qbman/qman_test.h | 2 -
> 3 files changed, 68 insertions(+), 57 deletions(-)
>
> diff --git a/drivers/soc/fsl/qbman/qman_ccsr.c b/drivers/soc/fsl/qbman/qman_ccsr.c
> index 90bc40c..35c59ca 100644
> --- a/drivers/soc/fsl/qbman/qman_ccsr.c
> +++ b/drivers/soc/fsl/qbman/qman_ccsr.c
> @@ -400,63 +400,19 @@ static int qm_init_pfdr(struct device *dev, u32 pfdr_start, u32 num)
> return -ENODEV;
> }
>
> -/*
> - * Ideally we would use the DMA API to turn rmem->base into a DMA address
> - * (especially if iommu translations ever get involved). Unfortunately, the
> - * DMA API currently does not allow mapping anything that is not backed with
> - * a struct page.
> - */
> +/* QMan needs two global memory areas initialized at boot time:
> + 1) FQD: Frame Queue Descriptors used to manage frame queues
> + 2) PFDR: Packed Frame Queue Descriptor Records used to store frames
> + Both areas are reserved using the device tree reserved memory framework
> + and the addresses and sizes are initialized when the QMan device is probed */
> static dma_addr_t fqd_a, pfdr_a;
> static size_t fqd_sz, pfdr_sz;
>
> -static int qman_fqd(struct reserved_mem *rmem)
> -{
> - fqd_a = rmem->base;
> - fqd_sz = rmem->size;
> -
> - WARN_ON(!(fqd_a && fqd_sz));
> -
> - return 0;
> -}
> -RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd);
> -
> -static int qman_pfdr(struct reserved_mem *rmem)
> -{
> - pfdr_a = rmem->base;
> - pfdr_sz = rmem->size;
> -
> - WARN_ON(!(pfdr_a && pfdr_sz));
> -
> - return 0;
> -}
> -RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr);
> -
I notice that patch #1 isn't removing the equivalent bman_fbpr() handler
and declaration as here - is that deliberate or just an oversight?
> static unsigned int qm_get_fqid_maxcnt(void)
> {
> return fqd_sz / 64;
> }
>
> -/*
> - * Flush this memory range from data cache so that QMAN originated
> - * transactions for this memory region could be marked non-coherent.
> - */
> -static int zero_priv_mem(struct device *dev, struct device_node *node,
> - phys_addr_t addr, size_t sz)
> -{
> - /* map as cacheable, non-guarded */
> - void __iomem *tmpp = ioremap_prot(addr, sz, 0);
> -
> - if (!tmpp)
> - return -ENOMEM;
> -
> - memset_io(tmpp, 0, sz);
> - flush_dcache_range((unsigned long)tmpp,
> - (unsigned long)tmpp + sz);
> - iounmap(tmpp);
> -
> - return 0;
> -}
> -
> static void log_edata_bits(struct device *dev, u32 bit_count)
> {
> u32 i, j, mask = 0xffffffff;
> @@ -687,11 +643,12 @@ static int qman_resource_init(struct device *dev)
> static int fsl_qman_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> - struct device_node *node = dev->of_node;
> + struct device_node *mem_node, *node = dev->of_node;
> struct resource *res;
> int ret, err_irq;
> u16 id;
> u8 major, minor;
> + u64 size;
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> if (!res) {
> @@ -727,10 +684,66 @@ static int fsl_qman_probe(struct platform_device *pdev)
> qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
> }
>
> - ret = zero_priv_mem(dev, node, fqd_a, fqd_sz);
> - WARN_ON(ret);
> - if (ret)
> + /* Order of memory regions is assumed as FQD followed by PFDR
> + in order to ensure allocations from the correct regions the
> + driver initializes then allocates each piece in order */
> +
> + ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, 0);
> + if (ret) {
> + dev_err(dev, "of_reserved_mem_device_init_by_idx(0) failed 0x%x\n",
> + ret);
> + return -ENODEV;
> + }
> + mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
> + if (mem_node) {
> + ret = of_property_read_u64(mem_node, "size", &size);
> + if (ret) {
> + dev_err(dev, "FQD: of_address_to_resource fails 0x%x\n", ret);
Nit: of_address_to_resource?
> + return -ENODEV;
> + }
> + fqd_sz = size;
> + } else {
> + dev_err(dev, "No memory-region found for FQD\n");
> + return -ENODEV;
> + }
> + if (!dma_zalloc_coherent(dev, fqd_sz, &fqd_a, 0)) {
> + dev_err(dev, "Alloc FQD memory failed\n");
> + return -ENODEV;
> + }
Between here, below, and patch #1, it looks like this "init, get size,
alloc" pattern could be nicely factored out into a common helper function.
> +
> + dev_info(dev, "Allocated FQD 0x%llx 0x%zx\n", fqd_a, fqd_sz);
> +
> + /* Disassociate the FQD reseverd memory area from the device because
> + a device can only have one DMA memory area. This should be fine
> + since the memory is allocated and initalized and only ever accessed
> + by the QMan device from now on */
Typos: reserved, initialized.
> + of_reserved_mem_device_release(dev);
I see the driver does not implement a .remove method where you would
otherwise be technically expected to balance the allocation with a
dma_free_coherent(), so I think this trick is acceptable. If anyone
wants to change that in future, it wouldn't seem unreasonable to extend
the core code to handle multiple areas per device (and at worst, I guess
you could deviously juggle dev->dma_mem around the DMA API calls).
Other than those first few nits, and any possible PPC-specific angles
I'm not aware of, I think the series is looking good!
Thanks,
Robin.
> +
> + /* Setup PFDR memory */
> + ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, 1);
> + if (ret) {
> + dev_err(dev, "of_reserved_mem_device_init(1) failed 0x%x\n",
> + ret);
> + return -ENODEV;
> + }
> + mem_node = of_parse_phandle(dev->of_node, "memory-region", 1);
> + if (mem_node) {
> + ret = of_property_read_u64(mem_node, "size", &size);
> + if (ret) {
> + dev_err(dev, "PFDR: of_address_to_resource fails 0x%x\n", ret);
> + return -ENODEV;
> + }
> + pfdr_sz = size;
> + } else {
> + dev_err(dev, "No memory-region found for PFDR\n");
> + return -ENODEV;
> + }
> + if (!dma_zalloc_coherent(dev, pfdr_sz, &pfdr_a, 0)) {
> + dev_err(dev, "Alloc PFDR Failed size 0x%zx\n", pfdr_sz);
> return -ENODEV;
> + }
> +
> + dev_info(dev, "Allocated PFDR 0x%llx 0x%zx\n", pfdr_a, pfdr_sz);
>
> ret = qman_init_ccsr(dev);
> if (ret) {
> diff --git a/drivers/soc/fsl/qbman/qman_priv.h b/drivers/soc/fsl/qbman/qman_priv.h
> index 22725bd..1e998ea5 100644
> --- a/drivers/soc/fsl/qbman/qman_priv.h
> +++ b/drivers/soc/fsl/qbman/qman_priv.h
> @@ -28,12 +28,12 @@
> * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> */
>
> -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> -
> #include "dpaa_sys.h"
>
> #include <soc/fsl/qman.h>
> #include <linux/iommu.h>
> +#include <linux/dma-contiguous.h>
> +#include <linux/of_address.h>
>
> #if defined(CONFIG_FSL_PAMU)
> #include <asm/fsl_pamu_stash.h>
> diff --git a/drivers/soc/fsl/qbman/qman_test.h b/drivers/soc/fsl/qbman/qman_test.h
> index d5f8cb2..41bdbc48 100644
> --- a/drivers/soc/fsl/qbman/qman_test.h
> +++ b/drivers/soc/fsl/qbman/qman_test.h
> @@ -30,7 +30,5 @@
>
> #include "qman_priv.h"
>
> -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> -
> int qman_test_stash(void);
> int qman_test_api(void);
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox