* Re: [PATCHv3] iio: adc: cpcap: Add minimal support for CPCAP PMIC ADC
From: Jonathan Cameron @ 2017-03-30 18:26 UTC (permalink / raw)
To: Rob Herring, Tony Lindgren
Cc: Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Marcel Partap, Michael Scott,
Sebastian Reichel
In-Reply-To: <20170329212637.syluvxy5cp2qub3h@rob-hp-laptop>
On 29/03/17 22:26, Rob Herring wrote:
> On Thu, Mar 23, 2017 at 08:38:42PM -0700, Tony Lindgren wrote:
>> On Motorola phones like droid 4 there is a custom CPCAP PMIC. This PMIC
>> has ADCs that are used for battery charging and USB PHY VBUS and ID pin
>> detection.
>>
>> Unfortunately the only documentation for this ADC seems to be the
>> Motorola mapphone Linux kernel tree. I have tested that reading raw and
>> scaled values works, but I have not used the timed sampling that the ADC
>> seems to support.
>>
>> Let's add a minimal support for it so we can eventually provide IIO
>> channels for the related battery charging and USB PHY drivers.
>>
>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Cc: Marcel Partap <mpartap-hi6Y0CQ0nG0@public.gmane.org>
>> Cc: Michael Scott <michael.scott-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> Cc: Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
>> ---
>>
>> Changes since v2:
>>
>> - Simplify things further by using channel based indexing and
>> remove more drivers specific enumerations
>>
>> Changes since v1:
>>
>> - Fix numerous issues pointed out by Peter Meerwald-Stadler
>> <pmeerw-jW+XmwGofnusTnJN9+BGXg@public.gmane.org> and Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>>
>> - Simplify things further by limiting read functions to a
>> single channel instead of a bank and got rid of the driver
>> specific cpcap_adc_conv_type in favor of IIO generic types
>>
>> ---
>> .../devicetree/bindings/iio/adc/cpcap-adc.txt | 18 +
>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Been long enough now that I'm happy to take this.
Thanks for looking at the bindings Rob!
Applied to the togreg branch of iio.git and pushed out as testing
for the autobuilders to play with it.
Jonathan
>
>> drivers/iio/adc/Kconfig | 11 +
>> drivers/iio/adc/Makefile | 1 +
>> drivers/iio/adc/cpcap-adc.c | 1007 ++++++++++++++++++++
>> 4 files changed, 1037 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iio/adc/cpcap-adc.txt
>> create mode 100644 drivers/iio/adc/cpcap-adc.c
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
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> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* Re: [PATCH v3 0/6] bus: brcmstb_gisb: add support for GISBv7 arbiter
From: Mark Rutland @ 2017-03-30 18:19 UTC (permalink / raw)
To: Florian Fainelli
Cc: Doug Berger, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
computersforpeace-Re5JQEeQqe8AvxtiuMwx3w,
gregory.0xf0-Re5JQEeQqe8AvxtiuMwx3w,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
treding-DDmLM1+adcrQT0dZR+AlfA, jonathanh-DDmLM1+adcrQT0dZR+AlfA,
olof-nZhT3qVonbNeoWH0uzbU5w, mirza.krak-Re5JQEeQqe8AvxtiuMwx3w,
suzuki.poulose-5wv7dgnIgG8, bgolaszewski-rdvid1DuHRBWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8
In-Reply-To: <c3182c24-2245-cf2e-32e4-248b8046a30f-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Thu, Mar 30, 2017 at 09:33:32AM -0700, Florian Fainelli wrote:
> On 03/29/2017 05:29 PM, Doug Berger wrote:
> > This patch set contains changes to enable the GISB arbiter driver
> > on the latest ARM64 architecture Set-Top Box chips from Broadcom.
> >
> > Since the ARM64 architecture does not support the hooking of low
> > level fault handlers the driver has been adjusted to depend solely
> > on GISB interrupts and notify events to provide diagnostic
> > messaging. The GISB hardware still triggers bus faults for the
> > processor so the default low-level aborts will occur and will be
> > handled based on the architecture specific kernel implementation.
> >
> > While this tends to obsure the GISB error messaging it is still
> > reasonable so the same approach is applied to the ARM architecture
> > for consistency.
> >
> > The patches also correct some issues with the existing driver
> > and add the new register map for the GISBv7 hardware first
> > appearing in the BCM7278 device.
>
> This all looks great to me, and since there are no more ARM64
> dependencies I can take this via the Broadcom ARM/ARM64 SoC pull requests.
>
> Mark, are you also happy with this v3?
It looks fine by me.
Thanks,
Mark.
--
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^ permalink raw reply
* Re: [PATCH v4 19/23] drivers/fsi: Add GPIO based FSI master
From: Christopher Bostic @ 2017-03-30 18:15 UTC (permalink / raw)
To: Joel Stanley
Cc: Rob Herring, Mark Rutland, Russell King,
rostedt-nx8X9YLhiw1AfugRpC6u6w, mingo-H+wXaHxf7aLQT0dZR+AlfA,
Greg KH, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Linux Kernel Mailing List, Andrew Jeffery, Alistair Popple,
Benjamin Herrenschmidt, Edward A . James, Jeremy Kerr
In-Reply-To: <CACPK8XfOSYPidHF6=psC4mP-tkRyWTu0psdcK6EwA2E6FF53Uw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 3/30/17 12:48 AM, Joel Stanley wrote:
> On Thu, Mar 30, 2017 at 4:13 AM, Christopher Bostic
> <cbostic-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org> wrote:
>> From: Chris Bostic <cbostic-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org>
>>
>> Implement a FSI master using GPIO. Will generate FSI protocol for
>> read and write commands to particular addresses. Sends master command
>> and waits for and decodes a slave response.
>>
>> Includes changes from Edward A. James <eajames-r/Jw6+rmf7HQT0dZR+AlfA@public.gmane.org> and Jeremy
>> Kerr <jk-mnsaURCQ41sdnm+yROfE0A@public.gmane.org>.
>>
>> Signed-off-by: Edward A. James <eajames-r/Jw6+rmf7HQT0dZR+AlfA@public.gmane.org>
>> Signed-off-by: Jeremy Kerr <jk-mnsaURCQ41sdnm+yROfE0A@public.gmane.org>
>> Signed-off-by: Chris Bostic <cbostic-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org>
>> Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
>> ---
>> arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 10 +
>> arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 12 +
>> drivers/fsi/Kconfig | 11 +
>> drivers/fsi/Makefile | 1 +
>> drivers/fsi/fsi-master-gpio.c | 614 ++++++++++++++++++++++++++
>> 5 files changed, 648 insertions(+)
>> create mode 100644 drivers/fsi/fsi-master-gpio.c
>>
>> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
>> index 1d2fc1e..cf7d7d7 100644
>> --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
>> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
>> @@ -29,6 +29,16 @@
>> reg = <0x5f000000 0x01000000>; /* 16M */
>> };
>> };
>> +
>> + gpio-fsi {
>> + compatible = "fsi-master-gpio", "fsi-master";
>> +
>> + clock-gpios = <&gpio ASPEED_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
>> + data-gpios = <&gpio ASPEED_GPIO(A, 5) GPIO_ACTIVE_HIGH>;
>> + mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
>> + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
>> + trans-gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
>> + };
>> };
>>
>> &uart5 {
>> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
>> index 7a3b2b5..2fd7db7 100644
>> --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
>> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
>> @@ -29,6 +29,18 @@
>> reg = <0xbf000000 0x01000000>; /* 16M */
>> };
>> };
>> +
>> + gpio-fsi {
>> + compatible = "fsi-master-gpio", "fsi-master";
>> +
>> + status = "okay";
>> +
>> + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
>> + data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
>> + mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
>> + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
>> + trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
>> + };
>> };
> I'm not sure what happened here. The changes to the device trees
> should not be in this patch.
Where would you recommend they be placed? I assume we want them
somewhere in the patch set.
Thanks,
Chris
> Cheers,
>
> Joel
>
>> &uart5 {
>> diff --git a/drivers/fsi/Kconfig b/drivers/fsi/Kconfig
>> index 04c1a0e..9cf8345 100644
>> --- a/drivers/fsi/Kconfig
>> +++ b/drivers/fsi/Kconfig
>> @@ -9,4 +9,15 @@ config FSI
>> ---help---
>> FSI - the FRU Support Interface - is a simple bus for low-level
>> access to POWER-based hardware.
>> +
>> +if FSI
>> +
>> +config FSI_MASTER_GPIO
>> + tristate "GPIO-based FSI master"
>> + depends on FSI && GPIOLIB
>> + ---help---
>> + This option enables a FSI master driver using GPIO lines.
>> +
>> +endif
>> +
>> endmenu
>> diff --git a/drivers/fsi/Makefile b/drivers/fsi/Makefile
>> index db0e5e7..ed28ac0 100644
>> --- a/drivers/fsi/Makefile
>> +++ b/drivers/fsi/Makefile
>> @@ -1,2 +1,3 @@
>>
>> obj-$(CONFIG_FSI) += fsi-core.o
>> +obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o
>> diff --git a/drivers/fsi/fsi-master-gpio.c b/drivers/fsi/fsi-master-gpio.c
>> new file mode 100644
>> index 0000000..0bf5caa
>> --- /dev/null
>> +++ b/drivers/fsi/fsi-master-gpio.c
>> @@ -0,0 +1,614 @@
>> +/*
>> + * A FSI master controller, using a simple GPIO bit-banging interface
>> + */
>> +
>> +#include <linux/platform_device.h>
>> +#include <linux/gpio/consumer.h>
>> +#include <linux/module.h>
>> +#include <linux/delay.h>
>> +#include <linux/fsi.h>
>> +#include <linux/device.h>
>> +#include <linux/io.h>
>> +#include <linux/slab.h>
>> +#include <linux/spinlock.h>
>> +
>> +#include "fsi-master.h"
>> +
>> +#define FSI_GPIO_STD_DLY 1 /* Standard pin delay in nS */
>> +#define FSI_ECHO_DELAY_CLOCKS 16 /* Number clocks for echo delay */
>> +#define FSI_PRE_BREAK_CLOCKS 50 /* Number clocks to prep for break */
>> +#define FSI_BREAK_CLOCKS 256 /* Number of clocks to issue break */
>> +#define FSI_POST_BREAK_CLOCKS 16000 /* Number clocks to set up cfam */
>> +#define FSI_INIT_CLOCKS 5000 /* Clock out any old data */
>> +#define FSI_GPIO_STD_DELAY 10 /* Standard GPIO delay in nS */
>> + /* todo: adjust down as low as */
>> + /* possible or eliminate */
>> +#define FSI_GPIO_CMD_DPOLL 0x2
>> +#define FSI_GPIO_CMD_TERM 0x3f
>> +#define FSI_GPIO_CMD_ABS_AR 0x4
>> +
>> +#define FSI_GPIO_DPOLL_CLOCKS 100 /* < 21 will cause slave to hang */
>> +
>> +/* Bus errors */
>> +#define FSI_GPIO_ERR_BUSY 1 /* Slave stuck in busy state */
>> +#define FSI_GPIO_RESP_ERRA 2 /* Any (misc) Error */
>> +#define FSI_GPIO_RESP_ERRC 3 /* Slave reports master CRC error */
>> +#define FSI_GPIO_MTOE 4 /* Master time out error */
>> +#define FSI_GPIO_CRC_INVAL 5 /* Master reports slave CRC error */
>> +
>> +/* Normal slave responses */
>> +#define FSI_GPIO_RESP_BUSY 1
>> +#define FSI_GPIO_RESP_ACK 0
>> +#define FSI_GPIO_RESP_ACKD 4
>> +
>> +#define FSI_GPIO_MAX_BUSY 100
>> +#define FSI_GPIO_MTOE_COUNT 1000
>> +#define FSI_GPIO_DRAIN_BITS 20
>> +#define FSI_GPIO_CRC_SIZE 4
>> +#define FSI_GPIO_MSG_ID_SIZE 2
>> +#define FSI_GPIO_MSG_RESPID_SIZE 2
>> +#define FSI_GPIO_PRIME_SLAVE_CLOCKS 100
>> +
>> +static DEFINE_SPINLOCK(fsi_gpio_cmd_lock); /* lock around fsi commands */
>> +
>> +struct fsi_master_gpio {
>> + struct fsi_master master;
>> + struct device *dev;
>> + struct gpio_desc *gpio_clk;
>> + struct gpio_desc *gpio_data;
>> + struct gpio_desc *gpio_trans; /* Voltage translator */
>> + struct gpio_desc *gpio_enable; /* FSI enable */
>> + struct gpio_desc *gpio_mux; /* Mux control */
>> +};
>> +
>> +#define to_fsi_master_gpio(m) container_of(m, struct fsi_master_gpio, master)
>> +
>> +struct fsi_gpio_msg {
>> + uint64_t msg;
>> + uint8_t bits;
>> +};
>> +
>> +static void clock_toggle(struct fsi_master_gpio *master, int count)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < count; i++) {
>> + ndelay(FSI_GPIO_STD_DLY);
>> + gpiod_set_value(master->gpio_clk, 0);
>> + ndelay(FSI_GPIO_STD_DLY);
>> + gpiod_set_value(master->gpio_clk, 1);
>> + }
>> +}
>> +
>> +static int sda_in(struct fsi_master_gpio *master)
>> +{
>> + int in;
>> +
>> + ndelay(FSI_GPIO_STD_DLY);
>> + in = gpiod_get_value(master->gpio_data);
>> + return in ? 1 : 0;
>> +}
>> +
>> +static void sda_out(struct fsi_master_gpio *master, int value)
>> +{
>> + gpiod_set_value(master->gpio_data, value);
>> +}
>> +
>> +static void set_sda_input(struct fsi_master_gpio *master)
>> +{
>> + gpiod_direction_input(master->gpio_data);
>> + if (master->gpio_trans)
>> + gpiod_set_value(master->gpio_trans, 0);
>> +}
>> +
>> +static void set_sda_output(struct fsi_master_gpio *master, int value)
>> +{
>> + if (master->gpio_trans)
>> + gpiod_set_value(master->gpio_trans, 1);
>> + gpiod_direction_output(master->gpio_data, value);
>> +}
>> +
>> +static void clock_zeros(struct fsi_master_gpio *master, int count)
>> +{
>> + set_sda_output(master, 1);
>> + clock_toggle(master, count);
>> +}
>> +
>> +static void serial_in(struct fsi_master_gpio *master, struct fsi_gpio_msg *msg,
>> + uint8_t num_bits)
>> +{
>> + uint8_t bit, in_bit;
>> +
>> + set_sda_input(master);
>> +
>> + for (bit = 0; bit < num_bits; bit++) {
>> + clock_toggle(master, 1);
>> + in_bit = sda_in(master);
>> + msg->msg <<= 1;
>> + msg->msg |= ~in_bit & 0x1; /* Data is negative active */
>> + }
>> + msg->bits += num_bits;
>> +}
>> +
>> +static void serial_out(struct fsi_master_gpio *master,
>> + const struct fsi_gpio_msg *cmd)
>> +{
>> + uint8_t bit;
>> + uint64_t msg = ~cmd->msg; /* Data is negative active */
>> + uint64_t sda_mask = 0x1ULL << (cmd->bits - 1);
>> + uint64_t last_bit = ~0;
>> + int next_bit;
>> +
>> + if (!cmd->bits) {
>> + dev_warn(master->dev, "trying to output 0 bits\n");
>> + return;
>> + }
>> + set_sda_output(master, 0);
>> +
>> + /* Send the start bit */
>> + sda_out(master, 0);
>> + clock_toggle(master, 1);
>> +
>> + /* Send the message */
>> + for (bit = 0; bit < cmd->bits; bit++) {
>> + next_bit = (msg & sda_mask) >> (cmd->bits - 1);
>> + if (last_bit ^ next_bit) {
>> + sda_out(master, next_bit);
>> + last_bit = next_bit;
>> + }
>> + clock_toggle(master, 1);
>> + msg <<= 1;
>> + }
>> +}
>> +
>> +static void msg_push_bits(struct fsi_gpio_msg *msg, uint64_t data, int bits)
>> +{
>> + msg->msg <<= bits;
>> + msg->msg |= data & ((1ull << bits) - 1);
>> + msg->bits += bits;
>> +}
>> +
>> +static void msg_push_crc(struct fsi_gpio_msg *msg)
>> +{
>> + uint8_t crc;
>> + int top;
>> +
>> + top = msg->bits & 0x3;
>> +
>> + /* start bit, and any non-aligned top bits */
>> + crc = fsi_crc4(0,
>> + 1 << top | msg->msg >> (msg->bits - top),
>> + top + 1);
>> +
>> + /* aligned bits */
>> + crc = fsi_crc4(crc, msg->msg, msg->bits - top);
>> +
>> + msg_push_bits(msg, crc, 4);
>> +}
>> +
>> +static void build_abs_ar_command(struct fsi_gpio_msg *cmd,
>> + uint8_t id, uint32_t addr, size_t size, const void *data)
>> +{
>> + bool write = !!data;
>> + uint8_t ds;
>> + int i;
>> +
>> + cmd->bits = 0;
>> + cmd->msg = 0;
>> +
>> + msg_push_bits(cmd, id, 2);
>> + msg_push_bits(cmd, FSI_GPIO_CMD_ABS_AR, 3);
>> + msg_push_bits(cmd, write ? 0 : 1, 1);
>> +
>> + /*
>> + * The read/write size is encoded in the lower bits of the address
>> + * (as it must be naturally-aligned), and the following ds bit.
>> + *
>> + * size addr:1 addr:0 ds
>> + * 1 x x 0
>> + * 2 x 0 1
>> + * 4 0 1 1
>> + *
>> + */
>> + ds = size > 1 ? 1 : 0;
>> + addr &= ~(size - 1);
>> + if (size == 4)
>> + addr |= 1;
>> +
>> + msg_push_bits(cmd, addr & ((1 << 21) - 1), 21);
>> + msg_push_bits(cmd, ds, 1);
>> + for (i = 0; write && i < size; i++)
>> + msg_push_bits(cmd, ((uint8_t *)data)[i], 8);
>> +
>> + msg_push_crc(cmd);
>> +}
>> +
>> +static void build_dpoll_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)
>> +{
>> + cmd->bits = 0;
>> + cmd->msg = 0;
>> +
>> + msg_push_bits(cmd, slave_id, 2);
>> + msg_push_bits(cmd, FSI_GPIO_CMD_DPOLL, 3);
>> + msg_push_crc(cmd);
>> +}
>> +
>> +static void echo_delay(struct fsi_master_gpio *master)
>> +{
>> + set_sda_output(master, 1);
>> + clock_toggle(master, FSI_ECHO_DELAY_CLOCKS);
>> +}
>> +
>> +static void build_term_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)
>> +{
>> + cmd->bits = 0;
>> + cmd->msg = 0;
>> +
>> + msg_push_bits(cmd, slave_id, 2);
>> + msg_push_bits(cmd, FSI_GPIO_CMD_TERM, 6);
>> + msg_push_crc(cmd);
>> +}
>> +
>> +/*
>> + * Store information on master errors so handler can detect and clean
>> + * up the bus
>> + */
>> +static void fsi_master_gpio_error(struct fsi_master_gpio *master, int error)
>> +{
>> +
>> +}
>> +
>> +static int read_one_response(struct fsi_master_gpio *master,
>> + uint8_t data_size, struct fsi_gpio_msg *msgp, uint8_t *tagp)
>> +{
>> + struct fsi_gpio_msg msg;
>> + uint8_t id, tag;
>> + uint32_t crc;
>> + int i;
>> +
>> + /* wait for the start bit */
>> + for (i = 0; i < FSI_GPIO_MTOE_COUNT; i++) {
>> + msg.bits = 0;
>> + msg.msg = 0;
>> + serial_in(master, &msg, 1);
>> + if (msg.msg)
>> + break;
>> + }
>> + if (i >= FSI_GPIO_MTOE_COUNT) {
>> + dev_dbg(master->dev,
>> + "Master time out waiting for response\n");
>> + fsi_master_gpio_error(master, FSI_GPIO_MTOE);
>> + return -EIO;
>> + }
>> +
>> + msg.bits = 0;
>> + msg.msg = 0;
>> +
>> + /* Read slave ID & response tag */
>> + serial_in(master, &msg, 4);
>> +
>> + id = (msg.msg >> FSI_GPIO_MSG_RESPID_SIZE) & 0x3;
>> + tag = msg.msg & 0x3;
>> +
>> + /* if we have an ACK, and we're expecting data, clock the
>> + * data in too
>> + */
>> + if (tag == FSI_GPIO_RESP_ACK && data_size)
>> + serial_in(master, &msg, data_size * 8);
>> +
>> + /* read CRC */
>> + serial_in(master, &msg, FSI_GPIO_CRC_SIZE);
>> +
>> + /* we have a whole message now; check CRC */
>> + crc = fsi_crc4(0, 1, 1);
>> + crc = fsi_crc4(crc, msg.msg, msg.bits);
>> + if (crc) {
>> + dev_dbg(master->dev, "ERR response CRC\n");
>> + fsi_master_gpio_error(master, FSI_GPIO_CRC_INVAL);
>> + return -EIO;
>> + }
>> +
>> + if (msgp)
>> + *msgp = msg;
>> + if (tagp)
>> + *tagp = tag;
>> +
>> + return 0;
>> +}
>> +
>> +static int issue_term(struct fsi_master_gpio *master, uint8_t slave)
>> +{
>> + struct fsi_gpio_msg cmd;
>> + uint8_t tag;
>> + int rc;
>> +
>> + build_term_command(&cmd, slave);
>> + serial_out(master, &cmd);
>> + echo_delay(master);
>> +
>> + rc = read_one_response(master, 0, NULL, &tag);
>> + if (rc) {
>> + dev_err(master->dev,
>> + "TERM failed; lost communication with slave\n");
>> + return -EIO;
>> + } else if (tag != FSI_GPIO_RESP_ACK) {
>> + dev_err(master->dev, "TERM failed; response %d\n", tag);
>> + return -EIO;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int poll_for_response(struct fsi_master_gpio *master,
>> + uint8_t slave, uint8_t size, void *data)
>> +{
>> + struct fsi_gpio_msg response, cmd;
>> + int busy_count = 0, rc, i;
>> + uint8_t tag;
>> +
>> +retry:
>> + rc = read_one_response(master, size, &response, &tag);
>> + if (rc)
>> + return rc;
>> +
>> + switch (tag) {
>> + case FSI_GPIO_RESP_ACK:
>> + if (size && data) {
>> + uint64_t val = response.msg;
>> + /* clear crc & mask */
>> + val >>= 4;
>> + val &= (1ull << (size * 8)) - 1;
>> +
>> + for (i = 0; i < size; i++) {
>> + ((uint8_t *)data)[size-i-1] =
>> + val & 0xff;
>> + val >>= 8;
>> + }
>> + }
>> + break;
>> + case FSI_GPIO_RESP_BUSY:
>> + /*
>> + * Its necessary to clock slave before issuing
>> + * d-poll, not indicated in the hardware protocol
>> + * spec. < 20 clocks causes slave to hang, 21 ok.
>> + */
>> + clock_zeros(master, FSI_GPIO_DPOLL_CLOCKS);
>> + if (busy_count++ < FSI_GPIO_MAX_BUSY) {
>> + build_dpoll_command(&cmd, slave);
>> + serial_out(master, &cmd);
>> + echo_delay(master);
>> + goto retry;
>> + }
>> + dev_warn(master->dev,
>> + "ERR slave is stuck in busy state, issuing TERM\n");
>> + issue_term(master, slave);
>> + rc = -EIO;
>> + break;
>> +
>> + case FSI_GPIO_RESP_ERRA:
>> + case FSI_GPIO_RESP_ERRC:
>> + dev_dbg(master->dev, "ERR%c received: 0x%x\n",
>> + tag == FSI_GPIO_RESP_ERRA ? 'A' : 'C',
>> + (int)response.msg);
>> + fsi_master_gpio_error(master, response.msg);
>> + rc = -EIO;
>> + break;
>> + }
>> +
>> + /* Clock the slave enough to be ready for next operation */
>> + clock_zeros(master, FSI_GPIO_PRIME_SLAVE_CLOCKS);
>> + return rc;
>> +}
>> +
>> +static int fsi_master_gpio_xfer(struct fsi_master_gpio *master, uint8_t slave,
>> + struct fsi_gpio_msg *cmd, size_t resp_len, void *resp)
>> +{
>> + unsigned long flags;
>> + int rc;
>> +
>> + spin_lock_irqsave(&fsi_gpio_cmd_lock, flags);
>> + serial_out(master, cmd);
>> + echo_delay(master);
>> + rc = poll_for_response(master, slave, resp_len, resp);
>> + spin_unlock_irqrestore(&fsi_gpio_cmd_lock, flags);
>> +
>> + return rc;
>> +}
>> +
>> +static int fsi_master_gpio_read(struct fsi_master *_master, int link,
>> + uint8_t id, uint32_t addr, void *val, size_t size)
>> +{
>> + struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
>> + struct fsi_gpio_msg cmd;
>> +
>> + if (link != 0)
>> + return -ENODEV;
>> +
>> + build_abs_ar_command(&cmd, id, addr, size, NULL);
>> + return fsi_master_gpio_xfer(master, id, &cmd, size, val);
>> +}
>> +
>> +static int fsi_master_gpio_write(struct fsi_master *_master, int link,
>> + uint8_t id, uint32_t addr, const void *val, size_t size)
>> +{
>> + struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
>> + struct fsi_gpio_msg cmd;
>> +
>> + if (link != 0)
>> + return -ENODEV;
>> +
>> + build_abs_ar_command(&cmd, id, addr, size, val);
>> + return fsi_master_gpio_xfer(master, id, &cmd, 0, NULL);
>> +}
>> +
>> +static int fsi_master_gpio_term(struct fsi_master *_master,
>> + int link, uint8_t id)
>> +{
>> + struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
>> + struct fsi_gpio_msg cmd;
>> +
>> + if (link != 0)
>> + return -ENODEV;
>> +
>> + build_term_command(&cmd, id);
>> + return fsi_master_gpio_xfer(master, id, &cmd, 0, NULL);
>> +}
>> +
>> +/*
>> + * Issue a break command on link
>> + */
>> +static int fsi_master_gpio_break(struct fsi_master *_master, int link)
>> +{
>> + struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
>> +
>> + if (link != 0)
>> + return -ENODEV;
>> +
>> + set_sda_output(master, 1);
>> + sda_out(master, 1);
>> + clock_toggle(master, FSI_PRE_BREAK_CLOCKS);
>> + sda_out(master, 0);
>> + clock_toggle(master, FSI_BREAK_CLOCKS);
>> + echo_delay(master);
>> + sda_out(master, 1);
>> + clock_toggle(master, FSI_POST_BREAK_CLOCKS);
>> +
>> + /* Wait for logic reset to take effect */
>> + udelay(200);
>> +
>> + return 0;
>> +}
>> +
>> +static void fsi_master_gpio_init(struct fsi_master_gpio *master)
>> +{
>> + if (master->gpio_mux)
>> + gpiod_direction_output(master->gpio_mux, 1);
>> + if (master->gpio_trans)
>> + gpiod_direction_output(master->gpio_trans, 1);
>> + if (master->gpio_enable)
>> + gpiod_direction_output(master->gpio_enable, 1);
>> + gpiod_direction_output(master->gpio_clk, 1);
>> + gpiod_direction_output(master->gpio_data, 1);
>> +
>> + /* todo: evaluate if clocks can be reduced */
>> + clock_zeros(master, FSI_INIT_CLOCKS);
>> +}
>> +
>> +static int fsi_master_gpio_link_enable(struct fsi_master *_master, int link)
>> +{
>> + struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
>> +
>> + if (link != 0)
>> + return -ENODEV;
>> + if (master->gpio_enable)
>> + gpiod_set_value(master->gpio_enable, 1);
>> +
>> + return 0;
>> +}
>> +
>> +static void fsi_master_gpio_release(struct device *dev)
>> +{
>> + struct fsi_master_gpio *master = to_fsi_master_gpio(
>> + dev_to_fsi_master(dev));
>> +
>> + kfree(master);
>> +}
>> +
>> +static int fsi_master_gpio_probe(struct platform_device *pdev)
>> +{
>> + struct fsi_master_gpio *master;
>> + struct gpio_desc *gpio;
>> +
>> + master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
>> + if (!master)
>> + return -ENOMEM;
>> +
>> + master->dev = &pdev->dev;
>> + master->master.dev.parent = master->dev;
>> + master->master.dev.release = fsi_master_gpio_release;
>> +
>> + gpio = devm_gpiod_get(&pdev->dev, "clock", 0);
>> + if (IS_ERR(gpio)) {
>> + dev_err(&pdev->dev, "failed to get clock gpio\n");
>> + return PTR_ERR(gpio);
>> + }
>> + master->gpio_clk = gpio;
>> +
>> + gpio = devm_gpiod_get(&pdev->dev, "data", 0);
>> + if (IS_ERR(gpio)) {
>> + dev_err(&pdev->dev, "failed to get data gpio\n");
>> + return PTR_ERR(gpio);
>> + }
>> + master->gpio_data = gpio;
>> +
>> + /* Optional GPIOs */
>> + gpio = devm_gpiod_get_optional(&pdev->dev, "trans", 0);
>> + if (IS_ERR(gpio)) {
>> + dev_err(&pdev->dev, "failed to get trans gpio\n");
>> + return PTR_ERR(gpio);
>> + }
>> + master->gpio_trans = gpio;
>> +
>> + gpio = devm_gpiod_get_optional(&pdev->dev, "enable", 0);
>> + if (IS_ERR(gpio)) {
>> + dev_err(&pdev->dev, "failed to get enable gpio\n");
>> + return PTR_ERR(gpio);
>> + }
>> + master->gpio_enable = gpio;
>> +
>> + gpio = devm_gpiod_get_optional(&pdev->dev, "mux", 0);
>> + if (IS_ERR(gpio)) {
>> + dev_err(&pdev->dev, "failed to get mux gpio\n");
>> + return PTR_ERR(gpio);
>> + }
>> + master->gpio_mux = gpio;
>> +
>> + master->master.n_links = 1;
>> + master->master.read = fsi_master_gpio_read;
>> + master->master.write = fsi_master_gpio_write;
>> + master->master.term = fsi_master_gpio_term;
>> + master->master.send_break = fsi_master_gpio_break;
>> + master->master.link_enable = fsi_master_gpio_link_enable;
>> + platform_set_drvdata(pdev, master);
>> +
>> + fsi_master_gpio_init(master);
>> +
>> + fsi_master_register(&master->master);
>> +
>> + return 0;
>> +}
>> +
>> +
>> +static int fsi_master_gpio_remove(struct platform_device *pdev)
>> +{
>> + struct fsi_master_gpio *master = platform_get_drvdata(pdev);
>> +
>> + devm_gpiod_put(&pdev->dev, master->gpio_clk);
>> + devm_gpiod_put(&pdev->dev, master->gpio_data);
>> + if (master->gpio_trans)
>> + devm_gpiod_put(&pdev->dev, master->gpio_trans);
>> + if (master->gpio_enable)
>> + devm_gpiod_put(&pdev->dev, master->gpio_enable);
>> + if (master->gpio_mux)
>> + devm_gpiod_put(&pdev->dev, master->gpio_mux);
>> + fsi_master_unregister(&master->master);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id fsi_master_gpio_match[] = {
>> + { .compatible = "fsi-master-gpio" },
>> + { },
>> +};
>> +
>> +static struct platform_driver fsi_master_gpio_driver = {
>> + .driver = {
>> + .name = "fsi-master-gpio",
>> + .of_match_table = fsi_master_gpio_match,
>> + },
>> + .probe = fsi_master_gpio_probe,
>> + .remove = fsi_master_gpio_remove,
>> +};
>> +
>> +module_platform_driver(fsi_master_gpio_driver);
>> +MODULE_LICENSE("GPL");
>> --
>> 1.8.2.2
>>
--
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^ permalink raw reply
* Re: [PATCH V1 1/1] mtd: mtk-nor: set controller to 4B mode with large capacity flash
From: Cyrille Pitchen @ 2017-03-30 17:40 UTC (permalink / raw)
To: Guochun Mao, Boris Brezillon, Marek Vasut
Cc: Mark Rutland, devicetree, Richard Weinberger, Russell King,
linux-kernel, Rob Herring, linux-mtd, Matthias Brugger,
linux-mediatek, Cyrille Pitchen, David Woodhouse,
linux-arm-kernel
In-Reply-To: <1490862222-723-2-git-send-email-guochun.mao@mediatek.com>
Hi Guochun,
Le 30/03/2017 à 10:23, Guochun Mao a écrit :
> when nor's size larger than 16MByte, nor and controller should
> enter 4Byte mode simultaneously.
>
> Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
> ---
> drivers/mtd/spi-nor/mtk-quadspi.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/mtk-quadspi.c b/drivers/mtd/spi-nor/mtk-quadspi.c
> index e661877..05cd8a8 100644
> --- a/drivers/mtd/spi-nor/mtk-quadspi.c
> +++ b/drivers/mtd/spi-nor/mtk-quadspi.c
> @@ -369,6 +369,13 @@ static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
> /* We only handle 1 byte */
> ret = mt8173_nor_wr_sr(mt8173_nor, *buf);
> break;
> + case SPINOR_OP_EN4B:
> + /* Set nor controller to 4-byte address mode,
> + * and simultaneously set nor flash.
> + * This case should cooperate with default operation.
> + */
> + writeb(readb(mt8173_nor->base + MTK_NOR_DUAL_REG) | 0x10,
> + mt8173_nor->base + MTK_NOR_DUAL_REG);
This is not good: you should check in both mt8173_nor_read() and
mt8173_nor_write() whether nor->addr_width is either 3 or 4.
from include/linux/mtd/spi-nor.h:
* @addr_width: number of address bytes
Besides SPI commands using an op code from 4-byte address instruction
set always carry a 4-byte address. They can be used directly, without
sending the SPINOR_OP_EN4B before. So you cannot assume that addresses
will be 4-byte long only if your SPI controller driver has seen a
SPINOR_OP_EN4B command before. This assumption is wrong.
SPI controller driver should never check SPINOR_OP_* op codes like this.
Then, testing SPINOR_OP_RDSR from mt8173_nor_read_reg() or
SPINOR_OP_WRSR from mt8173_nor_write_reg() is not a good practice too:
op codes may change depending on the memory manufacturer. So testing op
code values like you do can work with some memories but maybe not all.
Finally, don't use 0x10, please define a macro instead.
Best regards,
Cyrille
> default:
> ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0);
> if (ret)
>
^ permalink raw reply
* [RFC] [media] imx: assume MEDIA_ENT_F_ATV_DECODER entities output video on pad 1
From: Philipp Zabel @ 2017-03-30 17:25 UTC (permalink / raw)
To: Steve Longerbeam
Cc: robh+dt, mark.rutland, shawnguo, kernel, fabio.estevam, linux,
mchehab, hverkuil, nick, markus.heiser, laurent.pinchart+renesas,
bparrot, geert, arnd, sudipm.mukherjee, minghsiu.tsai,
tiffany.lin, jean-christophe.trotin, horms+renesas,
niklas.soderlund+renesas, robert.jarzmik, songjun.wu,
andrew-ct.chen, gregkh, shuah, sakari.ailus, pavel, devicetree,
linux-kernel, linux-arm-kernel, linux-media
In-Reply-To: <1490661656-10318-20-git-send-email-steve_longerbeam@mentor.com>
The TVP5150 DT bindings specify a single output port (port 0) that
corresponds to the video output pad (pad 1, DEMOD_PAD_VID_OUT).
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
I'm trying to get this to work with a TVP5150 analog TV decoder, and the
first problem is that this device doesn't have pad 0 as its single
output pad. Instead, as a MEDIA_ENT_F_ATV_DECODER entity, it has for
pads (input, video out, vbi out, audio out), and video out is pad 1,
whereas the device tree only defines a single port (0).
---
drivers/staging/media/imx/imx-media-dev.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/staging/media/imx/imx-media-dev.c b/drivers/staging/media/imx/imx-media-dev.c
index 17e2386a3ca3a..c52d6ca797965 100644
--- a/drivers/staging/media/imx/imx-media-dev.c
+++ b/drivers/staging/media/imx/imx-media-dev.c
@@ -267,6 +267,15 @@ static int imx_media_create_link(struct imx_media_dev *imxmd,
source_pad = link->local_pad;
sink_pad = link->remote_pad;
+ /*
+ * If the source subdev is an analog video decoder with a single source
+ * port, assume that this port 0 corresponds to the DEMOD_PAD_VID_OUT
+ * entity pad.
+ */
+ if (source->entity.function == MEDIA_ENT_F_ATV_DECODER &&
+ local_sd->num_sink_pads == 0 && local_sd->num_src_pads == 1)
+ source_pad = DEMOD_PAD_VID_OUT;
+
v4l2_info(&imxmd->v4l2_dev, "%s: %s:%d -> %s:%d\n", __func__,
source->name, source_pad, sink->name, sink_pad);
--
2.11.0
^ permalink raw reply related
* Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support
From: Gregory CLEMENT @ 2017-03-30 16:57 UTC (permalink / raw)
To: Linus Walleij
Cc: linux-gpio@vger.kernel.org, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Thomas Petazzoni,
linux-arm-kernel@lists.infradead.org, Rob Herring,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Nadav Haklai, Victor Gu, Marcin Wojtas, Wilson Ding, Hua Jing,
Neta Zur Hershkovits
In-Reply-To: <CACRpkdYA9xq3TmW-=0+cxdeBcq6v3HAFf3f5E-FAvUpGZqns3g@mail.gmail.com>
Hi Linus,
On mer., mars 29 2017, Linus Walleij <linus.walleij@linaro.org> wrote:
>>> It has irq_create_mapping(gpiochip->irqdomain, offset); that get
>>> called for every IRQ, and that will eventually call irq_of_parse_and_map()
>>> if the IRQs are defined in the device tree. (IIRC)
>>
>> When I followed the functions called I never find a call to
>> irq_of_parse_and_map(), the closer things related to device tree I found
>> was:
>> "virq = irq_domain_alloc_descs(-1, 1, hwirq, of_node_to_nid(of_node),
>> NULL);"
>> http://elixir.free-electrons.com/source/kernel/irq/irqdomain.c?v=4.11-rc4#L507
>
> I don't know if I'm rambling or what. I'm pretty sure it gets called, maybe
> even earlier, like when the DT is parsed for the platform. We have so many
> drivers not seemingly needing this, but if your driver needs it, all others
> may need to be fixed too.
>
> Can you put a print in irq_of_parse_and_map() and see what happens?
So if I don't call it explicitly in my driver, then this function is
never called for the gpio.
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH] ARM: dts: armada-385-linksys: disk-activity trigger for all
From: Ralph Sennhauser @ 2017-03-30 16:54 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Ralph Sennhauser, Jason Cooper, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Commit a4ee7e18d808 ("ARM: dts: armada: Add default trigger for sata
led") adds the default trigger to individual boards, move it to
armada-385-linksys.dtsi which effectively enables the definition for
the WRT1900ACS (Shelby) as well as for future boards.
Signed-off-by: Ralph Sennhauser <ralph.sennhauser-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/armada-385-linksys-caiman.dts | 1 -
arch/arm/boot/dts/armada-385-linksys-cobra.dts | 1 -
arch/arm/boot/dts/armada-385-linksys.dtsi | 1 +
3 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
index a1b6e68..f3cee91 100644
--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
@@ -109,7 +109,6 @@
sata {
label = "caiman:white:sata";
- linux,default-trigger = "disk-activity";
};
};
};
diff --git a/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
index a1a75af..1110718 100644
--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
@@ -109,7 +109,6 @@
sata {
label = "cobra:white:sata";
- linux,default-trigger = "disk-activity";
};
};
};
diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi
index aa0d225..2306c45 100644
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -320,6 +320,7 @@
sata {
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
default-state = "off";
+ linux,default-trigger = "disk-activity";
};
};
--
2.10.2
--
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^ permalink raw reply related
* Re: [PATCH v3 00/37] mtd: nand: denali: 2nd round of Denali NAND IP patch bomb
From: Boris Brezillon @ 2017-03-30 16:38 UTC (permalink / raw)
To: Masahiro Yamada
Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Enrico Jorns,
Artem Bityutskiy, Dinh Nguyen, Marek Vasut, Graham Moore,
David Woodhouse, Masami Hiramatsu, Chuanxiao Dong, Jassi Brar,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Brian Norris,
Richard Weinberger, Cyrille Pitchen, Rob Herring, Mark Rutland
In-Reply-To: <1490856383-31560-1-git-send-email-yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
On Thu, 30 Mar 2017 15:45:46 +0900
Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org> wrote:
> This driver includes many problems.
>
> One of the biggest one is a bunch of hard-coded parameters. This IP
> has many parameters that can be customized when a delivery RTL is
> generated. However, this driver was upstreamed by Intel, with
> Intel parameters hard-coded. Later, Altera added denali_dt.c to use
> this driver for embedded boards, but they did not fix the code in
> denali.c So, this driver has never worked. Even some DT bindings
> actually turned out wrong.
>
> There are more problems: [1] The driver just retrieves the OOB area as-is
> whereas the controller uses syndrome page layout. [2] Many NAND chip
> specific parameters are hard-coded in the driver. [3] ONFi devices are
> not working [4] It can not read Bad Block Marker
>
> This patch series intends to solve those problems.
>
> Outstanding changes are:
> - Fix raw/oob callbacks for syndrome page layout
> - Implement setup_data_interface() callback
> - Fix/implement more commands for ONFi devices
> - Allow to skip the driver internal bounce buffer
> - Support PIO in case DMA is not supported
> - Switch from ->cmdfunc over to ->cmd_ctrl
>
> 18 patches were merged at v2.
> Here is the rest of the series.
>
> v1: https://lkml.org/lkml/2016/11/26/144
> v2: https://lkml.org/lkml/2017/3/22/804
>
>
> Masahiro Yamada (37):
> mtd: nand: relax ecc.read_page() return value for uncorrectable ECC
> mtd: nand: denali: allow to override mtd->name from label DT property
> mtd: nand: denali: remove meaningless pipeline read-ahead operation
> mtd: nand: denali: fix bitflips calculation in handle_ecc()
> mtd: nand: denali: fix erased page checking
> mtd: nand: denali: support HW_ECC_FIXUP capability
> mtd: nand: denali_dt: enable HW_ECC_FIXUP for Altera SOCFPGA variant
> mtd: nand: denali: support 64bit capable DMA engine
> mtd: nand: denali_dt: remove dma-mask DT property
> mtd: nand: denali_dt: use pdev instead of ofdev for platform_device
> mtd: nand: denali: allow to override revision number
Applied patches 1 to 11.
> mtd: nand: denali: support 1024 byte ECC step size
> mtd: nand: denali: avoid hard-coding ecc.strength and ecc.bytes
> mtd: nand: denali: support "nand-ecc-strength" DT property
> mtd: nand: denali: remove Toshiba and Hynix specific fixup code
> mtd: nand: denali_dt: add compatible strings for UniPhier SoC variants
> mtd: nand: denali: set NAND_ECC_CUSTOM_PAGE_ACCESS
> mtd: nand: denali: do not propagate NAND_STATUS_FAIL to waitfunc()
> mtd: nand: denali: use BIT() and GENMASK() for register macros
> mtd: nand: denali: remove unneeded find_valid_banks()
> mtd: nand: denali: handle timing parameters by setup_data_interface()
> mtd: nand: denali: rework interrupt handling
> mtd: nand: denali: fix NAND_CMD_STATUS handling
> mtd: nand: denali: fix NAND_CMD_PARAM handling
> mtd: nand: denali: switch over to cmd_ctrl instead of cmdfunc
> mtd: nand: denali: fix bank reset function
> mtd: nand: denali: use interrupt instead of polling for bank reset
> mtd: nand: denali: propagate page to helpers via function argument
> mtd: nand: denali: merge struct nand_buf into struct denali_nand_info
> mtd: nand: denali: use flag instead of register macro for direction
> mtd: nand: denali: fix raw and oob accessors for syndrome page layout
> mtd: nand: denali: support hardware-assisted erased page detection
> mtd: nand: allocate aligned buffers if NAND_OWN_BUFFERS is unset
> mtd: nand: allow drivers to request minimum alignment for passed
> buffer
> mtd: nand: denali: skip driver internal bounce buffer when possible
> mtd: nand: denali: use non-managed kmalloc() for DMA buffer
> mtd: nand: denali: enable bad block table scan
The rest looks almost good, except for a few comments I had on patch
14, 18, 25, 26 and 32.
I'll probably apply 33 and 34 soon.
>
> .../devicetree/bindings/mtd/denali-nand.txt | 24 +-
> drivers/mtd/nand/denali.c | 1971 ++++++++++----------
> drivers/mtd/nand/denali.h | 308 +--
> drivers/mtd/nand/denali_dt.c | 90 +-
> drivers/mtd/nand/denali_pci.c | 10 +-
> drivers/mtd/nand/nand_base.c | 49 +-
> include/linux/mtd/nand.h | 4 +-
> 7 files changed, 1234 insertions(+), 1222 deletions(-)
>
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^ permalink raw reply
* Re: [PATCH v3 0/6] bus: brcmstb_gisb: add support for GISBv7 arbiter
From: Florian Fainelli @ 2017-03-30 16:33 UTC (permalink / raw)
To: Doug Berger, mark.rutland
Cc: robh+dt, computersforpeace, gregory.0xf0, f.fainelli,
bcm-kernel-feedback-list, linus.walleij, treding, jonathanh, olof,
mirza.krak, suzuki.poulose, bgolaszewski, devicetree,
linux-kernel, linux-arm-kernel, catalin.marinas, will.deacon
In-Reply-To: <20170330002914.7371-1-opendmb@gmail.com>
On 03/29/2017 05:29 PM, Doug Berger wrote:
> This patch set contains changes to enable the GISB arbiter driver
> on the latest ARM64 architecture Set-Top Box chips from Broadcom.
>
> Since the ARM64 architecture does not support the hooking of low
> level fault handlers the driver has been adjusted to depend solely
> on GISB interrupts and notify events to provide diagnostic
> messaging. The GISB hardware still triggers bus faults for the
> processor so the default low-level aborts will occur and will be
> handled based on the architecture specific kernel implementation.
>
> While this tends to obsure the GISB error messaging it is still
> reasonable so the same approach is applied to the ARM architecture
> for consistency.
>
> The patches also correct some issues with the existing driver
> and add the new register map for the GISBv7 hardware first
> appearing in the BCM7278 device.
This all looks great to me, and since there are no more ARM64
dependencies I can take this via the Broadcom ARM/ARM64 SoC pull requests.
Mark, are you also happy with this v3?
Thanks Doug!
>
> Changes since v2 at [2]:
> - Removed code associated with enabling the hooking of ARM64
> memory faults as well as the code that hooks them for both
> ARM and ARM64 architectures within the GISB arbiter driver.
> - Created separate notifiers for die and panic events to
> prevent list corruption, and substituted the notifier return
> name for the previous magic number (Thanks Mark!)
>
> Changes since v1 at [1]:
> - Removed code associated with hooking SError handling in favor
> of a registered notifier (Thanks Mark!)
> - Removed an unnecessary explicit cast (Thanks Gregory!)
>
> [1] https://lkml.org/lkml/2017/3/24/413
> [2] https://lkml.org/lkml/2017/3/28/1125
>
> Doug Berger (6):
> bus: brcmstb_gisb: Use register offsets with writes too
> bus: brcmstb_gisb: correct support for 64-bit address output
> bus: brcmstb_gisb: add notifier handling
> bus: brcmstb_gisb: remove low-level ARM hooks
> bus: brcmstb_gisb: enable driver for ARM64 architecture
> bus: brcmstb_gisb: update to support new revision
>
> .../devicetree/bindings/bus/brcm,gisb-arb.txt | 3 +-
> drivers/bus/Kconfig | 2 +-
> drivers/bus/brcmstb_gisb.c | 121 ++++++++++++---------
> 3 files changed, 75 insertions(+), 51 deletions(-)
>
--
Florian
^ permalink raw reply
* Re: [PATCH v6 00/39] i.MX Media Driver
From: Russell King - ARM Linux @ 2017-03-30 16:27 UTC (permalink / raw)
To: Steve Longerbeam
Cc: mark.rutland, andrew-ct.chen, minghsiu.tsai, nick, songjun.wu,
hverkuil, pavel, shuah, devel, markus.heiser, Steve Longerbeam,
robert.jarzmik, geert, p.zabel, linux-media, devicetree, kernel,
arnd, tiffany.lin, bparrot, robh+dt, horms+renesas, mchehab,
laurent.pinchart+renesas, linux-arm-kernel,
niklas.soderlund+renesas, gregkh, linux-kernel,
jean-christophe.trotin, sakari.ailus, fabio.estevam, shawnguo,
sudipm.mukherjee
In-Reply-To: <d715bcdf-b2df-8080-6ab4-854aeace31a8@gmail.com>
On Thu, Mar 30, 2017 at 09:12:29AM -0700, Steve Longerbeam wrote:
>
>
> On 03/30/2017 04:02 AM, Russell King - ARM Linux wrote:
> >This fails at step 1. The removal of the frame interval support now
> >means my setup script fails when trying to set the frame interval on
> >the camera:
> >
> >Enumerating pads and links
> >Setting up format SRGGB8_1X8 816x616 on pad imx219 0-0010/0
> >Format set: SRGGB8_1X8 816x616
> >Setting up frame interval 1/25 on pad imx219 0-0010/0
> >Frame interval set: 1/25
> >Setting up format SRGGB8_1X8 816x616 on pad imx6-mipi-csi2/0
> >Format set: SRGGB8_1X8 816x616
> >Setting up frame interval 1/25 on pad imx6-mipi-csi2/0
> >Unable to set frame interval: Inappropriate ioctl for device (-25)Unable to setup formats: Inappropriate ioctl for device (25)
> >
> >This is because media-ctl tries to propagate it from the imx219 source
> >pad to the csi2 sink pad, and the csi2 now fails that ioctl.
>
> I assume you're using Philipp's frame interval patches to media-ctl.
> Can you make the frame interval propagation optional in those patches?
> I.e. don't error-out with a failure code if the ioctl returns ENOTTY.
Damn, you're right. There's way too much stuff to try and keep track
of with this stuff.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* Re: [PATCH v3 1/7] pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
From: Gregory CLEMENT @ 2017-03-30 16:18 UTC (permalink / raw)
To: Rob Herring
Cc: Linus Walleij, linux-gpio-u79uwXL29TY76Z2rM5mHXA, Jason Cooper,
Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Nadav Haklai, Victor Gu,
Marcin Wojtas, Wilson Ding, Hua Jing, Neta Zur Hershkovits
In-Reply-To: <20170329211105.ype3os6jldsjyrqa@rob-hp-laptop>
Hi Rob,
On mer., mars 29 2017, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>> +GPIO subnode:
>> +
>> +Please refer to gpio.txt in this directory for details of gpio-ranges property
>> +and the common GPIO bindings used by client devices.
>> +
>> +Required properties for gpio driver under the gpio subnode:
>
> Why does this need to be a sub node? You should probably have a
> compatible if it is.
It is needed to be able to have a phandle associated to the gpio. Then
the other node can refer to it.
But if we can do without it I would happy to do it.
>
>> +- interrupts: List of interrupt specifier for the controllers interrupt.
>> +- gpio-controller: Marks the device node as a gpio controller.
>> +- #gpio-cells: Should be 2. The first cell is the GPIO number and the
>> + second cell specifies GPIO flags, as defined in
>> + <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and
>> + GPIO_ACTIVE_LOW flags are supported.
>> +- gpio-ranges: Range of pins managed by the GPIO controller.
>> +
>> +Xtal Clock bindings for Marvell Armada 37xx SoCs
>> +------------------------------------------------
>> +
>> +see Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
>> +
>> +
>> +Example:
>> +pinctrl_sb: pinctrl-sb@18800 {
>
> pinctrl@
OK
>
>> + compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
>> + reg = <0x18800 0x100>, <0x18C00 0x20>;
>> + gpiosb: gpiosb {
>
> gpio@
There is no reg property so we don't use the @
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH v4 2/4] mvebu: xp: Add PWM properties to .dtsi files
From: Ralph Sennhauser @ 2017-03-30 16:14 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Linus Walleij, Thierry Reding, Imre Kaloz, Andrew Lunn,
Alexandre Courbot, Rob Herring, Mark Rutland, Jason Cooper,
Sebastian Hesselbarth, Russell King, linux-pwm, linux-gpio,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <87wpb693az.fsf@free-electrons.com>
On Thu, 30 Mar 2017 17:45:08 +0200
Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
> Hi Ralph,
>
> On lun., mars 27 2017, Ralph Sennhauser <ralph.sennhauser@gmail.com>
> wrote:
>
> The title should start by ARM: dts: mvebu:
>
> If there is no need to have a v5 then I wil take care of modifying the
> title while applying it.
Noted.
>
>
> > From: Andrew Lunn <andrew@lunn.ch>
> >
> > Add properties to the GPIO nodes to allow them to be also used as
> > PWM lines.
> >
> > Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> > URL: https://patchwork.ozlabs.org/patch/427294/
> > [Ralph Sennhauser:
> > * Use new compatible string marvell,armada-370-xp-gpio
> > * Add missing reg-names / #pwm-cell properties to
> > armada-xp-mv78260.dtsi 'gpio1' node]
> > Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
> > ---
> > arch/arm/boot/dts/armada-370.dtsi | 16 +++++++++++-----
> > arch/arm/boot/dts/armada-xp-mv78230.dtsi | 14 ++++++++++----
> > arch/arm/boot/dts/armada-xp-mv78260.dtsi | 16 +++++++++++-----
> > arch/arm/boot/dts/armada-xp-mv78460.dtsi | 16 +++++++++++-----
> > 4 files changed, 43 insertions(+), 19 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/armada-370.dtsi
> > b/arch/arm/boot/dts/armada-370.dtsi index cc011c8..e30b076 100644
> > --- a/arch/arm/boot/dts/armada-370.dtsi
> > +++ b/arch/arm/boot/dts/armada-370.dtsi
> > @@ -137,29 +137,35 @@
> > };
> >
> > gpio0: gpio@18100 {
> > - compatible = "marvell,orion-gpio";
> > - reg = <0x18100 0x40>;
> > + compatible =
> > "marvell,armada-370-xp-gpio";
>
> I think we should keep the "marvell,orion-gpio" too because the
> hardware is still compatible with it. Morever it will allow to use a
> recent dtb with an old kernel.
And it will remain compatible. Apart from not collecting compatible
strings there is no reason to drop them right now, so will add them back
for a (possible) v5.
Thanks
Ralph
^ permalink raw reply
* Re: [PATCH v6 00/39] i.MX Media Driver
From: Steve Longerbeam @ 2017-03-30 16:12 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: mark.rutland, andrew-ct.chen, minghsiu.tsai, sakari.ailus, nick,
songjun.wu, hverkuil, Steve Longerbeam, pavel, robert.jarzmik,
devel, markus.heiser, laurent.pinchart+renesas, shuah, geert,
linux-media, devicetree, kernel, arnd, mchehab, bparrot, robh+dt,
horms+renesas, tiffany.lin, linux-arm-kernel,
niklas.soderlund+renesas, gregkh, linux-kernel,
jean-christophe.trotin, p.zabel, fabio.estevam, shawnguo,
sudipm.mukherjee
In-Reply-To: <20170330110249.GF7909@n2100.armlinux.org.uk>
On 03/30/2017 04:02 AM, Russell King - ARM Linux wrote:
> This fails at step 1. The removal of the frame interval support now
> means my setup script fails when trying to set the frame interval on
> the camera:
>
> Enumerating pads and links
> Setting up format SRGGB8_1X8 816x616 on pad imx219 0-0010/0
> Format set: SRGGB8_1X8 816x616
> Setting up frame interval 1/25 on pad imx219 0-0010/0
> Frame interval set: 1/25
> Setting up format SRGGB8_1X8 816x616 on pad imx6-mipi-csi2/0
> Format set: SRGGB8_1X8 816x616
> Setting up frame interval 1/25 on pad imx6-mipi-csi2/0
> Unable to set frame interval: Inappropriate ioctl for device (-25)Unable to setup formats: Inappropriate ioctl for device (25)
>
> This is because media-ctl tries to propagate it from the imx219 source
> pad to the csi2 sink pad, and the csi2 now fails that ioctl.
I assume you're using Philipp's frame interval patches to media-ctl.
Can you make the frame interval propagation optional in those patches?
I.e. don't error-out with a failure code if the ioctl returns ENOTTY.
Steve
>
> This makes media-ctl return a failure code, which means that it's not
> possible for a script to determine whether the failure was due to the
> camera setup or something else. So, we have to assume that the
> whole command failed.
>
> This is completely broken, and I'm even more convinced that those
> arguing for this behaviour really have not thought it through well
> enough before demanding that this code was removed.
>
> As far as I'm concerned, the end result is completely broken and
> unusable. I'm going to be merging the frame interval support back
> into my test tree, because that's the only sane thing to do.
>
> If v4l2 people want to object to having frame interval support present
> for all subdevs, then _they_ need to make sure that the rest of their
> software conforms to what they're telling people to do.
>
^ permalink raw reply
* Re: [PATCH v5 6/9] coresight: add support for CPU debug module
From: Sudeep Holla @ 2017-03-30 16:04 UTC (permalink / raw)
To: Leo Yan
Cc: Mathieu Poirier, Sudeep Holla, Jonathan Corbet, Rob Herring,
Mark Rutland, Wei Xu, Catalin Marinas, Will Deacon, Andy Gross,
David Brown, Michael Turquette, Stephen Boyd, Guodong Xu,
John Stultz, linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <CANLsYkwPYSvy2xjf8uuvx1WGWpGdMFy7kF=30VbvgW+jDvnFuw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 30/03/17 16:46, Mathieu Poirier wrote:
> On 29 March 2017 at 19:59, Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
>> On Wed, Mar 29, 2017 at 10:55:35AM -0600, Mathieu Poirier wrote:
>>
>> [...]
>>
>>>> So this is why add "idle_constraint" as a central place to control
>>>> power domain for CPU debug purpose and I also think this is more
>>>> friendly for hardware design, e.g. some platforms can enable partial
>>>> low power states to save power and avoid overheat after using this
>>>> driver.
>>>>
>>>> How about you think for this?
>>>
>>> Like Sudeep pointed out we should concentrate on doing the right thing,
>>> that is work with EDPRSR.PU, EDPRCR.COREPURQ and EDPRCR.CORENPDRQ.
>>
>> Agree, and I think we have aligned for this.
>>
>>> Anything outside of that becomes platform specific and can't be handled in
>>> this driver.
>>
>> Sorry I argue a bit for this just want to make things more clear and
>> if can have better method.
>>
>> Though the issue is platform specific, but the code is to seek common
>> method to handle them. So the driver has no any platform specific code.
>
> Seeking a common way to handle platform specific problems doesn't
> scale and will never be encompassing. There will always be a quirk
> somewhere to deal with, hence the idea of keeping things separate.
>
I completely agree and just responded to the original patch.
>>
>> I read again for Suziki's suggestion: "4) Should document the fact that,
>> on some platforms, the user may have to disable CPUidle explicitly to
>> get the driver working. But let us not make it the default. The user
>> with a not so ideal platform could add "nohlt" and get it working."
>
> Suzuki and I are expressing the same view using different words.
>
+1, as I just mentioned on the patch, we can warn user to take action
when this feature gets enabled to get desired result and *nothing more*
than that. Please drop all these pm_qos stuff.
--
Regards,
Sudeep
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^ permalink raw reply
* Re: [PATCH v4 0/4] gpio: mvebu: Add PWM fan support
From: Gregory CLEMENT @ 2017-03-30 16:03 UTC (permalink / raw)
To: Ralph Sennhauser
Cc: Linus Walleij, Thierry Reding, Imre Kaloz, Alexandre Courbot,
Rob Herring, Mark Rutland, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Russell King, linux-pwm, linux-gpio,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20170327194301.1104-1-ralph.sennhauser@gmail.com>
Hi Ralph,
On lun., mars 27 2017, Ralph Sennhauser <ralph.sennhauser@gmail.com> wrote:
[...]
> Andrew Lunn (4):
> gpio: mvebu: Add limited PWM support
> mvebu: xp: Add PWM properties to .dtsi files
> ARM: mvebu: Enable SENSORS_PWM_FAN in defconfig
> mvebu: wrt1900ac: Use pwm-fan rather than gpio-fan
I didn't see any big problem with this 3 patches, I will applied them
once the first one will be applied on the gpio tree or at least acked.
Thanks,
Gregory
>
> .../devicetree/bindings/gpio/gpio-mvebu.txt | 32 ++
> MAINTAINERS | 2 +
> arch/arm/boot/dts/armada-370.dtsi | 16 +-
> arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 +-
> arch/arm/boot/dts/armada-xp-mv78230.dtsi | 14 +-
> arch/arm/boot/dts/armada-xp-mv78260.dtsi | 16 +-
> arch/arm/boot/dts/armada-xp-mv78460.dtsi | 16 +-
> arch/arm/configs/mvebu_v7_defconfig | 2 +
> drivers/gpio/gpio-mvebu.c | 324 ++++++++++++++++++++-
> 9 files changed, 394 insertions(+), 36 deletions(-)
>
> --
> 2.10.2
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH v4 4/4] mvebu: wrt1900ac: Use pwm-fan rather than gpio-fan
From: Gregory CLEMENT @ 2017-03-30 16:01 UTC (permalink / raw)
To: Ralph Sennhauser
Cc: Linus Walleij, Thierry Reding, Imre Kaloz, Andrew Lunn,
Alexandre Courbot, Rob Herring, Mark Rutland, Jason Cooper,
Sebastian Hesselbarth, Russell King,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170327194301.1104-5-ralph.sennhauser-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi Ralph,
On lun., mars 27 2017, Ralph Sennhauser <ralph.sennhauser-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
Here again the title should start with ARM: dts: armada-xp.
As for the other patch if there is no need for a v5 I will fix it while
appliig it.
Thanks,
Gregory
> From: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
>
> The mvebu GPIO driver can also perform PWM on some pins. Use the pwm-fan
> driver to control the fan of the WRT1900AC, giving us finer grained control
> over its speed and hence noise.
>
> Signed-off-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> URL: https://patchwork.ozlabs.org/patch/427291/
> [Ralph Sennhauser: drop flags paramter from pwms, no longer used]
> Signed-off-by: Ralph Sennhauser <ralph.sennhauser-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> index 9efcf59..6d705f5 100644
> --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> @@ -308,13 +308,11 @@
> };
> };
>
> - gpio_fan {
> + pwm_fan {
> /* SUNON HA4010V4-0000-C99 */
> - compatible = "gpio-fan";
> - gpios = <&gpio0 24 0>;
>
> - gpio-fan,speed-map = <0 0
> - 4500 1>;
> + compatible = "pwm-fan";
> + pwms = <&gpio0 24 4000>;
> };
>
> dsa {
> --
> 2.10.2
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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^ permalink raw reply
* [PATCH] mtd: physmap_of: use OF helpers for reading strings
From: Rafał Miłecki @ 2017-03-30 15:58 UTC (permalink / raw)
To: David Woodhouse, Brian Norris, Boris Brezillon, Marek Vasut,
Richard Weinberger, Cyrille Pitchen
Cc: Linus Walleij, Jason Gunthorpe,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rafał Miłecki
From: Rafał Miłecki <rafal-g1n6cQUeyibVItvQsEIGlw@public.gmane.org>
OF core code provides helpers for counting strings and reading them so
use them instead of doing this manually. This simplifies the code a bit.
Signed-off-by: Rafał Miłecki <rafal-g1n6cQUeyibVItvQsEIGlw@public.gmane.org>
---
drivers/mtd/maps/physmap_of.c | 30 ++++++++++--------------------
1 file changed, 10 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/maps/physmap_of.c b/drivers/mtd/maps/physmap_of.c
index 14e8909c9955..62fa6836f218 100644
--- a/drivers/mtd/maps/physmap_of.c
+++ b/drivers/mtd/maps/physmap_of.c
@@ -116,32 +116,22 @@ static const char * const part_probe_types_def[] = {
static const char * const *of_get_probes(struct device_node *dp)
{
- const char *cp;
- int cplen;
- unsigned int l;
- unsigned int count;
const char **res;
+ int count;
- cp = of_get_property(dp, "linux,part-probe", &cplen);
- if (cp == NULL)
+ count = of_property_count_strings(dp, "linux,part-probe");
+ if (count < 0)
return part_probe_types_def;
- count = 0;
- for (l = 0; l != cplen; l++)
- if (cp[l] == 0)
- count++;
-
- res = kzalloc((count + 1)*sizeof(*res), GFP_KERNEL);
+ res = kzalloc((count + 1) * sizeof(*res), GFP_KERNEL);
if (!res)
return NULL;
- count = 0;
- while (cplen > 0) {
- res[count] = cp;
- l = strlen(cp) + 1;
- cp += l;
- cplen -= l;
- count++;
- }
+
+ count = of_property_read_string_array(dp, "linux,part-probe", res,
+ count);
+ if (count < 0)
+ return NULL;
+
return res;
}
--
2.11.0
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^ permalink raw reply related
* Re: [PATCH v5 6/9] coresight: add support for CPU debug module
From: Sudeep Holla @ 2017-03-30 15:56 UTC (permalink / raw)
To: Leo Yan, Jonathan Corbet, Rob Herring, Mark Rutland, Wei Xu,
Catalin Marinas, Will Deacon, Andy Gross, David Brown,
Michael Turquette, Stephen Boyd, Mathieu Poirier, Guodong Xu,
John Stultz, linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
mike.leach-QSEj5FYQhm4dnm+yROfE0A, Suzuki.Po
Cc: Sudeep Holla
In-Reply-To: <1490466197-29163-7-git-send-email-leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On 25/03/17 18:23, Leo Yan wrote:
> Coresight includes debug module and usually the module connects with CPU
> debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
> description for related info in "Part H: External Debug".
>
> Chapter H7 "The Sample-based Profiling Extension" introduces several
> sampling registers, e.g. we can check program counter value with
> combined CPU exception level, secure state, etc. So this is helpful for
> analysis CPU lockup scenarios, e.g. if one CPU has run into infinite
> loop with IRQ disabled. In this case the CPU cannot switch context and
> handle any interrupt (including IPIs), as the result it cannot handle
> SMP call for stack dump.
>
> This patch is to enable coresight debug module, so firstly this driver
> is to bind apb clock for debug module and this is to ensure the debug
> module can be accessed from program or external debugger. And the driver
> uses sample-based registers for debug purpose, e.g. when system triggers
> panic, the driver will dump program counter and combined context
> registers (EDCIDSR, EDVIDSR); by parsing context registers so can
> quickly get to know CPU secure state, exception level, etc.
>
> Some of the debug module registers are located in CPU power domain, so
> this requires the CPU power domain stays on when access related debug
> registers, but the power management for CPU power domain is quite
> dependent on SoC integration for power management. For the platforms
> which with sane power controller implementations, this driver follows
> the method to set EDPRCR to try to pull the CPU out of low power state
> and then set 'no power down request' bit so the CPU has no chance to
> lose power.
>
> If the SoC has not followed up this design well for power management
> controller, the driver introduces module parameter "idle_constraint".
> Setting this parameter for latency requirement in microseconds, finally
> we can constrain all or partial idle states to ensure the CPU power
> domain is enabled, this is a backup method to access coresight CPU
> debug component safely.
>
> Signed-off-by: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> drivers/hwtracing/coresight/Kconfig | 11 +
> drivers/hwtracing/coresight/Makefile | 1 +
> drivers/hwtracing/coresight/coresight-cpu-debug.c | 704 ++++++++++++++++++++++
> 3 files changed, 716 insertions(+)
> create mode 100644 drivers/hwtracing/coresight/coresight-cpu-debug.c
>
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index 130cb21..18d7931 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -89,4 +89,15 @@ config CORESIGHT_STM
> logging useful software events or data coming from various entities
> in the system, possibly running different OSs
>
> +config CORESIGHT_CPU_DEBUG
> + tristate "CoreSight CPU Debug driver"
> + depends on ARM || ARM64
> + depends on DEBUG_FS
> + help
> + This driver provides support for coresight debugging module. This
> + is primarily used to dump sample-based profiling registers when
> + system triggers panic, the driver will parse context registers so
> + can quickly get to know program counter (PC), secure state,
> + exception level, etc.
> +
> endif
> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> index af480d9..433d590 100644
> --- a/drivers/hwtracing/coresight/Makefile
> +++ b/drivers/hwtracing/coresight/Makefile
> @@ -16,3 +16,4 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
> coresight-etm4x-sysfs.o
> obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o
> obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
> +obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
> diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c
> new file mode 100644
> index 0000000..fbec1d1
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c
> @@ -0,0 +1,704 @@
> +/*
> + * Copyright (c) 2017 Linaro Limited. All rights reserved.
> + *
> + * Author: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +#include <linux/amba/bus.h>
> +#include <linux/coresight.h>
> +#include <linux/cpu.h>
> +#include <linux/debugfs.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/pm_qos.h>
> +#include <linux/slab.h>
> +#include <linux/smp.h>
> +#include <linux/types.h>
> +#include <linux/uaccess.h>
> +
> +#include "coresight-priv.h"
> +
> +#define EDPCSR 0x0A0
> +#define EDCIDSR 0x0A4
> +#define EDVIDSR 0x0A8
> +#define EDPCSR_HI 0x0AC
> +#define EDOSLAR 0x300
> +#define EDPRCR 0x310
> +#define EDPRSR 0x314
> +#define EDDEVID1 0xFC4
> +#define EDDEVID 0xFC8
> +
> +#define EDPCSR_PROHIBITED 0xFFFFFFFF
> +
> +/* bits definition for EDPCSR */
> +#ifndef CONFIG_64BIT
> +#define EDPCSR_THUMB BIT(0)
> +#define EDPCSR_ARM_INST_MASK GENMASK(31, 2)
> +#define EDPCSR_THUMB_INST_MASK GENMASK(31, 1)
> +#endif
> +
> +/* bits definition for EDPRCR */
> +#define EDPRCR_COREPURQ BIT(3)
> +#define EDPRCR_CORENPDRQ BIT(0)
> +
> +/* bits definition for EDPRSR */
> +#define EDPRSR_DLK BIT(6)
> +#define EDPRSR_PU BIT(0)
> +
> +/* bits definition for EDVIDSR */
> +#define EDVIDSR_NS BIT(31)
> +#define EDVIDSR_E2 BIT(30)
> +#define EDVIDSR_E3 BIT(29)
> +#define EDVIDSR_HV BIT(28)
> +#define EDVIDSR_VMID GENMASK(7, 0)
> +
> +/*
> + * bits definition for EDDEVID1:PSCROffset
> + *
> + * NOTE: armv8 and armv7 have different definition for the register,
> + * so consolidate the bits definition as below:
> + *
> + * 0b0000 - Sample offset applies based on the instruction state, we
> + * rely on EDDEVID to check if EDPCSR is implemented or not
> + * 0b0001 - No offset applies.
> + * 0b0010 - No offset applies, but do not use in AArch32 mode
> + *
> + */
> +#define EDDEVID1_PCSR_OFFSET_MASK GENMASK(3, 0)
> +#define EDDEVID1_PCSR_OFFSET_INS_SET (0x0)
> +#define EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32 (0x2)
> +
> +/* bits definition for EDDEVID */
> +#define EDDEVID_PCSAMPLE_MODE GENMASK(3, 0)
> +#define EDDEVID_IMPL_NONE (0x0)
> +#define EDDEVID_IMPL_EDPCSR (0x1)
> +#define EDDEVID_IMPL_EDPCSR_EDCIDSR (0x2)
> +#define EDDEVID_IMPL_FULL (0x3)
> +
> +#define DEBUG_WAIT_TIMEOUT 32
> +
> +struct debug_drvdata {
> + void __iomem *base;
> + struct device *dev;
> + int cpu;
> +
> + bool edpcsr_present;
> + bool edcidsr_present;
> + bool edvidsr_present;
> + bool pc_has_offset;
> +
> + u32 eddevid;
> + u32 eddevid1;
> +
> + u32 edpcsr;
> + u32 edpcsr_hi;
> + u32 edprcr;
> + u32 edprsr;
> + u32 edvidsr;
> + u32 edcidsr;
> +};
> +
> +static DEFINE_MUTEX(debug_lock);
> +static DEFINE_PER_CPU(struct debug_drvdata *, debug_drvdata);
> +static int debug_count;
> +static struct dentry *debug_debugfs_dir;
> +
> +static struct pm_qos_request debug_qos_req;
> +static int idle_constraint = PM_QOS_DEFAULT_VALUE;
> +module_param(idle_constraint, int, 0600);
> +MODULE_PARM_DESC(idle_constraint, "Latency requirement in microseconds for CPU "
> + "idle states (default is -1, which means have no limiation "
> + "to CPU idle states; 0 means disabling all idle states; user "
> + "can choose other platform dependent values so can disable "
> + "specific idle states for the platform)");
> +
NACK for this. Why you want the policy inside the driver. You can always
do that from the user-space. I have mentioned it several times now.
What can't you do these ?
1. echo "what_ever_latency_you_need_in_uS" > /dev/cpu_dma_latency
2. echo 1 > /sys/devices/system/cpu/cpu$cpu/cpuidle/state$state/disable
(for all cpus and their states) (1) is definitely simpler way to
disable deeper idle if latency = 0uS
You can always warn user about that when it's enabled via debugfs/sysfs
--
Regards,
Sudeep
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^ permalink raw reply
* Re: [PATCH v5 6/9] coresight: add support for CPU debug module
From: Sudeep Holla @ 2017-03-30 15:47 UTC (permalink / raw)
To: Mike Leach, Leo Yan
Cc: Sudeep Holla, Mathieu Poirier, Jonathan Corbet, Rob Herring,
Mark Rutland, Wei Xu, Catalin Marinas, Will Deacon, Andy Gross,
David Brown, Michael Turquette, Stephen Boyd, Guodong Xu,
John Stultz, linux-doc, linux-kernel, devicetree,
linux-arm-kernel, linux-arm-msm, linux-soc, linux-clk, Suzuki
In-Reply-To: <CAJ9a7VhQRuVOCJkjPc9RANGo=fgA8wjtB65dC5f19ZX22a5FHQ@mail.gmail.com>
On 29/03/17 15:56, Mike Leach wrote:
[...]
>
> No - EDPRCR_COREPURQ and EDPRCR_CORENPDRQ have different semantics and purposes
>
> EDPRCR_COREPURQ is in the debug power domain an is tied to an external
> debug request that should be an input to the external (to the PE)
> system power controller.
> The requirement is that the system power controller powers up the core
> domain and does not power it down while it remains asserted.
>
> EDPRCR_CORENPDRQ is in the core power domain and thus to the specific
> core only. This ensures that any power control software running on
> that core should emulate a power down if this is set to one.
>
> We cannot know the power control design of the system, so the safe
> solution is to set both bits.
>
+1
I agree that's the safe bet.
--
Regards,
Sudeep
^ permalink raw reply
* Re: [PATCH v5 6/9] coresight: add support for CPU debug module
From: Mathieu Poirier @ 2017-03-30 15:46 UTC (permalink / raw)
To: Leo Yan
Cc: Jonathan Corbet, Rob Herring, Mark Rutland, Wei Xu,
Catalin Marinas, Will Deacon, Andy Gross, David Brown,
Michael Turquette, Stephen Boyd, Guodong Xu, John Stultz,
linux-doc, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-arm-msm, linux-soc, linux-clk
In-Reply-To: <20170330015941.GD3038@leoy-linaro>
On 29 March 2017 at 19:59, Leo Yan <leo.yan@linaro.org> wrote:
> On Wed, Mar 29, 2017 at 10:55:35AM -0600, Mathieu Poirier wrote:
>
> [...]
>
>> > So this is why add "idle_constraint" as a central place to control
>> > power domain for CPU debug purpose and I also think this is more
>> > friendly for hardware design, e.g. some platforms can enable partial
>> > low power states to save power and avoid overheat after using this
>> > driver.
>> >
>> > How about you think for this?
>>
>> Like Sudeep pointed out we should concentrate on doing the right thing,
>> that is work with EDPRSR.PU, EDPRCR.COREPURQ and EDPRCR.CORENPDRQ.
>
> Agree, and I think we have aligned for this.
>
>> Anything outside of that becomes platform specific and can't be handled in
>> this driver.
>
> Sorry I argue a bit for this just want to make things more clear and
> if can have better method.
>
> Though the issue is platform specific, but the code is to seek common
> method to handle them. So the driver has no any platform specific code.
Seeking a common way to handle platform specific problems doesn't
scale and will never be encompassing. There will always be a quirk
somewhere to deal with, hence the idea of keeping things separate.
>
> I read again for Suziki's suggestion: "4) Should document the fact that,
> on some platforms, the user may have to disable CPUidle explicitly to
> get the driver working. But let us not make it the default. The user
> with a not so ideal platform could add "nohlt" and get it working."
Suzuki and I are expressing the same view using different words.
>
> So I'm not strong to resist and if this is alignment yet, I should
> document well for this but doesn't handle it in driver (keep driver
> simple).
>
> Thanks,
> Leo Yan
^ permalink raw reply
* Re: [PATCH v4 2/4] mvebu: xp: Add PWM properties to .dtsi files
From: Gregory CLEMENT @ 2017-03-30 15:45 UTC (permalink / raw)
To: Ralph Sennhauser
Cc: Linus Walleij, Thierry Reding, Imre Kaloz, Andrew Lunn,
Alexandre Courbot, Rob Herring, Mark Rutland, Jason Cooper,
Sebastian Hesselbarth, Russell King,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170327194301.1104-3-ralph.sennhauser-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi Ralph,
On lun., mars 27 2017, Ralph Sennhauser <ralph.sennhauser-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
The title should start by ARM: dts: mvebu:
If there is no need to have a v5 then I wil take care of modifying the
title while applying it.
> From: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
>
> Add properties to the GPIO nodes to allow them to be also used as PWM
> lines.
>
> Signed-off-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> URL: https://patchwork.ozlabs.org/patch/427294/
> [Ralph Sennhauser:
> * Use new compatible string marvell,armada-370-xp-gpio
> * Add missing reg-names / #pwm-cell properties to armada-xp-mv78260.dtsi
> 'gpio1' node]
> Signed-off-by: Ralph Sennhauser <ralph.sennhauser-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/boot/dts/armada-370.dtsi | 16 +++++++++++-----
> arch/arm/boot/dts/armada-xp-mv78230.dtsi | 14 ++++++++++----
> arch/arm/boot/dts/armada-xp-mv78260.dtsi | 16 +++++++++++-----
> arch/arm/boot/dts/armada-xp-mv78460.dtsi | 16 +++++++++++-----
> 4 files changed, 43 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
> index cc011c8..e30b076 100644
> --- a/arch/arm/boot/dts/armada-370.dtsi
> +++ b/arch/arm/boot/dts/armada-370.dtsi
> @@ -137,29 +137,35 @@
> };
>
> gpio0: gpio@18100 {
> - compatible = "marvell,orion-gpio";
> - reg = <0x18100 0x40>;
> + compatible = "marvell,armada-370-xp-gpio";
I think we should keep the "marvell,orion-gpio" too because the hardware
is still compatible with it. Morever it will allow to use a recent dtb
with an old kernel.
> + reg = <0x18100 0x40>, <0x181c0 0x08>;
> + reg-names = "gpio", "pwm";
> ngpios = <32>;
> gpio-controller;
> #gpio-cells = <2>;
> + #pwm-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> interrupts = <82>, <83>, <84>, <85>;
> + clocks = <&coreclk 0>;
> };
>
> gpio1: gpio@18140 {
> - compatible = "marvell,orion-gpio";
> - reg = <0x18140 0x40>;
> + compatible = "marvell,armada-370-xp-gpio";
Same here and for all the others...
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH v6 3/3] MAINTAINERS: Broadcom Vulcan is now Cavium ThunderX2
From: Arnd Bergmann @ 2017-03-30 15:40 UTC (permalink / raw)
To: Jayachandran C
Cc: arm-soc, Linux ARM, devicetree-u79uwXL29TY76Z2rM5mHXA,
Rob Herring, Florian Fainelli, Matthias Brugger
In-Reply-To: <1489608662-4434-4-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
On Wed, Mar 15, 2017 at 9:11 PM, Jayachandran C
<jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> wrote:
> Now that the dts files are moved to the new location, we can remove
> the Broadcom Vulcan entry in the MAINTAINERS.
>
> Also fix up the Cavium ThunderX2 entry with the correct pattern for
> the new names.
>
> Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
> ---
Applied to next/arm64, thanks!
Arnd
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^ permalink raw reply
* Re: [PATCH] ARM: dts: clearfog: keep dts alphabetically ordered
From: Gregory CLEMENT @ 2017-03-30 15:34 UTC (permalink / raw)
To: Russell King
Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Rob Herring,
Mark Rutland, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <E1crlBu-0002Gp-V4-eh5Bv4kxaXIk46pC+1QYvQNdhmdF6hFW@public.gmane.org>
Hi Russell,
On sam., mars 25 2017, Russell King <rmk+kernel-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> wrote:
> Keep the clearfog DTS file ordered alphabetically - Florian placed the
> MDIO entry after pinctrl, which mis-orders the file.
>
> Signed-off-by: Russell King <rmk+kernel-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>
Applied on mvebu/dt with Reviewed-by flag from Andrew Lunn
Thanks,
Gregory
> ---
> arch/arm/boot/dts/armada-388-clearfog.dts | 38 +++++++++++++++----------------
> 1 file changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
> index b9ad1641bcf3..e74904bcd0a0 100644
> --- a/arch/arm/boot/dts/armada-388-clearfog.dts
> +++ b/arch/arm/boot/dts/armada-388-clearfog.dts
> @@ -183,25 +183,6 @@
> };
> };
>
> -&pinctrl {
> - clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
> - marvell,pins = "mpp46";
> - marvell,function = "ref";
> - };
> - clearfog_dsa0_pins: clearfog-dsa0-pins {
> - marvell,pins = "mpp23", "mpp41";
> - marvell,function = "gpio";
> - };
> - clearfog_spi1_cs_pins: spi1-cs-pins {
> - marvell,pins = "mpp55";
> - marvell,function = "spi1";
> - };
> - rear_button_pins: rear-button-pins {
> - marvell,pins = "mpp34";
> - marvell,function = "gpio";
> - };
> -};
> -
> &mdio {
> status = "okay";
>
> @@ -261,6 +242,25 @@
> };
> };
>
> +&pinctrl {
> + clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
> + marvell,pins = "mpp46";
> + marvell,function = "ref";
> + };
> + clearfog_dsa0_pins: clearfog-dsa0-pins {
> + marvell,pins = "mpp23", "mpp41";
> + marvell,function = "gpio";
> + };
> + clearfog_spi1_cs_pins: spi1-cs-pins {
> + marvell,pins = "mpp55";
> + marvell,function = "spi1";
> + };
> + rear_button_pins: rear-button-pins {
> + marvell,pins = "mpp34";
> + marvell,function = "gpio";
> + };
> +};
> +
> &spi1 {
> /*
> * Add SPI CS pins for clearfog:
> --
> 2.7.4
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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^ permalink raw reply
* [PATCH v13 1/6] dt-bindings: mmc: Add Cavium SOCs MMC bindings
From: Jan Glauber @ 2017-03-30 15:31 UTC (permalink / raw)
To: Ulf Hansson
Cc: David Daney, Steven J . Hill, linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Jan Glauber, Rob Herring,
Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170330153128.22842-1-jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
Add description of Cavium Octeon and ThunderX SOC device tree bindings.
CC: Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
CC: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
CC: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
CC: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Jan Glauber <jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
Signed-off-by: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
Signed-off-by: Steven J. Hill <steven.hill-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
Acked-by: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
.../devicetree/bindings/mmc/cavium-mmc.txt | 57 ++++++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/cavium-mmc.txt
diff --git a/Documentation/devicetree/bindings/mmc/cavium-mmc.txt b/Documentation/devicetree/bindings/mmc/cavium-mmc.txt
new file mode 100644
index 0000000..1433e62
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/cavium-mmc.txt
@@ -0,0 +1,57 @@
+* Cavium Octeon & ThunderX MMC controller
+
+The highspeed MMC host controller on Caviums SoCs provides an interface
+for MMC and SD types of memory cards.
+
+Supported maximum speeds are the ones of the eMMC standard 4.41 as well
+as the speed of SD standard 4.0. Only 3.3 Volt is supported.
+
+Required properties:
+ - compatible : should be one of:
+ cavium,octeon-6130-mmc
+ cavium,octeon-7890-mmc
+ cavium,thunder-8190-mmc
+ cavium,thunder-8390-mmc
+ mmc-slot
+ - reg : mmc controller base registers
+ - clocks : phandle
+
+Optional properties:
+ - for cd, bus-width and additional generic mmc parameters
+ please refer to mmc.txt within this directory
+ - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command
+ - cavium,dat-clk-skew : number of coprocessor clocks before sampling data
+
+Deprecated properties:
+- spi-max-frequency : use max-frequency instead
+- cavium,bus-max-width : use bus-width instead
+- power-gpios : use vmmc-supply instead
+- cavium,octeon-6130-mmc-slot : use mmc-slot instead
+
+Examples:
+ mmc_1_4: mmc@1,4 {
+ compatible = "cavium,thunder-8390-mmc";
+ reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&sclk>;
+
+ mmc-slot@0 {
+ compatible = "mmc-slot";
+ reg = <0>;
+ vmmc-supply = <&mmc_supply_3v3>;
+ max-frequency = <42000000>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ };
+
+ mmc-slot@1 {
+ compatible = "mmc-slot";
+ reg = <1>;
+ vmmc-supply = <&mmc_supply_3v3>;
+ max-frequency = <42000000>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ non-removable;
+ };
+ };
--
2.9.0.rc0.21.g7777322
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^ permalink raw reply related
* [PATCH 2/2] ARM: dts: keystone: Add minimum support for K2G ICE evm
From: Franklin S Cooper Jr @ 2017-03-30 15:29 UTC (permalink / raw)
To: robh+dt, linux, ssantosh, devicetree, linux-kernel,
linux-arm-kernel
Cc: Franklin S Cooper Jr
In-Reply-To: <20170330152907.12595-1-fcooper@ti.com>
Add barebones dts support for TI's K2G Industrial Communication Engine evm.
This dts allows the board to boot using a ram based filesystem.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/keystone-k2g-ice.dts | 42 ++++++++++++++++++++++++++++++++++
2 files changed, 44 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/keystone-k2g-ice.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0118084..01a98f1 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -193,7 +193,8 @@ dtb-$(CONFIG_ARCH_KEYSTONE) += \
keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
keystone-k2e-evm.dtb \
- keystone-k2g-evm.dtb
+ keystone-k2g-evm.dtb \
+ keystone-k2g-ice.dtb
dtb-$(CONFIG_MACH_KIRKWOOD) += \
kirkwood-b3.dtb \
kirkwood-blackarmor-nas220.dtb \
diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts
new file mode 100644
index 0000000..9ab5f42
--- /dev/null
+++ b/arch/arm/boot/dts/keystone-k2g-ice.dts
@@ -0,0 +1,42 @@
+/*
+ * Device Tree Source for K2G Industrial Communication Engine EVM
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+
+#include "keystone-k2g.dtsi"
+
+/ {
+ compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
+ model = "Texas Instruments K2G Industrial Communication EVM";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
+ };
+};
+
+&k2g_pinctrl {
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
--
2.10.0
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