* Re: [PATCH 1/2 v4] ARM: dts: i.MX25: add AIPS control registers
From: Shawn Guo @ 2017-04-04 13:13 UTC (permalink / raw)
To: Martin Kaiser
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sascha Hauer,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1491248825-23041-1-git-send-email-martin-XxZfDwE/svGeZLLa646FqQ@public.gmane.org>
On Mon, Apr 03, 2017 at 09:47:04PM +0200, Martin Kaiser wrote:
> The i.MX25 contains two AHB to IP bridges (AIPS), each of which has a set of
> control registers. Add the memory regions for the control registers to
> the Device Tree.
>
> Signed-off-by: Martin Kaiser <martin-XxZfDwE/svGeZLLa646FqQ@public.gmane.org>
> Reviewed-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Applied, thanks.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 2/2 v2] ARM: i.MX25: globally disable supervisor protect
From: Shawn Guo @ 2017-04-04 13:14 UTC (permalink / raw)
To: Martin Kaiser
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sascha Hauer,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1491248825-23041-2-git-send-email-martin-XxZfDwE/svGeZLLa646FqQ@public.gmane.org>
On Mon, Apr 03, 2017 at 09:47:05PM +0200, Martin Kaiser wrote:
> The problem described in 6befda9a272b98bfb1dc772efc3564644cbfb270
This causes the following checkpatch error.
ERROR: Please use git commit description style 'commit <12+ chars of
sha1> ("<title line>")' - ie: 'commit 6befda9a272b ("ARM: i.MX53:
globally disable supervisor protect")'
I fixed it and applied the patch.
Shawn
> for the i.MX53 platform applies to i.MX25 as well.
>
> E.g. CSPI1+SDMA and SSI1+SDMA are not working with the default AIPS
> configuration. Modifiy the AIPS configuration to allow access to the bus
> by SDMA and peripherals.
>
> Signed-off-by: Martin Kaiser <martin-XxZfDwE/svGeZLLa646FqQ@public.gmane.org>
> ---
> v2:
> rebased against latest linux-next
> re-sending both patches, it seems they got lost along the way
>
> arch/arm/mach-imx/mach-imx25.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/mach-imx/mach-imx25.c b/arch/arm/mach-imx/mach-imx25.c
> index 32dcb5e..353b86e 100644
> --- a/arch/arm/mach-imx/mach-imx25.c
> +++ b/arch/arm/mach-imx/mach-imx25.c
> @@ -23,6 +23,11 @@ static void __init imx25_init_early(void)
> mxc_set_cpu_type(MXC_CPU_MX25);
> }
>
> +static void __init imx25_dt_init(void)
> +{
> + imx_aips_allow_unprivileged_access("fsl,imx25-aips");
> +}
> +
> static void __init mx25_init_irq(void)
> {
> struct device_node *np;
> @@ -41,6 +46,7 @@ static const char * const imx25_dt_board_compat[] __initconst = {
>
> DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
> .init_early = imx25_init_early,
> + .init_machine = imx25_dt_init,
> .init_late = imx25_pm_init,
> .init_irq = mx25_init_irq,
> .dt_compat = imx25_dt_board_compat,
> --
> 2.1.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH] dt-bindings: display: rk3288-mipi-dsi: add reset property
From: John Keeping @ 2017-04-04 13:15 UTC (permalink / raw)
To: Sean Paul
Cc: Rob Herring, Brian Norris, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Chris Zhong,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170312120659.hpiwnsto6hkxs5yh@rob-hp-laptop>
Hi Sean,
On Sun, 12 Mar 2017 07:06:59 -0500, Rob Herring wrote:
> On Fri, Mar 03, 2017 at 11:39:45AM +0000, John Keeping wrote:
> > This reset is required in order to fully reset the internal state of the
> > MIPI controller.
> >
> > Signed-off-by: John Keeping <john-HooS5bfzL4hWk0Htik3J/w@public.gmane.org>
> > ---
> > On Thu, 2 Mar 2017 13:56:46 -0800, Brian Norris wrote:
> > > On Fri, Feb 24, 2017 at 12:55:06PM +0000, John Keeping wrote:
> > > > + /*
> > > > + * Note that the reset was not defined in the initial device tree, so
> > > > + * we have to be prepared for it not being found.
> > > > + */
> > > > + apb_rst = devm_reset_control_get(dev, "apb");
> > >
> > > Did this reset ever get documented in the device tree bindings? I
> > > couldn't find it. Perhaps a follow-up patch is in order?
> >
> > Here's a patch to do that.
> >
> > .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +++++++
> > 1 file changed, 7 insertions(+)
>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
I don't see this patch in linux-next, so I guess it has fallen through
the cracks somewhere. Since we have Rob's ack, can you pick this via
drm-misc?
Regards,
John
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 0/2] clk: Add support for IDT 5P49V5935
From: Alexey Firago @ 2017-04-04 13:16 UTC (permalink / raw)
To: mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
marek.vasut-Re5JQEeQqe8AvxtiuMwx3w,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Alexey Firago
This series adds support for IDT VersaClock 5P49V5935 programmable clock
generator to the existing clk-versaclock5 driver.
Patches were verified on Avnet UltraZed-EG board with IO Carrier Card.
Alexey Firago (2):
clk: vc5: Add bindings for IDT VersaClock 5P49V5935
clk: vc5: Add support for IDT VersaClock 5P49V5935
.../devicetree/bindings/clock/idt,versaclock5.txt | 16 +++++--
drivers/clk/clk-versaclock5.c | 50 +++++++++++++++++-----
2 files changed, 53 insertions(+), 13 deletions(-)
--
2.7.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 1/2] clk: vc5: Add bindings for IDT VersaClock 5P49V5935
From: Alexey Firago @ 2017-04-04 13:16 UTC (permalink / raw)
To: mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
marek.vasut-Re5JQEeQqe8AvxtiuMwx3w,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Alexey Firago
In-Reply-To: <1491311788-31905-1-git-send-email-alexey_firago-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
IDT VersaClock 5 5P49V5935 has 4 clock outputs, 4 fractional dividers.
Input clock source can be taken from either integrated crystal or from
external reference clock.
Signed-off-by: Alexey Firago <alexey_firago-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
---
.../devicetree/bindings/clock/idt,versaclock5.txt | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
index 87e9c47..53d7e50 100644
--- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
@@ -6,18 +6,21 @@ from 3 to 12 output clocks.
==I2C device node==
Required properties:
-- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933".
+- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933" ,
+ "idt,5p49v5935".
- reg: i2c device address, shall be 0x68 or 0x6a.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock handles,
- 5p49v5923: (required) either or both of XTAL or CLKIN
reference clock.
- - 5p49v5933: (optional) property not present (internal
+ - 5p49v5933 and
+ - 5p49v5935: (optional) property not present (internal
Xtal used) or CLKIN reference
clock.
- clock-names: from common clock binding; clock input names, can be
- 5p49v5923: (required) either or both of "xin", "clkin".
- - 5p49v5933: (optional) property not present or "clkin".
+ - 5p49v5933 and
+ - 5p49v5935: (optional) property not present or "clkin".
==Mapping between clock specifier and physical pins==
@@ -34,6 +37,13 @@ clock specifier, the following mapping applies:
1 -- OUT1
2 -- OUT4
+5P49V5935:
+ 0 -- OUT0_SEL_I2CB
+ 1 -- OUT1
+ 2 -- OUT2
+ 3 -- OUT3
+ 4 -- OUT4
+
==Example==
/* 25MHz reference crystal */
--
2.7.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 2/2] clk: vc5: Add support for IDT VersaClock 5P49V5935
From: Alexey Firago @ 2017-04-04 13:16 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, marek.vasut, linux-clk, devicetree
Cc: Alexey Firago
In-Reply-To: <1491311788-31905-1-git-send-email-alexey_firago@mentor.com>
Update IDT VersaClock 5 driver to support 5P49V5935. This chip has
two clock inputs (internal XTAL or external CLKIN), four fractional
dividers (FODs) and five clock outputs (four universal clock outputs
and one reference clock output at OUT0_SELB_I2C).
Current driver supports up to 2 FODs and up to 3 clock outputs.
This patch sets max number of supported FODs to 4 and max number
of supported clocks to 5.
Number of used FODs and clock outputs is set on probe according to
the model specified via device-tree.
Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
---
drivers/clk/clk-versaclock5.c | 50 ++++++++++++++++++++++++++++++++++---------
1 file changed, 40 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index 56741f3..f74d6e4 100644
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -113,10 +113,17 @@
#define VC5_MUX_IN_XIN BIT(0)
#define VC5_MUX_IN_CLKIN BIT(1)
+/* Maximum number of clk_out supported by this driver */
+#define VC5_MAX_CLK_OUT_NUM 5
+
+/* Maximum number of FODs supported by this driver */
+#define VC5_MAX_FOD_NUM 4
+
/* Supported IDT VC5 models. */
enum vc5_model {
IDT_VC5_5P49V5923,
IDT_VC5_5P49V5933,
+ IDT_VC5_5P49V5935,
};
struct vc5_driver_data;
@@ -139,8 +146,10 @@ struct vc5_driver_data {
unsigned char clk_mux_ins;
struct clk_hw clk_mux;
struct vc5_hw_data clk_pll;
- struct vc5_hw_data clk_fod[2];
- struct vc5_hw_data clk_out[3];
+ int clk_fod_cnt;
+ struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
+ int clk_out_cnt;
+ struct vc5_hw_data clk_out[VC5_MAX_CLK_OUT_NUM];
};
static const char * const vc5_mux_names[] = {
@@ -563,7 +572,7 @@ static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
struct vc5_driver_data *vc5 = data;
unsigned int idx = clkspec->args[0];
- if (idx > 2)
+ if (idx > vc5->clk_out_cnt)
return ERR_PTR(-EINVAL);
return &vc5->clk_out[idx].hw;
@@ -576,6 +585,7 @@ static int vc5_map_index_to_output(const enum vc5_model model,
case IDT_VC5_5P49V5933:
return (n == 0) ? 0 : 3;
case IDT_VC5_5P49V5923:
+ case IDT_VC5_5P49V5935:
default:
return n;
}
@@ -591,7 +601,7 @@ static int vc5_probe(struct i2c_client *client,
struct vc5_driver_data *vc5;
struct clk_init_data init;
const char *parent_names[2];
- unsigned int n, idx;
+ unsigned int n, idx = 0;
int ret;
vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
@@ -602,6 +612,23 @@ static int vc5_probe(struct i2c_client *client,
vc5->client = client;
vc5->model = (enum vc5_model)of_id->data;
+ /* Set number of supported outputs according to the repoted model */
+ switch (vc5->model) {
+ case IDT_VC5_5P49V5923:
+ case IDT_VC5_5P49V5933:
+ vc5->clk_fod_cnt = 2;
+ vc5->clk_out_cnt = 3;
+ break;
+ case IDT_VC5_5P49V5935:
+ vc5->clk_fod_cnt = 4;
+ vc5->clk_out_cnt = 5;
+ break;
+ default:
+ /* Should never go here */
+ dev_err(&client->dev, "unsupported IDT VC5 ID specified\n");
+ return -EINVAL;
+ }
+
vc5->pin_xin = devm_clk_get(&client->dev, "xin");
if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
return -EPROBE_DEFER;
@@ -622,8 +649,9 @@ static int vc5_probe(struct i2c_client *client,
if (!IS_ERR(vc5->pin_xin)) {
vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
- } else if (vc5->model == IDT_VC5_5P49V5933) {
- /* IDT VC5 5P49V5933 has built-in oscilator. */
+ } else if (vc5->model == IDT_VC5_5P49V5933 ||
+ vc5->model == IDT_VC5_5P49V5935) {
+ /* IDT VC5 5P49V5933 and 5P49V5935 have built-in oscilator. */
vc5->pin_xin = clk_register_fixed_rate(&client->dev,
"internal-xtal", NULL,
0, 25000000);
@@ -672,7 +700,7 @@ static int vc5_probe(struct i2c_client *client,
}
/* Register FODs */
- for (n = 0; n < 2; n++) {
+ for (n = 0; n < vc5->clk_fod_cnt; n++) {
idx = vc5_map_index_to_output(vc5->model, n);
memset(&init, 0, sizeof(init));
init.name = vc5_fod_names[idx];
@@ -709,7 +737,7 @@ static int vc5_probe(struct i2c_client *client,
}
/* Register FOD-connected OUTx outputs */
- for (n = 1; n < 3; n++) {
+ for (n = 1; n < vc5->clk_out_cnt; n++) {
idx = vc5_map_index_to_output(vc5->model, n - 1);
parent_names[0] = vc5_fod_names[idx];
if (n == 1)
@@ -744,7 +772,7 @@ static int vc5_probe(struct i2c_client *client,
return 0;
err_clk:
- if (vc5->model == IDT_VC5_5P49V5933)
+ if (vc5->model == IDT_VC5_5P49V5933 || vc5->model == IDT_VC5_5P49V5935)
clk_unregister_fixed_rate(vc5->pin_xin);
return ret;
}
@@ -755,7 +783,7 @@ static int vc5_remove(struct i2c_client *client)
of_clk_del_provider(client->dev.of_node);
- if (vc5->model == IDT_VC5_5P49V5933)
+ if (vc5->model == IDT_VC5_5P49V5933 || vc5->model == IDT_VC5_5P49V5935)
clk_unregister_fixed_rate(vc5->pin_xin);
return 0;
@@ -764,6 +792,7 @@ static int vc5_remove(struct i2c_client *client)
static const struct i2c_device_id vc5_id[] = {
{ "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
{ "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
+ { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
{ }
};
MODULE_DEVICE_TABLE(i2c, vc5_id);
@@ -771,6 +800,7 @@ MODULE_DEVICE_TABLE(i2c, vc5_id);
static const struct of_device_id clk_vc5_of_match[] = {
{ .compatible = "idt,5p49v5923", .data = (void *)IDT_VC5_5P49V5923 },
{ .compatible = "idt,5p49v5933", .data = (void *)IDT_VC5_5P49V5933 },
+ { .compatible = "idt,5p49v5935", .data = (void *)IDT_VC5_5P49V5935 },
{ },
};
MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
--
2.7.4
^ permalink raw reply related
* Re: [RFC PATCH v2 1/4] dt-bindings: update the Allwinner GPADC device tree binding for H3
From: Maxime Ripard @ 2017-04-04 13:20 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Lee Jones, Chen-Yu Tsai, Jonathan Cameron, Quentin Schulz,
Zhang Rui, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <e4d50e78-afe7-6107-6d9a-15e4c732d79a-h8G6r0blFSE@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 2645 bytes --]
On Mon, Apr 03, 2017 at 05:31:11PM +0800, Icenowy Zheng wrote:
>
>
> 在 2017年04月03日 17:15, Maxime Ripard 写道:
> > On Sun, Apr 02, 2017 at 09:33:01PM +0800, Icenowy Zheng wrote:
> > > Allwinner H3 features a thermal sensor like the one in A33, but has its
> > > register re-arranged, the clock divider moved to CCU (originally the
> > > clock divider is in ADC) and added a pair of bus clock and reset.
> > >
> > > Update the binding document to cover H3.
> > >
> > > Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> > > ---
> > > .../devicetree/bindings/mfd/sun4i-gpadc.txt | 23 ++++++++++++++++++++--
> > > 1 file changed, 21 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
> > > index badff3611a98..7753133ca0ff 100644
> > > --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
> > > +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
> > > @@ -4,12 +4,20 @@ The Allwinner SoCs all have an ADC that can also act as a thermal sensor
> > > and sometimes as a touchscreen controller.
> > >
> > > Required properties:
> > > - - compatible: "allwinner,sun8i-a33-ths",
> > > + - compatible: must contain one of the following compatibles:
> > > + - "allwinner,sun8i-a33-ths"
> > > + - "allwinner,sun8i-h3-ths"
> > > - reg: mmio address range of the chip,
> > > - #thermal-sensor-cells: shall be 0,
> > > - #io-channel-cells: shall be 0,
> > >
> > > -Example:
> > > +Required properties for the following compatibles:
> > > + - "allwinner,sun8i-h3-ths"
> > > + - clocks: the bus clock and the input clock of the ADC,
> > > + - clock-names: should be "bus" and "ths",
> >
> > I guess mod instead of ths would be more consistent.
>
> In fact I will prefer "sample" here if not "ths", as it's used
> for the sampling, not like other mod clocks, which controls
> all the IP block's logic.
All the other mod clocks control some sort of sampling. The audio mod
clocks will be used to sample data in capture, same thing for NAND,
MMC, SPI, etc.
Please remain consistent.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
--
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/d/optout.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply
* Re: [PATCH v2 2/2] phy: meson: add USB2 PHY support for Meson GXL and GXM
From: Kishon Vijay Abraham I @ 2017-04-04 13:20 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: mark.rutland, devicetree, khilman, robh+dt, hendrik, carlo,
linux-amlogic, linux-arm-kernel
In-Reply-To: <CAFBinCAfO9_JfbCgHT3GmsKqoYhW-KqiT2s1f3WXRMO2LN4u_g@mail.gmail.com>
Hi,
On Saturday 01 April 2017 03:07 PM, Martin Blumenstingl wrote:
> Hi Kishon,
>
> On Wed, Mar 29, 2017 at 12:56 PM, Kishon Vijay Abraham I <kishon@ti.com> wrote:
>> Hi,
>>
>> On Wednesday 29 March 2017 03:03 AM, Martin Blumenstingl wrote:
>>> Hi Kishon,
>>>
>>> On Sat, Mar 18, 2017 at 2:00 PM, Martin Blumenstingl
>>> <martin.blumenstingl@googlemail.com> wrote:
>>>> This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs
>>>> (both SoCs are using the same USB PHY register layout).
>>>>
>>>> The USB2 PHY is a simple PHY which only has a few registers to configure
>>>> the mode (host/device) and a reset register (to enable/disable the PHY).
>>>>
>>>> Unfortunately there are no datasheets available for this PHY. The driver
>>>> was written by reading the code from Amlogic's GPL kernel sources and
>>>> by analyzing the registers on an actual GXL and GXM device running the
>>>> kernel that was shipped on the boards I have.
>>> gentle ping - did you have time to review this patch in v2 yet?
>>
>> Have a few comments, see below..
> thanks for taking the time to review this!
>
>>>
>>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>>> ---
>>>> drivers/phy/Kconfig | 14 ++
>>>> drivers/phy/Makefile | 1 +
>>>> drivers/phy/phy-meson-gxl-usb2.c | 273 +++++++++++++++++++++++++++++++++++++++
>>>> 3 files changed, 288 insertions(+)
>>>> create mode 100644 drivers/phy/phy-meson-gxl-usb2.c
>>>>
>>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>>> index dc5277ad1b5a..2573e139fd17 100644
>>>> --- a/drivers/phy/Kconfig
>>>> +++ b/drivers/phy/Kconfig
>>>> @@ -510,6 +510,19 @@ config PHY_MESON8B_USB2
>>>> and GXBB SoCs.
>>>> If unsure, say N.
>>>>
>>>> +config PHY_MESON_GXL_USB
>>>> + tristate "Meson GXL and GXM USB2 PHY drivers"
>>>> + default ARCH_MESON
>>>> + depends on OF && (ARCH_MESON || COMPILE_TEST)
>>>> + depends on USB_SUPPORT
>>>> + select USB_COMMON
>>>> + select GENERIC_PHY
>>>> + select REGMAP_MMIO
>>>> + help
>>>> + Enable this to support the Meson USB2 PHYs found in Meson
>>>> + GXL and GXM SoCs.
>>>> + If unsure, say N.
>>>> +
>>>> config PHY_NSP_USB3
>>>> tristate "Broadcom NorthStar plus USB3 PHY driver"
>>>> depends on OF && (ARCH_BCM_NSP || COMPILE_TEST)
>>>> @@ -518,4 +531,5 @@ config PHY_NSP_USB3
>>>> help
>>>> Enable this to support the Broadcom Northstar plus USB3 PHY.
>>>> If unsure, say N.
>>>> +
>>
>> spurious space..
> you're right, this shouldn't be here. I'll fix this in the next version
>
>>>> endmenu
>>>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>>>> index e7b0feb1e125..e680b856e38e 100644
>>>> --- a/drivers/phy/Makefile
>>>> +++ b/drivers/phy/Makefile
>>>> @@ -62,4 +62,5 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
>>>> obj-$(CONFIG_ARCH_TEGRA) += tegra/
>>>> obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
>>>> obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
>>>> +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.o
>>>> obj-$(CONFIG_PHY_NSP_USB3) += phy-bcm-nsp-usb3.o
>>>> diff --git a/drivers/phy/phy-meson-gxl-usb2.c b/drivers/phy/phy-meson-gxl-usb2.c
>>>> new file mode 100644
>>>> index 000000000000..4bf646a52c45
>>>> --- /dev/null
>>>> +++ b/drivers/phy/phy-meson-gxl-usb2.c
>>>> @@ -0,0 +1,273 @@
>>>> +/*
>>>> + * Meson GXL and GXM USB2 PHY driver
>>>> + *
>>>> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or modify
>>>> + * it under the terms of the GNU General Public License version 2 as
>>>> + * published by the Free Software Foundation.
>>>> + *
>>>> + * You should have received a copy of the GNU General Public License
>>>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>>>> + */
>>>> +
>>>> +#include <linux/delay.h>
>>>> +#include <linux/io.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/of_device.h>
>>>> +#include <linux/regmap.h>
>>>> +#include <linux/phy/phy.h>
>>>> +#include <linux/platform_device.h>
>>>> +#include <linux/usb/of.h>
>>>> +
>>>> +/* bits [31:27] are read-only */
>>>> +#define U2P_R0 0x0
>>>> + #define U2P_R0_BYPASS_SEL BIT(0)
>>>> + #define U2P_R0_BYPASS_DM_EN BIT(1)
>>>> + #define U2P_R0_BYPASS_DP_EN BIT(2)
>>>> + #define U2P_R0_TXBITSTUFF_ENH BIT(3)
>>>> + #define U2P_R0_TXBITSTUFF_EN BIT(4)
>>>> + #define U2P_R0_DM_PULLDOWN BIT(5)
>>>> + #define U2P_R0_DP_PULLDOWN BIT(6)
>>>> + #define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7)
>>>> + #define U2P_R0_DP_VBUS_VLD_EXT BIT(8)
>>>> + #define U2P_R0_ADP_PRB_EN BIT(9)
>>>> + #define U2P_R0_ADP_DISCHARGE BIT(10)
>>>> + #define U2P_R0_ADP_CHARGE BIT(11)
>>>> + #define U2P_R0_DRV_VBUS BIT(12)
>>>> + #define U2P_R0_ID_PULLUP BIT(13)
>>>> + #define U2P_R0_LOOPBACK_EN_B BIT(14)
>>>> + #define U2P_R0_OTG_DISABLE BIT(15)
>>>> + #define U2P_R0_COMMON_ONN BIT(16)
>>>> + #define U2P_R0_FSEL_MASK GENMASK(19, 17)
>>>> + #define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)
>>>> + #define U2P_R0_POWER_ON_RESET BIT(22)
>>>> + #define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)
>>>> + #define U2P_R0_ID_SET_ID_DQ BIT(25)
>>>> + #define U2P_R0_ATE_RESET BIT(26)
>>>> + #define U2P_R0_FSV_MINUS BIT(27)
>>>> + #define U2P_R0_FSV_PLUS BIT(28)
>>>> + #define U2P_R0_BYPASS_DM_DATA BIT(29)
>>>> + #define U2P_R0_BYPASS_DP_DATA BIT(30)
>>>> +
>>>> +#define U2P_R1 0x4
>>>> + #define U2P_R1_BURN_IN_TEST BIT(0)
>>>> + #define U2P_R1_ACA_ENABLE BIT(1)
>>>> + #define U2P_R1_DCD_ENABLE BIT(2)
>>>> + #define U2P_R1_VDAT_SRC_EN_B BIT(3)
>>>> + #define U2P_R1_VDAT_DET_EN_B BIT(4)
>>>> + #define U2P_R1_CHARGES_SEL BIT(5)
>>>> + #define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6)
>>>> + #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)
>>>> + #define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)
>>>> + #define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)
>>>> + #define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)
>>>> + #define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)
>>>> + #define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)
>>>> + #define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)
>>>> + #define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26)
>>>> + #define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29)
>>>> +
>>>> +/* bits [31:14] are read-only */
>>>> +#define U2P_R2 0x8
>>>> + #define U2P_R2_DATA_IN_MASK GENMASK(3, 0)
>>>> + #define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4)
>>>> + #define U2P_R2_ADDR_MASK GENMASK(11, 8)
>>>> + #define U2P_R2_DATA_OUT_SEL BIT(12)
>>>> + #define U2P_R2_CLK BIT(13)
>>>> + #define U2P_R2_DATA_OUT_MASK GENMASK(17, 14)
>>>> + #define U2P_R2_ACA_PIN_RANGE_C BIT(18)
>>>> + #define U2P_R2_ACA_PIN_RANGE_B BIT(19)
>>>> + #define U2P_R2_ACA_PIN_RANGE_A BIT(20)
>>>> + #define U2P_R2_ACA_PIN_GND BIT(21)
>>>> + #define U2P_R2_ACA_PIN_FLOAT BIT(22)
>>>> + #define U2P_R2_CHARGE_DETECT BIT(23)
>>>> + #define U2P_R2_DEVICE_SESSION_VALID BIT(24)
>>>> + #define U2P_R2_ADP_PROBE BIT(25)
>>>> + #define U2P_R2_ADP_SENSE BIT(26)
>>>> + #define U2P_R2_SESSION_END BIT(27)
>>>> + #define U2P_R2_VBUS_VALID BIT(28)
>>>> + #define U2P_R2_B_VALID BIT(29)
>>>> + #define U2P_R2_A_VALID BIT(30)
>>>> + #define U2P_R2_ID_DIG BIT(31)
>>>> +
>>>> +#define U2P_R3 0xc
>>>> +
>>>> +#define RESET_COMPLETE_TIME 500
>>>> +
>>>> +struct phy_meson_gxl_usb2_priv {
>>>> + struct regmap *regmap;
>>>> + enum phy_mode mode;
>>>> + int is_enabled;
>>>> +};
>>>> +
>>>> +static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = {
>>>> + .reg_bits = 8,
>>>> + .val_bits = 32,
>>>> + .reg_stride = 4,
>>>> + .max_register = U2P_R3,
>>>> +};
>>>> +
>>>> +static int phy_meson_gxl_usb2_reset(struct phy *phy)
>>>> +{
>>>> + struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
>>>> +
>>>> + if (priv->is_enabled) {
>>>> + /* reset the PHY and wait until settings are stabilized */
>>>> + regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET,
>>>> + U2P_R0_POWER_ON_RESET);
>>>> + udelay(RESET_COMPLETE_TIME);
>>>> + regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET,
>>>> + 0);
>>>> + udelay(RESET_COMPLETE_TIME);
>>>> + }
>>
>> Instead of having big if condition blocks, it could be
>> if (!priv->is_enabled)
>> return 0
>>
>> the configuration when priv->is_enabled is true should go here.
> makes sense (and the code easier to read) in this case - I'll fix it
> in the next version
>
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int phy_meson_gxl_usb2_set_mode(struct phy *phy, enum phy_mode mode)
>>>> +{
>>>> + struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
>>>> +
>>>> + switch (mode) {
>>>> + case PHY_MODE_USB_HOST:
>>>> + case PHY_MODE_USB_OTG:
>>>> + regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DM_PULLDOWN,
>>>> + U2P_R0_DM_PULLDOWN);
>>>> + regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DP_PULLDOWN,
>>>> + U2P_R0_DP_PULLDOWN);
>>>> + regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_ID_PULLUP, 0);
>>>> + break;
>>>> +
>>>> + case PHY_MODE_USB_DEVICE:
>>>> + regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DM_PULLDOWN,
>>>> + 0);
>>>> + regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DP_PULLDOWN,
>>>> + 0);
>>>> + regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_ID_PULLUP,
>>>> + U2P_R0_ID_PULLUP);
>>>> + break;
>>>> +
>>>> + default:
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + phy_meson_gxl_usb2_reset(phy);
>>>> +
>>>> + priv->mode = mode;
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int phy_meson_gxl_usb2_power_off(struct phy *phy)
>>>> +{
>>>> + struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
>>>> +
>>>> + priv->is_enabled = 0;
>>>> +
>>>> + /* power off the PHY by putting it into reset mode */
>>>> + regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET,
>>>> + U2P_R0_POWER_ON_RESET);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int phy_meson_gxl_usb2_power_on(struct phy *phy)
>>>> +{
>>>> + struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
>>>> + int ret;
>>>> +
>>>> + priv->is_enabled = 1;
>>>> +
>>>> + /* power on the PHY by taking it out of reset mode */
>>>> + regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET, 0);
>>>> +
>>>> + ret = phy_meson_gxl_usb2_set_mode(phy, priv->mode);
>>
>> Since this is already part of phy_ops, the consumer of this phy will take care
>> of setting the mode right?
> many USB PHYs are configured through of_usb_get_dr_mode_by_phy()
> (which fetches the USB controller DT node and looks up the dr_mode
> property). this means that the driver will even work for controller
> which did not call phy_set_mode() (currently dwc2 and dwc3 are an
> example where phy_set_mode() is not called, and this driver is
> probably going to be used by both). are you fine with keeping this or
> should we instead investigate why dwc2 and dwc3 are not calling
> phy_set_mode yet?
If the driver want to set_mode of the phy, then it should be fine. But let's
remove .set_mode from phy_ops. Either the driver should set the mode by itself
or allow the consumers to set the mode but not both.
>
>>>> + if (ret) {
>>>> + phy_meson_gxl_usb2_power_off(phy);
>>
>> This would mess up the reference count in phy_core, since this function is also
>> part of the phy_ops. The consumer should be responsible for powering off the phy.
> actually it shouldn't. it would cause issues if I used
> phy_power_off(phy) here, but I'm using the driver-internal callback
> here.
I didn't mean you should use phy_power_off(). I meant powering on the phy or
powering off the phy should be controlled by the consumer.
> if phy_meson_gxl_usb2_power_on() fails then phy_power_on() (from
> phy-core) prints a warnings and does not increment the internal
> ref-counter (++phy->power_count).
> so in my opinion there shouldn't be a problem
That makes sense.
Thanks
Kishon
^ permalink raw reply
* Re: [PATCH 2/2] clk: vc5: Add support for IDT VersaClock 5P49V5935
From: Marek Vasut @ 2017-04-04 13:21 UTC (permalink / raw)
To: Alexey Firago, mturquette, sboyd, robh+dt, linux-clk, devicetree
In-Reply-To: <1491311788-31905-3-git-send-email-alexey_firago@mentor.com>
On 04/04/2017 03:16 PM, Alexey Firago wrote:
> Update IDT VersaClock 5 driver to support 5P49V5935. This chip has
> two clock inputs (internal XTAL or external CLKIN), four fractional
> dividers (FODs) and five clock outputs (four universal clock outputs
> and one reference clock output at OUT0_SELB_I2C).
>
> Current driver supports up to 2 FODs and up to 3 clock outputs.
> This patch sets max number of supported FODs to 4 and max number
> of supported clocks to 5.
>
> Number of used FODs and clock outputs is set on probe according to
> the model specified via device-tree.
>
> Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
> ---
> drivers/clk/clk-versaclock5.c | 50 ++++++++++++++++++++++++++++++++++---------
> 1 file changed, 40 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
> index 56741f3..f74d6e4 100644
> --- a/drivers/clk/clk-versaclock5.c
> +++ b/drivers/clk/clk-versaclock5.c
> @@ -113,10 +113,17 @@
> #define VC5_MUX_IN_XIN BIT(0)
> #define VC5_MUX_IN_CLKIN BIT(1)
>
> +/* Maximum number of clk_out supported by this driver */
> +#define VC5_MAX_CLK_OUT_NUM 5
> +
> +/* Maximum number of FODs supported by this driver */
> +#define VC5_MAX_FOD_NUM 4
> +
> /* Supported IDT VC5 models. */
> enum vc5_model {
> IDT_VC5_5P49V5923,
> IDT_VC5_5P49V5933,
> + IDT_VC5_5P49V5935,
> };
>
> struct vc5_driver_data;
> @@ -139,8 +146,10 @@ struct vc5_driver_data {
> unsigned char clk_mux_ins;
> struct clk_hw clk_mux;
> struct vc5_hw_data clk_pll;
> - struct vc5_hw_data clk_fod[2];
> - struct vc5_hw_data clk_out[3];
> + int clk_fod_cnt;
> + struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
> + int clk_out_cnt;
> + struct vc5_hw_data clk_out[VC5_MAX_CLK_OUT_NUM];
> };
>
> static const char * const vc5_mux_names[] = {
> @@ -563,7 +572,7 @@ static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
> struct vc5_driver_data *vc5 = data;
> unsigned int idx = clkspec->args[0];
>
> - if (idx > 2)
> + if (idx > vc5->clk_out_cnt)
> return ERR_PTR(-EINVAL);
>
> return &vc5->clk_out[idx].hw;
> @@ -576,6 +585,7 @@ static int vc5_map_index_to_output(const enum vc5_model model,
> case IDT_VC5_5P49V5933:
> return (n == 0) ? 0 : 3;
> case IDT_VC5_5P49V5923:
> + case IDT_VC5_5P49V5935:
> default:
> return n;
> }
> @@ -591,7 +601,7 @@ static int vc5_probe(struct i2c_client *client,
> struct vc5_driver_data *vc5;
> struct clk_init_data init;
> const char *parent_names[2];
> - unsigned int n, idx;
> + unsigned int n, idx = 0;
> int ret;
>
> vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
> @@ -602,6 +612,23 @@ static int vc5_probe(struct i2c_client *client,
> vc5->client = client;
> vc5->model = (enum vc5_model)of_id->data;
>
> + /* Set number of supported outputs according to the repoted model */
s/repoted/reported/ :)
> + switch (vc5->model) {
> + case IDT_VC5_5P49V5923:
> + case IDT_VC5_5P49V5933:
> + vc5->clk_fod_cnt = 2;
> + vc5->clk_out_cnt = 3;
> + break;
> + case IDT_VC5_5P49V5935:
> + vc5->clk_fod_cnt = 4;
> + vc5->clk_out_cnt = 5;
> + break;
> + default:
> + /* Should never go here */
> + dev_err(&client->dev, "unsupported IDT VC5 ID specified\n");
> + return -EINVAL;
> + }
> +
> vc5->pin_xin = devm_clk_get(&client->dev, "xin");
> if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
> return -EPROBE_DEFER;
> @@ -622,8 +649,9 @@ static int vc5_probe(struct i2c_client *client,
> if (!IS_ERR(vc5->pin_xin)) {
> vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
> parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
> - } else if (vc5->model == IDT_VC5_5P49V5933) {
> - /* IDT VC5 5P49V5933 has built-in oscilator. */
> + } else if (vc5->model == IDT_VC5_5P49V5933 ||
> + vc5->model == IDT_VC5_5P49V5935) {
> + /* IDT VC5 5P49V5933 and 5P49V5935 have built-in oscilator. */
> vc5->pin_xin = clk_register_fixed_rate(&client->dev,
> "internal-xtal", NULL,
> 0, 25000000);
> @@ -672,7 +700,7 @@ static int vc5_probe(struct i2c_client *client,
> }
>
> /* Register FODs */
> - for (n = 0; n < 2; n++) {
> + for (n = 0; n < vc5->clk_fod_cnt; n++) {
> idx = vc5_map_index_to_output(vc5->model, n);
> memset(&init, 0, sizeof(init));
> init.name = vc5_fod_names[idx];
> @@ -709,7 +737,7 @@ static int vc5_probe(struct i2c_client *client,
> }
>
> /* Register FOD-connected OUTx outputs */
> - for (n = 1; n < 3; n++) {
> + for (n = 1; n < vc5->clk_out_cnt; n++) {
> idx = vc5_map_index_to_output(vc5->model, n - 1);
> parent_names[0] = vc5_fod_names[idx];
> if (n == 1)
> @@ -744,7 +772,7 @@ static int vc5_probe(struct i2c_client *client,
> return 0;
>
> err_clk:
> - if (vc5->model == IDT_VC5_5P49V5933)
> + if (vc5->model == IDT_VC5_5P49V5933 || vc5->model == IDT_VC5_5P49V5935)
Maybe we should introduce some sort of flags to describe the VC
properties instead of using the model all over the place ?
--
Best regards,
Marek Vasut
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: Add documentation for GP10B GPU
From: Thierry Reding @ 2017-04-04 13:21 UTC (permalink / raw)
To: Alexandre Courbot
Cc: Jonathan Hunter, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, gnurou-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <20170330092644.11890-1-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 588 bytes --]
On Thu, Mar 30, 2017 at 06:26:44PM +0900, Alexandre Courbot wrote:
> GP10B's definition is mostly similar to GK20A's and GM20B's. The only
> noticeable difference is the use of power domains instead of a regulator
> for power supply.
>
> Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> Changes since v1:
> - It's much better when it compiles.
>
> .../devicetree/bindings/gpu/nvidia,gk20a.txt | 25 +++++++++++++++++++++-
> 1 file changed, 24 insertions(+), 1 deletion(-)
Applied to for-4.12/arm64/dt, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH v2] arm64: tegra: Add GPU node for Tegra 186
From: Thierry Reding @ 2017-04-04 13:22 UTC (permalink / raw)
To: Alexandre Courbot
Cc: Jonathan Hunter, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, gnurou-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <20170330092828.13336-1-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 375 bytes --]
On Thu, Mar 30, 2017 at 06:28:28PM +0900, Alexandre Courbot wrote:
> Add the DT node for the GP10B GPU on Tegra 186.
>
> Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
Applied to for-4.12/arm64/dt, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH 2/2] clk: vc5: Add support for IDT VersaClock 5P49V5935
From: Geert Uytterhoeven @ 2017-04-04 13:23 UTC (permalink / raw)
To: Marek Vasut
Cc: Alexey Firago, Michael Turquette, Stephen Boyd, Rob Herring,
linux-clk, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <72c66927-0acf-c888-2b4b-906a6c27e15c-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Tue, Apr 4, 2017 at 3:21 PM, Marek Vasut <marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>On 04/04/2017 03:16 PM, Alexey Firago wrote:
>> + switch (vc5->model) {
>> + case IDT_VC5_5P49V5923:
>> + case IDT_VC5_5P49V5933:
>> + vc5->clk_fod_cnt = 2;
>> + vc5->clk_out_cnt = 3;
>> + break;
>> + case IDT_VC5_5P49V5935:
>> + vc5->clk_fod_cnt = 4;
>> + vc5->clk_out_cnt = 5;
>> + break;
>> + default:
>> + /* Should never go here */
>> + dev_err(&client->dev, "unsupported IDT VC5 ID specified\n");
>> + return -EINVAL;
>> + }
>> +
>> vc5->pin_xin = devm_clk_get(&client->dev, "xin");
>> if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
>> return -EPROBE_DEFER;
>> @@ -744,7 +772,7 @@ static int vc5_probe(struct i2c_client *client,
>> return 0;
>>
>> err_clk:
>> - if (vc5->model == IDT_VC5_5P49V5933)
>> + if (vc5->model == IDT_VC5_5P49V5933 || vc5->model == IDT_VC5_5P49V5935)
>
> Maybe we should introduce some sort of flags to describe the VC
> properties instead of using the model all over the place ?
Yep, a structure describing the features (incl. fod_cnt and out_cnt), to be
pointed to by clk_vc5_of_match[].data.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH V4 1/2] regulator: DT: Add settling time property for non-linear voltage change
From: Laxman Dewangan @ 2017-04-04 13:29 UTC (permalink / raw)
To: broonie-DgEjT+Ai2ygdnm+yROfE0A, lgirdwood-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: mark.rutland-5wv7dgnIgG8, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Laxman Dewangan
Some regulators (some PWM regulators) have the voltage transition
exponentially. On such cases, the settling time for voltage change
is treated as constant time.
Add DT property for providing the settling time for any level of
voltage change for non-linear voltage change.
signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
This patch is continuation of discussion on patch
regulator: pwm: Fix regulator ramp delay for continuous mode
https://patchwork.kernel.org/patch/9216857/
where is it discussed to have separate property for PWM which has
exponential voltage transition.
Changes from V1:
- Pass the flag to tell that voltage ramp is exponential instead of
providing delay.
Changes from V2:
- Based on review comment from V1, make the settling time property
independent of the regulator-ramp-delay and move this out of PWM
regulator.
Changes from V3:
- The change was sent long back and resuming this patch.
- Added Rob's ack from V3 and content is same as V3.
https://lkml.org/lkml/2016/11/30/632
- Rebase on linux-next tag 20170330 for resend.
---
Documentation/devicetree/bindings/regulator/regulator.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt
index 6ab5aef..d18edb0 100644
--- a/Documentation/devicetree/bindings/regulator/regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/regulator.txt
@@ -21,6 +21,9 @@ Optional properties:
design requires. This property describes the total system ramp time
required due to the combination of internal ramping of the regulator itself,
and board design issues such as trace capacitance and load on the supply.
+- regulator-settling-time-us: Settling time, in microseconds, for voltage
+ change if regulator have the constant time for any level voltage change.
+ This is useful when regulator have exponential voltage change.
- regulator-soft-start: Enable soft start so that voltage ramps slowly
- regulator-state-mem sub-root node for Suspend-to-RAM mode
: suspend to memory, the device goes to sleep, but all data stored in memory,
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH V4 2/2] regulator: Add settling time for non-linear voltage transition
From: Laxman Dewangan @ 2017-04-04 13:29 UTC (permalink / raw)
To: broonie, lgirdwood, robh+dt
Cc: mark.rutland, linux-kernel, devicetree, Laxman Dewangan
In-Reply-To: <1491312590-20887-1-git-send-email-ldewangan@nvidia.com>
Some regulators (some PWM regulators) have the voltage transition
non-linear i.e. exponentially. On such cases, the settling time
for voltage transition can not be presented in the voltage-ramp-delay.
Add new property for non-linear voltage transition and handle this
in getting the voltage settling time.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
This patch is continuation of discussion on patch
regulator: pwm: Fix regulator ramp delay for continuous mode
https://patchwork.kernel.org/patch/9216857/
where is it discussed to have separate property for PWM which has
exponential voltage transition.
Changes from V1:
- Use new DT property to finding that voltage ramp is exponential or
not and use flag for having fixed delay for all voltage change.
Changes from V2:
- Based on review comment from V1, make the settling time property
independent of the regulator-ramp-delay and move this to core
framework instead of handling in PWM regulator.
Changes from V3:
- The change was sent long back and resuming this patch.
- Rebase on linux-next tag 20170330 for resend.
---
drivers/regulator/core.c | 2 ++
drivers/regulator/of_regulator.c | 4 ++++
include/linux/regulator/machine.h | 3 +++
3 files changed, 9 insertions(+)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 0753635..7303454 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -2773,6 +2773,8 @@ static int _regulator_set_voltage_time(struct regulator_dev *rdev,
ramp_delay = rdev->constraints->ramp_delay;
else if (rdev->desc->ramp_delay)
ramp_delay = rdev->desc->ramp_delay;
+ else if (rdev->constraints->settling_time)
+ return rdev->constraints->settling_time;
if (ramp_delay == 0) {
rdev_dbg(rdev, "ramp_delay not set\n");
diff --git a/drivers/regulator/of_regulator.c b/drivers/regulator/of_regulator.c
index 4f613ec..09d677d 100644
--- a/drivers/regulator/of_regulator.c
+++ b/drivers/regulator/of_regulator.c
@@ -86,6 +86,10 @@ static void of_get_regulation_constraints(struct device_node *np,
constraints->ramp_disable = true;
}
+ ret = of_property_read_u32(np, "regulator-settling-time-us", &pval);
+ if (!ret)
+ constraints->settling_time = pval;
+
ret = of_property_read_u32(np, "regulator-enable-ramp-delay", &pval);
if (!ret)
constraints->enable_time = pval;
diff --git a/include/linux/regulator/machine.h b/include/linux/regulator/machine.h
index c9f795e..117699d 100644
--- a/include/linux/regulator/machine.h
+++ b/include/linux/regulator/machine.h
@@ -108,6 +108,8 @@ struct regulator_state {
* @initial_state: Suspend state to set by default.
* @initial_mode: Mode to set at startup.
* @ramp_delay: Time to settle down after voltage change (unit: uV/us)
+ * @settling_time: Time to settle down after voltage change when voltage
+ * change is non-linear (unit: microseconds).
* @active_discharge: Enable/disable active discharge. The enum
* regulator_active_discharge values are used for
* initialisation.
@@ -149,6 +151,7 @@ struct regulation_constraints {
unsigned int initial_mode;
unsigned int ramp_delay;
+ unsigned int settling_time;
unsigned int enable_time;
unsigned int active_discharge;
--
2.1.4
^ permalink raw reply related
* Re: [PATCH 2/2] clk: vc5: Add support for IDT VersaClock 5P49V5935
From: Alexey Firago @ 2017-04-04 13:35 UTC (permalink / raw)
To: Marek Vasut, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <72c66927-0acf-c888-2b4b-906a6c27e15c-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 04.04.2017 16:21, Marek Vasut wrote:
> On 04/04/2017 03:16 PM, Alexey Firago wrote:
>> Update IDT VersaClock 5 driver to support 5P49V5935. This chip has
>> two clock inputs (internal XTAL or external CLKIN), four fractional
>> dividers (FODs) and five clock outputs (four universal clock outputs
>> and one reference clock output at OUT0_SELB_I2C).
>>
>> Current driver supports up to 2 FODs and up to 3 clock outputs.
>> This patch sets max number of supported FODs to 4 and max number
>> of supported clocks to 5.
>>
>> Number of used FODs and clock outputs is set on probe according to
>> the model specified via device-tree.
>>
>> Signed-off-by: Alexey Firago <alexey_firago-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
>> ---
>> drivers/clk/clk-versaclock5.c | 50 ++++++++++++++++++++++++++++++++++---------
>> 1 file changed, 40 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
>> index 56741f3..f74d6e4 100644
>> --- a/drivers/clk/clk-versaclock5.c
>> +++ b/drivers/clk/clk-versaclock5.c
>> @@ -113,10 +113,17 @@
>> #define VC5_MUX_IN_XIN BIT(0)
>> #define VC5_MUX_IN_CLKIN BIT(1)
>>
>> +/* Maximum number of clk_out supported by this driver */
>> +#define VC5_MAX_CLK_OUT_NUM 5
>> +
>> +/* Maximum number of FODs supported by this driver */
>> +#define VC5_MAX_FOD_NUM 4
>> +
>> /* Supported IDT VC5 models. */
>> enum vc5_model {
>> IDT_VC5_5P49V5923,
>> IDT_VC5_5P49V5933,
>> + IDT_VC5_5P49V5935,
>> };
>>
>> struct vc5_driver_data;
>> @@ -139,8 +146,10 @@ struct vc5_driver_data {
>> unsigned char clk_mux_ins;
>> struct clk_hw clk_mux;
>> struct vc5_hw_data clk_pll;
>> - struct vc5_hw_data clk_fod[2];
>> - struct vc5_hw_data clk_out[3];
>> + int clk_fod_cnt;
>> + struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
>> + int clk_out_cnt;
>> + struct vc5_hw_data clk_out[VC5_MAX_CLK_OUT_NUM];
>> };
>>
>> static const char * const vc5_mux_names[] = {
>> @@ -563,7 +572,7 @@ static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
>> struct vc5_driver_data *vc5 = data;
>> unsigned int idx = clkspec->args[0];
>>
>> - if (idx > 2)
>> + if (idx > vc5->clk_out_cnt)
>> return ERR_PTR(-EINVAL);
>>
>> return &vc5->clk_out[idx].hw;
>> @@ -576,6 +585,7 @@ static int vc5_map_index_to_output(const enum vc5_model model,
>> case IDT_VC5_5P49V5933:
>> return (n == 0) ? 0 : 3;
>> case IDT_VC5_5P49V5923:
>> + case IDT_VC5_5P49V5935:
>> default:
>> return n;
>> }
>> @@ -591,7 +601,7 @@ static int vc5_probe(struct i2c_client *client,
>> struct vc5_driver_data *vc5;
>> struct clk_init_data init;
>> const char *parent_names[2];
>> - unsigned int n, idx;
>> + unsigned int n, idx = 0;
>> int ret;
>>
>> vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
>> @@ -602,6 +612,23 @@ static int vc5_probe(struct i2c_client *client,
>> vc5->client = client;
>> vc5->model = (enum vc5_model)of_id->data;
>>
>> + /* Set number of supported outputs according to the repoted model */
>
> s/repoted/reported/ :)
Oops. Thanks, will fix.
>
>> + switch (vc5->model) {
>> + case IDT_VC5_5P49V5923:
>> + case IDT_VC5_5P49V5933:
>> + vc5->clk_fod_cnt = 2;
>> + vc5->clk_out_cnt = 3;
>> + break;
>> + case IDT_VC5_5P49V5935:
>> + vc5->clk_fod_cnt = 4;
>> + vc5->clk_out_cnt = 5;
>> + break;
>> + default:
>> + /* Should never go here */
>> + dev_err(&client->dev, "unsupported IDT VC5 ID specified\n");
>> + return -EINVAL;
>> + }
>> +
>> vc5->pin_xin = devm_clk_get(&client->dev, "xin");
>> if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
>> return -EPROBE_DEFER;
>> @@ -622,8 +649,9 @@ static int vc5_probe(struct i2c_client *client,
>> if (!IS_ERR(vc5->pin_xin)) {
>> vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
>> parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
>> - } else if (vc5->model == IDT_VC5_5P49V5933) {
>> - /* IDT VC5 5P49V5933 has built-in oscilator. */
>> + } else if (vc5->model == IDT_VC5_5P49V5933 ||
>> + vc5->model == IDT_VC5_5P49V5935) {
>> + /* IDT VC5 5P49V5933 and 5P49V5935 have built-in oscilator. */
>> vc5->pin_xin = clk_register_fixed_rate(&client->dev,
>> "internal-xtal", NULL,
>> 0, 25000000);
>> @@ -672,7 +700,7 @@ static int vc5_probe(struct i2c_client *client,
>> }
>>
>> /* Register FODs */
>> - for (n = 0; n < 2; n++) {
>> + for (n = 0; n < vc5->clk_fod_cnt; n++) {
>> idx = vc5_map_index_to_output(vc5->model, n);
>> memset(&init, 0, sizeof(init));
>> init.name = vc5_fod_names[idx];
>> @@ -709,7 +737,7 @@ static int vc5_probe(struct i2c_client *client,
>> }
>>
>> /* Register FOD-connected OUTx outputs */
>> - for (n = 1; n < 3; n++) {
>> + for (n = 1; n < vc5->clk_out_cnt; n++) {
>> idx = vc5_map_index_to_output(vc5->model, n - 1);
>> parent_names[0] = vc5_fod_names[idx];
>> if (n == 1)
>> @@ -744,7 +772,7 @@ static int vc5_probe(struct i2c_client *client,
>> return 0;
>>
>> err_clk:
>> - if (vc5->model == IDT_VC5_5P49V5933)
>> + if (vc5->model == IDT_VC5_5P49V5933 || vc5->model == IDT_VC5_5P49V5935)
>
> Maybe we should introduce some sort of flags to describe the VC
> properties instead of using the model all over the place ?
That makes sense. Will rework.
Regards,
Alexey
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 2/2] clk: vc5: Add support for IDT VersaClock 5P49V5935
From: Alexey Firago @ 2017-04-04 13:36 UTC (permalink / raw)
To: Geert Uytterhoeven, Marek Vasut
Cc: Michael Turquette, Stephen Boyd, Rob Herring, linux-clk,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAMuHMdUOtY5i0_BoS7cKYzWKpA_fF3VssN4bZnNyFB117EpacQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 04.04.2017 16:23, Geert Uytterhoeven wrote:
> On Tue, Apr 4, 2017 at 3:21 PM, Marek Vasut <marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> On 04/04/2017 03:16 PM, Alexey Firago wrote:
>>> + switch (vc5->model) {
>>> + case IDT_VC5_5P49V5923:
>>> + case IDT_VC5_5P49V5933:
>>> + vc5->clk_fod_cnt = 2;
>>> + vc5->clk_out_cnt = 3;
>>> + break;
>>> + case IDT_VC5_5P49V5935:
>>> + vc5->clk_fod_cnt = 4;
>>> + vc5->clk_out_cnt = 5;
>>> + break;
>>> + default:
>>> + /* Should never go here */
>>> + dev_err(&client->dev, "unsupported IDT VC5 ID specified\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> vc5->pin_xin = devm_clk_get(&client->dev, "xin");
>>> if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
>>> return -EPROBE_DEFER;
>
>>> @@ -744,7 +772,7 @@ static int vc5_probe(struct i2c_client *client,
>>> return 0;
>>>
>>> err_clk:
>>> - if (vc5->model == IDT_VC5_5P49V5933)
>>> + if (vc5->model == IDT_VC5_5P49V5933 || vc5->model == IDT_VC5_5P49V5935)
>>
>> Maybe we should introduce some sort of flags to describe the VC
>> properties instead of using the model all over the place ?
>
> Yep, a structure describing the features (incl. fod_cnt and out_cnt), to be
> pointed to by clk_vc5_of_match[].data.
Ok, will rework and resend.
Thanks,
Alexey
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH V3 1/6] ARM: tegra: Remove unnecessary inclusion of flowctrl header
From: Thierry Reding @ 2017-04-04 13:41 UTC (permalink / raw)
To: Jon Hunter
Cc: Rob Herring, Mark Rutland, Russell King, Stephen Warren,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1490704978-22906-2-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 407 bytes --]
On Tue, Mar 28, 2017 at 01:42:53PM +0100, Jon Hunter wrote:
> The Tegra flowctrl.h header is included unnecessarily by the Tegra
> sleep.S source file. Remove this unnecessary inclusion.
>
> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> arch/arm/mach-tegra/sleep.S | 2 --
> 1 file changed, 2 deletions(-)
Applied to for-4.12/arm/soc, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCHv6 00/14] atmel-isi/ov7670/ov2640: convert to standalone drivers
From: Nicolas Ferre @ 2017-04-04 14:00 UTC (permalink / raw)
To: Hans Verkuil, linux-media
Cc: Guennadi Liakhovetski, Songjun Wu, Sakari Ailus, devicetree,
Wu, Songjun
In-Reply-To: <20170328082347.11159-1-hverkuil@xs4all.nl>
Le 28/03/2017 à 10:23, Hans Verkuil a écrit :
> From: Hans Verkuil <hans.verkuil@cisco.com>
>
> This patch series converts the soc-camera atmel-isi to a standalone V4L2
> driver.
>
> The same is done for the ov7670 and ov2640 sensor drivers: the ov7670 was
> used to test the atmel-isi driver. The ov2640 is needed because the em28xx
> driver has a soc_camera include dependency. Both ov7670 and ov2640 sensors
> have been tested with the atmel-isi driver.
>
> The first 5 patches improve the ov7670 sensor driver, mostly adding modern
> features such as DT support.
>
> The next three convert the atmel-isi and move it out of soc_camera.
>
> The following 6 patches convert ov2640 and drop the soc_camera dependency
> in em28xx. I have tested that this works with my 'SpeedLink Vicious And
> Divine Laplace webcam'.
>
> Tested with my sama5d3-Xplained board, the ov2640 sensor and two ov7670
> sensors: one with and one without reset/pwdn pins. Also tested with my
> em28xx-based webcam.
>
> I'd like to get this in for 4.12. Fingers crossed.
>
> Regards,
>
> Hans
>
> Changes since v5:
> - Dropped the last two dts patches as these were for demonstration purposes
> only.
> - Simplified isi_graph_init() return handling as suggested by Sakari.
> - Simplified atmel-isi format handling as suggested by Guennadi. Thanks for
> the suggestion, this improves the code nicely!
> - Improved RGB handling in atmel-isi, allowing for all YUV ordering and not
> just YUYV. Tested with YUYV and UYVY (the only two I can test with my
> hardware).
> - Improved commit message of the "atmel-isi: document device tree bindings"
> patch and dropped unnecessary properties from the example as per Rob's
> comments.
>
> Changes since v4:
> - the ov2640 colorspace fixes were inexplicably part of an atmel-isi patch.
> Split it off as a separate patch.
> - add V4L2_SUBDEV_FL_HAS_DEVNODE to ov2640.
> - drop #if defined(CONFIG_MEDIA_CONTROLLER) guard around media_entity_cleanup
> in ov2640.
>
> Changes since v3:
> - ov2640/ov7670: call clk_disable_unprepare where needed. I assumed this was
> done by the devm_clk_get cleanup, but that wasn't the case.
> - bindings: be even more explicit about which properties are mandatory.
> - ov2640/ov7670: drop unused bus-width from the dts binding examples and from
> the actual dts patches.
>
> Changes since v2:
> - Incorporated Sakari's and Rob's device tree bindings comments.
> - ov2640: dropped the reset/power changes. These actually broke the em28xx
> and there was really nothing wrong with it.
> - merged the "ov2640: allow use inside em28xx" into patches 10 and 11.
> It really shouldn't have been a separate patch in the first place.
> - rebased on top of 4.11-rc1.
>
> Changes since v1:
>
> - Dropped MC support from atmel-isi and ov7670: not needed to make this
> work. Only for the ov2640 was it kept since the em28xx driver requires it.
> - Use devm_clk_get instead of clk_get.
> - The ov7670 lower limit of the clock speed is 10 MHz instead of 12. Adjust
> accordingly.
>
>
> Hans Verkuil (14):
> ov7670: document device tree bindings
> ov7670: call v4l2_async_register_subdev
> ov7670: fix g/s_parm
> ov7670: get xclk
> ov7670: add devicetree support
> atmel-isi: update device tree bindings documentation
> atmel-isi: remove dependency of the soc-camera framework
> atmel-isi: move out of soc_camera to atmel
> ov2640: fix colorspace handling
> ov2640: update bindings
> ov2640: convert from soc-camera to a standard subdev sensor driver.
> ov2640: use standard clk and enable it.
> ov2640: add MC support
> em28xx: drop last soc_camera link
For the record, here is my test tag:
Tested-by: Nicolas Ferre <nicolas.ferre@microchip.com>
On a Microchip/Atmel SAMA5D4-EK with OV2640 and the per-existing OV7740.
Thanks a lot Hans for this valuable work!
Best regards,
> .../devicetree/bindings/media/atmel-isi.txt | 91 +-
> .../devicetree/bindings/media/i2c/ov2640.txt | 23 +-
> .../devicetree/bindings/media/i2c/ov7670.txt | 43 +
> MAINTAINERS | 1 +
> drivers/media/i2c/Kconfig | 11 +
> drivers/media/i2c/Makefile | 1 +
> drivers/media/i2c/{soc_camera => }/ov2640.c | 153 +--
> drivers/media/i2c/ov7670.c | 75 +-
> drivers/media/i2c/soc_camera/Kconfig | 6 -
> drivers/media/i2c/soc_camera/Makefile | 1 -
> drivers/media/platform/Makefile | 1 +
> drivers/media/platform/atmel/Kconfig | 11 +-
> drivers/media/platform/atmel/Makefile | 1 +
> drivers/media/platform/atmel/atmel-isi.c | 1368 ++++++++++++++++++++
> .../platform/{soc_camera => atmel}/atmel-isi.h | 0
> drivers/media/platform/soc_camera/Kconfig | 11 -
> drivers/media/platform/soc_camera/Makefile | 1 -
> drivers/media/platform/soc_camera/atmel-isi.c | 1167 -----------------
> drivers/media/usb/em28xx/em28xx-camera.c | 9 -
> 19 files changed, 1614 insertions(+), 1360 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/media/i2c/ov7670.txt
> rename drivers/media/i2c/{soc_camera => }/ov2640.c (92%)
> create mode 100644 drivers/media/platform/atmel/atmel-isi.c
> rename drivers/media/platform/{soc_camera => atmel}/atmel-isi.h (100%)
> delete mode 100644 drivers/media/platform/soc_camera/atmel-isi.c
>
--
Nicolas Ferre
^ permalink raw reply
* Re: [PATCH V3 2/6] soc/tegra: Move Tegra flowctrl driver
From: Thierry Reding @ 2017-04-04 14:01 UTC (permalink / raw)
To: Jon Hunter
Cc: Rob Herring, Mark Rutland, Russell King, Stephen Warren,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1490704978-22906-3-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1688 bytes --]
On Tue, Mar 28, 2017 at 01:42:54PM +0100, Jon Hunter wrote:
> The flowctrl driver is required for both ARM and ARM64 Tegra devices
> and in order to enable support for it for ARM64, move the Tegra flowctrl
> driver into drivers/soc/tegra.
>
> By moving the flowctrl driver, tegra_flowctrl_init() is now called by
> via an early initcall and to prevent this function from attempting to
> mapping IO space for a non-Tegra device, a test for 'soc_is_tegra()'
> is also added.
>
> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> arch/arm/mach-tegra/Makefile | 1 -
> arch/arm/mach-tegra/cpuidle-tegra20.c | 3 +-
> arch/arm/mach-tegra/flowctrl.c | 179 --------------------------------
> arch/arm/mach-tegra/flowctrl.h | 66 ------------
> arch/arm/mach-tegra/platsmp.c | 2 +-
> arch/arm/mach-tegra/pm.c | 2 +-
> arch/arm/mach-tegra/reset-handler.S | 2 +-
> arch/arm/mach-tegra/sleep-tegra20.S | 3 +-
> arch/arm/mach-tegra/sleep-tegra30.S | 2 +-
> arch/arm/mach-tegra/tegra.c | 2 -
> drivers/soc/tegra/Kconfig | 7 ++
> drivers/soc/tegra/Makefile | 1 +
> drivers/soc/tegra/flowctrl.c | 187 ++++++++++++++++++++++++++++++++++
> include/soc/tegra/flowctrl.h | 82 +++++++++++++++
> 14 files changed, 285 insertions(+), 254 deletions(-)
> delete mode 100644 arch/arm/mach-tegra/flowctrl.c
> delete mode 100644 arch/arm/mach-tegra/flowctrl.h
> create mode 100644 drivers/soc/tegra/flowctrl.c
> create mode 100644 include/soc/tegra/flowctrl.h
Applied to for-4.12/soc, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH V3 3/6] soc/tegra: flowctrl: Add basic platform driver
From: Thierry Reding @ 2017-04-04 14:01 UTC (permalink / raw)
To: Jon Hunter
Cc: Rob Herring, Mark Rutland, Russell King, Stephen Warren,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1490704978-22906-4-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 432 bytes --]
On Tue, Mar 28, 2017 at 01:42:55PM +0100, Jon Hunter wrote:
> Add a simple platform driver for the flowctrl module so that it gets
> registered as a proper device.
>
> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/soc/tegra/flowctrl.c | 34 ++++++++++++++++++++++++++++++----
> 1 file changed, 30 insertions(+), 4 deletions(-)
Applied to for-4.12/soc, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH V3 4/6] dt-bindings: tegra: Update compatible strings for Tegra flowctrl
From: Thierry Reding @ 2017-04-04 14:01 UTC (permalink / raw)
To: Jon Hunter
Cc: Rob Herring, Mark Rutland, Russell King, Stephen Warren,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1490704978-22906-5-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 457 bytes --]
On Tue, Mar 28, 2017 at 01:42:56PM +0100, Jon Hunter wrote:
> Update the compatible strings for Tegra Flow Control driver to match
> the device-tree source files for Tegra.
>
> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> .../devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
Applied to for-4.12/dt-bindings, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH V3 5/6] arm64: tegra: Update the Tegra132 flowctrl compatible string
From: Thierry Reding @ 2017-04-04 14:01 UTC (permalink / raw)
To: Jon Hunter
Cc: Rob Herring, Mark Rutland, Russell King, Stephen Warren,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1490704978-22906-6-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 459 bytes --]
On Tue, Mar 28, 2017 at 01:42:57PM +0100, Jon Hunter wrote:
> Update the Tegra132 flowctrl compatible string to include
> "nvidia,tegra132-flowctrl" so it is aligned with the flowctrl binding
> documentation.
>
> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to for-4.12/arm64/dt, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH V3 6/6] soc/tegra: Add initial flowctrl support for Tegra132/210
From: Thierry Reding @ 2017-04-04 14:02 UTC (permalink / raw)
To: Jon Hunter
Cc: Rob Herring, Mark Rutland, Russell King, Stephen Warren,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1490704978-22906-7-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 849 bytes --]
On Tue, Mar 28, 2017 at 01:42:58PM +0100, Jon Hunter wrote:
> Tegra132 and Tegra210 support the flowctrl module and so add initial
> support for these devices.
>
> Please note that Tegra186 does not support the flowctrl module, so
> update the initialisation function such that we do not fall back and
> attempt to map the 'hardcoded' address range for Tegra186. Furthermore
> 64-bit Tegra devices have always had the flowctrl node defined in their
> device-tree and so only use the 'hardcoded' addresses for 32-bit Tegra
> devices.
>
> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/soc/tegra/Kconfig | 2 ++
> drivers/soc/tegra/flowctrl.c | 31 +++++++++++++++++++++----------
> 2 files changed, 23 insertions(+), 10 deletions(-)
Applied to for-4.12/soc, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH] clk: tegra: add missing Tegra210 clocks
From: Thierry Reding @ 2017-04-04 14:03 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Prashant Gaikwad, Michael Turquette, Stephen Boyd,
Jonathan Hunter, Rob Herring, Mark Rutland, Mikko Perttunen,
Rhyland Klein, linux-clk, linux-tegra, linux-kernel, devicetree
In-Reply-To: <1490192598-26862-1-git-send-email-pdeschrijver@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 630 bytes --]
On Wed, Mar 22, 2017 at 04:23:16PM +0200, Peter De Schrijver wrote:
> iqc1, iqc2, tegra_clk_pll_a_out_adsp, tegra_clk_pll_a_out0_out_adsp, adsp
> and adsp neon were not modelled. dp2 wasn't modelled for Tegra210.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
> drivers/clk/tegra/clk-id.h | 6 ++++++
> drivers/clk/tegra/clk-tegra-periph.c | 6 ++++++
> drivers/clk/tegra/clk-tegra210.c | 7 +++++++
> include/dt-bindings/clock/tegra210-car.h | 16 ++++++++--------
> 4 files changed, 27 insertions(+), 8 deletions(-)
Applied to for-4.12/clk, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* [PATCH] mmc: core: add mmc-card hardware reset enable support
From: Richard Leitner @ 2017-04-04 14:16 UTC (permalink / raw)
To: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: shawn.lin-TNX95d0MmH7DzftRWevZcw,
adrian.hunter-ral2JQCrhuEAvxtiuMwx3w,
jh80.chung-Sze3O3UU22JBDgjK7y7TUQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, dev-M/VWbR8SM2SsTnJN9+BGXg,
Richard Leitner
Some eMMCs disable their hardware reset line (RST_N) by default. To enable
it the host must set the corresponding bit in ECSD. An example for such
a device is the Micron MTFCxGACAANA-4M.
This patch adds a new mmc-card devicetree property to let the host enable
this feature during card initialization.
Signed-off-by: Richard Leitner <richard.leitner-WcANXNA0UjBBDgjK7y7TUQ@public.gmane.org>
---
Documentation/devicetree/bindings/mmc/mmc-card.txt | 3 +++
drivers/mmc/core/mmc.c | 21 +++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmc-card.txt b/Documentation/devicetree/bindings/mmc/mmc-card.txt
index a70fcd6..8590a40 100644
--- a/Documentation/devicetree/bindings/mmc/mmc-card.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc-card.txt
@@ -12,6 +12,9 @@ Required properties:
Optional properties:
-broken-hpi : Use this to indicate that the mmc-card has a broken hpi
implementation, and that hpi should not be used
+-enable-hw-reset : some eMMC devices have disabled the hw reset functionality
+ (RST_N_FUNCTION) by default. By adding this property the
+ host will enable it during initialization.
Example:
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index b502601..518d0e3 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -1520,9 +1520,16 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
int err;
u32 cid[4];
u32 rocr;
+ struct device_node *np;
+ bool enable_rst_n = false;
WARN_ON(!host->claimed);
+ np = mmc_of_find_child_device(host, 0);
+ if (np && of_device_is_compatible(np, "mmc-card"))
+ enable_rst_n = of_property_read_bool(np, "enable-hw-reset");
+ of_node_put(np);
+
/* Set correct bus mode for MMC before attempting init */
if (!mmc_host_is_spi(host))
mmc_set_bus_mode(host, MMC_BUSMODE_OPENDRAIN);
@@ -1810,6 +1817,20 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
}
}
+ /*
+ * try to enable RST_N if requested
+ * This is needed because some eMMC chips disable this function by
+ * default.
+ */
+ if (enable_rst_n) {
+ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_RST_N_FUNCTION, EXT_CSD_RST_N_ENABLED,
+ card->ext_csd.generic_cmd6_time);
+ if (err && err != -EBADMSG)
+ pr_warn("%s: Enabling RST_N feature failed\n",
+ mmc_hostname(card->host));
+ }
+
if (!oldcard)
host->card = card;
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox