* [PATCH v5 3/4] iio: adc: Add Maxim max9611 ADC driver
From: Jacopo Mondi @ 2017-04-06 14:20 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g,
wsa+renesas-jBu1N2QxHDJrcw3mvpCnnVaTQe2KTcn/,
magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw,
jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1491488454-22468-1-git-send-email-jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
Add iio driver for Maxim max9611 and max9612 current-sense amplifiers
with 12-bits ADC interface.
Datasheet publicly available at:
https://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf
Signed-off-by: Jacopo Mondi <jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
---
Output of iio_info on Salvator-X board for max9611 chip installed on
VDD_0.8 lines.
The VDD_0.8 line powers the CPU cluster and on-board RAM.
iio:device0: max9611
5 channels found:
voltage0: (input)
1 channel-specific attributes found:
attr 0: input value: 4.085000000
voltage1: (input)
3 channel-specific attributes found:
attr 0: scale value: 14
attr 1: offset value: 1
attr 2: raw value: 59
power: (input)
2 channel-specific attributes found:
attr 0: shunt_resistor value: 5.000
attr 1: input value: 663.404000000
current: (input)
2 channel-specific attributes found:
attr 0: shunt_resistor value: 5.000
attr 1: input value: 817.000000000
temp: (input)
2 channel-specific attributes found:
attr 0: scale value: 480.076812289
attr 1: raw value: 59
The collected information represent:
* voltage0 (current sense voltage) Vcsa
voltage drop between RS+ and RS- input = 4,085 mV
* voltage1: (common input voltage) Vcim
voltage at RS+ input = (59 - 1) * 14 = 812 mV
* current flowing on shunt resistor (Icsa)
= Vcsa / Rshunt = 817 mA
* power load on the sensed line (Pload)
= Vcim * Icsa = 663 m
* die temperature = (57 * 480.07) = 27360 milli Celsius
---
drivers/iio/adc/Kconfig | 10 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/max9611.c | 585 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 596 insertions(+)
create mode 100644 drivers/iio/adc/max9611.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index dedae7a..82f2e7b8 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -354,6 +354,16 @@ config MAX1363
To compile this driver as a module, choose M here: the module will be
called max1363.
+config MAX9611
+ tristate "Maxim max9611/max9612 ADC driver"
+ depends on I2C
+ help
+ Say yes here to build support for Maxim max9611/max9612 current sense
+ amplifier with 12-bits ADC interface.
+
+ To compile this driver as a module, choose M here: the module will be
+ called max9611.
+
config MCP320X
tristate "Microchip Technology MCP3x01/02/04/08"
depends on SPI
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d001262..149f979 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_LTC2485) += ltc2485.o
obj-$(CONFIG_MAX1027) += max1027.o
obj-$(CONFIG_MAX11100) += max11100.o
obj-$(CONFIG_MAX1363) += max1363.o
+obj-$(CONFIG_MAX9611) += max9611.o
obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
diff --git a/drivers/iio/adc/max9611.c b/drivers/iio/adc/max9611.c
new file mode 100644
index 0000000..f0b47fa
--- /dev/null
+++ b/drivers/iio/adc/max9611.c
@@ -0,0 +1,585 @@
+/*
+ * iio/adc/max9611.c
+ *
+ * Maxim max9611/max9612 high side current sense amplifier with
+ * 12-bit ADC interface.
+ *
+ * Copyright (C) 2017 Jacopo Mondi
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * This driver supports input common-mode voltage, current-sense
+ * amplifier with programmable gains and die temperature reading from
+ * Maxim max9611/max9612.
+ *
+ * Op-amp, analog comparator, and watchdog functionalities are not
+ * supported by this driver.
+ */
+
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/iio/iio.h>
+#include <linux/iio/sysfs.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+
+#define DRIVER_NAME "max9611"
+
+/* max9611 register addresses */
+#define MAX9611_REG_CSA_DATA 0x00
+#define MAX9611_REG_RS_DATA 0x02
+#define MAX9611_REG_TEMP_DATA 0x08
+#define MAX9611_REG_CTRL1 0x0a
+#define MAX9611_REG_CTRL2 0x0b
+
+/* max9611 REG1 mux configuration options */
+#define MAX9611_MUX_MASK GENMASK(3, 0)
+#define MAX9611_MUX_SENSE_1x 0x00
+#define MAX9611_MUX_SENSE_4x 0x01
+#define MAX9611_MUX_SENSE_8x 0x02
+#define MAX9611_INPUT_VOLT 0x03
+#define MAX9611_MUX_TEMP 0x06
+
+/* max9611 voltage (both csa and input) helper macros */
+#define MAX9611_VOLTAGE_SHIFT 0x04
+#define MAX9611_VOLTAGE_RAW(_r) ((_r) >> MAX9611_VOLTAGE_SHIFT)
+
+/*
+ * max9611 current sense amplifier voltage output:
+ * LSB and offset values depends on selected gain (1x, 4x, 8x)
+ *
+ * GAIN LSB (nV) OFFSET (LSB steps)
+ * 1x 107500 1
+ * 4x 26880 1
+ * 8x 13440 3
+ *
+ * The complete formula to calculate current sense voltage is:
+ * (((adc_read >> 4) - offset) / ((1 / LSB) * 10^-3)
+ */
+#define MAX9611_CSA_1X_LSB_nV 107500
+#define MAX9611_CSA_4X_LSB_nV 26880
+#define MAX9611_CSA_8X_LSB_nV 13440
+
+#define MAX9611_CSA_1X_OFFS_RAW 1
+#define MAX9611_CSA_4X_OFFS_RAW 1
+#define MAX9611_CSA_8X_OFFS_RAW 3
+
+/*
+ * max9611 common input mode (CIM): LSB is 14mV, with 14mV offset at 25 C
+ *
+ * The complete formula to calculate input common voltage is:
+ * (((adc_read >> 4) * 1000) - offset) / (1 / 14 * 1000)
+ */
+#define MAX9611_CIM_LSB_mV 14
+#define MAX9611_CIM_OFFSET_RAW 1
+
+/*
+ * max9611 temperature reading: LSB is 480 milli degrees Celsius
+ *
+ * The complete formula to calculate temperature is:
+ * ((adc_read >> 7) * 1000) / (1 / 480 * 1000)
+ */
+#define MAX9611_TEMP_MAX_POS 0x7f80
+#define MAX9611_TEMP_MAX_NEG 0xff80
+#define MAX9611_TEMP_MIN_NEG 0xd980
+#define MAX9611_TEMP_MASK GENMASK(7, 15)
+#define MAX9611_TEMP_SHIFT 0x07
+#define MAX9611_TEMP_RAW(_r) ((_r) >> MAX9611_TEMP_SHIFT)
+#define MAX9611_TEMP_SCALE_NUM 1000000
+#define MAX9611_TEMP_SCALE_DIV 2083
+
+struct max9611_dev {
+ struct device *dev;
+ struct i2c_client *i2c_client;
+ struct mutex lock;
+ unsigned int shunt_resistor_uohm;
+};
+
+enum max9611_conf_ids {
+ CONF_SENSE_1x,
+ CONF_SENSE_4x,
+ CONF_SENSE_8x,
+ CONF_IN_VOLT,
+ CONF_TEMP,
+};
+
+/**
+ * max9611_mux_conf - associate ADC mux configuration with register address
+ * where data shall be read from
+ */
+static const unsigned int max9611_mux_conf[][2] = {
+ /* CONF_SENSE_1x */
+ { MAX9611_MUX_SENSE_1x, MAX9611_REG_CSA_DATA },
+ /* CONF_SENSE_4x */
+ { MAX9611_MUX_SENSE_4x, MAX9611_REG_CSA_DATA },
+ /* CONF_SENSE_8x */
+ { MAX9611_MUX_SENSE_8x, MAX9611_REG_CSA_DATA },
+ /* CONF_IN_VOLT */
+ { MAX9611_INPUT_VOLT, MAX9611_REG_RS_DATA },
+ /* CONF_TEMP */
+ { MAX9611_MUX_TEMP, MAX9611_REG_TEMP_DATA },
+};
+
+enum max9611_csa_gain {
+ CSA_GAIN_1x,
+ CSA_GAIN_4x,
+ CSA_GAIN_8x,
+};
+
+enum max9611_csa_gain_params {
+ CSA_GAIN_LSB_nV,
+ CSA_GAIN_OFFS_RAW,
+};
+
+/**
+ * max9611_csa_gain_conf - associate gain multiplier with LSB and
+ * offset values.
+ *
+ * Group together parameters associated with configurable gain
+ * on current sense amplifier path to ADC interface.
+ * Current sense read routine adjusts gain until it gets a meaningful
+ * value; use this structure to retrieve the correct LSB and offset values.
+ */
+static const unsigned int max9611_gain_conf[][2] = {
+ { /* [0] CSA_GAIN_1x */
+ MAX9611_CSA_1X_LSB_nV,
+ MAX9611_CSA_1X_OFFS_RAW,
+ },
+ { /* [1] CSA_GAIN_4x */
+ MAX9611_CSA_4X_LSB_nV,
+ MAX9611_CSA_4X_OFFS_RAW,
+ },
+ { /* [2] CSA_GAIN_8x */
+ MAX9611_CSA_8X_LSB_nV,
+ MAX9611_CSA_8X_OFFS_RAW,
+ },
+};
+
+enum max9611_chan_addrs {
+ MAX9611_CHAN_VOLTAGE_INPUT,
+ MAX9611_CHAN_VOLTAGE_SENSE,
+ MAX9611_CHAN_TEMPERATURE,
+ MAX9611_CHAN_CURRENT_LOAD,
+ MAX9611_CHAN_POWER_LOAD,
+};
+
+static const struct iio_chan_spec max9611_channels[] = {
+ {
+ .type = IIO_TEMP,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_SCALE),
+ .address = MAX9611_CHAN_TEMPERATURE,
+ },
+ {
+ .type = IIO_VOLTAGE,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
+ .address = MAX9611_CHAN_VOLTAGE_SENSE,
+ .indexed = 1,
+ .channel = 0,
+ },
+ {
+ .type = IIO_VOLTAGE,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_SCALE) |
+ BIT(IIO_CHAN_INFO_OFFSET),
+ .address = MAX9611_CHAN_VOLTAGE_INPUT,
+ .indexed = 1,
+ .channel = 1,
+ },
+ {
+ .type = IIO_CURRENT,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
+ .address = MAX9611_CHAN_CURRENT_LOAD,
+ },
+ {
+ .type = IIO_POWER,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
+ .address = MAX9611_CHAN_POWER_LOAD
+ },
+};
+
+/**
+ * max9611_read_single() - read a single value from ADC interface
+ *
+ * Data registers are 16 bit long, spread between two 8 bit registers
+ * with consecutive addresses.
+ * Configure ADC mux first, then read register at address "reg_addr".
+ * The smbus_read_word routine asks for 16 bits and the ADC is kind enough
+ * to return values from "reg_addr" and "reg_addr + 1" consecutively.
+ * Data are transmitted with big-endian ordering: MSB arrives first.
+ *
+ * @max9611: max9611 device
+ * @selector: index for mux and register configuration
+ * @raw_val: the value returned from ADC
+ */
+static int max9611_read_single(struct max9611_dev *max9611,
+ enum max9611_conf_ids selector,
+ u16 *raw_val)
+{
+ int ret;
+
+ u8 mux_conf = max9611_mux_conf[selector][0] & MAX9611_MUX_MASK;
+ u8 reg_addr = max9611_mux_conf[selector][1];
+
+ /*
+ * Keep mutex lock held during read-write to avoid mux register
+ * (CTRL1) re-configuration.
+ */
+ mutex_lock(&max9611->lock);
+ ret = i2c_smbus_write_byte_data(max9611->i2c_client,
+ MAX9611_REG_CTRL1, mux_conf);
+ if (ret) {
+ dev_err(max9611->dev, "i2c write byte failed: 0x%2x - 0x%2x\n",
+ MAX9611_REG_CTRL1, mux_conf);
+ mutex_unlock(&max9611->lock);
+ return ret;
+ }
+
+ /*
+ * need a delay here to make register configuration
+ * stabilize. 1 msec at least, from empirical testing.
+ */
+ usleep_range(1000, 2000);
+
+ ret = i2c_smbus_read_word_swapped(max9611->i2c_client, reg_addr);
+ if (ret < 0) {
+ dev_err(max9611->dev, "i2c read word from 0x%2x failed\n",
+ reg_addr);
+ mutex_unlock(&max9611->lock);
+ return ret;
+ }
+
+ *raw_val = ret;
+ mutex_unlock(&max9611->lock);
+
+ return 0;
+}
+
+/**
+ * max9611_read_csa_voltage() - read current sense amplifier output voltage
+ *
+ * Current sense amplifier output voltage is read through a configurable
+ * 1x, 4x or 8x gain.
+ * Start with plain 1x gain, and adjust gain control properly until a
+ * meaningful value is read from ADC output.
+ *
+ * @max9611: max9611 device
+ * @adc_raw: raw value read from ADC output
+ * @csa_gain: gain configuration option selector
+ */
+static int max9611_read_csa_voltage(struct max9611_dev *max9611,
+ u16 *adc_raw,
+ enum max9611_csa_gain *csa_gain)
+{
+ enum max9611_conf_ids gain_selectors[] = {
+ CONF_SENSE_1x,
+ CONF_SENSE_4x,
+ CONF_SENSE_8x
+ };
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(gain_selectors); ++i) {
+ ret = max9611_read_single(max9611, gain_selectors[i], adc_raw);
+ if (ret)
+ return ret;
+
+ if (*adc_raw > 0) {
+ *csa_gain = gain_selectors[i];
+ return 0;
+ }
+ }
+
+ return -EIO;
+}
+
+static int max9611_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2, long mask)
+{
+ struct max9611_dev *dev = iio_priv(indio_dev);
+ enum max9611_csa_gain gain_selector;
+ const unsigned int *csa_gain;
+ u16 adc_data;
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+
+ switch (chan->address) {
+ case MAX9611_CHAN_TEMPERATURE:
+ ret = max9611_read_single(dev, CONF_TEMP,
+ &adc_data);
+ if (ret)
+ return -EINVAL;
+
+ *val = MAX9611_TEMP_RAW(adc_data);
+ return IIO_VAL_INT;
+
+ case MAX9611_CHAN_VOLTAGE_INPUT:
+ ret = max9611_read_single(dev, CONF_IN_VOLT,
+ &adc_data);
+ if (ret)
+ return -EINVAL;
+
+ *val = MAX9611_VOLTAGE_RAW(adc_data);
+ return IIO_VAL_INT;
+ }
+
+ break;
+
+ case IIO_CHAN_INFO_OFFSET:
+ /* MAX9611_CHAN_VOLTAGE_INPUT */
+ *val = MAX9611_CIM_OFFSET_RAW;
+
+ return IIO_VAL_INT;
+
+ case IIO_CHAN_INFO_SCALE:
+
+ switch (chan->address) {
+ case MAX9611_CHAN_TEMPERATURE:
+ *val = MAX9611_TEMP_SCALE_NUM;
+ *val2 = MAX9611_TEMP_SCALE_DIV;
+
+ return IIO_VAL_FRACTIONAL;
+
+ case MAX9611_CHAN_VOLTAGE_INPUT:
+ *val = MAX9611_CIM_LSB_mV;
+
+ return IIO_VAL_INT;
+ }
+
+ break;
+
+ case IIO_CHAN_INFO_PROCESSED:
+
+ switch (chan->address) {
+ case MAX9611_CHAN_VOLTAGE_SENSE:
+ /*
+ * processed (mV): (raw - offset) * LSB (nV) / 10^6
+ *
+ * Even if max9611 can output raw csa voltage readings,
+ * use a produced value as scale depends on gain.
+ */
+ ret = max9611_read_csa_voltage(dev, &adc_data,
+ &gain_selector);
+ if (ret)
+ return -EINVAL;
+
+ csa_gain = max9611_gain_conf[gain_selector];
+
+ adc_data -= csa_gain[CSA_GAIN_OFFS_RAW];
+ *val = MAX9611_VOLTAGE_RAW(adc_data) *
+ csa_gain[CSA_GAIN_LSB_nV];
+ *val2 = 1000000;
+
+ return IIO_VAL_FRACTIONAL;
+
+ case MAX9611_CHAN_CURRENT_LOAD:
+ /* processed (mA): Vcsa (nV) / Rshunt (uOhm) */
+ ret = max9611_read_csa_voltage(dev, &adc_data,
+ &gain_selector);
+ if (ret)
+ return -EINVAL;
+
+ csa_gain = max9611_gain_conf[gain_selector];
+
+ adc_data -= csa_gain[CSA_GAIN_OFFS_RAW];
+ *val = MAX9611_VOLTAGE_RAW(adc_data) *
+ csa_gain[CSA_GAIN_LSB_nV];
+ *val2 = dev->shunt_resistor_uohm;
+
+ return IIO_VAL_FRACTIONAL;
+
+ case MAX9611_CHAN_POWER_LOAD:
+ /*
+ * processed (mW): Vin (mV) * Vcsa (uV) /
+ * Rshunt (uOhm)
+ */
+ ret = max9611_read_single(dev, CONF_IN_VOLT,
+ &adc_data);
+ if (ret)
+ return -EINVAL;
+
+ adc_data -= MAX9611_CIM_OFFSET_RAW;
+ *val = MAX9611_VOLTAGE_RAW(adc_data) *
+ MAX9611_CIM_LSB_mV;
+
+ ret = max9611_read_csa_voltage(dev, &adc_data,
+ &gain_selector);
+ if (ret)
+ return -EINVAL;
+
+ csa_gain = max9611_gain_conf[gain_selector];
+
+ /* divide by 10^3 here to avoid 32bit overflow */
+ adc_data -= csa_gain[CSA_GAIN_OFFS_RAW];
+ *val *= MAX9611_VOLTAGE_RAW(adc_data) *
+ csa_gain[CSA_GAIN_LSB_nV] / 1000;
+ *val2 = dev->shunt_resistor_uohm;
+
+ return IIO_VAL_FRACTIONAL;
+ }
+
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static ssize_t max9611_shunt_resistor_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct max9611_dev *max9611 = iio_priv(dev_to_iio_dev(dev));
+ unsigned int i, r;
+
+ i = max9611->shunt_resistor_uohm / 1000;
+ r = max9611->shunt_resistor_uohm % 1000;
+
+ return sprintf(buf, "%u.%03u\n", i, r);
+}
+
+static IIO_DEVICE_ATTR(in_power_shunt_resistor, 0444,
+ max9611_shunt_resistor_show, NULL, 0);
+static IIO_DEVICE_ATTR(in_current_shunt_resistor, 0444,
+ max9611_shunt_resistor_show, NULL, 0);
+
+static struct attribute *max9611_attributes[] = {
+ &iio_dev_attr_in_power_shunt_resistor.dev_attr.attr,
+ &iio_dev_attr_in_current_shunt_resistor.dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group max9611_attribute_group = {
+ .attrs = max9611_attributes,
+};
+
+static const struct iio_info indio_info = {
+ .driver_module = THIS_MODULE,
+ .read_raw = max9611_read_raw,
+ .attrs = &max9611_attribute_group,
+};
+
+static int max9611_init(struct max9611_dev *max9611)
+{
+ struct i2c_client *client = max9611->i2c_client;
+ u16 regval;
+ int ret;
+
+ if (!i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_WRITE_BYTE |
+ I2C_FUNC_SMBUS_READ_WORD_DATA)) {
+ dev_err(max9611->dev,
+ "I2c adapter does not support smbus write_byte or read_word functionalities: aborting probe.\n");
+ return -EINVAL;
+ }
+
+ /* Make sure die temperature is in range to test communications. */
+ ret = max9611_read_single(max9611, CONF_TEMP, ®val);
+ if (ret)
+ return ret;
+
+ regval = ret & MAX9611_TEMP_MASK;
+
+ if ((regval > MAX9611_TEMP_MAX_POS &&
+ regval < MAX9611_TEMP_MIN_NEG) ||
+ regval > MAX9611_TEMP_MAX_NEG) {
+ dev_err(max9611->dev,
+ "Invalid value received from ADC 0x%4x: aborting\n",
+ regval);
+ return -EIO;
+ }
+
+ /* Mux shall be zeroed back before applying other configurations */
+ ret = i2c_smbus_write_byte_data(max9611->i2c_client,
+ MAX9611_REG_CTRL1, 0);
+ if (ret) {
+ dev_err(max9611->dev, "i2c write byte failed: 0x%2x - 0x%2x\n",
+ MAX9611_REG_CTRL1, 0);
+ return ret;
+ }
+
+ ret = i2c_smbus_write_byte_data(max9611->i2c_client,
+ MAX9611_REG_CTRL2, 0);
+ if (ret) {
+ dev_err(max9611->dev, "i2c write byte failed: 0x%2x - 0x%2x\n",
+ MAX9611_REG_CTRL2, 0);
+ return ret;
+ }
+ usleep_range(1000, 2000);
+
+ return 0;
+}
+
+static const struct of_device_id max9611_of_table[] = {
+ {.compatible = "maxim,max9611", .data = "max9611"},
+ {.compatible = "maxim,max9612", .data = "max9612"},
+ { },
+};
+
+MODULE_DEVICE_TABLE(of, max9611_of_table);
+static int max9611_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ const char * const shunt_res_prop = "shunt-resistor-micro-ohms";
+ const struct device_node *of_node = client->dev.of_node;
+ const struct of_device_id *of_id =
+ of_match_device(max9611_of_table, &client->dev);
+ struct max9611_dev *max9611;
+ struct iio_dev *indio_dev;
+ unsigned int of_shunt;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*max9611));
+ if (IS_ERR(indio_dev))
+ return PTR_ERR(indio_dev);
+
+ i2c_set_clientdata(client, indio_dev);
+
+ max9611 = iio_priv(indio_dev);
+ max9611->dev = &client->dev;
+ max9611->i2c_client = client;
+ mutex_init(&max9611->lock);
+
+ ret = of_property_read_u32(of_node, shunt_res_prop, &of_shunt);
+ if (ret) {
+ dev_err(&client->dev,
+ "Missing %s property for %s node\n",
+ shunt_res_prop, of_node->full_name);
+ return ret;
+ }
+ max9611->shunt_resistor_uohm = of_shunt;
+
+ ret = max9611_init(max9611);
+ if (ret)
+ return ret;
+
+ indio_dev->dev.parent = &client->dev;
+ indio_dev->dev.of_node = client->dev.of_node;
+ indio_dev->name = of_id->data;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &indio_info;
+ indio_dev->channels = max9611_channels;
+ indio_dev->num_channels = ARRAY_SIZE(max9611_channels);
+
+ return devm_iio_device_register(&client->dev, indio_dev);
+}
+
+static struct i2c_driver max9611_driver = {
+ .driver = {
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = max9611_of_table,
+ },
+ .probe = max9611_probe,
+};
+module_i2c_driver(max9611_driver);
+
+MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>");
+MODULE_DESCRIPTION("Maxim max9611/12 current sense amplifier with 12bit ADC");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related
* [PATCH v5 4/4] arm64: dts: salvator-x: Add current sense amplifiers
From: Jacopo Mondi @ 2017-04-06 14:20 UTC (permalink / raw)
To: geert, wsa+renesas, magnus.damm, laurent.pinchart, jic23,
knaack.h, lars, pmeerw, robh+dt, mark.rutland
Cc: linux-iio, linux-renesas-soc, devicetree
In-Reply-To: <1491488454-22468-1-git-send-email-jacopo+renesas@jmondi.org>
Add device nodes for two Maxim max961x current sense amplifiers
sensing VDD_08 and DVFS_08 lines.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index c7f40f8..c4860a1 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -257,6 +257,24 @@
status = "okay";
};
+&i2c4 {
+ status = "okay";
+
+ csa_vdd: adc@7c {
+ compatible = "maxim,max9611";
+ reg = <0x7c>;
+
+ shunt-resistor-micro-ohms = <5000>;
+ };
+
+ csa_dvfs: adc@7f {
+ compatible = "maxim,max9611";
+ reg = <0x7f>;
+
+ shunt-resistor-micro-ohms = <5000>;
+ };
+};
+
&wdt0 {
timeout-sec = <60>;
status = "okay";
--
2.7.4
^ permalink raw reply related
* [PATCH V2 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups
From: Laxman Dewangan @ 2017-04-06 14:20 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, jonathanh-DDmLM1+adcrQT0dZR+AlfA
Cc: mark.rutland-5wv7dgnIgG8, linux-pwm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Laxman Dewangan
This patch series have following fixes:
- Add more precession in PWM period register value calculation
for lower pwm frequency.
- Add support to configure PWM pins in different state in the
suspend/resume.
Changes from v1:
- Use standard pinctrl names for sleep and active state.
- Use API pinctrl_pm_select_*()
Laxman Dewangan (4):
pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local
implementation
pwm: tegra: Increase precision in pwm rate calculation
pwm: tegra: Add DT binding details to configure pin in suspends/resume
pwm: tegra: Add support to configure pin state in suspends/resume
.../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 43 ++++++++++++
drivers/pwm/pwm-tegra.c | 77 ++++++++++++++++++++--
2 files changed, 116 insertions(+), 4 deletions(-)
--
2.1.4
--
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^ permalink raw reply
* [PATCH V2 1/4] pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation
From: Laxman Dewangan @ 2017-04-06 14:20 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, jonathanh-DDmLM1+adcrQT0dZR+AlfA
Cc: mark.rutland-5wv7dgnIgG8, linux-pwm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Laxman Dewangan
In-Reply-To: <1491488461-24621-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closet one
instead of implementing the same locally. This increase readability.
Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
Changes from V1:
None
drivers/pwm/pwm-tegra.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index e464784..0a688da 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -85,8 +85,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
* nearest integer during division.
*/
c *= (1 << PWM_DUTY_WIDTH);
- c += period_ns / 2;
- do_div(c, period_ns);
+ c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
val = (u32)c << PWM_DUTY_SHIFT;
--
2.1.4
--
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^ permalink raw reply related
* [PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate calculation
From: Laxman Dewangan @ 2017-04-06 14:20 UTC (permalink / raw)
To: thierry.reding, robh+dt, jonathanh
Cc: mark.rutland, linux-pwm, devicetree, linux-tegra, linux-kernel,
Laxman Dewangan
In-Reply-To: <1491488461-24621-1-git-send-email-ldewangan@nvidia.com>
The rate of the PWM calculated as follows:
hz = NSEC_PER_SEC / period_ns;
rate = (rate + (hz / 2)) / hz;
This has the precision loss in lower PWM rate.
Changing this to have more precision as:
hz = DIV_ROUND_CLOSE(NSEC_PER_SEC * 100, period_ns);
rate = DIV_ROUND_CLOSE(rate * 100, hz)
Example:
1. period_ns = 16672000, PWM clock rate is 200KHz.
Based on old formula
hz = NSEC_PER_SEC / period_ns
= 1000000000ul/16672000
= 59 (59.98)
rate = (200K + 59/2)/59 = 3390
Based on new method:
hz = 5998
rate = DIV_ROUND_CLOSE(200000*100, 5998) = 3334
If we measure the PWM signal rate, we will get more accurate period
with rate value of 3334 instead of 3390.
2. period_ns = 16803898, PWM clock rate is 200KHz.
Based on old formula:
hz = 60, rate = 3333
Based on new formula:
hz = 5951, rate = 3360
The rate of 3360 is more near to requested period then the 3333.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
- None
drivers/pwm/pwm-tegra.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 0a688da..e9c4de5 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -76,6 +76,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
unsigned long long c = duty_ns;
unsigned long rate, hz;
+ unsigned long long ns100 = NSEC_PER_SEC;
+ unsigned long precision = 100; /* Consider 2 digit precision */
u32 val = 0;
int err;
@@ -94,9 +96,11 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
* cycles at the PWM clock rate will take period_ns nanoseconds.
*/
rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
- hz = NSEC_PER_SEC / period_ns;
- rate = (rate + (hz / 2)) / hz;
+ /* Consider precision in PWM_SCALE_WIDTH rate calculation */
+ ns100 *= precision;
+ hz = DIV_ROUND_CLOSEST_ULL(ns100, period_ns);
+ rate = DIV_ROUND_CLOSEST(rate * precision, hz);
/*
* Since the actual PWM divider is the register's frequency divider
--
2.1.4
^ permalink raw reply related
* [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume
From: Laxman Dewangan @ 2017-04-06 14:21 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, jonathanh-DDmLM1+adcrQT0dZR+AlfA
Cc: mark.rutland-5wv7dgnIgG8, linux-pwm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Laxman Dewangan
In-Reply-To: <1491488461-24621-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
In some of NVIDIA Tegra's platform, PWM controller is used to
control the PWM controlled regulators. PWM signal is connected to
the VID pin of the regulator where duty cycle of PWM signal decide
the voltage level of the regulator output.
The tristate (high impedance of PWM pin form Tegra) also define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add DT binding details to provide the pin configuration state
from PWM and pinctrl DT node in suspend and active state of
the system.
Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
Changes from v1:
- Use standard pinctrl names for sleep and active state.
.../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index b4e7377..4128cdc 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -19,6 +19,19 @@ Required properties:
- reset-names: Must include the following entries:
- pwm
+Optional properties:
+============================
+In some of the interface like PWM based regulator device, it is required
+to configure the pins differently in different states, especially in suspend
+state of the system. The configuration of pin is provided via the pinctrl
+DT node as detailed in the pinctrl DT binding document
+ Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+The PWM node will have following optional properties.
+pinctrl-names: Pin state names. Must be "default" and "sleep".
+pinctrl-0: Node handle for the default/active state of pi configurations.
+pinctrl-1: Node handle for the sleep state of pin configurations.
+
Example:
pwm: pwm@7000a000 {
@@ -29,3 +42,33 @@ Example:
resets = <&tegra_car 17>;
reset-names = "pwm";
};
+
+
+Example with the pin configuration for suspend and resume:
+=========================================================
+Pin PE7 is used as PWM interface.
+
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+ pinmux@70000868 {
+ pwm_active_state: pwm_active_state {
+ pe7 {
+ nvidia,pins = "pe7";
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ };
+
+ pwm_sleep_state: pwm_sleep_state {
+ pe7 {
+ nvidia,pins = "pe7";
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
+ pwm@7000a000 {
+ /* Mandatory PWM properties */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pwm_active_state>;
+ pinctrl-1 = <&pwm_sleep_state>;
+ };
--
2.1.4
^ permalink raw reply related
* [PATCH V4 4/4] pwm: tegra: Add support to configure pin state in suspends/resume
From: Laxman Dewangan @ 2017-04-06 14:21 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, jonathanh-DDmLM1+adcrQT0dZR+AlfA
Cc: mark.rutland-5wv7dgnIgG8, linux-pwm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Laxman Dewangan
In-Reply-To: <1491488461-24621-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
In some of NVIDIA Tegra's platform, PWM controller is used to
control the PWM controlled regulators. PWM signal is connected to
the VID pin of the regulator where duty cycle of PWM signal decide
the voltage level of the regulator output.
The tristate (high impedance of PWM pin form Tegra) also define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add support to configure the pin state via pinctrl frameworks in
suspend and active state of the system.
Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
Changes from v1:
- Use standard pinctrl names for sleep and active state.
- Use API pinctrl_pm_select_*()
drivers/pwm/pwm-tegra.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index e9c4de5..af1bd4f 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -29,6 +29,7 @@
#include <linux/of_device.h>
#include <linux/pwm.h>
#include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
#include <linux/slab.h>
#include <linux/reset.h>
@@ -256,6 +257,22 @@ static int tegra_pwm_remove(struct platform_device *pdev)
return pwmchip_remove(&pc->chip);
}
+#ifdef CONFIG_PM_SLEEP
+static int tegra_pwm_suspend(struct device *dev)
+{
+ pinctrl_pm_select_sleep_state(dev);
+
+ return 0;
+}
+
+static int tegra_pwm_resume(struct device *dev)
+{
+ pinctrl_pm_select_default_state(dev);
+
+ return 0;
+}
+#endif
+
static const struct tegra_pwm_soc tegra20_pwm_soc = {
.num_channels = 4,
};
@@ -272,10 +289,15 @@ static const struct of_device_id tegra_pwm_of_match[] = {
MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
+static const struct dev_pm_ops tegra_pwm_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume)
+};
+
static struct platform_driver tegra_pwm_driver = {
.driver = {
.name = "tegra-pwm",
.of_match_table = tegra_pwm_of_match,
+ .pm = &tegra_pwm_pm_ops,
},
.probe = tegra_pwm_probe,
.remove = tegra_pwm_remove,
--
2.1.4
--
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^ permalink raw reply related
* Re: [PATCH v3 0/2] switch to atomic PWM
From: Thierry Reding @ 2017-04-06 14:33 UTC (permalink / raw)
To: Claudiu Beznea
Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
boris.brezillon, alexandre.belloni, linux-pwm, devicetree,
linux-kernel, linux-arm-kernel, nicolas.ferre, cristian.birsan,
andrei.pistirica, tudor.ambarus, eugen.hristev
In-Reply-To: <1490189375-20384-1-git-send-email-claudiu.beznea@microchip.com>
[-- Attachment #1: Type: text/plain, Size: 3774 bytes --]
On Wed, Mar 22, 2017 at 03:29:33PM +0200, Claudiu Beznea wrote:
> Changes in v3:
> - since v2 introduced per-IP register layout there is no need
> to keep update_cdty and set_cprd_cdty members in atmel_pwm_data
> data structure used in v2; doing in this way the atmel_pwm_data
> data structure will remain with only one member, regs. To avoid
> another level of indirection, the atmel_pwm_data has been removed
> and only atmel_pwm_registers data structure has been keept. In
> this way, "data" member of atmel_pwm_chip data structure was
> replaced by "regs" member; due to these changes prototype of
> atmel_pwm_get_driver_data() function was also changed;
> also, driver private data variables were renamed in the following
> format "atmel_pwm_regs_v*"
> - there is no need for the following checks at the begining
> of atmel_pwm_apply() which were present in v2:
>
> if (cstate.enabled &&
> (cstate.polarity != state->polarity ||
> cstate.period != state->period))
> pwm_reset = true;
>
> it is enough to add:
>
> if (state->enabled) {
> if (cstate.enabled &&
> cstate.polarity == state->polarity &&
> cstate.period == state->period) {
>
> inside "if (state->enabled)" block and also to check cstate.enabled
> instead of checking pwm_reset variable introduced in v2:
>
> if (cstate.enabled) {
> atmel_pwm_disable(chip, pwm, false);
> } else {
> ret = clk_enable(atmel_pwm->clk);
> if (ret) {
> dev_err(chip->dev, "failed to enable clock\n");
> return ret;
> }
> }
>
> Changes in v2:
> - update only duty factor without disabling the PWM channel
> - if PWM channel is enabled, period, as signal polarity, is
> updated by disabling + enabling the PWM channel
> - atmel_pwm_config_prepare() function has been removed and
> added instead two functions, one to compute the CPRD+Prescaler
> (atmel_pwm_calculate_cprd_and_pres()), one to compute CRDY
> (atmel_pwm_calculate_cdty())
> - atmel_pwm_config_set() body was directly moved to atmel_pwm_apply()
> - add 3 new members to atmel_pwm_data: update_cdty, set_cprd_cdty and
> regs:
> - update_cdty is called to configure duty factor without
> disabling PWM channel, when necessary
> - set_cprd_cdty is called to configure both period and
> duty factor parameters
> - regs keeps the period and duty registers and was added to
> have common functions for update_cdty and set_cprd_cdty
> members of atmel_pwm_data for all boards;
> - add a new parameter to atmel_pwm_disable(); this will be used in
> updating period + signal polarity by disabling + enabling the
> PWM channel. In this case, there is no need to disable PWM clock
> since new configuration will be imediately applied.
> - adapted the other reviewer comments excepts the one regarding
> "cdty = cprd - cycles;" from atmel_pwm_calculate_cdty() since
> in atmel_pwm_apply(), selecting polarity in the other way arround
> than is currently done in this commit will need the changing of DPOLI
> bit from Channel Mode Register, in order to keep the initial
> output level of PWM channel after disable operation; this works
> for sama5d2 but not for sam9rl which hasn't document the DPOLI
> bit in datasheet; sama5d3 also hasn't document the DPOLI bit in
> datasheet; one option was to have different aproach for different
> boards but the code becomes messy.
>
> Claudiu Beznea (2):
> drivers: pwm: pwm-atmel: switch to atomic PWM
> drivers: pwm: pwm-atmel: enable PWM on sama5d2
>
> .../devicetree/bindings/pwm/atmel-pwm.txt | 1 +
> drivers/pwm/pwm-atmel.c | 276 ++++++++++-----------
> 2 files changed, 133 insertions(+), 144 deletions(-)
Applied, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH] [media] imx: csi: retain current field order and colorimetry setting as default
From: Russell King - ARM Linux @ 2017-04-06 14:38 UTC (permalink / raw)
To: Hans Verkuil
Cc: Philipp Zabel, Steve Longerbeam, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, shawnguo-DgEjT+Ai2ygdnm+yROfE0A,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, fabio.estevam-3arQi8VN3Tc,
mchehab-DgEjT+Ai2ygdnm+yROfE0A, nick-gcszYUEDH4VrovVCs/uTlw,
markus.heiser-O6JHGLzbNUwb1SvskN2V4Q,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
bparrot-l0cyMroinI0, geert-Td1EMuHUCqxL1ZNQvxDV9g,
arnd-r2nGTMty4D4, sudipm.mukherjee-Re5JQEeQqe8AvxtiuMwx3w,
minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w,
tiffany.lin-NuS5LvNUpcJWk0Htik3J/w,
jean-christophe.trotin-qxv4g6HH51o,
horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ,
niklas.soderlund+renesas-1zkq55x86MTxsAP9Fp7wbw,
robert.jarzmik-GANU6spQydw, songjun.wu-UWL1GkI3JZL3oGB3hsPCZA,
andrew-ct.chen-NuS5LvNUpcJWk0Htik3J/w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
shuah-DgEjT+Ai2ygdnm+yROfE0A, sakari.ailus-VuQAYsv1563Yd54FQh9/CA,
pavel-+ZI9xUNit7I, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel
In-Reply-To: <0f9690f8-c7f6-59ff-9e3e-123af9972d4b-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org>
On Thu, Apr 06, 2017 at 04:20:21PM +0200, Hans Verkuil wrote:
> On 04/06/2017 03:55 PM, Philipp Zabel wrote:
> > If the the field order is set to ANY in set_fmt, choose the currently
> > set field order. If the colorspace is set to DEFAULT, choose the current
> > colorspace. If any of xfer_func, ycbcr_enc or quantization are set to
> > DEFAULT, either choose the current setting, or the default setting for the
> > new colorspace, if non-DEFAULT colorspace was given.
> >
> > This allows to let field order and colorimetry settings be propagated
> > from upstream by calling media-ctl on the upstream entity source pad,
> > and then call media-ctl on the sink pad to manually set the input frame
> > interval, without changing the already set field order and colorimetry
> > information.
> >
> > Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> > ---
> > This is based on imx-media-staging-md-v14, and it is supposed to allow
> > configuring the pipeline with media-ctl like this:
> >
> > 1) media-ctl --set-v4l2 "'tc358743 1-000f':0[fmt:UYVY8_1X16/1920x1080]"
> > 2) media-ctl --set-v4l2 "'imx6-mipi-csi2':1[fmt:UYVY8_1X16/1920x108]"
> > 3) media-ctl --set-v4l2 "'ipu1_csi0_mux':2[fmt:UYVY8_1X16/1920x1080]"
> > 4) media-ctl --set-v4l2 "'ipu1_csi0':0[fmt:UYVY8_1X16/1920x1080@1/60]"
> > 5) media-ctl --set-v4l2 "'ipu1_csi0':2[fmt:AYUV32/1920x1080@1/30]"
> >
> > Without having step 4) overwrite the colorspace and field order set on
> > 'ipu1_csi0':0 by the propagation in step 3).
> > ---
> > drivers/staging/media/imx/imx-media-csi.c | 34 +++++++++++++++++++++++++++++++
> > 1 file changed, 34 insertions(+)
> >
> > diff --git a/drivers/staging/media/imx/imx-media-csi.c b/drivers/staging/media/imx/imx-media-csi.c
> > index 64dc454f6b371..d94ce1de2bf05 100644
> > --- a/drivers/staging/media/imx/imx-media-csi.c
> > +++ b/drivers/staging/media/imx/imx-media-csi.c
> > @@ -1325,6 +1325,40 @@ static int csi_set_fmt(struct v4l2_subdev *sd,
> > csi_try_fmt(priv, sensor, cfg, sdformat, crop, compose, &cc);
> >
> > fmt = __csi_get_fmt(priv, cfg, sdformat->pad, sdformat->which);
> > +
> > + /* Retain current field setting as default */
> > + if (sdformat->format.field == V4L2_FIELD_ANY)
> > + sdformat->format.field = fmt->field;
>
> sdformat->format.field should never be FIELD_ANY. If it is, then that's a
> subdev bug and I'm pretty sure FIELD_NONE was intended.
Please explain further - sdformat->format.field is the field passed _in_
from userspace, and from what I can see, userspace is free to pass in
any value through the ioctl as check_format() does nothing to validate
that the various format.* fields are sane.
This patch is detecting that the user is requesting FIELD_ANY, and
fixing it up. Surely that's the right thing to do, and is way more
preferable than just accepting the FIELD_ANY from userspace and
storing that value?
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
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^ permalink raw reply
* Re: [PATCH v4 13/14] pwm: jz4740: Let the pinctrl driver configure the pins
From: Thierry Reding @ 2017-04-06 14:40 UTC (permalink / raw)
To: Paul Cercueil
Cc: Linus Walleij, Alexandre Courbot, Rob Herring, Mark Rutland,
Ralf Baechle, Boris Brezillon, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton,
james.hogan-1AXoQHu6uovQT0dZR+AlfA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170402204244.14216-14-paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1509 bytes --]
On Sun, Apr 02, 2017 at 10:42:43PM +0200, Paul Cercueil wrote:
> Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
> the pins being properly configured before the driver probes.
>
> One inherent problem of this new approach is that the pinctrl framework
> does not allow us to configure each pin on demand, when the various PWM
> channels are requested or released. For instance, the PWM channels can
> be configured from sysfs, which would require all PWM pins to be configured
> properly beforehand for the PWM function, eventually causing conflicts
> with other platform or board drivers.
>
> The proper solution here would be to modify the pwm-jz4740 driver to
> handle only one PWM channel, and create an instance of this driver
> for each one of the 8 PWM channels. Then, it could use the pinctrl
> framework to dynamically configure the PWM pin it controls.
>
> Until this can be done, the only jz4740 board supported upstream
> (Qi lb60) can configure all of its connected PWM pins in PWM function
> mode, since those are not used by other drivers nor by GPIOs on the
> board.
>
> Signed-off-by: Paul Cercueil <paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
> ---
> drivers/pwm/pwm-jz4740.c | 29 -----------------------------
> 1 file changed, 29 deletions(-)
Assuming that you want to take this through the pinctrl tree along with
the remainder of the series:
Acked-by: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH v5 1/4] Documentation: dt-bindings: iio: Add max9611 ADC
From: Geert Uytterhoeven @ 2017-04-06 14:43 UTC (permalink / raw)
To: Jacopo Mondi
Cc: Wolfram Sang, Magnus Damm, Laurent Pinchart, Jonathan Cameron,
Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald, Rob Herring,
Mark Rutland, linux-iio-u79uwXL29TY76Z2rM5mHXA, Linux-Renesas,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1491488454-22468-2-git-send-email-jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
On Thu, Apr 6, 2017 at 4:20 PM, Jacopo Mondi <jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org> wrote:
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/max9611.txt
> @@ -0,0 +1,27 @@
> +* Maxim max9611/max9612 current sense amplifier with 12-bits ADC interface
> +
> +Maxim max9611/max9612 is an high-side current sense amplifier with integrated
> +12-bits ADC communicating over I2c bus.
> +The device node for this driver shall be a child of a I2c controller.
> +
> +Required properties
> + - compatible: Should be "maxim,max9611" or "maxim,max9612"
> + - reg: The 7-bits long I2c address of the device
> + - shunt-resistor-micro-homs: Value, in micro Ohms, of the current sense shunt
s/homs/ohms/
> + resistor
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH V10 06/12] of: device: Fix overflow of coherent_dma_mask
From: Robin Murphy @ 2017-04-06 14:45 UTC (permalink / raw)
To: Rob Herring
Cc: Catalin Marinas, Will Deacon, Sinan Kaya, Frank Rowand,
linux-arch-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Tomasz Nowicki,
linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Len Brown,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Arnd Bergmann,
linux-arm-msm, bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Greg Kroah-Hartman, Rafael J. Wysocki,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Linux IOMMU,
Sudeep Holla <sudeep.holla>
In-Reply-To: <CAL_JsqLsE378hfs=xNvSdPV2r+7H81cAFzOwtda2W+mFVoohuA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 06/04/17 14:56, Rob Herring wrote:
> On Thu, Apr 6, 2017 at 5:24 AM, Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> wrote:
>> On 06/04/17 08:01, Frank Rowand wrote:
>>> On 04/04/17 03:18, Sricharan R wrote:
>>>> Size of the dma-range is calculated as coherent_dma_mask + 1
>>>> and passed to arch_setup_dma_ops further. It overflows when
>>>> the coherent_dma_mask is set for full 64 bits 0xFFFFFFFFFFFFFFFF,
>>>> resulting in size getting passed as 0 wrongly. Fix this by
>>>> passsing in max(mask, mask + 1). Note that in this case
>>>> when the mask is set to full 64bits, we will be passing the mask
>>>> itself to arch_setup_dma_ops instead of the size. The real fix
>>>> for this should be to make arch_setup_dma_ops receive the
>>>> mask and handle it, to be done in the future.
>>>>
>>>> Signed-off-by: Sricharan R <sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>>>> ---
>>>> drivers/of/device.c | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/of/device.c b/drivers/of/device.c
>>>> index c17c19d..c2ae6bb 100644
>>>> --- a/drivers/of/device.c
>>>> +++ b/drivers/of/device.c
>>>> @@ -107,7 +107,7 @@ void of_dma_configure(struct device *dev, struct device_node *np)
>>>> ret = of_dma_get_range(np, &dma_addr, &paddr, &size);
>>>> if (ret < 0) {
>>>> dma_addr = offset = 0;
>>>> - size = dev->coherent_dma_mask + 1;
>>>> + size = max(dev->coherent_dma_mask, dev->coherent_dma_mask + 1);
>>>> } else {
>>>> offset = PFN_DOWN(paddr - dma_addr);
>>>> dev_dbg(dev, "dma_pfn_offset(%#08lx)\n", offset);
>>>>
>>>
>>> NACK.
>>>
>>> Passing an invalid size to arch_setup_dma_ops() is only part of the problem.
>>> size is also used in of_dma_configure() before calling arch_setup_dma_ops():
>>>
>>> dev->coherent_dma_mask = min(dev->coherent_dma_mask,
>>> DMA_BIT_MASK(ilog2(dma_addr + size)));
>>> *dev->dma_mask = min((*dev->dma_mask),
>>> DMA_BIT_MASK(ilog2(dma_addr + size)));
>>>
>>> which would be incorrect for size == 0xffffffffffffffffULL when
>>> dma_addr != 0. So the proposed fix really is not papering over
>>> the base problem very well.
>>
>> I'm not sure I agree there. Granted, there exist many more problematic
>> aspects than are dealt with here (I've got more patches cooking to sort
>> out some of the other issues we have with dma-ranges), but considering
>> size specifically:
>>
>> - It is not possible to explicitly specify a range with a size of 2^64
>> in DT. If someone does specify a size of 0, they've done a silly thing
>> and should not be surprised that it ends badly.
>
> And because of this, we allow ~0 (both 32 and 64 bit) in DT dma-ranges
> and fix these up as 2^32 and 2^64 sizes.
...which is what Frank's patch gets rid of.
Robin.
>
> Rob
>
^ permalink raw reply
* Re: [PATCH v3 1/3] clk: vc5: Add structure to describe particular chip features
From: Marek Vasut @ 2017-04-06 14:54 UTC (permalink / raw)
To: Alexey Firago, mturquette, sboyd, robh+dt, geert, linux-clk,
devicetree
In-Reply-To: <1491470130-6655-2-git-send-email-alexey_firago@mentor.com>
On 04/06/2017 11:15 AM, Alexey Firago wrote:
> Introduce vc5_chip_info structure to describe features of a particular
> VC5 chip (id, number of FODs, number of outputs, flags).
> For now flags are only used to indicate if chip has internal XTAL.
> vc5_chip_info is set on probe from the matched of_device_id->data.
>
> Also add defines to specify maximum number of FODs and clock outputs
> supported by the driver.
>
> With these changes it should be easier to extend driver to support
> more VC5 models.
>
> Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
> ---
> drivers/clk/clk-versaclock5.c | 65 +++++++++++++++++++++++++++++++------------
> 1 file changed, 47 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
> index 56741f3..4e81fb1 100644
> --- a/drivers/clk/clk-versaclock5.c
> +++ b/drivers/clk/clk-versaclock5.c
> @@ -113,12 +113,30 @@
> #define VC5_MUX_IN_XIN BIT(0)
> #define VC5_MUX_IN_CLKIN BIT(1)
>
> +/* Maximum number of clk_out supported by this driver */
> +#define VC5_MAX_CLK_OUT_NUM 3
> +
> +/* Maximum number of FODs supported by this driver */
> +#define VC5_MAX_FOD_NUM 2
> +
> +/* flags to describe chip features */
> +/* chip has built-in oscilator */
> +#define VC5_HAS_INTERNAL_XTAL BIT(0)
> +
> /* Supported IDT VC5 models. */
> enum vc5_model {
> IDT_VC5_5P49V5923,
> IDT_VC5_5P49V5933,
> };
>
> +/* Structure to describe features of a particular VC5 model */
> +struct vc5_chip_info {
> + const enum vc5_model model;
> + const unsigned int clk_fod_cnt;
> + const unsigned int clk_out_cnt;
> + u32 flags;
Shouldn't this also be const ?
> +};
[...]
--
Best regards,
Marek Vasut
^ permalink raw reply
* Re: [PATCH] [media] imx: csi: retain current field order and colorimetry setting as default
From: Philipp Zabel @ 2017-04-06 14:54 UTC (permalink / raw)
To: Hans Verkuil
Cc: Steve Longerbeam, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, shawnguo-DgEjT+Ai2ygdnm+yROfE0A,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, fabio.estevam-3arQi8VN3Tc,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, mchehab-DgEjT+Ai2ygdnm+yROfE0A,
nick-gcszYUEDH4VrovVCs/uTlw, markus.heiser-O6JHGLzbNUwb1SvskN2V4Q,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
bparrot-l0cyMroinI0, geert-Td1EMuHUCqxL1ZNQvxDV9g,
arnd-r2nGTMty4D4, sudipm.mukherjee-Re5JQEeQqe8AvxtiuMwx3w,
minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w,
tiffany.lin-NuS5LvNUpcJWk0Htik3J/w,
jean-christophe.trotin-qxv4g6HH51o,
horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ,
niklas.soderlund+renesas-1zkq55x86MTxsAP9Fp7wbw,
robert.jarzmik-GANU6spQydw, songjun.wu-UWL1GkI3JZL3oGB3hsPCZA,
andrew-ct.chen-NuS5LvNUpcJWk0Htik3J/w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
shuah-DgEjT+Ai2ygdnm+yROfE0A, sakari.ailus-VuQAYsv1563Yd54FQh9/CA,
pavel-+ZI9xUNit7I, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-medi
In-Reply-To: <0f9690f8-c7f6-59ff-9e3e-123af9972d4b-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org>
On Thu, 2017-04-06 at 16:20 +0200, Hans Verkuil wrote:
> On 04/06/2017 03:55 PM, Philipp Zabel wrote:
> > If the the field order is set to ANY in set_fmt, choose the currently
> > set field order. If the colorspace is set to DEFAULT, choose the current
> > colorspace. If any of xfer_func, ycbcr_enc or quantization are set to
> > DEFAULT, either choose the current setting, or the default setting for the
> > new colorspace, if non-DEFAULT colorspace was given.
> >
> > This allows to let field order and colorimetry settings be propagated
> > from upstream by calling media-ctl on the upstream entity source pad,
> > and then call media-ctl on the sink pad to manually set the input frame
> > interval, without changing the already set field order and colorimetry
> > information.
> >
> > Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> > ---
> > This is based on imx-media-staging-md-v14, and it is supposed to allow
> > configuring the pipeline with media-ctl like this:
> >
> > 1) media-ctl --set-v4l2 "'tc358743 1-000f':0[fmt:UYVY8_1X16/1920x1080]"
> > 2) media-ctl --set-v4l2 "'imx6-mipi-csi2':1[fmt:UYVY8_1X16/1920x108]"
> > 3) media-ctl --set-v4l2 "'ipu1_csi0_mux':2[fmt:UYVY8_1X16/1920x1080]"
> > 4) media-ctl --set-v4l2 "'ipu1_csi0':0[fmt:UYVY8_1X16/1920x1080@1/60]"
> > 5) media-ctl --set-v4l2 "'ipu1_csi0':2[fmt:AYUV32/1920x1080@1/30]"
> >
> > Without having step 4) overwrite the colorspace and field order set on
> > 'ipu1_csi0':0 by the propagation in step 3).
> > ---
> > drivers/staging/media/imx/imx-media-csi.c | 34 +++++++++++++++++++++++++++++++
> > 1 file changed, 34 insertions(+)
> >
> > diff --git a/drivers/staging/media/imx/imx-media-csi.c b/drivers/staging/media/imx/imx-media-csi.c
> > index 64dc454f6b371..d94ce1de2bf05 100644
> > --- a/drivers/staging/media/imx/imx-media-csi.c
> > +++ b/drivers/staging/media/imx/imx-media-csi.c
> > @@ -1325,6 +1325,40 @@ static int csi_set_fmt(struct v4l2_subdev *sd,
> > csi_try_fmt(priv, sensor, cfg, sdformat, crop, compose, &cc);
> >
> > fmt = __csi_get_fmt(priv, cfg, sdformat->pad, sdformat->which);
> > +
> > + /* Retain current field setting as default */
> > + if (sdformat->format.field == V4L2_FIELD_ANY)
> > + sdformat->format.field = fmt->field;
>
> sdformat->format.field should never be FIELD_ANY. If it is, then that's a
> subdev bug and I'm pretty sure FIELD_NONE was intended.
This is the subdev. sdformat is passed in from userspace, so we have to
deal with it being set to ANY. I'm trying hard right now not to return
ANY though. The values in sdformat->format are applied to fmt down
below.
> > +
> > + /* Retain current colorspace setting as default */
> > + if (sdformat->format.colorspace == V4L2_COLORSPACE_DEFAULT) {
> > + sdformat->format.colorspace = fmt->colorspace;
>
> No! Subdevs should never return COLORSPACE_DEFAULT. If they do, then fix
> them. If this happens a lot (I'm not sure how reliably subdevs fill this
> in) you could set it to COLORSPACE_RAW. Perhaps with a WARN_ON_ONCE.
Same here, if userspace calls VIDIOC_SUBDEV_S_FMT with DEFAULT
colorspace, I don't want to return that unchanged, but overwrite it with
the currently set value.
> > + if (sdformat->format.xfer_func == V4L2_XFER_FUNC_DEFAULT)
> > + sdformat->format.xfer_func = fmt->xfer_func;
> > + if (sdformat->format.ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT)
> > + sdformat->format.ycbcr_enc = fmt->ycbcr_enc;
> > + if (sdformat->format.quantization == V4L2_QUANTIZATION_DEFAULT)
> > + sdformat->format.quantization = fmt->quantization;
>
> Nack. This is meaningless.
It isn't. It may be wrong, but it is not without effect. If the
colorimetry info (in fmt) is currently set to something that is
non-standard, calling VIDIOC_SUBDEV_S_FMT with DEFAULT in xfer_func,
ycbcr_enc or quantization will cause those old values to be retained,
instead of overwriting them to DEFAULT.
> > + } else {
> > + if (sdformat->format.xfer_func == V4L2_XFER_FUNC_DEFAULT) {
> > + sdformat->format.xfer_func =
> > + V4L2_MAP_XFER_FUNC_DEFAULT(
> > + sdformat->format.colorspace);
> > + }
> > + if (sdformat->format.ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) {
> > + sdformat->format.ycbcr_enc =
> > + V4L2_MAP_YCBCR_ENC_DEFAULT(
> > + sdformat->format.colorspace);
> > + }
> > + if (sdformat->format.quantization == V4L2_QUANTIZATION_DEFAULT) {
> > + sdformat->format.quantization =
> > + V4L2_MAP_QUANTIZATION_DEFAULT(
> > + cc->cs != IPUV3_COLORSPACE_YUV,
> > + sdformat->format.colorspace,
> > + sdformat->format.ycbcr_enc);
> > + }
>
> This isn't wrong, but it is perfectly fine to keep the DEFAULT here and let
> the application call V4L2_MAP_.
>
> I get the feeling this patch is a workaround for subdev errors. Either that,
> or the commit log doesn't give me enough information to really understand the
> problem that's being addressed here.
It's the latter. I should have written VIDIOC_SUBDEV_S_FMT instead of
just set_fmt in the comment.
> Regards,
>
> Hans
>
> > + }
> > +
> > *fmt = sdformat->format;
Here sdformat is applied to the subdev pad.
regards
Philipp
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* Re: [PATCH v3 3/3] clk: vc5: Add support for IDT VersaClock 5P49V5935
From: Marek Vasut @ 2017-04-06 14:56 UTC (permalink / raw)
To: Alexey Firago, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
geert-Td1EMuHUCqxL1ZNQvxDV9g, linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1491470130-6655-4-git-send-email-alexey_firago-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
On 04/06/2017 11:15 AM, Alexey Firago wrote:
> Update IDT VersaClock 5 driver to support 5P49V5935. This chip has
> two clock inputs (internal XTAL or external CLKIN), four fractional
> dividers (FODs) and five clock outputs (four universal clock outputs
> and one reference clock output at OUT0_SELB_I2C).
>
> Current driver supports up to 2 FODs and up to 3 clock outputs. This
> patch sets max number of supported FODs to 4 and max number of supported
> clock outputs to 5.
>
> Signed-off-by: Alexey Firago <alexey_firago-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
Reviewed-by: Marek Vasut <marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
I really like how easily this driver could be extended :)
> ---
> drivers/clk/clk-versaclock5.c | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
> index 4e81fb1..34c4e5a 100644
> --- a/drivers/clk/clk-versaclock5.c
> +++ b/drivers/clk/clk-versaclock5.c
> @@ -114,10 +114,10 @@
> #define VC5_MUX_IN_CLKIN BIT(1)
>
> /* Maximum number of clk_out supported by this driver */
> -#define VC5_MAX_CLK_OUT_NUM 3
> +#define VC5_MAX_CLK_OUT_NUM 5
>
> /* Maximum number of FODs supported by this driver */
> -#define VC5_MAX_FOD_NUM 2
> +#define VC5_MAX_FOD_NUM 4
>
> /* flags to describe chip features */
> /* chip has built-in oscilator */
> @@ -127,6 +127,7 @@
> enum vc5_model {
> IDT_VC5_5P49V5923,
> IDT_VC5_5P49V5933,
> + IDT_VC5_5P49V5935,
> };
>
> /* Structure to describe features of a particular VC5 model */
> @@ -594,6 +595,7 @@ static int vc5_map_index_to_output(const enum vc5_model model,
> case IDT_VC5_5P49V5933:
> return (n == 0) ? 0 : 3;
> case IDT_VC5_5P49V5923:
> + case IDT_VC5_5P49V5935:
> default:
> return n;
> }
> @@ -790,9 +792,17 @@ static const struct vc5_chip_info idt_5p49v5933_info = {
> .flags = VC5_HAS_INTERNAL_XTAL,
> };
>
> +static const struct vc5_chip_info idt_5p49v5935_info = {
> + .model = IDT_VC5_5P49V5935,
> + .clk_fod_cnt = 4,
> + .clk_out_cnt = 5,
> + .flags = VC5_HAS_INTERNAL_XTAL,
> +};
> +
> static const struct i2c_device_id vc5_id[] = {
> { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
> { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
> + { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
> { }
> };
> MODULE_DEVICE_TABLE(i2c, vc5_id);
> @@ -800,6 +810,7 @@ MODULE_DEVICE_TABLE(i2c, vc5_id);
> static const struct of_device_id clk_vc5_of_match[] = {
> { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
> { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
> + { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
> { },
> };
> MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
>
--
Best regards,
Marek Vasut
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* [PATCH v2 0/4] Add ZTE VGA driver support
From: Shawn Guo @ 2017-04-06 15:01 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Sean Paul,
Daniel Vetter, Baoyou Xie, Xin Zhou, Jun Nie, Shawn Guo
From: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
The series adds the driver for ZTE VGA device, which becomes the third
VOU output device we support, besides the existing HDMI and TV Encoder.
Changes for v2:
- Add return check for encoder and connector init function calls.
- Improve comments in function zx_vga_irq_handler() to avoid confusion.
- Add lock for VGA_AUTO_DETECT_SEL register access to avoid race
condition between irq handler and .get_modes hook.
- Copy device tree maintainer and list for bindings doc.
Shawn Guo (4):
drm: zte: do not enable clock auto-gating by default
drm: zte: move CSC register definitions into a common header
dt-bindings: display: add support for ZTE VGA device
drm: zte: add VGA driver support
.../devicetree/bindings/display/zte,vou.txt | 21 +
drivers/gpu/drm/zte/Makefile | 1 +
drivers/gpu/drm/zte/zx_common_regs.h | 31 ++
drivers/gpu/drm/zte/zx_drm_drv.c | 1 +
drivers/gpu/drm/zte/zx_drm_drv.h | 1 +
drivers/gpu/drm/zte/zx_plane.c | 1 +
drivers/gpu/drm/zte/zx_plane_regs.h | 18 -
drivers/gpu/drm/zte/zx_vga.c | 530 +++++++++++++++++++++
drivers/gpu/drm/zte/zx_vga_regs.h | 36 ++
drivers/gpu/drm/zte/zx_vou.c | 36 +-
drivers/gpu/drm/zte/zx_vou_regs.h | 12 +-
11 files changed, 663 insertions(+), 25 deletions(-)
create mode 100644 drivers/gpu/drm/zte/zx_common_regs.h
create mode 100644 drivers/gpu/drm/zte/zx_vga.c
create mode 100644 drivers/gpu/drm/zte/zx_vga_regs.h
--
1.9.1
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* [PATCH v2 1/4] drm: zte: do not enable clock auto-gating by default
From: Shawn Guo @ 2017-04-06 15:01 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Sean Paul,
Daniel Vetter, Baoyou Xie, Xin Zhou, Jun Nie, Shawn Guo
In-Reply-To: <1491490870-6330-1-git-send-email-shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
From: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Some VOU modules do not work well with clock auto-gating. For example,
VGA I2C bus will fail to read EDID data from monitor. Let's not enable
this feature by default, and leave it to the possible future low-power
optimization.
Signed-off-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Reviewed-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Acked-by: Daniel Vetter <daniel.vetter-/w4YWyX8dFk@public.gmane.org>
---
drivers/gpu/drm/zte/zx_vou.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/zte/zx_vou.c b/drivers/gpu/drm/zte/zx_vou.c
index cf92d675feaa..2a2d90bd9425 100644
--- a/drivers/gpu/drm/zte/zx_vou.c
+++ b/drivers/gpu/drm/zte/zx_vou.c
@@ -720,9 +720,6 @@ static void vou_hw_init(struct zx_vou_hw *vou)
/* Release reset for all VOU modules */
zx_writel(vou->vouctl + VOU_SOFT_RST, ~0);
- /* Enable clock auto-gating for all VOU modules */
- zx_writel(vou->vouctl + VOU_CLK_REQEN, ~0);
-
/* Enable all VOU module clocks */
zx_writel(vou->vouctl + VOU_CLK_EN, ~0);
--
1.9.1
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* [PATCH v2 2/4] drm: zte: move CSC register definitions into a common header
From: Shawn Guo @ 2017-04-06 15:01 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Sean Paul,
Daniel Vetter, Baoyou Xie, Xin Zhou, Jun Nie, Shawn Guo
In-Reply-To: <1491490870-6330-1-git-send-email-shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
From: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
The CSC (Color Space Conversion) block in VOU is used by not only
Graphic Layer (plane) but also channel (CRTC) module. Let's move
its register definitions into a common header, so that CRTC driver can
include it when needed.
Signed-off-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Reviewed-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Acked-by: Daniel Vetter <daniel.vetter-/w4YWyX8dFk@public.gmane.org>
---
drivers/gpu/drm/zte/zx_common_regs.h | 31 +++++++++++++++++++++++++++++++
drivers/gpu/drm/zte/zx_plane.c | 1 +
drivers/gpu/drm/zte/zx_plane_regs.h | 18 ------------------
3 files changed, 32 insertions(+), 18 deletions(-)
create mode 100644 drivers/gpu/drm/zte/zx_common_regs.h
diff --git a/drivers/gpu/drm/zte/zx_common_regs.h b/drivers/gpu/drm/zte/zx_common_regs.h
new file mode 100644
index 000000000000..2afd80664c51
--- /dev/null
+++ b/drivers/gpu/drm/zte/zx_common_regs.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * Copyright 2017 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ZX_COMMON_REGS_H__
+#define __ZX_COMMON_REGS_H__
+
+/* CSC registers */
+#define CSC_CTRL0 0x30
+#define CSC_COV_MODE_SHIFT 16
+#define CSC_COV_MODE_MASK (0xffff << CSC_COV_MODE_SHIFT)
+#define CSC_BT601_IMAGE_RGB2YCBCR 0
+#define CSC_BT601_IMAGE_YCBCR2RGB 1
+#define CSC_BT601_VIDEO_RGB2YCBCR 2
+#define CSC_BT601_VIDEO_YCBCR2RGB 3
+#define CSC_BT709_IMAGE_RGB2YCBCR 4
+#define CSC_BT709_IMAGE_YCBCR2RGB 5
+#define CSC_BT709_VIDEO_RGB2YCBCR 6
+#define CSC_BT709_VIDEO_YCBCR2RGB 7
+#define CSC_BT2020_IMAGE_RGB2YCBCR 8
+#define CSC_BT2020_IMAGE_YCBCR2RGB 9
+#define CSC_BT2020_VIDEO_RGB2YCBCR 10
+#define CSC_BT2020_VIDEO_YCBCR2RGB 11
+#define CSC_WORK_ENABLE BIT(0)
+
+#endif /* __ZX_COMMON_REGS_H__ */
diff --git a/drivers/gpu/drm/zte/zx_plane.c b/drivers/gpu/drm/zte/zx_plane.c
index d646ac931663..4a6252720c10 100644
--- a/drivers/gpu/drm/zte/zx_plane.c
+++ b/drivers/gpu/drm/zte/zx_plane.c
@@ -16,6 +16,7 @@
#include <drm/drm_plane_helper.h>
#include <drm/drmP.h>
+#include "zx_common_regs.h"
#include "zx_drm_drv.h"
#include "zx_plane.h"
#include "zx_plane_regs.h"
diff --git a/drivers/gpu/drm/zte/zx_plane_regs.h b/drivers/gpu/drm/zte/zx_plane_regs.h
index 65f271aeabed..9c655f59f9f7 100644
--- a/drivers/gpu/drm/zte/zx_plane_regs.h
+++ b/drivers/gpu/drm/zte/zx_plane_regs.h
@@ -77,24 +77,6 @@
#define LUMA_STRIDE(x) (((x) << LUMA_STRIDE_SHIFT) & LUMA_STRIDE_MASK)
#define CHROMA_STRIDE(x) (((x) << CHROMA_STRIDE_SHIFT) & CHROMA_STRIDE_MASK)
-/* CSC registers */
-#define CSC_CTRL0 0x30
-#define CSC_COV_MODE_SHIFT 16
-#define CSC_COV_MODE_MASK (0xffff << CSC_COV_MODE_SHIFT)
-#define CSC_BT601_IMAGE_RGB2YCBCR 0
-#define CSC_BT601_IMAGE_YCBCR2RGB 1
-#define CSC_BT601_VIDEO_RGB2YCBCR 2
-#define CSC_BT601_VIDEO_YCBCR2RGB 3
-#define CSC_BT709_IMAGE_RGB2YCBCR 4
-#define CSC_BT709_IMAGE_YCBCR2RGB 5
-#define CSC_BT709_VIDEO_RGB2YCBCR 6
-#define CSC_BT709_VIDEO_YCBCR2RGB 7
-#define CSC_BT2020_IMAGE_RGB2YCBCR 8
-#define CSC_BT2020_IMAGE_YCBCR2RGB 9
-#define CSC_BT2020_VIDEO_RGB2YCBCR 10
-#define CSC_BT2020_VIDEO_YCBCR2RGB 11
-#define CSC_WORK_ENABLE BIT(0)
-
/* RSZ registers */
#define RSZ_SRC_CFG 0x00
#define RSZ_DEST_CFG 0x04
--
1.9.1
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* [PATCH v2 3/4] dt-bindings: display: add support for ZTE VGA device
From: Shawn Guo @ 2017-04-06 15:01 UTC (permalink / raw)
To: dri-devel
Cc: devicetree, Xin Zhou, Daniel Vetter, Baoyou Xie, Rob Herring,
Jun Nie
In-Reply-To: <1491490870-6330-1-git-send-email-shawnguo@kernel.org>
From: Shawn Guo <shawn.guo@linaro.org>
It adds bindings doc for ZTE VOU VGA output device.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
.../devicetree/bindings/display/zte,vou.txt | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/zte,vou.txt b/Documentation/devicetree/bindings/display/zte,vou.txt
index 9c356284232b..38476475fd60 100644
--- a/Documentation/devicetree/bindings/display/zte,vou.txt
+++ b/Documentation/devicetree/bindings/display/zte,vou.txt
@@ -58,6 +58,18 @@ Required properties:
integer cells. The first cell is the offset of SYSCTRL register used
to control TV Encoder DAC power, and the second cell is the bit mask.
+* VGA output device
+
+Required properties:
+ - compatible: should be "zte,zx296718-vga"
+ - reg: Physical base address and length of the VGA device IO region
+ - interrupts : VGA interrupt number to CPU
+ - clocks: Phandle with clock-specifier pointing to VGA I2C clock.
+ - clock-names: Must be "i2c_wclk".
+ - zte,vga-power-control: the phandle to SYSCTRL block followed by two
+ integer cells. The first cell is the offset of SYSCTRL register used
+ to control VGA DAC power, and the second cell is the bit mask.
+
Example:
vou: vou@1440000 {
@@ -81,6 +93,15 @@ vou: vou@1440000 {
"main_wclk", "aux_wclk";
};
+ vga: vga@8000 {
+ compatible = "zte,zx296718-vga";
+ reg = <0x8000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topcrm VGA_I2C_WCLK>;
+ clock-names = "i2c_wclk";
+ zte,vga-power-control = <&sysctrl 0x170 0xe0>;
+ };
+
hdmi: hdmi@c000 {
compatible = "zte,zx296718-hdmi";
reg = <0xc000 0x4000>;
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
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* [PATCH v2 4/4] drm: zte: add VGA driver support
From: Shawn Guo @ 2017-04-06 15:01 UTC (permalink / raw)
To: dri-devel
Cc: devicetree, Xin Zhou, Daniel Vetter, Baoyou Xie, Rob Herring,
Jun Nie
In-Reply-To: <1491490870-6330-1-git-send-email-shawnguo@kernel.org>
From: Shawn Guo <shawn.guo@linaro.org>
It adds VGA driver support, which needs to configure corresponding VOU
interface in RGB_888 format, and thus the following changes are needed
on zx_vou.
- Rename the CSC block of Graphic Layer a bit to make it more specific,
and add CSC of Channel to support RGB output.
- Bypass Dither block for RGB output.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/zte/Makefile | 1 +
drivers/gpu/drm/zte/zx_drm_drv.c | 1 +
drivers/gpu/drm/zte/zx_drm_drv.h | 1 +
drivers/gpu/drm/zte/zx_vga.c | 530 ++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/zte/zx_vga_regs.h | 36 +++
drivers/gpu/drm/zte/zx_vou.c | 33 ++-
drivers/gpu/drm/zte/zx_vou_regs.h | 12 +-
7 files changed, 610 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/zte/zx_vga.c
create mode 100644 drivers/gpu/drm/zte/zx_vga_regs.h
diff --git a/drivers/gpu/drm/zte/Makefile b/drivers/gpu/drm/zte/Makefile
index 01352b56c418..9df7766a7f9d 100644
--- a/drivers/gpu/drm/zte/Makefile
+++ b/drivers/gpu/drm/zte/Makefile
@@ -3,6 +3,7 @@ zxdrm-y := \
zx_hdmi.o \
zx_plane.o \
zx_tvenc.o \
+ zx_vga.o \
zx_vou.o
obj-$(CONFIG_DRM_ZTE) += zxdrm.o
diff --git a/drivers/gpu/drm/zte/zx_drm_drv.c b/drivers/gpu/drm/zte/zx_drm_drv.c
index 5c6944a1e72c..8a6892eeb44f 100644
--- a/drivers/gpu/drm/zte/zx_drm_drv.c
+++ b/drivers/gpu/drm/zte/zx_drm_drv.c
@@ -248,6 +248,7 @@ static int zx_drm_remove(struct platform_device *pdev)
&zx_crtc_driver,
&zx_hdmi_driver,
&zx_tvenc_driver,
+ &zx_vga_driver,
&zx_drm_platform_driver,
};
diff --git a/drivers/gpu/drm/zte/zx_drm_drv.h b/drivers/gpu/drm/zte/zx_drm_drv.h
index 5ca035b079c7..2a8cdc5f8be4 100644
--- a/drivers/gpu/drm/zte/zx_drm_drv.h
+++ b/drivers/gpu/drm/zte/zx_drm_drv.h
@@ -14,6 +14,7 @@
extern struct platform_driver zx_crtc_driver;
extern struct platform_driver zx_hdmi_driver;
extern struct platform_driver zx_tvenc_driver;
+extern struct platform_driver zx_vga_driver;
static inline u32 zx_readl(void __iomem *reg)
{
diff --git a/drivers/gpu/drm/zte/zx_vga.c b/drivers/gpu/drm/zte/zx_vga.c
new file mode 100644
index 000000000000..0d850d9ea700
--- /dev/null
+++ b/drivers/gpu/drm/zte/zx_vga.c
@@ -0,0 +1,530 @@
+/*
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * Copyright 2017 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drmP.h>
+
+#include "zx_drm_drv.h"
+#include "zx_vga_regs.h"
+#include "zx_vou.h"
+
+struct zx_vga_pwrctrl {
+ struct regmap *regmap;
+ u32 reg;
+ u32 mask;
+};
+
+struct zx_vga_i2c {
+ struct i2c_adapter adap;
+ struct mutex lock;
+};
+
+struct zx_vga {
+ struct drm_connector connector;
+ struct drm_encoder encoder;
+ struct zx_vga_i2c *ddc;
+ struct device *dev;
+ void __iomem *mmio;
+ struct clk *i2c_wclk;
+ struct zx_vga_pwrctrl pwrctrl;
+ spinlock_t lock;
+ struct completion complete;
+ bool connected;
+};
+
+#define to_zx_vga(x) container_of(x, struct zx_vga, x)
+
+static void zx_vga_encoder_enable(struct drm_encoder *encoder)
+{
+ struct zx_vga *vga = to_zx_vga(encoder);
+ struct zx_vga_pwrctrl *pwrctrl = &vga->pwrctrl;
+
+ /* Set bit to power up VGA DACs */
+ regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask,
+ pwrctrl->mask);
+
+ vou_inf_enable(VOU_VGA, encoder->crtc);
+}
+
+static void zx_vga_encoder_disable(struct drm_encoder *encoder)
+{
+ struct zx_vga *vga = to_zx_vga(encoder);
+ struct zx_vga_pwrctrl *pwrctrl = &vga->pwrctrl;
+
+ vou_inf_disable(VOU_VGA, encoder->crtc);
+
+ /* Clear bit to power down VGA DACs */
+ regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, 0);
+}
+
+static const struct drm_encoder_helper_funcs zx_vga_encoder_helper_funcs = {
+ .enable = zx_vga_encoder_enable,
+ .disable = zx_vga_encoder_disable,
+};
+
+static const struct drm_encoder_funcs zx_vga_encoder_funcs = {
+ .destroy = drm_encoder_cleanup,
+};
+
+static int zx_vga_connector_get_modes(struct drm_connector *connector)
+{
+ struct zx_vga *vga = to_zx_vga(connector);
+ unsigned long flags;
+ struct edid *edid;
+ int ret;
+
+ /*
+ * Clear both detection bits to switch I2C bus from device
+ * detecting to EDID reading.
+ */
+ spin_lock_irqsave(&vga->lock, flags);
+ zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, 0);
+ spin_unlock_irqrestore(&vga->lock, flags);
+
+ edid = drm_get_edid(connector, &vga->ddc->adap);
+ if (!edid)
+ return 0;
+
+ /*
+ * As edid reading succeeds, device must be connected, so we set
+ * up detection bit for unplug interrupt here.
+ */
+ spin_lock_irqsave(&vga->lock, flags);
+ zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, VGA_DETECT_SEL_HAS_DEVICE);
+ spin_unlock_irqrestore(&vga->lock, flags);
+
+ drm_mode_connector_update_edid_property(connector, edid);
+ ret = drm_add_edid_modes(connector, edid);
+ kfree(edid);
+
+ return ret;
+}
+
+static enum drm_mode_status
+zx_vga_connector_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ return MODE_OK;
+}
+
+static struct drm_connector_helper_funcs zx_vga_connector_helper_funcs = {
+ .get_modes = zx_vga_connector_get_modes,
+ .mode_valid = zx_vga_connector_mode_valid,
+};
+
+static enum drm_connector_status
+zx_vga_connector_detect(struct drm_connector *connector, bool force)
+{
+ struct zx_vga *vga = to_zx_vga(connector);
+
+ return vga->connected ? connector_status_connected :
+ connector_status_disconnected;
+}
+
+static const struct drm_connector_funcs zx_vga_connector_funcs = {
+ .dpms = drm_atomic_helper_connector_dpms,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .detect = zx_vga_connector_detect,
+ .destroy = drm_connector_cleanup,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int zx_vga_register(struct drm_device *drm, struct zx_vga *vga)
+{
+ struct drm_encoder *encoder = &vga->encoder;
+ struct drm_connector *connector = &vga->connector;
+ struct device *dev = vga->dev;
+ int ret;
+
+ encoder->possible_crtcs = VOU_CRTC_MASK;
+
+ ret = drm_encoder_init(drm, encoder, &zx_vga_encoder_funcs,
+ DRM_MODE_ENCODER_DAC, NULL);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to init encoder: %d\n", ret);
+ return ret;
+ };
+
+ drm_encoder_helper_add(encoder, &zx_vga_encoder_helper_funcs);
+
+ vga->connector.polled = DRM_CONNECTOR_POLL_HPD;
+
+ ret = drm_connector_init(drm, connector, &zx_vga_connector_funcs,
+ DRM_MODE_CONNECTOR_VGA);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to init connector: %d\n", ret);
+ goto clean_encoder;
+ };
+
+ drm_connector_helper_add(connector, &zx_vga_connector_helper_funcs);
+
+ ret = drm_mode_connector_attach_encoder(connector, encoder);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to attach encoder: %d\n", ret);
+ goto clean_connector;
+ };
+
+ return 0;
+
+clean_connector:
+ drm_connector_cleanup(connector);
+clean_encoder:
+ drm_encoder_cleanup(encoder);
+ return ret;
+}
+
+static int zx_vga_pwrctrl_init(struct zx_vga *vga)
+{
+ struct zx_vga_pwrctrl *pwrctrl = &vga->pwrctrl;
+ struct device *dev = vga->dev;
+ struct of_phandle_args out_args;
+ struct regmap *regmap;
+ int ret;
+
+ ret = of_parse_phandle_with_fixed_args(dev->of_node,
+ "zte,vga-power-control", 2, 0, &out_args);
+ if (ret)
+ return ret;
+
+ regmap = syscon_node_to_regmap(out_args.np);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+ goto out;
+ }
+
+ pwrctrl->regmap = regmap;
+ pwrctrl->reg = out_args.args[0];
+ pwrctrl->mask = out_args.args[1];
+
+out:
+ of_node_put(out_args.np);
+ return ret;
+}
+
+static int zx_vga_i2c_read(struct zx_vga *vga, struct i2c_msg *msg)
+{
+ int len = msg->len;
+ u8 *buf = msg->buf;
+ u32 offset = 0;
+ int i;
+
+ reinit_completion(&vga->complete);
+
+ /* Select combo write */
+ zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_COMBO, VGA_CMD_COMBO);
+ zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_RW, 0);
+
+ while (len > 0) {
+ u32 cnt;
+
+ /* Clear RX FIFO */
+ zx_writel_mask(vga->mmio + VGA_RXF_CTRL, VGA_RX_FIFO_CLEAR,
+ VGA_RX_FIFO_CLEAR);
+
+ /* Data offset to read from */
+ zx_writel(vga->mmio + VGA_SUB_ADDR, offset);
+
+ /* Kick off the transfer */
+ zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_TRANS,
+ VGA_CMD_TRANS);
+
+ if (!wait_for_completion_timeout(&vga->complete,
+ msecs_to_jiffies(1000))) {
+ DRM_DEV_ERROR(vga->dev, "transfer timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ cnt = zx_readl(vga->mmio + VGA_RXF_STATUS);
+ cnt = (cnt & VGA_RXF_COUNT_MASK) >> VGA_RXF_COUNT_SHIFT;
+ /* FIFO status may report more data than we need to read */
+ cnt = min_t(u32, len, cnt);
+
+ for (i = 0; i < cnt; i++)
+ *buf++ = zx_readl(vga->mmio + VGA_DATA);
+
+ len -= cnt;
+ offset += cnt;
+ }
+
+ return 0;
+}
+
+static int zx_vga_i2c_write(struct zx_vga *vga, struct i2c_msg *msg)
+{
+ /*
+ * The DDC I2C adapter is only for reading EDID data, so we assume
+ * that the write to this adapter must be the EDID data offset.
+ */
+ if ((msg->len != 1) || ((msg->addr != DDC_ADDR)))
+ return -EINVAL;
+
+ /* Hardware will take care of the slave address shifting */
+ zx_writel(vga->mmio + VGA_DEVICE_ADDR, msg->addr);
+
+ return 0;
+}
+
+static int zx_vga_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
+ int num)
+{
+ struct zx_vga *vga = i2c_get_adapdata(adap);
+ struct zx_vga_i2c *ddc = vga->ddc;
+ int ret = 0;
+ int i;
+
+ mutex_lock(&ddc->lock);
+
+ for (i = 0; i < num; i++) {
+ if (msgs[i].flags & I2C_M_RD)
+ ret = zx_vga_i2c_read(vga, &msgs[i]);
+ else
+ ret = zx_vga_i2c_write(vga, &msgs[i]);
+
+ if (ret < 0)
+ break;
+ }
+
+ if (!ret)
+ ret = num;
+
+ mutex_unlock(&ddc->lock);
+
+ return ret;
+}
+
+static u32 zx_vga_i2c_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm zx_vga_algorithm = {
+ .master_xfer = zx_vga_i2c_xfer,
+ .functionality = zx_vga_i2c_func,
+};
+
+static int zx_vga_ddc_register(struct zx_vga *vga)
+{
+ struct device *dev = vga->dev;
+ struct i2c_adapter *adap;
+ struct zx_vga_i2c *ddc;
+ int ret;
+
+ ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);
+ if (!ddc)
+ return -ENOMEM;
+
+ vga->ddc = ddc;
+ mutex_init(&ddc->lock);
+
+ adap = &ddc->adap;
+ adap->owner = THIS_MODULE;
+ adap->class = I2C_CLASS_DDC;
+ adap->dev.parent = dev;
+ adap->algo = &zx_vga_algorithm;
+ snprintf(adap->name, sizeof(adap->name), "zx vga i2c");
+
+ ret = i2c_add_adapter(adap);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to add I2C adapter: %d\n", ret);
+ return ret;
+ }
+
+ i2c_set_adapdata(adap, vga);
+
+ return 0;
+}
+
+static irqreturn_t zx_vga_irq_thread(int irq, void *dev_id)
+{
+ struct zx_vga *vga = dev_id;
+
+ drm_helper_hpd_irq_event(vga->connector.dev);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t zx_vga_irq_handler(int irq, void *dev_id)
+{
+ struct zx_vga *vga = dev_id;
+ u32 status;
+
+ status = zx_readl(vga->mmio + VGA_I2C_STATUS);
+
+ /* Clear interrupt status */
+ zx_writel_mask(vga->mmio + VGA_I2C_STATUS, VGA_CLEAR_IRQ,
+ VGA_CLEAR_IRQ);
+
+ if (status & VGA_DEVICE_CONNECTED) {
+ /*
+ * Since VGA_DETECT_SEL bits need to be reset for switching DDC
+ * bus from device detection to EDID read, rather than setting
+ * up HAS_DEVICE bit here, we need to do that in .get_modes
+ * hook for unplug detecting after EDID read succeeds.
+ */
+ vga->connected = true;
+ return IRQ_WAKE_THREAD;
+ }
+
+ if (status & VGA_DEVICE_DISCONNECTED) {
+ spin_lock(&vga->lock);
+ zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL,
+ VGA_DETECT_SEL_NO_DEVICE);
+ spin_unlock(&vga->lock);
+ vga->connected = false;
+ return IRQ_WAKE_THREAD;
+ }
+
+ if (status & VGA_TRANS_DONE) {
+ complete(&vga->complete);
+ return IRQ_HANDLED;
+ }
+
+ return IRQ_NONE;
+}
+
+static void zx_vga_hw_init(struct zx_vga *vga)
+{
+ unsigned long ref = clk_get_rate(vga->i2c_wclk);
+ int div;
+
+ /*
+ * Set up I2C fast speed divider per formula below to get 400kHz.
+ * scl = ref / ((div + 1) * 4)
+ */
+ div = DIV_ROUND_UP(ref / 1000, 400 * 4) - 1;
+ zx_writel(vga->mmio + VGA_CLK_DIV_FS, div);
+
+ /* Set up device detection */
+ zx_writel(vga->mmio + VGA_AUTO_DETECT_PARA, 0x80);
+ zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, VGA_DETECT_SEL_NO_DEVICE);
+
+ /*
+ * We need to poke monitor via DDC bus to get connection irq
+ * start working.
+ */
+ zx_writel(vga->mmio + VGA_DEVICE_ADDR, DDC_ADDR);
+ zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_TRANS, VGA_CMD_TRANS);
+}
+
+static int zx_vga_bind(struct device *dev, struct device *master, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct drm_device *drm = data;
+ struct resource *res;
+ struct zx_vga *vga;
+ int irq;
+ int ret;
+
+ vga = devm_kzalloc(dev, sizeof(*vga), GFP_KERNEL);
+ if (!vga)
+ return -ENOMEM;
+
+ vga->dev = dev;
+ dev_set_drvdata(dev, vga);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ vga->mmio = devm_ioremap_resource(dev, res);
+ if (IS_ERR(vga->mmio))
+ return PTR_ERR(vga->mmio);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ vga->i2c_wclk = devm_clk_get(dev, "i2c_wclk");
+ if (IS_ERR(vga->i2c_wclk)) {
+ ret = PTR_ERR(vga->i2c_wclk);
+ DRM_DEV_ERROR(dev, "failed to get i2c_wclk: %d\n", ret);
+ return ret;
+ }
+
+ ret = zx_vga_pwrctrl_init(vga);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to init power control: %d\n", ret);
+ return ret;
+ }
+
+ ret = zx_vga_ddc_register(vga);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to register ddc: %d\n", ret);
+ return ret;
+ }
+
+ ret = zx_vga_register(drm, vga);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to register vga: %d\n", ret);
+ return ret;
+ }
+
+ init_completion(&vga->complete);
+ spin_lock_init(&vga->lock);
+
+ ret = devm_request_threaded_irq(dev, irq, zx_vga_irq_handler,
+ zx_vga_irq_thread, IRQF_SHARED,
+ dev_name(dev), vga);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to request threaded irq: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(vga->i2c_wclk);
+ if (ret)
+ return ret;
+
+ zx_vga_hw_init(vga);
+
+ return 0;
+}
+
+static void zx_vga_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct zx_vga *vga = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(vga->i2c_wclk);
+}
+
+static const struct component_ops zx_vga_component_ops = {
+ .bind = zx_vga_bind,
+ .unbind = zx_vga_unbind,
+};
+
+static int zx_vga_probe(struct platform_device *pdev)
+{
+ return component_add(&pdev->dev, &zx_vga_component_ops);
+}
+
+static int zx_vga_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &zx_vga_component_ops);
+ return 0;
+}
+
+static const struct of_device_id zx_vga_of_match[] = {
+ { .compatible = "zte,zx296718-vga", },
+ { /* end */ },
+};
+MODULE_DEVICE_TABLE(of, zx_vga_of_match);
+
+struct platform_driver zx_vga_driver = {
+ .probe = zx_vga_probe,
+ .remove = zx_vga_remove,
+ .driver = {
+ .name = "zx-vga",
+ .of_match_table = zx_vga_of_match,
+ },
+};
diff --git a/drivers/gpu/drm/zte/zx_vga_regs.h b/drivers/gpu/drm/zte/zx_vga_regs.h
new file mode 100644
index 000000000000..feaa345fe6a6
--- /dev/null
+++ b/drivers/gpu/drm/zte/zx_vga_regs.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * Copyright 2017 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ZX_VGA_REGS_H__
+#define __ZX_VGA_REGS_H__
+
+#define VGA_CMD_CFG 0x04
+#define VGA_CMD_TRANS BIT(6)
+#define VGA_CMD_COMBO BIT(5)
+#define VGA_CMD_RW BIT(4)
+#define VGA_SUB_ADDR 0x0c
+#define VGA_DEVICE_ADDR 0x10
+#define VGA_CLK_DIV_FS 0x14
+#define VGA_RXF_CTRL 0x20
+#define VGA_RX_FIFO_CLEAR BIT(7)
+#define VGA_DATA 0x24
+#define VGA_I2C_STATUS 0x28
+#define VGA_DEVICE_DISCONNECTED BIT(7)
+#define VGA_DEVICE_CONNECTED BIT(6)
+#define VGA_CLEAR_IRQ BIT(4)
+#define VGA_TRANS_DONE BIT(0)
+#define VGA_RXF_STATUS 0x30
+#define VGA_RXF_COUNT_SHIFT 2
+#define VGA_RXF_COUNT_MASK GENMASK(7, 2)
+#define VGA_AUTO_DETECT_PARA 0x34
+#define VGA_AUTO_DETECT_SEL 0x38
+#define VGA_DETECT_SEL_HAS_DEVICE BIT(1)
+#define VGA_DETECT_SEL_NO_DEVICE BIT(0)
+
+#endif /* __ZX_VGA_REGS_H__ */
diff --git a/drivers/gpu/drm/zte/zx_vou.c b/drivers/gpu/drm/zte/zx_vou.c
index 2a2d90bd9425..cc5bdfc53e8e 100644
--- a/drivers/gpu/drm/zte/zx_vou.c
+++ b/drivers/gpu/drm/zte/zx_vou.c
@@ -23,6 +23,7 @@
#include <drm/drm_plane_helper.h>
#include <drm/drmP.h>
+#include "zx_common_regs.h"
#include "zx_drm_drv.h"
#include "zx_plane.h"
#include "zx_vou.h"
@@ -122,6 +123,8 @@ struct zx_crtc {
struct drm_plane *primary;
struct zx_vou_hw *vou;
void __iomem *chnreg;
+ void __iomem *chncsc;
+ void __iomem *dither;
const struct zx_crtc_regs *regs;
const struct zx_crtc_bits *bits;
enum vou_chn_type chn_type;
@@ -204,6 +207,11 @@ struct vou_inf {
.clocks_en_bits = BIT(15),
.clocks_sel_bits = BIT(11) | BIT(0),
},
+ [VOU_VGA] = {
+ .data_sel = VOU_RGB_888,
+ .clocks_en_bits = BIT(1),
+ .clocks_sel_bits = BIT(10),
+ },
};
static inline struct zx_vou_hw *crtc_to_vou(struct drm_crtc *crtc)
@@ -227,9 +235,26 @@ void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc)
struct zx_crtc *zcrtc = to_zx_crtc(crtc);
struct zx_vou_hw *vou = zcrtc->vou;
struct vou_inf *inf = &vou_infs[id];
+ void __iomem *dither = zcrtc->dither;
+ void __iomem *csc = zcrtc->chncsc;
bool is_main = zcrtc->chn_type == VOU_CHN_MAIN;
u32 data_sel_shift = id << 1;
+ if (inf->data_sel != VOU_YUV444) {
+ /* Enable channel CSC for RGB output */
+ zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK,
+ CSC_BT709_IMAGE_YCBCR2RGB << CSC_COV_MODE_SHIFT);
+ zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE,
+ CSC_WORK_ENABLE);
+
+ /* Bypass Dither block for RGB output */
+ zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS,
+ DITHER_BYSPASS);
+ } else {
+ zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE, 0);
+ zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS, 0);
+ }
+
/* Select data format */
zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift,
inf->data_sel << data_sel_shift);
@@ -502,20 +527,24 @@ static int zx_crtc_init(struct drm_device *drm, struct zx_vou_hw *vou,
if (chn_type == VOU_CHN_MAIN) {
zplane->layer = vou->osd + MAIN_GL_OFFSET;
- zplane->csc = vou->osd + MAIN_CSC_OFFSET;
+ zplane->csc = vou->osd + MAIN_GL_CSC_OFFSET;
zplane->hbsc = vou->osd + MAIN_HBSC_OFFSET;
zplane->rsz = vou->otfppu + MAIN_RSZ_OFFSET;
zplane->bits = &zx_gl_bits[0];
zcrtc->chnreg = vou->osd + OSD_MAIN_CHN;
+ zcrtc->chncsc = vou->osd + MAIN_CHN_CSC_OFFSET;
+ zcrtc->dither = vou->osd + MAIN_DITHER_OFFSET;
zcrtc->regs = &main_crtc_regs;
zcrtc->bits = &main_crtc_bits;
} else {
zplane->layer = vou->osd + AUX_GL_OFFSET;
- zplane->csc = vou->osd + AUX_CSC_OFFSET;
+ zplane->csc = vou->osd + AUX_GL_CSC_OFFSET;
zplane->hbsc = vou->osd + AUX_HBSC_OFFSET;
zplane->rsz = vou->otfppu + AUX_RSZ_OFFSET;
zplane->bits = &zx_gl_bits[1];
zcrtc->chnreg = vou->osd + OSD_AUX_CHN;
+ zcrtc->chncsc = vou->osd + AUX_CHN_CSC_OFFSET;
+ zcrtc->dither = vou->osd + AUX_DITHER_OFFSET;
zcrtc->regs = &aux_crtc_regs;
zcrtc->bits = &aux_crtc_bits;
}
diff --git a/drivers/gpu/drm/zte/zx_vou_regs.h b/drivers/gpu/drm/zte/zx_vou_regs.h
index c066ef123434..5a218351b497 100644
--- a/drivers/gpu/drm/zte/zx_vou_regs.h
+++ b/drivers/gpu/drm/zte/zx_vou_regs.h
@@ -13,13 +13,17 @@
/* Sub-module offset */
#define MAIN_GL_OFFSET 0x130
-#define MAIN_CSC_OFFSET 0x580
+#define MAIN_GL_CSC_OFFSET 0x580
+#define MAIN_CHN_CSC_OFFSET 0x6c0
#define MAIN_HBSC_OFFSET 0x820
+#define MAIN_DITHER_OFFSET 0x960
#define MAIN_RSZ_OFFSET 0x600 /* OTFPPU sub-module */
#define AUX_GL_OFFSET 0x200
-#define AUX_CSC_OFFSET 0x5d0
+#define AUX_GL_CSC_OFFSET 0x5d0
+#define AUX_CHN_CSC_OFFSET 0x710
#define AUX_HBSC_OFFSET 0x860
+#define AUX_DITHER_OFFSET 0x970
#define AUX_RSZ_OFFSET 0x800
#define OSD_VL0_OFFSET 0x040
@@ -78,6 +82,10 @@
#define CHN_INTERLACE_BUF_CTRL 0x24
#define CHN_INTERLACE_EN BIT(2)
+/* Dither registers */
+#define OSD_DITHER_CTRL0 0x00
+#define DITHER_BYSPASS BIT(31)
+
/* TIMING_CTRL registers */
#define TIMING_TC_ENABLE 0x04
#define AUX_TC_EN BIT(1)
--
1.9.1
_______________________________________________
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^ permalink raw reply related
* Re: [PATCH] [media] imx: csi: retain current field order and colorimetry setting as default
From: Philipp Zabel @ 2017-04-06 15:01 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Steve Longerbeam, robh+dt, mark.rutland, shawnguo, kernel,
fabio.estevam, mchehab, hverkuil, nick, markus.heiser,
laurent.pinchart+renesas, bparrot, geert, arnd, sudipm.mukherjee,
minghsiu.tsai, tiffany.lin, jean-christophe.trotin, horms+renesas,
niklas.soderlund+renesas, robert.jarzmik, songjun.wu,
andrew-ct.chen, gregkh, shuah, sakari.ailus, pavel, devicetree,
linux-kernel, linux-arm-kernel, linux-media
In-Reply-To: <20170406140533.GF17774@n2100.armlinux.org.uk>
On Thu, 2017-04-06 at 15:05 +0100, Russell King - ARM Linux wrote:
> On Thu, Apr 06, 2017 at 03:55:29PM +0200, Philipp Zabel wrote:
> > +
> > + /* Retain current field setting as default */
> > + if (sdformat->format.field == V4L2_FIELD_ANY)
> > + sdformat->format.field = fmt->field;
> > +
> > + /* Retain current colorspace setting as default */
> > + if (sdformat->format.colorspace == V4L2_COLORSPACE_DEFAULT) {
> > + sdformat->format.colorspace = fmt->colorspace;
> > + if (sdformat->format.xfer_func == V4L2_XFER_FUNC_DEFAULT)
> > + sdformat->format.xfer_func = fmt->xfer_func;
> > + if (sdformat->format.ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT)
> > + sdformat->format.ycbcr_enc = fmt->ycbcr_enc;
> > + if (sdformat->format.quantization == V4L2_QUANTIZATION_DEFAULT)
> > + sdformat->format.quantization = fmt->quantization;
> > + } else {
> > + if (sdformat->format.xfer_func == V4L2_XFER_FUNC_DEFAULT) {
> > + sdformat->format.xfer_func =
> > + V4L2_MAP_XFER_FUNC_DEFAULT(
> > + sdformat->format.colorspace);
> > + }
> > + if (sdformat->format.ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) {
> > + sdformat->format.ycbcr_enc =
> > + V4L2_MAP_YCBCR_ENC_DEFAULT(
> > + sdformat->format.colorspace);
> > + }
> > + if (sdformat->format.quantization == V4L2_QUANTIZATION_DEFAULT) {
> > + sdformat->format.quantization =
> > + V4L2_MAP_QUANTIZATION_DEFAULT(
> > + cc->cs != IPUV3_COLORSPACE_YUV,
> > + sdformat->format.colorspace,
> > + sdformat->format.ycbcr_enc);
> > + }
> > + }
>
> Would it make sense for this to be a helper function?
Quite possible, the next subdev that has to set frame_interval on both
pads manually because its upstream source pad doesn't suport
frame_interval might want to do the same.
regards
Philipp
^ permalink raw reply
* Re: [PATCH] [media] imx: csi: retain current field order and colorimetry setting as default
From: Russell King - ARM Linux @ 2017-04-06 15:10 UTC (permalink / raw)
To: Philipp Zabel
Cc: Steve Longerbeam, robh+dt, mark.rutland, shawnguo, kernel,
fabio.estevam, mchehab, hverkuil, nick, markus.heiser,
laurent.pinchart+renesas, bparrot, geert, arnd, sudipm.mukherjee,
minghsiu.tsai, tiffany.lin, jean-christophe.trotin, horms+renesas,
niklas.soderlund+renesas, robert.jarzmik, songjun.wu,
andrew-ct.chen, gregkh, shuah, sakari.ailus, pavel, devicetree,
linux-kernel, linux-arm-kernel, linux-media
In-Reply-To: <1491490912.2392.74.camel@pengutronix.de>
On Thu, Apr 06, 2017 at 05:01:52PM +0200, Philipp Zabel wrote:
> On Thu, 2017-04-06 at 15:05 +0100, Russell King - ARM Linux wrote:
> > On Thu, Apr 06, 2017 at 03:55:29PM +0200, Philipp Zabel wrote:
> > > +
> > > + /* Retain current field setting as default */
> > > + if (sdformat->format.field == V4L2_FIELD_ANY)
> > > + sdformat->format.field = fmt->field;
> > > +
> > > + /* Retain current colorspace setting as default */
> > > + if (sdformat->format.colorspace == V4L2_COLORSPACE_DEFAULT) {
> > > + sdformat->format.colorspace = fmt->colorspace;
> > > + if (sdformat->format.xfer_func == V4L2_XFER_FUNC_DEFAULT)
> > > + sdformat->format.xfer_func = fmt->xfer_func;
> > > + if (sdformat->format.ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT)
> > > + sdformat->format.ycbcr_enc = fmt->ycbcr_enc;
> > > + if (sdformat->format.quantization == V4L2_QUANTIZATION_DEFAULT)
> > > + sdformat->format.quantization = fmt->quantization;
> > > + } else {
> > > + if (sdformat->format.xfer_func == V4L2_XFER_FUNC_DEFAULT) {
> > > + sdformat->format.xfer_func =
> > > + V4L2_MAP_XFER_FUNC_DEFAULT(
> > > + sdformat->format.colorspace);
> > > + }
> > > + if (sdformat->format.ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) {
> > > + sdformat->format.ycbcr_enc =
> > > + V4L2_MAP_YCBCR_ENC_DEFAULT(
> > > + sdformat->format.colorspace);
> > > + }
> > > + if (sdformat->format.quantization == V4L2_QUANTIZATION_DEFAULT) {
> > > + sdformat->format.quantization =
> > > + V4L2_MAP_QUANTIZATION_DEFAULT(
> > > + cc->cs != IPUV3_COLORSPACE_YUV,
> > > + sdformat->format.colorspace,
> > > + sdformat->format.ycbcr_enc);
> > > + }
> > > + }
> >
> > Would it make sense for this to be a helper function?
>
> Quite possible, the next subdev that has to set frame_interval on both
> pads manually because its upstream source pad doesn't suport
> frame_interval might want to do the same.
Hmm. I'm not sure I agree with this approach. If a subdev hardware
does not support any modification of the colourspace or field, then
it should not be modifyable at the source pad - it should retain the
propagated settings from the sink pad.
I thought I had already sent a patch doing exactly that.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* Re: [PATCH V4 4/4] pwm: tegra: Add support to configure pin state in suspends/resume
From: Jon Hunter @ 2017-04-06 15:17 UTC (permalink / raw)
To: Laxman Dewangan, thierry.reding, robh+dt
Cc: mark.rutland, linux-pwm, devicetree, linux-tegra, linux-kernel
In-Reply-To: <1491488461-24621-5-git-send-email-ldewangan@nvidia.com>
On 06/04/17 15:21, Laxman Dewangan wrote:
> In some of NVIDIA Tegra's platform, PWM controller is used to
> control the PWM controlled regulators. PWM signal is connected to
> the VID pin of the regulator where duty cycle of PWM signal decide
> the voltage level of the regulator output.
>
> The tristate (high impedance of PWM pin form Tegra) also define
> one of the state of PWM regulator which needs to be configure in
> suspend state of system.
>
> Add support to configure the pin state via pinctrl frameworks in
> suspend and active state of the system.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> ---
> Changes from v1:
> - Use standard pinctrl names for sleep and active state.
> - Use API pinctrl_pm_select_*()
>
> drivers/pwm/pwm-tegra.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> index e9c4de5..af1bd4f 100644
> --- a/drivers/pwm/pwm-tegra.c
> +++ b/drivers/pwm/pwm-tegra.c
> @@ -29,6 +29,7 @@
> #include <linux/of_device.h>
> #include <linux/pwm.h>
> #include <linux/platform_device.h>
> +#include <linux/pinctrl/consumer.h>
> #include <linux/slab.h>
> #include <linux/reset.h>
>
> @@ -256,6 +257,22 @@ static int tegra_pwm_remove(struct platform_device *pdev)
> return pwmchip_remove(&pc->chip);
> }
>
> +#ifdef CONFIG_PM_SLEEP
> +static int tegra_pwm_suspend(struct device *dev)
> +{
> + pinctrl_pm_select_sleep_state(dev);
Why not return the error code here?
> +
> + return 0;
> +}
> +
> +static int tegra_pwm_resume(struct device *dev)
> +{
> + pinctrl_pm_select_default_state(dev);
And here.
By the way, do you plan to include patches to populate the bindings for
the pwm devices?
Cheers
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH] [media] imx: csi: retain current field order and colorimetry setting as default
From: Philipp Zabel @ 2017-04-06 15:18 UTC (permalink / raw)
To: Hans Verkuil
Cc: Steve Longerbeam, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, shawnguo-DgEjT+Ai2ygdnm+yROfE0A,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, fabio.estevam-3arQi8VN3Tc,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, mchehab-DgEjT+Ai2ygdnm+yROfE0A,
nick-gcszYUEDH4VrovVCs/uTlw, markus.heiser-O6JHGLzbNUwb1SvskN2V4Q,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
bparrot-l0cyMroinI0, geert-Td1EMuHUCqxL1ZNQvxDV9g,
arnd-r2nGTMty4D4, sudipm.mukherjee-Re5JQEeQqe8AvxtiuMwx3w,
minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w,
tiffany.lin-NuS5LvNUpcJWk0Htik3J/w,
jean-christophe.trotin-qxv4g6HH51o,
horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ,
niklas.soderlund+renesas-1zkq55x86MTxsAP9Fp7wbw,
robert.jarzmik-GANU6spQydw, songjun.wu-UWL1GkI3JZL3oGB3hsPCZA,
andrew-ct.chen-NuS5LvNUpcJWk0Htik3J/w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
shuah-DgEjT+Ai2ygdnm+yROfE0A, sakari.ailus-VuQAYsv1563Yd54FQh9/CA,
pavel-+ZI9xUNit7I, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-medi
In-Reply-To: <0f9690f8-c7f6-59ff-9e3e-123af9972d4b-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org>
On Thu, 2017-04-06 at 16:20 +0200, Hans Verkuil wrote:
> On 04/06/2017 03:55 PM, Philipp Zabel wrote:
> > If the the field order is set to ANY in set_fmt, choose the currently
> > set field order. If the colorspace is set to DEFAULT, choose the current
> > colorspace. If any of xfer_func, ycbcr_enc or quantization are set to
> > DEFAULT, either choose the current setting, or the default setting for the
> > new colorspace, if non-DEFAULT colorspace was given.
> >
> > This allows to let field order and colorimetry settings be propagated
> > from upstream by calling media-ctl on the upstream entity source pad,
> > and then call media-ctl on the sink pad to manually set the input frame
> > interval, without changing the already set field order and colorimetry
> > information.
> >
> > Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> > ---
> > This is based on imx-media-staging-md-v14, and it is supposed to allow
> > configuring the pipeline with media-ctl like this:
> >
> > 1) media-ctl --set-v4l2 "'tc358743 1-000f':0[fmt:UYVY8_1X16/1920x1080]"
> > 2) media-ctl --set-v4l2 "'imx6-mipi-csi2':1[fmt:UYVY8_1X16/1920x108]"
> > 3) media-ctl --set-v4l2 "'ipu1_csi0_mux':2[fmt:UYVY8_1X16/1920x1080]"
To be more clear, this media-ctl command will call VIDIOC_SUBDEV_S_FMT
on the 'ipu1_csi0':0 sink pad during the propagation phase, with field
and colorspace set to whatever was propagated from the
'tc358743 1-000f':0 pad in the previous steps (as returned by
VIDIOC_SUBDEV_G_FMT on the 'ipu1_csi0_mux':2 source pad).
> > 4) media-ctl --set-v4l2 "'ipu1_csi0':0[fmt:UYVY8_1X16/1920x1080@1/60]"
And this media-ctl command will call VIDIOC_SUBDEV_S_FMT on the
'ipu1_csi0':0 sink pad with V4L2_FIELD_ANY (since there is no "field:"
set), and with V4L2_COLORSPACE_DEFAULT (since there is no colorspace:"
set) and so on. I don't want the correct values from step 3) to be
replaced with DEFAULT here.
> > 5) media-ctl --set-v4l2 "'ipu1_csi0':2[fmt:AYUV32/1920x1080@1/30]"
> >
> > Without having step 4) overwrite the colorspace and field order set on
> > 'ipu1_csi0':0 by the propagation in step 3).
> > ---
> > drivers/staging/media/imx/imx-media-csi.c | 34 +++++++++++++++++++++++++++++++
> > 1 file changed, 34 insertions(+)
> >
> > diff --git a/drivers/staging/media/imx/imx-media-csi.c b/drivers/staging/media/imx/imx-media-csi.c
> > index 64dc454f6b371..d94ce1de2bf05 100644
> > --- a/drivers/staging/media/imx/imx-media-csi.c
> > +++ b/drivers/staging/media/imx/imx-media-csi.c
> > @@ -1325,6 +1325,40 @@ static int csi_set_fmt(struct v4l2_subdev *sd,
So the VIDIOC_SUBDEV_S_FMT callback has to check for DEFAULT values and
do something about them.
> > csi_try_fmt(priv, sensor, cfg, sdformat, crop, compose, &cc);
> >
> > fmt = __csi_get_fmt(priv, cfg, sdformat->pad, sdformat->which);
> > +
> > + /* Retain current field setting as default */
> > + if (sdformat->format.field == V4L2_FIELD_ANY)
> > + sdformat->format.field = fmt->field;
>
> sdformat->format.field should never be FIELD_ANY. If it is, then that's a
> subdev bug and I'm pretty sure FIELD_NONE was intended.
>
> > +
> > + /* Retain current colorspace setting as default */
> > + if (sdformat->format.colorspace == V4L2_COLORSPACE_DEFAULT) {
> > + sdformat->format.colorspace = fmt->colorspace;
>
> No! Subdevs should never return COLORSPACE_DEFAULT. If they do, then fix
> them. If this happens a lot (I'm not sure how reliably subdevs fill this
> in) you could set it to COLORSPACE_RAW. Perhaps with a WARN_ON_ONCE.
>
> > + if (sdformat->format.xfer_func == V4L2_XFER_FUNC_DEFAULT)
> > + sdformat->format.xfer_func = fmt->xfer_func;
> > + if (sdformat->format.ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT)
> > + sdformat->format.ycbcr_enc = fmt->ycbcr_enc;
> > + if (sdformat->format.quantization == V4L2_QUANTIZATION_DEFAULT)
> > + sdformat->format.quantization = fmt->quantization;
>
> Nack. This is meaningless.
>
> > + } else {
> > + if (sdformat->format.xfer_func == V4L2_XFER_FUNC_DEFAULT) {
> > + sdformat->format.xfer_func =
> > + V4L2_MAP_XFER_FUNC_DEFAULT(
> > + sdformat->format.colorspace);
> > + }
> > + if (sdformat->format.ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) {
> > + sdformat->format.ycbcr_enc =
> > + V4L2_MAP_YCBCR_ENC_DEFAULT(
> > + sdformat->format.colorspace);
> > + }
> > + if (sdformat->format.quantization == V4L2_QUANTIZATION_DEFAULT) {
> > + sdformat->format.quantization =
> > + V4L2_MAP_QUANTIZATION_DEFAULT(
> > + cc->cs != IPUV3_COLORSPACE_YUV,
> > + sdformat->format.colorspace,
> > + sdformat->format.ycbcr_enc);
> > + }
>
> This isn't wrong, but it is perfectly fine to keep the DEFAULT here and let
> the application call V4L2_MAP_.
>
> I get the feeling this patch is a workaround for subdev errors. Either that,
> or the commit log doesn't give me enough information to really understand the
> problem that's being addressed here.
>
> Regards,
>
> Hans
>
> > + }
> > +
> > *fmt = sdformat->format;
> >
> > if (sdformat->pad == CSI_SINK_PAD) {
> >
regards
Philipp
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^ permalink raw reply
* Re: [PATCH] [media] imx: csi: retain current field order and colorimetry setting as default
From: Philipp Zabel @ 2017-04-06 15:25 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Steve Longerbeam, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, shawnguo-DgEjT+Ai2ygdnm+yROfE0A,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, fabio.estevam-3arQi8VN3Tc,
mchehab-DgEjT+Ai2ygdnm+yROfE0A, hverkuil-qWit8jRvyhVmR6Xm/wNWPw,
nick-gcszYUEDH4VrovVCs/uTlw, markus.heiser-O6JHGLzbNUwb1SvskN2V4Q,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
bparrot-l0cyMroinI0, geert-Td1EMuHUCqxL1ZNQvxDV9g,
arnd-r2nGTMty4D4, sudipm.mukherjee-Re5JQEeQqe8AvxtiuMwx3w,
minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w,
tiffany.lin-NuS5LvNUpcJWk0Htik3J/w,
jean-christophe.trotin-qxv4g6HH51o,
horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ,
niklas.soderlund+renesas-1zkq55x86MTxsAP9Fp7wbw,
robert.jarzmik-GANU6spQydw, songjun.wu-UWL1GkI3JZL3oGB3hsPCZA,
andrew-ct.chen-NuS5LvNUpcJWk0Htik3J/w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
shuah-DgEjT+Ai2ygdnm+yROfE0A, sakari.ailus-VuQAYsv1563Yd54FQh9/CA,
pavel-+ZI9xUNit7I, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-media
In-Reply-To: <20170406151032.GH17774-l+eeeJia6m9URfEZ8mYm6t73F7V6hmMc@public.gmane.org>
On Thu, 2017-04-06 at 16:10 +0100, Russell King - ARM Linux wrote:
> On Thu, Apr 06, 2017 at 05:01:52PM +0200, Philipp Zabel wrote:
> > On Thu, 2017-04-06 at 15:05 +0100, Russell King - ARM Linux wrote:
> > > On Thu, Apr 06, 2017 at 03:55:29PM +0200, Philipp Zabel wrote:
> > > > +
> > > > + /* Retain current field setting as default */
> > > > + if (sdformat->format.field == V4L2_FIELD_ANY)
> > > > + sdformat->format.field = fmt->field;
> > > > +
> > > > + /* Retain current colorspace setting as default */
> > > > + if (sdformat->format.colorspace == V4L2_COLORSPACE_DEFAULT) {
> > > > + sdformat->format.colorspace = fmt->colorspace;
> > > > + if (sdformat->format.xfer_func == V4L2_XFER_FUNC_DEFAULT)
> > > > + sdformat->format.xfer_func = fmt->xfer_func;
> > > > + if (sdformat->format.ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT)
> > > > + sdformat->format.ycbcr_enc = fmt->ycbcr_enc;
> > > > + if (sdformat->format.quantization == V4L2_QUANTIZATION_DEFAULT)
> > > > + sdformat->format.quantization = fmt->quantization;
> > > > + } else {
> > > > + if (sdformat->format.xfer_func == V4L2_XFER_FUNC_DEFAULT) {
> > > > + sdformat->format.xfer_func =
> > > > + V4L2_MAP_XFER_FUNC_DEFAULT(
> > > > + sdformat->format.colorspace);
> > > > + }
> > > > + if (sdformat->format.ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) {
> > > > + sdformat->format.ycbcr_enc =
> > > > + V4L2_MAP_YCBCR_ENC_DEFAULT(
> > > > + sdformat->format.colorspace);
> > > > + }
> > > > + if (sdformat->format.quantization == V4L2_QUANTIZATION_DEFAULT) {
> > > > + sdformat->format.quantization =
> > > > + V4L2_MAP_QUANTIZATION_DEFAULT(
> > > > + cc->cs != IPUV3_COLORSPACE_YUV,
> > > > + sdformat->format.colorspace,
> > > > + sdformat->format.ycbcr_enc);
> > > > + }
> > > > + }
> > >
> > > Would it make sense for this to be a helper function?
> >
> > Quite possible, the next subdev that has to set frame_interval on both
> > pads manually because its upstream source pad doesn't suport
> > frame_interval might want to do the same.
>
> Hmm. I'm not sure I agree with this approach. If a subdev hardware
> does not support any modification of the colourspace or field, then
> it should not be modifyable at the source pad - it should retain the
> propagated settings from the sink pad.
This new code is only relevant for the CSI_SINK_PAD.
> I thought I had already sent a patch doing exactly that.
Yes. Right above the modification there is a call to csi_try_fmt which
will already fix up sdformat->format for the source pads. So for the
CSI_SRC_PAD_DIRECT and CSI_SRC_PAD_IDMAC this should amount to a no-op.
If might be better to move this into a separate function and only call
it if sdformat->pad == CSI_SINK_PAD.
regards
Philipp
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