* Applied "ASoC: cs35l35: Add DT binding to specify usage of an external boost supply" to the asoc tree
From: Mark Brown @ 2017-04-06 18:55 UTC (permalink / raw)
To: Charles Keepax; +Cc: Brian Austin, Mark Brown
In-Reply-To: <1491483134-28079-3-git-send-email-ckeepax-yzvPICuk2AATkU/dhu1WVueM+bqZidxxQQ4Iyu8u01E@public.gmane.org>
The patch
ASoC: cs35l35: Add DT binding to specify usage of an external boost supply
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From 0c67fb5544061cb990e07a73e1b7ba1f8ca22479 Mon Sep 17 00:00:00 2001
From: Charles Keepax <ckeepax-yzvPICuk2AATkU/dhu1WVueM+bqZidxxQQ4Iyu8u01E@public.gmane.org>
Date: Thu, 6 Apr 2017 13:52:14 +0100
Subject: [PATCH] ASoC: cs35l35: Add DT binding to specify usage of an external
boost supply
Add a device tree binding to let the driver know that the amplifier is
configured to use an external boost supply.
Signed-off-by: Charles Keepax <ckeepax-yzvPICuk2AATkU/dhu1WVueM+bqZidxxQQ4Iyu8u01E@public.gmane.org>
Acked-by: Brian Austin <brian.austin-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
Signed-off-by: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/sound/cs35l35.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/cs35l35.txt b/Documentation/devicetree/bindings/sound/cs35l35.txt
index 958f0eabfdfc..457d176dcee0 100644
--- a/Documentation/devicetree/bindings/sound/cs35l35.txt
+++ b/Documentation/devicetree/bindings/sound/cs35l35.txt
@@ -33,6 +33,10 @@ Optional properties:
- cirrus,shared-boost : Boolean to enable ClassH tracking of Advisory Signal
if 2 Devices share Boost BST_CTL
+ - cirrus,external-boost : Boolean to specify the device is using an external
+ boost supply, note that sharing a boost from another cs35l35 would constitute
+ using an external supply for the slave device
+
- cirrus,sp-drv-strength : Value for setting the Serial Port drive strength
Table 3-10 of the datasheet lists drive-strength specifications
0 = 1x (Default)
--
2.11.0
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^ permalink raw reply related
* Re: [RFC 4/8] regulator: core: Check enabling bypass respects constraints
From: Mark Brown @ 2017-04-06 18:52 UTC (permalink / raw)
To: Leonard Crestez
Cc: Sascha Hauer, Liam Girdwood, Viresh Kumar, Rafael J. Wysocki,
Shawn Guo, Robin Gong, Anson Huang, Irina Tirdea, Rob Herring,
Mark Rutland, Fabio Estevam, Octavian Purdila,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1490730595.15830.1.camel-3arQi8VN3Tc@public.gmane.org>
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On Tue, Mar 28, 2017 at 10:49:55PM +0300, Leonard Crestez wrote:
> On Tue, 2017-03-28 at 17:47 +0100, Mark Brown wrote:
> > To repeat what I said previously the whole point of bypassing is to not
> > do regulation and generally the constraints in the unregulated idle case
> > are substantially more relaxed. This would break use cases relying on
> > the existing behaviour which wouldn't expect to affect the parent
> > voltage at all, either stopping things working or making them less
> > efficient by needlessly regulating the voltage down which defeats the
> > main point of bypassing.
> So what you want is to prevent voltage changes unless strictly
> required, even lowering? What I want is to get the minimum voltage in
> the SOC because that's where power is being consumed.
So your end goal here is to bypass a regulator which is forced into your
system design by being integrated into the SoC which isn't able to
regulate down to a low enough voltage for your use case? I guess one
question is if you need to use the regulator at all?
> It's not at all obvious that in bypass mode the output constraints of a
> regulator need not be respected by the core. I expected the opposite,
> this is something that should be documented.
SubmittingPatches... Bear in mind that most regulators are fixed
voltage in a given system so bypass would be very difficult to use if it
tried to pass the constraints upstream.
> But if the bypassed regulator has a downstream consumer then it's
> requirements should definitely still be met in bypass mode, right? I
> could set my maximum voltage directly from cpufreq in that case.
What we're interpreting bypass mode as meaning is "stop regulating".
There will still be some limits but we're expecting them to be enforced
in the extremes of the constraints in the parent regulators.
> Or should a bypassed regulator ignore all other requests? One of the
> behaviors that this patch series relies on is that calling set_voltage
> on a bypassed regulator propagates this request to the supply and picks
> the minimum voltage there. An alternative implementation would be to
Yes, the expectation is that if anything is being changed it won't have
any effect until regulation is reenabled but we're not particularly
expecting much activity on bypassed regulators.
> call set_voltage directly on the supply regulator by changing the
> "{arm,soc,pu}-supply" references in DT to point to the PMIC instead.
> Would that be better?
That's more what's expected here.
> Both approaches work. Relying on propagation feels like it is the
> "right way" to handle this, even if it's harder to get right and the
> regulator core does not entirely support it. But it's possible that
> this is based on a misunderstanding of what "bypass" is actually
> supposed to do.
Another option would be to add a regulator configuration which allowed
the regulator to transparently go into bypass mode if the parent could
do things directly, only enabling regulation if the parent couldn't
support. That would mean you'd loose the supply cleanup function which
is typically part of why there are LDOs in the system but it sounds like
you're OK with that in at least your use case.
We could also perhaps have a way to set the regulator into permanent
bypass mode from the constraints for use cases that just never need it
and then remap the supply relationship at probe time (which avoids any
special runtime casing) for something even simpler.
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^ permalink raw reply
* Re: [PATCH V10 00/12] IOMMU probe deferral support
From: Frank Rowand @ 2017-04-06 18:46 UTC (permalink / raw)
To: Rob Herring, Sricharan R
Cc: Robin Murphy, Will Deacon, Joerg Roedel, Lorenzo Pieralisi,
Linux IOMMU, linux-arm-kernel@lists.infradead.org, linux-arm-msm,
Marek Szyprowski, bhelgaas@google.com, linux-pci@vger.kernel.org,
linux-acpi@vger.kernel.org, Tomasz Nowicki, Hanjun Guo,
Sinan Kaya, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <CAL_JsqJH9C9sNGBSLH88bJ=uKF7RibHDAUZUW9M2xeO2AM-FUw@mail.gmail.com>
On 04/04/17 18:23, Rob Herring wrote:
> On Tue, Apr 4, 2017 at 5:18 AM, Sricharan R <sricharan@codeaurora.org> wrote:
>> This series calls the dma ops configuration for the devices
>> at a generic place so that it works for all busses.
>> The dma_configure_ops for a device is now called during
>> the device_attach callback just before the probe of the
>> bus/driver is called. Similarly dma_deconfigure is called during
>> device/driver_detach path.
>
> For patches 3, 4, 6, 7, 8:
>
> Acked-by: Rob Herring <robh@kernel.org>
> .
>
And a few hours later, I had the opposite opinion on a couple of
patches, so there is some ongoing discussion working this out.
-Frank
^ permalink raw reply
* Re: [PATCH] of: change fixup of dma-ranges size to error
From: Frank Rowand @ 2017-04-06 18:37 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAL_Jsq+GLBtaezUiTbm0DAA2+MjcvxAcCsS-qJrr05YcTO5tdw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 04/06/17 07:03, Rob Herring wrote:
> On Thu, Apr 6, 2017 at 1:18 AM, <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> From: Frank Rowand <frank.rowand-7U/KSKJipcs@public.gmane.org>
>>
>> of_dma_get_range() has workaround code to fixup a device tree that
>> incorrectly specified a mask instead of a size for property
>> dma-ranges. That device tree was fixed a year ago in v4.6, so
>> the workaround is no longer needed. Leave a data validation
>> check in place, but no longer do the fixup. Move the check
>> one level deeper in the call stack so that other possible users
>> of dma-ranges will also be protected.
>>
>> The fix to the device tree was in
>> commit c91cb9123cdd ("dtb: amd: Fix DMA ranges in device tree").
>
> NACK.
> This was by design. You can't represent a size of 2^64 or 2^32.
I agree that being unable to represent a size of 2^32 in a u32 and
a size of 2^64 in a u64 is the underlying issue.
But the code to convert a mask to a size is _not_ design, it is a
hack that temporarily worked around a device tree that did not follow
the dma-ranges binding in the ePAPR.
That device tree was corrected a year ago to provide a size instead of
a mask.
> Well, technically you can for the latter, but then you have to grow
> #size-cells to 2 for an otherwise all 32-bit system which seems kind
> of pointless and wasteful. You could further restrict this to only
> allow ~0 and not just any case with bit 0 set.
>
> I'm pretty sure AMD is not the only system. There were 32-bit systems too.
I examined all instances of property dma-ranges in in tree dts files in
Linux 4.11-rc1. There are none that incorrectly specify mask instead of
size.
#size-cells only changes to 2 for the dma-ranges property and the ranges
property when size is 2^32, so that is a very small amount of space.
The patch does not allow for a size of 2^64. If a system requires a
size of 2^64 then the type of size needs to increase to be larger
than a u64. If you would like for the code to be defensive and
detect a device tree providing a size of 2^64 then I can add a
check to of_dma_get_range() to return -EINVAL if #size-cells > 2.
When that error triggers, the type of size can be changed.
>
> Rob
>
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^ permalink raw reply
* Re: [PATCH v3] regulator: Add driver for voltage controlled regulators
From: Mark Brown @ 2017-04-06 18:21 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Liam Girdwood, Rob Herring, Mark Rutland,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Douglas Anderson, Brian Norris
In-Reply-To: <20170331205035.126001-1-mka-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 815 bytes --]
On Fri, Mar 31, 2017 at 01:50:35PM -0700, Matthias Kaehlcke wrote:
> +- compatible : must be "vctrl-regulator".
> +- regulator-min-microvolt : smallest voltage consumers may set
> +- regulator-max-microvolt : largest voltage consumers may set
> +- ctrl-regulator: : the name of the regulator supplying the control
> + voltage.
This looks good except for this bit where we read the regulator name out
of the DT, that's generally a sign of bad practice for things that are
less simple passives than things like this or fixed voltage regulators.
As with the supplies for fixed voltage regulators just pick a name for
the supply (ctrl seems fine to me) and use that, neither option is
perfect but at elast this less typing for everyone and it's consistent
with what other similar things are already doing.
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^ permalink raw reply
* [PATCH v3 9/9] ARM: dts: imx6ul-isiot: Add FEC node support
From: Jagan Teki @ 2017-04-06 18:02 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Sascha Hauer, Fabio Estevam,
Matteo Lisi, Michael Trimarchi, Jagan Teki
In-Reply-To: <1491501735-1649-1-git-send-email-jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Add support for fec1 node on Engicam Is.IoT variant boards.
Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Matteo Lisi <matteo.lisi-4s7YQHO/iPVBDgjK7y7TUQ@public.gmane.org>
Cc: Michael Trimarchi <michael-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
Changes for v3:
- none
Changes for v2:
- Newly added patch
arch/arm/boot/dts/imx6ul-isiot.dtsi | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi
index 7e947e5..ccc5477 100644
--- a/arch/arm/boot/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi
@@ -129,6 +129,24 @@
status = "okay";
};
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+};
+
&pwm8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
@@ -159,6 +177,21 @@
};
&iomuxc {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
--
1.9.1
--
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^ permalink raw reply related
* [PATCH v3 8/9] ARM: dts: imx6qdl-icore-rqs: Add CAN nodes
From: Jagan Teki @ 2017-04-06 18:02 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel, devicetree, linux-kernel, Sascha Hauer,
Fabio Estevam, Matteo Lisi, Michael Trimarchi, Jagan Teki
In-Reply-To: <1491501735-1649-1-git-send-email-jagan@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
Add support for can1 and can2 nodes on Engicam i.CoreM6 RQS
QDL module boards.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v3:
- none
Changes for v2:
- s/flexcan/can
- s/pinctrl_flexcan/pinctrl_can
arch/arm/boot/dts/imx6dl-icore-rqs.dts | 8 ++++++++
arch/arm/boot/dts/imx6q-icore-rqs.dts | 8 ++++++++
arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 26 ++++++++++++++++++++++++++
3 files changed, 42 insertions(+)
diff --git a/arch/arm/boot/dts/imx6dl-icore-rqs.dts b/arch/arm/boot/dts/imx6dl-icore-rqs.dts
index 053e7cb..74335c4 100644
--- a/arch/arm/boot/dts/imx6dl-icore-rqs.dts
+++ b/arch/arm/boot/dts/imx6dl-icore-rqs.dts
@@ -60,3 +60,11 @@
VDDD-supply = <®_1p8v>;
};
};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-icore-rqs.dts b/arch/arm/boot/dts/imx6q-icore-rqs.dts
index d45e4f5..2d4539a 100644
--- a/arch/arm/boot/dts/imx6q-icore-rqs.dts
+++ b/arch/arm/boot/dts/imx6q-icore-rqs.dts
@@ -49,6 +49,14 @@
compatible = "engicam,imx6-icore-rqs", "fsl,imx6q";
};
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
+
&i2c3 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
index 0e79a5b..998fa77 100644
--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
@@ -145,6 +145,18 @@
};
};
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1>;
+ xceiver-supply = <®_3p3v>;
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can2>;
+ xceiver-supply = <®_3p3v>;
+};
+
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
@@ -296,6 +308,20 @@
>;
};
+ pinctrl_can1: can1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
+ >;
+ };
+
+ pinctrl_can2: can2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
--
1.9.1
^ permalink raw reply related
* [PATCH v3 7/9] ARM: dts: imx6dl-icore: Add touchscreen node
From: Jagan Teki @ 2017-04-06 18:02 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Sascha Hauer, Fabio Estevam,
Matteo Lisi, Michael Trimarchi, Jagan Teki
In-Reply-To: <1491501735-1649-1-git-send-email-jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
max11801 touchscreen on Engicam iCoreM6 DualLite/Solo module is
connected via i2c1, so add max11801: touchscreen@48 on i2c1.
Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Matteo Lisi <matteo.lisi-4s7YQHO/iPVBDgjK7y7TUQ@public.gmane.org>
Cc: Michael Trimarchi <michael-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
Changes for v3,v2:
- none
arch/arm/boot/dts/imx6dl-icore.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts
index ea9ab05..27f37cd 100644
--- a/arch/arm/boot/dts/imx6dl-icore.dts
+++ b/arch/arm/boot/dts/imx6dl-icore.dts
@@ -58,6 +58,15 @@
status = "okay";
};
+&i2c1 {
+ max11801: touchscreen@48 {
+ compatible = "maxim,max11801";
+ reg = <0x48>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
&i2c3 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
--
1.9.1
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^ permalink raw reply related
* [PATCH v3 6/9] ARM: dts: imx6dl-icore: Add LVDS support
From: Jagan Teki @ 2017-04-06 18:02 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel, devicetree, linux-kernel, Sascha Hauer,
Fabio Estevam, Matteo Lisi, Michael Trimarchi, Jagan Teki
In-Reply-To: <1491501735-1649-1-git-send-email-jagan@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
Add LVDS display support for OpenFrame Capacitive touch 7 inc
display which is supported by Engicam i.CoreM6 DualLite/Solo Starter Kit.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v3,v2:
- none
arch/arm/boot/dts/imx6dl-icore.dts | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts
index 0562ce4..ea9ab05 100644
--- a/arch/arm/boot/dts/imx6dl-icore.dts
+++ b/arch/arm/boot/dts/imx6dl-icore.dts
@@ -68,3 +68,28 @@
VDDD-supply = <®_1p8v>;
};
};
+
+&ldb {
+ status = "okay";
+
+ lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <60000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <30>;
+ hfront-porch = <30>;
+ vback-porch = <5>;
+ vfront-porch = <5>;
+ hsync-len = <64>;
+ vsync-len = <20>;
+ };
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related
* [PATCH v3 5/9] ARM: dts: imx6qdl-icore-rqs: Replace to use simple-audio-card
From: Jagan Teki @ 2017-04-06 18:02 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree, Matteo Lisi, linux-kernel, Jagan Teki, Sascha Hauer,
Fabio Estevam, Michael Trimarchi, linux-arm-kernel
In-Reply-To: <1491501735-1649-1-git-send-email-jagan@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
This patch replace fsl,imx-audio-sgtl5000 and use simple-audio-card
for Engicam i.CoreM6 RQS QDL platform boards.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v3:
- Newly added patch
arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 26 +++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
index d24e531..0e79a5b 100644
--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
@@ -120,16 +120,28 @@
};
sound {
- compatible = "fsl,imx-audio-sgtl5000";
- model = "imx-audio-sgtl5000";
- ssi-controller = <&ssi1>;
- audio-codec = <&sgtl5000>;
- audio-routing =
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx6qdl-icore-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
- mux-int-port = <1>;
- mux-ext-port = <4>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&ssi1>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ };
};
};
--
1.9.1
^ permalink raw reply related
* [PATCH v3 4/9] ARM: dts: imx6dl-icore-rqs: Add sgtl5000 codec node
From: Jagan Teki @ 2017-04-06 18:02 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel, devicetree, linux-kernel, Sascha Hauer,
Fabio Estevam, Matteo Lisi, Michael Trimarchi, Jagan Teki
In-Reply-To: <1491501735-1649-1-git-send-email-jagan@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
- Moved sound card node to imx6qdl-icore-rqs.dtsi
- Added codec node in imx6dl-icore-rqs
- Replace codec: sgtl5000@0a => sgtl5000: codec@a
on imx6q-icore-rqs.dts to [label:] node-name[@unit-address]
according to devicetree specification from ePAPER v1.1
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v3:
- squash previous [PATCH v2 10/15] and [PATCH v2 11/15]
Changes for v2:
- Newly added patch
arch/arm/boot/dts/imx6dl-icore-rqs.dts | 11 +++++++++++
arch/arm/boot/dts/imx6q-icore-rqs.dts | 15 +--------------
arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 13 +++++++++++++
3 files changed, 25 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-icore-rqs.dts b/arch/arm/boot/dts/imx6dl-icore-rqs.dts
index cf42c2f..053e7cb 100644
--- a/arch/arm/boot/dts/imx6dl-icore-rqs.dts
+++ b/arch/arm/boot/dts/imx6dl-icore-rqs.dts
@@ -49,3 +49,14 @@
model = "Engicam i.CoreM6 DualLite/Solo RQS Starter Kit";
compatible = "engicam,imx6-icore-rqs", "fsl,imx6dl";
};
+
+&i2c3 {
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ VDDD-supply = <®_1p8v>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6q-icore-rqs.dts b/arch/arm/boot/dts/imx6q-icore-rqs.dts
index e451b4c..d45e4f5 100644
--- a/arch/arm/boot/dts/imx6q-icore-rqs.dts
+++ b/arch/arm/boot/dts/imx6q-icore-rqs.dts
@@ -47,23 +47,10 @@
/ {
model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit";
compatible = "engicam,imx6-icore-rqs", "fsl,imx6q";
-
- sound {
- compatible = "fsl,imx-audio-sgtl5000";
- model = "imx-audio-sgtl5000";
- ssi-controller = <&ssi1>;
- audio-codec = <&codec>;
- audio-routing =
- "MIC_IN", "Mic Jack",
- "Mic Jack", "Mic Bias",
- "Headphone Jack", "HP_OUT";
- mux-int-port = <1>;
- mux-ext-port = <4>;
- };
};
&i2c3 {
- codec: sgtl5000@0a {
+ sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
index 5fab5be..d24e531 100644
--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
@@ -118,6 +118,19 @@
clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
clock-names = "refclk";
};
+
+ sound {
+ compatible = "fsl,imx-audio-sgtl5000";
+ model = "imx-audio-sgtl5000";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <4>;
+ };
};
&clks {
--
1.9.1
^ permalink raw reply related
* [PATCH v3 3/9] ARM: dts: imx6qdl-icore: Add Sound card with codec node
From: Jagan Teki @ 2017-04-06 18:02 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel, devicetree, linux-kernel, Sascha Hauer,
Fabio Estevam, Matteo Lisi, Michael Trimarchi, Jagan Teki
In-Reply-To: <1491501735-1649-1-git-send-email-jagan@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
Add support for Sound card and related codec(via i2c1) nodes
on below Engicam module boards.
- i.CoreM6 DualLite/Solo Starter kit
- i.CoreM6 Quad/Dual Starter kit
- i.CoreM6 Quad/Dual OpenFrame Cap touch 10.1
- i.CoreM6 Quad/Dual OpenFrame Cap touch 12.3
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v3:
- Replace fsl,imx-audio-sgtl5000 and use simple-audio-card
Changes for v2:
- Use proper [label:] node-name[@unit-address] for codec
arch/arm/boot/dts/imx6dl-icore.dts | 11 +++++++
arch/arm/boot/dts/imx6q-icore-ofcap10.dts | 11 +++++++
arch/arm/boot/dts/imx6q-icore-ofcap12.dts | 11 +++++++
arch/arm/boot/dts/imx6q-icore.dts | 11 +++++++
arch/arm/boot/dts/imx6qdl-icore.dtsi | 48 +++++++++++++++++++++++++++++++
5 files changed, 92 insertions(+)
diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts
index 6de83c7..0562ce4 100644
--- a/arch/arm/boot/dts/imx6dl-icore.dts
+++ b/arch/arm/boot/dts/imx6dl-icore.dts
@@ -57,3 +57,14 @@
&can2 {
status = "okay";
};
+
+&i2c3 {
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ VDDD-supply = <®_1p8v>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
index 49b60ca..f63b87f 100644
--- a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
+++ b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
@@ -50,6 +50,17 @@
compatible = "engicam,imx6-icore", "fsl,imx6q";
};
+&i2c3 {
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ VDDD-supply = <®_1p8v>;
+ };
+};
+
&ldb {
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap12.dts b/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
index 9e230f5..68ca828 100644
--- a/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
+++ b/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
@@ -50,6 +50,17 @@
compatible = "engicam,imx6-icore", "fsl,imx6q";
};
+&i2c3 {
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ VDDD-supply = <®_1p8v>;
+ };
+};
+
&ldb {
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-icore.dts b/arch/arm/boot/dts/imx6q-icore.dts
index 5613dd9..1ae7294 100644
--- a/arch/arm/boot/dts/imx6q-icore.dts
+++ b/arch/arm/boot/dts/imx6q-icore.dts
@@ -67,6 +67,17 @@
};
};
+&i2c3 {
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ VDDD-supply = <®_1p8v>;
+ };
+};
+
&ldb {
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
index 56d0c5d..1bd7cdb 100644
--- a/arch/arm/boot/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
@@ -55,6 +55,25 @@
default-brightness-level = <7>;
};
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+
+ reg_2p5v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
@@ -87,6 +106,31 @@
#clock-cells = <0>;
clock-frequency = <25000000>; /* 25MHz for example */
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx6qdl-icore-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&ssi1>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ };
+ };
};
&can1 {
@@ -149,6 +193,10 @@
status = "okay";
};
+&ssi1 {
+ status = "okay";
+};
+
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
--
1.9.1
^ permalink raw reply related
* [PATCH v3 2/9] ARM: dts: imx6ul-geam: Add Sound card with codec node
From: Jagan Teki @ 2017-04-06 18:02 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Sascha Hauer, Fabio Estevam,
Matteo Lisi, Michael Trimarchi, Jagan Teki
In-Reply-To: <1491501735-1649-1-git-send-email-jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Add support for Sound card and related codec(via i2c1) nodes
on Engicam GEAM6UL variant module boards.
Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Matteo Lisi <matteo.lisi-4s7YQHO/iPVBDgjK7y7TUQ@public.gmane.org>
Cc: Michael Trimarchi <michael-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
Changes for v3:
- Replace fsl,imx-audio-sgtl5000 and use simple-audio-card
Changes for v2:
- Use proper [label:] node-name[@unit-address] for codec
- Remove incorrect codec property 'wlf,shared-lrclk'
- Remove 'gpr' from sound card node
arch/arm/boot/dts/imx6ul-geam-kit.dts | 12 ++++++++++++
arch/arm/boot/dts/imx6ul-geam.dtsi | 26 ++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul-geam-kit.dts b/arch/arm/boot/dts/imx6ul-geam-kit.dts
index 142e60c..02edcba 100644
--- a/arch/arm/boot/dts/imx6ul-geam-kit.dts
+++ b/arch/arm/boot/dts/imx6ul-geam-kit.dts
@@ -58,6 +58,18 @@
status = "okay";
};
+&i2c1 {
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6UL_CLK_OSC>;
+ clock-names = "mclk";
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ VDDD-supply = <®_1p8v>;
+ };
+};
+
&lcdif {
display = <&display0>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6ul-geam.dtsi b/arch/arm/boot/dts/imx6ul-geam.dtsi
index eb94d95..3bc3238 100644
--- a/arch/arm/boot/dts/imx6ul-geam.dtsi
+++ b/arch/arm/boot/dts/imx6ul-geam.dtsi
@@ -87,6 +87,32 @@
regulator-always-on;
regulator-boot-on;
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx6ul-geam-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ clocks = <&clks IMX6UL_CLK_SAI2>;
+ };
+ };
};
&can1 {
--
1.9.1
--
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v3 1/9] ARM: dts: imx6ul-isiot: Add Sound card with codec node
From: Jagan Teki @ 2017-04-06 18:02 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Sascha Hauer, Fabio Estevam,
Matteo Lisi, Michael Trimarchi, Jagan Teki
In-Reply-To: <1491501735-1649-1-git-send-email-jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Add support for Sound card and related codec(via i2c1) nodes
on Engicam Is.IoT MX6UL variant module boards.
Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Matteo Lisi <matteo.lisi-4s7YQHO/iPVBDgjK7y7TUQ@public.gmane.org>
Cc: Michael Trimarchi <michael-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
Changes for v3:
- Replace fsl,imx-audio-sgtl5000 and use simple-audio-card
Changes for v2:
- Use proper [label:] node-name[@unit-address] for codec
- Remove incorrect codec property 'wlf,shared-lrclk'
- Remove 'gpr' from sound card node
arch/arm/boot/dts/imx6ul-isiot-common.dtsi | 10 +++++++
arch/arm/boot/dts/imx6ul-isiot.dtsi | 44 ++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul-isiot-common.dtsi b/arch/arm/boot/dts/imx6ul-isiot-common.dtsi
index 2beaab6..d456080 100644
--- a/arch/arm/boot/dts/imx6ul-isiot-common.dtsi
+++ b/arch/arm/boot/dts/imx6ul-isiot-common.dtsi
@@ -41,6 +41,16 @@
*/
&i2c1 {
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6UL_CLK_OSC>;
+ clock-names = "mclk";
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ VDDD-supply = <®_1p8v>;
+ };
+
stmpe811: gpio-expander@44 {
compatible = "st,stmpe811";
reg = <0x44>;
diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi
index ea30380..7e947e5 100644
--- a/arch/arm/boot/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi
@@ -69,6 +69,50 @@
100>;
default-brightness-level = <100>;
};
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx6ul-isiot-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ clocks = <&clks IMX6UL_CLK_SAI2>;
+ };
+ };
};
&i2c1 {
--
1.9.1
--
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^ permalink raw reply related
* [PATCH v3 0/9] ARM: dts: i.MX6: Add lcdif/sound nodes on Engicam SOMs
From: Jagan Teki @ 2017-04-06 18:02 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel, devicetree, linux-kernel, Sascha Hauer,
Fabio Estevam, Matteo Lisi, Michael Trimarchi, Jagan Teki
From: Jagan Teki <jagan@amarulasolutions.com>
This patchset, add support for LVDS, touchscreen, sound card and related codec
and can nodes all Engicam SOM's which are supporting mainline as of now.
Jagan Teki (9):
ARM: dts: imx6ul-isiot: Add Sound card with codec node
ARM: dts: imx6ul-geam: Add Sound card with codec node
ARM: dts: imx6qdl-icore: Add Sound card with codec node
ARM: dts: imx6dl-icore-rqs: Add sgtl5000 codec node
ARM: dts: imx6qdl-icore-rqs: Replace to use simple-audio-card
ARM: dts: imx6dl-icore: Add LVDS support
ARM: dts: imx6dl-icore: Add touchscreen node
ARM: dts: imx6qdl-icore-rqs: Add CAN nodes
ARM: dts: imx6ul-isiot: Add FEC node support
arch/arm/boot/dts/imx6dl-icore-rqs.dts | 19 ++++++++
arch/arm/boot/dts/imx6dl-icore.dts | 45 +++++++++++++++++
arch/arm/boot/dts/imx6q-icore-ofcap10.dts | 11 +++++
arch/arm/boot/dts/imx6q-icore-ofcap12.dts | 11 +++++
arch/arm/boot/dts/imx6q-icore-rqs.dts | 21 ++++----
arch/arm/boot/dts/imx6q-icore.dts | 11 +++++
arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 51 ++++++++++++++++++++
arch/arm/boot/dts/imx6qdl-icore.dtsi | 48 +++++++++++++++++++
arch/arm/boot/dts/imx6ul-geam-kit.dts | 12 +++++
arch/arm/boot/dts/imx6ul-geam.dtsi | 26 ++++++++++
arch/arm/boot/dts/imx6ul-isiot-common.dtsi | 10 ++++
arch/arm/boot/dts/imx6ul-isiot.dtsi | 77 ++++++++++++++++++++++++++++++
12 files changed, 329 insertions(+), 13 deletions(-)
--
1.9.1
^ permalink raw reply
* Re: [PATCH 1/1] gpio: core: Decouple open drain/source flag with active low/high
From: Andy Shevchenko @ 2017-04-06 17:30 UTC (permalink / raw)
To: Laxman Dewangan
Cc: Linus Walleij, Alexandre Courbot, Rob Herring, Mark Rutland,
Frank Rowand, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree
In-Reply-To: <58E67328.5040805@nvidia.com>
On Thu, Apr 6, 2017 at 7:56 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote:
> On Thursday 06 April 2017 09:40 PM, Andy Shevchenko wrote:
>> On Thu, Apr 6, 2017 at 4:35 PM, Laxman Dewangan <ldewangan@nvidia.com>
>> wrote:
>>> Adding different flag for the Open Drain/Open Source which is valid
>>> only when Single ended flag is enabled.
>>> if (single_ended) {
>>> - if (active_low)
>>> + if (open_drain)
>>
>> This breaks ACPI case, right?
> In acpi case, single_ended is not handled. It only handles the active LOW.
>
> From code:
Fair enough.
I would look into ACPI spec for possibility to add this kind of functionality.
Thanks.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v2 4/4] drm: zte: add VGA driver support
From: Sean Paul @ 2017-04-06 17:12 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree, Xin Zhou, Daniel Vetter, Baoyou Xie, dri-devel,
Rob Herring, Jun Nie
In-Reply-To: <1491490870-6330-5-git-send-email-shawnguo@kernel.org>
On Thu, Apr 06, 2017 at 11:01:10PM +0800, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> It adds VGA driver support, which needs to configure corresponding VOU
> interface in RGB_888 format, and thus the following changes are needed
> on zx_vou.
>
> - Rename the CSC block of Graphic Layer a bit to make it more specific,
> and add CSC of Channel to support RGB output.
> - Bypass Dither block for RGB output.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/zte/Makefile | 1 +
> drivers/gpu/drm/zte/zx_drm_drv.c | 1 +
> drivers/gpu/drm/zte/zx_drm_drv.h | 1 +
> drivers/gpu/drm/zte/zx_vga.c | 530 ++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/zte/zx_vga_regs.h | 36 +++
> drivers/gpu/drm/zte/zx_vou.c | 33 ++-
> drivers/gpu/drm/zte/zx_vou_regs.h | 12 +-
> 7 files changed, 610 insertions(+), 4 deletions(-)
> create mode 100644 drivers/gpu/drm/zte/zx_vga.c
> create mode 100644 drivers/gpu/drm/zte/zx_vga_regs.h
>
> diff --git a/drivers/gpu/drm/zte/Makefile b/drivers/gpu/drm/zte/Makefile
> index 01352b56c418..9df7766a7f9d 100644
> --- a/drivers/gpu/drm/zte/Makefile
> +++ b/drivers/gpu/drm/zte/Makefile
> @@ -3,6 +3,7 @@ zxdrm-y := \
> zx_hdmi.o \
> zx_plane.o \
> zx_tvenc.o \
> + zx_vga.o \
> zx_vou.o
>
> obj-$(CONFIG_DRM_ZTE) += zxdrm.o
> diff --git a/drivers/gpu/drm/zte/zx_drm_drv.c b/drivers/gpu/drm/zte/zx_drm_drv.c
> index 5c6944a1e72c..8a6892eeb44f 100644
> --- a/drivers/gpu/drm/zte/zx_drm_drv.c
> +++ b/drivers/gpu/drm/zte/zx_drm_drv.c
> @@ -248,6 +248,7 @@ static int zx_drm_remove(struct platform_device *pdev)
> &zx_crtc_driver,
> &zx_hdmi_driver,
> &zx_tvenc_driver,
> + &zx_vga_driver,
> &zx_drm_platform_driver,
> };
>
> diff --git a/drivers/gpu/drm/zte/zx_drm_drv.h b/drivers/gpu/drm/zte/zx_drm_drv.h
> index 5ca035b079c7..2a8cdc5f8be4 100644
> --- a/drivers/gpu/drm/zte/zx_drm_drv.h
> +++ b/drivers/gpu/drm/zte/zx_drm_drv.h
> @@ -14,6 +14,7 @@
> extern struct platform_driver zx_crtc_driver;
> extern struct platform_driver zx_hdmi_driver;
> extern struct platform_driver zx_tvenc_driver;
> +extern struct platform_driver zx_vga_driver;
>
> static inline u32 zx_readl(void __iomem *reg)
> {
> diff --git a/drivers/gpu/drm/zte/zx_vga.c b/drivers/gpu/drm/zte/zx_vga.c
> new file mode 100644
> index 000000000000..0d850d9ea700
> --- /dev/null
> +++ b/drivers/gpu/drm/zte/zx_vga.c
> @@ -0,0 +1,530 @@
> +/*
> + * Copyright (C) 2017 Sanechips Technology Co., Ltd.
> + * Copyright 2017 Linaro Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drmP.h>
> +
> +#include "zx_drm_drv.h"
> +#include "zx_vga_regs.h"
> +#include "zx_vou.h"
> +
> +struct zx_vga_pwrctrl {
> + struct regmap *regmap;
> + u32 reg;
> + u32 mask;
> +};
> +
> +struct zx_vga_i2c {
> + struct i2c_adapter adap;
> + struct mutex lock;
> +};
> +
> +struct zx_vga {
> + struct drm_connector connector;
> + struct drm_encoder encoder;
> + struct zx_vga_i2c *ddc;
> + struct device *dev;
> + void __iomem *mmio;
> + struct clk *i2c_wclk;
> + struct zx_vga_pwrctrl pwrctrl;
> + spinlock_t lock;
> + struct completion complete;
> + bool connected;
> +};
> +
> +#define to_zx_vga(x) container_of(x, struct zx_vga, x)
> +
> +static void zx_vga_encoder_enable(struct drm_encoder *encoder)
> +{
> + struct zx_vga *vga = to_zx_vga(encoder);
> + struct zx_vga_pwrctrl *pwrctrl = &vga->pwrctrl;
> +
> + /* Set bit to power up VGA DACs */
> + regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask,
> + pwrctrl->mask);
> +
> + vou_inf_enable(VOU_VGA, encoder->crtc);
> +}
> +
> +static void zx_vga_encoder_disable(struct drm_encoder *encoder)
> +{
> + struct zx_vga *vga = to_zx_vga(encoder);
> + struct zx_vga_pwrctrl *pwrctrl = &vga->pwrctrl;
> +
> + vou_inf_disable(VOU_VGA, encoder->crtc);
> +
> + /* Clear bit to power down VGA DACs */
> + regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, 0);
> +}
> +
> +static const struct drm_encoder_helper_funcs zx_vga_encoder_helper_funcs = {
> + .enable = zx_vga_encoder_enable,
> + .disable = zx_vga_encoder_disable,
> +};
> +
> +static const struct drm_encoder_funcs zx_vga_encoder_funcs = {
> + .destroy = drm_encoder_cleanup,
> +};
> +
> +static int zx_vga_connector_get_modes(struct drm_connector *connector)
> +{
> + struct zx_vga *vga = to_zx_vga(connector);
> + unsigned long flags;
> + struct edid *edid;
> + int ret;
> +
> + /*
> + * Clear both detection bits to switch I2C bus from device
> + * detecting to EDID reading.
> + */
> + spin_lock_irqsave(&vga->lock, flags);
> + zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, 0);
> + spin_unlock_irqrestore(&vga->lock, flags);
> +
> + edid = drm_get_edid(connector, &vga->ddc->adap);
> + if (!edid)
> + return 0;
> +
> + /*
> + * As edid reading succeeds, device must be connected, so we set
> + * up detection bit for unplug interrupt here.
> + */
> + spin_lock_irqsave(&vga->lock, flags);
> + zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, VGA_DETECT_SEL_HAS_DEVICE);
> + spin_unlock_irqrestore(&vga->lock, flags);
> +
> + drm_mode_connector_update_edid_property(connector, edid);
> + ret = drm_add_edid_modes(connector, edid);
> + kfree(edid);
> +
> + return ret;
> +}
> +
> +static enum drm_mode_status
> +zx_vga_connector_mode_valid(struct drm_connector *connector,
> + struct drm_display_mode *mode)
> +{
> + return MODE_OK;
> +}
> +
> +static struct drm_connector_helper_funcs zx_vga_connector_helper_funcs = {
> + .get_modes = zx_vga_connector_get_modes,
> + .mode_valid = zx_vga_connector_mode_valid,
> +};
> +
> +static enum drm_connector_status
> +zx_vga_connector_detect(struct drm_connector *connector, bool force)
> +{
> + struct zx_vga *vga = to_zx_vga(connector);
> +
> + return vga->connected ? connector_status_connected :
> + connector_status_disconnected;
> +}
> +
> +static const struct drm_connector_funcs zx_vga_connector_funcs = {
> + .dpms = drm_atomic_helper_connector_dpms,
> + .fill_modes = drm_helper_probe_single_connector_modes,
> + .detect = zx_vga_connector_detect,
> + .destroy = drm_connector_cleanup,
> + .reset = drm_atomic_helper_connector_reset,
> + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> +};
> +
> +static int zx_vga_register(struct drm_device *drm, struct zx_vga *vga)
> +{
> + struct drm_encoder *encoder = &vga->encoder;
> + struct drm_connector *connector = &vga->connector;
> + struct device *dev = vga->dev;
> + int ret;
> +
> + encoder->possible_crtcs = VOU_CRTC_MASK;
> +
> + ret = drm_encoder_init(drm, encoder, &zx_vga_encoder_funcs,
> + DRM_MODE_ENCODER_DAC, NULL);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "failed to init encoder: %d\n", ret);
> + return ret;
> + };
> +
> + drm_encoder_helper_add(encoder, &zx_vga_encoder_helper_funcs);
> +
> + vga->connector.polled = DRM_CONNECTOR_POLL_HPD;
> +
> + ret = drm_connector_init(drm, connector, &zx_vga_connector_funcs,
> + DRM_MODE_CONNECTOR_VGA);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "failed to init connector: %d\n", ret);
> + goto clean_encoder;
> + };
> +
> + drm_connector_helper_add(connector, &zx_vga_connector_helper_funcs);
> +
> + ret = drm_mode_connector_attach_encoder(connector, encoder);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "failed to attach encoder: %d\n", ret);
> + goto clean_connector;
> + };
> +
> + return 0;
> +
> +clean_connector:
> + drm_connector_cleanup(connector);
> +clean_encoder:
> + drm_encoder_cleanup(encoder);
> + return ret;
> +}
> +
> +static int zx_vga_pwrctrl_init(struct zx_vga *vga)
> +{
> + struct zx_vga_pwrctrl *pwrctrl = &vga->pwrctrl;
> + struct device *dev = vga->dev;
> + struct of_phandle_args out_args;
> + struct regmap *regmap;
> + int ret;
> +
> + ret = of_parse_phandle_with_fixed_args(dev->of_node,
> + "zte,vga-power-control", 2, 0, &out_args);
> + if (ret)
> + return ret;
> +
> + regmap = syscon_node_to_regmap(out_args.np);
> + if (IS_ERR(regmap)) {
> + ret = PTR_ERR(regmap);
> + goto out;
> + }
> +
> + pwrctrl->regmap = regmap;
> + pwrctrl->reg = out_args.args[0];
> + pwrctrl->mask = out_args.args[1];
> +
> +out:
> + of_node_put(out_args.np);
> + return ret;
> +}
> +
> +static int zx_vga_i2c_read(struct zx_vga *vga, struct i2c_msg *msg)
> +{
> + int len = msg->len;
> + u8 *buf = msg->buf;
> + u32 offset = 0;
> + int i;
> +
> + reinit_completion(&vga->complete);
> +
> + /* Select combo write */
> + zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_COMBO, VGA_CMD_COMBO);
> + zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_RW, 0);
> +
> + while (len > 0) {
> + u32 cnt;
> +
> + /* Clear RX FIFO */
> + zx_writel_mask(vga->mmio + VGA_RXF_CTRL, VGA_RX_FIFO_CLEAR,
> + VGA_RX_FIFO_CLEAR);
> +
> + /* Data offset to read from */
> + zx_writel(vga->mmio + VGA_SUB_ADDR, offset);
> +
> + /* Kick off the transfer */
> + zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_TRANS,
> + VGA_CMD_TRANS);
> +
> + if (!wait_for_completion_timeout(&vga->complete,
> + msecs_to_jiffies(1000))) {
> + DRM_DEV_ERROR(vga->dev, "transfer timeout\n");
> + return -ETIMEDOUT;
> + }
> +
> + cnt = zx_readl(vga->mmio + VGA_RXF_STATUS);
> + cnt = (cnt & VGA_RXF_COUNT_MASK) >> VGA_RXF_COUNT_SHIFT;
> + /* FIFO status may report more data than we need to read */
> + cnt = min_t(u32, len, cnt);
> +
> + for (i = 0; i < cnt; i++)
> + *buf++ = zx_readl(vga->mmio + VGA_DATA);
> +
> + len -= cnt;
> + offset += cnt;
> + }
> +
> + return 0;
> +}
> +
> +static int zx_vga_i2c_write(struct zx_vga *vga, struct i2c_msg *msg)
> +{
> + /*
> + * The DDC I2C adapter is only for reading EDID data, so we assume
> + * that the write to this adapter must be the EDID data offset.
> + */
> + if ((msg->len != 1) || ((msg->addr != DDC_ADDR)))
> + return -EINVAL;
> +
> + /* Hardware will take care of the slave address shifting */
> + zx_writel(vga->mmio + VGA_DEVICE_ADDR, msg->addr);
> +
> + return 0;
> +}
> +
> +static int zx_vga_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
> + int num)
> +{
> + struct zx_vga *vga = i2c_get_adapdata(adap);
> + struct zx_vga_i2c *ddc = vga->ddc;
> + int ret = 0;
> + int i;
> +
> + mutex_lock(&ddc->lock);
> +
> + for (i = 0; i < num; i++) {
> + if (msgs[i].flags & I2C_M_RD)
> + ret = zx_vga_i2c_read(vga, &msgs[i]);
> + else
> + ret = zx_vga_i2c_write(vga, &msgs[i]);
> +
> + if (ret < 0)
> + break;
> + }
> +
> + if (!ret)
> + ret = num;
> +
> + mutex_unlock(&ddc->lock);
> +
> + return ret;
> +}
> +
> +static u32 zx_vga_i2c_func(struct i2c_adapter *adapter)
> +{
> + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> +}
> +
> +static const struct i2c_algorithm zx_vga_algorithm = {
> + .master_xfer = zx_vga_i2c_xfer,
> + .functionality = zx_vga_i2c_func,
> +};
> +
> +static int zx_vga_ddc_register(struct zx_vga *vga)
> +{
> + struct device *dev = vga->dev;
> + struct i2c_adapter *adap;
> + struct zx_vga_i2c *ddc;
> + int ret;
> +
> + ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);
> + if (!ddc)
> + return -ENOMEM;
> +
> + vga->ddc = ddc;
> + mutex_init(&ddc->lock);
> +
> + adap = &ddc->adap;
> + adap->owner = THIS_MODULE;
> + adap->class = I2C_CLASS_DDC;
> + adap->dev.parent = dev;
> + adap->algo = &zx_vga_algorithm;
> + snprintf(adap->name, sizeof(adap->name), "zx vga i2c");
> +
> + ret = i2c_add_adapter(adap);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "failed to add I2C adapter: %d\n", ret);
> + return ret;
> + }
> +
> + i2c_set_adapdata(adap, vga);
> +
> + return 0;
> +}
> +
> +static irqreturn_t zx_vga_irq_thread(int irq, void *dev_id)
> +{
> + struct zx_vga *vga = dev_id;
> +
> + drm_helper_hpd_irq_event(vga->connector.dev);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t zx_vga_irq_handler(int irq, void *dev_id)
> +{
> + struct zx_vga *vga = dev_id;
> + u32 status;
> +
> + status = zx_readl(vga->mmio + VGA_I2C_STATUS);
> +
> + /* Clear interrupt status */
> + zx_writel_mask(vga->mmio + VGA_I2C_STATUS, VGA_CLEAR_IRQ,
> + VGA_CLEAR_IRQ);
> +
> + if (status & VGA_DEVICE_CONNECTED) {
> + /*
> + * Since VGA_DETECT_SEL bits need to be reset for switching DDC
> + * bus from device detection to EDID read, rather than setting
> + * up HAS_DEVICE bit here, we need to do that in .get_modes
> + * hook for unplug detecting after EDID read succeeds.
> + */
> + vga->connected = true;
> + return IRQ_WAKE_THREAD;
> + }
> +
> + if (status & VGA_DEVICE_DISCONNECTED) {
> + spin_lock(&vga->lock);
> + zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL,
> + VGA_DETECT_SEL_NO_DEVICE);
> + spin_unlock(&vga->lock);
I think you still have the race here. If you get a disconnect between get_edid
successfully finishing, and resetting the DETECT_SEL register, you will end up
with the device being disconnected and DETECT_SEL == VGA_DETECT_SEL_HAS_DEVICE.
In order to close this, you'll need to hold the lock across the edid read.
Sean
> + vga->connected = false;
> + return IRQ_WAKE_THREAD;
> + }
> +
> + if (status & VGA_TRANS_DONE) {
> + complete(&vga->complete);
> + return IRQ_HANDLED;
> + }
> +
> + return IRQ_NONE;
> +}
> +
> +static void zx_vga_hw_init(struct zx_vga *vga)
> +{
> + unsigned long ref = clk_get_rate(vga->i2c_wclk);
> + int div;
> +
> + /*
> + * Set up I2C fast speed divider per formula below to get 400kHz.
> + * scl = ref / ((div + 1) * 4)
> + */
> + div = DIV_ROUND_UP(ref / 1000, 400 * 4) - 1;
> + zx_writel(vga->mmio + VGA_CLK_DIV_FS, div);
> +
> + /* Set up device detection */
> + zx_writel(vga->mmio + VGA_AUTO_DETECT_PARA, 0x80);
> + zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, VGA_DETECT_SEL_NO_DEVICE);
> +
> + /*
> + * We need to poke monitor via DDC bus to get connection irq
> + * start working.
> + */
> + zx_writel(vga->mmio + VGA_DEVICE_ADDR, DDC_ADDR);
> + zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_TRANS, VGA_CMD_TRANS);
> +}
> +
> +static int zx_vga_bind(struct device *dev, struct device *master, void *data)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct drm_device *drm = data;
> + struct resource *res;
> + struct zx_vga *vga;
> + int irq;
> + int ret;
> +
> + vga = devm_kzalloc(dev, sizeof(*vga), GFP_KERNEL);
> + if (!vga)
> + return -ENOMEM;
> +
> + vga->dev = dev;
> + dev_set_drvdata(dev, vga);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + vga->mmio = devm_ioremap_resource(dev, res);
> + if (IS_ERR(vga->mmio))
> + return PTR_ERR(vga->mmio);
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0)
> + return irq;
> +
> + vga->i2c_wclk = devm_clk_get(dev, "i2c_wclk");
> + if (IS_ERR(vga->i2c_wclk)) {
> + ret = PTR_ERR(vga->i2c_wclk);
> + DRM_DEV_ERROR(dev, "failed to get i2c_wclk: %d\n", ret);
> + return ret;
> + }
> +
> + ret = zx_vga_pwrctrl_init(vga);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "failed to init power control: %d\n", ret);
> + return ret;
> + }
> +
> + ret = zx_vga_ddc_register(vga);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "failed to register ddc: %d\n", ret);
> + return ret;
> + }
> +
> + ret = zx_vga_register(drm, vga);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "failed to register vga: %d\n", ret);
> + return ret;
> + }
> +
> + init_completion(&vga->complete);
> + spin_lock_init(&vga->lock);
> +
> + ret = devm_request_threaded_irq(dev, irq, zx_vga_irq_handler,
> + zx_vga_irq_thread, IRQF_SHARED,
> + dev_name(dev), vga);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "failed to request threaded irq: %d\n", ret);
> + return ret;
> + }
> +
> + ret = clk_prepare_enable(vga->i2c_wclk);
> + if (ret)
> + return ret;
> +
> + zx_vga_hw_init(vga);
> +
> + return 0;
> +}
> +
> +static void zx_vga_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct zx_vga *vga = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(vga->i2c_wclk);
> +}
> +
> +static const struct component_ops zx_vga_component_ops = {
> + .bind = zx_vga_bind,
> + .unbind = zx_vga_unbind,
> +};
> +
> +static int zx_vga_probe(struct platform_device *pdev)
> +{
> + return component_add(&pdev->dev, &zx_vga_component_ops);
> +}
> +
> +static int zx_vga_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &zx_vga_component_ops);
> + return 0;
> +}
> +
> +static const struct of_device_id zx_vga_of_match[] = {
> + { .compatible = "zte,zx296718-vga", },
> + { /* end */ },
> +};
> +MODULE_DEVICE_TABLE(of, zx_vga_of_match);
> +
> +struct platform_driver zx_vga_driver = {
> + .probe = zx_vga_probe,
> + .remove = zx_vga_remove,
> + .driver = {
> + .name = "zx-vga",
> + .of_match_table = zx_vga_of_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/zte/zx_vga_regs.h b/drivers/gpu/drm/zte/zx_vga_regs.h
> new file mode 100644
> index 000000000000..feaa345fe6a6
> --- /dev/null
> +++ b/drivers/gpu/drm/zte/zx_vga_regs.h
> @@ -0,0 +1,36 @@
> +/*
> + * Copyright (C) 2017 Sanechips Technology Co., Ltd.
> + * Copyright 2017 Linaro Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __ZX_VGA_REGS_H__
> +#define __ZX_VGA_REGS_H__
> +
> +#define VGA_CMD_CFG 0x04
> +#define VGA_CMD_TRANS BIT(6)
> +#define VGA_CMD_COMBO BIT(5)
> +#define VGA_CMD_RW BIT(4)
> +#define VGA_SUB_ADDR 0x0c
> +#define VGA_DEVICE_ADDR 0x10
> +#define VGA_CLK_DIV_FS 0x14
> +#define VGA_RXF_CTRL 0x20
> +#define VGA_RX_FIFO_CLEAR BIT(7)
> +#define VGA_DATA 0x24
> +#define VGA_I2C_STATUS 0x28
> +#define VGA_DEVICE_DISCONNECTED BIT(7)
> +#define VGA_DEVICE_CONNECTED BIT(6)
> +#define VGA_CLEAR_IRQ BIT(4)
> +#define VGA_TRANS_DONE BIT(0)
> +#define VGA_RXF_STATUS 0x30
> +#define VGA_RXF_COUNT_SHIFT 2
> +#define VGA_RXF_COUNT_MASK GENMASK(7, 2)
> +#define VGA_AUTO_DETECT_PARA 0x34
> +#define VGA_AUTO_DETECT_SEL 0x38
> +#define VGA_DETECT_SEL_HAS_DEVICE BIT(1)
> +#define VGA_DETECT_SEL_NO_DEVICE BIT(0)
> +
> +#endif /* __ZX_VGA_REGS_H__ */
> diff --git a/drivers/gpu/drm/zte/zx_vou.c b/drivers/gpu/drm/zte/zx_vou.c
> index 2a2d90bd9425..cc5bdfc53e8e 100644
> --- a/drivers/gpu/drm/zte/zx_vou.c
> +++ b/drivers/gpu/drm/zte/zx_vou.c
> @@ -23,6 +23,7 @@
> #include <drm/drm_plane_helper.h>
> #include <drm/drmP.h>
>
> +#include "zx_common_regs.h"
> #include "zx_drm_drv.h"
> #include "zx_plane.h"
> #include "zx_vou.h"
> @@ -122,6 +123,8 @@ struct zx_crtc {
> struct drm_plane *primary;
> struct zx_vou_hw *vou;
> void __iomem *chnreg;
> + void __iomem *chncsc;
> + void __iomem *dither;
> const struct zx_crtc_regs *regs;
> const struct zx_crtc_bits *bits;
> enum vou_chn_type chn_type;
> @@ -204,6 +207,11 @@ struct vou_inf {
> .clocks_en_bits = BIT(15),
> .clocks_sel_bits = BIT(11) | BIT(0),
> },
> + [VOU_VGA] = {
> + .data_sel = VOU_RGB_888,
> + .clocks_en_bits = BIT(1),
> + .clocks_sel_bits = BIT(10),
> + },
> };
>
> static inline struct zx_vou_hw *crtc_to_vou(struct drm_crtc *crtc)
> @@ -227,9 +235,26 @@ void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc)
> struct zx_crtc *zcrtc = to_zx_crtc(crtc);
> struct zx_vou_hw *vou = zcrtc->vou;
> struct vou_inf *inf = &vou_infs[id];
> + void __iomem *dither = zcrtc->dither;
> + void __iomem *csc = zcrtc->chncsc;
> bool is_main = zcrtc->chn_type == VOU_CHN_MAIN;
> u32 data_sel_shift = id << 1;
>
> + if (inf->data_sel != VOU_YUV444) {
> + /* Enable channel CSC for RGB output */
> + zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK,
> + CSC_BT709_IMAGE_YCBCR2RGB << CSC_COV_MODE_SHIFT);
> + zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE,
> + CSC_WORK_ENABLE);
> +
> + /* Bypass Dither block for RGB output */
> + zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS,
> + DITHER_BYSPASS);
> + } else {
> + zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE, 0);
> + zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS, 0);
> + }
> +
> /* Select data format */
> zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift,
> inf->data_sel << data_sel_shift);
> @@ -502,20 +527,24 @@ static int zx_crtc_init(struct drm_device *drm, struct zx_vou_hw *vou,
>
> if (chn_type == VOU_CHN_MAIN) {
> zplane->layer = vou->osd + MAIN_GL_OFFSET;
> - zplane->csc = vou->osd + MAIN_CSC_OFFSET;
> + zplane->csc = vou->osd + MAIN_GL_CSC_OFFSET;
> zplane->hbsc = vou->osd + MAIN_HBSC_OFFSET;
> zplane->rsz = vou->otfppu + MAIN_RSZ_OFFSET;
> zplane->bits = &zx_gl_bits[0];
> zcrtc->chnreg = vou->osd + OSD_MAIN_CHN;
> + zcrtc->chncsc = vou->osd + MAIN_CHN_CSC_OFFSET;
> + zcrtc->dither = vou->osd + MAIN_DITHER_OFFSET;
> zcrtc->regs = &main_crtc_regs;
> zcrtc->bits = &main_crtc_bits;
> } else {
> zplane->layer = vou->osd + AUX_GL_OFFSET;
> - zplane->csc = vou->osd + AUX_CSC_OFFSET;
> + zplane->csc = vou->osd + AUX_GL_CSC_OFFSET;
> zplane->hbsc = vou->osd + AUX_HBSC_OFFSET;
> zplane->rsz = vou->otfppu + AUX_RSZ_OFFSET;
> zplane->bits = &zx_gl_bits[1];
> zcrtc->chnreg = vou->osd + OSD_AUX_CHN;
> + zcrtc->chncsc = vou->osd + AUX_CHN_CSC_OFFSET;
> + zcrtc->dither = vou->osd + AUX_DITHER_OFFSET;
> zcrtc->regs = &aux_crtc_regs;
> zcrtc->bits = &aux_crtc_bits;
> }
> diff --git a/drivers/gpu/drm/zte/zx_vou_regs.h b/drivers/gpu/drm/zte/zx_vou_regs.h
> index c066ef123434..5a218351b497 100644
> --- a/drivers/gpu/drm/zte/zx_vou_regs.h
> +++ b/drivers/gpu/drm/zte/zx_vou_regs.h
> @@ -13,13 +13,17 @@
>
> /* Sub-module offset */
> #define MAIN_GL_OFFSET 0x130
> -#define MAIN_CSC_OFFSET 0x580
> +#define MAIN_GL_CSC_OFFSET 0x580
> +#define MAIN_CHN_CSC_OFFSET 0x6c0
> #define MAIN_HBSC_OFFSET 0x820
> +#define MAIN_DITHER_OFFSET 0x960
> #define MAIN_RSZ_OFFSET 0x600 /* OTFPPU sub-module */
>
> #define AUX_GL_OFFSET 0x200
> -#define AUX_CSC_OFFSET 0x5d0
> +#define AUX_GL_CSC_OFFSET 0x5d0
> +#define AUX_CHN_CSC_OFFSET 0x710
> #define AUX_HBSC_OFFSET 0x860
> +#define AUX_DITHER_OFFSET 0x970
> #define AUX_RSZ_OFFSET 0x800
>
> #define OSD_VL0_OFFSET 0x040
> @@ -78,6 +82,10 @@
> #define CHN_INTERLACE_BUF_CTRL 0x24
> #define CHN_INTERLACE_EN BIT(2)
>
> +/* Dither registers */
> +#define OSD_DITHER_CTRL0 0x00
> +#define DITHER_BYSPASS BIT(31)
> +
> /* TIMING_CTRL registers */
> #define TIMING_TC_ENABLE 0x04
> #define AUX_TC_EN BIT(1)
> --
> 1.9.1
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate calculation
From: Laxman Dewangan @ 2017-04-06 17:03 UTC (permalink / raw)
To: Thierry Reding
Cc: robh+dt, jonathanh, mark.rutland, linux-pwm, devicetree,
linux-tegra, linux-kernel
In-Reply-To: <20170406162417.GB19312@ulmo.ba.sec>
[-- Attachment #1: Type: text/plain, Size: 783 bytes --]
On Thursday 06 April 2017 09:54 PM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Thu, Apr 06, 2017 at 07:50:59PM +0530, Laxman Dewangan wrote:
>> The rate of the PWM calculated as follows:
>> hz = NSEC_PER_SEC / period_ns;
>> rate = (rate + (hz / 2)) / hz;
>>
>> This has the precision loss in lower PWM rate.
>> Changing this to have more precision as:
>> hz = DIV_ROUND_CLOSE(NSEC_PER_SEC * 100, period_ns);
>> rate = DIV_ROUND_CLOSE(rate * 100, hz)
> DIV_ROUND_CLOSEST(). And I much prefer this to the actual code below. I
> don't think it's necessary to have a local variable for the precision.
Do you suggest to use DIV_ROUND_CLOSEST() instead of
DIV_ROUND_CLOSEST_ULL()?
This is ULL division and so we need to use this one.
Or am I missing something
[-- Attachment #2: Type: text/html, Size: 1288 bytes --]
^ permalink raw reply
* [PATCH] ARM: dts: aspeed: add a fastread property
From: Cédric Le Goater @ 2017-04-06 17:02 UTC (permalink / raw)
To: Joel Stanley
Cc: Mark Rutland, devicetree, Russell King, Rob Herring,
Cédric Le Goater, linux-arm-kernel
All chips on OpenPOWER platforms support the fastread SPI command.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 ++
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 2 ++
arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 2 ++
3 files changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index 8f82e8ab1875..7c90dac99822 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -24,6 +24,7 @@
status = "okay";
flash@0 {
status = "okay";
+ m25p,fast-read;
label = "bmc";
};
};
@@ -32,6 +33,7 @@
status = "okay";
flash@0 {
status = "okay";
+ m25p,fast-read;
label = "pnor";
};
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index aab1889f702f..112551766275 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -35,6 +35,7 @@
status = "okay";
flash@0 {
status = "okay";
+ m25p,fast-read;
label = "bmc";
};
};
@@ -43,6 +44,7 @@
status = "okay";
flash@0 {
status = "okay";
+ m25p,fast-read;
label = "pnor";
};
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index e3c6358bc7d9..b82f67eb3dae 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -35,6 +35,7 @@
status = "okay";
flash@0 {
status = "okay";
+ m25p,fast-read;
label = "bmc";
};
};
@@ -43,6 +44,7 @@
status = "okay";
flash@0 {
status = "okay";
+ m25p,fast-read;
label = "pnor";
};
};
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH 1/1] gpio: core: Decouple open drain/source flag with active low/high
From: Laxman Dewangan @ 2017-04-06 16:56 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Linus Walleij, Alexandre Courbot, Rob Herring, Mark Rutland,
Frank Rowand, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree
In-Reply-To: <CAHp75Ver7n=Xoer0YzA0sVVrcXKOB1bDz0ygSm0V0YoyYbe3pg@mail.gmail.com>
On Thursday 06 April 2017 09:40 PM, Andy Shevchenko wrote:
> On Thu, Apr 6, 2017 at 4:35 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote:
>> Currently, the GPIO interface is said to Open Drain if it is Single
>> Ended and active LOW. Similarly, it is said as Open Source if it is
>> Single Ended and active HIGH.
>>
>> The active HIGH/LOW is used in the interface for setting the pin
>> state to HIGH or LOW when enabling/disabling the interface.
>>
>> In Open Drain interface, pin is set to HIGH by putting pin in
>> high impedance and LOW by driving to the LOW.
>>
>> In Open Source interface, pin is set to HIGH by driving pin to
>> HIGH and set to LOW by putting pin in high impedance.
>>
>> With above, the Open Drain/Source is unrelated to the active LOW/HIGH
>> in interface. There is interface where the enable/disable of interface
>> is ether active LOW or HIGH but it is Open Drain type.
>>
>> Hence decouple the Open Drain with Single Ended + Active LOW and
>> Open Source with Single Ended + Active HIGH.
>>
>> Adding different flag for the Open Drain/Open Source which is valid
>> only when Single ended flag is enabled.
>> if (single_ended) {
>> - if (active_low)
>> + if (open_drain)
> This breaks ACPI case, right?
>
In acpi case, single_ended is not handled. It only handles the active LOW.
From code:
bool active_low = false;
bool single_ended = false;
int ret;
if (!fwnode)
return ERR_PTR(-EINVAL);
if (is_of_node(fwnode)) {
enum of_gpio_flags flags;
desc = of_get_named_gpiod_flags(to_of_node(fwnode),
propname,
index, &flags);
if (!IS_ERR(desc)) {
active_low = flags & OF_GPIO_ACTIVE_LOW;
single_ended = flags & OF_GPIO_SINGLE_ENDED;
}
} else if (is_acpi_node(fwnode)) {
struct acpi_gpio_info info;
desc = acpi_node_get_gpiod(fwnode, propname, index, &info);
if (!IS_ERR(desc))
active_low = info.polarity == GPIO_ACTIVE_LOW;
}
^ permalink raw reply
* Re: [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume
From: Laxman Dewangan @ 2017-04-06 16:48 UTC (permalink / raw)
To: Jon Hunter, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: mark.rutland-5wv7dgnIgG8, linux-pwm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <f43c83a9-8ae0-73b0-d41d-97d3bc6c253e-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Thursday 06 April 2017 08:56 PM, Jon Hunter wrote:
> On 06/04/17 15:21, Laxman Dewangan wrote:
>> In some of NVIDIA Tegra's platform, PWM controller is used to
>> control the PWM controlled regulators. PWM signal is connected to
>> the VID pin of the regulator where duty cycle of PWM signal decide
>> the voltage level of the regulator output.
>>
>> The tristate (high impedance of PWM pin form Tegra) also define
> s/form/from/
> s/define/defines/
>
>> one of the state of PWM regulator which needs to be configure in
>> suspend state of system.
> It maybe clearer to say that when the system enters suspend the
> regulator requires the pwm output to be tristated.
Not necessarily that every PWM regulator interfaces needs it. It
depends on the devices.
So I will say:
When system enters suspend, in some of PWM regulator interface, it is
required to to set the PWM output to be tristated.
> pwm: pwm@7000a000 {
> @@ -29,3 +42,33 @@ Example:
> resets = <&tegra_car 17>;
> reset-names = "pwm";
> };
> +
> +
> +Example with the pin configuration for suspend and resume:
> +=========================================================
> +Pin PE7 is used as PWM interface.
> Nit-pick. On what devices? Sounds like this is verbatim. Maybe state
> what device this is an example for.
Let me phrase it as:
Suppose pin PE7 (On tegra210) interfaced with the regulator device and
this requires PWM output to be tristated when system enters suspend.
Following will be DT binding to achieve this:
^ permalink raw reply
* Re: [PATCH V4 4/4] pwm: tegra: Add support to configure pin state in suspends/resume
From: Laxman Dewangan @ 2017-04-06 16:40 UTC (permalink / raw)
To: Jon Hunter, thierry.reding, robh+dt
Cc: mark.rutland, linux-pwm, devicetree, linux-tegra, linux-kernel
In-Reply-To: <e6eef15a-45e4-002b-dd45-38c268070241@nvidia.com>
Oops, it was actually v2.
On Thursday 06 April 2017 08:47 PM, Jon Hunter wrote:
> On 06/04/17 15:21, Laxman Dewangan wrote:
>> In some of NVIDIA Tegra's platform, PWM controller is used to
>> control the PWM controlled regulators. PWM signal is connected to
>> the VID pin of the regulator where duty cycle of PWM signal decide
>> the voltage level of the regulator output.
>>
>> The tristate (high impedance of PWM pin form Tegra) also define
>> one of the state of PWM regulator which needs to be configure in
>> suspend state of system.
>>
>> Add support to configure the pin state via pinctrl frameworks in
>> suspend and active state of the system.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>> ---
>> Changes from v1:
>> - Use standard pinctrl names for sleep and active state.
>> - Use API pinctrl_pm_select_*()
>>
>> drivers/pwm/pwm-tegra.c | 22 ++++++++++++++++++++++
>> 1 file changed, 22 insertions(+)
>>
>> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
>> index e9c4de5..af1bd4f 100644
>> --- a/drivers/pwm/pwm-tegra.c
>> +++ b/drivers/pwm/pwm-tegra.c
>> @@ -29,6 +29,7 @@
>> #include <linux/of_device.h>
>> #include <linux/pwm.h>
>> #include <linux/platform_device.h>
>> +#include <linux/pinctrl/consumer.h>
>> #include <linux/slab.h>
>> #include <linux/reset.h>
>>
>> @@ -256,6 +257,22 @@ static int tegra_pwm_remove(struct platform_device *pdev)
>> return pwmchip_remove(&pc->chip);
>> }
>>
>> +#ifdef CONFIG_PM_SLEEP
>> +static int tegra_pwm_suspend(struct device *dev)
>> +{
>> + pinctrl_pm_select_sleep_state(dev);
> Why not return the error code here?
As the pin state in suspend is optional, I dont want to return error if
the sleep state is not available.
However, it seems pinctrl take care of retuning success if there is no
sleep state. By seeing code.
Let me test this on different condition and it it works fine then we can
return the return of pinctrl_pm_select_*()
BTW, it should be OK to have pwm_tegra_resume/suspend wrapper, not
directly use the pinctrl_pm_select_* in pm ops suspend/resume. The
prototype matches.
>
> By the way, do you plan to include patches to populate the bindings for
> the pwm devices?
I am planning to populate the GPU regulator which is PWM based. This
will only populate the regulator.
^ permalink raw reply
* Re: [PATCH V2 1/4] pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation
From: Thierry Reding @ 2017-04-06 16:28 UTC (permalink / raw)
To: Laxman Dewangan
Cc: robh+dt, jonathanh, mark.rutland, linux-pwm, devicetree,
linux-tegra, linux-kernel
In-Reply-To: <1491488461-24621-2-git-send-email-ldewangan@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 934 bytes --]
On Thu, Apr 06, 2017 at 07:50:58PM +0530, Laxman Dewangan wrote:
> Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closet one
"closest"
Thierry
> instead of implementing the same locally. This increase readability.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> ---
> Changes from V1:
> None
>
> drivers/pwm/pwm-tegra.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> index e464784..0a688da 100644
> --- a/drivers/pwm/pwm-tegra.c
> +++ b/drivers/pwm/pwm-tegra.c
> @@ -85,8 +85,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> * nearest integer during division.
> */
> c *= (1 << PWM_DUTY_WIDTH);
> - c += period_ns / 2;
> - do_div(c, period_ns);
> + c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
>
> val = (u32)c << PWM_DUTY_SHIFT;
>
> --
> 2.1.4
>
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^ permalink raw reply
* Re: [PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate calculation
From: Thierry Reding @ 2017-04-06 16:28 UTC (permalink / raw)
To: Laxman Dewangan
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, jonathanh-DDmLM1+adcrQT0dZR+AlfA,
mark.rutland-5wv7dgnIgG8, linux-pwm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1491488461-24621-3-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 2591 bytes --]
On Thu, Apr 06, 2017 at 07:50:59PM +0530, Laxman Dewangan wrote:
> The rate of the PWM calculated as follows:
> hz = NSEC_PER_SEC / period_ns;
> rate = (rate + (hz / 2)) / hz;
>
> This has the precision loss in lower PWM rate.
> Changing this to have more precision as:
> hz = DIV_ROUND_CLOSE(NSEC_PER_SEC * 100, period_ns);
> rate = DIV_ROUND_CLOSE(rate * 100, hz)
DIV_ROUND_CLOSEST(). Also I very much prefer this notation over the
actual code below. I don't think we need a local variable to hold the
precision.
Thierry
> Example:
> 1. period_ns = 16672000, PWM clock rate is 200KHz.
> Based on old formula
> hz = NSEC_PER_SEC / period_ns
> = 1000000000ul/16672000
> = 59 (59.98)
> rate = (200K + 59/2)/59 = 3390
>
> Based on new method:
> hz = 5998
> rate = DIV_ROUND_CLOSE(200000*100, 5998) = 3334
>
> If we measure the PWM signal rate, we will get more accurate period
> with rate value of 3334 instead of 3390.
>
> 2. period_ns = 16803898, PWM clock rate is 200KHz.
> Based on old formula:
> hz = 60, rate = 3333
> Based on new formula:
> hz = 5951, rate = 3360
>
> The rate of 3360 is more near to requested period then the 3333.
>
> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> Changes from V1:
> - None
>
> drivers/pwm/pwm-tegra.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> index 0a688da..e9c4de5 100644
> --- a/drivers/pwm/pwm-tegra.c
> +++ b/drivers/pwm/pwm-tegra.c
> @@ -76,6 +76,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
> unsigned long long c = duty_ns;
> unsigned long rate, hz;
> + unsigned long long ns100 = NSEC_PER_SEC;
> + unsigned long precision = 100; /* Consider 2 digit precision */
> u32 val = 0;
> int err;
>
> @@ -94,9 +96,11 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> * cycles at the PWM clock rate will take period_ns nanoseconds.
> */
> rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
> - hz = NSEC_PER_SEC / period_ns;
>
> - rate = (rate + (hz / 2)) / hz;
> + /* Consider precision in PWM_SCALE_WIDTH rate calculation */
> + ns100 *= precision;
> + hz = DIV_ROUND_CLOSEST_ULL(ns100, period_ns);
> + rate = DIV_ROUND_CLOSEST(rate * precision, hz);
>
> /*
> * Since the actual PWM divider is the register's frequency divider
> --
> 2.1.4
>
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^ permalink raw reply
* Re: [PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate calculation
From: Thierry Reding @ 2017-04-06 16:24 UTC (permalink / raw)
To: Laxman Dewangan
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, jonathanh-DDmLM1+adcrQT0dZR+AlfA,
mark.rutland-5wv7dgnIgG8, linux-pwm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1491488461-24621-3-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 2584 bytes --]
On Thu, Apr 06, 2017 at 07:50:59PM +0530, Laxman Dewangan wrote:
> The rate of the PWM calculated as follows:
> hz = NSEC_PER_SEC / period_ns;
> rate = (rate + (hz / 2)) / hz;
>
> This has the precision loss in lower PWM rate.
> Changing this to have more precision as:
> hz = DIV_ROUND_CLOSE(NSEC_PER_SEC * 100, period_ns);
> rate = DIV_ROUND_CLOSE(rate * 100, hz)
DIV_ROUND_CLOSEST(). And I much prefer this to the actual code below. I
don't think it's necessary to have a local variable for the precision.
Thierry
> Example:
> 1. period_ns = 16672000, PWM clock rate is 200KHz.
> Based on old formula
> hz = NSEC_PER_SEC / period_ns
> = 1000000000ul/16672000
> = 59 (59.98)
> rate = (200K + 59/2)/59 = 3390
>
> Based on new method:
> hz = 5998
> rate = DIV_ROUND_CLOSE(200000*100, 5998) = 3334
>
> If we measure the PWM signal rate, we will get more accurate period
> with rate value of 3334 instead of 3390.
>
> 2. period_ns = 16803898, PWM clock rate is 200KHz.
> Based on old formula:
> hz = 60, rate = 3333
> Based on new formula:
> hz = 5951, rate = 3360
>
> The rate of 3360 is more near to requested period then the 3333.
>
> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> Changes from V1:
> - None
>
> drivers/pwm/pwm-tegra.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> index 0a688da..e9c4de5 100644
> --- a/drivers/pwm/pwm-tegra.c
> +++ b/drivers/pwm/pwm-tegra.c
> @@ -76,6 +76,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
> unsigned long long c = duty_ns;
> unsigned long rate, hz;
> + unsigned long long ns100 = NSEC_PER_SEC;
> + unsigned long precision = 100; /* Consider 2 digit precision */
> u32 val = 0;
> int err;
>
> @@ -94,9 +96,11 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> * cycles at the PWM clock rate will take period_ns nanoseconds.
> */
> rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
> - hz = NSEC_PER_SEC / period_ns;
>
> - rate = (rate + (hz / 2)) / hz;
> + /* Consider precision in PWM_SCALE_WIDTH rate calculation */
> + ns100 *= precision;
> + hz = DIV_ROUND_CLOSEST_ULL(ns100, period_ns);
> + rate = DIV_ROUND_CLOSEST(rate * precision, hz);
>
> /*
> * Since the actual PWM divider is the register's frequency divider
> --
> 2.1.4
>
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^ permalink raw reply
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