* Re: [PATCH v3 02/20] net: stmmac: add optional setup function
From: Corentin Labbe @ 2017-04-07 12:51 UTC (permalink / raw)
To: Giuseppe CAVALLARO
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, alexandre.torgue-qxv4g6HH51o,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
netdev-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <262f763b-d158-dd77-3dba-1d7b90a1eef9-qxv4g6HH51o@public.gmane.org>
On Mon, Apr 03, 2017 at 02:32:33PM +0200, Giuseppe CAVALLARO wrote:
> Hello Corentin
>
> On 4/3/2017 11:14 AM, Corentin Labbe wrote:
> > Instead of adding more ifthen logic for adding a new mac_device_info
> > setup function, it is easier to add a function pointer to the function
> > needed.
> >
> > Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > ---
> > drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 +++-
> > include/linux/stmmac.h | 3 +++
> > 2 files changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > index 43361f3..3beca41 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > @@ -3508,7 +3508,9 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
> > struct mac_device_info *mac;
> >
> > /* Identify the MAC HW device */
> > - if (priv->plat->has_gmac) {
> > + if (priv->plat->setup) {
> > + mac = priv->plat->setup(priv);
> > + } else if (priv->plat->has_gmac) {
> > priv->dev->priv_flags |= IFF_UNICAST_FLT;
> > mac = dwmac1000_setup(priv->ioaddr,
> > priv->plat->multicast_filter_bins,
> > diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
> > index 3921cb9..dadd74b 100644
> > --- a/include/linux/stmmac.h
> > +++ b/include/linux/stmmac.h
> > @@ -144,6 +144,8 @@ struct stmmac_txq_cfg {
> > u32 prio;
> > };
> >
> > +struct stmmac_priv;
> > +
> > struct plat_stmmacenet_data {
> > int bus_id;
> > int phy_addr;
> > @@ -177,6 +179,7 @@ struct plat_stmmacenet_data {
> > void (*fix_mac_speed)(void *priv, unsigned int speed);
> > int (*init)(struct platform_device *pdev, void *priv);
> > void (*exit)(struct platform_device *pdev, void *priv);
> > + struct mac_device_info *(*setup)(struct stmmac_priv *priv);
>
> In that case I prefer to have void *priv as done for the other callbacks.
> I mean, keep the priv struct inside the driver part.
>
Agree, I will change it
Thanks
Regards
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^ permalink raw reply
* Re: [PATCH 1/2] leds: Add driver for Qualcomm LPG
From: Pavel Machek @ 2017-04-07 12:54 UTC (permalink / raw)
To: Jacek Anaszewski
Cc: Bjorn Andersson, Rob Herring, Richard Purdie,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-leds-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <bf999f34-4509-6f0b-602c-f82d50a18e97-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1199 bytes --]
Hi!
> > Second, there are more issues than just patterns with the RGB
> > LED. Most important is ability to set particular colors. You want to
> > set the RGB LED to "white", but that does not mean you can set
> > red=green=blue=1.0. You want color to look the same on LCD and on the
> > LED, which means coefficients for white and some kind of function for
> > brightness-to-PWM conversion.
>
> Shouldn't we leave that entirely to the userspace? Can we come up
> with coefficients that will guarantee the same result on all existing
> LCD devices?
I don't think we should. We want (red = 70%, green = 80%, blue = 20%)
to look approximately the same on all the hardware. That's currently
not the case; even (red = green = blue = 100%) is not white.
I believe easiest solution is "the kernel does the work", as it does
for LCD screens.
[Now... as long as userspace has enough information to display white
and specific colors, I don't care much -- having kernel present
coefficients for userspace would work, too.]
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: drm: rcar-du: Document optional reset properties
From: Laurent Pinchart @ 2017-04-07 12:55 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Geert Uytterhoeven, David Airlie, Mark Rutland,
Philipp Zabel, DRI Development, Linux-Renesas,
devicetree@vger.kernel.org
In-Reply-To: <CAMuHMdU0=WfkUUjXTYpp4JWM4mzFcV3AwSwf_7p+YnQQh=uE-w@mail.gmail.com>
Hi Geert and Rob,
On Thursday 16 Mar 2017 21:59:04 Geert Uytterhoeven wrote:
> On Thu, Mar 16, 2017 at 9:56 PM, Rob Herring <robh@kernel.org> wrote:
> > On Thu, Mar 16, 2017 at 09:13:16AM +0100, Geert Uytterhoeven wrote:
> >> On Wed, Mar 15, 2017 at 6:01 PM, Rob Herring <robh@kernel.org> wrote:
> >>> On Mon, Mar 06, 2017 at 05:25:56PM +0100, Geert Uytterhoeven wrote:
> >>>> Document the optional properties for describing module resets, to
> >>>> support resetting display channels and LVDS encoders on R-Car Gen2 and
> >>>> Gen3.
> >>>>
> >>>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >>>> ---
> >>>> See "[v2,1/4] dt-bindings: clock: renesas: cpg-mssr: Document reset
> >>>> control support" (https://patchwork.kernel.org/patch/9536627/) for the
> >>>> format of a reset specifier in the Renesas CPG/MSSR case.
> >>>>
> >>>> E.g. "resets = <&cpg 310>;"
> >>>>
> >>>> v2:
> >>>> - s/phandles/phandle/.
> >>>>
> >>>> ---
> >>>>
> >>>> Documentation/devicetree/bindings/display/renesas,du.txt | 10 ++++++++
> >>>> 1 file changed, 10 insertions(+)
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt
> >>>> b/Documentation/devicetree/bindings/display/renesas,du.txt index
> >>>> 1a02f099a0ff0a3a..3db418c827193e82 100644
> >>>> --- a/Documentation/devicetree/bindings/display/renesas,du.txt
> >>>> +++ b/Documentation/devicetree/bindings/display/renesas,du.txt
> >>>> @@ -36,6 +36,16 @@ Required Properties:
> >>>> When supplied they must be named "dclkin.x" with "x" being the
> >>>> input clock numerical index.
> >>>>
> >>>> +Optional properties:
> >>>> + - resets: A list of phandle + reset-specifier pairs, one for each
> >>>> entry in
> >>>> + the reset-names property.
> >>>> + - reset-names: Names of the resets. This property is
> >>>> model-dependent.
> >>>> + - R8A779[0123456] use one reset for a group of one or more
> >>>> successive
> >>>> + channels, and one reset per LVDS encoder (if available). The
> >>>> resets
> >>>> + must be named "du.x" with "x" being the numerical index of the
> >>>> lowest
> >>>> + channel in the group. The LVDS resets must be named "lvds.x"
> >>>> with "x"
> >>>> + being the LVDS encoder numerical index.
> >>>
> >>> LVDS is not a separate block?
> >>
> >> Well... from a hardware point of view, the LVDS encoders and DU channels
> >> are all separate blocks (they have separate reg blocks, clocks, and
> >> resets). But due to the dependencies between the blocks, they're modeled
> >> in DT as a single device, with multiple reg, clocks, and resets
> >> properties.
> >
> > Dependencies being DRM requirement of wanting a single device with
> > sub-devices or some h/w dependencies? The former shouldn't define your
> > binding.
>
> Hardware dependencies. Laurent can tell you more about them (when he'll
> be back).
I believe we could model the LVDS encoder as a separate DT node. It was
probably a historical mistake (that would however need to be confirmed, I
haven't double-checked all details). Obviously I can't break backward
compatibility, so we're kind of stuck :-S
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH v2 0/4] pinctrl: aspeed: Add initial pinconf support
From: Andrew Jeffery @ 2017-04-07 12:57 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Jeffery, Rob Herring, Joel Stanley, Benjamin Herrenschmidt,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ
Hi Linus,
v2 breaks the pinconf patch for the Aspeed pin controller out into a series,
adding explicit documentation to the devicetree bindings and breaking out
changes to the core from those to the SoC drivers.
The changes also address review comments from Joel.
Cheers,
Andrew
Andrew Jeffery (4):
pinctrl: aspeed: Document pinconf in devicetree bindings
pinctrl: aspeed: Add core pinconf support
pinctrl: aspeed: g4: Add pinconf support
pinctrl: aspeed: g5: Add pinconf support
.../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 40 +++-
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 117 +++++++++++-
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 153 ++++++++++++++-
drivers/pinctrl/aspeed/pinctrl-aspeed.c | 211 +++++++++++++++++++++
drivers/pinctrl/aspeed/pinctrl-aspeed.h | 28 +++
5 files changed, 538 insertions(+), 11 deletions(-)
--
2.9.3
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^ permalink raw reply
* [PATCH v2 1/4] pinctrl: aspeed: Document pinconf in devicetree bindings
From: Andrew Jeffery @ 2017-04-07 12:57 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Jeffery, Rob Herring, Joel Stanley, Benjamin Herrenschmidt,
linux-gpio, devicetree, linux-kernel, openbmc
In-Reply-To: <20170407125713.15678-1-andrew@aj.id.au>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
.../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 40 +++++++++++++++++-----
1 file changed, 31 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
index b98e6f030da8..ca01710ee29a 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -34,13 +34,28 @@ Documentation/devicetree/bindings/mfd/syscon.txt
Subnode Format
==============
-The required properties of child nodes are (as defined in pinctrl-bindings):
-- function
-- groups
+The required properties of pinmux child nodes are:
+- function: the mux function to select
+- groups : the list of groups to select with this function
-Each function has only one associated pin group. Each group is named by its
-function. The following values for the function and groups properties are
-supported:
+Required properties of pinconf child nodes are:
+- groups: A list of groups to select (either this or "pins" must be
+ specified)
+- pins : A list of ball names as strings, eg "D14" (either this or "groups"
+ must be specified)
+
+Optional properties of pinconf child nodes are:
+- bias-disable : disable any pin bias
+- bias-pull-down: pull down the pin
+- drive-strength: sink or source at most X mA
+
+Definitions are as specified in
+Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt, with any
+further limitations as described above.
+
+For pinmux, each mux function has only one associated pin group. Each group is
+named by its function. The following values for the function and groups
+properties are supported:
aspeed,ast2400-pinctrl, aspeed,g4-pinctrl:
@@ -90,6 +105,11 @@ syscon: scu@1e6e2000 {
function = "I2C3";
groups = "I2C3";
};
+
+ pinctrl_gpioh0_unbiased_default: gpioh0 {
+ pins = "A8";
+ bias-disable;
+ };
};
};
@@ -110,6 +130,11 @@ ahb {
function = "I2C3";
groups = "I2C3";
};
+
+ pinctrl_gpioh0_unbiased_default: gpioh0 {
+ pins = "A18";
+ bias-disable;
+ };
};
};
@@ -143,6 +168,3 @@ ahb {
};
};
};
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices.
--
2.9.3
^ permalink raw reply related
* [PATCH v2 2/4] pinctrl: aspeed: Add core pinconf support
From: Andrew Jeffery @ 2017-04-07 12:57 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Jeffery, Rob Herring, Joel Stanley, Benjamin Herrenschmidt,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20170407125713.15678-1-andrew-zrmu5oMJ5Fs@public.gmane.org>
Several pinconf parameters have a fairly straight-forward mapping onto
the Aspeed pin controller. These include management of pull-down bias,
drive-strength, and some debounce configuration.
Pin biasing largely is managed on a per-GPIO-bank basis, aside from the
ADC and RMII/RGMII pins. As the bias configuration for each pin in a
bank maps onto a single per-bank bit, configuration tables will be
introduced to describe the ranges of pins and the supported pinconf
parameter. The use of tables also helps with the sparse support of
pinconf properties, and the fact that not all GPIO banks support
biasing or drive-strength configuration.
Further, as the pin controller uses a consistent approach for bias and
drive strength configuration at the register level, a second table is
defined for looking up the the bit-state required to enable or query the
provided configuration.
Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto
system, and pinctrl-aspeed-g5 on an AST2500EVB as well as under QEMU.
The test method was to set the appropriate bits via devmem and verify
the result through the controller's pinconf-pins debugfs file. This
simultaneously validates the get() path and half of the set() path. The
remainder of the set() path was validated by configuring a handful of
pins via the devicetree with the supported pinconf properties and
verifying the appropriate registers were touched.
Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
---
drivers/pinctrl/aspeed/pinctrl-aspeed.c | 211 ++++++++++++++++++++++++++++++++
drivers/pinctrl/aspeed/pinctrl-aspeed.h | 28 +++++
2 files changed, 239 insertions(+)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
index 76f62bd45f02..3dcf82533bef 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
@@ -537,3 +537,214 @@ int aspeed_pinctrl_probe(struct platform_device *pdev,
return 0;
}
+
+static inline bool pin_in_config_range(unsigned int offset,
+ const struct aspeed_pin_config *config)
+{
+ return offset >= config->pins[0] && offset <= config->pins[1];
+}
+
+static inline const struct aspeed_pin_config *find_pinconf_config(
+ const struct aspeed_pinctrl_data *pdata,
+ unsigned int offset,
+ enum pin_config_param param)
+{
+ unsigned int i;
+
+ for (i = 0; i < pdata->nconfigs; i++) {
+ if (param == pdata->configs[i].param &&
+ pin_in_config_range(offset, &pdata->configs[i]))
+ return &pdata->configs[i];
+ }
+
+ return NULL;
+}
+
+/**
+ * @param: pinconf configuration parameter
+ * @arg: The supported argument for @param, or -1 if any value is supported
+ * @value: The register value to write to configure @arg for @param
+ *
+ * The map is to be used in conjunction with the configuration array supplied
+ * by the driver implementation.
+ */
+struct aspeed_pin_config_map {
+ enum pin_config_param param;
+ s32 arg;
+ u32 val;
+};
+
+enum aspeed_pin_config_map_type { MAP_TYPE_ARG, MAP_TYPE_VAL };
+
+/* Aspeed consistently both:
+ *
+ * 1. Defines "disable bits" for internal pull-downs
+ * 2. Uses 8mA or 16mA drive strengths
+ */
+static const struct aspeed_pin_config_map pin_config_map[] = {
+ { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0 },
+ { PIN_CONFIG_BIAS_DISABLE, -1, 1 },
+ { PIN_CONFIG_DRIVE_STRENGTH, 8, 0 },
+ { PIN_CONFIG_DRIVE_STRENGTH, 16, 1 },
+};
+
+static const struct aspeed_pin_config_map *find_pinconf_map(
+ enum pin_config_param param,
+ enum aspeed_pin_config_map_type type,
+ s64 value)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pin_config_map); i++) {
+ const struct aspeed_pin_config_map *elem;
+ bool match;
+
+ elem = &pin_config_map[i];
+
+ switch (type) {
+ case MAP_TYPE_ARG:
+ match = (elem->arg == -1 || elem->arg == value);
+ break;
+ case MAP_TYPE_VAL:
+ match = (elem->val == value);
+ break;
+ }
+
+ if (param == elem->param && match)
+ return elem;
+ }
+
+ return NULL;
+}
+
+int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
+ unsigned long *config)
+{
+ const enum pin_config_param param = pinconf_to_config_param(*config);
+ const struct aspeed_pin_config_map *pmap;
+ const struct aspeed_pinctrl_data *pdata;
+ const struct aspeed_pin_config *pconf;
+ unsigned int val;
+ int rc = 0;
+ u32 arg;
+
+ pdata = pinctrl_dev_get_drvdata(pctldev);
+ pconf = find_pinconf_config(pdata, offset, param);
+ if (!pconf)
+ return -ENOTSUPP;
+
+ rc = regmap_read(pdata->maps[ASPEED_IP_SCU], pconf->reg, &val);
+ if (rc < 0)
+ return rc;
+
+ pmap = find_pinconf_map(param, MAP_TYPE_VAL,
+ (val & BIT(pconf->bit)) >> pconf->bit);
+
+ if (!pmap)
+ return -EINVAL;
+
+ if (param == PIN_CONFIG_DRIVE_STRENGTH)
+ arg = (u32) pmap->arg;
+ else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
+ arg = !!pmap->arg;
+ else
+ arg = 1;
+
+ if (!arg)
+ return -EINVAL;
+
+ *config = pinconf_to_config_packed(param, arg);
+
+ return 0;
+}
+
+int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
+ unsigned long *configs, unsigned int num_configs)
+{
+ const struct aspeed_pinctrl_data *pdata;
+ unsigned int i;
+ int rc = 0;
+
+ pdata = pinctrl_dev_get_drvdata(pctldev);
+
+ for (i = 0; i < num_configs; i++) {
+ const struct aspeed_pin_config_map *pmap;
+ const struct aspeed_pin_config *pconf;
+ enum pin_config_param param;
+ unsigned int val;
+ u32 arg;
+
+ param = pinconf_to_config_param(configs[i]);
+ arg = pinconf_to_config_argument(configs[i]);
+
+ pconf = find_pinconf_config(pdata, offset, param);
+ if (!pconf)
+ return -ENOTSUPP;
+
+ pmap = find_pinconf_map(param, MAP_TYPE_ARG, arg);
+
+ if (unlikely(WARN_ON(!pmap)))
+ return -EINVAL;
+
+ val = pmap->val << pconf->bit;
+
+ rc = regmap_update_bits(pdata->maps[ASPEED_IP_SCU], pconf->reg,
+ BIT(pconf->bit), val);
+
+ if (rc < 0)
+ return rc;
+
+ pr_debug("%s: Set SCU%02X[%d]=%d for param %d(=%d) on pin %d\n",
+ __func__, pconf->reg, pconf->bit, pmap->val,
+ param, arg, offset);
+ }
+
+ return 0;
+}
+
+int aspeed_pin_config_group_get(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ unsigned long *config)
+{
+ const unsigned int *pins;
+ unsigned int npins;
+ int rc;
+
+ rc = aspeed_pinctrl_get_group_pins(pctldev, selector, &pins, &npins);
+ if (rc < 0)
+ return rc;
+
+ if (!npins)
+ return -ENODEV;
+
+ rc = aspeed_pin_config_get(pctldev, pins[0], config);
+
+ return rc;
+}
+
+int aspeed_pin_config_group_set(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ const unsigned int *pins;
+ unsigned int npins;
+ int rc;
+ int i;
+
+ pr_debug("%s: Fetching pins for group selector %d\n",
+ __func__, selector);
+ rc = aspeed_pinctrl_get_group_pins(pctldev, selector, &pins, &npins);
+ if (rc < 0)
+ return rc;
+
+ for (i = 0; i < npins; i++) {
+ rc = aspeed_pin_config_set(pctldev, pins[i], configs,
+ num_configs);
+ if (rc < 0)
+ return rc;
+ }
+
+ return 0;
+}
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
index 08a10d4db229..fa125db828f5 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
@@ -514,6 +514,20 @@ struct aspeed_pin_desc {
SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \
MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio))
+/**
+ * @param The pinconf parameter type
+ * @pins The pin range this config struct covers, [low, high]
+ * @reg The register housing the configuration bits
+ * @mask The mask to select the bits of interest in @reg
+ */
+struct aspeed_pin_config {
+ enum pin_config_param param;
+ unsigned int pins[2];
+ unsigned int reg;
+ u8 bit;
+ u8 value;
+};
+
struct aspeed_pinctrl_data {
struct regmap *maps[ASPEED_NR_PINMUX_IPS];
@@ -525,6 +539,9 @@ struct aspeed_pinctrl_data {
const struct aspeed_pin_function *functions;
const unsigned int nfunctions;
+
+ const struct aspeed_pin_config *configs;
+ const unsigned int nconfigs;
};
#define ASPEED_PINCTRL_PIN(name_) \
@@ -580,5 +597,16 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
int aspeed_pinctrl_probe(struct platform_device *pdev,
struct pinctrl_desc *pdesc,
struct aspeed_pinctrl_data *pdata);
+int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
+ unsigned long *config);
+int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
+ unsigned long *configs, unsigned int num_configs);
+int aspeed_pin_config_group_get(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ unsigned long *config);
+int aspeed_pin_config_group_set(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ unsigned long *configs,
+ unsigned int num_configs);
#endif /* PINCTRL_ASPEED */
--
2.9.3
--
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* [PATCH v2 3/4] pinctrl: aspeed: g4: Add pinconf support
From: Andrew Jeffery @ 2017-04-07 12:57 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Jeffery, Rob Herring, Joel Stanley, Benjamin Herrenschmidt,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20170407125713.15678-1-andrew-zrmu5oMJ5Fs@public.gmane.org>
Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto
system, using the strategy outlined in the commit message for the
change to the Aspeed pinctrl core.
Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 117 ++++++++++++++++++++++++++++-
1 file changed, 116 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
index 7de596e2b9d4..b6a049643555 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
@@ -2234,6 +2234,110 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(WDTRST2),
};
+static const struct aspeed_pin_config aspeed_g4_configs[] = {
+ /* GPIO banks ranges [A, B], [D, J], [M, R] */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { D6, D5 }, SCU8C, 16 },
+ { PIN_CONFIG_BIAS_DISABLE, { D6, D5 }, SCU8C, 16 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { J21, E18 }, SCU8C, 17 },
+ { PIN_CONFIG_BIAS_DISABLE, { J21, E18 }, SCU8C, 17 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { A18, E15 }, SCU8C, 19 },
+ { PIN_CONFIG_BIAS_DISABLE, { A18, E15 }, SCU8C, 19 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { D15, B14 }, SCU8C, 20 },
+ { PIN_CONFIG_BIAS_DISABLE, { D15, B14 }, SCU8C, 20 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { D18, C17 }, SCU8C, 21 },
+ { PIN_CONFIG_BIAS_DISABLE, { D18, C17 }, SCU8C, 21 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { A14, U18 }, SCU8C, 22 },
+ { PIN_CONFIG_BIAS_DISABLE, { A14, U18 }, SCU8C, 22 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { A8, E7 }, SCU8C, 23 },
+ { PIN_CONFIG_BIAS_DISABLE, { A8, E7 }, SCU8C, 23 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { C22, E20 }, SCU8C, 24 },
+ { PIN_CONFIG_BIAS_DISABLE, { C22, E20 }, SCU8C, 24 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { J5, T1 }, SCU8C, 25 },
+ { PIN_CONFIG_BIAS_DISABLE, { J5, T1 }, SCU8C, 25 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { U1, U5 }, SCU8C, 26 },
+ { PIN_CONFIG_BIAS_DISABLE, { U1, U5 }, SCU8C, 26 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { V3, V5 }, SCU8C, 27 },
+ { PIN_CONFIG_BIAS_DISABLE, { V3, V5 }, SCU8C, 27 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { W4, AB2 }, SCU8C, 28 },
+ { PIN_CONFIG_BIAS_DISABLE, { W4, AB2 }, SCU8C, 28 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { V6, V7 }, SCU8C, 29 },
+ { PIN_CONFIG_BIAS_DISABLE, { V6, V7 }, SCU8C, 29 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { Y6, AB7 }, SCU8C, 30 },
+ { PIN_CONFIG_BIAS_DISABLE, { Y6, AB7 }, SCU8C, 30 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { V20, A5 }, SCU8C, 31 },
+ { PIN_CONFIG_BIAS_DISABLE, { V20, A5 }, SCU8C, 31 },
+
+ /* GPIOs T[0-5] (RGMII1 Tx pins) */
+ { PIN_CONFIG_DRIVE_STRENGTH, { A12, A13 }, SCU90, 9 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { A12, A13 }, SCU90, 12 },
+ { PIN_CONFIG_BIAS_DISABLE, { A12, A13 }, SCU90, 12 },
+
+ /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
+ { PIN_CONFIG_DRIVE_STRENGTH, { D9, D10 }, SCU90, 11 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { D9, D10 }, SCU90, 14 },
+ { PIN_CONFIG_BIAS_DISABLE, { D9, D10 }, SCU90, 14 },
+
+ /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { E11, E10 }, SCU90, 13 },
+ { PIN_CONFIG_BIAS_DISABLE, { E11, E10 }, SCU90, 13 },
+
+ /* GPIOs V[2-7] (RGMII2 Rx pins) */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { C9, C8 }, SCU90, 15 },
+ { PIN_CONFIG_BIAS_DISABLE, { C9, C8 }, SCU90, 15 },
+
+ /* ADC pull-downs (SCUA8[19:4]) */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { L5, L5 }, SCUA8, 4 },
+ { PIN_CONFIG_BIAS_DISABLE, { L5, L5 }, SCUA8, 4 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { L4, L4 }, SCUA8, 5 },
+ { PIN_CONFIG_BIAS_DISABLE, { L4, L4 }, SCUA8, 5 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { L3, L3 }, SCUA8, 6 },
+ { PIN_CONFIG_BIAS_DISABLE, { L3, L3 }, SCUA8, 6 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { L2, L2 }, SCUA8, 7 },
+ { PIN_CONFIG_BIAS_DISABLE, { L2, L2 }, SCUA8, 7 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { L1, L1 }, SCUA8, 8 },
+ { PIN_CONFIG_BIAS_DISABLE, { L1, L1 }, SCUA8, 8 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { M5, M5 }, SCUA8, 9 },
+ { PIN_CONFIG_BIAS_DISABLE, { M5, M5 }, SCUA8, 9 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { M4, M4 }, SCUA8, 10 },
+ { PIN_CONFIG_BIAS_DISABLE, { M4, M4 }, SCUA8, 10 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { M3, M3 }, SCUA8, 11 },
+ { PIN_CONFIG_BIAS_DISABLE, { M3, M3 }, SCUA8, 11 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { M2, M2 }, SCUA8, 12 },
+ { PIN_CONFIG_BIAS_DISABLE, { M2, M2 }, SCUA8, 12 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { M1, M1 }, SCUA8, 13 },
+ { PIN_CONFIG_BIAS_DISABLE, { M1, M1 }, SCUA8, 13 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { N5, N5 }, SCUA8, 14 },
+ { PIN_CONFIG_BIAS_DISABLE, { N5, N5 }, SCUA8, 14 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { N4, N4 }, SCUA8, 15 },
+ { PIN_CONFIG_BIAS_DISABLE, { N4, N4 }, SCUA8, 15 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { N3, N3 }, SCUA8, 16 },
+ { PIN_CONFIG_BIAS_DISABLE, { N3, N3 }, SCUA8, 16 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { N2, N2 }, SCUA8, 17 },
+ { PIN_CONFIG_BIAS_DISABLE, { N2, N2 }, SCUA8, 17 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { N1, N1 }, SCUA8, 18 },
+ { PIN_CONFIG_BIAS_DISABLE, { N1, N1 }, SCUA8, 18 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { P5, P5 }, SCUA8, 19 },
+ { PIN_CONFIG_BIAS_DISABLE, { P5, P5 }, SCUA8, 19 },
+
+ /*
+ * Debounce settings for GPIOs D and E passthrough mode are in
+ * SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for
+ * banks D and E is handled by the GPIO driver - GPIO passthrough is
+ * treated like any other non-GPIO mux function. There is a catch
+ * however, in that the debounce period is configured in the GPIO
+ * controller. Due to this tangle between GPIO and pinctrl we don't yet
+ * fully support pass-through debounce.
+ */
+ { PIN_CONFIG_INPUT_DEBOUNCE, { A18, D16 }, SCUA8, 20 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { B17, A17 }, SCUA8, 21 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { C16, B16 }, SCUA8, 22 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { A16, E15 }, SCUA8, 23 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { D15, C15 }, SCUA8, 24 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { B15, A15 }, SCUA8, 25 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { E14, D14 }, SCUA8, 26 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 },
+};
+
static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
.pins = aspeed_g4_pins,
.npins = ARRAY_SIZE(aspeed_g4_pins),
@@ -2241,6 +2345,8 @@ static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
.ngroups = ARRAY_SIZE(aspeed_g4_groups),
.functions = aspeed_g4_functions,
.nfunctions = ARRAY_SIZE(aspeed_g4_functions),
+ .configs = aspeed_g4_configs,
+ .nconfigs = ARRAY_SIZE(aspeed_g4_configs),
};
static struct pinmux_ops aspeed_g4_pinmux_ops = {
@@ -2257,16 +2363,25 @@ static struct pinctrl_ops aspeed_g4_pinctrl_ops = {
.get_group_name = aspeed_pinctrl_get_group_name,
.get_group_pins = aspeed_pinctrl_get_group_pins,
.pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
- .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
+static const struct pinconf_ops aspeed_g4_conf_ops = {
+ .is_generic = true,
+ .pin_config_get = aspeed_pin_config_get,
+ .pin_config_set = aspeed_pin_config_set,
+ .pin_config_group_get = aspeed_pin_config_group_get,
+ .pin_config_group_set = aspeed_pin_config_group_set,
+};
+
static struct pinctrl_desc aspeed_g4_pinctrl_desc = {
.name = "aspeed-g4-pinctrl",
.pins = aspeed_g4_pins,
.npins = ARRAY_SIZE(aspeed_g4_pins),
.pctlops = &aspeed_g4_pinctrl_ops,
.pmxops = &aspeed_g4_pinmux_ops,
+ .confops = &aspeed_g4_conf_ops,
};
static int aspeed_g4_pinctrl_probe(struct platform_device *pdev)
--
2.9.3
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^ permalink raw reply related
* [PATCH v2 4/4] pinctrl: aspeed: g5: Add pinconf support
From: Andrew Jeffery @ 2017-04-07 12:57 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Jeffery, Rob Herring, Joel Stanley, Benjamin Herrenschmidt,
linux-gpio, devicetree, linux-kernel, openbmc
In-Reply-To: <20170407125713.15678-1-andrew@aj.id.au>
Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system,
using the strategy outlined in the commit message for the change to the
Aspeed pinctrl core.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 153 ++++++++++++++++++++++++++++-
1 file changed, 152 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 43221a3c7e23..68aa04664a62 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -2285,6 +2285,146 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
ASPEED_PINCTRL_FUNC(WDTRST2),
};
+static struct aspeed_pin_config aspeed_g5_configs[] = {
+ /* GPIOA, GPIOQ */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { B14, B13 }, SCU8C, 16 },
+ { PIN_CONFIG_BIAS_DISABLE, { B14, B13 }, SCU8C, 16 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { A11, N20 }, SCU8C, 16 },
+ { PIN_CONFIG_BIAS_DISABLE, { A11, N20 }, SCU8C, 16 },
+
+ /* GPIOB, GPIOR */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { K19, H20 }, SCU8C, 17 },
+ { PIN_CONFIG_BIAS_DISABLE, { K19, H20 }, SCU8C, 17 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { AA19, E10 }, SCU8C, 17 },
+ { PIN_CONFIG_BIAS_DISABLE, { AA19, E10 }, SCU8C, 17 },
+
+ /* GPIOC, GPIOS*/
+ { PIN_CONFIG_BIAS_PULL_DOWN, { C12, B11 }, SCU8C, 18 },
+ { PIN_CONFIG_BIAS_DISABLE, { C12, B11 }, SCU8C, 18 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { V20, AA20 }, SCU8C, 18 },
+ { PIN_CONFIG_BIAS_DISABLE, { V20, AA20 }, SCU8C, 18 },
+
+ /* GPIOD, GPIOY */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { F19, C21 }, SCU8C, 19 },
+ { PIN_CONFIG_BIAS_DISABLE, { F19, C21 }, SCU8C, 19 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { R22, P20 }, SCU8C, 19 },
+ { PIN_CONFIG_BIAS_DISABLE, { R22, P20 }, SCU8C, 19 },
+
+ /* GPIOE, GPIOZ */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { B20, B19 }, SCU8C, 20 },
+ { PIN_CONFIG_BIAS_DISABLE, { B20, B19 }, SCU8C, 20 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { Y20, W21 }, SCU8C, 20 },
+ { PIN_CONFIG_BIAS_DISABLE, { Y20, W21 }, SCU8C, 20 },
+
+ /* GPIOF, GPIOAA */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { J19, H18 }, SCU8C, 21 },
+ { PIN_CONFIG_BIAS_DISABLE, { J19, H18 }, SCU8C, 21 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { Y21, P19 }, SCU8C, 21 },
+ { PIN_CONFIG_BIAS_DISABLE, { Y21, P19 }, SCU8C, 21 },
+
+ /* GPIOG, GPIOAB */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { A19, E14 }, SCU8C, 22 },
+ { PIN_CONFIG_BIAS_DISABLE, { A19, E14 }, SCU8C, 22 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { N19, R20 }, SCU8C, 22 },
+ { PIN_CONFIG_BIAS_DISABLE, { N19, R20 }, SCU8C, 22 },
+
+ /* GPIOH, GPIOAC */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { A18, D18 }, SCU8C, 23 },
+ { PIN_CONFIG_BIAS_DISABLE, { A18, D18 }, SCU8C, 23 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { G21, G22 }, SCU8C, 23 },
+ { PIN_CONFIG_BIAS_DISABLE, { G21, G22 }, SCU8C, 23 },
+
+ /* GPIOs [I, P] */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { C18, A15 }, SCU8C, 24 },
+ { PIN_CONFIG_BIAS_DISABLE, { C18, A15 }, SCU8C, 24 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { R2, T3 }, SCU8C, 25 },
+ { PIN_CONFIG_BIAS_DISABLE, { R2, T3 }, SCU8C, 25 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { L3, R1 }, SCU8C, 26 },
+ { PIN_CONFIG_BIAS_DISABLE, { L3, R1 }, SCU8C, 26 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { T2, W1 }, SCU8C, 27 },
+ { PIN_CONFIG_BIAS_DISABLE, { T2, W1 }, SCU8C, 27 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { Y1, T5 }, SCU8C, 28 },
+ { PIN_CONFIG_BIAS_DISABLE, { Y1, T5 }, SCU8C, 28 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { V2, T4 }, SCU8C, 29 },
+ { PIN_CONFIG_BIAS_DISABLE, { V2, T4 }, SCU8C, 29 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { U5, W4 }, SCU8C, 30 },
+ { PIN_CONFIG_BIAS_DISABLE, { U5, W4 }, SCU8C, 30 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { V4, V6 }, SCU8C, 31 },
+ { PIN_CONFIG_BIAS_DISABLE, { V4, V6 }, SCU8C, 31 },
+
+ /* GPIOs T[0-5] (RGMII1 Tx pins) */
+ { PIN_CONFIG_DRIVE_STRENGTH, { B5, B5 }, SCU90, 8 },
+ { PIN_CONFIG_DRIVE_STRENGTH, { E9, A5 }, SCU90, 9 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { B5, D7 }, SCU90, 12 },
+ { PIN_CONFIG_BIAS_DISABLE, { B5, D7 }, SCU90, 12 },
+
+ /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
+ { PIN_CONFIG_DRIVE_STRENGTH, { B2, B2 }, SCU90, 10 },
+ { PIN_CONFIG_DRIVE_STRENGTH, { B1, B3 }, SCU90, 11 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { B2, D4 }, SCU90, 14 },
+ { PIN_CONFIG_BIAS_DISABLE, { B2, D4 }, SCU90, 14 },
+
+ /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { B4, C4 }, SCU90, 13 },
+ { PIN_CONFIG_BIAS_DISABLE, { B4, C4 }, SCU90, 13 },
+
+ /* GPIOs V[2-7] (RGMII2 Rx pins) */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { C2, E6 }, SCU90, 15 },
+ { PIN_CONFIG_BIAS_DISABLE, { C2, E6 }, SCU90, 15 },
+
+ /* ADC pull-downs (SCUA8[19:4]) */
+ { PIN_CONFIG_BIAS_PULL_DOWN, { F4, F4 }, SCUA8, 4 },
+ { PIN_CONFIG_BIAS_DISABLE, { F4, F4 }, SCUA8, 4 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { F5, F5 }, SCUA8, 5 },
+ { PIN_CONFIG_BIAS_DISABLE, { F5, F5 }, SCUA8, 5 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { E2, E2 }, SCUA8, 6 },
+ { PIN_CONFIG_BIAS_DISABLE, { E2, E2 }, SCUA8, 6 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { E1, E1 }, SCUA8, 7 },
+ { PIN_CONFIG_BIAS_DISABLE, { E1, E1 }, SCUA8, 7 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { F3, F3 }, SCUA8, 8 },
+ { PIN_CONFIG_BIAS_DISABLE, { F3, F3 }, SCUA8, 8 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { E3, E3 }, SCUA8, 9 },
+ { PIN_CONFIG_BIAS_DISABLE, { E3, E3 }, SCUA8, 9 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { G5, G5 }, SCUA8, 10 },
+ { PIN_CONFIG_BIAS_DISABLE, { G5, G5 }, SCUA8, 10 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { G4, G4 }, SCUA8, 11 },
+ { PIN_CONFIG_BIAS_DISABLE, { G4, G4 }, SCUA8, 11 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { F2, F2 }, SCUA8, 12 },
+ { PIN_CONFIG_BIAS_DISABLE, { F2, F2 }, SCUA8, 12 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { G3, G3 }, SCUA8, 13 },
+ { PIN_CONFIG_BIAS_DISABLE, { G3, G3 }, SCUA8, 13 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { G2, G2 }, SCUA8, 14 },
+ { PIN_CONFIG_BIAS_DISABLE, { G2, G2 }, SCUA8, 14 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { F1, F1 }, SCUA8, 15 },
+ { PIN_CONFIG_BIAS_DISABLE, { F1, F1 }, SCUA8, 15 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { H5, H5 }, SCUA8, 16 },
+ { PIN_CONFIG_BIAS_DISABLE, { H5, H5 }, SCUA8, 16 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { G1, G1 }, SCUA8, 17 },
+ { PIN_CONFIG_BIAS_DISABLE, { G1, G1 }, SCUA8, 17 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { H3, H3 }, SCUA8, 18 },
+ { PIN_CONFIG_BIAS_DISABLE, { H3, H3 }, SCUA8, 18 },
+ { PIN_CONFIG_BIAS_PULL_DOWN, { H4, H4 }, SCUA8, 19 },
+ { PIN_CONFIG_BIAS_DISABLE, { H4, H4 }, SCUA8, 19 },
+
+ /*
+ * Debounce settings for GPIOs D and E passthrough mode are in
+ * SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for
+ * banks D and E is handled by the GPIO driver - GPIO passthrough is
+ * treated like any other non-GPIO mux function. There is a catch
+ * however, in that the debounce period is configured in the GPIO
+ * controller. Due to this tangle between GPIO and pinctrl we don't yet
+ * fully support pass-through debounce.
+ */
+ { PIN_CONFIG_INPUT_DEBOUNCE, { F19, E21 }, SCUA8, 20 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { F20, D20 }, SCUA8, 21 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { D21, E20 }, SCUA8, 22 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { G18, C21 }, SCUA8, 23 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { B20, C20 }, SCUA8, 24 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { F18, F17 }, SCUA8, 25 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { E18, D19 }, SCUA8, 26 },
+ { PIN_CONFIG_INPUT_DEBOUNCE, { A20, B19 }, SCUA8, 27 },
+};
+
static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
.pins = aspeed_g5_pins,
.npins = ARRAY_SIZE(aspeed_g5_pins),
@@ -2292,6 +2432,8 @@ static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
.ngroups = ARRAY_SIZE(aspeed_g5_groups),
.functions = aspeed_g5_functions,
.nfunctions = ARRAY_SIZE(aspeed_g5_functions),
+ .configs = aspeed_g5_configs,
+ .nconfigs = ARRAY_SIZE(aspeed_g5_configs),
};
static struct pinmux_ops aspeed_g5_pinmux_ops = {
@@ -2308,16 +2450,25 @@ static struct pinctrl_ops aspeed_g5_pinctrl_ops = {
.get_group_name = aspeed_pinctrl_get_group_name,
.get_group_pins = aspeed_pinctrl_get_group_pins,
.pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
- .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
+static struct pinconf_ops aspeed_g5_conf_ops = {
+ .is_generic = true,
+ .pin_config_get = aspeed_pin_config_get,
+ .pin_config_set = aspeed_pin_config_set,
+ .pin_config_group_get = aspeed_pin_config_group_get,
+ .pin_config_group_set = aspeed_pin_config_group_set,
+};
+
static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
.name = "aspeed-g5-pinctrl",
.pins = aspeed_g5_pins,
.npins = ARRAY_SIZE(aspeed_g5_pins),
.pctlops = &aspeed_g5_pinctrl_ops,
.pmxops = &aspeed_g5_pinmux_ops,
+ .confops = &aspeed_g5_conf_ops,
};
static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
--
2.9.3
^ permalink raw reply related
* [PATCH v2 0/4] gpio: aspeed: Add debounce support
From: Andrew Jeffery @ 2017-04-07 12:58 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Jeffery, Rob Herring, Joel Stanley, Benjamin Herrenschmidt,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ
Hi Linus,
v2 of the Aspeed GPIO debounce patch expands it out into a series, resolving a
lack of devicetree binding documentation updates in the initial send, and
completely reworking the debounce timer use tracking for space efficiency.
I do wonder whether there's a more acceptable way to track the use of the
timers than what I've got, but it at least works.
The rework was largely an effort to resolve Joel's review of v1, in the absence
of any other feedback.
Cheers,
Andrew
In v2:
* Update devicetree bindings documentation
* Address Joel's comments
Andrew Jeffery (4):
gpio: aspeed: dt: Fix description alignment in bindings document
gpio: aspeed: dt: Add optional clocks property
gpio: aspeed: Add debounce support
gpio: aspeed: Add open-source and open-drain support
.../devicetree/bindings/gpio/gpio-aspeed.txt | 3 +-
drivers/gpio/gpio-aspeed.c | 285 ++++++++++++++++++++-
2 files changed, 282 insertions(+), 6 deletions(-)
--
2.9.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH v2 1/4] gpio: aspeed: dt: Fix description alignment in bindings document
From: Andrew Jeffery @ 2017-04-07 12:58 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Jeffery, Rob Herring, Joel Stanley, Benjamin Herrenschmidt,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20170407125902.15960-1-andrew-zrmu5oMJ5Fs@public.gmane.org>
Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
---
Documentation/devicetree/bindings/gpio/gpio-aspeed.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
index 393bb2ed8a77..6f30b9a048da 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
@@ -17,7 +17,7 @@ Required properties:
Optional properties:
-- interrupt-parent : The parent interrupt controller, optional if inherited
+- interrupt-parent : The parent interrupt controller, optional if inherited
The gpio and interrupt properties are further described in their respective
bindings documentation:
--
2.9.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v2 2/4] gpio: aspeed: dt: Add optional clocks property
From: Andrew Jeffery @ 2017-04-07 12:59 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Jeffery, Rob Herring, Joel Stanley, Benjamin Herrenschmidt,
linux-gpio, devicetree, linux-kernel, openbmc
In-Reply-To: <20170407125902.15960-1-andrew@aj.id.au>
We need a reference to the HPLL to calculate debounce cycles. If the
clocks property is not supplied in the GPIO node then the consumer
should deny any debounce requests.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
Documentation/devicetree/bindings/gpio/gpio-aspeed.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
index 6f30b9a048da..c756afa88cc6 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
@@ -18,6 +18,7 @@ Required properties:
Optional properties:
- interrupt-parent : The parent interrupt controller, optional if inherited
+- clocks : A phandle to the HPLL clock node for debounce timings
The gpio and interrupt properties are further described in their respective
bindings documentation:
--
2.9.3
^ permalink raw reply related
* [PATCH v2 3/4] gpio: aspeed: Add debounce support
From: Andrew Jeffery @ 2017-04-07 12:59 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Jeffery, Rob Herring, Joel Stanley, Benjamin Herrenschmidt,
linux-gpio, devicetree, linux-kernel, openbmc
In-Reply-To: <20170407125902.15960-1-andrew@aj.id.au>
Each GPIO in the Aspeed GPIO controller can choose one of four input
debounce states: to disable debouncing for an input, or select from one
of three programmable debounce timer values. Each GPIO in a
four-bank-set is assigned one bit in each of two debounce configuration
registers dedicated to the set, and selects a debounce state by
configuring the two bits to select one of the four options.
The limitation on debounce timer values is managed by mapping offsets
onto a configured timer value and keeping count of the number of users
a timer has. Timer values are configured on a first-come-first-served
basis.
A small twist in the hardware design is that the debounce configuration
register numbering is reversed with respect to the binary representation
of the debounce timer of interest (i.e. debounce register 1 represents
bit 1, and debounce register 2 represents bit 0 of the timer numbering).
Tested on an AST2500EVB with additional inspection under QEMU's
romulus-bmc machine.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/gpio/gpio-aspeed.c | 281 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 276 insertions(+), 5 deletions(-)
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index fb16cc771c0d..3327a48df862 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -9,14 +9,18 @@
* 2 of the License, or (at your option) any later version.
*/
-#include <linux/module.h>
-#include <linux/kernel.h>
+#include <asm/div64.h>
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/hashtable.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/spinlock.h>
-#include <linux/platform_device.h>
-#include <linux/gpio/driver.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
struct aspeed_bank_props {
unsigned int bank;
@@ -29,59 +33,85 @@ struct aspeed_gpio_config {
const struct aspeed_bank_props *props;
};
+/*
+ * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
+ * @timer_users: Tracks the number of users for each timer
+ *
+ * The @timer_users has four elements but the first element is unused. This is
+ * to simplify accounting and indexing, as a zero value in @offset_timer
+ * represents disabled debouncing for the GPIO. Any other value for an element
+ * of @offset_timer is used as an index into @timer_users. This behaviour of
+ * the zero value aligns with the behaviour of zero built from the timer
+ * configuration registers (i.e. debouncing is disabled).
+ */
struct aspeed_gpio {
struct gpio_chip chip;
spinlock_t lock;
void __iomem *base;
int irq;
const struct aspeed_gpio_config *config;
+
+ u8 *offset_timer;
+ unsigned int timer_users[4];
+ struct clk *clk;
};
struct aspeed_gpio_bank {
uint16_t val_regs;
uint16_t irq_regs;
+ uint16_t debounce_regs;
const char names[4][3];
};
+static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
+
static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
{
.val_regs = 0x0000,
.irq_regs = 0x0008,
+ .debounce_regs = 0x0040,
.names = { "A", "B", "C", "D" },
},
{
.val_regs = 0x0020,
.irq_regs = 0x0028,
+ .debounce_regs = 0x0048,
.names = { "E", "F", "G", "H" },
},
{
.val_regs = 0x0070,
.irq_regs = 0x0098,
+ .debounce_regs = 0x00b0,
.names = { "I", "J", "K", "L" },
},
{
.val_regs = 0x0078,
.irq_regs = 0x00e8,
+ .debounce_regs = 0x0100,
.names = { "M", "N", "O", "P" },
},
{
.val_regs = 0x0080,
.irq_regs = 0x0118,
+ .debounce_regs = 0x0130,
.names = { "Q", "R", "S", "T" },
},
{
.val_regs = 0x0088,
.irq_regs = 0x0148,
+ .debounce_regs = 0x0160,
.names = { "U", "V", "W", "X" },
},
{
.val_regs = 0x01E0,
.irq_regs = 0x0178,
+ .debounce_regs = 0x0190,
.names = { "Y", "Z", "AA", "AB" },
},
{
.val_regs = 0x01E8,
.irq_regs = 0x01A8,
+ .debounce_regs = 0x01c0,
.names = { "AC", "", "", "" },
},
};
@@ -99,6 +129,13 @@ static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
#define GPIO_IRQ_TYPE2 0x0c
#define GPIO_IRQ_STATUS 0x10
+#define GPIO_DEBOUNCE_SEL1 0x00
+#define GPIO_DEBOUNCE_SEL2 0x04
+
+#define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o))
+#define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1)
+#define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0)
+
static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
{
unsigned int bank = GPIO_BANK(offset);
@@ -144,6 +181,7 @@ static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
}
#define have_irq(g, o) have_input((g), (o))
+#define have_debounce(g, o) have_input((g), (o))
static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
{
@@ -506,6 +544,227 @@ static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
pinctrl_free_gpio(chip->base + offset);
}
+static inline void __iomem *bank_debounce_reg(struct aspeed_gpio *gpio,
+ const struct aspeed_gpio_bank *bank,
+ unsigned int reg)
+{
+ return gpio->base + bank->debounce_regs + reg;
+}
+
+static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
+ u32 *cycles)
+{
+ u64 rate;
+ u64 n;
+ u32 r;
+
+ rate = clk_get_rate(gpio->clk);
+ if (!rate)
+ return -ENOTSUPP;
+
+ n = rate * usecs;
+ r = do_div(n, 1000000);
+
+ if (n >= U32_MAX)
+ return -ERANGE;
+
+ /* At least as long as the requested time */
+ *cycles = n + (!!r);
+
+ return 0;
+}
+
+/* Call under gpio->lock */
+static int register_allocated_timer(struct aspeed_gpio *gpio,
+ unsigned int offset, unsigned int timer)
+{
+ if (WARN(gpio->offset_timer[offset] != 0,
+ "Offset %d already allocated timer %d\n",
+ offset, gpio->offset_timer[offset]))
+ return -EINVAL;
+
+ if (WARN(gpio->timer_users[timer] == UINT_MAX,
+ "Timer user count would overflow\n"))
+ return -EPERM;
+
+ gpio->offset_timer[offset] = timer;
+ gpio->timer_users[timer]++;
+
+ return 0;
+}
+
+/* Call under gpio->lock */
+static int unregister_allocated_timer(struct aspeed_gpio *gpio,
+ unsigned int offset)
+{
+ if (WARN(gpio->offset_timer[offset] == 0,
+ "No timer allocated to offset %d\n", offset))
+ return -EINVAL;
+
+ if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
+ "No users recorded for timer %d\n",
+ gpio->offset_timer[offset]))
+ return -EINVAL;
+
+ gpio->timer_users[gpio->offset_timer[offset]]--;
+ gpio->offset_timer[offset] = 0;
+
+ return 0;
+}
+
+/* Call under gpio->lock */
+static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
+ unsigned int offset)
+{
+ return gpio->offset_timer[offset] > 0;
+}
+
+/* Call under gpio->lock */
+static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
+ unsigned int timer)
+{
+ const struct aspeed_gpio_bank *bank = to_bank(offset);
+ const u32 mask = GPIO_BIT(offset);
+ void __iomem *addr;
+ u32 val;
+
+ addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL1);
+ val = ioread32(addr);
+ iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr);
+
+ addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL2);
+ val = ioread32(addr);
+ iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr);
+}
+
+static int enable_debounce(struct gpio_chip *chip, unsigned int offset,
+ unsigned long usecs)
+{
+ struct aspeed_gpio *gpio = gpiochip_get_data(chip);
+ u32 requested_cycles;
+ unsigned long flags;
+ int rc;
+ int i;
+
+ rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
+ if (rc < 0) {
+ dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",
+ usecs, clk_get_rate(gpio->clk), rc);
+ return rc;
+ }
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ if (timer_allocation_registered(gpio, offset)) {
+ rc = unregister_allocated_timer(gpio, offset);
+ if (rc < 0)
+ goto out;
+ }
+
+ /* Try to find a timer already configured for the debounce period */
+ for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) {
+ u32 cycles;
+
+ cycles = ioread32(gpio->base + debounce_timers[i]);
+ if (requested_cycles == cycles)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(debounce_timers)) {
+ int j;
+
+ /*
+ * As there are no timers configured for the requested debounce
+ * period, find an unused timer instead
+ */
+ for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
+ if (gpio->timer_users[j] == 0)
+ break;
+ }
+
+ if (j == ARRAY_SIZE(gpio->timer_users)) {
+ dev_warn(chip->parent,
+ "Debounce timers exhausted, cannot debounce for period %luus\n",
+ usecs);
+
+ rc = -EPERM;
+
+ /*
+ * We already adjusted the accounting to remove @offset
+ * as a user of its previous timer, so also configure
+ * the hardware so @offset has timers disabled for
+ * consistency.
+ */
+ configure_timer(gpio, offset, 0);
+ goto out;
+ }
+
+ i = j;
+
+ iowrite32(requested_cycles, gpio->base + debounce_timers[i]);
+ }
+
+ if (WARN(i == 0, "Cannot register index of disabled timer\n")) {
+ rc = -EINVAL;
+ goto out;
+ }
+
+ register_allocated_timer(gpio, offset, i);
+ configure_timer(gpio, offset, i);
+
+out:
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return rc;
+}
+
+static int disable_debounce(struct gpio_chip *chip, unsigned int offset)
+{
+ struct aspeed_gpio *gpio = gpiochip_get_data(chip);
+ unsigned long flags;
+ int rc;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ rc = unregister_allocated_timer(gpio, offset);
+ if (!rc)
+ configure_timer(gpio, offset, 0);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return rc;
+}
+
+static int set_debounce(struct gpio_chip *chip, unsigned int offset,
+ unsigned long usecs)
+{
+ struct aspeed_gpio *gpio = gpiochip_get_data(chip);
+
+ if (!have_debounce(gpio, offset))
+ return -ENOTSUPP;
+
+ if (usecs)
+ return enable_debounce(chip, offset, usecs);
+
+ return disable_debounce(chip, offset);
+}
+
+static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
+ unsigned long config)
+{
+ unsigned long param = pinconf_to_config_param(config);
+ u32 arg = pinconf_to_config_argument(config);
+
+ if (param == PIN_CONFIG_INPUT_DEBOUNCE)
+ return set_debounce(chip, offset, arg);
+ else if (param == PIN_CONFIG_BIAS_DISABLE ||
+ param == PIN_CONFIG_BIAS_PULL_DOWN ||
+ param == PIN_CONFIG_DRIVE_STRENGTH)
+ return pinctrl_gpio_set_config(offset, config);
+
+ return -ENOTSUPP;
+}
+
/*
* Any banks not specified in a struct aspeed_bank_props array are assumed to
* have the properties:
@@ -565,8 +824,16 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
if (!gpio_id)
return -EINVAL;
+ gpio->clk = of_clk_get(pdev->dev.of_node, 0);
+ if (IS_ERR(gpio->clk)) {
+ dev_warn(&pdev->dev,
+ "No HPLL clock phandle provided, debouncing disabled\n");
+ gpio->clk = NULL;
+ }
+
gpio->config = gpio_id->data;
+ gpio->chip.parent = &pdev->dev;
gpio->chip.ngpio = gpio->config->nr_gpios;
gpio->chip.parent = &pdev->dev;
gpio->chip.direction_input = aspeed_gpio_dir_in;
@@ -576,6 +843,7 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
gpio->chip.free = aspeed_gpio_free;
gpio->chip.get = aspeed_gpio_get;
gpio->chip.set = aspeed_gpio_set;
+ gpio->chip.set_config = aspeed_gpio_set_config;
gpio->chip.label = dev_name(&pdev->dev);
gpio->chip.base = -1;
gpio->chip.irq_need_valid_mask = true;
@@ -584,6 +852,9 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
if (rc < 0)
return rc;
+ gpio->offset_timer =
+ devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
+
return aspeed_gpio_setup_irqs(gpio, pdev);
}
--
2.9.3
^ permalink raw reply related
* [PATCH v2 4/4] gpio: aspeed: Add open-source and open-drain support
From: Andrew Jeffery @ 2017-04-07 12:59 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Jeffery, Rob Herring, Joel Stanley, Benjamin Herrenschmidt,
linux-gpio, devicetree, linux-kernel, openbmc
In-Reply-To: <20170407125902.15960-1-andrew@aj.id.au>
As per the datasheet, manage the IO and value states to implement
open-source/open-drain, but do this by falling back to gpiolib's
emulation.
This commit simply makes the behaviour explicit for clarity, rather than
relying on the implicit return of -ENOTSUPP to trigger the emulation.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/gpio/gpio-aspeed.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index 3327a48df862..ccea609676ee 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -761,6 +761,10 @@ static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
param == PIN_CONFIG_BIAS_PULL_DOWN ||
param == PIN_CONFIG_DRIVE_STRENGTH)
return pinctrl_gpio_set_config(offset, config);
+ else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN ||
+ param == PIN_CONFIG_DRIVE_OPEN_SOURCE)
+ /* Return -ENOTSUPP to trigger emulation, as per datasheet */
+ return -ENOTSUPP;
return -ENOTSUPP;
}
--
2.9.3
^ permalink raw reply related
* Re: [PATCH v2 2/8] v4l: fwnode: Support generic fwnode for parsing standardised properties
From: Sakari Ailus @ 2017-04-07 13:03 UTC (permalink / raw)
To: Laurent Pinchart; +Cc: Sakari Ailus, linux-media, linux-acpi, devicetree
In-Reply-To: <1761689.CzVR5YAybi@avalon>
Hi Laurent,
On Fri, Apr 07, 2017 at 01:54:58PM +0300, Laurent Pinchart wrote:
> Hi Sakari,
>
> On Friday 07 Apr 2017 13:36:34 Sakari Ailus wrote:
> > On Fri, Apr 07, 2017 at 12:44:27PM +0300, Laurent Pinchart wrote:
> > > On Thursday 06 Apr 2017 16:12:04 Sakari Ailus wrote:
> > > > The fwnode_handle is a more generic way than OF device_node to describe
> > > > firmware nodes. Instead of the OF API, use more generic fwnode API to
> > > > obtain the same information.
> > >
> > > I would mention that this is a copy of v4l2-of.c with the OF API replaced
> > > with the fwnode API.
> >
> > I'll add that to the description.
> >
> > > > As the V4L2 fwnode support will be required by a small minority of e.g.
> > > > ACPI based systems (the same might actually go for OF), make this a
> > > > module instead of embedding it in the videodev module.
> > > >
> > > > Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> > > > ---
> > > >
> > > > drivers/media/v4l2-core/Kconfig | 3 +
> > > > drivers/media/v4l2-core/Makefile | 1 +
> > > > drivers/media/v4l2-core/v4l2-fwnode.c | 353 +++++++++++++++++++++++++++
> > > > include/media/v4l2-fwnode.h | 104 ++++++++++
> > > > 4 files changed, 461 insertions(+)
> > > > create mode 100644 drivers/media/v4l2-core/v4l2-fwnode.c
> > > > create mode 100644 include/media/v4l2-fwnode.h
>
> [snip]
>
> > > > diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c
> > > > b/drivers/media/v4l2-core/v4l2-fwnode.c new file mode 100644
> > > > index 0000000..4f69b11
> > > > --- /dev/null
> > > > +++ b/drivers/media/v4l2-core/v4l2-fwnode.c
> > > > @@ -0,0 +1,353 @@
> > > > +/*
> > > > + * V4L2 fwnode binding parsing library
> > > > + *
> > > > + * Copyright (c) 2016 Intel Corporation.
> > > > + * Author: Sakari Ailus <sakari.ailus@linux.intel.com>
> > > > + *
> > > > + * Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd.
> > > > + * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
> > > > + *
> > > > + * Copyright (C) 2012 Renesas Electronics Corp.
> > > > + * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
> > > > + *
> > > > + * This program is free software; you can redistribute it and/or modify
> > > > + * it under the terms of version 2 of the GNU General Public License as
> > > > + * published by the Free Software Foundation.
> > > > + */
> > > > +#include <linux/acpi.h>
> > > > +#include <linux/kernel.h>
> > > > +#include <linux/module.h>
> > > > +#include <linux/of.h>
> > > > +#include <linux/property.h>
> > > > +#include <linux/slab.h>
> > > > +#include <linux/string.h>
> > > > +#include <linux/types.h>
> > > > +
> > > > +#include <media/v4l2-fwnode.h>
> > > > +
> > > > +static int v4l2_fwnode_endpoint_parse_csi_bus(struct fwnode_handle
> > > > *fwn,
> > > > + struct v4l2_fwnode_endpoint
> > > > *vfwn)
> > > > +{
> > > > + struct v4l2_fwnode_bus_mipi_csi2 *bus = &vfwn->bus.mipi_csi2;
> > > > + bool have_clk_lane = false;
> > > > + unsigned int flags = 0, lanes_used = 0;
> > > > + unsigned int i;
> > > > + u32 v;
> > > > + int rval;
> > >
> > > I would have used "ret" instead of "rval" ;-)
> >
> > I know. But
> >
> > 1) there's no established convention in the file and
> >
> > 2) "rval" has the benefit is easier to look up; one doesn't find a plethora
> > of "return something". Therefore it is better than "ret" for the purpose.
>
> The solution to that is
>
> /ret\>
>
> (and, of course, switching to vim :-D)
What's "\>" for?
I don't think you can convince people to switch to vim this way. :-)
>
> [snip]
>
> > > > +/*
> > > > + * v4l2_fwnode_endpoint_free() - free the V4L2 fwnode acquired by
> > > > + * v4l2_fwnode_endpoint_alloc_parse()
> > > > + * @fwn - the V4L2 fwnode the resources of which are to be released
> > >
> > > Mayeb "the V4L2 fwnode whose resources are to be released" ?
> > >
> > > > + *
> > > > + * It is safe to call this function with NULL argument or on an
> > >
> > > s/on an/on a/
> >
> > Yes.
> >
> > > > + * V4L2 fwnode the parsing of which failed.
> > >
> > > "whose parsing failed" ?
> >
> > Any particular reason? Do you like "whose"? :-)
>
> "of which" sounds dubious in this context, but please consult a native English
> speaker in case of doubt.
"Whose" is the possessive form of "who". Albeit nowadays it could probably
be used for other purposes as well.
In my opinion "of which" is perfectly appropriate language here.
--
Regards,
Sakari Ailus
e-mail: sakari.ailus@iki.fi XMPP: sailus@retiisi.org.uk
^ permalink raw reply
* Re: [PATCH v3 1/9] ARM: dts: imx6ul-isiot: Add Sound card with codec node
From: Shawn Guo @ 2017-04-07 13:16 UTC (permalink / raw)
To: Jagan Teki
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Sascha Hauer, Fabio Estevam,
Matteo Lisi, Michael Trimarchi, Jagan Teki
In-Reply-To: <1491501735-1649-2-git-send-email-jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
On Thu, Apr 06, 2017 at 11:32:07PM +0530, Jagan Teki wrote:
> From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
>
> Add support for Sound card and related codec(via i2c1) nodes
> on Engicam Is.IoT MX6UL variant module boards.
>
> Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Matteo Lisi <matteo.lisi-4s7YQHO/iPVBDgjK7y7TUQ@public.gmane.org>
> Cc: Michael Trimarchi <michael-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
> Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
> ---
> Changes for v3:
> - Replace fsl,imx-audio-sgtl5000 and use simple-audio-card
> Changes for v2:
> - Use proper [label:] node-name[@unit-address] for codec
> - Remove incorrect codec property 'wlf,shared-lrclk'
> - Remove 'gpr' from sound card node
>
> arch/arm/boot/dts/imx6ul-isiot-common.dtsi | 10 +++++++
> arch/arm/boot/dts/imx6ul-isiot.dtsi | 44 ++++++++++++++++++++++++++++++
Can you help me understand how these two files are related? Why is
sgtl5000 added into one and sound node added into the other?
Shawn
> 2 files changed, 54 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6ul-isiot-common.dtsi b/arch/arm/boot/dts/imx6ul-isiot-common.dtsi
> index 2beaab6..d456080 100644
> --- a/arch/arm/boot/dts/imx6ul-isiot-common.dtsi
> +++ b/arch/arm/boot/dts/imx6ul-isiot-common.dtsi
> @@ -41,6 +41,16 @@
> */
>
> &i2c1 {
> + sgtl5000: codec@a {
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + clocks = <&clks IMX6UL_CLK_OSC>;
> + clock-names = "mclk";
> + VDDA-supply = <®_3p3v>;
> + VDDIO-supply = <®_3p3v>;
> + VDDD-supply = <®_1p8v>;
> + };
> +
> stmpe811: gpio-expander@44 {
> compatible = "st,stmpe811";
> reg = <0x44>;
> diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi
> index ea30380..7e947e5 100644
> --- a/arch/arm/boot/dts/imx6ul-isiot.dtsi
> +++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi
> @@ -69,6 +69,50 @@
> 100>;
> default-brightness-level = <100>;
> };
> +
> + reg_1p8v: regulator-1p8v {
> + compatible = "regulator-fixed";
> + regulator-name = "1P8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + reg_3p3v: regulator-3p3v {
> + compatible = "regulator-fixed";
> + regulator-name = "3P3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "imx6ul-isiot-sgtl5000";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <&dailink_master>;
> + simple-audio-card,frame-master = <&dailink_master>;
> + simple-audio-card,widgets =
> + "Microphone", "Mic Jack",
> + "Line", "Line In",
> + "Line", "Line Out",
> + "Headphone", "Headphone Jack";
> + simple-audio-card,routing =
> + "MIC_IN", "Mic Jack",
> + "Mic Jack", "Mic Bias",
> + "Headphone Jack", "HP_OUT";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&sai2>;
> + };
> +
> + dailink_master: simple-audio-card,codec {
> + sound-dai = <&sgtl5000>;
> + clocks = <&clks IMX6UL_CLK_SAI2>;
> + };
> + };
> };
>
> &i2c1 {
> --
> 1.9.1
>
--
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^ permalink raw reply
* Re: [PATCH v3 2/9] ARM: dts: imx6ul-geam: Add Sound card with codec node
From: Shawn Guo @ 2017-04-07 13:19 UTC (permalink / raw)
To: Jagan Teki
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Sascha Hauer, Fabio Estevam,
Matteo Lisi, Michael Trimarchi, Jagan Teki
In-Reply-To: <1491501735-1649-3-git-send-email-jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
On Thu, Apr 06, 2017 at 11:32:08PM +0530, Jagan Teki wrote:
> From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
>
> Add support for Sound card and related codec(via i2c1) nodes
> on Engicam GEAM6UL variant module boards.
>
> Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Matteo Lisi <matteo.lisi-4s7YQHO/iPVBDgjK7y7TUQ@public.gmane.org>
> Cc: Michael Trimarchi <michael-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
> Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
> ---
> Changes for v3:
> - Replace fsl,imx-audio-sgtl5000 and use simple-audio-card
> Changes for v2:
> - Use proper [label:] node-name[@unit-address] for codec
> - Remove incorrect codec property 'wlf,shared-lrclk'
> - Remove 'gpr' from sound card node
>
> arch/arm/boot/dts/imx6ul-geam-kit.dts | 12 ++++++++++++
> arch/arm/boot/dts/imx6ul-geam.dtsi | 26 ++++++++++++++++++++++++++
Same question here: why is sgtl5000 added to imx6ul-geam-kit.dts, while
sound code that references to sgtl5000 is added to imx6ul-geam.dtsi?
Shawn
> 2 files changed, 38 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6ul-geam-kit.dts b/arch/arm/boot/dts/imx6ul-geam-kit.dts
> index 142e60c..02edcba 100644
> --- a/arch/arm/boot/dts/imx6ul-geam-kit.dts
> +++ b/arch/arm/boot/dts/imx6ul-geam-kit.dts
> @@ -58,6 +58,18 @@
> status = "okay";
> };
>
> +&i2c1 {
> + sgtl5000: codec@a {
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + clocks = <&clks IMX6UL_CLK_OSC>;
> + clock-names = "mclk";
> + VDDA-supply = <®_3p3v>;
> + VDDIO-supply = <®_3p3v>;
> + VDDD-supply = <®_1p8v>;
> + };
> +};
> +
> &lcdif {
> display = <&display0>;
> status = "okay";
> diff --git a/arch/arm/boot/dts/imx6ul-geam.dtsi b/arch/arm/boot/dts/imx6ul-geam.dtsi
> index eb94d95..3bc3238 100644
> --- a/arch/arm/boot/dts/imx6ul-geam.dtsi
> +++ b/arch/arm/boot/dts/imx6ul-geam.dtsi
> @@ -87,6 +87,32 @@
> regulator-always-on;
> regulator-boot-on;
> };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "imx6ul-geam-sgtl5000";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <&dailink_master>;
> + simple-audio-card,frame-master = <&dailink_master>;
> + simple-audio-card,widgets =
> + "Microphone", "Mic Jack",
> + "Line", "Line In",
> + "Line", "Line Out",
> + "Headphone", "Headphone Jack";
> + simple-audio-card,routing =
> + "MIC_IN", "Mic Jack",
> + "Mic Jack", "Mic Bias",
> + "Headphone Jack", "HP_OUT";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&sai2>;
> + };
> +
> + dailink_master: simple-audio-card,codec {
> + sound-dai = <&sgtl5000>;
> + clocks = <&clks IMX6UL_CLK_SAI2>;
> + };
> + };
> };
>
> &can1 {
> --
> 1.9.1
>
--
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^ permalink raw reply
* Re: [PATCH v3 3/9] ARM: dts: imx6qdl-icore: Add Sound card with codec node
From: Shawn Guo @ 2017-04-07 13:23 UTC (permalink / raw)
To: Jagan Teki
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Sascha Hauer, Fabio Estevam,
Matteo Lisi, Michael Trimarchi, Jagan Teki
In-Reply-To: <1491501735-1649-4-git-send-email-jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
On Thu, Apr 06, 2017 at 11:32:09PM +0530, Jagan Teki wrote:
> From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
>
> Add support for Sound card and related codec(via i2c1) nodes
> on below Engicam module boards.
> - i.CoreM6 DualLite/Solo Starter kit
> - i.CoreM6 Quad/Dual Starter kit
> - i.CoreM6 Quad/Dual OpenFrame Cap touch 10.1
> - i.CoreM6 Quad/Dual OpenFrame Cap touch 12.3
>
> Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Matteo Lisi <matteo.lisi-4s7YQHO/iPVBDgjK7y7TUQ@public.gmane.org>
> Cc: Michael Trimarchi <michael-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
> Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
> ---
> Changes for v3:
> - Replace fsl,imx-audio-sgtl5000 and use simple-audio-card
> Changes for v2:
> - Use proper [label:] node-name[@unit-address] for codec
>
> arch/arm/boot/dts/imx6dl-icore.dts | 11 +++++++
> arch/arm/boot/dts/imx6q-icore-ofcap10.dts | 11 +++++++
> arch/arm/boot/dts/imx6q-icore-ofcap12.dts | 11 +++++++
> arch/arm/boot/dts/imx6q-icore.dts | 11 +++++++
> arch/arm/boot/dts/imx6qdl-icore.dtsi | 48 +++++++++++++++++++++++++++++++
Why cannot you just add sgtl5000 node into dtsi rather than keeping the
same copy for 4 dts files?
Shawn
> 5 files changed, 92 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts
> index 6de83c7..0562ce4 100644
> --- a/arch/arm/boot/dts/imx6dl-icore.dts
> +++ b/arch/arm/boot/dts/imx6dl-icore.dts
> @@ -57,3 +57,14 @@
> &can2 {
> status = "okay";
> };
> +
> +&i2c3 {
> + sgtl5000: codec@a {
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + clocks = <&clks IMX6QDL_CLK_CKO>;
> + VDDA-supply = <®_2p5v>;
> + VDDIO-supply = <®_3p3v>;
> + VDDD-supply = <®_1p8v>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
> index 49b60ca..f63b87f 100644
> --- a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
> +++ b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
> @@ -50,6 +50,17 @@
> compatible = "engicam,imx6-icore", "fsl,imx6q";
> };
>
> +&i2c3 {
> + sgtl5000: codec@a {
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + clocks = <&clks IMX6QDL_CLK_CKO>;
> + VDDA-supply = <®_2p5v>;
> + VDDIO-supply = <®_3p3v>;
> + VDDD-supply = <®_1p8v>;
> + };
> +};
> +
> &ldb {
> status = "okay";
>
> diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap12.dts b/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
> index 9e230f5..68ca828 100644
> --- a/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
> +++ b/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
> @@ -50,6 +50,17 @@
> compatible = "engicam,imx6-icore", "fsl,imx6q";
> };
>
> +&i2c3 {
> + sgtl5000: codec@a {
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + clocks = <&clks IMX6QDL_CLK_CKO>;
> + VDDA-supply = <®_2p5v>;
> + VDDIO-supply = <®_3p3v>;
> + VDDD-supply = <®_1p8v>;
> + };
> +};
> +
> &ldb {
> status = "okay";
>
> diff --git a/arch/arm/boot/dts/imx6q-icore.dts b/arch/arm/boot/dts/imx6q-icore.dts
> index 5613dd9..1ae7294 100644
> --- a/arch/arm/boot/dts/imx6q-icore.dts
> +++ b/arch/arm/boot/dts/imx6q-icore.dts
> @@ -67,6 +67,17 @@
> };
> };
>
> +&i2c3 {
> + sgtl5000: codec@a {
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + clocks = <&clks IMX6QDL_CLK_CKO>;
> + VDDA-supply = <®_2p5v>;
> + VDDIO-supply = <®_3p3v>;
> + VDDD-supply = <®_1p8v>;
> + };
> +};
> +
> &ldb {
> status = "okay";
>
> diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
> index 56d0c5d..1bd7cdb 100644
> --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
> @@ -55,6 +55,25 @@
> default-brightness-level = <7>;
> };
>
> + reg_1p8v: regulator-1p8v {
> + compatible = "regulator-fixed";
> + regulator-name = "1P8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> +
> + reg_2p5v: regulator-3p3v {
> + compatible = "regulator-fixed";
> + regulator-name = "2P5V";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> reg_3p3v: regulator-3p3v {
> compatible = "regulator-fixed";
> regulator-name = "3P3V";
> @@ -87,6 +106,31 @@
> #clock-cells = <0>;
> clock-frequency = <25000000>; /* 25MHz for example */
> };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "imx6qdl-icore-sgtl5000";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <&dailink_master>;
> + simple-audio-card,frame-master = <&dailink_master>;
> + simple-audio-card,widgets =
> + "Microphone", "Mic Jack",
> + "Line", "Line In",
> + "Line", "Line Out",
> + "Headphone", "Headphone Jack";
> + simple-audio-card,routing =
> + "MIC_IN", "Mic Jack",
> + "Mic Jack", "Mic Bias",
> + "Headphone Jack", "HP_OUT";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&ssi1>;
> + };
> +
> + dailink_master: simple-audio-card,codec {
> + sound-dai = <&sgtl5000>;
> + };
> + };
> };
>
> &can1 {
> @@ -149,6 +193,10 @@
> status = "okay";
> };
>
> +&ssi1 {
> + status = "okay";
> +};
> +
> &uart4 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_uart4>;
> --
> 1.9.1
>
--
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/2] leds: Add driver for Qualcomm LPG
From: Pavel Machek @ 2017-04-07 13:32 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Jacek Anaszewski, Rob Herring, Richard Purdie, linux-kernel,
linux-leds, linux-arm-msm, Mark Rutland, devicetree
In-Reply-To: <20170403190032.GX20094@minitux>
[-- Attachment #1: Type: text/plain, Size: 1608 bytes --]
Hi!
> > In both RGB and pattern approaches we should assess
> > if it is acceptable to provide a pattern for trigger name,
> > e.g. blink-pattern-{num_intervals}.
> >
> > If so, then "echo transition-pattern-15" would create a directory
> > e.g. transition_intervals with files interval_0 to interval_14,
> > that could be adjusted by userspace.
>
> Having a RGB-trigger that proxy a accepts a userspace request of a
> brightness-tripple and sets the brightness on the individual associated
> LEDs sounds reasonable - but should probably be generalized to any
> number of LEDs.
Well.. Generalizing for any number of leds would be nice -- because
hardware can do that. OTOH, if we do that, we'll not have a place
where to do "white-adjustment".
> A slightly related matter is the question on how to use a single LED for
> multiple trigger sources, e.g. how do I get a single LED to show
> activity of two MMCs?.
We normally don't do that. We'd either have a trigger for a single
MMC, or trigger of all the MMCs..
> For the patterns I don't know how a trigger for this would look like,
> how would setting the pattern of a trigger be propagated down to the
> hardware?
Well... I'm not sure if we _want_ to do triggers for
patterns. LED triggers change rather quickly (100 times a second?) so
doing them in kernel makes sense. Patterns take 10s of seconds, so we
do not need to handle them in kernel.
Thanks,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply
* Re: Re: [PATCH v2 1/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver
From: Maxime Ripard @ 2017-04-07 13:38 UTC (permalink / raw)
To: Priit Laes
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng, Russell King,
Chen-Yu Tsai, Mark Rutland, Rob Herring, Stephen Boyd,
Michael Turquette, Philipp Zabel
In-Reply-To: <20170404200919.GA22159-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 4589 bytes --]
Hi Priit,
On Tue, Apr 04, 2017 at 08:09:19PM +0000, Priit Laes wrote:
> > > +/* Not documented on A10 */
> > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-sata", "pll-periph",
> > > + 0x028, BIT(14), 0);
> >
> > The rate doesn't come from pll-periph directly, does it?
>
> So it uses hosc (24MHz parent clock) instead of pll-periph?
I never looked too much at this, but it looks more like the input is
pll-periph-sata itself.
> > > +/* Undocumented on A10 */
> > > +static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
> > > + 0x088, 8, 3, 0);
> > > +/* Undocumented on A10 */
> > > +static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
> > > + 0x088, 20, 3, 0);
> >
> > The A10 doesn't have them.
>
> Are you sure? Although, they weren't listed in datasheet, they are defined
> in the sun4i-a10.dtsi:
>
> mmc0_clk: clk@01c20088 {
> #clock-cells = <1>;
> compatible = "allwinner,sun4i-a10-mmc-clk";
> reg = <0x01c20088 0x4>;
> clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> clock-output-names = "mmc0",
> "mmc0_output",
> "mmc0_sample";
> };
Yes, those clocks have been introduced in the A20, but we didn't find
out until much later, which is why there's still left overs in the
DT. We're not using them in the driver for the A10 either (but we do
for the A20, obviously).
> > > +/* TODO: Check whether A10 actually supports osc32k as 4th parent? */
> > > +static const char *const ir_parents_sun4i[] = { "hosc", "pll-periph",
> > > + "pll-ddr-other" };
> >
> > What does the BSP say about this?
>
> sun7i datasheet mentions osc32k, but BSP code for sun4i, sun5i and sun7i
> is identical and supports only 3 first parents without osc32k.
Ok. Leave the TODO for now, we'll fix it if relevant.
> > > +/* Undocumented on A10 */
> > > +static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", audio_parents,
> > > + 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
> >
> > This doesn't seem to exist at all on the A10
>
> Wasn't listed in datasheet, but it's in BSP and also in sun4i-a10.dtsi:
>
> spdif_clk: clk@01c200c0 {
> #clock-cells = <0>;
> compatible = "allwinner,sun4i-a10-mod1-clk";
> reg = <0x01c200c0 0x4>;
> clocks = <&pll2 SUN4I_A10_PLL2_8X>,
> <&pll2 SUN4I_A10_PLL2_4X>,
> <&pll2 SUN4I_A10_PLL2_2X>,
> <&pll2 SUN4I_A10_PLL2_1X>;
> clock-output-names = "spdif";
> };
Ack.
> > > +/*
> > > + * TODO: SATA clock also supports external clock as parent via BIT(24)
> > > + * The external clock is probably an optional crystal or oscillator
> > > + * that can be connected to the SATA-CLKM / SATA-CLKP pins.
> > > + */
> > > +static SUNXI_CCU_GATE(sata_clk, "sata", "pll-periph-sata",
> > > + 0x0c8, BIT(31), 0);
> >
> > The rate won't be good here either. This is supposed to be 100MHz.
>
> Hmm.. I tested SATA with Cubietruck. Or what do you mean?
As long as you don't have any dependency on the rate itself, as long
as the gate is opened, I expect it to work. But the rate itself will
be reported wrong.
> > > +static const char *const csi_isp_parents[] = { "pll-video0", "pll-ve",
> > > + "pll-ddr-other", "pll-sata" };
> > > +
> > > +static SUNXI_CCU_M_WITH_MUX_GATE(csi_isp_clk, "csi-isp",
> > > + csi_isp_parents,
> > > + 0x120, 0, 4, 24, 2, BIT(31), 0);
> >
> > We've been calling it sclk in the other SoC iirc. Any particular
> > reason to call it differently?
>
> It's called ISP in BSP and A10 manual.
> In A20 it's indeed Special Clock Register (SCLK).
Let's call it SCLK too then, for consistency.
> > > +static const char *const out_parents[] = { "hosc", "osc32k", "hosc" };
> > > +static SUNXI_CCU_MP_WITH_MUX_GATE(out_a_clk, "out-a", out_parents,
> > > + 0x1f0, 8, 5, 20, 2, 24, 2, BIT(31), 0);
> > > +static SUNXI_CCU_MP_WITH_MUX_GATE(out_b_clk, "out-b", out_parents,
> > > + 0x1f4, 8, 5, 20, 2, 24, 2, BIT(31), 0);
> >
> > There's a fixed pre-divider on the first hosc of 750.
>
> Nice catch.
>
> So it should be something like this:
>
> [snip]
> static const char *const out_parents[] = { "osc24M", "osc32k", "osc24M" };
> static const struct ccu_mux_fixed_prediv out_prediv = {
> .index = 0, .div = 750
> };
I think it shoud still be hosc (or at least, the name that you used
for the gate controlling the 24MHz oscillator input).
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH] ARM: dts: hi6220: Reset the mmc hosts
From: Daniel Lezcano @ 2017-04-07 13:45 UTC (permalink / raw)
To: xuwei5; +Cc: guodong.xu, linux-arm-kernel, stable, devicetree, linux-kernel
In-Reply-To: <1489673004-11075-1-git-send-email-daniel.lezcano@linaro.org>
On Thu, Mar 16, 2017 at 03:03:24PM +0100, Daniel Lezcano wrote:
> The MMC hosts could be left in an unconsistent or uninitialized state from
> the firmware. Instead of assuming, the firmware did the right things, let's
> reset the host controllers.
>
> This change fixes a bug when the mmc2/sdio is initialized leading to a hung
> task:
>
> [ 242.704294] INFO: task kworker/7:1:675 blocked for more than 120 seconds.
> [ 242.711129] Not tainted 4.9.0-rc8-00017-gcf0251f #3
> [ 242.716571] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
> [ 242.724435] kworker/7:1 D 0 675 2 0x00000000
> [ 242.729973] Workqueue: events_freezable mmc_rescan
> [ 242.734796] Call trace:
> [ 242.737269] [<ffff00000808611c>] __switch_to+0xa8/0xb4
> [ 242.742437] [<ffff000008d07c04>] __schedule+0x1c0/0x67c
> [ 242.747689] [<ffff000008d08254>] schedule+0x40/0xa0
> [ 242.752594] [<ffff000008d0b284>] schedule_timeout+0x1c4/0x35c
> [ 242.758366] [<ffff000008d08e38>] wait_for_common+0xd0/0x15c
> [ 242.763964] [<ffff000008d09008>] wait_for_completion+0x28/0x34
> [ 242.769825] [<ffff000008a1a9f4>] mmc_wait_for_req_done+0x40/0x124
> [ 242.775949] [<ffff000008a1ab98>] mmc_wait_for_req+0xc0/0xf8
> [ 242.781549] [<ffff000008a1ac3c>] mmc_wait_for_cmd+0x6c/0x84
> [ 242.787149] [<ffff000008a26610>] mmc_io_rw_direct_host+0x9c/0x114
> [ 242.793270] [<ffff000008a26aa0>] sdio_reset+0x34/0x7c
> [ 242.798347] [<ffff000008a1d46c>] mmc_rescan+0x2fc/0x360
>
> [ ... ]
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> ---
Hi Xu,
gentle ping.
Thanks.
-- Daniel
> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> index 470461d..1e5129b 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> @@ -774,6 +774,7 @@
> clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
> clock-names = "ciu", "biu";
> resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
> + reset-names = "reset";
> bus-width = <0x8>;
> vmmc-supply = <&ldo19>;
> pinctrl-names = "default";
> @@ -797,6 +798,7 @@
> clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
> clock-names = "ciu", "biu";
> resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
> + reset-names = "reset";
> vqmmc-supply = <&ldo7>;
> vmmc-supply = <&ldo10>;
> bus-width = <0x4>;
> @@ -815,6 +817,7 @@
> clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
> clock-names = "ciu", "biu";
> resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
> + reset-names = "reset";
> bus-width = <0x4>;
> broken-cd;
> pinctrl-names = "default", "idle";
> --
> 1.9.1
>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* Re: [PATCH v3] clk: stm32h7: Add stm32h743 clock driver
From: kbuild test robot @ 2017-04-07 13:51 UTC (permalink / raw)
Cc: Mark Rutland, amelie.delaunay, Michael Turquette, Lee Jones,
linux-clk, daniel.thompson, Nicolas Pitre, Russell King,
linux-arm-kernel, devicetree, Alexandre Torgue, Arnd Bergmann,
Rob Herring, ludovic.barre, radoslaw.pietrzyk, andrea.merello,
olivier.bideau, Stephen Boyd, linux-kernel, kbuild-all,
Maxime Coquelin, gabriel.fernandez
In-Reply-To: <1491309014-13967-1-git-send-email-gabriel.fernandez@st.com>
[-- Attachment #1: Type: text/plain, Size: 2156 bytes --]
Hi Gabriel,
[auto build test WARNING on clk/clk-next]
[also build test WARNING on v4.11-rc5 next-20170406]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/gabriel-fernandez-st-com/clk-stm32h7-Add-stm32h743-clock-driver/20170405-100654
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm-stm32_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All warnings (new ones prefixed by >>):
drivers/clk/clk-stm32h7.c: In function 'ready_gate_clk_disable':
>> drivers/clk/clk-stm32h7.c:250:2: warning: this 'if' clause does not guard... [-Wmisleading-indentation]
if (rgate->backup_domain && dbp_status)
^~
drivers/clk/clk-stm32h7.c:253:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the 'if'
clk_gate_ops.disable(hw);
^~~~~~~~~~~~
vim +/if +250 drivers/clk/clk-stm32h7.c
234 return bit_status;
235 }
236
237 static void ready_gate_clk_disable(struct clk_hw *hw)
238 {
239 struct clk_gate *gate = to_clk_gate(hw);
240 struct stm32_ready_gate *rgate = to_ready_gate_clk(gate);
241 int dbp_status;
242 int bit_status;
243 unsigned int timeout = RGATE_TIMEOUT;
244
245 if (!ready_gate_clk_is_enabled(hw))
246 return;
247
248 dbp_status = is_enable_power_domain_write_protection();
249
> 250 if (rgate->backup_domain && dbp_status)
251 disable_power_domain_write_protection();
252
253 clk_gate_ops.disable(hw);
254
255 do {
256 bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy));
257
258 if (bit_status)
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
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[-- Attachment #3: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 0/4] arm64: renesas: enable M3ULCB board peripherals
From: Simon Horman @ 2017-04-07 13:52 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Vladimir Barinov, Magnus Damm, Rob Herring, Mark Rutland,
devicetree@vger.kernel.org, Linux-Renesas, Sjoerd Simons
In-Reply-To: <CAMuHMdX9caECvsBnfUQhbQKdW_uGJ_VXAUksMMXw7EAGP8QUCQ@mail.gmail.com>
On Thu, Apr 06, 2017 at 11:53:45AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Fri, Mar 17, 2017 at 11:02 PM, Sjoerd Simons
> <sjoerd.simons@collabora.co.uk> wrote:
> > On Thu, 2017-01-26 at 17:53 +0300, Vladimir Barinov wrote:
> >> This adds the folowing:
> >> - R8A7796 SoC based M3ULCB board peripherals
> >>
> >> Vladimir Barinov (4):
> >> [1/4] arm64: dts: m3ulcb: enable I2C
> >> [2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map
I have queued up the above two patches.
> >> [3/4] arm64: dts: m3ulcb: enable EthernetAVB
Please update the above patch to reflect the changes made in
ef3f08c83fd1 ("arm64: dts: r8a7796: salvator-x: Fix EthernetAVB PHY timing")
> >> [4/4] arm64: dts: m3ulcb: enable HS200 for eMMC
I will look at queuing this up in the near future
with other HS200 enablement patches.
> > Seems these didn't hit -next just yet, for this series (tested on a
> > M3ULCB)
> >
> > Tested-By: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
>
> It seems this series is still pending? Any reason (not) to apply it?
Sorry for the extended delay.
^ permalink raw reply
* Re: [PATCH v4 06/14] MIPS: jz4740: DTS: Add nodes for ingenic pinctrl and gpio drivers
From: Paul Cercueil @ 2017-04-07 13:57 UTC (permalink / raw)
To: Linus Walleij
Cc: Alexandre Courbot, Rob Herring, Mark Rutland, Ralf Baechle,
Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, James Hogan,
linux-gpio, devicetree, linux-kernel, Linux MIPS, linux-mmc,
linux-mtd, linux-pwm, linux-fbdev
In-Reply-To: <CACRpkdbXe1Xxk93jqLXBdEDwWOnWD+CkZrqvok-PcmWxzBbSZA@mail.gmail.com>
Le 2017-04-07 11:44, Linus Walleij a écrit :
> On Sun, Apr 2, 2017 at 10:42 PM, Paul Cercueil <paul@crapouillou.net>
> wrote:
>
>> For a description of the pinctrl devicetree node, please read
>> Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
>>
>> For a description of the gpio devicetree nodes, please read
>> Documentation/devicetree/bindings/gpio/ingenic,gpio.txt
>>
>> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
>> ---
>> arch/mips/boot/dts/ingenic/jz4740.dtsi | 61
>> ++++++++++++++++++++++++++++++++++
>> 1 file changed, 61 insertions(+)
>>
>> v2: Changed the devicetree bindings to match the new driver
>> v3: No changes
>> v4: Update the bindings for the v4 version of the drivers
> (...)
>
>> + pinctrl: ingenic-pinctrl@10010000 {
>> + compatible = "ingenic,jz4740-pinctrl";
>> + reg = <0x10010000 0x400>;
>> +
>> + gpa: gpio-controller@0 {
>> + compatible = "ingenic,gpio-bank-a",
>> "ingenic,jz4740-gpio";
>
> As Sergei and Rob notes, the bank compatible properties look
> a bit strange. Especially if they are all the same essentially.
>
> I like Sergei's idea to simply use the reg property if what you want
> is really a unique ID number. What do you think about this?
>
> Yours,
> Linus Walleij
I think the 'reg' property makes more sense, yes. I'll fix this in the
v5, this
week-end. Do you think it can go in 4.12?
Thanks,
-Paul
^ permalink raw reply
* [PATCH v2 0/2] dmaengine: Add DW AXI DMAC driver
From: Eugeniy Paltsev @ 2017-04-07 14:04 UTC (permalink / raw)
To: dmaengine-u79uwXL29TY76Z2rM5mHXA
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-snps-arc-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Dan Williams,
Vinod Koul, Rob Herring, Andy Shevchenko, Alexey Brodkin,
Eugeniy Paltsev
This patch series add support for the DW AXI DMAC controller.
DW AXI DMAC is a part of upcoming development board from Synopsys.
In this driver implementation only DMA_MEMCPY and DMA_SG transfers
are supported.
Changes for v2:
* Use async version of runtime PM get/put callbacks.
* Use atomic_t (and corresponding operations) for allocated descriptors
counter.
* Use GFP_NOWAIT flag for allocating dma descriptors in "dma_pool_zalloc"
instead of GFP_ATOMIC flag.
* Add kernel-doc style comments for the irq enum, cleanup.
Changes for v1:
* Implement Runtime PM (the driver can operate with or without
Runtime PM support)
* Move submitting new txn to interrupt handler from tasklet
* Free IRQ manually in driver remove function
* Add 64 bit support
* Rid of subsys_initcall
* Use dev_vdbg instead dev_dbg in some places
* Rid of C99 style comments
* Add IP version to DT compatible string
Note:
* I left "is_paused" variable untouched. I checked the drivers which
have 'enum dma_status' field in their channel data structures -
there is no much sense to add enum to this driver channel data
structure - it will be used only for determinating is channel
paused or not.
* I left preparation of SG list according to max data width and
max block size in dma_chan_prep_dma_sg function.
* I left axi_chan_is_hw_enable assert untouched because it is
HW per-channel assert. It can't be managed by runtime PM.
Changes for v0:
* Switch to virt-dma API (according to previous RFC)
* Small fixies according to previous RFC
* Add DT bindings
Eugeniy Paltsev (2):
dt-bindings: Document the Synopsys DW AXI DMA bindings
dmaengine: Add DW AXI DMAC driver
.../devicetree/bindings/dma/snps,axi-dw-dmac.txt | 34 +
drivers/dma/Kconfig | 10 +
drivers/dma/Makefile | 1 +
drivers/dma/axi_dma_platform.c | 1044 ++++++++++++++++++++
drivers/dma/axi_dma_platform.h | 119 +++
drivers/dma/axi_dma_platform_reg.h | 220 +++++
6 files changed, 1428 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/snps,axi-dw-dmac.txt
create mode 100644 drivers/dma/axi_dma_platform.c
create mode 100644 drivers/dma/axi_dma_platform.h
create mode 100644 drivers/dma/axi_dma_platform_reg.h
--
2.5.5
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^ permalink raw reply
* [PATCH v2 1/2] dt-bindings: Document the Synopsys DW AXI DMA bindings
From: Eugeniy Paltsev @ 2017-04-07 14:04 UTC (permalink / raw)
To: dmaengine
Cc: devicetree, Andy Shevchenko, Vinod Koul, Alexey Brodkin,
linux-kernel, Rob Herring, Dan Williams, linux-snps-arc,
Eugeniy Paltsev
In-Reply-To: <1491573855-1039-1-git-send-email-Eugeniy.Paltsev@synopsys.com>
This patch adds documentation of device tree bindings for the Synopsys
DesignWare AXI DMA controller.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/dma/snps,axi-dw-dmac.txt | 34 ++++++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/snps,axi-dw-dmac.txt
diff --git a/Documentation/devicetree/bindings/dma/snps,axi-dw-dmac.txt b/Documentation/devicetree/bindings/dma/snps,axi-dw-dmac.txt
new file mode 100644
index 0000000..21666fe
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/snps,axi-dw-dmac.txt
@@ -0,0 +1,34 @@
+* Synopsys DesignWare AXI DMA Controller
+
+Required properties:
+- compatible: "snps,axi-dma-1.01a"
+- reg: Address range of the DMAC registers. This should include
+ all of the per-channel registers.
+- interrupt: Should contain the DMAC interrupt number.
+- interrupt-parent: Should be the phandle for the interrupt controller
+ that services interrupts for this device.
+- dma-channels: Number of channels supported by hardware.
+- snps,dma-masters: Number of AXI masters supported by the hardware.
+- snps,data-width: Maximum AXI data width supported by hardware.
+ (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
+- snps,priority: Priority of channel. Array size is equal to the number of
+ dma-channels. Priority value must be programmed within [0:dma-channels-1]
+ range. (0 - minimum priority)
+- snps,block-size: Maximum block size supported by the controller channel.
+ Array size is equal to the number of dma-channels.
+
+Example:
+
+dmac: dma-controller@80000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x80000 0x400>;
+ clocks = <&core_clk>;
+ interrupt-parent = <&intc>;
+ interrupts = <27>;
+
+ dma-channels = <4>;
+ snps,dma-masters = <2>;
+ snps,data-width = <3>;
+ snps,block-size = <4096 4096 4096 4096>;
+ snps,priority = <0 1 2 3>;
+};
--
2.5.5
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