* Re: [PATCHv3 00/10] Nokia H4+ support
From: Sebastian Reichel @ 2017-04-10 23:10 UTC (permalink / raw)
To: Marcel Holtmann
Cc: Greg Kroah-Hartman, Gustavo F. Padovan, Johan Hedberg,
Samuel Thibault, Pavel Machek, Tony Lindgren, Jiri Slaby,
Mark Rutland, open list:BLUETOOTH DRIVERS,
linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
David S. Miller, Rob Herring
In-Reply-To: <CAL_Jsq+NU3M5yuBpK1UGgzCVvq0eABMApCqEe3_d5+tDaABsgQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
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Hi,
On Wed, Apr 05, 2017 at 01:16:58PM -0500, Rob Herring wrote:
> On Fri, Mar 31, 2017 at 8:33 AM, Greg Kroah-Hartman
> <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org> wrote:
> > On Wed, Mar 29, 2017 at 11:33:26PM +0200, Marcel Holtmann wrote:
> >> Hi Rob,
> >>
> >> >> Here is PATCHv3 for the Nokia bluetooth patchset. I addressed all comments from
> >> >> Rob and Pavel regarding the serdev patches and dropped the *.dts patches, since
> >> >> they were queued by Tony. I also changed the patch order, so that the serdev
> >> >> patches come first. All of them have Acked-by from Rob, so I think it makes
> >> >> sense to merge them to serdev subsystem (now) and provide an immutable branch
> >> >> for the bluetooth subsystem.
> >> >
> >> > Greg doesn't read cover letters generally and since the serdev patches
> >> > are Cc rather than To him, he's probably not planning to pick them up.
> >>
> >> I wonder actually if we should merge all of these via bluetooth-next
> >> tree with proper Ack from Greg. However it would be good to also get
> >> buy in from Dave for merging this ultimately through net-next.
> >
> > I don't really care where it goes. I can take the whole thing in my
> > tty/serial tree now if no one objects and I get an ack from the relevant
> > maintainers {hint...}
>
> I think it is better if it goes thru BT tree. I have another driver
> converted that is dependent on this series. There's a couple other
> serdev changes on the list too, but this shouldn't depend on them.
Is this waiting for something, or could it be queued to
bluetooth-next then? It would be nice to finally have
this in 4.12 :)
-- Sebastian
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^ permalink raw reply
* Re: [alsa-devel] [PATCH v4 6/9] ASoC: add snd_soc_get_dai_id()
From: Kuninori Morimoto @ 2017-04-10 23:59 UTC (permalink / raw)
To: Rob Herring; +Cc: Linux-DT, Linux-ALSA, Mark Brown, Simon
In-Reply-To: <CAL_JsqLp1cg_iJ1V9bk=GW6CF5BmsqkLc04D6EcQcaFaAAL+2g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi Rob
> > ports {
> > port { endpoint }; /* ID = 0 */
> > port { endpoint }; /* ID = 1 */
> > port { endpoint }; /* ID = 2 */
>
> These ports are audio channels? If these are 3 separate data paths,
> then this is correct. If you have a single data path with multiple
> connections (e.g. a mux), then that should be a single port with
> multiple endpoints. For example, a design that routes the same I2S
> interface to HDMI and a codec and their use is mutually exclusive. I
> imagine you will need to support both.
Thanks.
Maybe we wil need it in the future, but not yet supported now.
> The pattern I prefer to see calling graph functions is that drivers
> are specific about which port and endpoint number for a parent node
> they want. Not just searching the graph for any match.
This related feature will be needed on HDMI sound support,
because it has not only sound port/endpoint.
> > 1 question
> >
> > It will support HDMI sound feature, thus I separated
> > it into OF-graph (= this patch-set) and HDMI (= next patch-set).
> > Should I merge it ?
>
> I think so if it affects the functions here. It seems better to let
> the driver controlling the DAI determine the id mapping than trying to
> do it in the core.
At this point, this feature (= HDMI sound) is not needed for OF-graph
patch-set. Thus, as-is is OK for OF-graph patch-set ?
Best regards
---
Kuninori Morimoto
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* Re: [PATCH V2] PM / OPP: Use - instead of @ for DT entries
From: Masahiro Yamada @ 2017-04-11 1:13 UTC (permalink / raw)
To: Viresh Kumar
Cc: Rafael Wysocki, Chanwoo Choi, MyungJoo Ham, Kyungmin Park,
Kukjin Kim, Krzysztof Kozlowski, Javier Martinez Canillas,
Viresh Kumar, Nishanth Menon, Stephen Boyd, Benoît Cousson,
Tony Lindgren, Rob Herring, Mark Rutland, Daniel Mack,
Haojian Zhuang, Robert Jarzmik, Maxime Ripard, Chen-Yu Tsai,
linaro-kernel
In-Reply-To: <70e7c7ee13722ab9c73cb073f88502eaf1ada5f5.1491816050.git.viresh.kumar@linaro.org>
Hi Viresh,
2017-04-10 18:21 GMT+09:00 Viresh Kumar <viresh.kumar@linaro.org>:
> Compiling the DT file with W=1, DTC warns like follows:
>
> Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
> unit name, but no reg property
>
> Fix this by replacing '@' with '-' as the OPP nodes will never have a
> "reg" property.
>
> Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Suggested-by: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> (sunxi)
> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (uniphier)
Thank you!
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* Re: [PATCH 2/2] ARM: dts: imx7: add USDHC NAND clock to SDHC instances
From: Dong Aisheng @ 2017-04-11 2:59 UTC (permalink / raw)
To: Stefan Agner
Cc: Fabio Estevam, Shawn Guo, Sascha Hauer, Stephen Boyd,
Dong Aisheng, Fabio Estevam, robh+dt, Mark Rutland,
linux-arm-kernel, devicetree, linux-clk, linux-kernel
In-Reply-To: <c95a7f535296623bdd4e4a640b3c27f5@agner.ch>
On Tue, Apr 04, 2017 at 07:36:01PM -0700, Stefan Agner wrote:
> On 2017-04-04 19:15, Fabio Estevam wrote:
> > On Sun, Apr 2, 2017 at 2:02 PM, Fabio Estevam <festevam@gmail.com> wrote:
> >> On Sat, Apr 1, 2017 at 1:15 AM, Stefan Agner <stefan@agner.ch> wrote:
> >>
> >>> IMX7D_IPG_ROOT_CLK is currently not a valid clock in upstream... So we
> >>> would have to add it to the clock driver first.
> >>>
> >>> I guess we could/should add it anyway at one point? But probably also as
> >>> init on, just to make sure Linux does not disable it since it is
> >>> currently used by several IPs implicitly.
> >>
> >> Yes, I made a previous attempt do add IMX7D_IPG_ROOT_CLK and it did
> >> not work as I did not put it in the init_on clock list.
> >>
> >> Will submit a new patch adding it to init_on, thanks.
> >
> > I thought that adding IMX7D_IPG_ROOT_CLK would do the trick, but the
> > patch below also causes the kernel to not boot:
> >
> > --- a/drivers/clk/imx/clk-imx7d.c
> > +++ b/drivers/clk/imx/clk-imx7d.c
> > @@ -386,7 +386,7 @@ static int const clks_init_on[] __initconst = {
> > IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK,
> > IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK,
> > IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK,
> > - IMX7D_AHB_CHANNEL_ROOT_CLK,
> > + IMX7D_AHB_CHANNEL_ROOT_CLK, IMX7D_IPG_ROOT_CLK,
> > };
> >
> > static struct clk_onecell_data clk_data;
> > @@ -788,7 +788,7 @@ static void __init imx7d_clocks_init(struct
> > device_node *ccm_node)
> > clks[IMX7D_WRCLK_ROOT_DIV] =
> > imx_clk_divider2("wrclk_post_div", "wrclk_pre_div", base + 0xbd00, 0,
> > 6);
> > clks[IMX7D_CLKO1_ROOT_DIV] =
> > imx_clk_divider2("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0,
> > 6);
> > clks[IMX7D_CLKO2_ROOT_DIV] =
> > imx_clk_divider2("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0,
> > 6);
> > -
> > + clks[IMX7D_IPG_ROOT_CLK] = imx_clk_divider2("ipg_root_clk",
> > "ahb_root_clk", base + 0x9080, 0, 2);
> > clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate4("arm_a7_root_clk",
> > "arm_a7_div", base + 0x4000, 0);
> > clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate4("arm_m4_root_clk",
> > "arm_m4_div", base + 0x4010, 0);
> > clks[IMX7D_ARM_M0_ROOT_CLK] = imx_clk_gate4("arm_m0_root_clk",
> > "arm_m0_div", base + 0x4020, 0);
>
> Hm, imx_clk_divider2 sets CLK_SET_RATE_PARENT, maybe that influences the
> parent?
>
> I guess we actually don't want the clock framework to change that clock
> rate, not sure whether we can freeze it or similar.
>
This is caused by ahb_root_clk gets disabled accidently and system hangs.
Because this patch defines ipg_root_clk earlier before its parent
(ahb_root_clk) got registered, then it will be marked as a orphan clk
temporarily. Until the parent ahb_root_clk got registered, the clk core
will reparent it to the newly found parent. (see __clk_core_init() function).
Due to CLK_SET_RATE_PARENT flag, the ahb clk will be enabled during
set_parent operation and then disabled after that.
Then system hang cause we still get no chance to run init_on clks.
I just send out a proper fix patch with correct register sequence.
Probably we can switch all imx clk driver to CLK_IS_CRITICAL for critical
clocks in the future, but that's another thing to do later.
Stefan,
I think you can just resend your series based on my patches.
Regards
Dong Aisheng
> --
> Stefan
^ permalink raw reply
* Re: [PATCH v1 3/3] nvmem: dt: document SNVS LPGPR binding
From: Oleksij Rempel @ 2017-04-11 4:36 UTC (permalink / raw)
To: Rob Herring, Oleksij Rempel
Cc: Srinivas Kandagatla, Maxime Ripard, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170410182235.pmobyxn6kvyvcwsj@rob-hp-laptop>
Hi,
On 04/10/2017 08:22 PM, Rob Herring wrote:
> On Thu, Apr 06, 2017 at 09:31:07AM +0200, Oleksij Rempel wrote:
>> Documenation bindings for the Low Power General Purpose Registe
>
> s/Registe/Register/
>
>> available on i.MX6 SoCs in the Secure Non-Volatile Storage.
>>
>> Signed-off-by: Oleksij Rempel <o.rempel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>> Cc: Srinivas Kandagatla <srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> Cc: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> ---
>> Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>>
>> diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>> new file mode 100644
>> index 000000000000..9a8be1a2d12e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>> @@ -0,0 +1,15 @@
>> +Device tree bindings for Low Power General Purpose Registe found in i.MX6Q/D
>> +Secure Non-Volatile Storage.
>> +
>> +Required properties:
>> +- compatible: should be one of
>> + "fsl,imx6q-snvs-lpgpr" (i.MX6Q/D/DL/S).
>> +- offset: Should contain the offset relative to syscon parrent node.
>
> typo
ok.
> +- regmap: Should contain a phandle pointing to syscon.
>> +
>> +Example:
>> + snvs_lpgpr: snvs-lpgpr {
>> + compatible = "fsl,imx6q-snvs-lpgpr";
>> + regmap = <&snvs>;
>> + offset = <0x68>;
>
> Why does this need to be in DT? Is something going to refer to this
> node? If not, the &snvs node should be enough information for the OS.
Jes, it is refereed by other driver.
Thank you.
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^ permalink raw reply
* Re: [PATCH v2 01/13] devicetree/bindings: display: Document common panel properties
From: Laurent Pinchart @ 2017-04-11 5:12 UTC (permalink / raw)
To: Emil Velikov
Cc: Laurent Pinchart, ML dri-devel, linux-renesas-soc, devicetree,
Tomi Valkeinen
In-Reply-To: <CACvgo52dydV5fpcDDPnFaRN32uxoeitvazwPpxOs4wOqg0=45A@mail.gmail.com>
Hi Emil,
On Sunday 09 Apr 2017 12:47:01 Emil Velikov wrote:
> Hi Laurent,
>
> Pardon for reviving this old thread. I've noticed a couple of things
> which might want some attention.
>
> On 19 November 2016 at 03:28, Laurent Pinchart wrote:
> > +
> > +- panel-timing: Most display panels are restricted to a single resolution
> > and + require specific display timings. The panel-timing subnode
> > expresses those + timings as specified in the timing subnode section of
> > the display timing + bindings defined in
> > + Documentation/devicetree/bindings/display/display-timing.txt.
>
> Cannot find such a file in linux-next. Perhaps you meant
> Documentation/devicetree/bindings/display/panel/display-timing.txt?
Oops. My bad, I'll fix that. Thank you for noticing it.
> Documentation/devicetree/bindings/display/panel/panel.txt includes a
> "rotation" property, which we might want to fold here.
I believe that panel.txt and panel-common.txt were added concurrently. We
should indeed merge the two.
--
Regards,
Laurent Pinchart
^ permalink raw reply
* RE: [v3, 1/7] mmc: sdhci-of-esdhc: add peripheral clock support
From: Y.B. Lu @ 2017-04-11 5:14 UTC (permalink / raw)
To: Adrian Hunter, linux-mmc@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
ulf.hansson@linaro.org, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon
Cc: Xiaobo Xie
In-Reply-To: <a8810e0a-95fa-a590-6827-15031ff52886@intel.com>
Hi Adrian,
> -----Original Message-----
> From: Adrian Hunter [mailto:adrian.hunter@intel.com]
> Sent: Monday, April 10, 2017 8:36 PM
> To: Y.B. Lu; linux-mmc@vger.kernel.org; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; ulf.hansson@linaro.org; Rob Herring;
> Mark Rutland; Catalin Marinas; Will Deacon
> Cc: Xiaobo Xie
> Subject: Re: [v3, 1/7] mmc: sdhci-of-esdhc: add peripheral clock support
>
> On 27/03/17 10:49, Yangbo Lu wrote:
> > eSDHC could select peripheral clock or platform clock as clock source
> > by the PCS bit of eSDHC Control Register, and this bit couldn't be
> > reset by software reset for all. In default, the platform clock is
> > used. But we have to use peripheral clock since it has a higher
> > frequency to support eMMC
> > HS200 mode and SD UHS-I mode. This patch is to add peripheral clock
> > support and use it instead of platform clock if it's declared in eSDHC
> dts node.
> >
> > Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
>
> Apart from minor comments:
>
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>
> > ---
> > Changes for v2:
> > - None
> > Changes for v3:
> > - None
> > ---
> > drivers/mmc/host/sdhci-esdhc.h | 1 +
> > drivers/mmc/host/sdhci-of-esdhc.c | 70
> > +++++++++++++++++++++++++++++++++++++--
> > 2 files changed, 69 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sdhci-esdhc.h
> > b/drivers/mmc/host/sdhci-esdhc.h index ece8b37..5343fc0 100644
> > --- a/drivers/mmc/host/sdhci-esdhc.h
> > +++ b/drivers/mmc/host/sdhci-esdhc.h
> > @@ -54,6 +54,7 @@
> >
> > /* Control Register for DMA transfer */
> > #define ESDHC_DMA_SYSCTL 0x40c
> > +#define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
> > #define ESDHC_DMA_SNOOP 0x00000040
> >
> > #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */ diff --git
> > a/drivers/mmc/host/sdhci-of-esdhc.c
> > b/drivers/mmc/host/sdhci-of-esdhc.c
> > index ff37e74..7ce1caf 100644
> > --- a/drivers/mmc/host/sdhci-of-esdhc.c
> > +++ b/drivers/mmc/host/sdhci-of-esdhc.c
> > @@ -19,6 +19,7 @@
> > #include <linux/delay.h>
> > #include <linux/module.h>
> > #include <linux/sys_soc.h>
> > +#include <linux/clk.h>
> > #include <linux/mmc/host.h>
> > #include "sdhci-pltfm.h"
> > #include "sdhci-esdhc.h"
> > @@ -30,6 +31,7 @@ struct sdhci_esdhc {
> > u8 vendor_ver;
> > u8 spec_ver;
> > bool quirk_incorrect_hostver;
> > + unsigned int peripheral_clock;
> > };
> >
> > /**
> > @@ -414,15 +416,25 @@ static int esdhc_of_enable_dma(struct sdhci_host
> > *host) static unsigned int esdhc_of_get_max_clock(struct sdhci_host
> > *host) {
> > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> > + struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
> >
> > - return pltfm_host->clock;
> > + if (esdhc->peripheral_clock)
> > + return esdhc->peripheral_clock;
> > + else
> > + return pltfm_host->clock;
> > }
> >
> > static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
> > {
> > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> > + struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
> > + unsigned int clock;
> >
> > - return pltfm_host->clock / 256 / 16;
> > + if (esdhc->peripheral_clock)
> > + clock = esdhc->peripheral_clock;
> > + else
> > + clock = pltfm_host->clock;
> > + return clock / 256 / 16;
> > }
> >
> > static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int
> > clock) @@ -512,6 +524,33 @@ static void
> esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
> > sdhci_writel(host, ctrl, ESDHC_PROCTL); }
> >
> > +static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
> > +{
> > + u32 val;
> > + u32 timeout;
> > +
> > + val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
> > +
> > + if (enable)
> > + val |= ESDHC_CLOCK_SDCLKEN;
> > + else
> > + val &= ~ESDHC_CLOCK_SDCLKEN;
> > +
> > + sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
> > +
> > + timeout = 20;
> > + val = ESDHC_CLOCK_STABLE;
> > + while (!(sdhci_readl(host, ESDHC_PRSSTAT) & val)) {
> > + if (timeout == 0) {
> > + pr_err("%s: Internal clock never stabilised.\n",
> > + mmc_hostname(host->mmc));
> > + break;
> > + }
> > + timeout--;
> > + mdelay(1);
>
> If the time to stabilize is much less that 1 ms then this loop can waste
> time. Have a look at the change in sdhci.c.
>
[Lu Yangbo-B47093] Thanks a lot. The method in sdhci.c is really better.
I will send next version to use it soon.
Currently another place in esdhc driver could also change to use this method. I will send a separate patch for that later.
> > + }
> > +}
> > +
> > static void esdhc_reset(struct sdhci_host *host, u8 mask) {
> > sdhci_reset(host, mask);
> > @@ -613,6 +652,9 @@ static void esdhc_init(struct platform_device
> > *pdev, struct sdhci_host *host) {
> > struct sdhci_pltfm_host *pltfm_host;
> > struct sdhci_esdhc *esdhc;
> > + struct device_node *np;
> > + struct clk *clk;
> > + u32 val;
> > u16 host_ver;
> >
> > pltfm_host = sdhci_priv(host);
> > @@ -626,6 +668,30 @@ static void esdhc_init(struct platform_device
> *pdev, struct sdhci_host *host)
> > esdhc->quirk_incorrect_hostver = true;
> > else
> > esdhc->quirk_incorrect_hostver = false;
> > +
> > + np = pdev->dev.of_node;
> > + clk = of_clk_get(np, 0);
>
> Should there be a clk_put somewhere?
[Lu Yangbo-B47093] Will add it after driver gets the clock value.
>
> > + if (!IS_ERR(clk)) {
> > + /*
> > + * esdhc->peripheral_clock would be assigned with a value
> > + * which is eSDHC base clock when use periperal clock.
> > + * For ls1046a, the clock value got by common clk API is
> > + * peripheral clock while the eSDHC base clock is 1/2
> > + * peripheral clock.
> > + */
> > + if (of_device_is_compatible(np, "fsl,ls1046a-esdhc"))
> > + esdhc->peripheral_clock = clk_get_rate(clk) / 2;
> > + else
> > + esdhc->peripheral_clock = clk_get_rate(clk);
> > + }
> > +
> > + if (esdhc->peripheral_clock) {
> > + esdhc_clock_enable(host, false);
> > + val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
> > + val |= ESDHC_PERIPHERAL_CLK_SEL;
> > + sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
> > + esdhc_clock_enable(host, true);
> > + }
> > }
> >
> > static int sdhci_esdhc_probe(struct platform_device *pdev)
> >
^ permalink raw reply
* RE: [v3, 2/7] mmc: sdhci-of-esdhc: add support for signal voltage switch
From: Y.B. Lu @ 2017-04-11 5:20 UTC (permalink / raw)
To: Adrian Hunter, linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, Rob Herring,
Mark Rutland, Catalin Marinas, Will Deacon
Cc: Xiaobo Xie
In-Reply-To: <e7e08c87-ecd6-ab24-636c-7707a5172b08-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Hi Adrian,
> -----Original Message-----
> From: linux-mmc-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org [mailto:linux-mmc-
> owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org] On Behalf Of Adrian Hunter
> Sent: Monday, April 10, 2017 8:38 PM
> To: Y.B. Lu; linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org;
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org; Rob Herring;
> Mark Rutland; Catalin Marinas; Will Deacon
> Cc: Xiaobo Xie
> Subject: Re: [v3, 2/7] mmc: sdhci-of-esdhc: add support for signal
> voltage switch
>
> On 27/03/17 10:49, Yangbo Lu wrote:
> > eSDHC supports signal voltage switch from 3.3v to 1.8v by
> > eSDHC_PROCTL[VOLT_SEL] bit. This bit changes the value of output
> > signal SDHC_VS, and there must be a control circuit out of eSDHC to
> > change the signal voltage according to SDHC_VS output signal.
> >
> > Signed-off-by: Yangbo Lu <yangbo.lu-3arQi8VN3Tc@public.gmane.org>
>
> Apart from minor comment below:
>
> Acked-by: Adrian Hunter <adrian.hunter-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
>
> > ---
> > Changes for v2:
> > - Used Adrain's method to support voltage switching:
> > host->mmc_host_ops.start_signal_voltage_switch =
> > esdhc_signal_voltage_switch; Changes for v3:
> > - Put .start_signal_voltage_switch assigning after IS_ERR(host)
> check.
> > ---
> > drivers/mmc/host/sdhci-esdhc.h | 1 +
> > drivers/mmc/host/sdhci-of-esdhc.c | 74
> > +++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 75 insertions(+)
> >
> > diff --git a/drivers/mmc/host/sdhci-esdhc.h
> > b/drivers/mmc/host/sdhci-esdhc.h index 5343fc0..6869567 100644
> > --- a/drivers/mmc/host/sdhci-esdhc.h
> > +++ b/drivers/mmc/host/sdhci-esdhc.h
> > @@ -37,6 +37,7 @@
> >
> > /* Protocol Control Register */
> > #define ESDHC_PROCTL 0x28
> > +#define ESDHC_VOLT_SEL 0x00000400
> > #define ESDHC_CTRL_4BITBUS (0x1 << 1)
> > #define ESDHC_CTRL_8BITBUS (0x2 << 1)
> > #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
> > diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
> > b/drivers/mmc/host/sdhci-of-esdhc.c
> > index 7ce1caf..a70499a 100644
> > --- a/drivers/mmc/host/sdhci-of-esdhc.c
> > +++ b/drivers/mmc/host/sdhci-of-esdhc.c
> > @@ -16,6 +16,7 @@
> > #include <linux/err.h>
> > #include <linux/io.h>
> > #include <linux/of.h>
> > +#include <linux/of_address.h>
> > #include <linux/delay.h>
> > #include <linux/module.h>
> > #include <linux/sys_soc.h>
> > @@ -559,6 +560,76 @@ static void esdhc_reset(struct sdhci_host *host,
> u8 mask)
> > sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); }
> >
> > +/* The SCFG, Supplemental Configuration Unit, provides SoC specific
> > + * configuration and status registers for the device. There is a
> > + * SDHC IO VSEL control register on SCFG for some platforms. It's
> > + * used to support SDHC IO voltage switching.
> > + */
> > +static const struct of_device_id scfg_device_ids[] = {
> > + { .compatible = "fsl,t1040-scfg", },
> > + { .compatible = "fsl,ls1012a-scfg", },
> > + { .compatible = "fsl,ls1046a-scfg", },
> > + {}
> > +};
> > +
> > +/* SDHC IO VSEL control register definition */
> > +#define SCFG_SDHCIOVSELCR 0x408
> > +#define SDHCIOVSELCR_TGLEN 0x80000000
> > +#define SDHCIOVSELCR_VSELVAL 0x60000000
> > +#define SDHCIOVSELCR_SDHC_VS 0x00000001
> > +
> > +static int esdhc_signal_voltage_switch(struct mmc_host *mmc,
> > + struct mmc_ios *ios)
> > +{
> > + struct sdhci_host *host = mmc_priv(mmc);
> > + struct device_node *scfg_node;
> > + void __iomem *scfg_base = NULL;
> > + u32 sdhciovselcr;
> > + u32 val;
> > +
> > + /*
> > + * Signal Voltage Switching is only applicable for Host Controllers
> > + * v3.00 and above.
> > + */
> > + if (host->version < SDHCI_SPEC_300)
> > + return 0;
> > +
> > + val = sdhci_readl(host, ESDHC_PROCTL);
> > +
> > + switch (ios->signal_voltage) {
> > + case MMC_SIGNAL_VOLTAGE_330:
> > + val &= ~ESDHC_VOLT_SEL;
> > + sdhci_writel(host, val, ESDHC_PROCTL);
> > + return 0;
> > + case MMC_SIGNAL_VOLTAGE_180:
> > + scfg_node = of_find_matching_node(NULL, scfg_device_ids);
> > + if (scfg_node)
> > + scfg_base = of_iomap(scfg_node, 0);
> > + if (scfg_base) {
> > + sdhciovselcr = SDHCIOVSELCR_TGLEN |
> > + SDHCIOVSELCR_VSELVAL;
> > + iowrite32be(sdhciovselcr,
> > + scfg_base + SCFG_SDHCIOVSELCR);
>
> In other places there is support for little endian also, so why not here?
[Lu Yangbo-B47093] The SCFG unit is always a big-endian module on both ARM and PPC QorIQ platforms.
There is little possibility to have little-endian in future.
>
> > +
> > + val |= ESDHC_VOLT_SEL;
> > + sdhci_writel(host, val, ESDHC_PROCTL);
> > + mdelay(5);
> > +
> > + sdhciovselcr = SDHCIOVSELCR_TGLEN |
> > + SDHCIOVSELCR_SDHC_VS;
> > + iowrite32be(sdhciovselcr,
> > + scfg_base + SCFG_SDHCIOVSELCR);
> > + iounmap(scfg_base);
> > + } else {
> > + val |= ESDHC_VOLT_SEL;
> > + sdhci_writel(host, val, ESDHC_PROCTL);
> > + }
> > + return 0;
> > + default:
> > + return 0;
> > + }
> > +}
> > +
> > #ifdef CONFIG_PM_SLEEP
> > static u32 esdhc_proctl;
> > static int esdhc_of_suspend(struct device *dev) @@ -714,6 +785,9 @@
> > static int sdhci_esdhc_probe(struct platform_device *pdev)
> > if (IS_ERR(host))
> > return PTR_ERR(host);
> >
> > + host->mmc_host_ops.start_signal_voltage_switch =
> > + esdhc_signal_voltage_switch;
> > +
> > esdhc_init(pdev, host);
> >
> > sdhci_get_of_property(pdev);
> >
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at
> http://vger.kernel.org/majordomo-info.html
--
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^ permalink raw reply
* RE: [v3, 0/7] Add SD UHS-I and eMMC HS200 support for eSDHC
From: Y.B. Lu @ 2017-04-11 5:24 UTC (permalink / raw)
To: Ulf Hansson
Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Adrian Hunter, Rob Herring,
Mark Rutland, Catalin Marinas, Will Deacon, Xiaobo Xie
In-Reply-To: <CAPDyKFpN-+7mxxeBHEELROWsn275Mec6unDHdnY3Gsz3oKT9pw@mail.gmail.com>
Hi Uffe and Adrian,
Thanks for your quick response.
I dropped the dts patches and would send the new version mmc patchset which addressed Adrian's comments.
The dts patches would be sent separately to arm soc and will not have new bindings/compatibles to discuss.
Thanks.
Best regards,
Yangbo Lu
> -----Original Message-----
> From: Ulf Hansson [mailto:ulf.hansson@linaro.org]
> Sent: Monday, April 10, 2017 6:49 PM
> To: Y.B. Lu
> Cc: linux-mmc@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Adrian Hunter; Rob Herring; Mark Rutland;
> Catalin Marinas; Will Deacon; Xiaobo Xie
> Subject: Re: [v3, 0/7] Add SD UHS-I and eMMC HS200 support for eSDHC
>
> On 10 April 2017 at 10:20, Y.B. Lu <yangbo.lu@nxp.com> wrote:
> > Hi Andrian and Uffe,
> >
> > Do you have any comments on MMC patches?
> > Could you help to merge the mmc patches if there is no changes
> requested?
>
> I am waiting for Adrian's acks.
>
> >
> > Regarding to the dts patches, I have some more platforms to support.
> > So I'd like to drop them currently, and send them all to arm mailing
> list for reviewing.
>
> If it's new bindings/compatibles, the DT doc changes needs to be
> discussed and agreed upon first. Actual changes to the DTS files, should
> preferably go via the arm soc tree.
>
> Kind regards
> Uffe
^ permalink raw reply
* [PATCH v2 2/3] ARM: dts: imx6qdl.dtsi: add "fsl, imx6q-snvs-lpgpr" node
From: Oleksij Rempel @ 2017-04-11 5:27 UTC (permalink / raw)
To: o.rempel; +Cc: devicetree, Rob Herring, Shawn Guo, linux-kernel,
linux-arm-kernel
In-Reply-To: <20170411052725.17464-1-o.rempel@pengutronix.de>
This node is for Low Power General Purpose Register which can
be used as Non-Volatile Storage.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6qdl.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 6d7bf6496117..8e90014705c3 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -768,6 +768,12 @@
mask = <0x60>;
status = "disabled";
};
+
+ snvs_lpgpr: snvs-lpgpr {
+ compatible = "fsl,imx6q-snvs-lpgpr";
+ regmap = <&snvs>;
+ offset = <0x68>;
+ };
};
epit1: epit@020d0000 { /* EPIT1 */
--
2.11.0
^ permalink raw reply related
* [PATCH v2 3/3] nvmem: dt: document SNVS LPGPR binding
From: Oleksij Rempel @ 2017-04-11 5:27 UTC (permalink / raw)
To: o.rempel
Cc: Srinivas Kandagatla, Maxime Ripard, Rob Herring, Mark Rutland,
devicetree, linux-kernel
In-Reply-To: <20170411052725.17464-1-o.rempel@pengutronix.de>
Documentation bindings for the Low Power General Purpose Register
available on i.MX6 SoCs in the Secure Non-Volatile Storage.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
new file mode 100644
index 000000000000..5399087a76d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
@@ -0,0 +1,15 @@
+Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D
+Secure Non-Volatile Storage.
+
+Required properties:
+- compatible: should be one of
+ "fsl,imx6q-snvs-lpgpr" (i.MX6Q/D/DL/S).
+- offset: Should contain the offset relative to syscon parent node.
+- regmap: Should contain a phandle pointing to syscon.
+
+Example:
+ snvs_lpgpr: snvs-lpgpr {
+ compatible = "fsl,imx6q-snvs-lpgpr";
+ regmap = <&snvs>;
+ offset = <0x68>;
+ };
--
2.11.0
^ permalink raw reply related
* Re: [PATCH v4 5/7] dt-bindings: display/panel: Add common rotation property
From: Laurent Pinchart @ 2017-04-11 5:29 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Noralf Trønnes, devicetree-u79uwXL29TY76Z2rM5mHXA,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170211184858.26421-6-noralf-L59+Z2yzLopAfugRpC6u6w@public.gmane.org>
Hi Noralf,
On Saturday 11 Feb 2017 19:48:56 Noralf Trønnes wrote:
> Display panels can be oriented many ways, especially in the embedded
> world. The rotation property is a way to describe this orientation.
> The counter clockwise direction is chosen because that's what fbdev
> and drm use.
>
> Signed-off-by: Noralf Trønnes <noralf-L59+Z2yzLopAfugRpC6u6w@public.gmane.org>
> Acked-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>
> Changes since version 3:
> - Changed display/display.txt -> display/panel/panel.txt
>
> Documentation/devicetree/bindings/display/panel/panel.txt | 4 ++++
We now have both Documentation/devicetree/bindings/display/panel/panel.txt and
Documentation/devicetree/bindings/display/panel/panel-common.txt as they have
been merged concurrently without being aware of each other. Would you mind if
I moved this property to panel-common.txt ?
I would also like to document the property in a bit more details to avoid
confusion about the rotation direction, as "display rotation" could be
interpreted as the angle by which the display output has to be rotated to
obtain an upside-up image. What would you think of the following, am I
overdoing it, or is it even more confusing ?
- rotation: Panels are commonly mounted rotated, with their native orientation
not aligned with the device's orientation. The rotation property specifies the
angle in degrees between the panel's orientation and the device's orientation
(corresponding to a counter-clockwise rotation of the panel). Valid values are
0, 90, 180 and 270.
> 1 file changed, 4 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/panel/panel.txt
>
> diff --git a/Documentation/devicetree/bindings/display/panel/panel.txt
> b/Documentation/devicetree/bindings/display/panel/panel.txt new file mode
> 100644
> index 0000000..e2e6867
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/panel/panel.txt
> @@ -0,0 +1,4 @@
> +Common display properties
> +-------------------------
> +
> +- rotation: Display rotation in degrees counter clockwise (0,90,180,270)
--
Regards,
Laurent Pinchart
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^ permalink raw reply
* 6f58284e66: BUG: kernel hang in boot stage
From: kernel test robot @ 2017-04-11 5:30 UTC (permalink / raw)
To: Stephen Rothwell
Cc: LKP, linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-ia64-u79uwXL29TY76Z2rM5mHXA,
linux-alpha-u79uwXL29TY76Z2rM5mHXA,
lvs-devel-u79uwXL29TY76Z2rM5mHXA,
linux-doc-u79uwXL29TY76Z2rM5mHXA,
intel-wired-lan-qjLDD68F18P21nG7glBr7A,
linux-can-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
netdev-u79uwXL29TY76Z2rM5mHXA, wfg-VuQAYsv1563Yd54FQh9/CA
[-- Attachment #1: Type: text/plain, Size: 5860 bytes --]
Greetings,
0day kernel testing robot got the below dmesg and the first bad commit is
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
commit 6f58284e666261162b2c95fdd8608f5e247e9a38
Merge: 7fd97bca bf74b20
Author: Stephen Rothwell <sfr-3FnU+UHB4dNDw9hX6IcOSA@public.gmane.org>
AuthorDate: Mon Apr 10 10:06:42 2017 +1000
Commit: Stephen Rothwell <sfr-3FnU+UHB4dNDw9hX6IcOSA@public.gmane.org>
CommitDate: Mon Apr 10 10:06:42 2017 +1000
Merge remote-tracking branch 'net-next/master'
7fd97bca68 Merge remote-tracking branch 'dlm/next'
bf74b20d00 Revert "rtnl: Add support for netdev event to link messages"
6f58284e66 Merge remote-tracking branch 'net-next/master'
f8c97bdb49 Add linux-next specific files for 20170410
+-------------------------------------------------+------------+------------+------------+---------------+
| | 7fd97bca68 | bf74b20d00 | 6f58284e66 | next-20170410 |
+-------------------------------------------------+------------+------------+------------+---------------+
| boot_successes | 42 | 38 | 0 | 0 |
| boot_failures | 0 | 0 | 17 | 17 |
| BUG:kernel_hang_in_boot_stage | 0 | 0 | 17 | 11 |
| BUG:kernel_reboot-without-warning_in_boot_stage | 0 | 0 | 0 | 6 |
+-------------------------------------------------+------------+------------+------------+---------------+
[ 0.000000] ACPI: RSDP 0x00000000000F6930 000014 (v00 BOCHS )
[ 0.000000] ACPI: RSDT 0x000000001FFE1936 000030 (v01 BOCHS BXPCRSDT 00000001 BXPC 00000001)
[ 0.000000] ACPI: FACP 0x000000001FFE180A 000074 (v01 BOCHS BXPCFACP 00000001 BXPC 00000001)
# HH:MM RESULT GOOD BAD GOOD_BUT_DIRTY DIRTY_NOT_BAD
git bisect start f8c97bdb49832d2b0edaa0c05db873aa2f6101ff 39da7c509acff13fc8cb12ec1bb20337c988ed36 --
git bisect bad af6d4e29c13fd47ef3d1b4d96b7f781aa7534413 # 05:19 B 0 3 14 0 Merge remote-tracking branch 'drm-panel/drm/panel/for-next'
git bisect good 8a41837405da3919179983b830eb648b65954797 # 05:40 G 13 0 0 0 Merge remote-tracking branch 'xtensa/xtensa-for-next'
git bisect good 1635d3d77b290e99090a4e7f613009cc68531bb8 # 06:04 G 13 0 0 0 Merge remote-tracking branch 'v4l-dvb/master'
git bisect bad 89c15a058190c83af2d029fad4de33f542bcfb42 # 06:28 B 0 2 13 0 Merge remote-tracking branch 'ipsec-next/master'
git bisect good 3d5657773c2ccdbeff13e2db374a1fd3b3e36722 # 07:06 G 12 0 0 0 Merge remote-tracking branch 'thermal/next'
git bisect good 3700d2a55af503f43ae0e4595c92557bcb89046e # 07:24 G 13 0 0 0 Merge remote-tracking branch 'ieee1394/for-next'
git bisect good 7fd97bca680b4ceedebf194f8316ae6c2b60ce01 # 08:32 G 13 0 0 0 Merge remote-tracking branch 'dlm/next'
git bisect bad 6f58284e666261162b2c95fdd8608f5e247e9a38 # 08:55 B 0 1 12 0 Merge remote-tracking branch 'net-next/master'
git bisect good 00ecfb3b34b69dd702dee1bd6de6fc100be384db # 09:12 G 12 0 0 0 netvsc: remove unnecessary lock on shutdown
git bisect good df1c631648c55bfb247339279f9bc573c7f283f4 # 09:54 G 12 0 0 0 net: mpls: Limit memory allocation for mpls_route
git bisect good b404127879471c38ad13a246ce5dec156f60f828 # 10:14 G 12 0 0 0 Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue
git bisect good 15ed8a47ff0571dd268e37002511993b47e996bd # 10:34 G 12 0 0 0 qede: Add support for ingress headroom
git bisect good e8c5f7231cc03153fee1b5fcb173585354c08ee8 # 10:53 G 12 0 0 0 i40e: Swap use of pf->flags and pf->hw_disabled_flags for ATR Eviction
git bisect good 0c264588b5de50353e4a1ce0c2521576426dd89d # 11:15 G 13 0 0 0 liquidio: fix VF incorrectly indicating that it successfully set its VLAN
git bisect good ca9ec0888d631c446040a7fab9985afdeb4f73f3 # 11:39 G 13 0 0 0 i40e/i40evf: Add support for padding start of frames
git bisect good 417d978fa532b61b89f0c3ccbd9cdb51090ea032 # 11:59 G 13 0 0 0 Merge branch 'dsa-receive-path-simplifications'
git bisect good 0492b71c42f76b6019ef5fe686a7cb253dded09c # 12:29 G 13 0 0 0 Merge branch '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue
git bisect good bf74b20d00b13919db7ae5d1015636e76f56f6ae # 12:45 G 13 0 0 0 Revert "rtnl: Add support for netdev event to link messages"
# first bad commit: [6f58284e666261162b2c95fdd8608f5e247e9a38] Merge remote-tracking branch 'net-next/master'
git bisect good 7fd97bca680b4ceedebf194f8316ae6c2b60ce01 # 12:50 G 38 0 0 0 Merge remote-tracking branch 'dlm/next'
git bisect good bf74b20d00b13919db7ae5d1015636e76f56f6ae # 12:54 G 38 0 0 0 Revert "rtnl: Add support for netdev event to link messages"
# extra tests with CONFIG_DEBUG_INFO_REDUCED
git bisect bad 6f58284e666261162b2c95fdd8608f5e247e9a38 # 13:26 B 0 13 24 0 Merge remote-tracking branch 'net-next/master'
# extra tests on HEAD of linux-next/master
git bisect bad f8c97bdb49832d2b0edaa0c05db873aa2f6101ff # 13:27 B 0 11 31 6 Add linux-next specific files for 20170410
# extra tests on tree/branch linux-next/master
git bisect bad f8c97bdb49832d2b0edaa0c05db873aa2f6101ff # 13:27 B 0 11 31 6 Add linux-next specific files for 20170410
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/lkp Intel Corporation
[-- Attachment #2: dmesg-quantal-kbuild-13:20170411085629:x86_64-randconfig-r0-04110023:4.11.0-rc6-03112-g6f58284e:2.gz --]
[-- Type: application/gzip, Size: 2163 bytes --]
[-- Attachment #3: reproduce-quantal-kbuild-13:20170411085629:x86_64-randconfig-r0-04110023:4.11.0-rc6-03112-g6f58284e:2 --]
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#!/bin/bash
kernel=$1
kvm=(
qemu-system-x86_64
-enable-kvm
-cpu kvm64
-kernel $kernel
-m 512
-smp 2
-device e1000,netdev=net0
-netdev user,id=net0
-boot order=nc
-no-reboot
-watchdog i6300esb
-watchdog-action debug
-rtc base=localtime
-serial stdio
-display none
-monitor null
)
append=(
root=/dev/ram0
hung_task_panic=1
debug
apic=debug
sysrq_always_enabled
rcupdate.rcu_cpu_stall_timeout=100
net.ifnames=0
printk.devkmsg=on
panic=-1
softlockup_panic=1
nmi_watchdog=panic
oops=panic
load_ramdisk=2
prompt_ramdisk=0
drbd.minor_count=8
systemd.log_level=err
ignore_loglevel
earlyprintk=ttyS0,115200
console=ttyS0,115200
console=tty0
vga=normal
rw
drbd.minor_count=8
)
"${kvm[@]}" -append "${append[*]}"
[-- Attachment #4: config-4.11.0-rc6-03112-g6f58284e --]
[-- Type: text/plain, Size: 96814 bytes --]
#
# Automatically generated file; DO NOT EDIT.
# Linux/x86_64 4.11.0-rc6 Kernel Configuration
#
CONFIG_64BIT=y
CONFIG_X86_64=y
CONFIG_X86=y
CONFIG_INSTRUCTION_DECODER=y
CONFIG_OUTPUT_FORMAT="elf64-x86-64"
CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig"
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_MMU=y
CONFIG_ARCH_MMAP_RND_BITS_MIN=28
CONFIG_ARCH_MMAP_RND_BITS_MAX=32
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_HAS_CPU_RELAX=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_HAVE_SETUP_PER_CPU_AREA=y
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_ZONE_DMA32=y
CONFIG_AUDIT_ARCH=y
CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_KASAN_SHADOW_OFFSET=0xdffffc0000000000
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_EXTABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y
#
# General setup
#
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE=""
# CONFIG_COMPILE_TEST is not set
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
# CONFIG_KERNEL_GZIP is not set
# CONFIG_KERNEL_BZIP2 is not set
CONFIG_KERNEL_LZMA=y
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
# CONFIG_KERNEL_LZ4 is not set
CONFIG_DEFAULT_HOSTNAME="(none)"
# CONFIG_SWAP is not set
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_FHANDLE=y
# CONFIG_USELIB is not set
# CONFIG_AUDIT is not set
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_DOMAIN_DEBUG=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
CONFIG_CLOCKSOURCE_WATCHDOG=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
CONFIG_GENERIC_CMOS_UPDATE=y
#
# Timers subsystem
#
CONFIG_HZ_PERIODIC=y
# CONFIG_NO_HZ_IDLE is not set
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
#
# CPU/Task time and stats accounting
#
CONFIG_VIRT_CPU_ACCOUNTING=y
# CONFIG_TICK_CPU_ACCOUNTING is not set
CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
# CONFIG_IRQ_TIME_ACCOUNTING is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
#
# RCU Subsystem
#
CONFIG_PREEMPT_RCU=y
CONFIG_RCU_EXPERT=y
CONFIG_SRCU=y
# CONFIG_TASKS_RCU is not set
CONFIG_RCU_STALL_COMMON=y
CONFIG_CONTEXT_TRACKING=y
# CONFIG_CONTEXT_TRACKING_FORCE is not set
CONFIG_RCU_FANOUT=64
CONFIG_RCU_FANOUT_LEAF=16
# CONFIG_TREE_RCU_TRACE is not set
CONFIG_RCU_BOOST=y
CONFIG_RCU_KTHREAD_PRIO=1
CONFIG_RCU_BOOST_DELAY=500
CONFIG_RCU_NOCB_CPU=y
# CONFIG_RCU_NOCB_CPU_NONE is not set
# CONFIG_RCU_NOCB_CPU_ZERO is not set
CONFIG_RCU_NOCB_CPU_ALL=y
CONFIG_BUILD_BIN2C=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=17
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
CONFIG_MEMCG=y
# CONFIG_BLK_CGROUP is not set
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
# CONFIG_RT_GROUP_SCHED is not set
# CONFIG_CGROUP_PIDS is not set
# CONFIG_CGROUP_RDMA is not set
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
# CONFIG_CPUSETS is not set
# CONFIG_CGROUP_DEVICE is not set
# CONFIG_CGROUP_CPUACCT is not set
# CONFIG_CGROUP_PERF is not set
# CONFIG_CGROUP_BPF is not set
CONFIG_CGROUP_DEBUG=y
# CONFIG_SOCK_CGROUP_DATA is not set
# CONFIG_CHECKPOINT_RESTORE is not set
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
CONFIG_SCHED_AUTOGROUP=y
# CONFIG_SYSFS_DEPRECATED is not set
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
CONFIG_INITRAMFS_COMPRESSION=".gz"
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_HAVE_PCSPKR_PLATFORM=y
CONFIG_BPF=y
# CONFIG_EXPERT is not set
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_POSIX_TIMERS=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_PRINTK=y
CONFIG_PRINTK_NMI=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_PCSPKR_PLATFORM=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_BPF_SYSCALL=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_ADVISE_SYSCALLS=y
# CONFIG_USERFAULTFD is not set
CONFIG_PCI_QUIRKS=y
CONFIG_MEMBARRIER=y
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set
#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_MEMCG_SYSFS_ON is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
CONFIG_SLAB_FREELIST_RANDOM=y
# CONFIG_SYSTEM_DATA_VERIFICATION is not set
# CONFIG_PROFILING is not set
CONFIG_TRACEPOINTS=y
CONFIG_HAVE_OPROFILE=y
CONFIG_OPROFILE_NMI_TIMER=y
# CONFIG_KPROBES is not set
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_UPROBES=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_KPROBES_ON_FTRACE=y
CONFIG_HAVE_NMI=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
CONFIG_HAVE_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_GCC_PLUGINS=y
# CONFIG_GCC_PLUGINS is not set
CONFIG_HAVE_CC_STACKPROTECTOR=y
# CONFIG_CC_STACKPROTECTOR is not set
CONFIG_CC_STACKPROTECTOR_NONE=y
# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
# CONFIG_CC_STACKPROTECTOR_STRONG is not set
CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_SOFT_DIRTY=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_HAVE_EXIT_THREAD=y
CONFIG_ARCH_MMAP_RND_BITS=28
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8
CONFIG_HAVE_COPY_THREAD_TLS=y
CONFIG_HAVE_STACK_VALIDATION=y
# CONFIG_HAVE_ARCH_HASH is not set
# CONFIG_ISA_BUS_API is not set
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
# CONFIG_CPU_NO_EFFICIENT_FFS is not set
CONFIG_HAVE_ARCH_VMAP_STACK=y
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_MODULE_COMPRESS=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
CONFIG_MODULE_COMPRESS_XZ=y
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_ZONED=y
# CONFIG_BLK_CMDLINE_PARSER is not set
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_SQ=y
CONFIG_BLK_WBT_MQ=y
CONFIG_BLK_DEBUG_FS=y
CONFIG_BLK_SED_OPAL=y
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_AMIGA_PARTITION=y
CONFIG_MSDOS_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_BLOCK_COMPAT=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_FREEZER=y
#
# Processor type and features
#
CONFIG_ZONE_DMA=y
# CONFIG_SMP is not set
CONFIG_X86_FEATURE_NAMES=y
CONFIG_X86_FAST_FEATURE_TESTS=y
# CONFIG_X86_X2APIC is not set
CONFIG_X86_MPPARSE=y
# CONFIG_GOLDFISH is not set
# CONFIG_INTEL_RDT_A is not set
# CONFIG_X86_EXTENDED_PLATFORM is not set
# CONFIG_X86_INTEL_LPSS is not set
# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
CONFIG_IOSF_MBI=m
# CONFIG_IOSF_MBI_DEBUG is not set
CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_SCHED_OMIT_FRAME_POINTER is not set
CONFIG_HYPERVISOR_GUEST=y
CONFIG_PARAVIRT=y
# CONFIG_PARAVIRT_DEBUG is not set
# CONFIG_XEN is not set
CONFIG_KVM_GUEST=y
# CONFIG_KVM_DEBUG_FS is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
CONFIG_PARAVIRT_CLOCK=y
CONFIG_NO_BOOTMEM=y
# CONFIG_MK8 is not set
# CONFIG_MPSC is not set
# CONFIG_MCORE2 is not set
# CONFIG_MATOM is not set
CONFIG_GENERIC_CPU=y
CONFIG_X86_INTERNODE_CACHE_SHIFT=6
CONFIG_X86_L1_CACHE_SHIFT=6
CONFIG_X86_TSC=y
CONFIG_X86_CMPXCHG64=y
CONFIG_X86_CMOV=y
CONFIG_X86_MINIMUM_CPU_FAMILY=64
CONFIG_X86_DEBUGCTLMSR=y
CONFIG_CPU_SUP_INTEL=y
CONFIG_CPU_SUP_AMD=y
CONFIG_CPU_SUP_CENTAUR=y
CONFIG_HPET_TIMER=y
CONFIG_DMI=y
# CONFIG_GART_IOMMU is not set
# CONFIG_CALGARY_IOMMU is not set
CONFIG_SWIOTLB=y
CONFIG_IOMMU_HELPER=y
CONFIG_NR_CPUS=1
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_UP_LATE_INIT=y
CONFIG_X86_LOCAL_APIC=y
CONFIG_X86_IO_APIC=y
CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
CONFIG_X86_MCE=y
CONFIG_X86_MCE_INTEL=y
CONFIG_X86_MCE_AMD=y
CONFIG_X86_MCE_THRESHOLD=y
# CONFIG_X86_MCE_INJECT is not set
CONFIG_X86_THERMAL_VECTOR=y
#
# Performance monitoring
#
CONFIG_PERF_EVENTS_INTEL_UNCORE=y
CONFIG_PERF_EVENTS_INTEL_RAPL=y
CONFIG_PERF_EVENTS_INTEL_CSTATE=y
CONFIG_PERF_EVENTS_AMD_POWER=m
# CONFIG_VM86 is not set
CONFIG_X86_16BIT=y
CONFIG_X86_ESPFIX64=y
CONFIG_X86_VSYSCALL_EMULATION=y
CONFIG_I8K=y
# CONFIG_MICROCODE is not set
CONFIG_X86_MSR=m
CONFIG_X86_CPUID=m
CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_X86_DIRECT_GBPAGES=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_ALLOC_MEM_MAP_TOGETHER=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_MEMORY_BALLOON=y
# CONFIG_COMPACTION is not set
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
CONFIG_MEMORY_FAILURE=y
# CONFIG_HWPOISON_INJECT is not set
# CONFIG_TRANSPARENT_HUGEPAGE is not set
CONFIG_NEED_PER_CPU_KM=y
# CONFIG_CLEANCACHE is not set
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
CONFIG_CMA_AREAS=7
# CONFIG_ZPOOL is not set
CONFIG_ZBUD=y
CONFIG_ZSMALLOC=y
CONFIG_PGTABLE_MAPPING=y
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_ARCH_SUPPORTS_DEFERRED_STRUCT_PAGE_INIT=y
CONFIG_IDLE_PAGE_TRACKING=y
# CONFIG_X86_PMEM_LEGACY is not set
CONFIG_X86_CHECK_BIOS_CORRUPTION=y
CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y
CONFIG_X86_RESERVE_LOW=64
CONFIG_MTRR=y
CONFIG_MTRR_SANITIZER=y
CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
CONFIG_X86_PAT=y
CONFIG_ARCH_USES_PG_UNCACHED=y
CONFIG_ARCH_RANDOM=y
CONFIG_X86_SMAP=y
CONFIG_X86_INTEL_MPX=y
# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set
# CONFIG_EFI is not set
# CONFIG_SECCOMP is not set
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
CONFIG_HZ_1000=y
CONFIG_HZ=1000
# CONFIG_SCHED_HRTICK is not set
# CONFIG_KEXEC is not set
# CONFIG_KEXEC_FILE is not set
CONFIG_CRASH_DUMP=y
CONFIG_PHYSICAL_START=0x1000000
CONFIG_RELOCATABLE=y
CONFIG_RANDOMIZE_BASE=y
CONFIG_X86_NEED_RELOCS=y
CONFIG_PHYSICAL_ALIGN=0x200000
CONFIG_RANDOMIZE_MEMORY=y
CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0x0
# CONFIG_COMPAT_VDSO is not set
# CONFIG_LEGACY_VSYSCALL_NATIVE is not set
CONFIG_LEGACY_VSYSCALL_EMULATE=y
# CONFIG_LEGACY_VSYSCALL_NONE is not set
# CONFIG_CMDLINE_BOOL is not set
CONFIG_MODIFY_LDT_SYSCALL=y
CONFIG_HAVE_LIVEPATCH=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
#
# Power management and ACPI options
#
# CONFIG_SUSPEND is not set
# CONFIG_PM is not set
CONFIG_ACPI=y
CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
# CONFIG_ACPI_DEBUGGER is not set
# CONFIG_ACPI_PROCFS_POWER is not set
CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
# CONFIG_ACPI_VIDEO is not set
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_CPU_FREQ_PSS=y
CONFIG_ACPI_PROCESSOR_CSTATE=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_PROCESSOR=y
# CONFIG_ACPI_IPMI is not set
# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
CONFIG_ACPI_THERMAL=y
CONFIG_ACPI_CUSTOM_DSDT_FILE=""
# CONFIG_ACPI_CUSTOM_DSDT is not set
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
# CONFIG_ACPI_PCI_SLOT is not set
CONFIG_X86_PM_TIMER=y
# CONFIG_ACPI_CONTAINER is not set
CONFIG_ACPI_HOTPLUG_IOAPIC=y
# CONFIG_ACPI_SBS is not set
# CONFIG_ACPI_HED is not set
# CONFIG_ACPI_CUSTOM_METHOD is not set
# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
# CONFIG_ACPI_NFIT is not set
CONFIG_HAVE_ACPI_APEI=y
CONFIG_HAVE_ACPI_APEI_NMI=y
# CONFIG_ACPI_APEI is not set
# CONFIG_DPTF_POWER is not set
# CONFIG_ACPI_EXTLOG is not set
# CONFIG_PMIC_OPREGION is not set
# CONFIG_ACPI_CONFIGFS is not set
# CONFIG_SFI is not set
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
# CONFIG_CPU_IDLE_GOV_MENU is not set
# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
# CONFIG_INTEL_IDLE is not set
#
# Bus options (PCI etc.)
#
CONFIG_PCI=y
CONFIG_PCI_DIRECT=y
# CONFIG_PCI_MMCONFIG is not set
CONFIG_PCI_DOMAINS=y
# CONFIG_PCIEPORTBUS is not set
CONFIG_PCI_BUS_ADDR_T_64BIT=y
# CONFIG_PCI_MSI is not set
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
# CONFIG_PCI_STUB is not set
CONFIG_HT_IRQ=y
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_PRI is not set
# CONFIG_PCI_PASID is not set
CONFIG_PCI_LABEL=y
# CONFIG_HOTPLUG_PCI is not set
#
# DesignWare PCI Core Support
#
#
# PCI host controller drivers
#
#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
CONFIG_ISA_DMA_API=y
CONFIG_AMD_NB=y
CONFIG_PCCARD=m
# CONFIG_PCMCIA is not set
CONFIG_CARDBUS=y
#
# PC-card bridges
#
# CONFIG_YENTA is not set
# CONFIG_RAPIDIO is not set
CONFIG_X86_SYSFB=y
#
# Executable file formats / Emulations
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ELFCORE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_SCRIPT=y
# CONFIG_HAVE_AOUT is not set
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
CONFIG_IA32_EMULATION=y
CONFIG_IA32_AOUT=m
CONFIG_X86_X32=y
CONFIG_COMPAT_32=y
CONFIG_COMPAT=y
CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
CONFIG_KEYS_COMPAT=y
CONFIG_X86_DEV_DMA_OPS=y
CONFIG_NET=y
#
# Networking options
#
# CONFIG_PACKET is not set
CONFIG_UNIX=y
# CONFIG_UNIX_DIAG is not set
# CONFIG_NET_KEY is not set
# CONFIG_INET is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NET_PTP_CLASSIFY is not set
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
# CONFIG_NETFILTER is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
# CONFIG_DNS_RESOLVER is not set
# CONFIG_BATMAN_ADV is not set
# CONFIG_VSOCKETS is not set
# CONFIG_NETLINK_DIAG is not set
# CONFIG_MPLS is not set
# CONFIG_HSR is not set
# CONFIG_CGROUP_NET_PRIO is not set
# CONFIG_CGROUP_NET_CLASSID is not set
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
# CONFIG_BPF_JIT is not set
#
# Network testing
#
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_STREAM_PARSER is not set
CONFIG_WIRELESS=y
# CONFIG_CFG80211 is not set
# CONFIG_LIB80211 is not set
#
# CFG80211 needs to be enabled for MAC80211
#
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
# CONFIG_CAIF is not set
# CONFIG_NFC is not set
# CONFIG_PSAMPLE is not set
# CONFIG_NET_IFE is not set
# CONFIG_LWTUNNEL is not set
# CONFIG_DST_CACHE is not set
# CONFIG_GRO_CELLS is not set
# CONFIG_NET_DEVLINK is not set
CONFIG_MAY_USE_DEVLINK=y
CONFIG_HAVE_EBPF_JIT=y
#
# Device Drivers
#
#
# Generic Driver Options
#
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
# CONFIG_DEVTMPFS_MOUNT is not set
# CONFIG_STANDALONE is not set
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_ALLOW_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
CONFIG_TEST_ASYNC_DRIVER_PROBE=m
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_GENERIC_CPU_DEVICES is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPMI=m
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_FENCE_TRACE=y
CONFIG_DMA_CMA=y
#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_PERCENTAGE=0
# CONFIG_CMA_SIZE_SEL_MBYTES is not set
CONFIG_CMA_SIZE_SEL_PERCENTAGE=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
#
# Bus devices
#
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
# CONFIG_OF is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_PARPORT=m
CONFIG_PARPORT_PC=m
# CONFIG_PARPORT_SERIAL is not set
# CONFIG_PARPORT_PC_FIFO is not set
# CONFIG_PARPORT_PC_SUPERIO is not set
# CONFIG_PARPORT_GSC is not set
CONFIG_PARPORT_AX88796=m
CONFIG_PARPORT_1284=y
CONFIG_PARPORT_NOT_PC=y
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y
#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
# CONFIG_BLK_DEV_FD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
# CONFIG_ZRAM is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
#
# DRBD disabled because PROC_FS or INET not selected
#
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SKD is not set
# CONFIG_BLK_DEV_SX8 is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_VIRTIO_BLK is not set
# CONFIG_BLK_DEV_HD is not set
# CONFIG_BLK_DEV_RSXX is not set
# CONFIG_BLK_DEV_NVME is not set
# CONFIG_NVME_FC is not set
# CONFIG_NVME_TARGET is not set
#
# Misc devices
#
CONFIG_SENSORS_LIS3LV02D=y
CONFIG_AD525X_DPOT=m
CONFIG_AD525X_DPOT_I2C=m
# CONFIG_DUMMY_IRQ is not set
# CONFIG_IBM_ASM is not set
# CONFIG_PHANTOM is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
# CONFIG_ICS932S401 is not set
CONFIG_ENCLOSURE_SERVICES=m
# CONFIG_HP_ILO is not set
CONFIG_APDS9802ALS=m
CONFIG_ISL29003=y
CONFIG_ISL29020=y
CONFIG_SENSORS_TSL2550=y
CONFIG_SENSORS_BH1770=y
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
CONFIG_DS1682=m
CONFIG_USB_SWITCH_FSA9480=y
CONFIG_SRAM=y
# CONFIG_PANEL is not set
# CONFIG_C2PORT is not set
#
# EEPROM support
#
CONFIG_EEPROM_AT24=y
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
CONFIG_EEPROM_IDT_89HPESX=m
# CONFIG_CB710_CORE is not set
#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
CONFIG_SENSORS_LIS3_I2C=y
#
# Altera FPGA firmware download module
#
# CONFIG_ALTERA_STAPL is not set
# CONFIG_INTEL_MEI is not set
# CONFIG_INTEL_MEI_ME is not set
# CONFIG_INTEL_MEI_TXE is not set
# CONFIG_VMWARE_VMCI is not set
#
# Intel MIC Bus Driver
#
# CONFIG_INTEL_MIC_BUS is not set
#
# SCIF Bus Driver
#
# CONFIG_SCIF_BUS is not set
#
# VOP Bus Driver
#
# CONFIG_VOP_BUS is not set
#
# Intel MIC Host Driver
#
#
# Intel MIC Card Driver
#
#
# SCIF Driver
#
#
# Intel MIC Coprocessor State Management (COSM) Drivers
#
#
# VOP Driver
#
# CONFIG_GENWQE is not set
CONFIG_ECHO=m
# CONFIG_CXL_BASE is not set
# CONFIG_CXL_AFU_DRIVER_OPS is not set
CONFIG_HAVE_IDE=y
CONFIG_IDE=m
#
# Please see Documentation/ide/ide.txt for help/info on IDE drives
#
CONFIG_IDE_XFER_MODE=y
CONFIG_IDE_TIMINGS=y
CONFIG_IDE_ATAPI=y
# CONFIG_BLK_DEV_IDE_SATA is not set
# CONFIG_IDE_GD is not set
# CONFIG_BLK_DEV_DELKIN is not set
CONFIG_BLK_DEV_IDECD=m
CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
CONFIG_BLK_DEV_IDETAPE=m
# CONFIG_BLK_DEV_IDEACPI is not set
# CONFIG_IDE_TASK_IOCTL is not set
CONFIG_IDE_PROC_FS=y
#
# IDE chipset support/bugfixes
#
# CONFIG_IDE_GENERIC is not set
CONFIG_BLK_DEV_PLATFORM=m
CONFIG_BLK_DEV_CMD640=m
CONFIG_BLK_DEV_CMD640_ENHANCED=y
# CONFIG_BLK_DEV_IDEPNP is not set
#
# PCI IDE chipsets support
#
# CONFIG_BLK_DEV_GENERIC is not set
# CONFIG_BLK_DEV_OPTI621 is not set
# CONFIG_BLK_DEV_RZ1000 is not set
# CONFIG_BLK_DEV_AEC62XX is not set
# CONFIG_BLK_DEV_ALI15X3 is not set
# CONFIG_BLK_DEV_AMD74XX is not set
# CONFIG_BLK_DEV_ATIIXP is not set
# CONFIG_BLK_DEV_CMD64X is not set
# CONFIG_BLK_DEV_TRIFLEX is not set
# CONFIG_BLK_DEV_HPT366 is not set
# CONFIG_BLK_DEV_JMICRON is not set
# CONFIG_BLK_DEV_PIIX is not set
# CONFIG_BLK_DEV_IT8172 is not set
# CONFIG_BLK_DEV_IT8213 is not set
# CONFIG_BLK_DEV_IT821X is not set
# CONFIG_BLK_DEV_NS87415 is not set
# CONFIG_BLK_DEV_PDC202XX_OLD is not set
# CONFIG_BLK_DEV_PDC202XX_NEW is not set
# CONFIG_BLK_DEV_SVWKS is not set
# CONFIG_BLK_DEV_SIIMAGE is not set
# CONFIG_BLK_DEV_SIS5513 is not set
# CONFIG_BLK_DEV_SLC90E66 is not set
# CONFIG_BLK_DEV_TRM290 is not set
# CONFIG_BLK_DEV_VIA82CXXX is not set
# CONFIG_BLK_DEV_TC86C001 is not set
# CONFIG_BLK_DEV_IDEDMA is not set
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
CONFIG_RAID_ATTRS=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_NETLINK is not set
# CONFIG_SCSI_MQ_DEFAULT is not set
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
CONFIG_CHR_DEV_OSST=y
CONFIG_BLK_DEV_SR=m
# CONFIG_BLK_DEV_SR_VENDOR is not set
CONFIG_CHR_DEV_SG=y
CONFIG_CHR_DEV_SCH=y
CONFIG_SCSI_ENCLOSURE=m
CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_LOGGING is not set
CONFIG_SCSI_SCAN_ASYNC=y
#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=y
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
CONFIG_SCSI_SAS_ATTRS=y
# CONFIG_SCSI_SAS_LIBSAS is not set
CONFIG_SCSI_SRP_ATTRS=m
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_BOOT_SYSFS is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_VMWARE_PVSCSI is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_ISCI is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
CONFIG_SCSI_PPA=m
CONFIG_SCSI_IMM=m
CONFIG_SCSI_IZIP_EPP16=y
# CONFIG_SCSI_IZIP_SLOW_CTR is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
CONFIG_SCSI_DEBUG=y
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=m
CONFIG_SCSI_DH=y
CONFIG_SCSI_DH_RDAC=m
# CONFIG_SCSI_DH_HP_SW is not set
# CONFIG_SCSI_DH_EMC is not set
# CONFIG_SCSI_DH_ALUA is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
CONFIG_ATA=m
# CONFIG_ATA_NONSTANDARD is not set
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_PMP is not set
#
# Controllers with non-SFF native interface
#
# CONFIG_SATA_AHCI is not set
CONFIG_SATA_AHCI_PLATFORM=m
# CONFIG_SATA_INIC162X is not set
# CONFIG_SATA_ACARD_AHCI is not set
# CONFIG_SATA_SIL24 is not set
# CONFIG_ATA_SFF is not set
# CONFIG_MD is not set
CONFIG_TARGET_CORE=y
CONFIG_TCM_IBLOCK=y
CONFIG_TCM_FILEIO=y
CONFIG_TCM_PSCSI=m
# CONFIG_LOOPBACK_TARGET is not set
# CONFIG_ISCSI_TARGET is not set
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
CONFIG_MACINTOSH_DRIVERS=y
CONFIG_MAC_EMUMOUSEBTN=m
# CONFIG_NETDEVICES is not set
# CONFIG_NVM is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_LEDS is not set
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_POLLDEV=y
CONFIG_INPUT_SPARSEKMAP=y
CONFIG_INPUT_MATRIXKMAP=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_EVDEV=m
CONFIG_INPUT_EVBUG=y
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADC is not set
CONFIG_KEYBOARD_ADP5520=y
CONFIG_KEYBOARD_ADP5588=y
CONFIG_KEYBOARD_ADP5589=y
CONFIG_KEYBOARD_ATKBD=y
CONFIG_KEYBOARD_QT1070=m
CONFIG_KEYBOARD_QT2160=m
CONFIG_KEYBOARD_LKKBD=m
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_GPIO_POLLED=y
CONFIG_KEYBOARD_TCA6416=m
# CONFIG_KEYBOARD_TCA8418 is not set
CONFIG_KEYBOARD_MATRIX=m
CONFIG_KEYBOARD_LM8323=m
# CONFIG_KEYBOARD_LM8333 is not set
CONFIG_KEYBOARD_MAX7359=y
CONFIG_KEYBOARD_MCS=y
CONFIG_KEYBOARD_MPR121=y
CONFIG_KEYBOARD_NEWTON=m
CONFIG_KEYBOARD_OPENCORES=y
# CONFIG_KEYBOARD_SAMSUNG is not set
CONFIG_KEYBOARD_STOWAWAY=y
CONFIG_KEYBOARD_SUNKBD=m
CONFIG_KEYBOARD_TM2_TOUCHKEY=y
CONFIG_KEYBOARD_TWL4030=y
CONFIG_KEYBOARD_XTKBD=y
# CONFIG_KEYBOARD_CROS_EC is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
CONFIG_RMI4_CORE=m
CONFIG_RMI4_I2C=m
CONFIG_RMI4_SMB=m
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=m
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
# CONFIG_RMI4_F54 is not set
CONFIG_RMI4_F55=y
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_CT82C710=m
CONFIG_SERIO_PARKBD=m
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_RAW=y
CONFIG_SERIO_ALTERA_PS2=y
CONFIG_SERIO_PS2MULT=m
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
CONFIG_GAMEPORT_NS558=m
# CONFIG_GAMEPORT_L4 is not set
# CONFIG_GAMEPORT_EMU10K1 is not set
# CONFIG_GAMEPORT_FM801 is not set
#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_NOZOMI is not set
# CONFIG_N_GSM is not set
# CONFIG_TRACE_SINK is not set
CONFIG_DEVMEM=y
CONFIG_DEVKMEM=y
#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_PNP=y
CONFIG_SERIAL_8250_FINTEK=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_EXAR=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
# CONFIG_SERIAL_8250_SHARE_IRQ is not set
CONFIG_SERIAL_8250_DETECT_IRQ=y
# CONFIG_SERIAL_8250_RSA is not set
# CONFIG_SERIAL_8250_FSL is not set
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_RT288X=y
CONFIG_SERIAL_8250_LPSS=y
CONFIG_SERIAL_8250_MID=y
# CONFIG_SERIAL_8250_MOXA is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_UARTLITE=m
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SCCNXP is not set
CONFIG_SERIAL_SC16IS7XX=m
# CONFIG_SERIAL_SC16IS7XX_I2C is not set
CONFIG_SERIAL_ALTERA_JTAGUART=y
CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE=y
# CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE_BYPASS is not set
CONFIG_SERIAL_ALTERA_UART=y
CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
CONFIG_SERIAL_ALTERA_UART_CONSOLE=y
CONFIG_SERIAL_ARC=y
# CONFIG_SERIAL_ARC_CONSOLE is not set
CONFIG_SERIAL_ARC_NR_PORTS=1
# CONFIG_SERIAL_RP2 is not set
CONFIG_SERIAL_FSL_LPUART=m
CONFIG_SERIAL_MEN_Z135=m
# CONFIG_SERIAL_DEV_BUS is not set
# CONFIG_PRINTER is not set
CONFIG_PPDEV=m
CONFIG_HVC_DRIVER=y
CONFIG_VIRTIO_CONSOLE=m
CONFIG_IPMI_HANDLER=m
# CONFIG_IPMI_PANIC_EVENT is not set
CONFIG_IPMI_DEVICE_INTERFACE=m
CONFIG_IPMI_SI=m
CONFIG_IPMI_SSIF=m
CONFIG_IPMI_WATCHDOG=m
CONFIG_IPMI_POWEROFF=m
CONFIG_HW_RANDOM=m
CONFIG_HW_RANDOM_TIMERIOMEM=m
CONFIG_HW_RANDOM_INTEL=m
CONFIG_HW_RANDOM_AMD=m
CONFIG_HW_RANDOM_VIA=m
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_TPM=m
# CONFIG_NVRAM is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
CONFIG_MWAVE=y
# CONFIG_RAW_DRIVER is not set
# CONFIG_HPET is not set
CONFIG_HANGCHECK_TIMER=y
CONFIG_TCG_TPM=m
# CONFIG_TCG_TIS is not set
# CONFIG_TCG_TIS_I2C_ATMEL is not set
# CONFIG_TCG_TIS_I2C_INFINEON is not set
# CONFIG_TCG_TIS_I2C_NUVOTON is not set
# CONFIG_TCG_NSC is not set
CONFIG_TCG_ATMEL=m
# CONFIG_TCG_INFINEON is not set
# CONFIG_TCG_CRB is not set
CONFIG_TCG_VTPM_PROXY=m
CONFIG_TCG_TIS_ST33ZP24=m
CONFIG_TCG_TIS_ST33ZP24_I2C=m
# CONFIG_TELCLOCK is not set
CONFIG_DEVPORT=y
# CONFIG_XILLYBUS is not set
#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_COMPAT is not set
# CONFIG_I2C_CHARDEV is not set
CONFIG_I2C_MUX=y
#
# Multiplexer I2C Chip support
#
# CONFIG_I2C_MUX_GPIO is not set
# CONFIG_I2C_MUX_PCA9541 is not set
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_I2C_MUX_REG is not set
CONFIG_I2C_MUX_MLXCPLD=y
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=m
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_ALGOPCA=y
#
# I2C Hardware Bus support
#
#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_ISMT is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set
#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CBUS_GPIO is not set
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_DESIGNWARE_PCI is not set
# CONFIG_I2C_EMEV2 is not set
# CONFIG_I2C_GPIO is not set
CONFIG_I2C_KEMPLD=y
CONFIG_I2C_OCORES=y
CONFIG_I2C_PCA_PLATFORM=y
# CONFIG_I2C_PXA_PCI is not set
CONFIG_I2C_SIMTEC=y
# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
CONFIG_I2C_DLN2=m
# CONFIG_I2C_PARPORT is not set
CONFIG_I2C_PARPORT_LIGHT=m
CONFIG_I2C_ROBOTFUZZ_OSIF=m
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set
# CONFIG_I2C_VIPERBOARD is not set
#
# Other I2C/SMBus bus drivers
#
CONFIG_I2C_MLXCPLD=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_STUB=m
# CONFIG_I2C_SLAVE is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_SPI is not set
CONFIG_SPMI=y
CONFIG_HSI=m
CONFIG_HSI_BOARDINFO=y
#
# HSI controllers
#
#
# HSI clients
#
# CONFIG_HSI_CHAR is not set
#
# PPS support
#
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set
CONFIG_NTP_PPS=y
#
# PPS clients support
#
CONFIG_PPS_CLIENT_KTIMER=y
CONFIG_PPS_CLIENT_LDISC=y
CONFIG_PPS_CLIENT_PARPORT=m
CONFIG_PPS_CLIENT_GPIO=m
#
# PPS generators support
#
#
# PTP clock support
#
# CONFIG_PTP_1588_CLOCK is not set
#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
CONFIG_GPIOLIB=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GENERIC=m
CONFIG_GPIO_MAX730X=y
#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_AMDPT is not set
CONFIG_GPIO_AXP209=m
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_EXAR is not set
CONFIG_GPIO_GENERIC_PLATFORM=m
# CONFIG_GPIO_ICH is not set
# CONFIG_GPIO_LYNXPOINT is not set
CONFIG_GPIO_MENZ127=m
CONFIG_GPIO_MOCKUP=y
# CONFIG_GPIO_VX855 is not set
#
# Port-mapped I/O GPIO drivers
#
CONFIG_GPIO_F7188X=y
CONFIG_GPIO_IT87=m
# CONFIG_GPIO_SCH is not set
CONFIG_GPIO_SCH311X=m
#
# I2C GPIO expanders
#
CONFIG_GPIO_ADP5588=y
CONFIG_GPIO_ADP5588_IRQ=y
CONFIG_GPIO_MAX7300=y
CONFIG_GPIO_MAX732X=y
CONFIG_GPIO_MAX732X_IRQ=y
CONFIG_GPIO_PCA953X=m
# CONFIG_GPIO_PCF857X is not set
CONFIG_GPIO_TPIC2810=m
#
# MFD GPIO expanders
#
CONFIG_GPIO_ADP5520=m
CONFIG_GPIO_DLN2=m
CONFIG_GPIO_KEMPLD=m
# CONFIG_GPIO_LP873X is not set
# CONFIG_GPIO_PALMAS is not set
# CONFIG_GPIO_RC5T583 is not set
CONFIG_GPIO_TPS65218=m
CONFIG_GPIO_TPS65912=y
# CONFIG_GPIO_TWL4030 is not set
CONFIG_GPIO_WM831X=m
CONFIG_GPIO_WM8350=m
CONFIG_GPIO_WM8994=m
#
# PCI GPIO expanders
#
# CONFIG_GPIO_AMD8111 is not set
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_ML_IOH is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_RDC321X is not set
#
# SPI or I2C GPIO expanders
#
#
# USB GPIO expanders
#
CONFIG_GPIO_VIPERBOARD=m
CONFIG_W1=m
#
# 1-wire Bus Masters
#
# CONFIG_W1_MASTER_MATROX is not set
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_DS1WM=m
CONFIG_W1_MASTER_GPIO=m
#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
# CONFIG_W1_SLAVE_SMEM is not set
CONFIG_W1_SLAVE_DS2405=m
# CONFIG_W1_SLAVE_DS2408 is not set
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
# CONFIG_W1_SLAVE_DS2433_CRC is not set
# CONFIG_W1_SLAVE_DS2760 is not set
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
CONFIG_W1_SLAVE_BQ27000=m
CONFIG_POWER_AVS=y
# CONFIG_POWER_RESET is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
# CONFIG_PDA_POWER is not set
CONFIG_GENERIC_ADC_BATTERY=m
CONFIG_MAX8925_POWER=y
# CONFIG_WM831X_BACKUP is not set
CONFIG_WM831X_POWER=m
# CONFIG_WM8350_POWER is not set
CONFIG_TEST_POWER=y
CONFIG_BATTERY_DS2780=m
CONFIG_BATTERY_DS2781=m
CONFIG_BATTERY_DS2782=y
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_AXP288_CHARGER is not set
CONFIG_AXP288_FUEL_GAUGE=m
CONFIG_BATTERY_MAX17040=m
CONFIG_BATTERY_MAX17042=y
# CONFIG_BATTERY_TWL4030_MADC is not set
# CONFIG_CHARGER_PCF50633 is not set
CONFIG_BATTERY_RX51=m
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
CONFIG_CHARGER_TWL4030=m
CONFIG_CHARGER_LP8727=y
CONFIG_CHARGER_GPIO=y
CONFIG_CHARGER_MAX14577=m
CONFIG_CHARGER_MAX77693=y
CONFIG_CHARGER_BQ2415X=m
# CONFIG_CHARGER_BQ24190 is not set
CONFIG_CHARGER_BQ24257=y
# CONFIG_CHARGER_BQ24735 is not set
CONFIG_CHARGER_BQ25890=m
CONFIG_CHARGER_SMB347=y
CONFIG_CHARGER_TPS65090=y
# CONFIG_CHARGER_TPS65217 is not set
CONFIG_BATTERY_GAUGE_LTC2941=y
CONFIG_BATTERY_RT5033=m
CONFIG_CHARGER_RT9455=m
CONFIG_AXP20X_POWER=m
CONFIG_HWMON=y
CONFIG_HWMON_VID=y
# CONFIG_HWMON_DEBUG_CHIP is not set
#
# Native drivers
#
CONFIG_SENSORS_ABITUGURU=y
# CONFIG_SENSORS_ABITUGURU3 is not set
CONFIG_SENSORS_AD7414=m
CONFIG_SENSORS_AD7418=y
# CONFIG_SENSORS_ADM1021 is not set
CONFIG_SENSORS_ADM1025=m
CONFIG_SENSORS_ADM1026=y
CONFIG_SENSORS_ADM1029=m
CONFIG_SENSORS_ADM1031=m
# CONFIG_SENSORS_ADM9240 is not set
CONFIG_SENSORS_ADT7X10=y
CONFIG_SENSORS_ADT7410=y
CONFIG_SENSORS_ADT7411=m
CONFIG_SENSORS_ADT7462=m
CONFIG_SENSORS_ADT7470=y
CONFIG_SENSORS_ADT7475=y
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_K8TEMP is not set
# CONFIG_SENSORS_K10TEMP is not set
# CONFIG_SENSORS_FAM15H_POWER is not set
CONFIG_SENSORS_APPLESMC=y
# CONFIG_SENSORS_ASB100 is not set
# CONFIG_SENSORS_ASPEED is not set
CONFIG_SENSORS_ATXP1=m
CONFIG_SENSORS_DS620=m
# CONFIG_SENSORS_DS1621 is not set
CONFIG_SENSORS_DELL_SMM=y
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
CONFIG_SENSORS_F75375S=y
CONFIG_SENSORS_FSCHMD=y
CONFIG_SENSORS_GL518SM=y
CONFIG_SENSORS_GL520SM=m
CONFIG_SENSORS_G760A=y
CONFIG_SENSORS_G762=m
# CONFIG_SENSORS_GPIO_FAN is not set
CONFIG_SENSORS_HIH6130=m
CONFIG_SENSORS_IBMAEM=m
CONFIG_SENSORS_IBMPEX=m
# CONFIG_SENSORS_IIO_HWMON is not set
# CONFIG_SENSORS_I5500 is not set
CONFIG_SENSORS_CORETEMP=y
CONFIG_SENSORS_IT87=m
CONFIG_SENSORS_JC42=m
# CONFIG_SENSORS_POWR1220 is not set
CONFIG_SENSORS_LINEAGE=m
CONFIG_SENSORS_LTC2945=y
CONFIG_SENSORS_LTC2990=m
CONFIG_SENSORS_LTC4151=y
CONFIG_SENSORS_LTC4215=m
# CONFIG_SENSORS_LTC4222 is not set
CONFIG_SENSORS_LTC4245=y
CONFIG_SENSORS_LTC4260=m
CONFIG_SENSORS_LTC4261=y
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
CONFIG_SENSORS_MAX1668=m
CONFIG_SENSORS_MAX197=m
# CONFIG_SENSORS_MAX6639 is not set
CONFIG_SENSORS_MAX6642=y
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
CONFIG_SENSORS_MAX31790=y
CONFIG_SENSORS_MCP3021=m
CONFIG_SENSORS_TC654=y
CONFIG_SENSORS_MENF21BMC_HWMON=y
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM73 is not set
CONFIG_SENSORS_LM75=y
# CONFIG_SENSORS_LM77 is not set
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
CONFIG_SENSORS_LM87=y
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_LM92=m
CONFIG_SENSORS_LM93=y
CONFIG_SENSORS_LM95234=y
CONFIG_SENSORS_LM95241=y
# CONFIG_SENSORS_LM95245 is not set
CONFIG_SENSORS_PC87360=m
CONFIG_SENSORS_PC87427=y
CONFIG_SENSORS_NTC_THERMISTOR=y
CONFIG_SENSORS_NCT6683=y
# CONFIG_SENSORS_NCT6775 is not set
CONFIG_SENSORS_NCT7802=m
CONFIG_SENSORS_NCT7904=m
CONFIG_SENSORS_PCF8591=m
CONFIG_PMBUS=y
CONFIG_SENSORS_PMBUS=m
# CONFIG_SENSORS_ADM1275 is not set
CONFIG_SENSORS_LM25066=y
# CONFIG_SENSORS_LTC2978 is not set
CONFIG_SENSORS_LTC3815=m
# CONFIG_SENSORS_MAX16064 is not set
CONFIG_SENSORS_MAX20751=y
# CONFIG_SENSORS_MAX34440 is not set
# CONFIG_SENSORS_MAX8688 is not set
CONFIG_SENSORS_TPS40422=y
CONFIG_SENSORS_UCD9000=y
CONFIG_SENSORS_UCD9200=m
CONFIG_SENSORS_ZL6100=m
CONFIG_SENSORS_SHT15=m
CONFIG_SENSORS_SHT21=m
# CONFIG_SENSORS_SHT3x is not set
CONFIG_SENSORS_SHTC1=m
# CONFIG_SENSORS_SIS5595 is not set
CONFIG_SENSORS_DME1737=m
# CONFIG_SENSORS_EMC1403 is not set
CONFIG_SENSORS_EMC2103=y
CONFIG_SENSORS_EMC6W201=m
# CONFIG_SENSORS_SMSC47M1 is not set
CONFIG_SENSORS_SMSC47M192=m
CONFIG_SENSORS_SMSC47B397=y
# CONFIG_SENSORS_SCH56XX_COMMON is not set
CONFIG_SENSORS_STTS751=y
CONFIG_SENSORS_SMM665=y
CONFIG_SENSORS_ADC128D818=y
CONFIG_SENSORS_ADS1015=y
CONFIG_SENSORS_ADS7828=y
# CONFIG_SENSORS_AMC6821 is not set
CONFIG_SENSORS_INA209=y
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA3221 is not set
CONFIG_SENSORS_TC74=m
# CONFIG_SENSORS_THMC50 is not set
CONFIG_SENSORS_TMP102=y
# CONFIG_SENSORS_TMP103 is not set
CONFIG_SENSORS_TMP108=y
CONFIG_SENSORS_TMP401=y
# CONFIG_SENSORS_TMP421 is not set
CONFIG_SENSORS_TWL4030_MADC=m
# CONFIG_SENSORS_VIA_CPUTEMP is not set
# CONFIG_SENSORS_VIA686A is not set
CONFIG_SENSORS_VT1211=y
# CONFIG_SENSORS_VT8231 is not set
CONFIG_SENSORS_W83781D=y
CONFIG_SENSORS_W83791D=y
CONFIG_SENSORS_W83792D=m
CONFIG_SENSORS_W83793=y
# CONFIG_SENSORS_W83795 is not set
CONFIG_SENSORS_W83L785TS=m
CONFIG_SENSORS_W83L786NG=y
CONFIG_SENSORS_W83627HF=m
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_WM831X is not set
CONFIG_SENSORS_WM8350=y
#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
# CONFIG_SENSORS_ATK0110 is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
# CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE is not set
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR=y
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
# CONFIG_THERMAL_GOV_USER_SPACE is not set
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
# CONFIG_THERMAL_EMULATION is not set
CONFIG_INTEL_POWERCLAMP=y
# CONFIG_X86_PKG_TEMP_THERMAL is not set
CONFIG_INTEL_SOC_DTS_IOSF_CORE=m
CONFIG_INTEL_SOC_DTS_THERMAL=m
#
# ACPI INT340X thermal drivers
#
# CONFIG_INT340X_THERMAL is not set
# CONFIG_INTEL_PCH_THERMAL is not set
CONFIG_GENERIC_ADC_THERMAL=m
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
CONFIG_SSB=y
CONFIG_SSB_SPROM=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
# CONFIG_SSB_B43_PCI_BRIDGE is not set
CONFIG_SSB_SDIOHOST_POSSIBLE=y
# CONFIG_SSB_SDIOHOST is not set
# CONFIG_SSB_DEBUG is not set
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
# CONFIG_SSB_DRIVER_PCICORE is not set
# CONFIG_SSB_DRIVER_GPIO is not set
CONFIG_BCMA_POSSIBLE=y
#
# Broadcom specific AMBA
#
CONFIG_BCMA=m
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
# CONFIG_BCMA_HOST_SOC is not set
CONFIG_BCMA_DRIVER_PCI=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
# CONFIG_BCMA_DRIVER_GPIO is not set
# CONFIG_BCMA_DEBUG is not set
#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_AS3711 is not set
CONFIG_PMIC_ADP5520=y
CONFIG_MFD_AAT2870_CORE=y
# CONFIG_MFD_BCM590XX is not set
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_CROS_EC=y
CONFIG_MFD_CROS_EC_I2C=y
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
CONFIG_MFD_DA9062=m
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
CONFIG_MFD_DLN2=m
# CONFIG_MFD_MC13XXX_I2C is not set
CONFIG_HTC_PASIC3=m
CONFIG_HTC_I2CPLD=y
# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_INTEL_SOC_PMIC is not set
# CONFIG_MFD_INTEL_LPSS_ACPI is not set
# CONFIG_MFD_INTEL_LPSS_PCI is not set
# CONFIG_MFD_JANZ_CMODIO is not set
CONFIG_MFD_KEMPLD=y
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
CONFIG_MFD_MAX14577=y
CONFIG_MFD_MAX77693=y
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
CONFIG_MFD_MAX8925=y
CONFIG_MFD_MAX8997=y
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6397 is not set
CONFIG_MFD_MENF21BMC=y
CONFIG_MFD_VIPERBOARD=m
# CONFIG_MFD_RETU is not set
CONFIG_MFD_PCF50633=y
CONFIG_PCF50633_ADC=y
# CONFIG_PCF50633_GPIO is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RTSX_PCI is not set
CONFIG_MFD_RT5033=y
CONFIG_MFD_RTSX_USB=m
CONFIG_MFD_RC5T583=y
# CONFIG_MFD_SEC_CORE is not set
CONFIG_MFD_SI476X_CORE=m
CONFIG_MFD_SM501=m
# CONFIG_MFD_SM501_GPIO is not set
CONFIG_MFD_SKY81452=y
# CONFIG_MFD_SMSC is not set
# CONFIG_ABX500_CORE is not set
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP3943 is not set
CONFIG_MFD_LP8788=y
CONFIG_MFD_PALMAS=y
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
CONFIG_TPS6507X=y
# CONFIG_MFD_TPS65086 is not set
CONFIG_MFD_TPS65090=y
CONFIG_MFD_TPS65217=y
CONFIG_MFD_TI_LP873X=m
CONFIG_MFD_TPS65218=y
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
CONFIG_MFD_TPS65912=y
CONFIG_MFD_TPS65912_I2C=y
CONFIG_MFD_TPS80031=y
CONFIG_TWL4030_CORE=y
CONFIG_MFD_TWL4030_AUDIO=y
# CONFIG_TWL6040_CORE is not set
CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_WM8400 is not set
CONFIG_MFD_WM831X=y
CONFIG_MFD_WM831X_I2C=y
CONFIG_MFD_WM8350=y
CONFIG_MFD_WM8350_I2C=y
CONFIG_MFD_WM8994=m
# CONFIG_REGULATOR is not set
CONFIG_MEDIA_SUPPORT=y
#
# Multimedia core support
#
# CONFIG_MEDIA_CAMERA_SUPPORT is not set
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
CONFIG_MEDIA_RADIO_SUPPORT=y
# CONFIG_MEDIA_SDR_SUPPORT is not set
# CONFIG_MEDIA_RC_SUPPORT is not set
# CONFIG_MEDIA_CEC_SUPPORT is not set
# CONFIG_MEDIA_CONTROLLER is not set
CONFIG_VIDEO_DEV=y
CONFIG_VIDEO_V4L2=y
# CONFIG_VIDEO_ADV_DEBUG is not set
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
# CONFIG_TTPCI_EEPROM is not set
#
# Media drivers
#
# CONFIG_MEDIA_USB_SUPPORT is not set
# CONFIG_MEDIA_PCI_SUPPORT is not set
#
# Supported MMC/SDIO adapters
#
# CONFIG_RADIO_ADAPTERS is not set
CONFIG_CYPRESS_FIRMWARE=m
#
# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
#
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_MEDIA_ATTACH=y
#
# I2C Encoders, decoders, sensors and other helper chips
#
#
# Audio decoders, processors and mixers
#
# CONFIG_VIDEO_TVAUDIO is not set
CONFIG_VIDEO_TDA7432=y
CONFIG_VIDEO_TDA9840=y
# CONFIG_VIDEO_TEA6415C is not set
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_MSP3400=y
CONFIG_VIDEO_CS3308=y
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_TLV320AIC23B=y
# CONFIG_VIDEO_UDA1342 is not set
CONFIG_VIDEO_WM8775=y
# CONFIG_VIDEO_WM8739 is not set
CONFIG_VIDEO_VP27SMPX=y
CONFIG_VIDEO_SONY_BTF_MPX=m
#
# RDS decoders
#
# CONFIG_VIDEO_SAA6588 is not set
#
# Video decoders
#
# CONFIG_VIDEO_ADV7183 is not set
# CONFIG_VIDEO_BT819 is not set
CONFIG_VIDEO_BT856=m
# CONFIG_VIDEO_BT866 is not set
CONFIG_VIDEO_KS0127=y
# CONFIG_VIDEO_ML86V7667 is not set
# CONFIG_VIDEO_SAA7110 is not set
CONFIG_VIDEO_SAA711X=m
CONFIG_VIDEO_TVP514X=y
CONFIG_VIDEO_TVP5150=m
# CONFIG_VIDEO_TVP7002 is not set
# CONFIG_VIDEO_TW2804 is not set
# CONFIG_VIDEO_TW9903 is not set
CONFIG_VIDEO_TW9906=m
CONFIG_VIDEO_VPX3220=m
#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
#
# Video encoders
#
CONFIG_VIDEO_SAA7127=m
CONFIG_VIDEO_SAA7185=y
CONFIG_VIDEO_ADV7170=y
# CONFIG_VIDEO_ADV7175 is not set
CONFIG_VIDEO_ADV7343=y
CONFIG_VIDEO_ADV7393=m
CONFIG_VIDEO_AK881X=m
CONFIG_VIDEO_THS8200=y
#
# Camera sensor devices
#
CONFIG_VIDEO_MT9M111=m
#
# Flash devices
#
#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
# CONFIG_VIDEO_UPD64083 is not set
#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
#
# Miscellaneous helper chips
#
CONFIG_VIDEO_THS7303=m
CONFIG_VIDEO_M52790=y
#
# Sensors used on soc_camera driver
#
#
# SPI helper chips
#
CONFIG_MEDIA_TUNER=y
#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_SIMPLE=y
CONFIG_MEDIA_TUNER_TDA8290=y
CONFIG_MEDIA_TUNER_TDA827X=y
CONFIG_MEDIA_TUNER_TDA18271=y
CONFIG_MEDIA_TUNER_TDA9887=y
CONFIG_MEDIA_TUNER_TEA5761=y
CONFIG_MEDIA_TUNER_TEA5767=m
# CONFIG_MEDIA_TUNER_MT20XX is not set
CONFIG_MEDIA_TUNER_MT2060=m
CONFIG_MEDIA_TUNER_MT2063=m
CONFIG_MEDIA_TUNER_MT2266=m
CONFIG_MEDIA_TUNER_MT2131=m
CONFIG_MEDIA_TUNER_QT1010=m
# CONFIG_MEDIA_TUNER_XC2028 is not set
CONFIG_MEDIA_TUNER_XC5000=y
CONFIG_MEDIA_TUNER_XC4000=m
CONFIG_MEDIA_TUNER_MXL5005S=m
# CONFIG_MEDIA_TUNER_MXL5007T is not set
CONFIG_MEDIA_TUNER_MC44S803=m
CONFIG_MEDIA_TUNER_MAX2165=m
CONFIG_MEDIA_TUNER_TDA18218=m
# CONFIG_MEDIA_TUNER_FC0011 is not set
CONFIG_MEDIA_TUNER_FC0012=y
# CONFIG_MEDIA_TUNER_FC0013 is not set
# CONFIG_MEDIA_TUNER_TDA18212 is not set
CONFIG_MEDIA_TUNER_E4000=y
CONFIG_MEDIA_TUNER_FC2580=m
CONFIG_MEDIA_TUNER_M88RS6000T=m
CONFIG_MEDIA_TUNER_TUA9001=m
CONFIG_MEDIA_TUNER_SI2157=m
CONFIG_MEDIA_TUNER_IT913X=y
# CONFIG_MEDIA_TUNER_R820T is not set
CONFIG_MEDIA_TUNER_MXL301RF=m
CONFIG_MEDIA_TUNER_QM1D1C0042=m
#
# Customise DVB Frontends
#
#
# Tools to develop new frontends
#
#
# Graphics support
#
# CONFIG_AGP is not set
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
# CONFIG_VGA_SWITCHEROO is not set
CONFIG_DRM=m
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DEBUG_MM_SELFTEST is not set
CONFIG_DRM_KMS_HELPER=m
CONFIG_DRM_KMS_FB_HELPER=y
# CONFIG_DRM_FBDEV_EMULATION is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_KMS_CMA_HELPER=y
#
# I2C encoder or helper chips
#
CONFIG_DRM_I2C_CH7006=m
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
#
# ACP (Audio CoProcessor) Configuration
#
# CONFIG_DRM_NOUVEAU is not set
# CONFIG_DRM_I915 is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VMWGFX is not set
# CONFIG_DRM_GMA500 is not set
CONFIG_DRM_UDL=m
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_QXL is not set
# CONFIG_DRM_BOCHS is not set
# CONFIG_DRM_VIRTIO_GPU is not set
CONFIG_DRM_BRIDGE=y
#
# Display Interface Bridges
#
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_HISI_HIBMC is not set
CONFIG_DRM_TINYDRM=m
# CONFIG_DRM_LEGACY is not set
# CONFIG_DRM_LIB_RANDOM is not set
#
# Frame buffer Devices
#
CONFIG_FB=m
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
# CONFIG_FB_DDC is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
CONFIG_FB_CFB_FILLRECT=m
CONFIG_FB_CFB_COPYAREA=m
CONFIG_FB_CFB_IMAGEBLIT=m
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
CONFIG_FB_SYS_FILLRECT=m
CONFIG_FB_SYS_COPYAREA=m
CONFIG_FB_SYS_IMAGEBLIT=m
# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set
CONFIG_FB_FOREIGN_ENDIAN=y
CONFIG_FB_BOTH_ENDIAN=y
# CONFIG_FB_BIG_ENDIAN is not set
# CONFIG_FB_LITTLE_ENDIAN is not set
CONFIG_FB_SYS_FOPS=m
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set
#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_CYBER2000 is not set
CONFIG_FB_ARC=m
# CONFIG_FB_VGA16 is not set
# CONFIG_FB_N411 is not set
CONFIG_FB_HGA=m
CONFIG_FB_OPENCORES=m
CONFIG_FB_S1D13XXX=m
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_LE80578 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_VIA is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
CONFIG_FB_SM501=m
CONFIG_FB_SMSCUFX=m
CONFIG_FB_UDL=m
# CONFIG_FB_IBM_GXT4500 is not set
CONFIG_FB_VIRTUAL=m
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_BROADSHEET is not set
CONFIG_FB_AUO_K190X=m
CONFIG_FB_AUO_K1900=m
# CONFIG_FB_AUO_K1901 is not set
# CONFIG_FB_SM712 is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
# CONFIG_LCD_PLATFORM is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=m
# CONFIG_BACKLIGHT_GENERIC is not set
# CONFIG_BACKLIGHT_PWM is not set
# CONFIG_BACKLIGHT_MAX8925 is not set
# CONFIG_BACKLIGHT_APPLE is not set
CONFIG_BACKLIGHT_PM8941_WLED=m
CONFIG_BACKLIGHT_SAHARA=m
# CONFIG_BACKLIGHT_WM831X is not set
CONFIG_BACKLIGHT_ADP5520=m
CONFIG_BACKLIGHT_ADP8860=m
CONFIG_BACKLIGHT_ADP8870=m
CONFIG_BACKLIGHT_PCF50633=m
# CONFIG_BACKLIGHT_AAT2870 is not set
CONFIG_BACKLIGHT_LM3630A=m
# CONFIG_BACKLIGHT_LM3639 is not set
CONFIG_BACKLIGHT_LP855X=m
CONFIG_BACKLIGHT_LP8788=m
CONFIG_BACKLIGHT_PANDORA=m
# CONFIG_BACKLIGHT_SKY81452 is not set
CONFIG_BACKLIGHT_TPS65217=m
# CONFIG_BACKLIGHT_GPIO is not set
CONFIG_BACKLIGHT_LV5207LP=m
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_VGASTATE is not set
CONFIG_HDMI=y
#
# Console display driver support
#
CONFIG_VGA_CONSOLE=y
# CONFIG_VGACON_SOFT_SCROLLBACK is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=m
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
# CONFIG_LOGO is not set
# CONFIG_SOUND is not set
#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=m
# CONFIG_HID_GENERIC is not set
#
# Special HID drivers
#
CONFIG_HID_A4TECH=y
CONFIG_HID_ACRUX=y
CONFIG_HID_ACRUX_FF=y
# CONFIG_HID_APPLE is not set
CONFIG_HID_APPLEIR=m
# CONFIG_HID_ASUS is not set
CONFIG_HID_AUREAL=m
CONFIG_HID_BELKIN=y
CONFIG_HID_BETOP_FF=m
# CONFIG_HID_CHERRY is not set
CONFIG_HID_CHICONY=y
# CONFIG_HID_CORSAIR is not set
# CONFIG_HID_CMEDIA is not set
# CONFIG_HID_CP2112 is not set
CONFIG_HID_CYPRESS=y
CONFIG_HID_DRAGONRISE=y
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELECOM=y
CONFIG_HID_ELO=m
CONFIG_HID_EZKEY=y
CONFIG_HID_GEMBIRD=y
CONFIG_HID_GFRM=m
CONFIG_HID_HOLTEK=m
CONFIG_HOLTEK_FF=y
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=y
# CONFIG_HID_KYE is not set
# CONFIG_HID_UCLOGIC is not set
CONFIG_HID_WALTOP=y
# CONFIG_HID_GYRATION is not set
CONFIG_HID_ICADE=y
CONFIG_HID_TWINHAN=y
CONFIG_HID_KENSINGTON=y
CONFIG_HID_LCPOWER=y
CONFIG_HID_LED=y
# CONFIG_HID_LENOVO is not set
CONFIG_HID_LOGITECH=y
CONFIG_HID_LOGITECH_DJ=y
CONFIG_HID_LOGITECH_HIDPP=y
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
# CONFIG_LOGIG940_FF is not set
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=m
CONFIG_HID_MAYFLASH=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=y
CONFIG_HID_NTRIG=m
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=y
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=m
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PRIMAX is not set
CONFIG_HID_ROCCAT=m
# CONFIG_HID_SAITEK is not set
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SONY=m
# CONFIG_SONY_FF is not set
# CONFIG_HID_SPEEDLINK is not set
CONFIG_HID_STEELSERIES=m
# CONFIG_HID_SUNPLUS is not set
CONFIG_HID_RMI=m
CONFIG_HID_GREENASIA=y
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=m
# CONFIG_SMARTJOYPLUS_FF is not set
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=y
CONFIG_HID_THINGM=y
CONFIG_HID_THRUSTMASTER=m
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=y
# CONFIG_HID_WACOM is not set
# CONFIG_HID_WIIMOTE is not set
CONFIG_HID_XINMO=y
# CONFIG_HID_ZEROPLUS is not set
CONFIG_HID_ZYDACRON=y
CONFIG_HID_SENSOR_HUB=y
# CONFIG_HID_SENSOR_CUSTOM_SENSOR is not set
CONFIG_HID_ALPS=m
#
# USB HID support
#
CONFIG_USB_HID=m
# CONFIG_HID_PID is not set
# CONFIG_USB_HIDDEV is not set
#
# I2C HID support
#
# CONFIG_I2C_HID is not set
#
# Intel ISH HID support
#
# CONFIG_INTEL_ISH_HID is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=m
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
CONFIG_USB_DYNAMIC_MINORS=y
# CONFIG_USB_OTG_WHITELIST is not set
CONFIG_USB_MON=m
CONFIG_USB_WUSB=m
CONFIG_USB_WUSB_CBAF=m
CONFIG_USB_WUSB_CBAF_DEBUG=y
#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=m
# CONFIG_USB_XHCI_HCD is not set
CONFIG_USB_EHCI_HCD=m
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=m
# CONFIG_USB_EHCI_HCD_PLATFORM is not set
CONFIG_USB_OXU210HP_HCD=m
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_ISP1362_HCD=m
# CONFIG_USB_FOTG210_HCD is not set
# CONFIG_USB_OHCI_HCD is not set
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_WHCI_HCD is not set
CONFIG_USB_HWA_HCD=m
# CONFIG_USB_HCD_BCMA is not set
# CONFIG_USB_HCD_SSB is not set
CONFIG_USB_HCD_TEST_MODE=y
#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
# CONFIG_USB_PRINTER is not set
CONFIG_USB_WDM=m
# CONFIG_USB_TMC is not set
#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
#
# also be needed; see USB_STORAGE Help for more info
#
# CONFIG_USB_STORAGE is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USBIP_CORE is not set
# CONFIG_USB_MUSB_HDRC is not set
CONFIG_USB_DWC3=m
CONFIG_USB_DWC3_HOST=y
#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=m
# CONFIG_USB_DWC2 is not set
# CONFIG_USB_CHIPIDEA is not set
CONFIG_USB_ISP1760=m
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1760_HOST_ROLE=y
#
# USB port drivers
#
CONFIG_USB_USS720=m
# CONFIG_USB_SERIAL is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
CONFIG_USB_EMI26=m
# CONFIG_USB_ADUTUX is not set
CONFIG_USB_SEVSEG=m
CONFIG_USB_RIO500=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_SISUSBVGA_CON=y
# CONFIG_USB_LD is not set
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
# CONFIG_USB_TEST is not set
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_HUB_USB251XB is not set
# CONFIG_USB_HSIC_USB3503 is not set
# CONFIG_USB_HSIC_USB4604 is not set
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m
# CONFIG_UCSI is not set
#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_USB_GPIO_VBUS=y
CONFIG_USB_ISP1301=m
# CONFIG_USB_GADGET is not set
# CONFIG_USB_ULPI_BUS is not set
CONFIG_UWB=m
CONFIG_UWB_HWA=m
# CONFIG_UWB_WHCI is not set
CONFIG_UWB_I1480U=m
CONFIG_MMC=y
CONFIG_MMC_DEBUG=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=8
CONFIG_MMC_BLOCK_BOUNCE=y
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set
#
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_MMC_SDHCI=m
# CONFIG_MMC_SDHCI_PCI is not set
# CONFIG_MMC_SDHCI_ACPI is not set
CONFIG_MMC_SDHCI_PLTFM=m
CONFIG_MMC_WBSD=y
# CONFIG_MMC_TIFM_SD is not set
# CONFIG_MMC_CB710 is not set
# CONFIG_MMC_VIA_SDMMC is not set
CONFIG_MMC_VUB300=m
# CONFIG_MMC_USHC is not set
CONFIG_MMC_USDHI6ROL0=y
# CONFIG_MMC_REALTEK_USB is not set
# CONFIG_MMC_TOSHIBA_PCI is not set
CONFIG_MMC_MTK=y
CONFIG_MEMSTICK=y
# CONFIG_MEMSTICK_DEBUG is not set
#
# MemoryStick drivers
#
CONFIG_MEMSTICK_UNSAFE_RESUME=y
CONFIG_MSPRO_BLOCK=y
# CONFIG_MS_BLOCK is not set
#
# MemoryStick Host Controller Drivers
#
# CONFIG_MEMSTICK_TIFM_MS is not set
# CONFIG_MEMSTICK_JMICRON_38X is not set
# CONFIG_MEMSTICK_R592 is not set
CONFIG_MEMSTICK_REALTEK_USB=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y
#
# LED drivers
#
CONFIG_LEDS_LM3530=m
CONFIG_LEDS_LM3642=m
CONFIG_LEDS_PCA9532=y
# CONFIG_LEDS_PCA9532_GPIO is not set
CONFIG_LEDS_GPIO=m
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP3952 is not set
CONFIG_LEDS_LP55XX_COMMON=m
CONFIG_LEDS_LP5521=m
CONFIG_LEDS_LP5523=m
# CONFIG_LEDS_LP5562 is not set
CONFIG_LEDS_LP8501=m
# CONFIG_LEDS_LP8788 is not set
# CONFIG_LEDS_LP8860 is not set
CONFIG_LEDS_CLEVO_MAIL=m
CONFIG_LEDS_PCA955X=y
CONFIG_LEDS_PCA963X=m
# CONFIG_LEDS_WM831X_STATUS is not set
# CONFIG_LEDS_WM8350 is not set
CONFIG_LEDS_PWM=y
CONFIG_LEDS_BD2802=y
# CONFIG_LEDS_INTEL_SS4200 is not set
CONFIG_LEDS_LT3593=y
CONFIG_LEDS_ADP5520=m
CONFIG_LEDS_TCA6507=y
CONFIG_LEDS_TLC591XX=m
# CONFIG_LEDS_MAX8997 is not set
CONFIG_LEDS_LM355x=y
CONFIG_LEDS_MENF21BMC=m
#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
# CONFIG_LEDS_MLXCPLD is not set
CONFIG_LEDS_USER=y
# CONFIG_LEDS_NIC78BX is not set
#
# LED Triggers
#
# CONFIG_LEDS_TRIGGERS is not set
# CONFIG_ACCESSIBILITY is not set
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
CONFIG_EDAC_DEBUG=y
CONFIG_EDAC_DECODE_MCE=y
CONFIG_EDAC_MM_EDAC=m
# CONFIG_EDAC_AMD64 is not set
# CONFIG_EDAC_E752X is not set
# CONFIG_EDAC_I82975X is not set
# CONFIG_EDAC_I3000 is not set
# CONFIG_EDAC_I3200 is not set
# CONFIG_EDAC_IE31200 is not set
# CONFIG_EDAC_X38 is not set
# CONFIG_EDAC_I5400 is not set
# CONFIG_EDAC_I7CORE is not set
# CONFIG_EDAC_I5000 is not set
# CONFIG_EDAC_I5100 is not set
# CONFIG_EDAC_I7300 is not set
# CONFIG_EDAC_PND2 is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_SYSTOHC is not set
CONFIG_RTC_DEBUG=y
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
# CONFIG_RTC_INTF_PROC is not set
# CONFIG_RTC_INTF_DEV is not set
CONFIG_RTC_DRV_TEST=m
#
# I2C RTC drivers
#
CONFIG_RTC_DRV_ABB5ZES3=m
CONFIG_RTC_DRV_ABX80X=y
CONFIG_RTC_DRV_DS1307=m
CONFIG_RTC_DRV_DS1307_HWMON=y
CONFIG_RTC_DRV_DS1307_CENTURY=y
CONFIG_RTC_DRV_DS1374=y
# CONFIG_RTC_DRV_DS1374_WDT is not set
CONFIG_RTC_DRV_DS1672=m
CONFIG_RTC_DRV_LP8788=m
CONFIG_RTC_DRV_MAX6900=m
CONFIG_RTC_DRV_MAX8925=y
# CONFIG_RTC_DRV_MAX8997 is not set
CONFIG_RTC_DRV_RS5C372=m
CONFIG_RTC_DRV_ISL1208=y
CONFIG_RTC_DRV_ISL12022=m
CONFIG_RTC_DRV_X1205=y
CONFIG_RTC_DRV_PCF8523=m
CONFIG_RTC_DRV_PCF85063=y
CONFIG_RTC_DRV_PCF8563=m
CONFIG_RTC_DRV_PCF8583=y
CONFIG_RTC_DRV_M41T80=m
# CONFIG_RTC_DRV_M41T80_WDT is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_PALMAS is not set
# CONFIG_RTC_DRV_TPS80031 is not set
CONFIG_RTC_DRV_RC5T583=y
CONFIG_RTC_DRV_S35390A=y
CONFIG_RTC_DRV_FM3130=y
# CONFIG_RTC_DRV_RX8010 is not set
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RX8025=y
CONFIG_RTC_DRV_EM3027=m
# CONFIG_RTC_DRV_RV8803 is not set
#
# SPI RTC drivers
#
CONFIG_RTC_I2C_AND_SPI=y
#
# SPI and I2C RTC drivers
#
CONFIG_RTC_DRV_DS3232=m
# CONFIG_RTC_DRV_PCF2127 is not set
CONFIG_RTC_DRV_RV3029C2=y
# CONFIG_RTC_DRV_RV3029_HWMON is not set
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
CONFIG_RTC_DRV_DS1286=y
CONFIG_RTC_DRV_DS1511=y
CONFIG_RTC_DRV_DS1553=y
CONFIG_RTC_DRV_DS1685_FAMILY=m
CONFIG_RTC_DRV_DS1685=y
# CONFIG_RTC_DRV_DS1689 is not set
# CONFIG_RTC_DRV_DS17285 is not set
# CONFIG_RTC_DRV_DS17485 is not set
# CONFIG_RTC_DRV_DS17885 is not set
# CONFIG_RTC_DS1685_PROC_REGS is not set
CONFIG_RTC_DS1685_SYSFS_REGS=y
CONFIG_RTC_DRV_DS1742=m
CONFIG_RTC_DRV_DS2404=m
# CONFIG_RTC_DRV_DA9063 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
CONFIG_RTC_DRV_BQ4802=y
CONFIG_RTC_DRV_RP5C01=m
CONFIG_RTC_DRV_V3020=y
# CONFIG_RTC_DRV_WM831X is not set
# CONFIG_RTC_DRV_WM8350 is not set
# CONFIG_RTC_DRV_PCF50633 is not set
#
# on-CPU RTC drivers
#
#
# HID Sensor RTC drivers
#
CONFIG_RTC_DRV_HID_SENSOR_TIME=m
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set
#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_INTEL_IDMA64=y
# CONFIG_INTEL_IOATDMA is not set
CONFIG_QCOM_HIDMA_MGMT=m
CONFIG_QCOM_HIDMA=y
CONFIG_DW_DMAC_CORE=y
CONFIG_DW_DMAC=y
# CONFIG_DW_DMAC_PCI is not set
CONFIG_HSU_DMA=y
#
# DMA Clients
#
CONFIG_ASYNC_TX_DMA=y
CONFIG_DMATEST=m
#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_AUXDISPLAY=y
CONFIG_KS0108=m
CONFIG_KS0108_PORT=0x378
CONFIG_KS0108_DELAY=2
CONFIG_CFAG12864B=m
CONFIG_CFAG12864B_RATE=20
CONFIG_IMG_ASCII_LCD=m
# CONFIG_UIO is not set
# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRTIO=m
#
# Virtio drivers
#
# CONFIG_VIRTIO_PCI is not set
CONFIG_VIRTIO_BALLOON=m
# CONFIG_VIRTIO_INPUT is not set
CONFIG_VIRTIO_MMIO=m
CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
CONFIG_STAGING=y
CONFIG_COMEDI=m
# CONFIG_COMEDI_DEBUG is not set
CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
CONFIG_COMEDI_MISC_DRIVERS=y
CONFIG_COMEDI_BOND=m
# CONFIG_COMEDI_TEST is not set
CONFIG_COMEDI_PARPORT=m
CONFIG_COMEDI_SERIAL2002=m
# CONFIG_COMEDI_ISA_DRIVERS is not set
# CONFIG_COMEDI_PCI_DRIVERS is not set
# CONFIG_COMEDI_USB_DRIVERS is not set
CONFIG_COMEDI_8255=m
CONFIG_COMEDI_8255_SA=m
CONFIG_COMEDI_KCOMEDILIB=m
# CONFIG_RTS5208 is not set
#
# IIO staging drivers
#
#
# Accelerometers
#
#
# Analog to digital converters
#
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set
#
# Capacitance to digital converters
#
CONFIG_AD7150=m
# CONFIG_AD7152 is not set
CONFIG_AD7746=m
#
# Direct Digital Synthesis
#
#
# Digital gyroscope sensors
#
#
# Network Analyzer, Impedance Converters
#
CONFIG_AD5933=m
#
# Light sensors
#
CONFIG_SENSORS_ISL29028=m
CONFIG_TSL2x7x=m
#
# Active energy metering IC
#
CONFIG_ADE7854=m
CONFIG_ADE7854_I2C=m
#
# Resolver to digital converters
#
#
# Triggers - standalone
#
# CONFIG_FB_SM750 is not set
# CONFIG_FB_XGI is not set
#
# Speakup console speech
#
CONFIG_SPEAKUP=m
CONFIG_SPEAKUP_SYNTH_ACNTSA=m
CONFIG_SPEAKUP_SYNTH_APOLLO=m
# CONFIG_SPEAKUP_SYNTH_AUDPTR is not set
CONFIG_SPEAKUP_SYNTH_BNS=m
CONFIG_SPEAKUP_SYNTH_DECTLK=m
CONFIG_SPEAKUP_SYNTH_DECEXT=m
CONFIG_SPEAKUP_SYNTH_LTLK=m
CONFIG_SPEAKUP_SYNTH_SOFT=m
CONFIG_SPEAKUP_SYNTH_SPKOUT=m
CONFIG_SPEAKUP_SYNTH_TXPRT=m
# CONFIG_SPEAKUP_SYNTH_DUMMY is not set
# CONFIG_STAGING_MEDIA is not set
#
# Android
#
# CONFIG_LTE_GDM724X is not set
# CONFIG_DGNC is not set
CONFIG_GS_FPGABOOT=y
CONFIG_CRYPTO_SKEIN=m
# CONFIG_UNISYSSPAR is not set
CONFIG_MOST=y
CONFIG_MOSTCORE=y
CONFIG_AIM_CDEV=m
# CONFIG_AIM_NETWORK is not set
# CONFIG_AIM_V4L2 is not set
CONFIG_HDM_I2C=m
# CONFIG_HDM_USB is not set
# CONFIG_KS7010 is not set
# CONFIG_GREYBUS is not set
CONFIG_X86_PLATFORM_DEVICES=y
# CONFIG_ACERHDF is not set
# CONFIG_ASUS_LAPTOP is not set
# CONFIG_DELL_LAPTOP is not set
# CONFIG_DELL_SMO8800 is not set
# CONFIG_FUJITSU_LAPTOP is not set
# CONFIG_FUJITSU_TABLET is not set
# CONFIG_HP_ACCEL is not set
# CONFIG_HP_WIRELESS is not set
# CONFIG_PANASONIC_LAPTOP is not set
# CONFIG_THINKPAD_ACPI is not set
CONFIG_SENSORS_HDAPS=m
# CONFIG_INTEL_MENLOW is not set
# CONFIG_ASUS_WIRELESS is not set
# CONFIG_ACPI_WMI is not set
# CONFIG_TOPSTAR_LAPTOP is not set
# CONFIG_TOSHIBA_BT_RFKILL is not set
# CONFIG_TOSHIBA_HAPS is not set
# CONFIG_ACPI_CMPC is not set
# CONFIG_INTEL_HID_EVENT is not set
# CONFIG_INTEL_VBTN is not set
# CONFIG_INTEL_IPS is not set
# CONFIG_INTEL_PMC_CORE is not set
# CONFIG_IBM_RTL is not set
CONFIG_SAMSUNG_LAPTOP=m
# CONFIG_SAMSUNG_Q10 is not set
# CONFIG_APPLE_GMUX is not set
# CONFIG_INTEL_RST is not set
# CONFIG_INTEL_SMARTCONNECT is not set
# CONFIG_PVPANIC is not set
# CONFIG_INTEL_PMC_IPC is not set
# CONFIG_SURFACE_PRO3_BUTTON is not set
# CONFIG_SURFACE_3_BUTTON is not set
CONFIG_INTEL_PUNIT_IPC=y
# CONFIG_MLX_PLATFORM is not set
CONFIG_MLX_CPLD_PLATFORM=y
# CONFIG_SILEAD_DMI is not set
CONFIG_PMC_ATOM=y
CONFIG_CHROME_PLATFORMS=y
CONFIG_CHROMEOS_LAPTOP=y
CONFIG_CHROMEOS_PSTORE=m
CONFIG_CROS_EC_CHARDEV=y
CONFIG_CROS_EC_LPC=m
CONFIG_CROS_EC_PROTO=y
# CONFIG_CROS_KBD_LED_BACKLIGHT is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
#
# Common Clock Framework
#
# CONFIG_COMMON_CLK_WM831X is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_COMMON_CLK_NXP is not set
# CONFIG_COMMON_CLK_PALMAS is not set
# CONFIG_COMMON_CLK_PWM is not set
# CONFIG_COMMON_CLK_PXA is not set
# CONFIG_COMMON_CLK_PIC32 is not set
#
# Hardware Spinlock drivers
#
#
# Clock Source drivers
#
CONFIG_CLKEVT_I8253=y
CONFIG_I8253_LOCK=y
CONFIG_CLKBLD_I8253=y
# CONFIG_ATMEL_PIT is not set
# CONFIG_SH_TIMER_CMT is not set
# CONFIG_SH_TIMER_MTU2 is not set
# CONFIG_SH_TIMER_TMU is not set
# CONFIG_EM_TIMER_STI is not set
CONFIG_MAILBOX=y
# CONFIG_PCC is not set
CONFIG_ALTERA_MBOX=m
CONFIG_IOMMU_SUPPORT=y
#
# Generic IOMMU Pagetable Support
#
# CONFIG_AMD_IOMMU is not set
#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
#
# Rpmsg drivers
#
#
# SOC (System On Chip) specific Drivers
#
#
# Broadcom SoC drivers
#
#
# i.MX SoC drivers
#
# CONFIG_SUNXI_SRAM is not set
CONFIG_SOC_TI=y
CONFIG_SOC_ZTE=y
CONFIG_PM_DEVFREQ=y
#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m
# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
CONFIG_DEVFREQ_GOV_POWERSAVE=m
# CONFIG_DEVFREQ_GOV_USERSPACE is not set
CONFIG_DEVFREQ_GOV_PASSIVE=y
#
# DEVFREQ Drivers
#
# CONFIG_PM_DEVFREQ_EVENT is not set
CONFIG_EXTCON=y
#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=m
CONFIG_EXTCON_AXP288=m
CONFIG_EXTCON_GPIO=y
# CONFIG_EXTCON_INTEL_INT3496 is not set
CONFIG_EXTCON_MAX14577=y
CONFIG_EXTCON_MAX3355=m
CONFIG_EXTCON_MAX77693=y
CONFIG_EXTCON_MAX8997=y
CONFIG_EXTCON_PALMAS=m
CONFIG_EXTCON_QCOM_SPMI_MISC=y
CONFIG_EXTCON_RT8973A=y
CONFIG_EXTCON_SM5502=m
# CONFIG_EXTCON_USB_GPIO is not set
CONFIG_MEMORY=y
CONFIG_IIO=m
CONFIG_IIO_BUFFER=y
# CONFIG_IIO_BUFFER_CB is not set
CONFIG_IIO_KFIFO_BUF=m
CONFIG_IIO_TRIGGERED_BUFFER=m
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
#
# Accelerometers
#
# CONFIG_BMA180 is not set
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
# CONFIG_DA280 is not set
CONFIG_DA311=m
CONFIG_DMARD09=m
CONFIG_DMARD10=m
CONFIG_HID_SENSOR_ACCEL_3D=m
# CONFIG_KXSD9 is not set
# CONFIG_KXCJK1013 is not set
CONFIG_MC3230=m
# CONFIG_MMA7455_I2C is not set
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
CONFIG_MMA9551=m
CONFIG_MMA9553=m
# CONFIG_MXC4005 is not set
CONFIG_MXC6255=m
# CONFIG_STK8312 is not set
CONFIG_STK8BA50=m
#
# Analog to digital converters
#
CONFIG_AD7291=m
CONFIG_AD799X=m
CONFIG_AXP288_ADC=m
CONFIG_HX711=m
CONFIG_INA2XX_ADC=m
# CONFIG_LP8788_ADC is not set
# CONFIG_LTC2485 is not set
CONFIG_MAX1363=m
# CONFIG_MCP3422 is not set
CONFIG_MEN_Z188_ADC=m
CONFIG_NAU7802=m
CONFIG_PALMAS_GPADC=m
CONFIG_QCOM_SPMI_IADC=m
# CONFIG_QCOM_SPMI_VADC is not set
# CONFIG_TI_ADC081C is not set
CONFIG_TWL4030_MADC=m
CONFIG_TWL6030_GPADC=m
CONFIG_VIPERBOARD_ADC=m
#
# Amplifiers
#
#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_IAQCORE=m
CONFIG_VZ89X=m
CONFIG_IIO_CROS_EC_SENSORS_CORE=m
CONFIG_IIO_CROS_EC_SENSORS=m
#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
CONFIG_IIO_MS_SENSORS_I2C=m
#
# SSP Sensor Common
#
CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_CORE=m
#
# Counters
#
#
# Digital to analog converters
#
CONFIG_AD5064=m
CONFIG_AD5380=m
# CONFIG_AD5446 is not set
# CONFIG_AD5593R is not set
CONFIG_M62332=m
# CONFIG_MAX517 is not set
CONFIG_MCP4725=m
#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
#
# Frequency Synthesizers DDS/PLL
#
#
# Clock Generator/Distribution
#
#
# Phase-Locked Loop (PLL) frequency synthesizers
#
#
# Digital gyroscope sensors
#
# CONFIG_BMG160 is not set
CONFIG_HID_SENSOR_GYRO_3D=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_ITG3200=m
#
# Health Sensors
#
#
# Heart Rate Monitors
#
CONFIG_AFE4404=m
CONFIG_MAX30100=m
#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTU21=m
CONFIG_SI7005=m
# CONFIG_SI7020 is not set
#
# Inertial measurement units
#
# CONFIG_BMI160_I2C is not set
# CONFIG_KMX61 is not set
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
#
# Light sensors
#
# CONFIG_ACPI_ALS is not set
CONFIG_ADJD_S311=m
CONFIG_AL3320A=m
CONFIG_APDS9300=m
# CONFIG_APDS9960 is not set
CONFIG_BH1750=m
CONFIG_BH1780=m
# CONFIG_CM32181 is not set
# CONFIG_CM3232 is not set
# CONFIG_CM3323 is not set
CONFIG_CM36651=m
CONFIG_GP2AP020A00F=m
CONFIG_SENSORS_ISL29018=m
# CONFIG_ISL29125 is not set
CONFIG_HID_SENSOR_ALS=m
CONFIG_HID_SENSOR_PROX=m
# CONFIG_JSA1212 is not set
CONFIG_RPR0521=m
# CONFIG_LTR501 is not set
CONFIG_MAX44000=m
CONFIG_OPT3001=m
CONFIG_PA12203001=m
CONFIG_SI1145=m
CONFIG_STK3310=m
# CONFIG_TCS3414 is not set
CONFIG_TCS3472=m
# CONFIG_SENSORS_TSL2563 is not set
CONFIG_TSL2583=m
CONFIG_TSL4531=m
CONFIG_US5182D=m
# CONFIG_VCNL4000 is not set
# CONFIG_VEML6070 is not set
#
# Magnetometer sensors
#
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_MAG3110=m
CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
CONFIG_MMC35240=m
# CONFIG_IIO_ST_MAGN_3AXIS is not set
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
#
# Inclinometer sensors
#
CONFIG_HID_SENSOR_INCLINOMETER_3D=m
CONFIG_HID_SENSOR_DEVICE_ROTATION=m
#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
# CONFIG_IIO_INTERRUPT_TRIGGER is not set
# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
CONFIG_IIO_SYSFS_TRIGGER=m
#
# Digital potentiometers
#
# CONFIG_DS1803 is not set
CONFIG_MCP4531=m
# CONFIG_TPL0102 is not set
#
# Digital potentiostats
#
# CONFIG_LMP91000 is not set
#
# Pressure sensors
#
# CONFIG_ABP060MG is not set
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
CONFIG_IIO_CROS_EC_BARO=m
# CONFIG_HID_SENSOR_PRESS is not set
CONFIG_HP03=m
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
# CONFIG_MPL3115 is not set
CONFIG_MS5611=m
CONFIG_MS5611_I2C=m
CONFIG_MS5637=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_T5403=m
CONFIG_HP206C=m
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
#
# Lightning sensors
#
#
# Proximity and distance sensors
#
CONFIG_LIDAR_LITE_V2=m
# CONFIG_SX9500 is not set
# CONFIG_SRF08 is not set
#
# Temperature sensors
#
CONFIG_MLX90614=m
CONFIG_TMP006=m
CONFIG_TMP007=m
CONFIG_TSYS01=m
# CONFIG_TSYS02D is not set
# CONFIG_NTB is not set
# CONFIG_VME_BUS is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
CONFIG_PWM_CROS_EC=y
# CONFIG_PWM_LPSS_PCI is not set
# CONFIG_PWM_LPSS_PLATFORM is not set
CONFIG_PWM_PCA9685=m
CONFIG_PWM_TWL=m
CONFIG_PWM_TWL_LED=m
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_IPACK_BUS=y
# CONFIG_BOARD_TPCI200 is not set
CONFIG_SERIAL_IPOCTAL=m
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_ATH79 is not set
# CONFIG_RESET_BERLIN is not set
# CONFIG_RESET_IMX7 is not set
# CONFIG_RESET_LPC18XX is not set
# CONFIG_RESET_MESON is not set
# CONFIG_RESET_PISTACHIO is not set
# CONFIG_RESET_SOCFPGA is not set
# CONFIG_RESET_STM32 is not set
# CONFIG_RESET_SUNXI is not set
CONFIG_TI_SYSCON_RESET=y
# CONFIG_RESET_ZYNQ is not set
# CONFIG_RESET_TEGRA_BPMP is not set
CONFIG_FMC=y
CONFIG_FMC_FAKEDEV=y
CONFIG_FMC_TRIVIAL=y
CONFIG_FMC_WRITE_EEPROM=m
CONFIG_FMC_CHARDEV=y
#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_PHY_PXA_28NM_HSIC=y
CONFIG_PHY_PXA_28NM_USB2=y
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_POWERCAP is not set
CONFIG_MCB=m
# CONFIG_MCB_PCI is not set
# CONFIG_MCB_LPC is not set
#
# Performance monitor support
#
CONFIG_RAS=y
# CONFIG_MCE_AMD_INJ is not set
# CONFIG_THUNDERBOLT is not set
#
# Android
#
# CONFIG_ANDROID is not set
# CONFIG_LIBNVDIMM is not set
CONFIG_NVMEM=y
CONFIG_STM=y
CONFIG_STM_DUMMY=m
CONFIG_STM_SOURCE_CONSOLE=m
CONFIG_STM_SOURCE_HEARTBEAT=m
# CONFIG_STM_SOURCE_FTRACE is not set
CONFIG_INTEL_TH=m
# CONFIG_INTEL_TH_PCI is not set
CONFIG_INTEL_TH_GTH=m
# CONFIG_INTEL_TH_STH is not set
# CONFIG_INTEL_TH_MSU is not set
# CONFIG_INTEL_TH_PTI is not set
CONFIG_INTEL_TH_DEBUG=y
#
# FPGA Configuration Support
#
CONFIG_FPGA=y
#
# FSI support
#
CONFIG_FSI=y
# CONFIG_TEE is not set
#
# Firmware Drivers
#
CONFIG_EDD=y
# CONFIG_EDD_OFF is not set
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_DELL_RBU=y
# CONFIG_DCDBAS is not set
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=m
CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
# CONFIG_ISCSI_IBFT_FIND is not set
# CONFIG_FW_CFG_SYSFS is not set
# CONFIG_GOOGLE_FIRMWARE is not set
# CONFIG_EFI_DEV_PATH_PARSER is not set
#
# Tegra firmware driver
#
#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_EXT2_FS=m
# CONFIG_EXT2_FS_XATTR is not set
CONFIG_EXT3_FS=m
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT4_FS=m
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_ENCRYPTION is not set
CONFIG_EXT4_DEBUG=y
CONFIG_JBD2=m
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=m
CONFIG_REISERFS_FS=y
# CONFIG_REISERFS_CHECK is not set
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
# CONFIG_REISERFS_FS_POSIX_ACL is not set
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=y
CONFIG_JFS_POSIX_ACL=y
# CONFIG_JFS_SECURITY is not set
CONFIG_JFS_DEBUG=y
CONFIG_JFS_STATISTICS=y
# CONFIG_XFS_FS is not set
CONFIG_GFS2_FS=m
# CONFIG_OCFS2_FS is not set
CONFIG_BTRFS_FS=m
# CONFIG_BTRFS_FS_POSIX_ACL is not set
CONFIG_BTRFS_FS_CHECK_INTEGRITY=y
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
CONFIG_NILFS2_FS=y
# CONFIG_F2FS_FS is not set
# CONFIG_FS_DAX is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
# CONFIG_EXPORTFS_BLOCK_OPS is not set
CONFIG_FILE_LOCKING=y
# CONFIG_MANDATORY_FILE_LOCKING is not set
# CONFIG_FS_ENCRYPTION is not set
CONFIG_FSNOTIFY=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
CONFIG_QUOTA=y
# CONFIG_QUOTA_NETLINK_INTERFACE is not set
# CONFIG_PRINT_QUOTA_WARNING is not set
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QFMT_V1=m
# CONFIG_QFMT_V2 is not set
CONFIG_QUOTACTL=y
CONFIG_QUOTACTL_COMPAT=y
# CONFIG_AUTOFS4_FS is not set
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_OVERLAY_FS=y
CONFIG_OVERLAY_FS_REDIRECT_DIR=y
#
# Caches
#
CONFIG_FSCACHE=y
# CONFIG_FSCACHE_STATS is not set
CONFIG_FSCACHE_HISTOGRAM=y
CONFIG_FSCACHE_DEBUG=y
# CONFIG_FSCACHE_OBJECT_LIST is not set
CONFIG_CACHEFILES=y
# CONFIG_CACHEFILES_DEBUG is not set
CONFIG_CACHEFILES_HISTOGRAM=y
#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=y
CONFIG_UDF_NLS=y
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_NTFS_FS=y
CONFIG_NTFS_DEBUG=y
# CONFIG_NTFS_RW is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_VMCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
# CONFIG_PROC_CHILDREN is not set
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_TMPFS_XATTR is not set
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_MISC_FILESYSTEMS=y
CONFIG_ORANGEFS_FS=m
# CONFIG_ADFS_FS is not set
CONFIG_AFFS_FS=y
CONFIG_ECRYPT_FS=m
CONFIG_ECRYPT_FS_MESSAGING=y
# CONFIG_HFS_FS is not set
CONFIG_HFSPLUS_FS=m
# CONFIG_HFSPLUS_FS_POSIX_ACL is not set
CONFIG_BEFS_FS=y
CONFIG_BEFS_DEBUG=y
CONFIG_BFS_FS=m
CONFIG_EFS_FS=y
# CONFIG_CRAMFS is not set
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_FILE_CACHE is not set
CONFIG_SQUASHFS_FILE_DIRECT=y
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_XATTR=y
# CONFIG_SQUASHFS_ZLIB is not set
CONFIG_SQUASHFS_LZ4=y
# CONFIG_SQUASHFS_LZO is not set
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
CONFIG_VXFS_FS=m
CONFIG_MINIX_FS=m
CONFIG_OMFS_FS=m
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
CONFIG_ROMFS_FS=m
CONFIG_ROMFS_BACKED_BY_BLOCK=y
CONFIG_ROMFS_ON_BLOCK=y
CONFIG_PSTORE=m
CONFIG_PSTORE_ZLIB_COMPRESS=y
# CONFIG_PSTORE_LZO_COMPRESS is not set
# CONFIG_PSTORE_LZ4_COMPRESS is not set
CONFIG_PSTORE_CONSOLE=y
# CONFIG_PSTORE_PMSG is not set
CONFIG_PSTORE_FTRACE=y
# CONFIG_PSTORE_RAM is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=m
# CONFIG_NLS_CODEPAGE_737 is not set
CONFIG_NLS_CODEPAGE_775=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=y
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=y
# CONFIG_NLS_CODEPAGE_863 is not set
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=y
# CONFIG_NLS_CODEPAGE_866 is not set
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
# CONFIG_NLS_CODEPAGE_950 is not set
CONFIG_NLS_CODEPAGE_932=m
# CONFIG_NLS_CODEPAGE_949 is not set
CONFIG_NLS_CODEPAGE_874=y
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=y
CONFIG_NLS_CODEPAGE_1251=y
CONFIG_NLS_ASCII=y
# CONFIG_NLS_ISO8859_1 is not set
CONFIG_NLS_ISO8859_2=y
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
CONFIG_NLS_ISO8859_5=y
CONFIG_NLS_ISO8859_6=y
# CONFIG_NLS_ISO8859_7 is not set
CONFIG_NLS_ISO8859_9=y
# CONFIG_NLS_ISO8859_13 is not set
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=y
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=y
# CONFIG_NLS_MAC_CELTIC is not set
# CONFIG_NLS_MAC_CENTEURO is not set
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=y
# CONFIG_NLS_MAC_GAELIC is not set
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=y
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
CONFIG_NLS_UTF8=y
#
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_DYNAMIC_DEBUG is not set
#
# Compile-time checks and compiler options
#
# CONFIG_DEBUG_INFO is not set
# CONFIG_ENABLE_WARN_DEPRECATED is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=8192
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_READABLE_ASM is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_PAGE_OWNER is not set
CONFIG_DEBUG_FS=y
CONFIG_HEADERS_CHECK=y
CONFIG_DEBUG_SECTION_MISMATCH=y
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_STACK_VALIDATION is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_DEBUG_KERNEL=y
#
# Memory Debugging
#
CONFIG_PAGE_EXTENSION=y
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_PAGE_POISONING=y
# CONFIG_PAGE_POISONING_NO_SANITY is not set
CONFIG_PAGE_POISONING_ZERO=y
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
# CONFIG_DEBUG_OBJECTS is not set
CONFIG_SLUB_DEBUG_ON=y
CONFIG_SLUB_STATS=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_VM is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
# CONFIG_DEBUG_STACKOVERFLOW is not set
CONFIG_HAVE_ARCH_KMEMCHECK=y
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_KASAN=y
# CONFIG_KASAN_OUTLINE is not set
CONFIG_KASAN_INLINE=y
# CONFIG_TEST_KASAN is not set
CONFIG_ARCH_HAS_KCOV=y
# CONFIG_KCOV is not set
# CONFIG_DEBUG_SHIRQ is not set
#
# Debug Lockups and Hangs
#
# CONFIG_LOCKUP_DETECTOR is not set
# CONFIG_DETECT_HUNG_TASK is not set
# CONFIG_WQ_WATCHDOG is not set
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_ON_OOPS_VALUE=1
CONFIG_PANIC_TIMEOUT=0
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHED_INFO is not set
# CONFIG_SCHEDSTATS is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
# CONFIG_DEBUG_TIMEKEEPING is not set
CONFIG_DEBUG_PREEMPT=y
#
# Lock Debugging (spinlocks, mutexes, etc...)
#
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
CONFIG_STACKTRACE=y
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PI_LIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set
#
# RCU Debugging
#
# CONFIG_PROVE_RCU is not set
# CONFIG_SPARSE_RCU_POINTER is not set
# CONFIG_TORTURE_TEST is not set
# CONFIG_RCU_PERF_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_FENTRY=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACER_MAX_TRACE=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_GENERIC_TRACER=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
CONFIG_FUNCTION_TRACER=y
CONFIG_FUNCTION_GRAPH_TRACER=y
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_PREEMPT_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
CONFIG_FTRACE_SYSCALLS=y
CONFIG_TRACER_SNAPSHOT=y
# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set
CONFIG_TRACE_BRANCH_PROFILING=y
# CONFIG_BRANCH_PROFILE_NONE is not set
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
CONFIG_PROFILE_ALL_BRANCHES=y
# CONFIG_BRANCH_TRACER is not set
CONFIG_STACK_TRACER=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_PROBE_EVENTS=y
# CONFIG_DYNAMIC_FTRACE is not set
CONFIG_FUNCTION_PROFILER=y
# CONFIG_FTRACE_STARTUP_TEST is not set
# CONFIG_MMIOTRACE is not set
CONFIG_TRACING_MAP=y
CONFIG_HIST_TRIGGERS=y
CONFIG_TRACEPOINT_BENCHMARK=y
CONFIG_RING_BUFFER_BENCHMARK=m
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
CONFIG_TRACE_ENUM_MAP_FILE=y
CONFIG_TRACING_EVENTS_GPIO=y
#
# Runtime Testing
#
CONFIG_LKDTM=m
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_TEST_SORT is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_TEST_HEXDUMP is not set
CONFIG_TEST_STRING_HELPERS=m
# CONFIG_TEST_KSTRTOX is not set
CONFIG_TEST_PRINTF=y
CONFIG_TEST_BITMAP=y
# CONFIG_TEST_UUID is not set
CONFIG_TEST_RHASHTABLE=y
# CONFIG_TEST_HASH is not set
# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
# CONFIG_DMA_API_DEBUG is not set
CONFIG_TEST_LKM=m
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_UDELAY=m
# CONFIG_MEMTEST is not set
CONFIG_TEST_STATIC_KEYS=m
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
CONFIG_UBSAN=y
# CONFIG_UBSAN_SANITIZE_ALL is not set
# CONFIG_UBSAN_ALIGNMENT is not set
# CONFIG_UBSAN_NULL is not set
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
# CONFIG_STRICT_DEVMEM is not set
CONFIG_X86_VERBOSE_BOOTUP=y
CONFIG_EARLY_PRINTK=y
# CONFIG_EARLY_PRINTK_DBGP is not set
CONFIG_X86_PTDUMP_CORE=y
# CONFIG_X86_PTDUMP is not set
CONFIG_DEBUG_WX=y
CONFIG_DOUBLEFAULT=y
# CONFIG_DEBUG_TLBFLUSH is not set
# CONFIG_IOMMU_STRESS is not set
CONFIG_HAVE_MMIOTRACE_SUPPORT=y
CONFIG_IO_DELAY_TYPE_0X80=0
CONFIG_IO_DELAY_TYPE_0XED=1
CONFIG_IO_DELAY_TYPE_UDELAY=2
CONFIG_IO_DELAY_TYPE_NONE=3
# CONFIG_IO_DELAY_0X80 is not set
CONFIG_IO_DELAY_0XED=y
# CONFIG_IO_DELAY_UDELAY is not set
# CONFIG_IO_DELAY_NONE is not set
CONFIG_DEFAULT_IO_DELAY_TYPE=1
# CONFIG_DEBUG_BOOT_PARAMS is not set
# CONFIG_CPA_DEBUG is not set
CONFIG_OPTIMIZE_INLINING=y
# CONFIG_DEBUG_ENTRY is not set
# CONFIG_DEBUG_NMI_SELFTEST is not set
CONFIG_X86_DEBUG_FPU=y
CONFIG_PUNIT_ATOM_DEBUG=m
#
# Security options
#
CONFIG_KEYS=y
CONFIG_PERSISTENT_KEYRINGS=y
# CONFIG_BIG_KEYS is not set
# CONFIG_TRUSTED_KEYS is not set
CONFIG_ENCRYPTED_KEYS=m
# CONFIG_KEY_DH_OPERATIONS is not set
CONFIG_SECURITY_DMESG_RESTRICT=y
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_PATH is not set
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
CONFIG_HARDENED_USERCOPY=y
# CONFIG_STATIC_USERMODEHELPER is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_SECURITY_APPARMOR is not set
# CONFIG_SECURITY_LOADPIN is not set
CONFIG_SECURITY_YAMA=y
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
# CONFIG_IMA is not set
# CONFIG_EVM is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_XOR_BLOCKS=m
CONFIG_CRYPTO=y
#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=m
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=m
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_USER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_MCRYPTD=y
# CONFIG_CRYPTO_AUTHENC is not set
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ABLK_HELPER=y
CONFIG_CRYPTO_GLUE_HELPER_X86=y
#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_SEQIV=y
# CONFIG_CRYPTO_ECHAINIV is not set
#
# Block modes
#
CONFIG_CRYPTO_CBC=m
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_KEYWRAP=y
#
# Hash modes
#
CONFIG_CRYPTO_CMAC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_VMAC=m
#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32C_INTEL=m
# CONFIG_CRYPTO_CRC32 is not set
# CONFIG_CRYPTO_CRC32_PCLMUL is not set
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRCT10DIF_PCLMUL=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_POLY1305_X86_64=y
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=m
CONFIG_CRYPTO_MICHAEL_MIC=y
# CONFIG_CRYPTO_RMD128 is not set
CONFIG_CRYPTO_RMD160=y
# CONFIG_CRYPTO_RMD256 is not set
CONFIG_CRYPTO_RMD320=m
CONFIG_CRYPTO_SHA1=y
# CONFIG_CRYPTO_SHA1_SSSE3 is not set
# CONFIG_CRYPTO_SHA256_SSSE3 is not set
CONFIG_CRYPTO_SHA512_SSSE3=y
CONFIG_CRYPTO_SHA1_MB=m
CONFIG_CRYPTO_SHA256_MB=y
# CONFIG_CRYPTO_SHA512_MB is not set
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
# CONFIG_CRYPTO_SHA3 is not set
CONFIG_CRYPTO_TGR192=y
# CONFIG_CRYPTO_WP512 is not set
CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m
#
# Ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_AES_X86_64=m
# CONFIG_CRYPTO_AES_NI_INTEL is not set
CONFIG_CRYPTO_ANUBIS=y
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_BLOWFISH_COMMON=m
# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set
# CONFIG_CRYPTO_CAMELLIA is not set
CONFIG_CRYPTO_CAMELLIA_X86_64=m
CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=m
# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set
CONFIG_CRYPTO_CAST_COMMON=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST5_AVX_X86_64=y
CONFIG_CRYPTO_CAST6=m
# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
CONFIG_CRYPTO_SALSA20=m
CONFIG_CRYPTO_SALSA20_X86_64=m
CONFIG_CRYPTO_CHACHA20=y
# CONFIG_CRYPTO_CHACHA20_X86_64 is not set
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_SERPENT_SSE2_X86_64=y
CONFIG_CRYPTO_SERPENT_AVX_X86_64=m
CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m
# CONFIG_CRYPTO_TEA is not set
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y
CONFIG_CRYPTO_TWOFISH_X86_64=m
CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=m
# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set
#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=m
CONFIG_CRYPTO_842=m
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=m
#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
CONFIG_CRYPTO_HASH_INFO=y
# CONFIG_CRYPTO_HW is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
# CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE is not set
#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
CONFIG_SYSTEM_EXTRA_CERTIFICATE=y
CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
CONFIG_HAVE_KVM=y
# CONFIG_VIRTUALIZATION is not set
CONFIG_BINARY_PRINTF=y
#
# Library routines
#
CONFIG_RAID6_PQ=m
CONFIG_BITREVERSE=y
# CONFIG_HAVE_ARCH_BITREVERSE is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IO=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_CRC_CCITT=m
CONFIG_CRC16=m
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
CONFIG_CRC32_SELFTEST=m
# CONFIG_CRC32_SLICEBY8 is not set
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_BIT=y
CONFIG_CRC7=m
# CONFIG_LIBCRC32C is not set
# CONFIG_CRC8 is not set
# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
CONFIG_RANDOM32_SELFTEST=y
CONFIG_842_COMPRESS=m
CONFIG_842_DECOMPRESS=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=m
CONFIG_LZ4_DECOMPRESS=y
CONFIG_XZ_DEC=y
CONFIG_XZ_DEC_X86=y
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_IA64=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_XZ_DEC_TEST=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
# CONFIG_DMA_NOOP_OPS is not set
# CONFIG_DMA_VIRT_OPS is not set
CONFIG_DQL=y
CONFIG_GLOB=y
CONFIG_GLOB_SELFTEST=m
CONFIG_NLATTR=y
CONFIG_CLZ_TAB=y
# CONFIG_CORDIC is not set
CONFIG_DDR=y
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_FONT_SUPPORT=m
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
# CONFIG_SG_SPLIT is not set
CONFIG_SG_POOL=y
CONFIG_ARCH_HAS_SG_CHAIN=y
CONFIG_ARCH_HAS_PMEM_API=y
CONFIG_ARCH_HAS_MMIO_FLUSH=y
CONFIG_STACKDEPOT=y
CONFIG_SBITMAP=y
^ permalink raw reply
* Re: [PATCH net-next v2] bindings: net: stmmac: add missing note about LPI interrupt
From: Giuseppe CAVALLARO @ 2017-04-11 6:08 UTC (permalink / raw)
To: Niklas Cassel, Rob Herring, Mark Rutland, David S. Miller,
Joao Pinto, Niklas Cassel, Alexandre TORGUE, Thierry Reding,
Eric Engestrom
Cc: netdev, devicetree, linux-kernel
In-Reply-To: <20170410074320.9506-1-niklass@axis.com>
Hi Niklas
On 4/10/2017 9:43 AM, Niklas Cassel wrote:
> From: Niklas Cassel <niklas.cassel@axis.com>
>
> The hardware has a LPI interrupt.
> There is already code in the stmmac driver to parse and handle the
> interrupt. However, this information was missing from the DT binding.
i wonder if we could improve the comments in this patch too
> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
> ---
> Documentation/devicetree/bindings/net/stmmac.txt | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
> index f652b0c384ce..84e4cbfd3b0f 100644
> --- a/Documentation/devicetree/bindings/net/stmmac.txt
> +++ b/Documentation/devicetree/bindings/net/stmmac.txt
> @@ -8,8 +8,8 @@ Required properties:
> that services interrupts for this device
> - interrupts: Should contain the STMMAC interrupts
> - interrupt-names: Should contain the interrupt names "macirq"
> - "eth_wake_irq" if this interrupt is supported in the "interrupts"
> - property
> + "eth_wake_irq" if this interrupt is supported in the "interrupts" property
this is the PMT interrupt to manage the remote wake-up packet detection
> + "eth_lpi" if this interrupt is supported in the "interrupts" property
This is the interrupt that occurs when Tx or Rx enter/exit from LPI state
Regards
Peppe
> - phy-mode: See ethernet.txt file in the same directory.
> - snps,reset-gpio gpio number for phy reset.
> - snps,reset-active-low boolean flag to indicate if phy reset is active low.
> @@ -152,8 +152,8 @@ Examples:
> compatible = "st,spear600-gmac";
> reg = <0xe0800000 0x8000>;
> interrupt-parent = <&vic1>;
> - interrupts = <24 23>;
> - interrupt-names = "macirq", "eth_wake_irq";
> + interrupts = <24 23 22>;
> + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
> mac-address = [000000000000]; /* Filled in by U-Boot */
> max-frame-size = <3800>;
> phy-mode = "gmii";
^ permalink raw reply
* Re: [PATCH v3 14/37] mtd: nand: denali: support "nand-ecc-strength" DT property
From: Masahiro Yamada @ 2017-04-11 6:19 UTC (permalink / raw)
To: Boris Brezillon
Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Enrico Jorns,
Artem Bityutskiy, Dinh Nguyen, Marek Vasut, Graham Moore,
David Woodhouse, Masami Hiramatsu, Chuanxiao Dong, Jassi Brar,
devicetree-u79uwXL29TY76Z2rM5mHXA, Linux Kernel Mailing List,
Brian Norris, Richard Weinberger, Cyrille Pitchen, Rob Herring,
Mark Rutland
In-Reply-To: <20170409183301.037d3f95@bbrezillon>
Hi Boris,
2017-04-10 1:33 GMT+09:00 Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>:
> On Mon, 3 Apr 2017 12:16:34 +0900
> Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org> wrote:
>
>> Hi Boris,
>>
>>
>>
>> 2017-03-31 18:46 GMT+09:00 Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>:
>>
>> > You can try something like that when no explicit ecc.strength and
>> > ecc.size has been set in the DT and when ECC_MAXIMIZE was not passed.
>> >
>> > static int
>> > denali_get_closest_ecc_strength(struct denali_nand_info *denali,
>> > int strength)
>> > {
>> > /*
>> > * Whatever you need to select a strength that is greater than
>> > * or equal to strength.
>> > */
>> >
>> > return X;
>> > }
>>
>>
>> Is here anything specific to Denali?
>
> Well, only the denali driver knows what the hardware supports, though
> having a generic function that takes a table of supported strengths
> would work.
>
>>
>>
>> > static int denali_try_to_match_ecc_req(struct denali_nand_info *denali)
>> > {
>> > struct nand_chip *chip = &denali->nand;
>> > struct mtd_info *mtd = nand_to_mtd(chip);
>> > int max_ecc_bytes = mtd->oobsize - denali->bbtskipbytes;
>> > int ecc_steps, ecc_strength, ecc_bytes;
>> > int ecc_size = chip->ecc_step_ds;
>> > int ecc_strength = chip->ecc_strength_ds;
>> >
>> > /*
>> > * No information provided by the NAND chip, let the core
>> > * maximize the strength.
>> > */
>> > if (!ecc_size || !ecc_strength)
>> > return -ENOTSUPP;
>> >
>> > if (ecc_size > 512)
>> > ecc_size = 1024;
>> > else
>> > ecc_size = 512;
>> >
>> > /* Adjust ECC step size based on hardware support. */
>> > if (ecc_size == 1024 &&
>> > !(denali->caps & DENALI_CAP_ECC_SIZE_1024))
>> > ecc_size = 512;
>> > else if(ecc_size == 512 &&
>> > !(denali->caps & DENALI_CAP_ECC_SIZE_512))
>> > ecc_size = 1024;
>> >
>> > if (ecc_size < chip->ecc_size_ds) {
>> > /*
>> > * When the selected size if smaller than the expected
>> > * one we try to use the same strength but on 512 blocks
>> > * so that we can still fix the same number of errors
>> > * even if they are concentrated in the first 512bytes
>> > * of a 1024bytes portion.
>> > */
>> > ecc_strength = chip->ecc_strength_ds;
>> > ecc_strength = denali_get_closest_ecc_strength(denali,
>> > ecc_strength);
>> > } else {
>> > /* Always prefer 1024bytes ECC blocks when possible. */
>> > if (ecc_size != 1024 &&
>> > (denali->caps & DENALI_CAP_ECC_SIZE_1024) &&
>> > mtd->writesize > 1024)
>> > ecc_size = 1024;
>> >
>> > /*
>> > * Adjust the strength based on the selected ECC step
>> > * size.
>> > */
>> > ecc_strength = DIV_ROUND_UP(ecc_size,
>> > chip->ecc_step_ds) *
>> > chip->ecc_strength_ds;
>> > }
>> >
>> > ecc_bytes = denali_calc_ecc_bytes(ecc_size,
>> > ecc_strength);
>> > ecc_bytes *= mtd->writesize / ecc_size;
>> >
>> > /*
>> > * If we don't have enough space, let the core maximize
>> > * the strength.
>> > */
>> > if (ecc_bytes > max_ecc_bytes)
>> > return -ENOTSUPP;
>> >
>> > chip->ecc.strength = ecc_strength;
>> > chip->ecc.size = ecc_size;
>> >
>> > return 0;
>> > }
>>
>>
>> As a whole, this does not seem to driver-specific.
>
> It's almost controller-agnostic, except for the denali_calc_ecc_bytes()
> function, but I guess we could ask drivers to implement a hook that is
> passed the ECC step size and strength and returns the associated
> number of ECC bytes.
>
>>
>>
>> [1] A driver provides some pairs of (ecc_strength, ecc_size)
>> it can support.
>>
>> [2] The core framework knows the chip's requirement
>> (ecc_strength_ds, ecc_size_ds).
>>
>>
>> Then, the core framework provides a function
>> to return a most recommended (ecc_strength, ecc_size).
>>
>>
>>
>> struct nand_ecc_spec {
>> int ecc_strength;
>> int ecc_size;
>> };
>>
>> /*
>> * This function choose the most recommented (ecc_str, ecc_size)
>> * "recommended" means: minimum ecc stregth that meets
>> * the chip's requirment.
>> *
>> *
>> * @chip - nand_chip
>> * @controller_ecc_spec - Array of (ecc_str, ecc_size) supported by the
>> controller. (terminated by NULL as sentinel)
>> */
>> struct nand_ecc_spec * nand_try_to_match_ecc_req(struct nand_chip *chip,
>> struct nand_ecc_spec
>> *controller_ecc_spec)
>> {
>> /*
>> * Return the pointer to the most recommended
>> * struct nand_ecc_spec.
>> * If nothing suitable found, return NULL.
>> */
>> }
>>
>
> I like the idea, except I would do this slightly differently to avoid
> declaring all combinations of stepsize and strengths
>
> struct nand_ecc_stepsize_info {
> int stepsize;
> int nstrengths;
> int *strengths;
> };
>
> struct nand_ecc_engine_caps {
> int nstepsizes;
> struct nand_ecc_stepsize_info *stepsizes;
> int (*calc_ecc_bytes)(int stepsize, int strength);
> };
>
> int nand_try_to_match_ecc_req(struct nand_chip *chip,
> const struct nand_ecc_engine_caps *caps,
> struct nand_ecc_spec *spec)
> {
> /*
> * Find the most appropriate setting based on the ECC engine
> * caps and fill the spec object accordingly.
> * Returns 0 in case of success and a negative error code
> * otherwise.
> */
> }
>
> Note that nand_try_to_match_ecc_req() has to be more generic than
> denali_try_to_match_ecc_req() WRT step sizes, which will probably
> complexify the logic.
After I fiddle with this generic approach for a while,
I started to feel like giving up.
I wonder if we really want over-implementation
for covering _theoretically_ possible cases.
In practice, there are not so many ECC settings possible
on a single controller.
As for Denali IP, it would be theoretically possible to instantiate
multiple ECC engines. However, in practice, there is no sensible
reason to do so. At least, I do not know any real chip to support that.
So, I'd like to simplify the logic for Denali.
- Support either 512 or 1024 ECC size.
If there is (ever) a controller that supports both,
1024 should be chosen.
- ECC strength is not specified via DT, it is simply maximized.
This simplifies the logic much and I believe this is enough.
One more reason is, as we talked before,
we need to match ECC setting between Linux and firmware (boot-loader),
so anyway we end up with using a fixed setting specified by DT.
--
Best Regards
Masahiro Yamada
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^ permalink raw reply
* [PATCH v3 3/4] net: dsa: LAN9303: add I2C managed mode support
From: Juergen Borleis @ 2017-04-11 7:22 UTC (permalink / raw)
To: netdev
Cc: linux-kernel, f.fainelli, kernel, andrew, vivien.didelot, davem,
devicetree, robh+dt, mark.rutland
In-Reply-To: <20170411072259.15356-1-jbe@pengutronix.de>
In this mode the switch device and the internal phys will be managed via
I2C interface. The MDIO interface is still supported, but for the
(emulated) CPU port only.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
CC: devicetree@vger.kernel.org
CC: robh+dt@kernel.org
CC: mark.rutland@arm.com
---
.../devicetree/bindings/net/dsa/lan9303.txt | 62 ++++++++++++
drivers/net/dsa/Kconfig | 17 ++++
drivers/net/dsa/Makefile | 5 +
drivers/net/dsa/lan9303_i2c.c | 109 +++++++++++++++++++++
4 files changed, 193 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/lan9303.txt
create mode 100644 drivers/net/dsa/lan9303_i2c.c
diff --git a/Documentation/devicetree/bindings/net/dsa/lan9303.txt b/Documentation/devicetree/bindings/net/dsa/lan9303.txt
new file mode 100644
index 0000000000000..2edc2561467a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/lan9303.txt
@@ -0,0 +1,62 @@
+SMSC/MicroChip LAN9303 three port ethernet switch
+-------------------------------------------------
+
+Required properties:
+
+- compatible: should be "smsc,lan9303-i2c"
+
+Optional properties:
+
+- reset-gpios: GPIO to be used to reset the whole device
+- reset-duration: reset duration in milliseconds, defaults to 200 ms
+
+Subnodes:
+
+The integrated switch subnode should be specified according to the binding
+described in dsa/dsa.txt. The CPU port of this switch is always port 0.
+
+Note: always use 'reg = <0/1/2>;' for the three DSA ports, even if the device is
+configured to use 1/2/3 instead. This hardware configuration will be
+auto-detected and mapped accordingly.
+
+Example:
+
+I2C managed mode:
+
+ master: masterdevice@X {
+ status = "okay";
+
+ fixed-link { /* RMII fixed link to LAN9303 */
+ speed = <100>;
+ full-duplex;
+ };
+ };
+
+ switch: switch@a {
+ compatible = "smsc,lan9303-i2c";
+ reg = <0xa>;
+ status = "okay";
+ reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+ reset-duration = <200>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 { /* RMII fixed link to master */
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&master>;
+ };
+
+ port@1 { /* external port 1 */
+ reg = <1>;
+ label = "lan1;
+ };
+
+ port@2 { /* external port 2 */
+ reg = <2>;
+ label = "lan2";
+ };
+ };
+ };
diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index 065984670ff19..73c86a19ae094 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -34,4 +34,21 @@ config NET_DSA_QCA8K
This enables support for the Qualcomm Atheros QCA8K Ethernet
switch chips.
+menuconfig NET_DSA_SMSC_LAN9303
+ tristate "SMSC/Microchip LAN9303 3-ports 10/100 ethernet switch"
+ depends on NET_DSA
+ select NET_DSA_TAG_LAN9303
+ ---help---
+ This enables support for the SMSC/Microchip LAN9303 3 port ethernet
+ switch chips.
+
+config NET_DSA_SMSC_LAN9303_I2C
+ bool "I2C managed mode"
+ depends on NET_DSA_SMSC_LAN9303
+ depends on I2C && OF
+ select REGMAP_I2C
+ ---help---
+ Enable access functions if the SMSC/Microchip LAN9303 is configured
+ for I2C managed mode.
+
endmenu
diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
index a3c9416322172..2711417c73ef3 100644
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -1,7 +1,12 @@
+lan9303-objs-y := lan9303-core.o
+lan9303-objs-$(CONFIG_NET_DSA_SMSC_LAN9303_I2C) += lan9303_i2c.o
+
obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm-sf2.o
bcm-sf2-objs := bcm_sf2.o bcm_sf2_cfp.o
obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o
+obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303.o
+lan9303-objs := $(lan9303-objs-y)
obj-y += b53/
obj-y += mv88e6xxx/
diff --git a/drivers/net/dsa/lan9303_i2c.c b/drivers/net/dsa/lan9303_i2c.c
new file mode 100644
index 0000000000000..23d942440e4b2
--- /dev/null
+++ b/drivers/net/dsa/lan9303_i2c.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/of.h>
+
+#include "lan9303.h"
+
+struct lan9303_i2c {
+ struct i2c_client *device;
+ struct lan9303 chip;
+};
+
+static const struct regmap_config lan9303_i2c_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 1,
+ .can_multi_write = true,
+ .max_register = 0x0ff, /* address bits 0..1 are not used */
+ .reg_format_endian = REGMAP_ENDIAN_LITTLE,
+
+ .volatile_table = &lan9303_register_set,
+ .wr_table = &lan9303_register_set,
+ .rd_table = &lan9303_register_set,
+
+ .cache_type = REGCACHE_NONE,
+};
+
+static int lan9303_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct lan9303_i2c *sw_dev;
+ int ret;
+
+ sw_dev = devm_kzalloc(&client->dev, sizeof(struct lan9303_i2c),
+ GFP_KERNEL);
+ if (!sw_dev)
+ return -ENOMEM;
+
+ sw_dev->chip.regmap = devm_regmap_init_i2c(client,
+ &lan9303_i2c_regmap_config);
+ if (IS_ERR(sw_dev->chip.regmap)) {
+ ret = PTR_ERR(sw_dev->chip.regmap);
+ dev_err(&client->dev, "Failed to allocate register map: %d\n",
+ ret);
+ return ret;
+ }
+
+ /* link forward and backward */
+ sw_dev->device = client;
+ i2c_set_clientdata(client, sw_dev);
+ sw_dev->chip.dev = &client->dev;
+
+ ret = lan9303_probe(&sw_dev->chip, client->dev.of_node);
+ if (ret != 0)
+ return ret;
+
+ dev_info(&client->dev, "LAN9303 I2C driver loaded successfully\n");
+
+ return 0;
+}
+
+static int lan9303_i2c_remove(struct i2c_client *client)
+{
+ struct lan9303_i2c *sw_dev;
+
+ sw_dev = i2c_get_clientdata(client);
+ if (!sw_dev)
+ return -ENODEV;
+
+ return lan9303_remove(&sw_dev->chip);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static const struct i2c_device_id lan9303_i2c_id[] = {
+ { "lan9303", 0 },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(i2c, lan9303_i2c_id);
+
+static const struct of_device_id lan9303_i2c_of_match[] = {
+ { .compatible = "smsc,lan9303-i2c", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, lan9303_i2c_of_match);
+
+static struct i2c_driver lan9303_i2c_driver = {
+ .driver = {
+ .name = "LAN9303_I2C",
+ .of_match_table = of_match_ptr(lan9303_i2c_of_match),
+ },
+ .probe = lan9303_i2c_probe,
+ .remove = lan9303_i2c_remove,
+ .id_table = lan9303_i2c_id,
+};
+module_i2c_driver(lan9303_i2c_driver);
--
2.11.0
^ permalink raw reply related
* [PATCH v3 4/4] net: dsa: LAN9303: add MDIO managed mode support
From: Juergen Borleis @ 2017-04-11 7:22 UTC (permalink / raw)
To: netdev
Cc: linux-kernel, f.fainelli, kernel, andrew, vivien.didelot, davem,
devicetree, robh+dt, mark.rutland
In-Reply-To: <20170411072259.15356-1-jbe@pengutronix.de>
When the LAN9303 device is in MDIO manged mode, all register accesses must
be done via MDIO.
Please note: this code is compile time tested only due to the absence of such
configured hardware. It is based on a patch from Stefan Roese from 2014.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
CC: devicetree@vger.kernel.org
CC: robh+dt@kernel.org
CC: mark.rutland@arm.com
---
.../devicetree/bindings/net/dsa/lan9303.txt | 45 ++++++-
drivers/net/dsa/Kconfig | 8 ++
drivers/net/dsa/Makefile | 1 +
drivers/net/dsa/lan9303_mdio.c | 144 +++++++++++++++++++++
4 files changed, 197 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/dsa/lan9303_mdio.c
diff --git a/Documentation/devicetree/bindings/net/dsa/lan9303.txt b/Documentation/devicetree/bindings/net/dsa/lan9303.txt
index 2edc2561467a7..04f2965a44676 100644
--- a/Documentation/devicetree/bindings/net/dsa/lan9303.txt
+++ b/Documentation/devicetree/bindings/net/dsa/lan9303.txt
@@ -3,7 +3,10 @@ SMSC/MicroChip LAN9303 three port ethernet switch
Required properties:
-- compatible: should be "smsc,lan9303-i2c"
+- compatible: should be
+ - "smsc,lan9303-i2c" for I2C managed mode
+ or
+ - "smsc,lan9303-mdio" for mdio managed mode
Optional properties:
@@ -60,3 +63,43 @@ I2C managed mode:
};
};
};
+
+MDIO managed mode:
+
+ master: masterdevice@X {
+ status = "okay";
+ phy-handle = <&switch>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch: switch-phy@0 {
+ compatible = "smsc,lan9303-mdio";
+ reg = <0>;
+ reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+ reset-duration = <100>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&master>;
+ };
+
+ port@1 { /* external port 1 */
+ reg = <1>;
+ label = "lan1;
+ };
+
+ port@2 { /* external port 2 */
+ reg = <2>;
+ label = "lan2";
+ };
+ };
+ };
+ };
+ };
diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index 73c86a19ae094..a4d0ba43b0781 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -51,4 +51,12 @@ config NET_DSA_SMSC_LAN9303_I2C
Enable access functions if the SMSC/Microchip LAN9303 is configured
for I2C managed mode.
+config NET_DSA_SMSC_LAN9303_MDIO
+ bool "MDIO managed mode"
+ depends on NET_DSA_SMSC_LAN9303
+ depends on OF_MDIO
+ ---help---
+ Enable access functions if the SMSC/Microchip LAN9303 is configured
+ for MDIO managed mode.
+
endmenu
diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
index 2711417c73ef3..6ccb8899f3082 100644
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -1,5 +1,6 @@
lan9303-objs-y := lan9303-core.o
lan9303-objs-$(CONFIG_NET_DSA_SMSC_LAN9303_I2C) += lan9303_i2c.o
+lan9303-objs-$(CONFIG_NET_DSA_SMSC_LAN9303_MDIO) += lan9303_mdio.o
obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm-sf2.o
diff --git a/drivers/net/dsa/lan9303_mdio.c b/drivers/net/dsa/lan9303_mdio.c
new file mode 100644
index 0000000000000..87c5cfa946a92
--- /dev/null
+++ b/drivers/net/dsa/lan9303_mdio.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de>
+ *
+ * Partially based on a patch from
+ * Copyright (c) 2014 Stefan Roese <sr@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mdio.h>
+#include <linux/phy.h>
+#include <linux/of.h>
+
+#include "lan9303.h"
+
+/* Generate phy-addr and -reg from the input address */
+#define PHY_ADDR(x) ((((x) >> 6) + 0x10) & 0x1f)
+#define PHY_REG(x) (((x) >> 1) & 0x1f)
+
+struct lan9303_mdio {
+ struct mdio_device *device;
+ struct lan9303 chip;
+};
+
+static void lan9303_mdio_real_write(struct mdio_device *mdio, int reg, u16 val)
+{
+ mdio->bus->write(mdio->bus, PHY_ADDR(reg), PHY_REG(reg), val);
+}
+
+static int lan9303_mdio_write(void *ctx, uint32_t reg, uint32_t val)
+{
+ struct lan9303_mdio *sw_dev = (struct lan9303_mdio *)ctx;
+
+ mutex_lock(&sw_dev->device->bus->mdio_lock);
+ lan9303_mdio_real_write(sw_dev->device, reg, val & 0xffff);
+ lan9303_mdio_real_write(sw_dev->device, reg + 2, (val >> 16) & 0xffff);
+ mutex_unlock(&sw_dev->device->bus->mdio_lock);
+
+ return 0;
+}
+
+static u16 lan9303_mdio_real_read(struct mdio_device *mdio, int reg)
+{
+ return mdio->bus->read(mdio->bus, PHY_ADDR(reg), PHY_REG(reg));
+}
+
+static int lan9303_mdio_read(void *ctx, uint32_t reg, uint32_t *val)
+{
+ struct lan9303_mdio *sw_dev = (struct lan9303_mdio *)ctx;
+
+ mutex_lock(&sw_dev->device->bus->mdio_lock);
+ *val = lan9303_mdio_real_read(sw_dev->device, reg);
+ *val |= (lan9303_mdio_real_read(sw_dev->device, reg + 2) << 16);
+ mutex_unlock(&sw_dev->device->bus->mdio_lock);
+
+ return 0;
+}
+
+static const struct regmap_config lan9303_mdio_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 1,
+ .can_multi_write = true,
+ .max_register = 0x0ff, /* address bits 0..1 are not used */
+ .reg_format_endian = REGMAP_ENDIAN_LITTLE,
+
+ .volatile_table = &lan9303_register_set,
+ .wr_table = &lan9303_register_set,
+ .rd_table = &lan9303_register_set,
+
+ .reg_read = lan9303_mdio_read,
+ .reg_write = lan9303_mdio_write,
+
+ .cache_type = REGCACHE_NONE,
+};
+
+static int lan9303_mdio_probe(struct mdio_device *mdiodev)
+{
+ struct lan9303_mdio *sw_dev;
+ int ret;
+
+ sw_dev = devm_kzalloc(&mdiodev->dev, sizeof(struct lan9303_mdio),
+ GFP_KERNEL);
+ if (!sw_dev)
+ return -ENOMEM;
+
+ sw_dev->chip.regmap = devm_regmap_init(&mdiodev->dev, NULL, sw_dev,
+ &lan9303_mdio_regmap_config);
+ if (IS_ERR(sw_dev->chip.regmap)) {
+ ret = PTR_ERR(sw_dev->chip.regmap);
+ dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret);
+ return ret;
+ }
+
+ /* link forward and backward */
+ sw_dev->device = mdiodev;
+ dev_set_drvdata(&mdiodev->dev, sw_dev);
+ sw_dev->chip.dev = &mdiodev->dev;
+
+ ret = lan9303_probe(&sw_dev->chip, mdiodev->dev.of_node);
+ if (ret != 0)
+ return ret;
+
+ dev_info(&mdiodev->dev, "LAN9303 MDIO driver loaded successfully\n");
+
+ return 0;
+}
+
+static void lan9303_mdio_remove(struct mdio_device *mdiodev)
+{
+ struct lan9303_mdio *sw_dev = dev_get_drvdata(&mdiodev->dev);
+
+ if (!sw_dev)
+ return;
+
+ lan9303_remove(&sw_dev->chip);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static const struct of_device_id lan9303_mdio_of_match[] = {
+ { .compatible = "smsc,lan9303-mdio" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, lan9303_mdio_of_match);
+
+static struct mdio_driver lan9303_mdio_driver = {
+ .mdiodrv.driver = {
+ .name = "LAN9303_MDIO",
+ .of_match_table = of_match_ptr(lan9303_mdio_of_match),
+ },
+ .probe = lan9303_mdio_probe,
+ .remove = lan9303_mdio_remove,
+};
+mdio_module_driver(lan9303_mdio_driver);
--
2.11.0
^ permalink raw reply related
* Re: [RESEND PATCH v4] iio: adc: add support for X-Powers AXP20X and AXP22X PMICs ADCs
From: Quentin Schulz @ 2017-04-11 7:29 UTC (permalink / raw)
To: lee.jones-QSEj5FYQhm4dnm+yROfE0A
Cc: sre-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
icenowy-ymACFijhrKM,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA, linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
liam-RYWXG+zxWwBdeoIcmNTgJF6hYfS7NtTn,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170410145445.ngfjau2dtjvquspg@dell>
Hi Lee,
On 10/04/2017 16:54, Lee Jones wrote:
> On Mon, 10 Apr 2017, Quentin Schulz wrote:
>
>> Hi Lee,
>>
>> Just to make sure you didn't miss that patch (can't find it in
>> for-mfd-next and for-mfd-next-next).
>
> It has not been missed, but is yet to be reviewed.
>
Hum.. What do you mean exactly? The maintainer of the AXP PMICs has
given its Acked-by and the maintainer of the IIO subsystem has given its
Reviewed-by. Is there something I'm missing (in your workflow maybe)?
Thanks,
Quentin
>> On 04/04/2017 08:34, Quentin Schulz wrote:
>>> The X-Powers AXP20X and AXP22X PMICs have multiple ADCs. They expose the
>>> battery voltage, battery charge and discharge currents, AC-in and VBUS
>>> voltages and currents, 2 GPIOs muxable in ADC mode and PMIC temperature.
>>>
>>> This adds support for most of AXP20X and AXP22X ADCs.
>>>
>>> Signed-off-by: Quentin Schulz <quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>> Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>> Acked-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
>>> Reviewed-by: Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>>> ---
>>>
>>> Lee, could you merge this through the mfd tree please?
>>> => https://lkml.org/lkml/2017/3/22/47
>>>
>>> v4:
>>> - added missing space at the beginning of a comment,
>>> - tidied axp20x_adc_offset_voltage and axp20x_write_raw to use switch case
>>> instead of if conditions,
>>> - added MODULE_DEVICE_TABLE for axp20x_adc_id_match for module autoloading,
>>> - merged two lines in axp20x_remove,
>>>
>>> v3:
>>> - moved from switch to if condition in axp20x_adc_raw and
>>> axp22x_adc_raw,
>>> - removed DT support as DT node has been dropped,
>>> - use of platform_device_id
>>> - correctly defined the name of the iio device (name used to probe the
>>> driver),
>>> - added goto for errors in probe,
>>> - added iio_map_array_unregister to the remove function,
>>>
>>> v2:
>>> - removed unused defines,
>>> - changed BIT(x) to 1 << x when describing bits purpose for which 2 <<
>>> x or 3 << x exists, to be consistent,
>>> - changed ADC rate defines to macro formulas,
>>> - reordered IIO channels, now different measures (current/voltage) of
>>> the same part of the PMIC (e.g. battery), have the same IIO channel in
>>> their respective IIO type. When a part of the PMIC have only one
>>> measure, a number is jumped,
>>> - left IIO channel mapping in DT to use iio_map structure,
>>> - removed indexing of ADC internal temperature,
>>> - removed unused iio_dev structure in axp20x_adc_iio,
>>> - added a structure for data specific to AXP20X or AXP22X PMICs instead
>>> of using an ID and an if condition when needing to separate the
>>> behaviour of both,
>>> - added a comment on batt_chrg_i really being on 12bits rather than
>>> what the Chinese datasheets say (13 bits),
>>> - corrected the offset for AXP22X PMIC temperature,
>>> - set the ADC rate to a value (100Hz) shared by the AXP20X and AXP22X,
>>> - created macro formulas to compute the ADC rate for each,
>>> - added a condition on presence of ADC_EN2 reg before setting/resetting
>>> it,
>>> - switched from devm_iio_device_unregister to the non-devm function
>>> because of the need for a remove function,
>>> - removed some dead code,
>>>
>>> drivers/iio/adc/Kconfig | 10 +
>>> drivers/iio/adc/Makefile | 1 +
>>> drivers/iio/adc/axp20x_adc.c | 617 +++++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 628 insertions(+)
>>> create mode 100644 drivers/iio/adc/axp20x_adc.c
>>>
>>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>>> index d777a97..d15e1bd 100644
>>> --- a/drivers/iio/adc/Kconfig
>>> +++ b/drivers/iio/adc/Kconfig
>>> @@ -154,6 +154,16 @@ config AT91_SAMA5D2_ADC
>>> To compile this driver as a module, choose M here: the module will be
>>> called at91-sama5d2_adc.
>>>
>>> +config AXP20X_ADC
>>> + tristate "X-Powers AXP20X and AXP22X ADC driver"
>>> + depends on MFD_AXP20X
>>> + help
>>> + Say yes here to have support for X-Powers power management IC (PMIC)
>>> + AXP20X and AXP22X ADC devices.
>>> +
>>> + To compile this driver as a module, choose M here: the module will be
>>> + called axp20x_adc.
>>> +
>>> config AXP288_ADC
>>> tristate "X-Powers AXP288 ADC driver"
>>> depends on MFD_AXP20X
>>> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
>>> index b11bb57..17899b5 100644
>>> --- a/drivers/iio/adc/Makefile
>>> +++ b/drivers/iio/adc/Makefile
>>> @@ -16,6 +16,7 @@ obj-$(CONFIG_AD7887) += ad7887.o
>>> obj-$(CONFIG_AD799X) += ad799x.o
>>> obj-$(CONFIG_AT91_ADC) += at91_adc.o
>>> obj-$(CONFIG_AT91_SAMA5D2_ADC) += at91-sama5d2_adc.o
>>> +obj-$(CONFIG_AXP20X_ADC) += axp20x_adc.o
>>> obj-$(CONFIG_AXP288_ADC) += axp288_adc.o
>>> obj-$(CONFIG_BCM_IPROC_ADC) += bcm_iproc_adc.o
>>> obj-$(CONFIG_BERLIN2_ADC) += berlin2-adc.o
>>> diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c
>>> new file mode 100644
>>> index 0000000..11e1771
>>> --- /dev/null
>>> +++ b/drivers/iio/adc/axp20x_adc.c
>>> @@ -0,0 +1,617 @@
>>> +/* ADC driver for AXP20X and AXP22X PMICs
>>> + *
>>> + * Copyright (c) 2016 Free Electrons NextThing Co.
>>> + * Quentin Schulz <quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify it under
>>> + * the terms of the GNU General Public License version 2 as published by the
>>> + * Free Software Foundation.
>>> + */
>>> +
>>> +#include <linux/completion.h>
>>> +#include <linux/interrupt.h>
>>> +#include <linux/io.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/pm_runtime.h>
>>> +#include <linux/regmap.h>
>>> +#include <linux/thermal.h>
>>> +
>>> +#include <linux/iio/iio.h>
>>> +#include <linux/iio/driver.h>
>>> +#include <linux/iio/machine.h>
>>> +#include <linux/mfd/axp20x.h>
>>> +
>>> +#define AXP20X_ADC_EN1_MASK GENMASK(7, 0)
>>> +
>>> +#define AXP20X_ADC_EN2_MASK (GENMASK(3, 2) | BIT(7))
>>> +#define AXP22X_ADC_EN1_MASK (GENMASK(7, 5) | BIT(0))
>>> +
>>> +#define AXP20X_GPIO10_IN_RANGE_GPIO0 BIT(0)
>>> +#define AXP20X_GPIO10_IN_RANGE_GPIO1 BIT(1)
>>> +#define AXP20X_GPIO10_IN_RANGE_GPIO0_VAL(x) ((x) & BIT(0))
>>> +#define AXP20X_GPIO10_IN_RANGE_GPIO1_VAL(x) (((x) & BIT(0)) << 1)
>>> +
>>> +#define AXP20X_ADC_RATE_MASK GENMASK(7, 6)
>>> +#define AXP20X_ADC_RATE_HZ(x) ((ilog2((x) / 25) << 6) & AXP20X_ADC_RATE_MASK)
>>> +#define AXP22X_ADC_RATE_HZ(x) ((ilog2((x) / 100) << 6) & AXP20X_ADC_RATE_MASK)
>>> +
>>> +#define AXP20X_ADC_CHANNEL(_channel, _name, _type, _reg) \
>>> + { \
>>> + .type = _type, \
>>> + .indexed = 1, \
>>> + .channel = _channel, \
>>> + .address = _reg, \
>>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
>>> + BIT(IIO_CHAN_INFO_SCALE), \
>>> + .datasheet_name = _name, \
>>> + }
>>> +
>>> +#define AXP20X_ADC_CHANNEL_OFFSET(_channel, _name, _type, _reg) \
>>> + { \
>>> + .type = _type, \
>>> + .indexed = 1, \
>>> + .channel = _channel, \
>>> + .address = _reg, \
>>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
>>> + BIT(IIO_CHAN_INFO_SCALE) |\
>>> + BIT(IIO_CHAN_INFO_OFFSET),\
>>> + .datasheet_name = _name, \
>>> + }
>>> +
>>> +struct axp_data;
>>> +
>>> +struct axp20x_adc_iio {
>>> + struct regmap *regmap;
>>> + struct axp_data *data;
>>> +};
>>> +
>>> +enum axp20x_adc_channel_v {
>>> + AXP20X_ACIN_V = 0,
>>> + AXP20X_VBUS_V,
>>> + AXP20X_TS_IN,
>>> + AXP20X_GPIO0_V,
>>> + AXP20X_GPIO1_V,
>>> + AXP20X_IPSOUT_V,
>>> + AXP20X_BATT_V,
>>> +};
>>> +
>>> +enum axp20x_adc_channel_i {
>>> + AXP20X_ACIN_I = 0,
>>> + AXP20X_VBUS_I,
>>> + AXP20X_BATT_CHRG_I,
>>> + AXP20X_BATT_DISCHRG_I,
>>> +};
>>> +
>>> +enum axp22x_adc_channel_v {
>>> + AXP22X_TS_IN = 0,
>>> + AXP22X_BATT_V,
>>> +};
>>> +
>>> +enum axp22x_adc_channel_i {
>>> + AXP22X_BATT_CHRG_I = 1,
>>> + AXP22X_BATT_DISCHRG_I,
>>> +};
>>> +
>>> +static struct iio_map axp20x_maps[] = {
>>> + {
>>> + .consumer_dev_name = "axp20x-usb-power-supply",
>>> + .consumer_channel = "vbus_v",
>>> + .adc_channel_label = "vbus_v",
>>> + }, {
>>> + .consumer_dev_name = "axp20x-usb-power-supply",
>>> + .consumer_channel = "vbus_i",
>>> + .adc_channel_label = "vbus_i",
>>> + }, {
>>> + .consumer_dev_name = "axp20x-ac-power-supply",
>>> + .consumer_channel = "acin_v",
>>> + .adc_channel_label = "acin_v",
>>> + }, {
>>> + .consumer_dev_name = "axp20x-ac-power-supply",
>>> + .consumer_channel = "acin_i",
>>> + .adc_channel_label = "acin_i",
>>> + }, {
>>> + .consumer_dev_name = "axp20x-battery-power-supply",
>>> + .consumer_channel = "batt_v",
>>> + .adc_channel_label = "batt_v",
>>> + }, {
>>> + .consumer_dev_name = "axp20x-battery-power-supply",
>>> + .consumer_channel = "batt_chrg_i",
>>> + .adc_channel_label = "batt_chrg_i",
>>> + }, {
>>> + .consumer_dev_name = "axp20x-battery-power-supply",
>>> + .consumer_channel = "batt_dischrg_i",
>>> + .adc_channel_label = "batt_dischrg_i",
>>> + }, { /* sentinel */ }
>>> +};
>>> +
>>> +static struct iio_map axp22x_maps[] = {
>>> + {
>>> + .consumer_dev_name = "axp20x-battery-power-supply",
>>> + .consumer_channel = "batt_v",
>>> + .adc_channel_label = "batt_v",
>>> + }, {
>>> + .consumer_dev_name = "axp20x-battery-power-supply",
>>> + .consumer_channel = "batt_chrg_i",
>>> + .adc_channel_label = "batt_chrg_i",
>>> + }, {
>>> + .consumer_dev_name = "axp20x-battery-power-supply",
>>> + .consumer_channel = "batt_dischrg_i",
>>> + .adc_channel_label = "batt_dischrg_i",
>>> + }, { /* sentinel */ }
>>> +};
>>> +
>>> +/*
>>> + * Channels are mapped by physical system. Their channels share the same index.
>>> + * i.e. acin_i is in_current0_raw and acin_v is in_voltage0_raw.
>>> + * The only exception is for the battery. batt_v will be in_voltage6_raw and
>>> + * charge current in_current6_raw and discharge current will be in_current7_raw.
>>> + */
>>> +static const struct iio_chan_spec axp20x_adc_channels[] = {
>>> + AXP20X_ADC_CHANNEL(AXP20X_ACIN_V, "acin_v", IIO_VOLTAGE,
>>> + AXP20X_ACIN_V_ADC_H),
>>> + AXP20X_ADC_CHANNEL(AXP20X_ACIN_I, "acin_i", IIO_CURRENT,
>>> + AXP20X_ACIN_I_ADC_H),
>>> + AXP20X_ADC_CHANNEL(AXP20X_VBUS_V, "vbus_v", IIO_VOLTAGE,
>>> + AXP20X_VBUS_V_ADC_H),
>>> + AXP20X_ADC_CHANNEL(AXP20X_VBUS_I, "vbus_i", IIO_CURRENT,
>>> + AXP20X_VBUS_I_ADC_H),
>>> + {
>>> + .type = IIO_TEMP,
>>> + .address = AXP20X_TEMP_ADC_H,
>>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
>>> + BIT(IIO_CHAN_INFO_SCALE) |
>>> + BIT(IIO_CHAN_INFO_OFFSET),
>>> + .datasheet_name = "pmic_temp",
>>> + },
>>> + AXP20X_ADC_CHANNEL_OFFSET(AXP20X_GPIO0_V, "gpio0_v", IIO_VOLTAGE,
>>> + AXP20X_GPIO0_V_ADC_H),
>>> + AXP20X_ADC_CHANNEL_OFFSET(AXP20X_GPIO1_V, "gpio1_v", IIO_VOLTAGE,
>>> + AXP20X_GPIO1_V_ADC_H),
>>> + AXP20X_ADC_CHANNEL(AXP20X_IPSOUT_V, "ipsout_v", IIO_VOLTAGE,
>>> + AXP20X_IPSOUT_V_HIGH_H),
>>> + AXP20X_ADC_CHANNEL(AXP20X_BATT_V, "batt_v", IIO_VOLTAGE,
>>> + AXP20X_BATT_V_H),
>>> + AXP20X_ADC_CHANNEL(AXP20X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
>>> + AXP20X_BATT_CHRG_I_H),
>>> + AXP20X_ADC_CHANNEL(AXP20X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
>>> + AXP20X_BATT_DISCHRG_I_H),
>>> +};
>>> +
>>> +static const struct iio_chan_spec axp22x_adc_channels[] = {
>>> + {
>>> + .type = IIO_TEMP,
>>> + .address = AXP22X_PMIC_TEMP_H,
>>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
>>> + BIT(IIO_CHAN_INFO_SCALE) |
>>> + BIT(IIO_CHAN_INFO_OFFSET),
>>> + .datasheet_name = "pmic_temp",
>>> + },
>>> + AXP20X_ADC_CHANNEL(AXP22X_BATT_V, "batt_v", IIO_VOLTAGE,
>>> + AXP20X_BATT_V_H),
>>> + AXP20X_ADC_CHANNEL(AXP22X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
>>> + AXP20X_BATT_CHRG_I_H),
>>> + AXP20X_ADC_CHANNEL(AXP22X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
>>> + AXP20X_BATT_DISCHRG_I_H),
>>> +};
>>> +
>>> +static int axp20x_adc_raw(struct iio_dev *indio_dev,
>>> + struct iio_chan_spec const *chan, int *val)
>>> +{
>>> + struct axp20x_adc_iio *info = iio_priv(indio_dev);
>>> + int size = 12;
>>> +
>>> + /*
>>> + * N.B.: Unlike the Chinese datasheets tell, the charging current is
>>> + * stored on 12 bits, not 13 bits. Only discharging current is on 13
>>> + * bits.
>>> + */
>>> + if (chan->type == IIO_CURRENT && chan->channel == AXP20X_BATT_DISCHRG_I)
>>> + size = 13;
>>> + else
>>> + size = 12;
>>> +
>>> + *val = axp20x_read_variable_width(info->regmap, chan->address, size);
>>> + if (*val < 0)
>>> + return *val;
>>> +
>>> + return IIO_VAL_INT;
>>> +}
>>> +
>>> +static int axp22x_adc_raw(struct iio_dev *indio_dev,
>>> + struct iio_chan_spec const *chan, int *val)
>>> +{
>>> + struct axp20x_adc_iio *info = iio_priv(indio_dev);
>>> + int size;
>>> +
>>> + /*
>>> + * N.B.: Unlike the Chinese datasheets tell, the charging current is
>>> + * stored on 12 bits, not 13 bits. Only discharging current is on 13
>>> + * bits.
>>> + */
>>> + if (chan->type == IIO_CURRENT && chan->channel == AXP22X_BATT_DISCHRG_I)
>>> + size = 13;
>>> + else
>>> + size = 12;
>>> +
>>> + *val = axp20x_read_variable_width(info->regmap, chan->address, size);
>>> + if (*val < 0)
>>> + return *val;
>>> +
>>> + return IIO_VAL_INT;
>>> +}
>>> +
>>> +static int axp20x_adc_scale_voltage(int channel, int *val, int *val2)
>>> +{
>>> + switch (channel) {
>>> + case AXP20X_ACIN_V:
>>> + case AXP20X_VBUS_V:
>>> + *val = 1;
>>> + *val2 = 700000;
>>> + return IIO_VAL_INT_PLUS_MICRO;
>>> +
>>> + case AXP20X_GPIO0_V:
>>> + case AXP20X_GPIO1_V:
>>> + *val = 0;
>>> + *val2 = 500000;
>>> + return IIO_VAL_INT_PLUS_MICRO;
>>> +
>>> + case AXP20X_BATT_V:
>>> + *val = 1;
>>> + *val2 = 100000;
>>> + return IIO_VAL_INT_PLUS_MICRO;
>>> +
>>> + case AXP20X_IPSOUT_V:
>>> + *val = 1;
>>> + *val2 = 400000;
>>> + return IIO_VAL_INT_PLUS_MICRO;
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +}
>>> +
>>> +static int axp20x_adc_scale_current(int channel, int *val, int *val2)
>>> +{
>>> + switch (channel) {
>>> + case AXP20X_ACIN_I:
>>> + *val = 0;
>>> + *val2 = 625000;
>>> + return IIO_VAL_INT_PLUS_MICRO;
>>> +
>>> + case AXP20X_VBUS_I:
>>> + *val = 0;
>>> + *val2 = 375000;
>>> + return IIO_VAL_INT_PLUS_MICRO;
>>> +
>>> + case AXP20X_BATT_DISCHRG_I:
>>> + case AXP20X_BATT_CHRG_I:
>>> + *val = 0;
>>> + *val2 = 500000;
>>> + return IIO_VAL_INT_PLUS_MICRO;
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +}
>>> +
>>> +static int axp20x_adc_scale(struct iio_chan_spec const *chan, int *val,
>>> + int *val2)
>>> +{
>>> + switch (chan->type) {
>>> + case IIO_VOLTAGE:
>>> + return axp20x_adc_scale_voltage(chan->channel, val, val2);
>>> +
>>> + case IIO_CURRENT:
>>> + return axp20x_adc_scale_current(chan->channel, val, val2);
>>> +
>>> + case IIO_TEMP:
>>> + *val = 100;
>>> + return IIO_VAL_INT;
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +}
>>> +
>>> +static int axp22x_adc_scale(struct iio_chan_spec const *chan, int *val,
>>> + int *val2)
>>> +{
>>> + switch (chan->type) {
>>> + case IIO_VOLTAGE:
>>> + if (chan->channel != AXP22X_BATT_V)
>>> + return -EINVAL;
>>> +
>>> + *val = 1;
>>> + *val2 = 100000;
>>> + return IIO_VAL_INT_PLUS_MICRO;
>>> +
>>> + case IIO_CURRENT:
>>> + *val = 0;
>>> + *val2 = 500000;
>>> + return IIO_VAL_INT_PLUS_MICRO;
>>> +
>>> + case IIO_TEMP:
>>> + *val = 100;
>>> + return IIO_VAL_INT;
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +}
>>> +
>>> +static int axp20x_adc_offset_voltage(struct iio_dev *indio_dev, int channel,
>>> + int *val)
>>> +{
>>> + struct axp20x_adc_iio *info = iio_priv(indio_dev);
>>> + int ret;
>>> +
>>> + ret = regmap_read(info->regmap, AXP20X_GPIO10_IN_RANGE, val);
>>> + if (ret < 0)
>>> + return ret;
>>> +
>>> + switch (channel) {
>>> + case AXP20X_GPIO0_V:
>>> + *val &= AXP20X_GPIO10_IN_RANGE_GPIO0;
>>> + break;
>>> +
>>> + case AXP20X_GPIO1_V:
>>> + *val &= AXP20X_GPIO10_IN_RANGE_GPIO1;
>>> + break;
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +
>>> + *val = !!(*val) * 700000;
>>> +
>>> + return IIO_VAL_INT;
>>> +}
>>> +
>>> +static int axp20x_adc_offset(struct iio_dev *indio_dev,
>>> + struct iio_chan_spec const *chan, int *val)
>>> +{
>>> + switch (chan->type) {
>>> + case IIO_VOLTAGE:
>>> + return axp20x_adc_offset_voltage(indio_dev, chan->channel, val);
>>> +
>>> + case IIO_TEMP:
>>> + *val = -1447;
>>> + return IIO_VAL_INT;
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +}
>>> +
>>> +static int axp20x_read_raw(struct iio_dev *indio_dev,
>>> + struct iio_chan_spec const *chan, int *val,
>>> + int *val2, long mask)
>>> +{
>>> + switch (mask) {
>>> + case IIO_CHAN_INFO_OFFSET:
>>> + return axp20x_adc_offset(indio_dev, chan, val);
>>> +
>>> + case IIO_CHAN_INFO_SCALE:
>>> + return axp20x_adc_scale(chan, val, val2);
>>> +
>>> + case IIO_CHAN_INFO_RAW:
>>> + return axp20x_adc_raw(indio_dev, chan, val);
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +}
>>> +
>>> +static int axp22x_read_raw(struct iio_dev *indio_dev,
>>> + struct iio_chan_spec const *chan, int *val,
>>> + int *val2, long mask)
>>> +{
>>> + switch (mask) {
>>> + case IIO_CHAN_INFO_OFFSET:
>>> + *val = -2677;
>>> + return IIO_VAL_INT;
>>> +
>>> + case IIO_CHAN_INFO_SCALE:
>>> + return axp22x_adc_scale(chan, val, val2);
>>> +
>>> + case IIO_CHAN_INFO_RAW:
>>> + return axp22x_adc_raw(indio_dev, chan, val);
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +}
>>> +
>>> +static int axp20x_write_raw(struct iio_dev *indio_dev,
>>> + struct iio_chan_spec const *chan, int val, int val2,
>>> + long mask)
>>> +{
>>> + struct axp20x_adc_iio *info = iio_priv(indio_dev);
>>> + unsigned int reg, regval;
>>> +
>>> + /*
>>> + * The AXP20X PMIC allows the user to choose between 0V and 0.7V offsets
>>> + * for (independently) GPIO0 and GPIO1 when in ADC mode.
>>> + */
>>> + if (mask != IIO_CHAN_INFO_OFFSET)
>>> + return -EINVAL;
>>> +
>>> + if (val != 0 && val != 700000)
>>> + return -EINVAL;
>>> +
>>> + switch (chan->channel) {
>>> + case AXP20X_GPIO0_V:
>>> + reg = AXP20X_GPIO10_IN_RANGE_GPIO0;
>>> + regval = AXP20X_GPIO10_IN_RANGE_GPIO0_VAL(!!val);
>>> + break;
>>> +
>>> + case AXP20X_GPIO1_V:
>>> + reg = AXP20X_GPIO10_IN_RANGE_GPIO1;
>>> + regval = AXP20X_GPIO10_IN_RANGE_GPIO1_VAL(!!val);
>>> + break;
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +
>>> + return regmap_update_bits(info->regmap, AXP20X_GPIO10_IN_RANGE, reg,
>>> + regval);
>>> +}
>>> +
>>> +static const struct iio_info axp20x_adc_iio_info = {
>>> + .read_raw = axp20x_read_raw,
>>> + .write_raw = axp20x_write_raw,
>>> + .driver_module = THIS_MODULE,
>>> +};
>>> +
>>> +static const struct iio_info axp22x_adc_iio_info = {
>>> + .read_raw = axp22x_read_raw,
>>> + .driver_module = THIS_MODULE,
>>> +};
>>> +
>>> +static int axp20x_adc_rate(int rate)
>>> +{
>>> + return AXP20X_ADC_RATE_HZ(rate);
>>> +}
>>> +
>>> +static int axp22x_adc_rate(int rate)
>>> +{
>>> + return AXP22X_ADC_RATE_HZ(rate);
>>> +}
>>> +
>>> +struct axp_data {
>>> + const struct iio_info *iio_info;
>>> + int num_channels;
>>> + struct iio_chan_spec const *channels;
>>> + unsigned long adc_en1_mask;
>>> + int (*adc_rate)(int rate);
>>> + bool adc_en2;
>>> + struct iio_map *maps;
>>> +};
>>> +
>>> +static const struct axp_data axp20x_data = {
>>> + .iio_info = &axp20x_adc_iio_info,
>>> + .num_channels = ARRAY_SIZE(axp20x_adc_channels),
>>> + .channels = axp20x_adc_channels,
>>> + .adc_en1_mask = AXP20X_ADC_EN1_MASK,
>>> + .adc_rate = axp20x_adc_rate,
>>> + .adc_en2 = true,
>>> + .maps = axp20x_maps,
>>> +};
>>> +
>>> +static const struct axp_data axp22x_data = {
>>> + .iio_info = &axp22x_adc_iio_info,
>>> + .num_channels = ARRAY_SIZE(axp22x_adc_channels),
>>> + .channels = axp22x_adc_channels,
>>> + .adc_en1_mask = AXP22X_ADC_EN1_MASK,
>>> + .adc_rate = axp22x_adc_rate,
>>> + .adc_en2 = false,
>>> + .maps = axp22x_maps,
>>> +};
>>> +
>>> +static const struct platform_device_id axp20x_adc_id_match[] = {
>>> + { .name = "axp20x-adc", .driver_data = (kernel_ulong_t)&axp20x_data, },
>>> + { .name = "axp22x-adc", .driver_data = (kernel_ulong_t)&axp22x_data, },
>>> + { /* sentinel */ },
>>> +};
>>> +MODULE_DEVICE_TABLE(platform, axp20x_adc_id_match);
>>> +
>>> +static int axp20x_probe(struct platform_device *pdev)
>>> +{
>>> + struct axp20x_adc_iio *info;
>>> + struct iio_dev *indio_dev;
>>> + struct axp20x_dev *axp20x_dev;
>>> + int ret;
>>> +
>>> + axp20x_dev = dev_get_drvdata(pdev->dev.parent);
>>> +
>>> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
>>> + if (!indio_dev)
>>> + return -ENOMEM;
>>> +
>>> + info = iio_priv(indio_dev);
>>> + platform_set_drvdata(pdev, indio_dev);
>>> +
>>> + info->regmap = axp20x_dev->regmap;
>>> + indio_dev->dev.parent = &pdev->dev;
>>> + indio_dev->dev.of_node = pdev->dev.of_node;
>>> + indio_dev->modes = INDIO_DIRECT_MODE;
>>> +
>>> + info->data = (struct axp_data *)platform_get_device_id(pdev)->driver_data;
>>> +
>>> + indio_dev->name = platform_get_device_id(pdev)->name;
>>> + indio_dev->info = info->data->iio_info;
>>> + indio_dev->num_channels = info->data->num_channels;
>>> + indio_dev->channels = info->data->channels;
>>> +
>>> + /* Enable the ADCs on IP */
>>> + regmap_write(info->regmap, AXP20X_ADC_EN1, info->data->adc_en1_mask);
>>> +
>>> + if (info->data->adc_en2)
>>> + /* Enable GPIO0/1 and internal temperature ADCs */
>>> + regmap_update_bits(info->regmap, AXP20X_ADC_EN2,
>>> + AXP20X_ADC_EN2_MASK, AXP20X_ADC_EN2_MASK);
>>> +
>>> + /* Configure ADCs rate */
>>> + regmap_update_bits(info->regmap, AXP20X_ADC_RATE, AXP20X_ADC_RATE_MASK,
>>> + info->data->adc_rate(100));
>>> +
>>> + ret = iio_map_array_register(indio_dev, info->data->maps);
>>> + if (ret < 0) {
>>> + dev_err(&pdev->dev, "failed to register IIO maps: %d\n", ret);
>>> + goto fail_map;
>>> + }
>>> +
>>> + ret = iio_device_register(indio_dev);
>>> + if (ret < 0) {
>>> + dev_err(&pdev->dev, "could not register the device\n");
>>> + goto fail_register;
>>> + }
>>> +
>>> + return 0;
>>> +
>>> +fail_register:
>>> + iio_map_array_unregister(indio_dev);
>>> +
>>> +fail_map:
>>> + regmap_write(info->regmap, AXP20X_ADC_EN1, 0);
>>> +
>>> + if (info->data->adc_en2)
>>> + regmap_write(info->regmap, AXP20X_ADC_EN2, 0);
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +static int axp20x_remove(struct platform_device *pdev)
>>> +{
>>> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
>>> + struct axp20x_adc_iio *info = iio_priv(indio_dev);
>>> +
>>> + iio_device_unregister(indio_dev);
>>> + iio_map_array_unregister(indio_dev);
>>> +
>>> + regmap_write(info->regmap, AXP20X_ADC_EN1, 0);
>>> +
>>> + if (info->data->adc_en2)
>>> + regmap_write(info->regmap, AXP20X_ADC_EN2, 0);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static struct platform_driver axp20x_adc_driver = {
>>> + .driver = {
>>> + .name = "axp20x-adc",
>>> + },
>>> + .id_table = axp20x_adc_id_match,
>>> + .probe = axp20x_probe,
>>> + .remove = axp20x_remove,
>>> +};
>>> +
>>> +module_platform_driver(axp20x_adc_driver);
>>> +
>>> +MODULE_DESCRIPTION("ADC driver for AXP20X and AXP22X PMICs");
>>> +MODULE_AUTHOR("Quentin Schulz <quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>");
>>> +MODULE_LICENSE("GPL");
>>>
>>
>
--
Quentin Schulz, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v2] mmc: core: add mmc-card hardware reset enable support
From: Richard Leitner @ 2017-04-11 7:31 UTC (permalink / raw)
To: ulf.hansson, robh+dt, mark.rutland
Cc: shawn.lin, adrian.hunter, jh80.chung, linus.walleij, linux-mmc,
linux-kernel, devicetree, dev, Richard Leitner
Some eMMCs disable their hardware reset line (RST_N) by default. To enable
it the host must set the corresponding bit in ECSD. An example for such
a device is the Micron MTFCxGACAANA-4M.
This patch adds a new mmc-card devicetree property to let the host enable
this feature during card initialization.
Signed-off-by: Richard Leitner <richard.leitner@skidata.com>
---
CHANGES v2:
- add RST_N_FUNCTION value to dt documentation
- set RST_N_FUNCTION only if it was not set before
---
Documentation/devicetree/bindings/mmc/mmc-card.txt | 4 ++++
drivers/mmc/core/mmc.c | 23 ++++++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmc-card.txt b/Documentation/devicetree/bindings/mmc/mmc-card.txt
index a70fcd6..bbfccce 100644
--- a/Documentation/devicetree/bindings/mmc/mmc-card.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc-card.txt
@@ -12,6 +12,10 @@ Required properties:
Optional properties:
-broken-hpi : Use this to indicate that the mmc-card has a broken hpi
implementation, and that hpi should not be used
+-enable-hw-reset : some eMMC devices have disabled the hw reset functionality
+ (RST_N_FUNCTION) by default. By adding this property the
+ host will enable it during initialization. This will set
+ RST_N_FUNCTION to 0x1 (permanently enabled).
Example:
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index b502601..30066be 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -1520,9 +1520,16 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
int err;
u32 cid[4];
u32 rocr;
+ struct device_node *np;
+ bool enable_rst_n = false;
WARN_ON(!host->claimed);
+ np = mmc_of_find_child_device(host, 0);
+ if (np && of_device_is_compatible(np, "mmc-card"))
+ enable_rst_n = of_property_read_bool(np, "enable-hw-reset");
+ of_node_put(np);
+
/* Set correct bus mode for MMC before attempting init */
if (!mmc_host_is_spi(host))
mmc_set_bus_mode(host, MMC_BUSMODE_OPENDRAIN);
@@ -1810,6 +1817,22 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
}
}
+ /*
+ * enable RST_N if requested (and rst_n_function is not set)
+ * This is needed because some eMMC chips disable this function by
+ * default.
+ */
+ if (enable_rst_n &&
+ !(card->ext_csd.rst_n_function & EXT_CSD_RST_N_EN_MASK)) {
+ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_RST_N_FUNCTION, EXT_CSD_RST_N_ENABLED,
+ card->ext_csd.generic_cmd6_time);
+ card->ext_csd.rst_n_function = EXT_CSD_RST_N_ENABLED;
+ if (err && err != -EBADMSG)
+ pr_warn("%s: Enabling RST_N feature failed\n",
+ mmc_hostname(card->host));
+ }
+
if (!oldcard)
host->card = card;
--
2.1.4
^ permalink raw reply related
* Re: [PATCH] ARM: dts: stm32f7: add STM32f769I & stm32f746 discovery board support
From: Alexandre Torgue @ 2017-04-11 7:50 UTC (permalink / raw)
To: Vikas Manocha, patrice.chotard-qxv4g6HH51o
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM PORT, open list, Mark Rutland, Maxime Coquelin,
Rob Herring, Russell King
In-Reply-To: <6e07ebcf-4463-523f-ea24-5a176efb0779-qxv4g6HH51o@public.gmane.org>
Hi Vikas
On 04/10/2017 08:40 PM, Vikas Manocha wrote:
> Thanks Alex,
>
> On 04/10/2017 12:23 AM, Alexandre Torgue wrote:
>> Hi
>>
>> On 04/08/2017 03:12 AM, Vikas Manocha wrote:
>>> Stm32f769I & stm32f746 are MCUs of stm32f7 family. Here are the major
>>> spces of the two boards:
>>>
>>> stm32f769I discovery board:
>>> - Cortex-M7 core @216MHz
>>> - 2MB mcu internal flash
>>> - 512KB internal sram
>>> - 16MB sdram memory
>>> - 64MB qspi flash memory
>>> - 4 inch wvga LCD-TFT Display
>>>
>>> stm32f746 discovery board:
>>> - Cortex-M7 core @216MHz
>>> - 1MB mcu internal flash
>>> - 320KB internal sram
>>> - 8MB sdram memory
>>> - 16MB qspi flash memory
>>> - 4.3 inch 480x272 LCD-TFT display
>>>
>>> Signed-off-by: Vikas Manocha <vikas.manocha-qxv4g6HH51o@public.gmane.org>
>>> ---
>>> arch/arm/boot/dts/Makefile | 2 +
>>> arch/arm/boot/dts/stm32f746-disco.dts | 101 ++++++++++++++++++++++++++++++++++
>>> arch/arm/boot/dts/stm32f746.dtsi | 2 +-
>>> arch/arm/boot/dts/stm32f769-disco.dts | 101 ++++++++++++++++++++++++++++++++++
>>> 4 files changed, 205 insertions(+), 1 deletion(-)
>>> create mode 100644 arch/arm/boot/dts/stm32f746-disco.dts
>>> create mode 100644 arch/arm/boot/dts/stm32f769-disco.dts
>>>
>>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>>> index 0118084..a119f74 100644
>>> --- a/arch/arm/boot/dts/Makefile
>>> +++ b/arch/arm/boot/dts/Makefile
>>> @@ -763,6 +763,8 @@ dtb-$(CONFIG_ARCH_STI) += \
>>> dtb-$(CONFIG_ARCH_STM32)+= \
>>> stm32f429-disco.dtb \
>>> stm32f469-disco.dtb \
>>> + stm32f746-disco.dtb \
>>> + stm32f769-disco.dtb \
>>> stm32429i-eval.dtb \
>>> stm32746g-eval.dtb
>>> dtb-$(CONFIG_MACH_SUN4I) += \
>>> diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts
>>> new file mode 100644
>>> index 0000000..c0e313f
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/stm32f746-disco.dts
>>> @@ -0,0 +1,101 @@
>>> +/*
>>> + * Copyright 2017 - Vikas MANOCHA <vikas.manocha-qxv4g6HH51o@public.gmane.org>
>>> + *
>>> + * This file is dual-licensed: you can use it either under the terms
>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>> + * licensing only applies to this file, and not this project as a
>>> + * whole.
>>> + *
>>> + * a) This file is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation; either version 2 of the
>>> + * License, or (at your option) any later version.
>>> + *
>>> + * This file is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * Or, alternatively,
>>> + *
>>> + * b) Permission is hereby granted, free of charge, to any person
>>> + * obtaining a copy of this software and associated documentation
>>> + * files (the "Software"), to deal in the Software without
>>> + * restriction, including without limitation the rights to use,
>>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>>> + * sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following
>>> + * conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be
>>> + * included in all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +#include "stm32f746.dtsi"
>>> +#include <dt-bindings/input/input.h>
>>> +
>>> +/ {
>>> + model = "STMicroelectronics STM32F746-DISCO board";
>>> + compatible = "st,stm32f746-disco", "st,stm32f746";
>>> +
>>> + chosen {
>>> + bootargs = "root=/dev/ram";
>>> + stdout-path = "serial0:115200n8";
>>> + };
>>> +
>>> + memory {
>>> + reg = <0xC0000000 0x800000>;
>>> + };
>>> +
>>> + aliases {
>>> + serial0 = &usart1;
>>> + };
>>> +
>>> +};
>>> +
>>> +&clk_hse {
>>> + clock-frequency = <25000000>;
>>> +};
>>> +
>>> +&pinctrl {
>>
>>
>> Pin muxing is not defined in board file. Please move it into SOC dtsi file.
>
> Pin muxing used is different for different boards. e.g. usart1_rx pad is PA10 for stm32f769-disco board while it is PB7 for stm32f746-disco board.
> The other possibilities for same pad (usart1_rx) is PB15. To make situation bit more complex, it is only available in f769 device.
>
> Putting in SOC dtsi file means having lot of combinations for different pins in separate groups.
> e.g. only for one instance of one ip (usart1), following groups might be required at one point of time:
>
> usart1_pa10_pa9 {..}
> usart1_pa10_pb14 {..}
> usart1_pa10_pb6 {..}
>
> usart1_pb7_pa9 {..}
> usart1_pb7_pb14 {..}
> usart1_pb7_pb6 {..}
>
> usart1_pb15_pa9 {..}
> usart1_pb15_pb14 {..}
> usart1_pb15_pb6 {..}
>
> In case of boards based on stm32f746 device, all the above mentioned groups with pb14 & pb15 will not be available.
> One solution (to avoid using not available groups) could be to have separate dtsi (or separate pinmux.dtsi) for different devices of same family like one for stm32f746 & other for stm32f769. Still it does not resolve the need to have lot of groups combinations for each instance of every peripheral in dtsi as mentioned above.
Yes, it is what I want to have. I did the job on for STM32F4 (F429 /
F469). You could have a look on ARM Linux patchwork:
https://patchwork.kernel.org/patch/9669433/
To sum-up the implementation:
-Pinmuxing is defined in separate files which will be included in board
dts file.
-We have a common pinmuxing file + a dedicated pinmuxing file per SOC.
Example for STMF469-disco:
stm32f4-pinctrl.dtsi --> stm32f469-pinctrl.dtsi --> stm32f469-disco.dts
stm32f4-pinctrl.dtsi contains common pinmuxing bindings between STM32F4
stm32f469-pinctrl.dtsi contains dedicated pinmuxing bindings for
STM32F469 (ex: QSPI pins, gpio-ranges ...)
This implementation is under review.
> It seems cleaner solution would be pin muxing in board dts file. Please let me know if there is some drawback of this approach. One point which i can think of is : duplication of pinmux groups in different board dts files.
Pinmuxing in board file is currently not my choice. In the board file we
only select the group to use.
Regards
Alex
>
> Cheers,
> Vikas
>
>>> + usart1_pins: usart1@0 {
>>> + pins1 {
>>> + pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
>>> + bias-disable;
>>> + drive-push-pull;
>>> + slew-rate = <2>;
>>> + };
>>> + pins2 {
>>> + pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
>>> + bias-disable;
>>> + };
>>> + };
>>> +
>>> + qspi_pins: qspi@0 {
>>> + pins {
>>> + pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
>>> + <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
>>> + <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
>>> + <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
>>> + <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
>>> + <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
>>> + slew-rate = <2>;
>>> + };
>>> + };
>>> +};
>>> +
>>> +&usart1 {
>>> + pinctrl-0 = <&usart1_pins>;
>>> + pinctrl-names = "default";
>>> + status = "okay";
>>> +};
>>> diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
>>> index f321ffe..826700f 100644
>>> --- a/arch/arm/boot/dts/stm32f746.dtsi
>>> +++ b/arch/arm/boot/dts/stm32f746.dtsi
>>> @@ -178,7 +178,7 @@
>>> interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
>>> };
>>>
>>> - pin-controller {
>>> + pinctrl: pin-controller {
>>> #address-cells = <1>;
>>> #size-cells = <1>;
>>> compatible = "st,stm32f746-pinctrl";
>>> diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts
>>> new file mode 100644
>>> index 0000000..5f8558e
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/stm32f769-disco.dts
>>> @@ -0,0 +1,101 @@
>>> +/*
>>> + * Copyright 2017 - Vikas MANOCHA <vikas.manocha-qxv4g6HH51o@public.gmane.org>
>>> + *
>>> + * This file is dual-licensed: you can use it either under the terms
>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>> + * licensing only applies to this file, and not this project as a
>>> + * whole.
>>> + *
>>> + * a) This file is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation; either version 2 of the
>>> + * License, or (at your option) any later version.
>>> + *
>>> + * This file is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * Or, alternatively,
>>> + *
>>> + * b) Permission is hereby granted, free of charge, to any person
>>> + * obtaining a copy of this software and associated documentation
>>> + * files (the "Software"), to deal in the Software without
>>> + * restriction, including without limitation the rights to use,
>>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>>> + * sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following
>>> + * conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be
>>> + * included in all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +#include "stm32f746.dtsi"
>>> +#include <dt-bindings/input/input.h>
>>> +
>>> +/ {
>>> + model = "STMicroelectronics STM32F769-DISCO board";
>>> + compatible = "st,stm32f769-disco", "st,stm32f7";
>>> +
>>> + chosen {
>>> + bootargs = "root=/dev/ram";
>>> + stdout-path = "serial0:115200n8";
>>> + };
>>> +
>>> + memory {
>>> + reg = <0xC0000000 0x1000000>;
>>> + };
>>> +
>>> + aliases {
>>> + serial0 = &usart1;
>>> + };
>>> +
>>> +};
>>> +
>>> +&clk_hse {
>>> + clock-frequency = <25000000>;
>>> +};
>>> +
>>> +&pinctrl {
>>
>> same.
>>
>>> + usart1_pins: usart1@0 {
>>> + pins1 {
>>> + pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
>>> + bias-disable;
>>> + drive-push-pull;
>>> + slew-rate = <2>;
>>> + };
>>> + pins2 {
>>> + pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
>>> + bias-disable;
>>> + };
>>> + };
>>> +
>>> + qspi_pins: qspi@0 {
>>> + pins {
>>> + pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
>>> + <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
>>> + <STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>,
>>> + <STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>,
>>> + <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
>>> + <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
>>> + slew-rate = <2>;
>>> + };
>>> + };
>>> +};
>>> +
>>> +&usart1 {
>>> + pinctrl-0 = <&usart1_pins>;
>>> + pinctrl-names = "default";
>>> + status = "okay";
>>> +};
>>>
>> .
>>
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^ permalink raw reply
* Re: [PATCH v4 3/9] dt-bindings: pinctrl: Add RZ/A1 bindings doc
From: Linus Walleij @ 2017-04-11 7:54 UTC (permalink / raw)
To: Rob Herring
Cc: Jacopo Mondi, Geert Uytterhoeven, Laurent Pinchart, Chris Brandt,
Mark Rutland, Russell King, Linux-Renesas,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20170410181215.e6cihbv2rfljbm3b@rob-hp-laptop>
On Mon, Apr 10, 2017 at 8:12 PM, Rob Herring <robh@kernel.org> wrote:
> On Wed, Apr 05, 2017 at 04:07:21PM +0200, Jacopo Mondi wrote:
>> + The allowed generic formats for a pin multiplexing sub-node are the
>> + following ones:
>> +
>> + node-1 {
>> + pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
>> + GENERIC_PINCONFIG;
>
> What's GENERIC_PINCONFIG? I see this in some other binding docs, but not
> used anywhere. If this is a boolean property then get rid of the all
> caps. If this is a define, then don't use complex defines that expand to
> dts source.
I guess it is a wildcard for everything under the heading in
"Generic pin configuration node content"
in Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
I'm all for documenting it properly.
It's kind of useful, but I don't know the recent ambtions about being
formal with DT bindings. The GPIO bindings are just over the top
with BNF notation in its formalism. Dunno what is best here :/
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3 14/37] mtd: nand: denali: support "nand-ecc-strength" DT property
From: Boris Brezillon @ 2017-04-11 7:56 UTC (permalink / raw)
To: Masahiro Yamada
Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Enrico Jorns,
Artem Bityutskiy, Dinh Nguyen, Marek Vasut, Graham Moore,
David Woodhouse, Masami Hiramatsu, Chuanxiao Dong, Jassi Brar,
devicetree-u79uwXL29TY76Z2rM5mHXA, Linux Kernel Mailing List,
Brian Norris, Richard Weinberger, Cyrille Pitchen, Rob Herring,
Mark Rutland
In-Reply-To: <CAK7LNARxR722uRE9SnJPuOqictrpnbFmcKBsW_g=f1OnNgvpRA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi Masahiro,
On Tue, 11 Apr 2017 15:19:21 +0900
Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org> wrote:
> Hi Boris,
>
>
>
> 2017-04-10 1:33 GMT+09:00 Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>:
> > On Mon, 3 Apr 2017 12:16:34 +0900
> > Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org> wrote:
> >
> >> Hi Boris,
> >>
> >>
> >>
> >> 2017-03-31 18:46 GMT+09:00 Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>:
> >>
> >> > You can try something like that when no explicit ecc.strength and
> >> > ecc.size has been set in the DT and when ECC_MAXIMIZE was not passed.
> >> >
> >> > static int
> >> > denali_get_closest_ecc_strength(struct denali_nand_info *denali,
> >> > int strength)
> >> > {
> >> > /*
> >> > * Whatever you need to select a strength that is greater than
> >> > * or equal to strength.
> >> > */
> >> >
> >> > return X;
> >> > }
> >>
> >>
> >> Is here anything specific to Denali?
> >
> > Well, only the denali driver knows what the hardware supports, though
> > having a generic function that takes a table of supported strengths
> > would work.
> >
> >>
> >>
> >> > static int denali_try_to_match_ecc_req(struct denali_nand_info *denali)
> >> > {
> >> > struct nand_chip *chip = &denali->nand;
> >> > struct mtd_info *mtd = nand_to_mtd(chip);
> >> > int max_ecc_bytes = mtd->oobsize - denali->bbtskipbytes;
> >> > int ecc_steps, ecc_strength, ecc_bytes;
> >> > int ecc_size = chip->ecc_step_ds;
> >> > int ecc_strength = chip->ecc_strength_ds;
> >> >
> >> > /*
> >> > * No information provided by the NAND chip, let the core
> >> > * maximize the strength.
> >> > */
> >> > if (!ecc_size || !ecc_strength)
> >> > return -ENOTSUPP;
> >> >
> >> > if (ecc_size > 512)
> >> > ecc_size = 1024;
> >> > else
> >> > ecc_size = 512;
> >> >
> >> > /* Adjust ECC step size based on hardware support. */
> >> > if (ecc_size == 1024 &&
> >> > !(denali->caps & DENALI_CAP_ECC_SIZE_1024))
> >> > ecc_size = 512;
> >> > else if(ecc_size == 512 &&
> >> > !(denali->caps & DENALI_CAP_ECC_SIZE_512))
> >> > ecc_size = 1024;
> >> >
> >> > if (ecc_size < chip->ecc_size_ds) {
> >> > /*
> >> > * When the selected size if smaller than the expected
> >> > * one we try to use the same strength but on 512 blocks
> >> > * so that we can still fix the same number of errors
> >> > * even if they are concentrated in the first 512bytes
> >> > * of a 1024bytes portion.
> >> > */
> >> > ecc_strength = chip->ecc_strength_ds;
> >> > ecc_strength = denali_get_closest_ecc_strength(denali,
> >> > ecc_strength);
> >> > } else {
> >> > /* Always prefer 1024bytes ECC blocks when possible. */
> >> > if (ecc_size != 1024 &&
> >> > (denali->caps & DENALI_CAP_ECC_SIZE_1024) &&
> >> > mtd->writesize > 1024)
> >> > ecc_size = 1024;
> >> >
> >> > /*
> >> > * Adjust the strength based on the selected ECC step
> >> > * size.
> >> > */
> >> > ecc_strength = DIV_ROUND_UP(ecc_size,
> >> > chip->ecc_step_ds) *
> >> > chip->ecc_strength_ds;
> >> > }
> >> >
> >> > ecc_bytes = denali_calc_ecc_bytes(ecc_size,
> >> > ecc_strength);
> >> > ecc_bytes *= mtd->writesize / ecc_size;
> >> >
> >> > /*
> >> > * If we don't have enough space, let the core maximize
> >> > * the strength.
> >> > */
> >> > if (ecc_bytes > max_ecc_bytes)
> >> > return -ENOTSUPP;
> >> >
> >> > chip->ecc.strength = ecc_strength;
> >> > chip->ecc.size = ecc_size;
> >> >
> >> > return 0;
> >> > }
> >>
> >>
> >> As a whole, this does not seem to driver-specific.
> >
> > It's almost controller-agnostic, except for the denali_calc_ecc_bytes()
> > function, but I guess we could ask drivers to implement a hook that is
> > passed the ECC step size and strength and returns the associated
> > number of ECC bytes.
> >
> >>
> >>
> >> [1] A driver provides some pairs of (ecc_strength, ecc_size)
> >> it can support.
> >>
> >> [2] The core framework knows the chip's requirement
> >> (ecc_strength_ds, ecc_size_ds).
> >>
> >>
> >> Then, the core framework provides a function
> >> to return a most recommended (ecc_strength, ecc_size).
> >>
> >>
> >>
> >> struct nand_ecc_spec {
> >> int ecc_strength;
> >> int ecc_size;
> >> };
> >>
> >> /*
> >> * This function choose the most recommented (ecc_str, ecc_size)
> >> * "recommended" means: minimum ecc stregth that meets
> >> * the chip's requirment.
> >> *
> >> *
> >> * @chip - nand_chip
> >> * @controller_ecc_spec - Array of (ecc_str, ecc_size) supported by the
> >> controller. (terminated by NULL as sentinel)
> >> */
> >> struct nand_ecc_spec * nand_try_to_match_ecc_req(struct nand_chip *chip,
> >> struct nand_ecc_spec
> >> *controller_ecc_spec)
> >> {
> >> /*
> >> * Return the pointer to the most recommended
> >> * struct nand_ecc_spec.
> >> * If nothing suitable found, return NULL.
> >> */
> >> }
> >>
> >
> > I like the idea, except I would do this slightly differently to avoid
> > declaring all combinations of stepsize and strengths
> >
> > struct nand_ecc_stepsize_info {
> > int stepsize;
> > int nstrengths;
> > int *strengths;
> > };
> >
> > struct nand_ecc_engine_caps {
> > int nstepsizes;
> > struct nand_ecc_stepsize_info *stepsizes;
> > int (*calc_ecc_bytes)(int stepsize, int strength);
> > };
> >
> > int nand_try_to_match_ecc_req(struct nand_chip *chip,
> > const struct nand_ecc_engine_caps *caps,
> > struct nand_ecc_spec *spec)
> > {
> > /*
> > * Find the most appropriate setting based on the ECC engine
> > * caps and fill the spec object accordingly.
> > * Returns 0 in case of success and a negative error code
> > * otherwise.
> > */
> > }
> >
> > Note that nand_try_to_match_ecc_req() has to be more generic than
> > denali_try_to_match_ecc_req() WRT step sizes, which will probably
> > complexify the logic.
>
>
> After I fiddle with this generic approach for a while,
> I started to feel like giving up.
I don't get it. What was the problem with my initial suggestion (the
denali specific one, not the generic approach)? You proposed to make it
generic, which, I agree, is a bit more complicated.
>
> I wonder if we really want over-implementation
> for covering _theoretically_ possible cases.
Okay, one more theoretical case I'd like to expose: you have board
design with different NAND parts which have different ECC requirements.
If you were about to describe the exact ECC strength you want for each
board you'll have to have different DTs. Maximizing the ECC strength
would still work, but what if the MTD user needs some OOB bytes (like
is the case with JFFS2) and ECC maximization reserved all of the
available bytes?
The other reason I prefer to have the drivers automatically guessing
what's appropriate is because then you don't have to care when writing
your DT.
>
> In practice, there are not so many ECC settings possible
> on a single controller.
>
> As for Denali IP, it would be theoretically possible to instantiate
> multiple ECC engines. However, in practice, there is no sensible
> reason to do so. At least, I do not know any real chip to support that.
>
> So, I'd like to simplify the logic for Denali.
>
> - Support either 512 or 1024 ECC size.
> If there is (ever) a controller that supports both,
> 1024 should be chosen.
>
> - ECC strength is not specified via DT, it is simply maximized.
>
> This simplifies the logic much and I believe this is enough.
>
> One more reason is, as we talked before,
> we need to match ECC setting between Linux and firmware (boot-loader),
If the bootloader implements the same logic it should match.
> so anyway we end up with using a fixed setting specified by DT.
>
Really, I don't see what's the problem with the function I proposed,
but I'm willing to make a concession.
Make the nand-ecc-strength+nand-ecc-step-size or nand-ecc-maximize
mandatory so that if someone ever needs to support the 'match NAND
requirements' feature we won't have to add a vendor specific property
like this one [1].
Are you fine with that?
[1]http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/mtd/gpmi-nand.txt#L20
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^ permalink raw reply
* Re: [PATCH v7 00/13] mmc: Add support to Marvell Xenon SD Host Controller
From: Gregory CLEMENT @ 2017-04-11 7:59 UTC (permalink / raw)
To: Ulf Hansson
Cc: Adrian Hunter, linux-mmc@vger.kernel.org, Jason Cooper,
Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni,
linux-arm-kernel@lists.infradead.org, Mike Turquette,
Stephen Boyd, linux-clk, linux-kernel@vger.kernel.org,
Rob Herring, devicetree@vger.kernel.org, Ziji Hu, Jimmy Xu,
Jisheng Zhang, Nadav Haklai
In-Reply-To: <CAPDyKFqsU6vSmM3kMzGw4DmoB8JpUKaTJYzXUfwCz5cCbYM_3A@mail.gmail.com>
Hi Ulf,
On lun., avril 10 2017, Ulf Hansson <ulf.hansson@linaro.org> wrote:
> On 30 March 2017 at 17:22, Gregory CLEMENT
> <gregory.clement@free-electrons.com> wrote:
>> Hello,
>>
>> This the seventh version of the series adding support for the SDHCI
>> Xenon controller. It can be currently found on the Armada 37xx and the
>> Armada 7K/8K but will be also used in more Marvell SoC (and not only
>> the mvebu ones actually).
>>
>> v6->v7:
>> - Add comments on vqmmc and vmmc in examples in dt binding doc.
>>
>> - Fix all the issues pointed out by Ulf and Adrian:
>>
>> - Align the prefix of function and variable names.
>> - Replace the if-else with switch statements when checking MMC_TIMING_*
>> - Remove the spinlocks in set_ios.
>> - Optimize the delay loop as Adrian patch does.
>> - Add release of phy params structures
>>
>> - Add check of Vqmmc supply in Xenon signal voltage switch. If Vqmmc
>> regulator doesn't exist, skip standard SD signal voltage regulator
>> switch process.
>>
>> - Remove parse of child node mmc-card. Wait for a better solution.
>>
>> v5->v6:
>>
>> - Add a generic "mmc-card" parse in core layer.
>>
>> - Fix the spelling issues in Xenon dt binding doc and drivers.
>>
>> - Remove descriptions to common mmc properties from Xenon dt binding
>> doc.
>>
>> - Split compatible string "marvell,armada-8k-sdhci" into
>> "marvell,armada-ap806-sdhci" and "marvell,armada-cp110-sdhci".
>>
>> - Also updates the example in Xenon dt binding doc.
>>
>> - Remove unnecessary dependency on MMC_SDHCI from Xenon entry in
>> Kconfig.
>>
>> - Move Xenon specific dt parse into a separate function.
>>
>> - Adjust warnings and condition check in Xenon PHY setting, to remove
>> fragile hs200->hs400/hs400->hs200 sequence check function.
>>
>> - Enable PHY Slow Mode in MMC_TIMING_LEGACY timing if PHY Slow Mode is
>> required in dts.
>>
>> - Add a patch allowing dts backwards compatible for the clock
>>
>> v4->v5:
>>
>> - Remove the patch to export sdhci_execute_tuning(). It is already
>> exported in v4.10.
>>
>> - Introduce a patch adding a missing clock for the sdhci controller
>> present on the CP master for A7K/A8K. There is no build dependency
>> but obviously this patch is need to use the sdhci controller present
>> on the CP part.
>>
>> - Adjust Xenon return setup, to avoid being overwritten by
>> sdhci_add_host().
>>
>> - Change Xenon register definition prefix to "XENON_".
>>
>> - Fix typos in Xenon driver and dt-binding docs.
>>
>> - Change compatible string "marvell,armada-7000-sdhci" to
>> "marvell,armada-8k-sdhci". Actually the Armada 7K SoCs are a subset
>> of the Armada 8K SoCs. Moreover, the use of the '000' is not
>> consistent with all the other compatible string already used for the
>> Armada 7K/8K family.
>>
>> - Added the Tested-by from Russell King on an Armada 8K based board.
>>
>> v3 -> v4:
>> For this version a few change have been done:
>> - fixes 2 bug reported by kbuild-bot
>> - remove extra of_node_put()
>> - convert 0 in false for function returning boolean
>>
>> - add a device tree node for the sdhci controller present on the CP
>> master for A7K/A8K. It also led to rename the sdhci0 node on AP to
>> ap_sdhci0 to make a distinction with the one present on CP master.
>>
>> v2 -> v3
>> I think that now most (if not all) the remarks had been taking into
>> account since the second version. According to Ziji Hu, here are the
>> following changes:
>> " Changes in V3:
>> Adjust and improve Xenon DT bindings. Move some caps setting from driver into
>> DT. Use mmc-card sub-node to represent eMMC type.
>> Remove PHY Sampling Fixed Delay Line scan in lower speed mode.
>> Improve Xenon probe and ->init_card() functions.
>> Export sdhci_enable_sdio_irq() and implement own SDIO IRQ control.
>> Split PHY patch into two smaller patches.
>> Temporarily remove AXI clock before its implementation is improved."
>>
>> Besides this changes I also
>> - Removed the sdhci-xenon-phy.h and moved its content in the
>> shc-xenon-phy.c file.
>> - Fixed the tuning-count usage
>> - Managed the error case for clk_prepare_enable
>>
>> For the record the change from v1 was:
>> " Changes in V2:
>> rebase on v4.9-rc2.
>> Re-write Xenon bindings. Ajust Xenon DT property naming.
>> Add a new DT property to indicate eMMC card type, instead of using
>> variable card_candidate.
>> Clear quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 in Xenon platform data
>> Add support to HS400 retuning."
>>
>> Thanks,
>>
>> Gregory
>>
>> Gregory CLEMENT (4):
>> clk: apn806: Turn the eMMC clock as optional for dts backwards compatible
>> arm64: dts: marvell: add eMMC support for Armada 37xx
>> arm64: dts: marvell: add sdhci support for Armada 7K/8K
>> arm64: configs: enable SDHCI driver for Xenon
>>
>> Hu Ziji (8):
>> mmc: sdhci: Export sdhci_set_ios() from sdhci.c
>> mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c
>> mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.c
>> dt: bindings: Add bindings for Marvell Xenon SD Host Controller
>> mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality
>> mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC
>> mmc: sdhci-xenon: Add SoC PHY PAD voltage control
>> MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers
>>
>> Konstantin Porotchkin (1):
>> clk: apn806: Add eMMC clock to system controller driver
>>
>> Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 170 +-
>> MAINTAINERS | 7 +-
>> arch/arm64/boot/dts/marvell/armada-3720-db.dts | 9 +-
>> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +-
>> arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 +-
>> arch/arm64/boot/dts/marvell/armada-8040-db.dts | 12 +-
>> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 14 +-
>> arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 11 +-
>> arch/arm64/configs/defconfig | 1 +-
>> drivers/clk/mvebu/ap806-system-controller.c | 21 +-
>> drivers/mmc/host/Kconfig | 8 +-
>> drivers/mmc/host/Makefile | 3 +-
>> drivers/mmc/host/sdhci-xenon-phy.c | 835 +++++++-
>> drivers/mmc/host/sdhci-xenon.c | 548 +++++-
>> drivers/mmc/host/sdhci-xenon.h | 101 +-
>> drivers/mmc/host/sdhci.c | 11 +-
>> drivers/mmc/host/sdhci.h | 4 +-
>> 17 files changed, 1774 insertions(+), 6 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
>> create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c
>> create mode 100644 drivers/mmc/host/sdhci-xenon.c
>> create mode 100644 drivers/mmc/host/sdhci-xenon.h
>>
>> base-commit: a645cc1df4ff41ba54a2fb839962b8ff142121d9
>> --
>> git-series 0.9.1
>
>
> Thanks, applied patch 1->10 for next! 11->13 will have to go via the
> SoC maintainer tree.
Great, thanks!
Patch 11 and 12 are now applied on mvebu/dt64 and patch 13 on
mvebu/defconfig64.
Gregory
>
> Kind regards
> Uffe
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* Re: [RESEND PATCH v4] iio: adc: add support for X-Powers AXP20X and AXP22X PMICs ADCs
From: Lee Jones @ 2017-04-11 8:01 UTC (permalink / raw)
To: Quentin Schulz
Cc: sre-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
icenowy-ymACFijhrKM,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA, linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
liam-RYWXG+zxWwBdeoIcmNTgJF6hYfS7NtTn,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1800d928-d804-71db-cd0b-ec79cc504ee6-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Tue, 11 Apr 2017, Quentin Schulz wrote:
> On 10/04/2017 16:54, Lee Jones wrote:
> > On Mon, 10 Apr 2017, Quentin Schulz wrote:
> >
> >> Hi Lee,
> >>
> >> Just to make sure you didn't miss that patch (can't find it in
> >> for-mfd-next and for-mfd-next-next).
> >
> > It has not been missed, but is yet to be reviewed.
> >
>
> Hum.. What do you mean exactly? The maintainer of the AXP PMICs has
> given its Acked-by and the maintainer of the IIO subsystem has given its
> Reviewed-by. Is there something I'm missing (in your workflow maybe)?
I mean I haven't reviewed and picked it up yet.
I will get around to it shortly.
> >> On 04/04/2017 08:34, Quentin Schulz wrote:
> >>> The X-Powers AXP20X and AXP22X PMICs have multiple ADCs. They expose the
> >>> battery voltage, battery charge and discharge currents, AC-in and VBUS
> >>> voltages and currents, 2 GPIOs muxable in ADC mode and PMIC temperature.
> >>>
> >>> This adds support for most of AXP20X and AXP22X ADCs.
> >>>
> >>> Signed-off-by: Quentin Schulz <quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> >>> Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> >>> Acked-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> >>> Reviewed-by: Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> >>> ---
> >>>
> >>> Lee, could you merge this through the mfd tree please?
> >>> => https://lkml.org/lkml/2017/3/22/47
> >>>
> >>> v4:
> >>> - added missing space at the beginning of a comment,
> >>> - tidied axp20x_adc_offset_voltage and axp20x_write_raw to use switch case
> >>> instead of if conditions,
> >>> - added MODULE_DEVICE_TABLE for axp20x_adc_id_match for module autoloading,
> >>> - merged two lines in axp20x_remove,
> >>>
> >>> v3:
> >>> - moved from switch to if condition in axp20x_adc_raw and
> >>> axp22x_adc_raw,
> >>> - removed DT support as DT node has been dropped,
> >>> - use of platform_device_id
> >>> - correctly defined the name of the iio device (name used to probe the
> >>> driver),
> >>> - added goto for errors in probe,
> >>> - added iio_map_array_unregister to the remove function,
> >>>
> >>> v2:
> >>> - removed unused defines,
> >>> - changed BIT(x) to 1 << x when describing bits purpose for which 2 <<
> >>> x or 3 << x exists, to be consistent,
> >>> - changed ADC rate defines to macro formulas,
> >>> - reordered IIO channels, now different measures (current/voltage) of
> >>> the same part of the PMIC (e.g. battery), have the same IIO channel in
> >>> their respective IIO type. When a part of the PMIC have only one
> >>> measure, a number is jumped,
> >>> - left IIO channel mapping in DT to use iio_map structure,
> >>> - removed indexing of ADC internal temperature,
> >>> - removed unused iio_dev structure in axp20x_adc_iio,
> >>> - added a structure for data specific to AXP20X or AXP22X PMICs instead
> >>> of using an ID and an if condition when needing to separate the
> >>> behaviour of both,
> >>> - added a comment on batt_chrg_i really being on 12bits rather than
> >>> what the Chinese datasheets say (13 bits),
> >>> - corrected the offset for AXP22X PMIC temperature,
> >>> - set the ADC rate to a value (100Hz) shared by the AXP20X and AXP22X,
> >>> - created macro formulas to compute the ADC rate for each,
> >>> - added a condition on presence of ADC_EN2 reg before setting/resetting
> >>> it,
> >>> - switched from devm_iio_device_unregister to the non-devm function
> >>> because of the need for a remove function,
> >>> - removed some dead code,
> >>>
> >>> drivers/iio/adc/Kconfig | 10 +
> >>> drivers/iio/adc/Makefile | 1 +
> >>> drivers/iio/adc/axp20x_adc.c | 617 +++++++++++++++++++++++++++++++++++++++++++
> >>> 3 files changed, 628 insertions(+)
> >>> create mode 100644 drivers/iio/adc/axp20x_adc.c
> >>>
> >>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> >>> index d777a97..d15e1bd 100644
> >>> --- a/drivers/iio/adc/Kconfig
> >>> +++ b/drivers/iio/adc/Kconfig
> >>> @@ -154,6 +154,16 @@ config AT91_SAMA5D2_ADC
> >>> To compile this driver as a module, choose M here: the module will be
> >>> called at91-sama5d2_adc.
> >>>
> >>> +config AXP20X_ADC
> >>> + tristate "X-Powers AXP20X and AXP22X ADC driver"
> >>> + depends on MFD_AXP20X
> >>> + help
> >>> + Say yes here to have support for X-Powers power management IC (PMIC)
> >>> + AXP20X and AXP22X ADC devices.
> >>> +
> >>> + To compile this driver as a module, choose M here: the module will be
> >>> + called axp20x_adc.
> >>> +
> >>> config AXP288_ADC
> >>> tristate "X-Powers AXP288 ADC driver"
> >>> depends on MFD_AXP20X
> >>> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> >>> index b11bb57..17899b5 100644
> >>> --- a/drivers/iio/adc/Makefile
> >>> +++ b/drivers/iio/adc/Makefile
> >>> @@ -16,6 +16,7 @@ obj-$(CONFIG_AD7887) += ad7887.o
> >>> obj-$(CONFIG_AD799X) += ad799x.o
> >>> obj-$(CONFIG_AT91_ADC) += at91_adc.o
> >>> obj-$(CONFIG_AT91_SAMA5D2_ADC) += at91-sama5d2_adc.o
> >>> +obj-$(CONFIG_AXP20X_ADC) += axp20x_adc.o
> >>> obj-$(CONFIG_AXP288_ADC) += axp288_adc.o
> >>> obj-$(CONFIG_BCM_IPROC_ADC) += bcm_iproc_adc.o
> >>> obj-$(CONFIG_BERLIN2_ADC) += berlin2-adc.o
> >>> diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c
> >>> new file mode 100644
> >>> index 0000000..11e1771
> >>> --- /dev/null
> >>> +++ b/drivers/iio/adc/axp20x_adc.c
> >>> @@ -0,0 +1,617 @@
> >>> +/* ADC driver for AXP20X and AXP22X PMICs
> >>> + *
> >>> + * Copyright (c) 2016 Free Electrons NextThing Co.
> >>> + * Quentin Schulz <quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> >>> + *
> >>> + * This program is free software; you can redistribute it and/or modify it under
> >>> + * the terms of the GNU General Public License version 2 as published by the
> >>> + * Free Software Foundation.
> >>> + */
> >>> +
> >>> +#include <linux/completion.h>
> >>> +#include <linux/interrupt.h>
> >>> +#include <linux/io.h>
> >>> +#include <linux/module.h>
> >>> +#include <linux/of.h>
> >>> +#include <linux/of_device.h>
> >>> +#include <linux/platform_device.h>
> >>> +#include <linux/pm_runtime.h>
> >>> +#include <linux/regmap.h>
> >>> +#include <linux/thermal.h>
> >>> +
> >>> +#include <linux/iio/iio.h>
> >>> +#include <linux/iio/driver.h>
> >>> +#include <linux/iio/machine.h>
> >>> +#include <linux/mfd/axp20x.h>
> >>> +
> >>> +#define AXP20X_ADC_EN1_MASK GENMASK(7, 0)
> >>> +
> >>> +#define AXP20X_ADC_EN2_MASK (GENMASK(3, 2) | BIT(7))
> >>> +#define AXP22X_ADC_EN1_MASK (GENMASK(7, 5) | BIT(0))
> >>> +
> >>> +#define AXP20X_GPIO10_IN_RANGE_GPIO0 BIT(0)
> >>> +#define AXP20X_GPIO10_IN_RANGE_GPIO1 BIT(1)
> >>> +#define AXP20X_GPIO10_IN_RANGE_GPIO0_VAL(x) ((x) & BIT(0))
> >>> +#define AXP20X_GPIO10_IN_RANGE_GPIO1_VAL(x) (((x) & BIT(0)) << 1)
> >>> +
> >>> +#define AXP20X_ADC_RATE_MASK GENMASK(7, 6)
> >>> +#define AXP20X_ADC_RATE_HZ(x) ((ilog2((x) / 25) << 6) & AXP20X_ADC_RATE_MASK)
> >>> +#define AXP22X_ADC_RATE_HZ(x) ((ilog2((x) / 100) << 6) & AXP20X_ADC_RATE_MASK)
> >>> +
> >>> +#define AXP20X_ADC_CHANNEL(_channel, _name, _type, _reg) \
> >>> + { \
> >>> + .type = _type, \
> >>> + .indexed = 1, \
> >>> + .channel = _channel, \
> >>> + .address = _reg, \
> >>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> >>> + BIT(IIO_CHAN_INFO_SCALE), \
> >>> + .datasheet_name = _name, \
> >>> + }
> >>> +
> >>> +#define AXP20X_ADC_CHANNEL_OFFSET(_channel, _name, _type, _reg) \
> >>> + { \
> >>> + .type = _type, \
> >>> + .indexed = 1, \
> >>> + .channel = _channel, \
> >>> + .address = _reg, \
> >>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> >>> + BIT(IIO_CHAN_INFO_SCALE) |\
> >>> + BIT(IIO_CHAN_INFO_OFFSET),\
> >>> + .datasheet_name = _name, \
> >>> + }
> >>> +
> >>> +struct axp_data;
> >>> +
> >>> +struct axp20x_adc_iio {
> >>> + struct regmap *regmap;
> >>> + struct axp_data *data;
> >>> +};
> >>> +
> >>> +enum axp20x_adc_channel_v {
> >>> + AXP20X_ACIN_V = 0,
> >>> + AXP20X_VBUS_V,
> >>> + AXP20X_TS_IN,
> >>> + AXP20X_GPIO0_V,
> >>> + AXP20X_GPIO1_V,
> >>> + AXP20X_IPSOUT_V,
> >>> + AXP20X_BATT_V,
> >>> +};
> >>> +
> >>> +enum axp20x_adc_channel_i {
> >>> + AXP20X_ACIN_I = 0,
> >>> + AXP20X_VBUS_I,
> >>> + AXP20X_BATT_CHRG_I,
> >>> + AXP20X_BATT_DISCHRG_I,
> >>> +};
> >>> +
> >>> +enum axp22x_adc_channel_v {
> >>> + AXP22X_TS_IN = 0,
> >>> + AXP22X_BATT_V,
> >>> +};
> >>> +
> >>> +enum axp22x_adc_channel_i {
> >>> + AXP22X_BATT_CHRG_I = 1,
> >>> + AXP22X_BATT_DISCHRG_I,
> >>> +};
> >>> +
> >>> +static struct iio_map axp20x_maps[] = {
> >>> + {
> >>> + .consumer_dev_name = "axp20x-usb-power-supply",
> >>> + .consumer_channel = "vbus_v",
> >>> + .adc_channel_label = "vbus_v",
> >>> + }, {
> >>> + .consumer_dev_name = "axp20x-usb-power-supply",
> >>> + .consumer_channel = "vbus_i",
> >>> + .adc_channel_label = "vbus_i",
> >>> + }, {
> >>> + .consumer_dev_name = "axp20x-ac-power-supply",
> >>> + .consumer_channel = "acin_v",
> >>> + .adc_channel_label = "acin_v",
> >>> + }, {
> >>> + .consumer_dev_name = "axp20x-ac-power-supply",
> >>> + .consumer_channel = "acin_i",
> >>> + .adc_channel_label = "acin_i",
> >>> + }, {
> >>> + .consumer_dev_name = "axp20x-battery-power-supply",
> >>> + .consumer_channel = "batt_v",
> >>> + .adc_channel_label = "batt_v",
> >>> + }, {
> >>> + .consumer_dev_name = "axp20x-battery-power-supply",
> >>> + .consumer_channel = "batt_chrg_i",
> >>> + .adc_channel_label = "batt_chrg_i",
> >>> + }, {
> >>> + .consumer_dev_name = "axp20x-battery-power-supply",
> >>> + .consumer_channel = "batt_dischrg_i",
> >>> + .adc_channel_label = "batt_dischrg_i",
> >>> + }, { /* sentinel */ }
> >>> +};
> >>> +
> >>> +static struct iio_map axp22x_maps[] = {
> >>> + {
> >>> + .consumer_dev_name = "axp20x-battery-power-supply",
> >>> + .consumer_channel = "batt_v",
> >>> + .adc_channel_label = "batt_v",
> >>> + }, {
> >>> + .consumer_dev_name = "axp20x-battery-power-supply",
> >>> + .consumer_channel = "batt_chrg_i",
> >>> + .adc_channel_label = "batt_chrg_i",
> >>> + }, {
> >>> + .consumer_dev_name = "axp20x-battery-power-supply",
> >>> + .consumer_channel = "batt_dischrg_i",
> >>> + .adc_channel_label = "batt_dischrg_i",
> >>> + }, { /* sentinel */ }
> >>> +};
> >>> +
> >>> +/*
> >>> + * Channels are mapped by physical system. Their channels share the same index.
> >>> + * i.e. acin_i is in_current0_raw and acin_v is in_voltage0_raw.
> >>> + * The only exception is for the battery. batt_v will be in_voltage6_raw and
> >>> + * charge current in_current6_raw and discharge current will be in_current7_raw.
> >>> + */
> >>> +static const struct iio_chan_spec axp20x_adc_channels[] = {
> >>> + AXP20X_ADC_CHANNEL(AXP20X_ACIN_V, "acin_v", IIO_VOLTAGE,
> >>> + AXP20X_ACIN_V_ADC_H),
> >>> + AXP20X_ADC_CHANNEL(AXP20X_ACIN_I, "acin_i", IIO_CURRENT,
> >>> + AXP20X_ACIN_I_ADC_H),
> >>> + AXP20X_ADC_CHANNEL(AXP20X_VBUS_V, "vbus_v", IIO_VOLTAGE,
> >>> + AXP20X_VBUS_V_ADC_H),
> >>> + AXP20X_ADC_CHANNEL(AXP20X_VBUS_I, "vbus_i", IIO_CURRENT,
> >>> + AXP20X_VBUS_I_ADC_H),
> >>> + {
> >>> + .type = IIO_TEMP,
> >>> + .address = AXP20X_TEMP_ADC_H,
> >>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
> >>> + BIT(IIO_CHAN_INFO_SCALE) |
> >>> + BIT(IIO_CHAN_INFO_OFFSET),
> >>> + .datasheet_name = "pmic_temp",
> >>> + },
> >>> + AXP20X_ADC_CHANNEL_OFFSET(AXP20X_GPIO0_V, "gpio0_v", IIO_VOLTAGE,
> >>> + AXP20X_GPIO0_V_ADC_H),
> >>> + AXP20X_ADC_CHANNEL_OFFSET(AXP20X_GPIO1_V, "gpio1_v", IIO_VOLTAGE,
> >>> + AXP20X_GPIO1_V_ADC_H),
> >>> + AXP20X_ADC_CHANNEL(AXP20X_IPSOUT_V, "ipsout_v", IIO_VOLTAGE,
> >>> + AXP20X_IPSOUT_V_HIGH_H),
> >>> + AXP20X_ADC_CHANNEL(AXP20X_BATT_V, "batt_v", IIO_VOLTAGE,
> >>> + AXP20X_BATT_V_H),
> >>> + AXP20X_ADC_CHANNEL(AXP20X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
> >>> + AXP20X_BATT_CHRG_I_H),
> >>> + AXP20X_ADC_CHANNEL(AXP20X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
> >>> + AXP20X_BATT_DISCHRG_I_H),
> >>> +};
> >>> +
> >>> +static const struct iio_chan_spec axp22x_adc_channels[] = {
> >>> + {
> >>> + .type = IIO_TEMP,
> >>> + .address = AXP22X_PMIC_TEMP_H,
> >>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
> >>> + BIT(IIO_CHAN_INFO_SCALE) |
> >>> + BIT(IIO_CHAN_INFO_OFFSET),
> >>> + .datasheet_name = "pmic_temp",
> >>> + },
> >>> + AXP20X_ADC_CHANNEL(AXP22X_BATT_V, "batt_v", IIO_VOLTAGE,
> >>> + AXP20X_BATT_V_H),
> >>> + AXP20X_ADC_CHANNEL(AXP22X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
> >>> + AXP20X_BATT_CHRG_I_H),
> >>> + AXP20X_ADC_CHANNEL(AXP22X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
> >>> + AXP20X_BATT_DISCHRG_I_H),
> >>> +};
> >>> +
> >>> +static int axp20x_adc_raw(struct iio_dev *indio_dev,
> >>> + struct iio_chan_spec const *chan, int *val)
> >>> +{
> >>> + struct axp20x_adc_iio *info = iio_priv(indio_dev);
> >>> + int size = 12;
> >>> +
> >>> + /*
> >>> + * N.B.: Unlike the Chinese datasheets tell, the charging current is
> >>> + * stored on 12 bits, not 13 bits. Only discharging current is on 13
> >>> + * bits.
> >>> + */
> >>> + if (chan->type == IIO_CURRENT && chan->channel == AXP20X_BATT_DISCHRG_I)
> >>> + size = 13;
> >>> + else
> >>> + size = 12;
> >>> +
> >>> + *val = axp20x_read_variable_width(info->regmap, chan->address, size);
> >>> + if (*val < 0)
> >>> + return *val;
> >>> +
> >>> + return IIO_VAL_INT;
> >>> +}
> >>> +
> >>> +static int axp22x_adc_raw(struct iio_dev *indio_dev,
> >>> + struct iio_chan_spec const *chan, int *val)
> >>> +{
> >>> + struct axp20x_adc_iio *info = iio_priv(indio_dev);
> >>> + int size;
> >>> +
> >>> + /*
> >>> + * N.B.: Unlike the Chinese datasheets tell, the charging current is
> >>> + * stored on 12 bits, not 13 bits. Only discharging current is on 13
> >>> + * bits.
> >>> + */
> >>> + if (chan->type == IIO_CURRENT && chan->channel == AXP22X_BATT_DISCHRG_I)
> >>> + size = 13;
> >>> + else
> >>> + size = 12;
> >>> +
> >>> + *val = axp20x_read_variable_width(info->regmap, chan->address, size);
> >>> + if (*val < 0)
> >>> + return *val;
> >>> +
> >>> + return IIO_VAL_INT;
> >>> +}
> >>> +
> >>> +static int axp20x_adc_scale_voltage(int channel, int *val, int *val2)
> >>> +{
> >>> + switch (channel) {
> >>> + case AXP20X_ACIN_V:
> >>> + case AXP20X_VBUS_V:
> >>> + *val = 1;
> >>> + *val2 = 700000;
> >>> + return IIO_VAL_INT_PLUS_MICRO;
> >>> +
> >>> + case AXP20X_GPIO0_V:
> >>> + case AXP20X_GPIO1_V:
> >>> + *val = 0;
> >>> + *val2 = 500000;
> >>> + return IIO_VAL_INT_PLUS_MICRO;
> >>> +
> >>> + case AXP20X_BATT_V:
> >>> + *val = 1;
> >>> + *val2 = 100000;
> >>> + return IIO_VAL_INT_PLUS_MICRO;
> >>> +
> >>> + case AXP20X_IPSOUT_V:
> >>> + *val = 1;
> >>> + *val2 = 400000;
> >>> + return IIO_VAL_INT_PLUS_MICRO;
> >>> +
> >>> + default:
> >>> + return -EINVAL;
> >>> + }
> >>> +}
> >>> +
> >>> +static int axp20x_adc_scale_current(int channel, int *val, int *val2)
> >>> +{
> >>> + switch (channel) {
> >>> + case AXP20X_ACIN_I:
> >>> + *val = 0;
> >>> + *val2 = 625000;
> >>> + return IIO_VAL_INT_PLUS_MICRO;
> >>> +
> >>> + case AXP20X_VBUS_I:
> >>> + *val = 0;
> >>> + *val2 = 375000;
> >>> + return IIO_VAL_INT_PLUS_MICRO;
> >>> +
> >>> + case AXP20X_BATT_DISCHRG_I:
> >>> + case AXP20X_BATT_CHRG_I:
> >>> + *val = 0;
> >>> + *val2 = 500000;
> >>> + return IIO_VAL_INT_PLUS_MICRO;
> >>> +
> >>> + default:
> >>> + return -EINVAL;
> >>> + }
> >>> +}
> >>> +
> >>> +static int axp20x_adc_scale(struct iio_chan_spec const *chan, int *val,
> >>> + int *val2)
> >>> +{
> >>> + switch (chan->type) {
> >>> + case IIO_VOLTAGE:
> >>> + return axp20x_adc_scale_voltage(chan->channel, val, val2);
> >>> +
> >>> + case IIO_CURRENT:
> >>> + return axp20x_adc_scale_current(chan->channel, val, val2);
> >>> +
> >>> + case IIO_TEMP:
> >>> + *val = 100;
> >>> + return IIO_VAL_INT;
> >>> +
> >>> + default:
> >>> + return -EINVAL;
> >>> + }
> >>> +}
> >>> +
> >>> +static int axp22x_adc_scale(struct iio_chan_spec const *chan, int *val,
> >>> + int *val2)
> >>> +{
> >>> + switch (chan->type) {
> >>> + case IIO_VOLTAGE:
> >>> + if (chan->channel != AXP22X_BATT_V)
> >>> + return -EINVAL;
> >>> +
> >>> + *val = 1;
> >>> + *val2 = 100000;
> >>> + return IIO_VAL_INT_PLUS_MICRO;
> >>> +
> >>> + case IIO_CURRENT:
> >>> + *val = 0;
> >>> + *val2 = 500000;
> >>> + return IIO_VAL_INT_PLUS_MICRO;
> >>> +
> >>> + case IIO_TEMP:
> >>> + *val = 100;
> >>> + return IIO_VAL_INT;
> >>> +
> >>> + default:
> >>> + return -EINVAL;
> >>> + }
> >>> +}
> >>> +
> >>> +static int axp20x_adc_offset_voltage(struct iio_dev *indio_dev, int channel,
> >>> + int *val)
> >>> +{
> >>> + struct axp20x_adc_iio *info = iio_priv(indio_dev);
> >>> + int ret;
> >>> +
> >>> + ret = regmap_read(info->regmap, AXP20X_GPIO10_IN_RANGE, val);
> >>> + if (ret < 0)
> >>> + return ret;
> >>> +
> >>> + switch (channel) {
> >>> + case AXP20X_GPIO0_V:
> >>> + *val &= AXP20X_GPIO10_IN_RANGE_GPIO0;
> >>> + break;
> >>> +
> >>> + case AXP20X_GPIO1_V:
> >>> + *val &= AXP20X_GPIO10_IN_RANGE_GPIO1;
> >>> + break;
> >>> +
> >>> + default:
> >>> + return -EINVAL;
> >>> + }
> >>> +
> >>> + *val = !!(*val) * 700000;
> >>> +
> >>> + return IIO_VAL_INT;
> >>> +}
> >>> +
> >>> +static int axp20x_adc_offset(struct iio_dev *indio_dev,
> >>> + struct iio_chan_spec const *chan, int *val)
> >>> +{
> >>> + switch (chan->type) {
> >>> + case IIO_VOLTAGE:
> >>> + return axp20x_adc_offset_voltage(indio_dev, chan->channel, val);
> >>> +
> >>> + case IIO_TEMP:
> >>> + *val = -1447;
> >>> + return IIO_VAL_INT;
> >>> +
> >>> + default:
> >>> + return -EINVAL;
> >>> + }
> >>> +}
> >>> +
> >>> +static int axp20x_read_raw(struct iio_dev *indio_dev,
> >>> + struct iio_chan_spec const *chan, int *val,
> >>> + int *val2, long mask)
> >>> +{
> >>> + switch (mask) {
> >>> + case IIO_CHAN_INFO_OFFSET:
> >>> + return axp20x_adc_offset(indio_dev, chan, val);
> >>> +
> >>> + case IIO_CHAN_INFO_SCALE:
> >>> + return axp20x_adc_scale(chan, val, val2);
> >>> +
> >>> + case IIO_CHAN_INFO_RAW:
> >>> + return axp20x_adc_raw(indio_dev, chan, val);
> >>> +
> >>> + default:
> >>> + return -EINVAL;
> >>> + }
> >>> +}
> >>> +
> >>> +static int axp22x_read_raw(struct iio_dev *indio_dev,
> >>> + struct iio_chan_spec const *chan, int *val,
> >>> + int *val2, long mask)
> >>> +{
> >>> + switch (mask) {
> >>> + case IIO_CHAN_INFO_OFFSET:
> >>> + *val = -2677;
> >>> + return IIO_VAL_INT;
> >>> +
> >>> + case IIO_CHAN_INFO_SCALE:
> >>> + return axp22x_adc_scale(chan, val, val2);
> >>> +
> >>> + case IIO_CHAN_INFO_RAW:
> >>> + return axp22x_adc_raw(indio_dev, chan, val);
> >>> +
> >>> + default:
> >>> + return -EINVAL;
> >>> + }
> >>> +}
> >>> +
> >>> +static int axp20x_write_raw(struct iio_dev *indio_dev,
> >>> + struct iio_chan_spec const *chan, int val, int val2,
> >>> + long mask)
> >>> +{
> >>> + struct axp20x_adc_iio *info = iio_priv(indio_dev);
> >>> + unsigned int reg, regval;
> >>> +
> >>> + /*
> >>> + * The AXP20X PMIC allows the user to choose between 0V and 0.7V offsets
> >>> + * for (independently) GPIO0 and GPIO1 when in ADC mode.
> >>> + */
> >>> + if (mask != IIO_CHAN_INFO_OFFSET)
> >>> + return -EINVAL;
> >>> +
> >>> + if (val != 0 && val != 700000)
> >>> + return -EINVAL;
> >>> +
> >>> + switch (chan->channel) {
> >>> + case AXP20X_GPIO0_V:
> >>> + reg = AXP20X_GPIO10_IN_RANGE_GPIO0;
> >>> + regval = AXP20X_GPIO10_IN_RANGE_GPIO0_VAL(!!val);
> >>> + break;
> >>> +
> >>> + case AXP20X_GPIO1_V:
> >>> + reg = AXP20X_GPIO10_IN_RANGE_GPIO1;
> >>> + regval = AXP20X_GPIO10_IN_RANGE_GPIO1_VAL(!!val);
> >>> + break;
> >>> +
> >>> + default:
> >>> + return -EINVAL;
> >>> + }
> >>> +
> >>> + return regmap_update_bits(info->regmap, AXP20X_GPIO10_IN_RANGE, reg,
> >>> + regval);
> >>> +}
> >>> +
> >>> +static const struct iio_info axp20x_adc_iio_info = {
> >>> + .read_raw = axp20x_read_raw,
> >>> + .write_raw = axp20x_write_raw,
> >>> + .driver_module = THIS_MODULE,
> >>> +};
> >>> +
> >>> +static const struct iio_info axp22x_adc_iio_info = {
> >>> + .read_raw = axp22x_read_raw,
> >>> + .driver_module = THIS_MODULE,
> >>> +};
> >>> +
> >>> +static int axp20x_adc_rate(int rate)
> >>> +{
> >>> + return AXP20X_ADC_RATE_HZ(rate);
> >>> +}
> >>> +
> >>> +static int axp22x_adc_rate(int rate)
> >>> +{
> >>> + return AXP22X_ADC_RATE_HZ(rate);
> >>> +}
> >>> +
> >>> +struct axp_data {
> >>> + const struct iio_info *iio_info;
> >>> + int num_channels;
> >>> + struct iio_chan_spec const *channels;
> >>> + unsigned long adc_en1_mask;
> >>> + int (*adc_rate)(int rate);
> >>> + bool adc_en2;
> >>> + struct iio_map *maps;
> >>> +};
> >>> +
> >>> +static const struct axp_data axp20x_data = {
> >>> + .iio_info = &axp20x_adc_iio_info,
> >>> + .num_channels = ARRAY_SIZE(axp20x_adc_channels),
> >>> + .channels = axp20x_adc_channels,
> >>> + .adc_en1_mask = AXP20X_ADC_EN1_MASK,
> >>> + .adc_rate = axp20x_adc_rate,
> >>> + .adc_en2 = true,
> >>> + .maps = axp20x_maps,
> >>> +};
> >>> +
> >>> +static const struct axp_data axp22x_data = {
> >>> + .iio_info = &axp22x_adc_iio_info,
> >>> + .num_channels = ARRAY_SIZE(axp22x_adc_channels),
> >>> + .channels = axp22x_adc_channels,
> >>> + .adc_en1_mask = AXP22X_ADC_EN1_MASK,
> >>> + .adc_rate = axp22x_adc_rate,
> >>> + .adc_en2 = false,
> >>> + .maps = axp22x_maps,
> >>> +};
> >>> +
> >>> +static const struct platform_device_id axp20x_adc_id_match[] = {
> >>> + { .name = "axp20x-adc", .driver_data = (kernel_ulong_t)&axp20x_data, },
> >>> + { .name = "axp22x-adc", .driver_data = (kernel_ulong_t)&axp22x_data, },
> >>> + { /* sentinel */ },
> >>> +};
> >>> +MODULE_DEVICE_TABLE(platform, axp20x_adc_id_match);
> >>> +
> >>> +static int axp20x_probe(struct platform_device *pdev)
> >>> +{
> >>> + struct axp20x_adc_iio *info;
> >>> + struct iio_dev *indio_dev;
> >>> + struct axp20x_dev *axp20x_dev;
> >>> + int ret;
> >>> +
> >>> + axp20x_dev = dev_get_drvdata(pdev->dev.parent);
> >>> +
> >>> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
> >>> + if (!indio_dev)
> >>> + return -ENOMEM;
> >>> +
> >>> + info = iio_priv(indio_dev);
> >>> + platform_set_drvdata(pdev, indio_dev);
> >>> +
> >>> + info->regmap = axp20x_dev->regmap;
> >>> + indio_dev->dev.parent = &pdev->dev;
> >>> + indio_dev->dev.of_node = pdev->dev.of_node;
> >>> + indio_dev->modes = INDIO_DIRECT_MODE;
> >>> +
> >>> + info->data = (struct axp_data *)platform_get_device_id(pdev)->driver_data;
> >>> +
> >>> + indio_dev->name = platform_get_device_id(pdev)->name;
> >>> + indio_dev->info = info->data->iio_info;
> >>> + indio_dev->num_channels = info->data->num_channels;
> >>> + indio_dev->channels = info->data->channels;
> >>> +
> >>> + /* Enable the ADCs on IP */
> >>> + regmap_write(info->regmap, AXP20X_ADC_EN1, info->data->adc_en1_mask);
> >>> +
> >>> + if (info->data->adc_en2)
> >>> + /* Enable GPIO0/1 and internal temperature ADCs */
> >>> + regmap_update_bits(info->regmap, AXP20X_ADC_EN2,
> >>> + AXP20X_ADC_EN2_MASK, AXP20X_ADC_EN2_MASK);
> >>> +
> >>> + /* Configure ADCs rate */
> >>> + regmap_update_bits(info->regmap, AXP20X_ADC_RATE, AXP20X_ADC_RATE_MASK,
> >>> + info->data->adc_rate(100));
> >>> +
> >>> + ret = iio_map_array_register(indio_dev, info->data->maps);
> >>> + if (ret < 0) {
> >>> + dev_err(&pdev->dev, "failed to register IIO maps: %d\n", ret);
> >>> + goto fail_map;
> >>> + }
> >>> +
> >>> + ret = iio_device_register(indio_dev);
> >>> + if (ret < 0) {
> >>> + dev_err(&pdev->dev, "could not register the device\n");
> >>> + goto fail_register;
> >>> + }
> >>> +
> >>> + return 0;
> >>> +
> >>> +fail_register:
> >>> + iio_map_array_unregister(indio_dev);
> >>> +
> >>> +fail_map:
> >>> + regmap_write(info->regmap, AXP20X_ADC_EN1, 0);
> >>> +
> >>> + if (info->data->adc_en2)
> >>> + regmap_write(info->regmap, AXP20X_ADC_EN2, 0);
> >>> +
> >>> + return ret;
> >>> +}
> >>> +
> >>> +static int axp20x_remove(struct platform_device *pdev)
> >>> +{
> >>> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> >>> + struct axp20x_adc_iio *info = iio_priv(indio_dev);
> >>> +
> >>> + iio_device_unregister(indio_dev);
> >>> + iio_map_array_unregister(indio_dev);
> >>> +
> >>> + regmap_write(info->regmap, AXP20X_ADC_EN1, 0);
> >>> +
> >>> + if (info->data->adc_en2)
> >>> + regmap_write(info->regmap, AXP20X_ADC_EN2, 0);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static struct platform_driver axp20x_adc_driver = {
> >>> + .driver = {
> >>> + .name = "axp20x-adc",
> >>> + },
> >>> + .id_table = axp20x_adc_id_match,
> >>> + .probe = axp20x_probe,
> >>> + .remove = axp20x_remove,
> >>> +};
> >>> +
> >>> +module_platform_driver(axp20x_adc_driver);
> >>> +
> >>> +MODULE_DESCRIPTION("ADC driver for AXP20X and AXP22X PMICs");
> >>> +MODULE_AUTHOR("Quentin Schulz <quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>");
> >>> +MODULE_LICENSE("GPL");
> >>>
> >>
> >
>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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^ permalink raw reply
* Re: [PATCH v2] mmc: core: add mmc-card hardware reset enable support
From: Linus Walleij @ 2017-04-11 8:17 UTC (permalink / raw)
To: Richard Leitner, Bart Van Assche, Luca Porzio
Cc: Ulf Hansson, Rob Herring, Mark Rutland, Shawn Lin, Adrian Hunter,
Jaehoon Chung, linux-mmc@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Richard Leitner
In-Reply-To: <1491895862-7952-1-git-send-email-richard.leitner@skidata.com>
On Tue, Apr 11, 2017 at 9:31 AM, Richard Leitner
<richard.leitner@skidata.com> wrote:
> Some eMMCs disable their hardware reset line (RST_N) by default. To enable
> it the host must set the corresponding bit in ECSD. An example for such
> a device is the Micron MTFCxGACAANA-4M.
>
> This patch adds a new mmc-card devicetree property to let the host enable
> this feature during card initialization.
>
> Signed-off-by: Richard Leitner <richard.leitner@skidata.com>
Do we know *WHY* these cards disable their hardware reset lines?
If it is just some random over-cautious panic thing we might consider
just force re-enableing it, maybe with a warning in the dmesg, so we can
always reset the card. No DT property needed.
Putting some people who work for eMMC vendors in the To: line so they
can say if they know about this.
Yours,
Linus Walleij
^ permalink raw reply
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