* Re: [PATCH v3 1/2] dt-bindings: iio: stm32-dac: Add support for STM32 DAC
From: Rob Herring @ 2017-04-13 20:22 UTC (permalink / raw)
To: Fabrice Gasnier
Cc: jic23-DgEjT+Ai2ygdnm+yROfE0A, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w,
alexandre.torgue-qxv4g6HH51o, lars-Qo5EllUWu/uELgA04lAiVw,
knaack.h-Mmb7MZpHnFY, pmeerw-jW+XmwGofnusTnJN9+BGXg,
benjamin.gaignard-QSEj5FYQhm4dnm+yROfE0A,
benjamin.gaignard-qxv4g6HH51o
In-Reply-To: <1491839390-2449-2-git-send-email-fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
On Mon, Apr 10, 2017 at 05:49:49PM +0200, Fabrice Gasnier wrote:
> Document STMicroelectronics STM32 DAC (digital-to-analog converter).
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
> ---
> Changes in v2:
> - use 'reg' instead of 'st,dac-channel' property
> - remove alignment from description
> ---
> .../devicetree/bindings/iio/dac/st,stm32-dac.txt | 61 ++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/dac/st,stm32-dac.txt
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
^ permalink raw reply
* Re: [PATCH V2] PM / OPP: Use - instead of @ for DT entries
From: Rob Herring @ 2017-04-13 20:20 UTC (permalink / raw)
To: Viresh Kumar
Cc: Rafael Wysocki, Chanwoo Choi, MyungJoo Ham, Kyungmin Park,
Kukjin Kim, Krzysztof Kozlowski, Javier Martinez Canillas,
Viresh Kumar, Nishanth Menon, Stephen Boyd, Benoît Cousson,
Tony Lindgren, Mark Rutland, Daniel Mack, Haojian Zhuang,
Robert Jarzmik, Maxime Ripard, Chen-Yu Tsai, Masahiro Yamada
In-Reply-To: <70e7c7ee13722ab9c73cb073f88502eaf1ada5f5.1491816050.git.viresh.kumar@linaro.org>
On Mon, Apr 10, 2017 at 02:51:35PM +0530, Viresh Kumar wrote:
> Compiling the DT file with W=1, DTC warns like follows:
>
> Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
> unit name, but no reg property
>
> Fix this by replacing '@' with '-' as the OPP nodes will never have a
> "reg" property.
>
> Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Suggested-by: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> (sunxi)
> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> V2:
> - Added more *-by tags.
> - Included TI DT and example files as well.
>
> .../devicetree/bindings/cpufreq/ti-cpufreq.txt | 20 +++----
> .../devicetree/bindings/devfreq/exynos-bus.txt | 46 +++++++--------
> Documentation/devicetree/bindings/opp/opp.txt | 38 ++++++-------
> arch/arm/boot/dts/am4372.dtsi | 10 ++--
> arch/arm/boot/dts/exynos3250.dtsi | 46 +++++++--------
> arch/arm/boot/dts/exynos4210.dtsi | 32 +++++------
> arch/arm/boot/dts/exynos4412-prime.dtsi | 4 +-
> arch/arm/boot/dts/exynos4412.dtsi | 66 +++++++++++-----------
> arch/arm/boot/dts/exynos5420.dtsi | 40 ++++++-------
> arch/arm/boot/dts/exynos5800.dtsi | 56 +++++++++---------
> arch/arm/boot/dts/pxa25x.dtsi | 8 +--
> arch/arm/boot/dts/pxa27x.dtsi | 14 ++---
> arch/arm/boot/dts/sun8i-a33.dtsi | 8 +--
> arch/arm/boot/dts/uniphier-pro5.dtsi | 32 +++++------
> arch/arm/boot/dts/uniphier-pxs2.dtsi | 16 +++---
> arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi | 48 ++++++++--------
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 50 ++++++++--------
> arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 14 ++---
> arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 32 +++++------
> arch/arm64/boot/dts/zte/zx296718.dtsi | 10 ++--
> 20 files changed, 295 insertions(+), 295 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v2] pinctrl: sh-pfc: r8a7794: add R8A7745 support
From: Sergei Shtylyov @ 2017-04-13 20:19 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Laurent Pinchart, Geert Uytterhoeven,
Linus Walleij, devicetree, linux-renesas-soc, linux-gpio
Cc: Sergei Shtylyov
[-- Attachment #1: pinctrl-sh-pfc-r8a7794-add-R8A7745-support-v2.patch --]
[-- Type: text/plain, Size: 126345 bytes --]
Renesas RZ/G1E (R8A7745) is pin compatible with R-Car E2 (R8A7794),
however it doesn't have several automotive specific peripherals.
Annotate all the items that only exist on the R-Car SoCs and only
supply the pin groups/functions existing on a given SoC (that required
splitting of the AVB function)...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git'
repo plus R8A7794 PFC fix and R8A7743 PFC support patch...
Changes in version 2:
- fixed indentation to use tabs instead of spaces;
- updated the PFC bindings.
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1
drivers/pinctrl/sh-pfc/Kconfig | 5
drivers/pinctrl/sh-pfc/Makefile | 1
drivers/pinctrl/sh-pfc/core.c | 6
drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 1970 +++++-----
drivers/pinctrl/sh-pfc/sh_pfc.h | 1
6 files changed, 1140 insertions(+), 844 deletions(-)
Index: linux-pinctrl/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
===================================================================
--- linux-pinctrl.orig/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ linux-pinctrl/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -14,6 +14,7 @@ Required Properties:
- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
+ - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/Kconfig
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/Kconfig
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/Kconfig
@@ -39,6 +39,11 @@ config PINCTRL_PFC_R8A7743
depends on ARCH_R8A7743
select PINCTRL_SH_PFC
+config PINCTRL_PFC_R8A7745
+ def_bool y
+ depends on ARCH_R8A7745
+ select PINCTRL_SH_PFC
+
config PINCTRL_PFC_R8A7778
def_bool y
depends on ARCH_R8A7778
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/Makefile
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/Makefile
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-e
obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o
obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/core.c
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/core.c
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/core.c
@@ -491,6 +491,12 @@ static const struct of_device_id sh_pfc_
.data = &r8a7743_pinmux_info,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7745
+ {
+ .compatible = "renesas,pfc-r8a7745",
+ .data = &r8a7745_pinmux_info,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7778
{
.compatible = "renesas,pfc-r8a7778",
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -1,9 +1,9 @@
/*
- * r8a7794 processor support - PFC hardware block.
+ * r8a7794/r8a7745 processor support - PFC hardware block.
*
* Copyright (C) 2014-2015 Renesas Electronics Corporation
* Copyright (C) 2015 Renesas Solutions Corp.
- * Copyright (C) 2015-2016 Cogent Embedded, Inc., <source@cogentembedded.com>
+ * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
@@ -110,10 +110,12 @@ enum {
FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6,
FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13,
- FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD,
- FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0,
- FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK,
- FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
+ FN_SCIFA1_SCK, FN_TANS1 /* R8A7794 only */, FN_PWM2_C, FN_TCLK2_B,
+ FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B,
+ FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B,
+ FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD,
+ FN_A3, FN_SCIFB0_SCK, FN_A4, FN_SCIFB0_TXD,
+ FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
/* IPSR2 */
@@ -123,77 +125,139 @@ enum {
FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2,
FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16,
- FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C,
- FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
- FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E,
- FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4,
- FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1,
+ FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN /* R8A7794 only */,
+ FN_VSP /* R8A7794 only */, FN_CAN_CLK_C, FN_TPUTO2_B,
+ FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
+ FN_AVB_AVTP_CAPTURE_B /* R8A7794 only */,
+ FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
+ FN_AVB_AVTP_MATCH_B /* R8A7794 only */,
+ FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, FN_MOUT0 /* R8A7794 only */,
+ FN_A20, FN_SPCLK, FN_MOUT1 /* R8A7794 only */,
/* IPSR3 */
- FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5,
- FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3,
- FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8,
+ FN_A21, FN_MOSI_IO0, FN_MOUT2 /* R8A7794 only */,
+ FN_A22, FN_MISO_IO1, FN_MOUT5 /* R8A7794 only */, FN_ATADIR1_N,
+ FN_A23, FN_IO2, FN_MOUT6 /* R8A7794 only */, FN_ATAWR1_N,
+ FN_A24, FN_IO3, FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N,
+ FN_CS0_N, FN_VI1_DATA8,
FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N,
- FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0,
- FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD,
- FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
- FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N,
- FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK,
- FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E,
- FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
- FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B,
+ FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
+ FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B /* R8A7794 only */,
+ FN_RIF0_SYNC /* R8A7794 only */, FN_TPUTO3, FN_SCIFB2_TXD,
+ FN_SDATA_B /* R8A7794 only */,
+ FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C,
+ FN_TS_SCK_B /* R8A7794 only */, FN_RIF0_CLK /* R8A7794 only */,
+ FN_BPFCLK /* R8A7794 only */, FN_SCIFB2_SCK,
+ FN_MDATA_B /* R8A7794 only */,
+ FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E,
+ FN_TS_SDEN_B /* R8A7794 only */, FN_RIF0_D0 /* R8A7794 only */,
+ FN_FMCLK /* R8A7794 only */, FN_SCIFB2_CTS_N,
+ FN_SCKZ_B /* R8A7794 only */,
+ FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E,
+ FN_TS_SPSYNC_B /* R8A7794 only */, FN_RIF0_D1 /* R8A7794 only */,
+ FN_FMIN /* R8A7794 only */, FN_SCIFB2_RTS_N,
+ FN_STM_N_B /* R8A7794 only */,
+ FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
+ FN_MTS_N_B /* R8A7794 only */,
FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N,
/* IPSR4 */
- FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0,
- FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0,
- FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1,
- FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19,
- FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5,
- FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6,
- FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8,
- FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9,
- FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10,
- FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4,
- FN_LCDOUT12, FN_CC50_STATE12,
+ FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0 /* R8A7794 only */,
+ FN_DU0_DR0, FN_LCDOUT16 /* R8A7794 only */, FN_SCIF5_RXD_C,
+ FN_I2C2_SCL_D, FN_CC50_STATE0 /* R8A7794 only */,
+ FN_DU0_DR1, FN_LCDOUT17 /* R8A7794 only */, FN_SCIF5_TXD_C,
+ FN_I2C2_SDA_D, FN_CC50_STATE1 /* R8A7794 only */,
+ FN_DU0_DR2, FN_LCDOUT18 /* R8A7794 only */,
+ FN_CC50_STATE2 /* R8A7794 only */,
+ FN_DU0_DR3, FN_LCDOUT19 /* R8A7794 only */,
+ FN_CC50_STATE3 /* R8A7794 only */,
+ FN_DU0_DR4, FN_LCDOUT20 /* R8A7794 only */,
+ FN_CC50_STATE4 /* R8A7794 only */,
+ FN_DU0_DR5, FN_LCDOUT21 /* R8A7794 only */,
+ FN_CC50_STATE5 /* R8A7794 only */,
+ FN_DU0_DR6, FN_LCDOUT22 /* R8A7794 only */,
+ FN_CC50_STATE6 /* R8A7794 only */,
+ FN_DU0_DR7, FN_LCDOUT23 /* R8A7794 only */,
+ FN_CC50_STATE7 /* R8A7794 only */,
+ FN_DU0_DG0, FN_LCDOUT8 /* R8A7794 only */, FN_SCIFA0_RXD_C,
+ FN_I2C3_SCL_D, FN_CC50_STATE8 /* R8A7794 only */,
+ FN_DU0_DG1, FN_LCDOUT9 /* R8A7794 only */, FN_SCIFA0_TXD_C,
+ FN_I2C3_SDA_D, FN_CC50_STATE9 /* R8A7794 only */,
+ FN_DU0_DG2, FN_LCDOUT10 /* R8A7794 only */,
+ FN_CC50_STATE10 /* R8A7794 only */,
+ FN_DU0_DG3, FN_LCDOUT11 /* R8A7794 only */,
+ FN_CC50_STATE11 /* R8A7794 only */,
+ FN_DU0_DG4, FN_LCDOUT12 /* R8A7794 only */,
+ FN_CC50_STATE12 /* R8A7794 only */,
/* IPSR5 */
- FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14,
- FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0,
- FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
- FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
- FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18,
- FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4,
- FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6,
- FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23,
- FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0,
- FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
- FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27,
+ FN_DU0_DG5, FN_LCDOUT13 /* R8A7794 only */,
+ FN_CC50_STATE13 /* R8A7794 only */,
+ FN_DU0_DG6, FN_LCDOUT14 /* R8A7794 only */,
+ FN_CC50_STATE14 /* R8A7794 only */,
+ FN_DU0_DG7, FN_LCDOUT15 /* R8A7794 only */,
+ FN_CC50_STATE15 /* R8A7794 only */,
+ FN_DU0_DB0, FN_LCDOUT0 /* R8A7794 only */, FN_SCIFA4_RXD_C,
+ FN_I2C4_SCL_D, FN_CAN0_RX_C, FN_CC50_STATE16 /* R8A7794 only */,
+ FN_DU0_DB1, FN_LCDOUT1 /* R8A7794 only */, FN_SCIFA4_TXD_C,
+ FN_I2C4_SDA_D, FN_CAN0_TX_C, FN_CC50_STATE17 /* R8A7794 only */,
+ FN_DU0_DB2, FN_LCDOUT2 /* R8A7794 only */,
+ FN_CC50_STATE18 /* R8A7794 only */,
+ FN_DU0_DB3, FN_LCDOUT3 /* R8A7794 only */,
+ FN_CC50_STATE19 /* R8A7794 only */,
+ FN_DU0_DB4, FN_LCDOUT4 /* R8A7794 only */,
+ FN_CC50_STATE20 /* R8A7794 only */,
+ FN_DU0_DB5, FN_LCDOUT5 /* R8A7794 only */,
+ FN_CC50_STATE21 /* R8A7794 only */,
+ FN_DU0_DB6, FN_LCDOUT6 /* R8A7794 only */,
+ FN_CC50_STATE22 /* R8A7794 only */,
+ FN_DU0_DB7, FN_LCDOUT7 /* R8A7794 only */,
+ FN_CC50_STATE23 /* R8A7794 only */,
+ FN_DU0_DOTCLKIN, FN_QSTVA_QVS /* R8A7794 only */,
+ FN_CC50_STATE24 /* R8A7794 only */,
+ FN_DU0_DOTCLKOUT0, FN_QCLK /* R8A7794 only */,
+ FN_CC50_STATE25 /* R8A7794 only */,
+ FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE /* R8A7794 only */,
+ FN_CC50_STATE26 /* R8A7794 only */,
+ FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS /* R8A7794 only */,
+ FN_CC50_STATE27 /* R8A7794 only */,
/* IPSR6 */
- FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
- FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
- FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
- FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
+ FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE /* R8A7794 only */,
+ FN_CC50_STATE28 /* R8A7794 only */,
+ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE /* R8A7794 only */,
+ FN_CC50_STATE29 /* R8A7794 only */,
+ FN_DU0_DISP, FN_QPOLA /* R8A7794 only */,
+ FN_CC50_STATE30 /* R8A7794 only */,
+ FN_DU0_CDE, FN_QPOLB /* R8A7794 only */,
+ FN_CC50_STATE31 /* R8A7794 only */,
+ FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
- FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
- FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
- FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
- FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
+ FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
+ FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C,
+ FN_IETX_C /* R8A7794 only */, FN_AVB_RXD7,
+ FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C,
+ FN_IECLK_C /* R8A7794 only */, FN_AVB_RX_ER,
+ FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C,
+ FN_IERX_C /* R8A7794 only */, FN_AVB_COL, FN_VI0_VSYNC_N,
FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
- FN_ADIDATA, FN_AD_DI,
+ FN_ADIDATA /* R8A7794 only */, FN_AD_DI /* R8A7794 only */,
/* IPSR7 */
FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
- FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
- FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
- FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
+ FN_ADICS_SAMP /* R8A7794 only */, FN_AD_DO /* R8A7794 only */,
+ FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
+ FN_ADICLK /* R8A7794 only */, FN_AD_CLK /* R8A7794 only */,
+ FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
+ FN_ADICHS0 /* R8A7794 only */, FN_AD_NCS_N /* R8A7794 only */,
FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
- FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
- FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
+ FN_ADICHS1 /* R8A7794 only */,
+ FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
+ FN_ADICHS2 /* R8A7794 only */,
+ FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
@@ -213,127 +277,188 @@ enum {
FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
- FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
- FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
- FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
- FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
+ FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B /* R8A7794 only */,
+ FN_TS_SDATA_D /* R8A7794 only */, FN_TPUTO1_B,
+ FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
+ FN_RIF1_CLK_B /* R8A7794 only */, FN_TS_SCK_D /* R8A7794 only */,
+ FN_BPFCLK_C /* R8A7794 only */,
+ FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
+ FN_RIF1_D0_B /* R8A7794 only */, FN_TS_SDEN_D /* R8A7794 only */,
+ FN_FMCLK_C /* R8A7794 only */, FN_RDS_CLK /* R8A7794 only */,
/* IPSR9 */
- FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B,
- FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0,
- FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC,
- FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1,
- FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B,
- FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
- FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL,
- FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
- FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
- FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK,
- FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32,
- FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
- FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2,
- FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34,
+ FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
+ FN_RIF1_D1_B /* R8A7794 only */, FN_TS_SPSYNC_D /* R8A7794 only */,
+ FN_FMIN_C /* R8A7794 only */, FN_RDS_DATA /* R8A7794 only */,
+ FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA /* R8A7794 only */, FN_DU1_DR4,
+ FN_RIF1_SYNC /* R8A7794 only */, FN_TPUTO1_C,
+ FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK /* R8A7794 only */, FN_DU1_DR5,
+ FN_RIF1_CLK /* R8A7794 only */, FN_BPFCLK_B /* R8A7794 only */,
+ FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN /* R8A7794 only */,
+ FN_DU1_DR6, FN_RIF1_D0 /* R8A7794 only */,
+ FN_FMCLK_B /* R8A7794 only */, FN_RDS_CLK_B /* R8A7794 only */,
+ FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC /* R8A7794 only */,
+ FN_DU1_DR7, FN_RIF1_D1 /* R8A7794 only */, FN_FMIN_B /* R8A7794 only */,
+ FN_RDS_DATA_B /* R8A7794 only */,
+ FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX,
+ FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, FN_HSCIF1_HSCK, FN_PWM2,
+ FN_IETX /* R8A7794 only */, FN_DU1_DG2, FN_REMOCON_B /* R8A7794 only */,
+ FN_SPEEDIN_B /* R8A7794 only */, FN_VSP_B /* R8A7794 only */,
+ FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK /* R8A7794 only */,
+ FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER /* R8A7794 only */,
+ FN_CC50_STATE32 /* R8A7794 only */,
+ FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX /* R8A7794 only */,
+ FN_DU1_DG4, FN_SSI_WS1_B, FN_CAN_STEP0 /* R8A7794 only */,
+ FN_CC50_STATE33 /* R8A7794 only */,
+ FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
+ FN_CAN_TXCLK /* R8A7794 only */, FN_CC50_STATE34 /* R8A7794 only */,
/* IPSR10 */
- FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0,
- FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
- FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL,
- FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2,
- FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
- FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1,
- FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4,
- FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
- FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
- FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
- FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD,
- FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
- FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6,
- FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA,
- FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9,
- FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
+ FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
+ FN_CAN_DEBUGOUT0 /* R8A7794 only */, FN_CC50_STATE35 /* R8A7794 only */,
+ FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
+ FN_CAN_DEBUGOUT1 /* R8A7794 only */, FN_CC50_STATE36 /* R8A7794 only */,
+ FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
+ FN_USB0_EXTLP /* R8A7794 only */, FN_CAN_DEBUGOUT2 /* R8A7794 only */,
+ FN_CC50_STATE37 /* R8A7794 only */,
+ FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
+ FN_USB0_OVC1 /* R8A7794 only */, FN_CAN_DEBUGOUT3 /* R8A7794 only */,
+ FN_CC50_STATE38 /* R8A7794 only */,
+ FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
+ FN_USB0_IDIN /* R8A7794 only */, FN_CAN_DEBUGOUT4 /* R8A7794 only */,
+ FN_CC50_STATE39 /* R8A7794 only */, FN_SCIF3_SCK, FN_IRQ2,
+ FN_BPFCLK_D /* R8A7794 only */, FN_DU1_DB3, FN_SSI_SDATA9_B,
+ FN_TANS2 /* R8A7794 only */, FN_CAN_DEBUGOUT5 /* R8A7794 only */,
+ FN_CC50_OSCOUT /* R8A7794 only */,
+ FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D /* R8A7794 only */, FN_DU1_DB4,
+ FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6 /* R8A7794 only */,
+ FN_RDS_CLK_C /* R8A7794 only */,
+ FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D /* R8A7794 only */, FN_DU1_DB5,
+ FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7 /* R8A7794 only */,
+ FN_RDS_DATA_C /* R8A7794 only */,
+ FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
+ FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8 /* R8A7794 only */,
+ FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
+ FN_CAN_DEBUGOUT9 /* R8A7794 only */,
+ FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
+ FN_CAN_DEBUGOUT10 /* R8A7794 only */,
/* IPSR11 */
FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
- FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
- FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
- FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
- FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
- FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
- FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
- FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
- FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
- FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
- FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
- FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
- FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
- FN_ADICLK_B, FN_AD_CLK_B,
+ FN_CAN_DEBUGOUT11 /* R8A7794 only */,
+ FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
+ FN_CAN_DEBUGOUT12 /* R8A7794 only */, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
+ FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13 /* R8A7794 only */,
+ FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
+ FN_CAN_DEBUGOUT14 /* R8A7794 only */,
+ FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
+ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15 /* R8A7794 only */,
+ FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
+ FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
+ FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
+ FN_PCMOE_N /* R8A7794 only */,
+ FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D,
+ FN_ADIDATA_B /* R8A7794 only */, FN_AD_DI_B /* R8A7794 only */,
+ FN_PCMWE_N /* R8A7794 only */,
+ FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
+ FN_ADICS_SAMP_B /* R8A7794 only */, FN_AD_DO_B /* R8A7794 only */,
+ FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
+ FN_ADICLK_B /* R8A7794 only */, FN_AD_CLK_B /* R8A7794 only */,
/* IPSR12 */
- FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
- FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B,
- FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3,
- FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C,
- FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4,
- FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT,
- FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B,
- FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1,
- FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
- FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B,
- FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,
- FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1,
- FN_ATAWR0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
- FN_MDATA, FN_ATAG0_N, FN_ETH_RXD1_B,
+ FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C,
+ FN_ADICHS0_B /* R8A7794 only */, FN_AD_NCS_N_B /* R8A7794 only */,
+ FN_DREQ1_N_B,
+ FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C,
+ FN_ADICHS1_B /* R8A7794 only */, FN_CAN1_RX_C, FN_DACK1_B,
+ FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C,
+ FN_ADICHS2_B /* R8A7794 only */, FN_CAN1_TX_C, FN_DREQ2_N,
+ FN_SSI_SCK4, FN_MLB_CLK /* R8A7794 only */,
+ FN_IETX_B /* R8A7794 only */, FN_IRD_TX /* R8A7794 only */,
+ FN_SSI_WS4, FN_MLB_SIG /* R8A7794 only */,
+ FN_IECLK_B /* R8A7794 only */, FN_IRD_RX /* R8A7794 only */,
+ FN_SSI_SDATA4, FN_MLB_DAT /* R8A7794 only */,
+ FN_IERX_B /* R8A7794 only */, FN_IRD_SCK /* R8A7794 only */,
+ FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
+ FN_REMOCON /* R8A7794 only */, FN_DACK2, FN_ETH_MDIO_B,
+ FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
+ FN_AVB_AVTP_CAPTURE /* R8A7794 only */, FN_ETH_CRS_DV_B,
+ FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
+ FN_AVB_AVTP_MATCH /* R8A7794 only */, FN_ETH_RX_ER_B,
+ FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA /* R8A7794 only */,
+ FN_VI1_DATA1, FN_ATAWR0_N, FN_ETH_RXD0_B,
+ FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA /* R8A7794 only */,
+ FN_ATAG0_N, FN_ETH_RXD1_B,
/* IPSR13 */
- FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ,
- FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B,
- FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B,
- FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N,
- FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E,
- FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9,
- FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N,
- FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D,
- FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B,
+ FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
+ FN_SCKZ /* R8A7794 only */, FN_ATACS00_N, FN_ETH_LINK_B,
+ FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
+ FN_STM_N /* R8A7794 only */, FN_ATACS10_N, FN_ETH_REFCLK_B,
+ FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
+ FN_MTS_N /* R8A7794 only */, FN_EX_WAIT1, FN_ETH_TXD1_B,
+ FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
+ FN_ETH_TX_EN_B,
+ FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
+ FN_ATADIR0_N, FN_ETH_MAGIC_B,
+ FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
+ FN_TS_SDATA_C /* R8A7794 only */, FN_RIF0_SYNC_B /* R8A7794 only */,
+ FN_ETH_TXD0_B,
FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
- FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC,
- FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C,
- FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B,
- FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B,
- FN_FMIN_E, FN_RDS_DATA_D,
+ FN_TS_SCK_C /* R8A7794 only */, FN_RIF0_CLK_B /* R8A7794 only */,
+ FN_BPFCLK_E /* R8A7794 only */, FN_ETH_MDC_B,
+ FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
+ FN_TS_SDEN_C /* R8A7794 only */, FN_RIF0_D0_B /* R8A7794 only */,
+ FN_FMCLK_E /* R8A7794 only */, FN_RDS_CLK_D /* R8A7794 only */,
+ FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
+ FN_TS_SPSYNC_C /* R8A7794 only */, FN_RIF0_D1_B /* R8A7794 only */,
+ FN_FMIN_E /* R8A7794 only */, FN_RDS_DATA_D /* R8A7794 only */,
/* MOD_SEL */
FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
- FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
- FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
- FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
- FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
- FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
- FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
+ /* R8A7794 only */ FN_SEL_ADI_0, FN_SEL_ADI_1,
+ FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
+ /* R8A7794 only */ FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2,
+ FN_SEL_DARC_3, FN_SEL_DARC_4,
+ /* R8A7794 only */ FN_SEL_DR0_0, FN_SEL_DR0_1,
+ /* R8A7794 only */ FN_SEL_DR1_0, FN_SEL_DR1_1,
+ /* R8A7794 only */ FN_SEL_DR2_0, FN_SEL_DR2_1,
+ /* R8A7794 only */ FN_SEL_DR3_0, FN_SEL_DR3_1,
+ FN_SEL_ETH_0, FN_SEL_ETH_1,
+ /* R8A7794 only */ FN_SEL_FSN_0, FN_SEL_FSN_1,
+ FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
- FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
+ FN_SEL_IIC00_2, FN_SEL_IIC00_3,
+ /* R8A7794 only */ FN_SEL_AVB_0, FN_SEL_AVB_1,
/* MOD_SEL2 */
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
- FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
- FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
- FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
- FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
- FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
- FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
- FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
- FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
- FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
- FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
- FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
- FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
- FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
- FN_SEL_RDS_2, FN_SEL_RDS_3,
+ /* R8A7794 only */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+ FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
+ FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
+ FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
+ /* R8A7794 only */ FN_SEL_RCN_0, FN_SEL_RCN_1,
+ /* R8A7794 only */ FN_SEL_RSP_0, FN_SEL_RSP_1,
+ FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
+ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+ FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
+ FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
+ FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
+ /* R8A7794 only */ FN_SEL_SPDM_0, FN_SEL_SPDM_1,
+ FN_SEL_TMU_0, FN_SEL_TMU_1,
+ /* R8A7794 only */ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2,
+ FN_SEL_TSIF0_3,
+ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+ FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
+ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+ /* R8A7794 only */ FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+ FN_SEL_RDS_3,
/* MOD_SEL3 */
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
@@ -378,7 +503,8 @@ enum {
HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
- D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK,
+ D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK /* R8A7794 only */, PWM2_C_MARK,
+ TCLK2_B_MARK,
D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK,
IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK,
SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK,
@@ -393,89 +519,145 @@ enum {
A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK,
HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK,
HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK,
- HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK,
- TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK,
- CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK,
- SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK,
- MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK,
- SPCLK_MARK, MOUT1_MARK,
+ HSCIF0_HSCK_B_MARK, SPEEDIN_MARK /* R8A7794 only */,
+ VSP_MARK /* R8A7794 only */, CAN_CLK_C_MARK, TPUTO2_B_MARK,
+ A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
+ AVB_AVTP_CAPTURE_B_MARK /* R8A7794 only */,
+ A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
+ AVB_AVTP_MATCH_B_MARK /* R8A7794 only */,
+ A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
+ MOUT0_MARK /* R8A7794 only */,
+ A20_MARK, SPCLK_MARK, MOUT1_MARK /* R8A7794 only */,
/* IPSR3 */
- A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK,
- MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK,
- ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK,
- ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK,
- VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK,
- TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK,
- PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK,
- TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK,
- SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK,
- BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK,
- SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK,
- FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK,
- SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK,
- FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK,
- PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK,
- ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK,
+ A21_MARK, MOSI_IO0_MARK, MOUT2_MARK /* R8A7794 only */,
+ A22_MARK, MISO_IO1_MARK, MOUT5_MARK /* R8A7794 only */, ATADIR1_N_MARK,
+ A23_MARK, IO2_MARK, MOUT6_MARK /* R8A7794 only */, ATAWR1_N_MARK,
+ A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK, ATARD1_N_MARK,
+ CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK, VI1_DATA9_MARK,
+ EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK, TPUTO3_B_MARK,
+ SCIFB2_RXD_MARK, VI1_DATA11_MARK,
+ EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK,
+ TS_SDATA_B_MARK /* R8A7794 only */, RIF0_SYNC_MARK /* R8A7794 only */,
+ TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK /* R8A7794 only */,
+ EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK,
+ TS_SCK_B_MARK /* R8A7794 only */, RIF0_CLK_MARK /* R8A7794 only */,
+ BPFCLK_MARK /* R8A7794 only */, SCIFB2_SCK_MARK,
+ MDATA_B_MARK /* R8A7794 only */,
+ EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK,
+ TS_SDEN_B_MARK /* R8A7794 only */, RIF0_D0_MARK /* R8A7794 only */,
+ FMCLK_MARK /* R8A7794 only */, SCIFB2_CTS_N_MARK,
+ SCKZ_B_MARK /* R8A7794 only */,
+ EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK,
+ TS_SPSYNC_B_MARK /* R8A7794 only */, RIF0_D1_MARK /* R8A7794 only */,
+ FMIN_MARK /* R8A7794 only */, SCIFB2_RTS_N_MARK,
+ STM_N_B_MARK /* R8A7794 only */, BS_N_MARK, DRACK0_MARK, PWM1_C_MARK,
+ TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK /* R8A7794 only */,
+ RD_N_MARK, ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK,
/* IPSR4 */
- EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK,
- DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
- CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK,
- I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK,
- CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK,
- DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK,
- LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK,
- CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK,
- DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
- CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK,
- I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK,
- CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK,
- DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK,
+ EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
+ PWMFSW0_MARK /* R8A7794 only */,
+ DU0_DR0_MARK, LCDOUT16_MARK /* R8A7794 only */, SCIF5_RXD_C_MARK,
+ I2C2_SCL_D_MARK, CC50_STATE0_MARK /* R8A7794 only */,
+ DU0_DR1_MARK, LCDOUT17_MARK /* R8A7794 only */, SCIF5_TXD_C_MARK,
+ I2C2_SDA_D_MARK, CC50_STATE1_MARK /* R8A7794 only */,
+ DU0_DR2_MARK, LCDOUT18_MARK /* R8A7794 only */,
+ CC50_STATE2_MARK /* R8A7794 only */,
+ DU0_DR3_MARK, LCDOUT19_MARK /* R8A7794 only */,
+ CC50_STATE3_MARK /* R8A7794 only */,
+ DU0_DR4_MARK, LCDOUT20_MARK /* R8A7794 only */,
+ CC50_STATE4_MARK /* R8A7794 only */,
+ DU0_DR5_MARK, LCDOUT21_MARK /* R8A7794 only */,
+ CC50_STATE5_MARK /* R8A7794 only */,
+ DU0_DR6_MARK, LCDOUT22_MARK /* R8A7794 only */,
+ CC50_STATE6_MARK /* R8A7794 only */,
+ DU0_DR7_MARK, LCDOUT23_MARK /* R8A7794 only */,
+ CC50_STATE7_MARK /* R8A7794 only */,
+ DU0_DG0_MARK, LCDOUT8_MARK /* R8A7794 only */, SCIFA0_RXD_C_MARK,
+ I2C3_SCL_D_MARK, CC50_STATE8_MARK /* R8A7794 only */,
+ DU0_DG1_MARK, LCDOUT9_MARK /* R8A7794 only */, SCIFA0_TXD_C_MARK,
+ I2C3_SDA_D_MARK, CC50_STATE9_MARK /* R8A7794 only */,
+ DU0_DG2_MARK, LCDOUT10_MARK /* R8A7794 only */,
+ CC50_STATE10_MARK /* R8A7794 only */,
+ DU0_DG3_MARK, LCDOUT11_MARK /* R8A7794 only */,
+ CC50_STATE11_MARK /* R8A7794 only */,
+ DU0_DG4_MARK, LCDOUT12_MARK /* R8A7794 only */,
+ CC50_STATE12_MARK /* R8A7794 only */,
/* IPSR5 */
- DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK,
- LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK,
- CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK,
- I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK,
- LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK,
- CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK,
- DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK,
- LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK,
- CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK,
- DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK,
- QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK,
- QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
- CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
- CC50_STATE27_MARK,
+ DU0_DG5_MARK, LCDOUT13_MARK /* R8A7794 only */,
+ CC50_STATE13_MARK /* R8A7794 only */,
+ DU0_DG6_MARK, LCDOUT14_MARK /* R8A7794 only */,
+ CC50_STATE14_MARK /* R8A7794 only */,
+ DU0_DG7_MARK, LCDOUT15_MARK /* R8A7794 only */,
+ CC50_STATE15_MARK /* R8A7794 only */,
+ DU0_DB0_MARK, LCDOUT0_MARK /* R8A7794 only */, SCIFA4_RXD_C_MARK,
+ I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK /* R8A7794 only */,
+ DU0_DB1_MARK, LCDOUT1_MARK /* R8A7794 only */, SCIFA4_TXD_C_MARK,
+ I2C4_SDA_D_MARK, CAN0_TX_C_MARK, CC50_STATE17_MARK /* R8A7794 only */,
+ DU0_DB2_MARK, LCDOUT2_MARK /* R8A7794 only */,
+ CC50_STATE18_MARK /* R8A7794 only */,
+ DU0_DB3_MARK, LCDOUT3_MARK /* R8A7794 only */,
+ CC50_STATE19_MARK /* R8A7794 only */,
+ DU0_DB4_MARK, LCDOUT4_MARK /* R8A7794 only */,
+ CC50_STATE20_MARK /* R8A7794 only */,
+ DU0_DB5_MARK, LCDOUT5_MARK /* R8A7794 only */,
+ CC50_STATE21_MARK /* R8A7794 only */,
+ DU0_DB6_MARK, LCDOUT6_MARK /* R8A7794 only */,
+ CC50_STATE22_MARK /* R8A7794 only */,
+ DU0_DB7_MARK, LCDOUT7_MARK /* R8A7794 only */,
+ CC50_STATE23_MARK /* R8A7794 only */,
+ DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK /* R8A7794 only */,
+ CC50_STATE24_MARK /* R8A7794 only */,
+ DU0_DOTCLKOUT0_MARK, QCLK_MARK /* R8A7794 only */,
+ CC50_STATE25_MARK /* R8A7794 only */,
+ DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK /* R8A7794 only */,
+ CC50_STATE26_MARK /* R8A7794 only */,
+ DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK /* R8A7794 only */,
+ CC50_STATE27_MARK /* R8A7794 only */,
/* IPSR6 */
- DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
- DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
- DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
- CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
+ DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK /* R8A7794 only */,
+ CC50_STATE28_MARK /* R8A7794 only */,
+ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK /* R8A7794 only */,
+ CC50_STATE29_MARK /* R8A7794 only */,
+ DU0_DISP_MARK, QPOLA_MARK /* R8A7794 only */,
+ CC50_STATE30_MARK /* R8A7794 only */,
+ DU0_CDE_MARK, QPOLB_MARK /* R8A7794 only */,
+ CC50_STATE31_MARK /* R8A7794 only */,
+ VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
- AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
- I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
- VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
- AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
- IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
- I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
- VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
- ADIDATA_MARK, AD_DI_MARK,
+ AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
+ VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK,
+ IETX_C_MARK /* R8A7794 only */, AVB_RXD7_MARK,
+ VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK,
+ IECLK_C_MARK /* R8A7794 only */, AVB_RX_ER_MARK,
+ VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
+ IERX_C_MARK /* R8A7794 only */, AVB_COL_MARK,
+ VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
+ AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
+ ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK,
+ AVB_TX_CLK_MARK, ADIDATA_MARK /* R8A7794 only */,
+ AD_DI_MARK /* R8A7794 only */,
/* IPSR7 */
ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
- AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
- MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
- AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
- CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
+ AVB_TXD0_MARK, ADICS_SAMP_MARK /* R8A7794 only */,
+ AD_DO_MARK /* R8A7794 only */,
+ ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
+ AVB_TXD1_MARK, ADICLK_MARK /* R8A7794 only */,
+ AD_CLK_MARK /* R8A7794 only */,
+ ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
+ AVB_TXD2_MARK, ADICHS0_MARK /* R8A7794 only */,
+ AD_NCS_N_MARK /* R8A7794 only */,
ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
- AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
- MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
+ AVB_TXD3_MARK, ADICHS1_MARK /* R8A7794 only */,
+ ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
+ AVB_TXD4_MARK, ADICHS2_MARK /* R8A7794 only */,
ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
@@ -499,102 +681,158 @@ enum {
AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
- DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
- I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
- TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
- I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
- FMCLK_C_MARK, RDS_CLK_MARK,
+ DU1_DR0_MARK, RIF1_SYNC_B_MARK /* R8A7794 only */,
+ TS_SDATA_D_MARK /* R8A7794 only */, TPUTO1_B_MARK,
+ I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK,
+ RIF1_CLK_B_MARK /* R8A7794 only */, TS_SCK_D_MARK /* R8A7794 only */,
+ BPFCLK_C_MARK /* R8A7794 only */,
+ MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
+ RIF1_D0_B_MARK /* R8A7794 only */, TS_SDEN_D_MARK /* R8A7794 only */,
+ FMCLK_C_MARK /* R8A7794 only */, RDS_CLK_MARK /* R8A7794 only */,
/* IPSR9 */
MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
- RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK,
- MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK,
- TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK,
- RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK,
- TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK,
- MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
- RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK,
- I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK,
- I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK,
- PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK,
- VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK,
- DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK,
- CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK,
- DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK,
+ RIF1_D1_B_MARK /* R8A7794 only */, TS_SPSYNC_D_MARK /* R8A7794 only */,
+ FMIN_C_MARK /* R8A7794 only */, RDS_DATA_MARK /* R8A7794 only */,
+ MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK /* R8A7794 only */,
+ DU1_DR4_MARK, RIF1_SYNC_MARK /* R8A7794 only */, TPUTO1_C_MARK,
+ MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK /* R8A7794 only */,
+ DU1_DR5_MARK, RIF1_CLK_MARK /* R8A7794 only */,
+ BPFCLK_B_MARK /* R8A7794 only */,
+ MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK /* R8A7794 only */,
+ DU1_DR6_MARK, RIF1_D0_MARK /* R8A7794 only */,
+ FMCLK_B_MARK /* R8A7794 only */, RDS_CLK_B_MARK /* R8A7794 only */,
+ MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK /* R8A7794 only */,
+ DU1_DR7_MARK, RIF1_D1_MARK /* R8A7794 only */,
+ FMIN_B_MARK /* R8A7794 only */, RDS_DATA_B_MARK /* R8A7794 only */,
+ HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
+ HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
+ HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK /* R8A7794 only */, DU1_DG2_MARK,
+ REMOCON_B_MARK /* R8A7794 only */, SPEEDIN_B_MARK /* R8A7794 only */,
+ VSP_B_MARK /* R8A7794 only */,
+ HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK /* R8A7794 only */,
+ DU1_DG3_MARK, SSI_SCK1_B_MARK,
+ CAN_DEBUG_HW_TRIGGER_MARK /* R8A7794 only */,
+ CC50_STATE32_MARK /* R8A7794 only */,
+ HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK /* R8A7794 only */,
+ DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK /* R8A7794 only */,
+ CC50_STATE33_MARK /* R8A7794 only */,
SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
- CAN_TXCLK_MARK, CC50_STATE34_MARK,
+ CAN_TXCLK_MARK /* R8A7794 only */, CC50_STATE34_MARK /* R8A7794 only */,
/* IPSR10 */
SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
- CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK,
- DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK,
+ CAN_DEBUGOUT0_MARK /* R8A7794 only */,
+ CC50_STATE35_MARK /* R8A7794 only */,
+ SCIF1_TXD_MARK, IIC0_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
+ CAN_DEBUGOUT1_MARK /* R8A7794 only */,
+ CC50_STATE36_MARK /* R8A7794 only */,
SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
- USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK,
- IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK,
- CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK,
- DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK,
- CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK,
- DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK,
- CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK,
- DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK,
- RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK,
- DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK,
- RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK,
- AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK,
- SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK,
- SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK,
+ USB0_EXTLP_MARK /* R8A7794 only */,
+ CAN_DEBUGOUT2_MARK /* R8A7794 only */,
+ CC50_STATE37_MARK /* R8A7794 only */,
+ SCIF2_TXD_MARK, IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
+ USB0_OVC1_MARK /* R8A7794 only */,
+ CAN_DEBUGOUT3_MARK /* R8A7794 only */,
+ CC50_STATE38_MARK /* R8A7794 only */,
+ SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
+ USB0_IDIN_MARK /* R8A7794 only */,
+ CAN_DEBUGOUT4_MARK /* R8A7794 only */,
+ CC50_STATE39_MARK /* R8A7794 only */,
+ SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK /* R8A7794 only */,
+ DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK /* R8A7794 only */,
+ CAN_DEBUGOUT5_MARK /* R8A7794 only */,
+ CC50_OSCOUT_MARK /* R8A7794 only */,
+ SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK /* R8A7794 only */,
+ DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
+ CAN_DEBUGOUT6_MARK /* R8A7794 only */,
+ RDS_CLK_C_MARK /* R8A7794 only */,
+ SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK /* R8A7794 only */,
+ DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
+ CAN_DEBUGOUT7_MARK /* R8A7794 only */,
+ RDS_DATA_C_MARK /* R8A7794 only */,
+ I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
+ SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK /* R8A7794 only */,
+ I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
+ CAN_DEBUGOUT9_MARK /* R8A7794 only */,
+ SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
+ CAN_DEBUGOUT10_MARK /* R8A7794 only */,
/* IPSR11 */
SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
- CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
- DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
- SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
+ CAN_DEBUGOUT11_MARK /* R8A7794 only */,
+ SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
+ CAN_DEBUGOUT12_MARK /* R8A7794 only */,
+ SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
+ CAN_DEBUGOUT13_MARK /* R8A7794 only */,
SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
- DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
- SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
- CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
- DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
- DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
- AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
- MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
- PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
- ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
- PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
+ DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK /* R8A7794 only */,
+ SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
+ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
+ CAN_DEBUGOUT15_MARK /* R8A7794 only */,
+ SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK, DU1_DISP_MARK,
+ SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK, DU1_CDE_MARK,
+ SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
+ CAN_CLK_D_MARK, PCMOE_N_MARK /* R8A7794 only */,
+ SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK,
+ ADIDATA_B_MARK /* R8A7794 only */, AD_DI_B_MARK /* R8A7794 only */,
+ PCMWE_N_MARK /* R8A7794 only */,
+ SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
+ ADICS_SAMP_B_MARK /* R8A7794 only */, AD_DO_B_MARK /* R8A7794 only */,
+ SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK,
+ ADICLK_B_MARK /* R8A7794 only */, AD_CLK_B_MARK /* R8A7794 only */,
/* IPSR12 */
- SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
- AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK,
- SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK,
- SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
- CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
- IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK,
- SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK,
- SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
- DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK,
- IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK,
- ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK,
- VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK,
- SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK,
- ATAWR0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
- VI1_DATA2_MARK, MDATA_MARK, ATAG0_N_MARK, ETH_RXD1_B_MARK,
+ SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK,
+ ADICHS0_B_MARK /* R8A7794 only */, AD_NCS_N_B_MARK /* R8A7794 only */,
+ DREQ1_N_B_MARK,
+ SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK,
+ ADICHS1_B_MARK /* R8A7794 only */, CAN1_RX_C_MARK, DACK1_B_MARK,
+ SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK,
+ ADICHS2_B_MARK /* R8A7794 only */, CAN1_TX_C_MARK, DREQ2_N_MARK,
+ SSI_SCK4_MARK, MLB_CLK_MARK /* R8A7794 only */,
+ IETX_B_MARK /* R8A7794 only */, IRD_TX_MARK /* R8A7794 only */,
+ SSI_WS4_MARK, MLB_SIG_MARK /* R8A7794 only */,
+ IECLK_B_MARK /* R8A7794 only */, IRD_RX_MARK,
+ SSI_SDATA4_MARK, MLB_DAT_MARK /* R8A7794 only */,
+ IERX_B_MARK /* R8A7794 only */, IRD_SCK_MARK /* R8A7794 only */,
+ SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK,
+ REMOCON_MARK /* R8A7794 only */, DACK2_MARK, ETH_MDIO_B_MARK,
+ SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC1_SCL_C_MARK, VI1_CLK_MARK,
+ CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK /* R8A7794 only */,
+ ETH_CRS_DV_B_MARK,
+ SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK, VI1_DATA0_MARK,
+ CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK /* R8A7794 only */,
+ ETH_RX_ER_B_MARK,
+ SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK,
+ SDATA_MARK /* R8A7794 only */, ATAWR0_N_MARK, ETH_RXD0_B_MARK,
+ SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK,
+ MDATA_MARK /* R8A7794 only */, ATAG0_N_MARK, ETH_RXD1_B_MARK,
/* IPSR13 */
SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
- SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK,
- HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK,
- ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK,
- PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK,
- ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK,
- VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK,
- SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK,
- ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK,
- VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK,
+ SCKZ_MARK /* R8A7794 only */, ATACS00_N_MARK, ETH_LINK_B_MARK,
+ SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
+ VI1_DATA4_MARK, STM_N_MARK /* R8A7794 only */, ATACS10_N_MARK,
+ ETH_REFCLK_B_MARK,
+ SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
+ MTS_N_MARK /* R8A7794 only */, EX_WAIT1_MARK, ETH_TXD1_B_MARK,
+ SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
+ ATARD0_N_MARK, ETH_TX_EN_B_MARK,
+ SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
+ ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
+ AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
+ TS_SDATA_C_MARK /* R8A7794 only */, RIF0_SYNC_B_MARK /* R8A7794 only */,
+ ETH_TXD0_B_MARK,
AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
- TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
+ TS_SCK_C_MARK /* R8A7794 only */, RIF0_CLK_B_MARK /* R8A7794 only */,
+ BPFCLK_E_MARK /* R8A7794 only */, ETH_MDC_B_MARK,
AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
- TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK,
+ TS_SDEN_C_MARK /* R8A7794 only */, RIF0_D0_B_MARK /* R8A7794 only */,
+ FMCLK_E_MARK /* R8A7794 only */, RDS_CLK_D_MARK /* R8A7794 only */,
AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
- TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK,
+ TS_SPSYNC_C_MARK /* R8A7794 only */, RIF0_D1_B_MARK /* R8A7794 only */,
+ FMIN_E_MARK /* R8A7794 only */, RDS_DATA_D_MARK /* R8A7794 only */,
PINMUX_MARK_END,
};
@@ -700,7 +938,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
PINMUX_IPSR_GPSR(IP1_17_15, D13),
PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
- PINMUX_IPSR_GPSR(IP1_17_15, TANS1),
+ PINMUX_IPSR_GPSR(IP1_17_15, TANS1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
PINMUX_IPSR_GPSR(IP1_19_18, D14),
@@ -760,40 +998,40 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2_20_18, A16),
PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
- PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
- PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0),
+ PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
PINMUX_IPSR_GPSR(IP2_23_21, A17),
PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
- PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
+ PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),/* R8A7794 */
PINMUX_IPSR_GPSR(IP2_26_24, A18),
PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
- PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1),
+ PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1), /* R8A7794 */
PINMUX_IPSR_GPSR(IP2_29_27, A19),
PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
- PINMUX_IPSR_GPSR(IP2_29_27, MOUT0),
+ PINMUX_IPSR_GPSR(IP2_29_27, MOUT0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP2_31_30, A20),
PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
- PINMUX_IPSR_GPSR(IP2_29_27, MOUT1),
+ PINMUX_IPSR_GPSR(IP2_29_27, MOUT1), /* R8A7794 only */
/* IPSR3 */
PINMUX_IPSR_GPSR(IP3_1_0, A21),
PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
- PINMUX_IPSR_GPSR(IP3_1_0, MOUT2),
+ PINMUX_IPSR_GPSR(IP3_1_0, MOUT2), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_3_2, A22),
PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
- PINMUX_IPSR_GPSR(IP3_3_2, MOUT5),
+ PINMUX_IPSR_GPSR(IP3_3_2, MOUT5), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
PINMUX_IPSR_GPSR(IP3_5_4, A23),
PINMUX_IPSR_GPSR(IP3_5_4, IO2),
- PINMUX_IPSR_GPSR(IP3_5_4, MOUT6),
+ PINMUX_IPSR_GPSR(IP3_5_4, MOUT6), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
PINMUX_IPSR_GPSR(IP3_7_6, A24),
PINMUX_IPSR_GPSR(IP3_7_6, IO3),
@@ -814,41 +1052,41 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
- PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
- PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0),
+ PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
- PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1),
+ PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
- PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
- PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0),
- PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
+ PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
- PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1),
+ PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
- PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
- PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0),
- PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
+ PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
- PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1),
+ PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
- PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
- PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0),
- PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
+ PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), /* R8A7794 */
+ PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
- PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1),
+ PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
- PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1),
+ PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_30, RD_N),
PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
@@ -858,121 +1096,121 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
- PINMUX_IPSR_GPSR(IP4_1_0, PWMFSW0),
+ PINMUX_IPSR_GPSR(IP4_1_0, PWMFSW0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
- PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
+ PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
- PINMUX_IPSR_GPSR(IP4_4_2, CC50_STATE0),
+ PINMUX_IPSR_GPSR(IP4_4_2, CC50_STATE0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
- PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
+ PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
- PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE1),
+ PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
- PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
- PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE2),
+ PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE2), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
- PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
- PINMUX_IPSR_GPSR(IP4_11_10, CC50_STATE3),
+ PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP4_11_10, CC50_STATE3), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
- PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
- PINMUX_IPSR_GPSR(IP4_13_12, CC50_STATE4),
+ PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP4_13_12, CC50_STATE4), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
- PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
- PINMUX_IPSR_GPSR(IP4_15_14, CC50_STATE5),
+ PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP4_15_14, CC50_STATE5), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
- PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
- PINMUX_IPSR_GPSR(IP4_17_16, CC50_STATE6),
+ PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP4_17_16, CC50_STATE6), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
- PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
- PINMUX_IPSR_GPSR(IP4_19_18, CC50_STATE7),
+ PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP4_19_18, CC50_STATE7), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
- PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
+ PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
- PINMUX_IPSR_GPSR(IP4_22_20, CC50_STATE8),
+ PINMUX_IPSR_GPSR(IP4_22_20, CC50_STATE8), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
- PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
+ PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
- PINMUX_IPSR_GPSR(IP4_25_23, CC50_STATE9),
+ PINMUX_IPSR_GPSR(IP4_25_23, CC50_STATE9), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
- PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
- PINMUX_IPSR_GPSR(IP4_27_26, CC50_STATE10),
+ PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP4_27_26, CC50_STATE10), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
- PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
- PINMUX_IPSR_GPSR(IP4_29_28, CC50_STATE11),
+ PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP4_29_28, CC50_STATE11), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
- PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
- PINMUX_IPSR_GPSR(IP4_31_30, CC50_STATE12),
+ PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP4_31_30, CC50_STATE12), /* R8A7794 only */
/* IPSR5 */
PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
- PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
- PINMUX_IPSR_GPSR(IP5_1_0, CC50_STATE13),
+ PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP5_1_0, CC50_STATE13), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
- PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
- PINMUX_IPSR_GPSR(IP5_3_2, CC50_STATE14),
+ PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP5_3_2, CC50_STATE14), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
- PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
- PINMUX_IPSR_GPSR(IP5_5_4, CC50_STATE15),
+ PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP5_5_4, CC50_STATE15), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
- PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
+ PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
- PINMUX_IPSR_GPSR(IP5_8_6, CC50_STATE16),
+ PINMUX_IPSR_GPSR(IP5_8_6, CC50_STATE16), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
- PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
+ PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
- PINMUX_IPSR_GPSR(IP5_11_9, CC50_STATE17),
+ PINMUX_IPSR_GPSR(IP5_11_9, CC50_STATE17), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
- PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
- PINMUX_IPSR_GPSR(IP5_13_12, CC50_STATE18),
+ PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP5_13_12, CC50_STATE18), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
- PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
- PINMUX_IPSR_GPSR(IP5_15_14, CC50_STATE19),
+ PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP5_15_14, CC50_STATE19), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
- PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
- PINMUX_IPSR_GPSR(IP5_17_16, CC50_STATE20),
+ PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP5_17_16, CC50_STATE20), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
- PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
- PINMUX_IPSR_GPSR(IP5_19_18, CC50_STATE21),
+ PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP5_19_18, CC50_STATE21), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
- PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
- PINMUX_IPSR_GPSR(IP5_21_20, CC50_STATE22),
+ PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP5_21_20, CC50_STATE22), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
- PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
- PINMUX_IPSR_GPSR(IP5_23_22, CC50_STATE23),
+ PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP5_23_22, CC50_STATE23), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
- PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
- PINMUX_IPSR_GPSR(IP5_25_24, CC50_STATE24),
+ PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP5_25_24, CC50_STATE24), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
- PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
- PINMUX_IPSR_GPSR(IP5_27_26, CC50_STATE25),
+ PINMUX_IPSR_GPSR(IP5_27_26, QCLK), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP5_27_26, CC50_STATE25), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
- PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
- PINMUX_IPSR_GPSR(IP5_29_28, CC50_STATE26),
+ PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP5_29_28, CC50_STATE26), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
- PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
- PINMUX_IPSR_GPSR(IP5_31_30, CC50_STATE27),
+ PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP5_31_30, CC50_STATE27), /* R8A7794 only */
/* IPSR6 */
PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
- PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
- PINMUX_IPSR_GPSR(IP6_1_0, CC50_STATE28),
+ PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP6_1_0, CC50_STATE28), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
- PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
- PINMUX_IPSR_GPSR(IP6_3_2, CC50_STATE29),
+ PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP6_3_2, CC50_STATE29), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
- PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
- PINMUX_IPSR_GPSR(IP6_5_4, CC50_STATE30),
+ PINMUX_IPSR_GPSR(IP6_5_4, QPOLA), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP6_5_4, CC50_STATE30), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
- PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
- PINMUX_IPSR_GPSR(IP6_7_6, CC50_STATE31),
+ PINMUX_IPSR_GPSR(IP6_7_6, QPOLB), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP6_7_6, CC50_STATE31), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
@@ -994,17 +1232,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
- PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
+ PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
- PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
+ PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
- PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
+ PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
@@ -1016,8 +1254,8 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
- PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
- PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0),
+ PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0), /* R8A7794 only */
/* IPSR7 */
PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
@@ -1025,34 +1263,34 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
- PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
- PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0),
+ PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
- PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
- PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0),
+ PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
- PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
- PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0),
+ PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
- PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
- PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
@@ -1136,60 +1374,60 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
- PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
- PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
- PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
- PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
- PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
+ PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
- PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
- PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
- PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
- PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0),
+ PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0), /* R8A7794 only */
/* IPSR9 */
PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
- PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1),
- PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
- PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
- PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0),
+ PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
- PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
- PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0),
+ PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
- PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
- PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0),
- PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
+ PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
- PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
- PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0),
- PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
- PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1),
+ PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
- PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
- PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0),
- PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
- PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1),
+ PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
@@ -1200,132 +1438,132 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
- PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
- PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
- PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
- PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1),
+ PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
- PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
- PINMUX_IPSR_GPSR(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
- PINMUX_IPSR_GPSR(IP9_24_22, CC50_STATE32),
+ PINMUX_IPSR_GPSR(IP9_24_22, CAN_DEBUG_HW_TRIGGER), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP9_24_22, CC50_STATE32), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
- PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
- PINMUX_IPSR_GPSR(IP9_27_25, CAN_STEP0),
- PINMUX_IPSR_GPSR(IP9_27_25, CC50_STATE33),
+ PINMUX_IPSR_GPSR(IP9_27_25, CAN_STEP0), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP9_27_25, CC50_STATE33), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
- PINMUX_IPSR_GPSR(IP9_30_28, CAN_TXCLK),
- PINMUX_IPSR_GPSR(IP9_30_28, CC50_STATE34),
+ PINMUX_IPSR_GPSR(IP9_30_28, CAN_TXCLK), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP9_30_28, CC50_STATE34), /* R8A7794 only */
/* IPSR10 */
PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0),
PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
- PINMUX_IPSR_GPSR(IP10_2_0, CAN_DEBUGOUT0),
- PINMUX_IPSR_GPSR(IP10_2_0, CC50_STATE35),
+ PINMUX_IPSR_GPSR(IP10_2_0, CAN_DEBUGOUT0), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP10_2_0, CC50_STATE35), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0),
PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
- PINMUX_IPSR_GPSR(IP10_5_3, CAN_DEBUGOUT1),
- PINMUX_IPSR_GPSR(IP10_5_3, CC50_STATE36),
+ PINMUX_IPSR_GPSR(IP10_5_3, CAN_DEBUGOUT1), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP10_5_3, CC50_STATE36), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0),
PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
- PINMUX_IPSR_GPSR(IP10_8_6, USB0_EXTLP),
- PINMUX_IPSR_GPSR(IP10_8_6, CAN_DEBUGOUT2),
- PINMUX_IPSR_GPSR(IP10_8_6, CC50_STATE37),
+ PINMUX_IPSR_GPSR(IP10_8_6, USB0_EXTLP), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP10_8_6, CAN_DEBUGOUT2), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP10_8_6, CC50_STATE37), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0),
PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
- PINMUX_IPSR_GPSR(IP10_11_9, USB0_OVC1),
- PINMUX_IPSR_GPSR(IP10_11_9, CAN_DEBUGOUT3),
- PINMUX_IPSR_GPSR(IP10_11_9, CC50_STATE38),
+ PINMUX_IPSR_GPSR(IP10_11_9, USB0_OVC1), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP10_11_9, CAN_DEBUGOUT3), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP10_11_9, CC50_STATE38), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
- PINMUX_IPSR_GPSR(IP10_14_12, USB0_IDIN),
- PINMUX_IPSR_GPSR(IP10_14_12, CAN_DEBUGOUT4),
- PINMUX_IPSR_GPSR(IP10_14_12, CC50_STATE39),
+ PINMUX_IPSR_GPSR(IP10_14_12, USB0_IDIN), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP10_14_12, CAN_DEBUGOUT4), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP10_14_12, CC50_STATE39), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
- PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
+ PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
- PINMUX_IPSR_GPSR(IP10_17_15, TANS2),
- PINMUX_IPSR_GPSR(IP10_17_15, CAN_DEBUGOUT5),
- PINMUX_IPSR_GPSR(IP10_17_15, CC50_OSCOUT),
+ PINMUX_IPSR_GPSR(IP10_17_15, TANS2), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP10_17_15, CAN_DEBUGOUT5), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP10_17_15, CC50_OSCOUT), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
- PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
+ PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
- PINMUX_IPSR_GPSR(IP10_20_18, CAN_DEBUGOUT6),
+ PINMUX_IPSR_GPSR(IP10_20_18, CAN_DEBUGOUT6), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2),
PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
- PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
+ PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
- PINMUX_IPSR_GPSR(IP10_23_21, CAN_DEBUGOUT7),
- PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2),
+ PINMUX_IPSR_GPSR(IP10_23_21, CAN_DEBUGOUT7), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
- PINMUX_IPSR_GPSR(IP10_26_24, CAN_DEBUGOUT8),
+ PINMUX_IPSR_GPSR(IP10_26_24, CAN_DEBUGOUT8), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
- PINMUX_IPSR_GPSR(IP10_29_27, CAN_DEBUGOUT9),
+ PINMUX_IPSR_GPSR(IP10_29_27, CAN_DEBUGOUT9), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
- PINMUX_IPSR_GPSR(IP10_31_30, CAN_DEBUGOUT10),
+ PINMUX_IPSR_GPSR(IP10_31_30, CAN_DEBUGOUT10), /* R8A7794 only */
/* IPSR11 */
PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
- PINMUX_IPSR_GPSR(IP11_2_0, CAN_DEBUGOUT11),
+ PINMUX_IPSR_GPSR(IP11_2_0, CAN_DEBUGOUT11), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
- PINMUX_IPSR_GPSR(IP11_5_3, CAN_DEBUGOUT12),
+ PINMUX_IPSR_GPSR(IP11_5_3, CAN_DEBUGOUT12), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
- PINMUX_IPSR_GPSR(IP11_7_6, CAN_DEBUGOUT13),
+ PINMUX_IPSR_GPSR(IP11_7_6, CAN_DEBUGOUT13), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
- PINMUX_IPSR_GPSR(IP11_10_8, CAN_DEBUGOUT14),
+ PINMUX_IPSR_GPSR(IP11_10_8, CAN_DEBUGOUT14), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
- PINMUX_IPSR_GPSR(IP11_13_11, CAN_DEBUGOUT15),
+ PINMUX_IPSR_GPSR(IP11_13_11, CAN_DEBUGOUT15), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
@@ -1339,60 +1577,60 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
- PINMUX_IPSR_GPSR(IP11_20_18, PCMOE_N),
+ PINMUX_IPSR_GPSR(IP11_20_18, PCMOE_N), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
- PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
- PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1),
- PINMUX_IPSR_GPSR(IP11_23_21, PCMWE_N),
+ PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP11_23_21, PCMWE_N), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
- PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
- PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1),
+ PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), /* R8A7794 */
+ PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
- PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
- PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1),
+ PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1), /* R8A7794 only */
/* IPSR12 */
PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
- PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
- PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1),
+ PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
- PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
- PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
- PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
- PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
- PINMUX_IPSR_GPSR(IP12_10_9, IRD_TX),
+ PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP12_10_9, IRD_TX), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
- PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
- PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
- PINMUX_IPSR_GPSR(IP12_12_11, IRD_RX),
+ PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP12_12_11, IRD_RX), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
- PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
- PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
- PINMUX_IPSR_GPSR(IP12_14_13, IRD_SCK),
+ PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1), /* R8A7794 only */
+ PINMUX_IPSR_GPSR(IP12_14_13, IRD_SCK), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
- PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
+ PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
@@ -1400,25 +1638,25 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2),
PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
- PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
+ PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0), /* R8A7794 */
PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2),
PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
- PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
+ PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0), /* R8A7794 */
PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
- PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),
+ PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
- PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),
+ PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
@@ -1427,21 +1665,21 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
- PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0),
+ PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
- PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0),
+ PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
- PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0),
+ PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
@@ -1460,33 +1698,33 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
- PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
- PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1),
+ PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), /* R8A7794 */
+ PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
- PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
- PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1),
- PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
+ PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
- PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
- PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1),
- PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
- PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3),
+ PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
- PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
- PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1),
- PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
- PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3),
+ PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), /* R8A7794 */
+ PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3), /* R8A7794 only */
};
static const struct sh_pfc_pin pinmux_pins[] = {
@@ -1660,6 +1898,7 @@ static const unsigned int avb_gmii_mux[]
AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
AVB_COL_MARK,
};
+/* - AVB AVTP (R8A7794 only) ------------------------------------------------ */
static const unsigned int avb_avtp_capture_pins[] = {
RCAR_GP_PIN(5, 11),
};
@@ -3515,275 +3754,282 @@ static const unsigned int vin1_clk_mux[]
VI1_CLK_MARK,
};
-static const struct sh_pfc_pin_group pinmux_groups[] = {
- SH_PFC_PIN_GROUP(audio_clka),
- SH_PFC_PIN_GROUP(audio_clka_b),
- SH_PFC_PIN_GROUP(audio_clka_c),
- SH_PFC_PIN_GROUP(audio_clka_d),
- SH_PFC_PIN_GROUP(audio_clkb),
- SH_PFC_PIN_GROUP(audio_clkb_b),
- SH_PFC_PIN_GROUP(audio_clkb_c),
- SH_PFC_PIN_GROUP(audio_clkc),
- SH_PFC_PIN_GROUP(audio_clkc_b),
- SH_PFC_PIN_GROUP(audio_clkc_c),
- SH_PFC_PIN_GROUP(audio_clkout),
- SH_PFC_PIN_GROUP(audio_clkout_b),
- SH_PFC_PIN_GROUP(audio_clkout_c),
- SH_PFC_PIN_GROUP(avb_link),
- SH_PFC_PIN_GROUP(avb_magic),
- SH_PFC_PIN_GROUP(avb_phy_int),
- SH_PFC_PIN_GROUP(avb_mdio),
- SH_PFC_PIN_GROUP(avb_mii),
- SH_PFC_PIN_GROUP(avb_gmii),
- SH_PFC_PIN_GROUP(avb_avtp_capture),
- SH_PFC_PIN_GROUP(avb_avtp_match),
- SH_PFC_PIN_GROUP(avb_avtp_capture_b),
- SH_PFC_PIN_GROUP(avb_avtp_match_b),
- SH_PFC_PIN_GROUP(du0_rgb666),
- SH_PFC_PIN_GROUP(du0_rgb888),
- SH_PFC_PIN_GROUP(du0_clk0_out),
- SH_PFC_PIN_GROUP(du0_clk1_out),
- SH_PFC_PIN_GROUP(du0_clk_in),
- SH_PFC_PIN_GROUP(du0_sync),
- SH_PFC_PIN_GROUP(du0_oddf),
- SH_PFC_PIN_GROUP(du0_cde),
- SH_PFC_PIN_GROUP(du0_disp),
- SH_PFC_PIN_GROUP(du1_rgb666),
- SH_PFC_PIN_GROUP(du1_rgb888),
- SH_PFC_PIN_GROUP(du1_clk0_out),
- SH_PFC_PIN_GROUP(du1_clk1_out),
- SH_PFC_PIN_GROUP(du1_clk_in),
- SH_PFC_PIN_GROUP(du1_sync),
- SH_PFC_PIN_GROUP(du1_oddf),
- SH_PFC_PIN_GROUP(du1_cde),
- SH_PFC_PIN_GROUP(du1_disp),
- SH_PFC_PIN_GROUP(eth_link),
- SH_PFC_PIN_GROUP(eth_magic),
- SH_PFC_PIN_GROUP(eth_mdio),
- SH_PFC_PIN_GROUP(eth_rmii),
- SH_PFC_PIN_GROUP(eth_link_b),
- SH_PFC_PIN_GROUP(eth_magic_b),
- SH_PFC_PIN_GROUP(eth_mdio_b),
- SH_PFC_PIN_GROUP(eth_rmii_b),
- SH_PFC_PIN_GROUP(hscif0_data),
- SH_PFC_PIN_GROUP(hscif0_clk),
- SH_PFC_PIN_GROUP(hscif0_ctrl),
- SH_PFC_PIN_GROUP(hscif0_data_b),
- SH_PFC_PIN_GROUP(hscif0_clk_b),
- SH_PFC_PIN_GROUP(hscif1_data),
- SH_PFC_PIN_GROUP(hscif1_clk),
- SH_PFC_PIN_GROUP(hscif1_ctrl),
- SH_PFC_PIN_GROUP(hscif1_data_b),
- SH_PFC_PIN_GROUP(hscif1_ctrl_b),
- SH_PFC_PIN_GROUP(hscif2_data),
- SH_PFC_PIN_GROUP(hscif2_clk),
- SH_PFC_PIN_GROUP(hscif2_ctrl),
- SH_PFC_PIN_GROUP(i2c0),
- SH_PFC_PIN_GROUP(i2c0_b),
- SH_PFC_PIN_GROUP(i2c0_c),
- SH_PFC_PIN_GROUP(i2c0_d),
- SH_PFC_PIN_GROUP(i2c0_e),
- SH_PFC_PIN_GROUP(i2c1),
- SH_PFC_PIN_GROUP(i2c1_b),
- SH_PFC_PIN_GROUP(i2c1_c),
- SH_PFC_PIN_GROUP(i2c1_d),
- SH_PFC_PIN_GROUP(i2c1_e),
- SH_PFC_PIN_GROUP(i2c2),
- SH_PFC_PIN_GROUP(i2c2_b),
- SH_PFC_PIN_GROUP(i2c2_c),
- SH_PFC_PIN_GROUP(i2c2_d),
- SH_PFC_PIN_GROUP(i2c2_e),
- SH_PFC_PIN_GROUP(i2c3),
- SH_PFC_PIN_GROUP(i2c3_b),
- SH_PFC_PIN_GROUP(i2c3_c),
- SH_PFC_PIN_GROUP(i2c3_d),
- SH_PFC_PIN_GROUP(i2c3_e),
- SH_PFC_PIN_GROUP(i2c4),
- SH_PFC_PIN_GROUP(i2c4_b),
- SH_PFC_PIN_GROUP(i2c4_c),
- SH_PFC_PIN_GROUP(i2c4_d),
- SH_PFC_PIN_GROUP(i2c4_e),
- SH_PFC_PIN_GROUP(intc_irq0),
- SH_PFC_PIN_GROUP(intc_irq1),
- SH_PFC_PIN_GROUP(intc_irq2),
- SH_PFC_PIN_GROUP(intc_irq3),
- SH_PFC_PIN_GROUP(intc_irq4),
- SH_PFC_PIN_GROUP(intc_irq5),
- SH_PFC_PIN_GROUP(intc_irq6),
- SH_PFC_PIN_GROUP(intc_irq7),
- SH_PFC_PIN_GROUP(intc_irq8),
- SH_PFC_PIN_GROUP(intc_irq9),
- SH_PFC_PIN_GROUP(mmc_data1),
- SH_PFC_PIN_GROUP(mmc_data4),
- SH_PFC_PIN_GROUP(mmc_data8),
- SH_PFC_PIN_GROUP(mmc_ctrl),
- SH_PFC_PIN_GROUP(msiof0_clk),
- SH_PFC_PIN_GROUP(msiof0_sync),
- SH_PFC_PIN_GROUP(msiof0_ss1),
- SH_PFC_PIN_GROUP(msiof0_ss2),
- SH_PFC_PIN_GROUP(msiof0_rx),
- SH_PFC_PIN_GROUP(msiof0_tx),
- SH_PFC_PIN_GROUP(msiof1_clk),
- SH_PFC_PIN_GROUP(msiof1_sync),
- SH_PFC_PIN_GROUP(msiof1_ss1),
- SH_PFC_PIN_GROUP(msiof1_ss2),
- SH_PFC_PIN_GROUP(msiof1_rx),
- SH_PFC_PIN_GROUP(msiof1_tx),
- SH_PFC_PIN_GROUP(msiof1_clk_b),
- SH_PFC_PIN_GROUP(msiof1_sync_b),
- SH_PFC_PIN_GROUP(msiof1_ss1_b),
- SH_PFC_PIN_GROUP(msiof1_ss2_b),
- SH_PFC_PIN_GROUP(msiof1_rx_b),
- SH_PFC_PIN_GROUP(msiof1_tx_b),
- SH_PFC_PIN_GROUP(msiof2_clk),
- SH_PFC_PIN_GROUP(msiof2_sync),
- SH_PFC_PIN_GROUP(msiof2_ss1),
- SH_PFC_PIN_GROUP(msiof2_ss2),
- SH_PFC_PIN_GROUP(msiof2_rx),
- SH_PFC_PIN_GROUP(msiof2_tx),
- SH_PFC_PIN_GROUP(msiof2_clk_b),
- SH_PFC_PIN_GROUP(msiof2_sync_b),
- SH_PFC_PIN_GROUP(msiof2_ss1_b),
- SH_PFC_PIN_GROUP(msiof2_ss2_b),
- SH_PFC_PIN_GROUP(msiof2_rx_b),
- SH_PFC_PIN_GROUP(msiof2_tx_b),
- SH_PFC_PIN_GROUP(qspi_ctrl),
- SH_PFC_PIN_GROUP(qspi_data2),
- SH_PFC_PIN_GROUP(qspi_data4),
- SH_PFC_PIN_GROUP(scif0_data),
- SH_PFC_PIN_GROUP(scif0_data_b),
- SH_PFC_PIN_GROUP(scif0_data_c),
- SH_PFC_PIN_GROUP(scif0_data_d),
- SH_PFC_PIN_GROUP(scif1_data),
- SH_PFC_PIN_GROUP(scif1_clk),
- SH_PFC_PIN_GROUP(scif1_data_b),
- SH_PFC_PIN_GROUP(scif1_clk_b),
- SH_PFC_PIN_GROUP(scif1_data_c),
- SH_PFC_PIN_GROUP(scif1_clk_c),
- SH_PFC_PIN_GROUP(scif2_data),
- SH_PFC_PIN_GROUP(scif2_clk),
- SH_PFC_PIN_GROUP(scif2_data_b),
- SH_PFC_PIN_GROUP(scif2_clk_b),
- SH_PFC_PIN_GROUP(scif2_data_c),
- SH_PFC_PIN_GROUP(scif2_clk_c),
- SH_PFC_PIN_GROUP(scif3_data),
- SH_PFC_PIN_GROUP(scif3_clk),
- SH_PFC_PIN_GROUP(scif3_data_b),
- SH_PFC_PIN_GROUP(scif3_clk_b),
- SH_PFC_PIN_GROUP(scif4_data),
- SH_PFC_PIN_GROUP(scif4_data_b),
- SH_PFC_PIN_GROUP(scif4_data_c),
- SH_PFC_PIN_GROUP(scif4_data_d),
- SH_PFC_PIN_GROUP(scif4_data_e),
- SH_PFC_PIN_GROUP(scif5_data),
- SH_PFC_PIN_GROUP(scif5_data_b),
- SH_PFC_PIN_GROUP(scif5_data_c),
- SH_PFC_PIN_GROUP(scif5_data_d),
- SH_PFC_PIN_GROUP(scifa0_data),
- SH_PFC_PIN_GROUP(scifa0_data_b),
- SH_PFC_PIN_GROUP(scifa0_data_c),
- SH_PFC_PIN_GROUP(scifa0_data_d),
- SH_PFC_PIN_GROUP(scifa1_data),
- SH_PFC_PIN_GROUP(scifa1_clk),
- SH_PFC_PIN_GROUP(scifa1_data_b),
- SH_PFC_PIN_GROUP(scifa1_clk_b),
- SH_PFC_PIN_GROUP(scifa1_data_c),
- SH_PFC_PIN_GROUP(scifa1_clk_c),
- SH_PFC_PIN_GROUP(scifa2_data),
- SH_PFC_PIN_GROUP(scifa2_clk),
- SH_PFC_PIN_GROUP(scifa2_data_b),
- SH_PFC_PIN_GROUP(scifa2_clk_b),
- SH_PFC_PIN_GROUP(scifa3_data),
- SH_PFC_PIN_GROUP(scifa3_clk),
- SH_PFC_PIN_GROUP(scifa3_data_b),
- SH_PFC_PIN_GROUP(scifa3_clk_b),
- SH_PFC_PIN_GROUP(scifa4_data),
- SH_PFC_PIN_GROUP(scifa4_data_b),
- SH_PFC_PIN_GROUP(scifa4_data_c),
- SH_PFC_PIN_GROUP(scifa4_data_d),
- SH_PFC_PIN_GROUP(scifa5_data),
- SH_PFC_PIN_GROUP(scifa5_data_b),
- SH_PFC_PIN_GROUP(scifa5_data_c),
- SH_PFC_PIN_GROUP(scifa5_data_d),
- SH_PFC_PIN_GROUP(scifb0_data),
- SH_PFC_PIN_GROUP(scifb0_clk),
- SH_PFC_PIN_GROUP(scifb0_ctrl),
- SH_PFC_PIN_GROUP(scifb1_data),
- SH_PFC_PIN_GROUP(scifb1_clk),
- SH_PFC_PIN_GROUP(scifb2_data),
- SH_PFC_PIN_GROUP(scifb2_clk),
- SH_PFC_PIN_GROUP(scifb2_ctrl),
- SH_PFC_PIN_GROUP(scif_clk),
- SH_PFC_PIN_GROUP(scif_clk_b),
- SH_PFC_PIN_GROUP(sdhi0_data1),
- SH_PFC_PIN_GROUP(sdhi0_data4),
- SH_PFC_PIN_GROUP(sdhi0_ctrl),
- SH_PFC_PIN_GROUP(sdhi0_cd),
- SH_PFC_PIN_GROUP(sdhi0_wp),
- SH_PFC_PIN_GROUP(sdhi1_data1),
- SH_PFC_PIN_GROUP(sdhi1_data4),
- SH_PFC_PIN_GROUP(sdhi1_ctrl),
- SH_PFC_PIN_GROUP(sdhi1_cd),
- SH_PFC_PIN_GROUP(sdhi1_wp),
- SH_PFC_PIN_GROUP(sdhi2_data1),
- SH_PFC_PIN_GROUP(sdhi2_data4),
- SH_PFC_PIN_GROUP(sdhi2_ctrl),
- SH_PFC_PIN_GROUP(sdhi2_cd),
- SH_PFC_PIN_GROUP(sdhi2_wp),
- SH_PFC_PIN_GROUP(ssi0_data),
- SH_PFC_PIN_GROUP(ssi0129_ctrl),
- SH_PFC_PIN_GROUP(ssi1_data),
- SH_PFC_PIN_GROUP(ssi1_ctrl),
- SH_PFC_PIN_GROUP(ssi1_data_b),
- SH_PFC_PIN_GROUP(ssi1_ctrl_b),
- SH_PFC_PIN_GROUP(ssi2_data),
- SH_PFC_PIN_GROUP(ssi2_ctrl),
- SH_PFC_PIN_GROUP(ssi2_data_b),
- SH_PFC_PIN_GROUP(ssi2_ctrl_b),
- SH_PFC_PIN_GROUP(ssi3_data),
- SH_PFC_PIN_GROUP(ssi34_ctrl),
- SH_PFC_PIN_GROUP(ssi4_data),
- SH_PFC_PIN_GROUP(ssi4_ctrl),
- SH_PFC_PIN_GROUP(ssi4_data_b),
- SH_PFC_PIN_GROUP(ssi4_ctrl_b),
- SH_PFC_PIN_GROUP(ssi5_data),
- SH_PFC_PIN_GROUP(ssi5_ctrl),
- SH_PFC_PIN_GROUP(ssi5_data_b),
- SH_PFC_PIN_GROUP(ssi5_ctrl_b),
- SH_PFC_PIN_GROUP(ssi6_data),
- SH_PFC_PIN_GROUP(ssi6_ctrl),
- SH_PFC_PIN_GROUP(ssi6_data_b),
- SH_PFC_PIN_GROUP(ssi6_ctrl_b),
- SH_PFC_PIN_GROUP(ssi7_data),
- SH_PFC_PIN_GROUP(ssi78_ctrl),
- SH_PFC_PIN_GROUP(ssi7_data_b),
- SH_PFC_PIN_GROUP(ssi78_ctrl_b),
- SH_PFC_PIN_GROUP(ssi8_data),
- SH_PFC_PIN_GROUP(ssi8_data_b),
- SH_PFC_PIN_GROUP(ssi9_data),
- SH_PFC_PIN_GROUP(ssi9_ctrl),
- SH_PFC_PIN_GROUP(ssi9_data_b),
- SH_PFC_PIN_GROUP(ssi9_ctrl_b),
- SH_PFC_PIN_GROUP(usb0),
- SH_PFC_PIN_GROUP(usb1),
- VIN_DATA_PIN_GROUP(vin0_data, 24),
- VIN_DATA_PIN_GROUP(vin0_data, 20),
- SH_PFC_PIN_GROUP(vin0_data18),
- VIN_DATA_PIN_GROUP(vin0_data, 16),
- VIN_DATA_PIN_GROUP(vin0_data, 12),
- VIN_DATA_PIN_GROUP(vin0_data, 10),
- VIN_DATA_PIN_GROUP(vin0_data, 8),
- SH_PFC_PIN_GROUP(vin0_sync),
- SH_PFC_PIN_GROUP(vin0_field),
- SH_PFC_PIN_GROUP(vin0_clkenb),
- SH_PFC_PIN_GROUP(vin0_clk),
- VIN_DATA_PIN_GROUP(vin1_data, 12),
- VIN_DATA_PIN_GROUP(vin1_data, 10),
- VIN_DATA_PIN_GROUP(vin1_data, 8),
- SH_PFC_PIN_GROUP(vin1_sync),
- SH_PFC_PIN_GROUP(vin1_field),
- SH_PFC_PIN_GROUP(vin1_clkenb),
- SH_PFC_PIN_GROUP(vin1_clk),
+static const struct {
+ struct sh_pfc_pin_group common[264];
+ struct sh_pfc_pin_group r8a7794[4];
+} pinmux_groups = {
+ .common = {
+ SH_PFC_PIN_GROUP(audio_clka),
+ SH_PFC_PIN_GROUP(audio_clka_b),
+ SH_PFC_PIN_GROUP(audio_clka_c),
+ SH_PFC_PIN_GROUP(audio_clka_d),
+ SH_PFC_PIN_GROUP(audio_clkb),
+ SH_PFC_PIN_GROUP(audio_clkb_b),
+ SH_PFC_PIN_GROUP(audio_clkb_c),
+ SH_PFC_PIN_GROUP(audio_clkc),
+ SH_PFC_PIN_GROUP(audio_clkc_b),
+ SH_PFC_PIN_GROUP(audio_clkc_c),
+ SH_PFC_PIN_GROUP(audio_clkout),
+ SH_PFC_PIN_GROUP(audio_clkout_b),
+ SH_PFC_PIN_GROUP(audio_clkout_c),
+ SH_PFC_PIN_GROUP(avb_link),
+ SH_PFC_PIN_GROUP(avb_magic),
+ SH_PFC_PIN_GROUP(avb_phy_int),
+ SH_PFC_PIN_GROUP(avb_mdio),
+ SH_PFC_PIN_GROUP(avb_mii),
+ SH_PFC_PIN_GROUP(avb_gmii),
+ SH_PFC_PIN_GROUP(du0_rgb666),
+ SH_PFC_PIN_GROUP(du0_rgb888),
+ SH_PFC_PIN_GROUP(du0_clk0_out),
+ SH_PFC_PIN_GROUP(du0_clk1_out),
+ SH_PFC_PIN_GROUP(du0_clk_in),
+ SH_PFC_PIN_GROUP(du0_sync),
+ SH_PFC_PIN_GROUP(du0_oddf),
+ SH_PFC_PIN_GROUP(du0_cde),
+ SH_PFC_PIN_GROUP(du0_disp),
+ SH_PFC_PIN_GROUP(du1_rgb666),
+ SH_PFC_PIN_GROUP(du1_rgb888),
+ SH_PFC_PIN_GROUP(du1_clk0_out),
+ SH_PFC_PIN_GROUP(du1_clk1_out),
+ SH_PFC_PIN_GROUP(du1_clk_in),
+ SH_PFC_PIN_GROUP(du1_sync),
+ SH_PFC_PIN_GROUP(du1_oddf),
+ SH_PFC_PIN_GROUP(du1_cde),
+ SH_PFC_PIN_GROUP(du1_disp),
+ SH_PFC_PIN_GROUP(eth_link),
+ SH_PFC_PIN_GROUP(eth_magic),
+ SH_PFC_PIN_GROUP(eth_mdio),
+ SH_PFC_PIN_GROUP(eth_rmii),
+ SH_PFC_PIN_GROUP(eth_link_b),
+ SH_PFC_PIN_GROUP(eth_magic_b),
+ SH_PFC_PIN_GROUP(eth_mdio_b),
+ SH_PFC_PIN_GROUP(eth_rmii_b),
+ SH_PFC_PIN_GROUP(hscif0_data),
+ SH_PFC_PIN_GROUP(hscif0_clk),
+ SH_PFC_PIN_GROUP(hscif0_ctrl),
+ SH_PFC_PIN_GROUP(hscif0_data_b),
+ SH_PFC_PIN_GROUP(hscif0_clk_b),
+ SH_PFC_PIN_GROUP(hscif1_data),
+ SH_PFC_PIN_GROUP(hscif1_clk),
+ SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif1_data_b),
+ SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+ SH_PFC_PIN_GROUP(hscif2_data),
+ SH_PFC_PIN_GROUP(hscif2_clk),
+ SH_PFC_PIN_GROUP(hscif2_ctrl),
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c0_b),
+ SH_PFC_PIN_GROUP(i2c0_c),
+ SH_PFC_PIN_GROUP(i2c0_d),
+ SH_PFC_PIN_GROUP(i2c0_e),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c1_b),
+ SH_PFC_PIN_GROUP(i2c1_c),
+ SH_PFC_PIN_GROUP(i2c1_d),
+ SH_PFC_PIN_GROUP(i2c1_e),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c2_b),
+ SH_PFC_PIN_GROUP(i2c2_c),
+ SH_PFC_PIN_GROUP(i2c2_d),
+ SH_PFC_PIN_GROUP(i2c2_e),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c3_b),
+ SH_PFC_PIN_GROUP(i2c3_c),
+ SH_PFC_PIN_GROUP(i2c3_d),
+ SH_PFC_PIN_GROUP(i2c3_e),
+ SH_PFC_PIN_GROUP(i2c4),
+ SH_PFC_PIN_GROUP(i2c4_b),
+ SH_PFC_PIN_GROUP(i2c4_c),
+ SH_PFC_PIN_GROUP(i2c4_d),
+ SH_PFC_PIN_GROUP(i2c4_e),
+ SH_PFC_PIN_GROUP(intc_irq0),
+ SH_PFC_PIN_GROUP(intc_irq1),
+ SH_PFC_PIN_GROUP(intc_irq2),
+ SH_PFC_PIN_GROUP(intc_irq3),
+ SH_PFC_PIN_GROUP(intc_irq4),
+ SH_PFC_PIN_GROUP(intc_irq5),
+ SH_PFC_PIN_GROUP(intc_irq6),
+ SH_PFC_PIN_GROUP(intc_irq7),
+ SH_PFC_PIN_GROUP(intc_irq8),
+ SH_PFC_PIN_GROUP(intc_irq9),
+ SH_PFC_PIN_GROUP(mmc_data1),
+ SH_PFC_PIN_GROUP(mmc_data4),
+ SH_PFC_PIN_GROUP(mmc_data8),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_rx),
+ SH_PFC_PIN_GROUP(msiof0_tx),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_rx),
+ SH_PFC_PIN_GROUP(msiof1_tx),
+ SH_PFC_PIN_GROUP(msiof1_clk_b),
+ SH_PFC_PIN_GROUP(msiof1_sync_b),
+ SH_PFC_PIN_GROUP(msiof1_ss1_b),
+ SH_PFC_PIN_GROUP(msiof1_ss2_b),
+ SH_PFC_PIN_GROUP(msiof1_rx_b),
+ SH_PFC_PIN_GROUP(msiof1_tx_b),
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_rx),
+ SH_PFC_PIN_GROUP(msiof2_tx),
+ SH_PFC_PIN_GROUP(msiof2_clk_b),
+ SH_PFC_PIN_GROUP(msiof2_sync_b),
+ SH_PFC_PIN_GROUP(msiof2_ss1_b),
+ SH_PFC_PIN_GROUP(msiof2_ss2_b),
+ SH_PFC_PIN_GROUP(msiof2_rx_b),
+ SH_PFC_PIN_GROUP(msiof2_tx_b),
+ SH_PFC_PIN_GROUP(qspi_ctrl),
+ SH_PFC_PIN_GROUP(qspi_data2),
+ SH_PFC_PIN_GROUP(qspi_data4),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_data_b),
+ SH_PFC_PIN_GROUP(scif0_data_c),
+ SH_PFC_PIN_GROUP(scif0_data_d),
+ SH_PFC_PIN_GROUP(scif1_data),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif1_clk_b),
+ SH_PFC_PIN_GROUP(scif1_data_c),
+ SH_PFC_PIN_GROUP(scif1_clk_c),
+ SH_PFC_PIN_GROUP(scif2_data),
+ SH_PFC_PIN_GROUP(scif2_clk),
+ SH_PFC_PIN_GROUP(scif2_data_b),
+ SH_PFC_PIN_GROUP(scif2_clk_b),
+ SH_PFC_PIN_GROUP(scif2_data_c),
+ SH_PFC_PIN_GROUP(scif2_clk_c),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_data_b),
+ SH_PFC_PIN_GROUP(scif3_clk_b),
+ SH_PFC_PIN_GROUP(scif4_data),
+ SH_PFC_PIN_GROUP(scif4_data_b),
+ SH_PFC_PIN_GROUP(scif4_data_c),
+ SH_PFC_PIN_GROUP(scif4_data_d),
+ SH_PFC_PIN_GROUP(scif4_data_e),
+ SH_PFC_PIN_GROUP(scif5_data),
+ SH_PFC_PIN_GROUP(scif5_data_b),
+ SH_PFC_PIN_GROUP(scif5_data_c),
+ SH_PFC_PIN_GROUP(scif5_data_d),
+ SH_PFC_PIN_GROUP(scifa0_data),
+ SH_PFC_PIN_GROUP(scifa0_data_b),
+ SH_PFC_PIN_GROUP(scifa0_data_c),
+ SH_PFC_PIN_GROUP(scifa0_data_d),
+ SH_PFC_PIN_GROUP(scifa1_data),
+ SH_PFC_PIN_GROUP(scifa1_clk),
+ SH_PFC_PIN_GROUP(scifa1_data_b),
+ SH_PFC_PIN_GROUP(scifa1_clk_b),
+ SH_PFC_PIN_GROUP(scifa1_data_c),
+ SH_PFC_PIN_GROUP(scifa1_clk_c),
+ SH_PFC_PIN_GROUP(scifa2_data),
+ SH_PFC_PIN_GROUP(scifa2_clk),
+ SH_PFC_PIN_GROUP(scifa2_data_b),
+ SH_PFC_PIN_GROUP(scifa2_clk_b),
+ SH_PFC_PIN_GROUP(scifa3_data),
+ SH_PFC_PIN_GROUP(scifa3_clk),
+ SH_PFC_PIN_GROUP(scifa3_data_b),
+ SH_PFC_PIN_GROUP(scifa3_clk_b),
+ SH_PFC_PIN_GROUP(scifa4_data),
+ SH_PFC_PIN_GROUP(scifa4_data_b),
+ SH_PFC_PIN_GROUP(scifa4_data_c),
+ SH_PFC_PIN_GROUP(scifa4_data_d),
+ SH_PFC_PIN_GROUP(scifa5_data),
+ SH_PFC_PIN_GROUP(scifa5_data_b),
+ SH_PFC_PIN_GROUP(scifa5_data_c),
+ SH_PFC_PIN_GROUP(scifa5_data_d),
+ SH_PFC_PIN_GROUP(scifb0_data),
+ SH_PFC_PIN_GROUP(scifb0_clk),
+ SH_PFC_PIN_GROUP(scifb0_ctrl),
+ SH_PFC_PIN_GROUP(scifb1_data),
+ SH_PFC_PIN_GROUP(scifb1_clk),
+ SH_PFC_PIN_GROUP(scifb2_data),
+ SH_PFC_PIN_GROUP(scifb2_clk),
+ SH_PFC_PIN_GROUP(scifb2_ctrl),
+ SH_PFC_PIN_GROUP(scif_clk),
+ SH_PFC_PIN_GROUP(scif_clk_b),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_cd),
+ SH_PFC_PIN_GROUP(sdhi2_wp),
+ SH_PFC_PIN_GROUP(ssi0_data),
+ SH_PFC_PIN_GROUP(ssi0129_ctrl),
+ SH_PFC_PIN_GROUP(ssi1_data),
+ SH_PFC_PIN_GROUP(ssi1_ctrl),
+ SH_PFC_PIN_GROUP(ssi1_data_b),
+ SH_PFC_PIN_GROUP(ssi1_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi2_data),
+ SH_PFC_PIN_GROUP(ssi2_ctrl),
+ SH_PFC_PIN_GROUP(ssi2_data_b),
+ SH_PFC_PIN_GROUP(ssi2_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi3_data),
+ SH_PFC_PIN_GROUP(ssi34_ctrl),
+ SH_PFC_PIN_GROUP(ssi4_data),
+ SH_PFC_PIN_GROUP(ssi4_ctrl),
+ SH_PFC_PIN_GROUP(ssi4_data_b),
+ SH_PFC_PIN_GROUP(ssi4_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi5_data),
+ SH_PFC_PIN_GROUP(ssi5_ctrl),
+ SH_PFC_PIN_GROUP(ssi5_data_b),
+ SH_PFC_PIN_GROUP(ssi5_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi6_data),
+ SH_PFC_PIN_GROUP(ssi6_ctrl),
+ SH_PFC_PIN_GROUP(ssi6_data_b),
+ SH_PFC_PIN_GROUP(ssi6_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi7_data),
+ SH_PFC_PIN_GROUP(ssi78_ctrl),
+ SH_PFC_PIN_GROUP(ssi7_data_b),
+ SH_PFC_PIN_GROUP(ssi78_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi8_data),
+ SH_PFC_PIN_GROUP(ssi8_data_b),
+ SH_PFC_PIN_GROUP(ssi9_data),
+ SH_PFC_PIN_GROUP(ssi9_ctrl),
+ SH_PFC_PIN_GROUP(ssi9_data_b),
+ SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+ SH_PFC_PIN_GROUP(usb0),
+ SH_PFC_PIN_GROUP(usb1),
+ VIN_DATA_PIN_GROUP(vin0_data, 24),
+ VIN_DATA_PIN_GROUP(vin0_data, 20),
+ SH_PFC_PIN_GROUP(vin0_data18),
+ VIN_DATA_PIN_GROUP(vin0_data, 16),
+ VIN_DATA_PIN_GROUP(vin0_data, 12),
+ VIN_DATA_PIN_GROUP(vin0_data, 10),
+ VIN_DATA_PIN_GROUP(vin0_data, 8),
+ SH_PFC_PIN_GROUP(vin0_sync),
+ SH_PFC_PIN_GROUP(vin0_field),
+ SH_PFC_PIN_GROUP(vin0_clkenb),
+ SH_PFC_PIN_GROUP(vin0_clk),
+ VIN_DATA_PIN_GROUP(vin1_data, 12),
+ VIN_DATA_PIN_GROUP(vin1_data, 10),
+ VIN_DATA_PIN_GROUP(vin1_data, 8),
+ SH_PFC_PIN_GROUP(vin1_sync),
+ SH_PFC_PIN_GROUP(vin1_field),
+ SH_PFC_PIN_GROUP(vin1_clkenb),
+ SH_PFC_PIN_GROUP(vin1_clk),
+ },
+ .r8a7794 = {
+ SH_PFC_PIN_GROUP(avb_avtp_capture),
+ SH_PFC_PIN_GROUP(avb_avtp_match),
+ SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+ SH_PFC_PIN_GROUP(avb_avtp_match_b),
+ }
};
static const char * const audio_clk_groups[] = {
@@ -3809,6 +4055,9 @@ static const char * const avb_groups[] =
"avb_mdio",
"avb_mii",
"avb_gmii",
+};
+
+static const char * const avb_avtp_groups[] = {
"avb_avtp_capture",
"avb_avtp_match",
"avb_avtp_capture_b",
@@ -4183,50 +4432,58 @@ static const char * const vin1_groups[]
"vin1_clk",
};
-static const struct sh_pfc_function pinmux_functions[] = {
- SH_PFC_FUNCTION(audio_clk),
- SH_PFC_FUNCTION(avb),
- SH_PFC_FUNCTION(du0),
- SH_PFC_FUNCTION(du1),
- SH_PFC_FUNCTION(eth),
- SH_PFC_FUNCTION(hscif0),
- SH_PFC_FUNCTION(hscif1),
- SH_PFC_FUNCTION(hscif2),
- SH_PFC_FUNCTION(i2c0),
- SH_PFC_FUNCTION(i2c1),
- SH_PFC_FUNCTION(i2c2),
- SH_PFC_FUNCTION(i2c3),
- SH_PFC_FUNCTION(i2c4),
- SH_PFC_FUNCTION(intc),
- SH_PFC_FUNCTION(mmc),
- SH_PFC_FUNCTION(msiof0),
- SH_PFC_FUNCTION(msiof1),
- SH_PFC_FUNCTION(msiof2),
- SH_PFC_FUNCTION(qspi),
- SH_PFC_FUNCTION(scif0),
- SH_PFC_FUNCTION(scif1),
- SH_PFC_FUNCTION(scif2),
- SH_PFC_FUNCTION(scif3),
- SH_PFC_FUNCTION(scif4),
- SH_PFC_FUNCTION(scif5),
- SH_PFC_FUNCTION(scifa0),
- SH_PFC_FUNCTION(scifa1),
- SH_PFC_FUNCTION(scifa2),
- SH_PFC_FUNCTION(scifa3),
- SH_PFC_FUNCTION(scifa4),
- SH_PFC_FUNCTION(scifa5),
- SH_PFC_FUNCTION(scifb0),
- SH_PFC_FUNCTION(scifb1),
- SH_PFC_FUNCTION(scifb2),
- SH_PFC_FUNCTION(scif_clk),
- SH_PFC_FUNCTION(sdhi0),
- SH_PFC_FUNCTION(sdhi1),
- SH_PFC_FUNCTION(sdhi2),
- SH_PFC_FUNCTION(ssi),
- SH_PFC_FUNCTION(usb0),
- SH_PFC_FUNCTION(usb1),
- SH_PFC_FUNCTION(vin0),
- SH_PFC_FUNCTION(vin1),
+static const struct {
+ struct sh_pfc_function common[43];
+ struct sh_pfc_function r8a7794[1];
+} pinmux_functions = {
+ .common = {
+ SH_PFC_FUNCTION(audio_clk),
+ SH_PFC_FUNCTION(avb),
+ SH_PFC_FUNCTION(du0),
+ SH_PFC_FUNCTION(du1),
+ SH_PFC_FUNCTION(eth),
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(hscif2),
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c4),
+ SH_PFC_FUNCTION(intc),
+ SH_PFC_FUNCTION(mmc),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(qspi),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif5),
+ SH_PFC_FUNCTION(scifa0),
+ SH_PFC_FUNCTION(scifa1),
+ SH_PFC_FUNCTION(scifa2),
+ SH_PFC_FUNCTION(scifa3),
+ SH_PFC_FUNCTION(scifa4),
+ SH_PFC_FUNCTION(scifa5),
+ SH_PFC_FUNCTION(scifb0),
+ SH_PFC_FUNCTION(scifb1),
+ SH_PFC_FUNCTION(scifb2),
+ SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(ssi),
+ SH_PFC_FUNCTION(usb0),
+ SH_PFC_FUNCTION(usb1),
+ SH_PFC_FUNCTION(vin0),
+ SH_PFC_FUNCTION(vin1),
+ },
+ .r8a7794 = {
+ SH_PFC_FUNCTION(avb_avtp),
+ }
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -5012,24 +5269,24 @@ static const struct pinmux_cfg_reg pinmu
2, 1) {
/* SEL_ADG [2] */
FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
- /* SEL_ADI [1] */
+ /* SEL_ADI [1] (R8A7794 only) */
FN_SEL_ADI_0, FN_SEL_ADI_1,
/* SEL_CAN [2] */
FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
- /* SEL_DARC [3] */
+ /* SEL_DARC [3] (R8A7794 only) */
FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
FN_SEL_DARC_4, 0, 0, 0,
- /* SEL_DR0 [1] */
+ /* SEL_DR0 [1] (R8A7794 only) */
FN_SEL_DR0_0, FN_SEL_DR0_1,
- /* SEL_DR1 [1] */
+ /* SEL_DR1 [1] (R8A7794 only)*/
FN_SEL_DR1_0, FN_SEL_DR1_1,
- /* SEL_DR2 [1] */
+ /* SEL_DR2 [1] (R8A7794 only) */
FN_SEL_DR2_0, FN_SEL_DR2_1,
- /* SEL_DR3 [1] */
+ /* SEL_DR3 [1] (R8A7794 only) */
FN_SEL_DR3_0, FN_SEL_DR3_1,
/* SEL_ETH [1] */
FN_SEL_ETH_0, FN_SEL_ETH_1,
- /* SLE_FSN [1] */
+ /* SEL_FSN [1] (R8A7794 only) */
FN_SEL_FSN_0, FN_SEL_FSN_1,
/* SEL_IC200 [3] */
FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
@@ -5054,7 +5311,7 @@ static const struct pinmux_cfg_reg pinmu
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
2, 2, 2, 1, 1, 2) {
- /* SEL_IEB [2] */
+ /* SEL_IEB [2] (R8A7794 only) */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
/* SEL_IIC0 [2] */
FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
@@ -5066,9 +5323,9 @@ static const struct pinmux_cfg_reg pinmu
FN_SEL_MSI2_0, FN_SEL_MSI2_1,
/* SEL_RAD [1] */
FN_SEL_RAD_0, FN_SEL_RAD_1,
- /* SEL_RCN [1] */
+ /* SEL_RCN [1] (R8A7794 only) */
FN_SEL_RCN_0, FN_SEL_RCN_1,
- /* SEL_RSP [1] */
+ /* SEL_RSP [1] (R8A7794 only) */
FN_SEL_RSP_0, FN_SEL_RSP_1,
/* SEL_SCIFA0 [2] */
FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
@@ -5085,11 +5342,11 @@ static const struct pinmux_cfg_reg pinmu
/* SEL_SCIFA5 [2] */
FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
FN_SEL_SCIFA5_3,
- /* SEL_SPDM [1] */
+ /* SEL_SPDM [1] (R8A7794 only) */
FN_SEL_SPDM_0, FN_SEL_SPDM_1,
/* SEL_TMU [1] */
FN_SEL_TMU_0, FN_SEL_TMU_1,
- /* SEL_TSIF0 [2] */
+ /* SEL_TSIF0 [2] (R8A7794 only) */
FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
/* SEL_CAN0 [2] */
FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
@@ -5099,7 +5356,7 @@ static const struct pinmux_cfg_reg pinmu
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
/* SEL_HSCIF1 [1] */
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
- /* SEL_RDS [2] */
+ /* SEL_RDS [2] (R8A7794 only) */
FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
@@ -5185,6 +5442,28 @@ static const struct sh_pfc_soc_operation
.pin_to_pocctrl = r8a7794_pin_to_pocctrl,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A7745
+const struct sh_pfc_soc_info r8a7745_pinmux_info = {
+ .name = "r8a77450_pfc",
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
+
+#ifdef CONFIG_PINCTRL_PFC_R8A7794
const struct sh_pfc_soc_info r8a7794_pinmux_info = {
.name = "r8a77940_pfc",
.ops = &r8a7794_pinmux_ops,
@@ -5194,13 +5473,16 @@ const struct sh_pfc_soc_info r8a7794_pin
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
- .groups = pinmux_groups,
- .nr_groups = ARRAY_SIZE(pinmux_groups),
- .functions = pinmux_functions,
- .nr_functions = ARRAY_SIZE(pinmux_functions),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
+ ARRAY_SIZE(pinmux_groups.r8a7794),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
+ ARRAY_SIZE(pinmux_functions.r8a7794),
.cfg_regs = pinmux_config_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
+#endif
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/sh_pfc.h
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -260,6 +260,7 @@ extern const struct sh_pfc_soc_info emev
extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
^ permalink raw reply
* Re: [PATCH v12.6 08/11] devicetree: power: bq27xxx: Add monitored-battery documentation
From: Rob Herring @ 2017-04-13 20:15 UTC (permalink / raw)
To: Liam Breck
Cc: Andrew F. Davis, linux-pm, devicetree, Matt Ranostay, Liam Breck
In-Reply-To: <20170410050712.930-5-liam@networkimprov.net>
On Sun, Apr 09, 2017 at 10:07:09PM -0700, Liam Breck wrote:
> From: Liam Breck <kernel@networkimprov.net>
>
> Document monitored-battery = <&battery_node>
>
> Cc: Rob Herring <robh@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Matt Ranostay <matt@ranostay.consulting>
> Signed-off-by: Liam Breck <kernel@networkimprov.net>
> ---
> .../devicetree/bindings/power/supply/bq27xxx.txt | 31 +++++++++++++++++-----
> 1 file changed, 24 insertions(+), 7 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v5 1/4] gpio: mvebu: Add limited PWM support
From: Rob Herring @ 2017-04-13 20:14 UTC (permalink / raw)
To: Ralph Sennhauser
Cc: Thierry Reding, Andrew Lunn, Linus Walleij, Alexandre Courbot,
Mark Rutland, Jason Cooper, Gregory Clement,
Sebastian Hesselbarth, Russell King,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170409180931.4884-2-ralph.sennhauser-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Sun, Apr 09, 2017 at 08:09:27PM +0200, Ralph Sennhauser wrote:
> From: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
>
> Armada 370/XP devices can 'blink' GPIO lines with a configurable on
> and off period. This can be modelled as a PWM.
>
> However, there are only two sets of PWM configuration registers for
> all the GPIO lines. This driver simply allows a single GPIO line per
> GPIO chip of 32 lines to be used as a PWM. Attempts to use more return
> EBUSY.
>
> Due to the interleaving of registers it is not simple to separate the
> PWM driver from the GPIO driver. Thus the GPIO driver has been
> extended with a PWM driver.
>
> Signed-off-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> URL: https://patchwork.ozlabs.org/patch/427287/
> URL: https://patchwork.ozlabs.org/patch/427295/
> [Ralph Sennhauser:
> * Port forward
> * Merge PWM portion into gpio-mvebu.c
> * Switch to atomic PWM API
> * Add new compatible string marvell,armada-370-xp-gpio
> * Update and merge documentation patch
> * Update MAINTAINERS]
> Signed-off-by: Ralph Sennhauser <ralph.sennhauser-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Tested-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> ---
> .../devicetree/bindings/gpio/gpio-mvebu.txt | 32 ++
> MAINTAINERS | 2 +
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> drivers/gpio/gpio-mvebu.c | 324 ++++++++++++++++++++-
> 3 files changed, 346 insertions(+), 12 deletions(-)
--
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^ permalink raw reply
* [PATCH v3] pinctrl: sh-pfc: r8a7791: add R8A7743 support
From: Sergei Shtylyov @ 2017-04-13 20:13 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Laurent Pinchart, Geert Uytterhoeven,
Linus Walleij, devicetree, linux-renesas-soc, linux-gpio
Cc: Sergei Shtylyov
[-- Attachment #1: pinctrl-sh-pfc-r8a7791-add-R8A7743-support-v3.patch --]
[-- Type: text/plain, Size: 122227 bytes --]
Renesas RZ/G1M (R8A7743) is pin compatible with R-Car M2-W/N (R8A7791/3),
however it doesn't have several automotive specific peripherals. Annotate
all the items that only exist on the R-Car SoCs and only supply the pin
groups/functions existing on a given SoC...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git'
repo plus 4 R8A7791 PFC fixes and the "grand I2C rename" patch...
Changes in version 3:
- updated the PFC bindings.
Changes in version 2:
- switch to supplying exactly the groups/functions existing on a given SoC,
update the patch descriptions accordingly;
- resolved rejects due to the "grand I2C rename" patch being updated.
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1
drivers/pinctrl/sh-pfc/Kconfig | 5
drivers/pinctrl/sh-pfc/Makefile | 1
drivers/pinctrl/sh-pfc/core.c | 6
drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 1889 +++++-----
drivers/pinctrl/sh-pfc/sh_pfc.h | 1
6 files changed, 1023 insertions(+), 880 deletions(-)
Index: linux-pinctrl/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
===================================================================
--- linux-pinctrl.orig/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ linux-pinctrl/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -13,6 +13,7 @@ Required Properties:
- "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
+ - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/Kconfig
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/Kconfig
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/Kconfig
@@ -34,6 +34,11 @@ config PINCTRL_PFC_R8A7740
depends on ARCH_R8A7740
select PINCTRL_SH_PFC_GPIO
+config PINCTRL_PFC_R8A7743
+ def_bool y
+ depends on ARCH_R8A7743
+ select PINCTRL_SH_PFC
+
config PINCTRL_PFC_R8A7778
def_bool y
depends on ARCH_R8A7778
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/Makefile
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/Makefile
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpi
obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/core.c
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/core.c
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/core.c
@@ -485,6 +485,12 @@ static const struct of_device_id sh_pfc_
.data = &r8a7740_pinmux_info,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7743
+ {
+ .compatible = "renesas,pfc-r8a7743",
+ .data = &r8a7743_pinmux_info,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7778
{
.compatible = "renesas,pfc-r8a7778",
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -1,8 +1,8 @@
/*
- * r8a7791 processor support - PFC hardware block.
+ * r8a7791/r8a7743 processor support - PFC hardware block.
*
* Copyright (C) 2013 Renesas Electronics Corporation
- * Copyright (C) 2014-2015 Cogent Embedded, Inc.
+ * Copyright (C) 2014-2017 Cogent Embedded, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
@@ -129,11 +129,12 @@ enum {
FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
- FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
- FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
- FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
- FN_A15, FN_BPFCLK_C,
- FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
+ FN_A12, FN_FMCLK /* R8A779x only */, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
+ FN_A13, FN_ATAG0_N_C, FN_BPFCLK /* R8A779x only */, FN_MSIOF1_SS1_D,
+ FN_A14, FN_ATADIR0_N_C, FN_FMIN /* R8A779x only */,
+ FN_FMIN_C /* R8A779x only */, FN_MSIOF1_SYNC_D,
+ FN_A15, FN_BPFCLK_C /* R8A779x only */,
+ FN_A16, FN_DREQ2_B, FN_FMCLK_C /* R8A779x only */, FN_SCIFA1_SCK_B,
FN_A17, FN_DACK2_B, FN_I2C0_SDA_C,
FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
@@ -141,8 +142,9 @@ enum {
FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
FN_A20, FN_SPCLK,
FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
- FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
- FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
+ FN_A22, FN_MISO_IO1, FN_FMCLK_B /* R8A779x only */, FN_TX0,
+ FN_SCIFA0_TXD,
+ FN_A23, FN_IO2, FN_BPFCLK_B /* R8A779x only */, FN_RX0, FN_SCIFA0_RXD,
FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL,
@@ -157,13 +159,14 @@ enum {
FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
- FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
+ FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B /* R8A779x only */, FN_SCIFB0_RXD_B,
+ FN_DREQ1_D,
FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
FN_DREQ0, FN_PWM3, FN_TPU_TO3,
- FN_DACK0, FN_DRACK0, FN_REMOCON,
- FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
+ FN_DACK0, FN_DRACK0, FN_REMOCON /* R8A779x only */,
+ FN_SPEEDIN /* R8A779x only */, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
@@ -171,138 +174,164 @@ enum {
/* IPSR4 */
FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C,
- FN_GLO_I0_D,
- FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
+ FN_GLO_I0_D /* R8A779x only */,
+ FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C,
+ FN_GLO_I1_D /* R8A779x only */,
FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
- FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
- FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
- FN_GLO_Q1_D, FN_HCTS1_N_E,
- FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
+ FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B /* R8A779x only */,
+ FN_GLO_Q0_D /* R8A779x only */, FN_HSCK1_E,
+ FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B /* R8A779x only */, FN_RX2_E,
+ FN_GLO_Q1_D /* R8A779x only */, FN_HCTS1_N_E,
+ FN_SSI_SDATA2, FN_GPS_MAG_B /* R8A779x only */, FN_TX2_E, FN_HRTS1_N_E,
FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
- FN_SSI_SCK4, FN_GLO_SS_D,
- FN_SSI_WS4, FN_GLO_RFON_D,
+ FN_SSI_SCK4, FN_GLO_SS_D /* R8A779x only */,
+ FN_SSI_WS4, FN_GLO_RFON_D /* R8A779x only */,
FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
- FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
+ FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0,
+ FN_GLO_I0 /* R8A779x only */,
FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
/* IPSR5 */
- FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
+ FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1 /* R8A779x only */,
FN_MSIOF2_TXD_D, FN_VI1_R3_B,
- FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
- FN_MSIOF2_SS1_D, FN_VI1_R4_B,
- FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
- FN_MSIOF2_RXD_D, FN_VI1_R5_B,
- FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
- FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
- FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
- FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
- FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
- FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
- FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
- FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
+ FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0,
+ FN_GLO_Q0 /* R8A779x only */, FN_MSIOF2_SS1_D, FN_VI1_R4_B,
+ FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0,
+ FN_GLO_Q1 /* R8A779x only */, FN_MSIOF2_RXD_D, FN_VI1_R5_B,
+ FN_SSI_WS6, FN_GLO_SCLK /* R8A779x only */, FN_MSIOF2_SS2_D,
+ FN_VI1_R6_B,
+ FN_SSI_SDATA6, FN_STP_IVCXO27_0_B /* R8A779x only */,
+ FN_GLO_SDATA /* R8A779x only */, FN_VI1_R7_B,
+ FN_SSI_SCK78, FN_STP_ISCLK_0_B /* R8A779x only */,
+ FN_GLO_SS /* R8A779x only */,
+ FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B /* R8A779x only */,
+ FN_GLO_RFON /* R8A779x only */,
+ FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B /* R8A779x only */,
+ FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B /* R8A779x only */,
+ FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D /* R8A779x only */,
+ FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D /* R8A779x only */,
FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
/* IPSR6 */
- FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
- FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
+ FN_AUDIO_CLKB, FN_STP_OPWM_0_B /* R8A779x only */, FN_MSIOF1_SCK_B,
+ FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E /* R8A779x only */,
FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
- FN_SCIFA2_RXD, FN_FMIN_E,
+ FN_SCIFA2_RXD, FN_FMIN_E /* R8A779x only */,
FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
- FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
- FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
- FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
- FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
- FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
+ FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N /* R8A779x only */,
+ FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N /* R8A779x only */,
+ FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N /* R8A779x only */,
+ FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E,
+ FN_INTC_IRQ3_N /* R8A779x only */,
+ FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
+ FN_INTC_IRQ4_N /* R8A779x only */,
FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
- FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
- FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
+ FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C /* R8A779x only */,
+ FN_GPS_CLK_D /* R8A779x only */,
+ FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
+ FN_GPS_SIGN_C /* R8A779x only */, FN_GPS_SIGN_D /* R8A779x only */,
/* IPSR7 */
- FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
- FN_SCIF_CLK_B, FN_GPS_MAG_D,
- FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
+ FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D,
+ FN_GPS_MAG_C /* R8A779x only */,
+ FN_SCIF_CLK_B, FN_GPS_MAG_D /* R8A779x only */,
+ FN_DU1_DR0, FN_LCDOUT0 /* R8A779x only */, FN_VI1_DATA0_B, FN_TX0_B,
FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
- FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
+ FN_DU1_DR1, FN_LCDOUT1 /* R8A779x only */, FN_VI1_DATA1_B, FN_RX0_B,
FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
- FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
- FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
- FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
- FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
- FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
- FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
- FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
+ FN_DU1_DR2, FN_LCDOUT2 /* R8A779x only */, FN_SSI_SCK0129_B,
+ FN_DU1_DR3, FN_LCDOUT3 /* R8A779x only */, FN_SSI_WS0129_B,
+ FN_DU1_DR4, FN_LCDOUT4 /* R8A779x only */, FN_SSI_SDATA0_B,
+ FN_DU1_DR5, FN_LCDOUT5 /* R8A779x only */, FN_SSI_SCK1_B,
+ FN_DU1_DR6, FN_LCDOUT6 /* R8A779x only */, FN_SSI_WS1_B,
+ FN_DU1_DR7, FN_LCDOUT7 /* R8A779x only */, FN_SSI_SDATA1_B,
+ FN_DU1_DG0, FN_LCDOUT8 /* R8A779x only */, FN_VI1_DATA2_B, FN_TX1_B,
FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
- FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
+ FN_DU1_DG1, FN_LCDOUT9 /* R8A779x only */, FN_VI1_DATA3_B, FN_RX1_B,
FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
- FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
- FN_SCIFA1_SCK, FN_SSI_SCK78_B,
+ FN_DU1_DG2, FN_LCDOUT10 /* R8A779x only */, FN_VI1_DATA4_B,
+ FN_SCIF1_SCK_B, FN_SCIFA1_SCK, FN_SSI_SCK78_B,
/* IPSR8 */
- FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
- FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
+ FN_DU1_DG3, FN_LCDOUT11 /* R8A779x only */, FN_VI1_DATA5_B,
+ FN_SSI_WS78_B,
+ FN_DU1_DG4, FN_LCDOUT12 /* R8A779x only */, FN_VI1_DATA6_B, FN_HRX0_B,
FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
- FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
+ FN_DU1_DG5, FN_LCDOUT13 /* R8A779x only */, FN_VI1_DATA7_B,
+ FN_HCTS0_N_B,
FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
- FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
+ FN_DU1_DG6, FN_LCDOUT14 /* R8A779x only */, FN_HRTS0_N_B,
FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
- FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
- FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
+ FN_DU1_DG7, FN_LCDOUT15 /* R8A779x only */, FN_HTX0_B,
+ FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
+ FN_DU1_DB0, FN_LCDOUT16 /* R8A779x only */, FN_VI1_CLK_B, FN_TX2_B,
FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
- FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
+ FN_DU1_DB1, FN_LCDOUT17 /* R8A779x only */, FN_VI1_HSYNC_N_B, FN_RX2_B,
FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
- FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
- FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
- FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
- FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
- FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
+ FN_DU1_DB2, FN_LCDOUT18 /* R8A779x only */, FN_VI1_VSYNC_N_B,
+ FN_SCIF2_SCK_B, FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
+ FN_DU1_DB3, FN_LCDOUT19 /* R8A779x only */, FN_VI1_CLKENB_B,
+ FN_DU1_DB4, FN_LCDOUT20 /* R8A779x only */, FN_VI1_FIELD_B, FN_CAN1_RX,
+ FN_DU1_DB5, FN_LCDOUT21 /* R8A779x only */, FN_TX3, FN_SCIFA3_TXD,
+ FN_CAN1_TX,
/* IPSR9 */
- FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
- FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
- FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
- FN_DU1_DOTCLKOUT0, FN_QCLK,
- FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
+ FN_DU1_DB6, FN_LCDOUT22 /* R8A779x only */, FN_I2C3_SCL_C, FN_RX3,
+ FN_SCIFA3_RXD,
+ FN_DU1_DB7, FN_LCDOUT23 /* R8A779x only */, FN_I2C3_SDA_C, FN_SCIF3_SCK,
+ FN_SCIFA3_SCK,
+ FN_DU1_DOTCLKIN, FN_QSTVA_QVS /* R8A779x only */,
+ FN_DU1_DOTCLKOUT0, FN_QCLK /* R8A779x only */,
+ FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE /* R8A779x only */, FN_CAN0_TX,
FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
- FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
- FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
- FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
+ FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS /* R8A779x only */,
+ FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE /* R8A779x only */,
+ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE /* R8A779x only */,
FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
- FN_DU1_DISP, FN_QPOLA,
- FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
+ FN_DU1_DISP, FN_QPOLA /* R8A779x only */,
+ FN_DU1_CDE, FN_QPOLB /* R8A779x only */, FN_PWM4_B,
FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
- FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
- FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
+ FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C /* R8A779x only */,
+ FN_I2C4_SCL, FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
/* IPSR10 */
- FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
+ FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C /* R8A779x only */,
+ FN_I2C4_SDA,
FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
- FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
+ FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C /* R8A779x only */,
+ FN_I2C3_SCL_B,
FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
- FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
+ FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C /* R8A779x only */,
+ FN_I2C3_SDA_B,
FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
- FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
+ FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C /* R8A779x only */,
FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
- FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
+ FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C /* R8A779x only */,
+ FN_FMCLK_D /* R8A779x only */,
FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
- FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
- FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
- FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
+ FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D /* R8A779x only */,
+ FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D /* R8A779x only */,
+ FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B /* R8A779x only */,
FN_TS_SDATA0_C, FN_ATACS11_N,
- FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
+ FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B /* R8A779x only */,
FN_TS_SCK0_C, FN_ATAG1_N,
- FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
- FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
- FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
+ FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B /* R8A779x only */, FN_TS_SDEN0_C,
+ FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B /* R8A779x only */,
+ FN_TS_SPSYNC0_C,
+ FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B /* R8A779x only */, FN_TX0_C,
+ FN_I2C1_SCL_D,
/* IPSR11 */
- FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D,
- FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
- FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
+ FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B /* R8A779x only */, FN_RX0_C,
+ FN_I2C1_SDA_D,
+ FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B /* R8A779x only */, FN_TX1_C,
+ FN_I2C4_SCL_B,
+ FN_VI0_R7, FN_GLO_RFON_B /* R8A779x only */, FN_RX1_C, FN_CAN0_RX_E,
FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
@@ -327,31 +356,35 @@ enum {
FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
- FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
- FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
- FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
- FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
- FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
- FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
- FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
+ FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C /* R8A779x only */,
+ FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C /* R8A779x only */,
+ FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C /* R8A779x only */,
+ FN_STP_IVCXO27_0 /* R8A779x only */, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
+ FN_ADIDATA_B /* R8A779x only */, FN_MSIOF0_SYNC_C,
+ FN_STP_ISCLK_0 /* R8A779x only */, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
+ FN_ADICS_SAMP_B /* R8A779x only */, FN_MSIOF0_SCK_C,
/* IPSR13 */
- FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
- FN_ADICLK_B, FN_MSIOF0_SS1_C,
- FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
- FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
- FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
- FN_ADICHS2_B, FN_MSIOF0_TXD_C,
+ FN_STP_ISD_0 /* R8A779x only */, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
+ FN_ADICLK_B /* R8A779x only */, FN_MSIOF0_SS1_C,
+ FN_STP_ISEN_0 /* R8A779x only */, FN_AVB_TX_CLK,
+ FN_ADICHS0_B /* R8A779x only */, FN_MSIOF0_SS2_C,
+ FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B /* R8A779x only */,
+ FN_MSIOF0_RXD_C,
+ FN_STP_OPWM_0 /* R8A779x only */, FN_AVB_GTX_CLK, FN_PWM0_B,
+ FN_ADICHS2_B /* R8A779x only */, FN_MSIOF0_TXD_C,
FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
- FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
+ FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B /* R8A779x only */, FN_CAN0_RX_F,
FN_SCIFA5_TXD_B, FN_TX3_C,
- FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
+ FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B /* R8A779x only */, FN_CAN0_TX_F,
FN_SCIFA5_RXD_B, FN_RX3_C,
- FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
- FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
- FN_SD1_DATA3, FN_IERX_B,
+ FN_SD1_CMD, FN_REMOCON_B /* R8A779x only */,
+ FN_SD1_DATA0, FN_SPEEDIN_B /* R8A779x only */,
+ FN_SD1_DATA1, FN_IETX_B /* R8A779x only */,
+ FN_SD1_DATA2, FN_IECLK_B /* R8A779x only */,
+ FN_SD1_DATA3, FN_IERX_B /* R8A779x only */,
FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
/* IPSR14 */
@@ -361,38 +394,53 @@ enum {
FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
- FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
- FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
- FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
- FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
- FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
+ FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA /* R8A779x only */, FN_VI1_CLK_C,
+ FN_VI1_G0_B,
+ FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP /* R8A779x only */,
+ FN_VI1_CLKENB_C, FN_VI1_G1_B,
+ FN_MSIOF0_TXD, FN_ADICLK /* R8A779x only */, FN_VI1_FIELD_C,
+ FN_VI1_G2_B,
+ FN_MSIOF0_RXD, FN_ADICHS0 /* R8A779x only */, FN_VI1_DATA0_C,
+ FN_VI1_G3_B,
+ FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1 /* R8A779x only */, FN_TX0_E,
FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B,
- FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
+ FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2 /* R8A779x only */, FN_RX0_E,
FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B,
/* IPSR15 */
- FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
- FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
- FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
- FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
+ FN_SIM0_RST /* R8A779x only */, FN_IETX /* R8A779x only */,
+ FN_CAN1_TX_D,
+ FN_SIM0_CLK /* R8A779x only */, FN_IECLK /* R8A779x only */,
+ FN_CAN_CLK_C,
+ FN_SIM0_D /* R8A779x only */, FN_IERX /* R8A779x only */, FN_CAN1_RX_D,
+ FN_GPS_CLK /* R8A779x only */, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
FN_PWM5_B, FN_SCIFA3_TXD_C,
- FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
+ FN_GPS_SIGN /* R8A779x only */, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
FN_VI1_G6_B, FN_SCIFA3_RXD_C,
- FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
+ FN_GPS_MAG /* R8A779x only */, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
FN_VI1_G7_B, FN_SCIFA3_SCK_C,
- FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
- FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
- FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
+ FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C /* R8A779x only */, FN_TCLK1,
+ FN_VI1_DATA1_C,
+ FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C /* R8A779x only */,
+ FN_VI1_DATA2_C,
+ FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C /* R8A779x only */, FN_CAN_CLK,
FN_TCLK2, FN_VI1_DATA3_C,
- FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
- FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
+ FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C /* R8A779x only */, FN_CAN0_RX_B,
+ FN_VI1_DATA4_C,
+ FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C /* R8A779x only */, FN_CAN0_TX_B,
+ FN_VI1_DATA5_C,
/* IPSR16 */
- FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
- FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
- FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
- FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
- FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
+ FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C /* R8A779x only */,
+ FN_VI1_DATA6_C,
+ FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C /* R8A779x only */,
+ FN_VI1_DATA7_C,
+ FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK /* R8A779x only */,
+ FN_GLO_RFON_C /* R8A779x only */,
+ FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG /* R8A779x only */,
+ FN_CAN1_TX_B,
+ FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT /* R8A779x only */,
+ FN_CAN1_RX_B,
/* MOD_SEL */
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
@@ -422,12 +470,14 @@ enum {
FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
FN_SEL_ADG_0, FN_SEL_ADG_1,
- FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
+ /* R8A779x only */ FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+ FN_SEL_FM_4,
FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
- FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
+ /* R8A779x only */ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
+ FN_SEL_GPS_3,
FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
- FN_SEL_SIM_0, FN_SEL_SIM_1,
+ /* R8A779x only */ FN_SEL_SIM_0, FN_SEL_SIM_1,
FN_SEL_SSI8_0, FN_SEL_SSI8_1,
/* MOD_SEL3 */
@@ -438,7 +488,7 @@ enum {
FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2,
FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+ /* R8A779x only */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
FN_SEL_MMC_0, FN_SEL_MMC_1,
FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
@@ -451,16 +501,16 @@ enum {
FN_SEL_SOF1_4,
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
- FN_SEL_RAD_0, FN_SEL_RAD_1,
- FN_SEL_RCN_0, FN_SEL_RCN_1,
- FN_SEL_RSP_0, FN_SEL_RSP_1,
+ /* R8A779x only */ FN_SEL_RAD_0, FN_SEL_RAD_1,
+ /* R8A779x only */ FN_SEL_RCN_0, FN_SEL_RCN_1,
+ /* R8A779x only */ FN_SEL_RSP_0, FN_SEL_RSP_1,
FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
FN_SEL_SCIF2_4,
FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
FN_SEL_SOF2_4,
FN_SEL_SSI1_0, FN_SEL_SSI1_1,
FN_SEL_SSI0_0, FN_SEL_SSI0_1,
- FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
+ /* R8A779x only */ FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
@@ -493,11 +543,15 @@ enum {
A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK,
A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK,
- A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK,
- A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
- A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
- A15_MARK, BPFCLK_C_MARK,
- A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
+ A12_MARK, FMCLK_MARK /* R8A779x only */, I2C3_SDA_D_MARK,
+ MSIOF1_SCK_D_MARK,
+ A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK /* R8A779x only */,
+ MSIOF1_SS1_D_MARK,
+ A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK /* R8A779x only */,
+ FMIN_C_MARK /* R8A779x only */, MSIOF1_SYNC_D_MARK,
+ A15_MARK, BPFCLK_C_MARK /* R8A779x only */,
+ A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK /* R8A779x only */,
+ SCIFA1_SCK_B_MARK,
A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK,
A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
@@ -506,8 +560,10 @@ enum {
SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
A20_MARK, SPCLK_MARK,
A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
- A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
- A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
+ A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK /* R8A779x only */, TX0_MARK,
+ SCIFA0_TXD_MARK,
+ A23_MARK, IO2_MARK, BPFCLK_B_MARK /* R8A779x only */, RX0_MARK,
+ SCIFA0_RXD_MARK,
A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
RX1_MARK, SCIFA1_RXD_MARK,
@@ -524,15 +580,15 @@ enum {
SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
- RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
+ RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK /* R8A779x only */,
SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
- DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
- SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
- SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
+ DACK0_MARK, DRACK0_MARK, REMOCON_MARK /* R8A779x only */,
+ SPEEDIN_MARK /* R8A779x only */, HSCK0_C_MARK, HSCK2_C_MARK,
+ SCIFB0_SCK_B_MARK, SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
@@ -541,149 +597,166 @@ enum {
/* IPSR4 */
SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK,
SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK,
- MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
+ MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK /* R8A779x only */,
SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK,
- MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
+ MSIOF2_TXD_C_MARK, GLO_I1_D_MARK /* R8A779x only */,
SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK,
- SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK,
- HSCK1_E_MARK,
- SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
- GLO_Q1_D_MARK, HCTS1_N_E_MARK,
- SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
+ SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK /* R8A779x only */,
+ GLO_Q0_D_MARK /* R8A779x only */, HSCK1_E_MARK,
+ SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK /* R8A779x only */,
+ RX2_E_MARK, GLO_Q1_D_MARK /* R8A779x only */, HCTS1_N_E_MARK,
+ SSI_SDATA2_MARK, GPS_MAG_B_MARK /* R8A779x only */, TX2_E_MARK,
+ HRTS1_N_E_MARK,
SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
- SSI_SCK4_MARK, GLO_SS_D_MARK,
- SSI_WS4_MARK, GLO_RFON_D_MARK,
+ SSI_SCK4_MARK, GLO_SS_D_MARK /* R8A779x only */,
+ SSI_WS4_MARK, GLO_RFON_D_MARK /* R8A779x only */,
SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
- SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
- MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
+ SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK,
+ GLO_I0_MARK /* R8A779x only */, MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
/* IPSR5 */
- SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
- MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
- SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
- MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
- SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
- MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
- SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
- SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
- SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
- SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
- SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
- SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
- SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
- SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
+ SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK,
+ GLO_I1_MARK /* R8A779x only */, MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
+ SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK,
+ GLO_Q0_MARK /* R8A779x only */, MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
+ SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK,
+ GLO_Q1_MARK /* R8A779x only */, MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
+ SSI_WS6_MARK, GLO_SCLK_MARK /* R8A779x only */, MSIOF2_SS2_D_MARK,
+ VI1_R6_B_MARK,
+ SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK /* R8A779x only */,
+ GLO_SDATA_MARK /* R8A779x only */, VI1_R7_B_MARK,
+ SSI_SCK78_MARK, STP_ISCLK_0_B_MARK /* R8A779x only */,
+ GLO_SS_MARK /* R8A779x only */,
+ SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK /* R8A779x only */,
+ GLO_RFON_MARK /* R8A779x only */,
+ SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK /* R8A779x only */,
+ SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK /* R8A779x only */,
+ SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK /* R8A779x only */,
+ SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK,
+ GLO_SDATA_D_MARK /* R8A779x only */,
SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
/* IPSR6 */
- AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
- SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
+ AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK /* R8A779x only */,
+ MSIOF1_SCK_B_MARK, SCIF_CLK_MARK, DVC_MUTE_MARK,
+ BPFCLK_E_MARK /* R8A779x only */,
AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
- SCIFA2_RXD_MARK, FMIN_E_MARK,
+ SCIFA2_RXD_MARK, FMIN_E_MARK /* R8A779x only */,
AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
- IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
- IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
- IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
- IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
+ IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK /* R8A779x only */,
+ IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK /* R8A779x only */,
+ IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK /* R8A779x only */,
+ IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK,
+ INTC_IRQ3_N_MARK /* R8A779x only */,
IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
- MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
+ MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK /* R8A779x only */,
IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
- GPS_CLK_C_MARK, GPS_CLK_D_MARK,
+ GPS_CLK_C_MARK /* R8A779x only */, GPS_CLK_D_MARK /* R8A779x only */,
IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
- GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
+ GPS_SIGN_C_MARK /* R8A779x only */, GPS_SIGN_D_MARK /* R8A779x only */,
/* IPSR7 */
- IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
- SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
- DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
- SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
- DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
- SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
- DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
- DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
- DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
- DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
- DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
- DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
- DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
- SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
- DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
- SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
- DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
- SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
+ IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK,
+ GPS_MAG_C_MARK /* R8A779x only */, SCIF_CLK_B_MARK,
+ GPS_MAG_D_MARK /* R8A779x only */,
+ DU1_DR0_MARK, LCDOUT0_MARK /* R8A779x only */, VI1_DATA0_B_MARK,
+ TX0_B_MARK, SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
+ DU1_DR1_MARK, LCDOUT1_MARK /* R8A779x only */, VI1_DATA1_B_MARK,
+ RX0_B_MARK, SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
+ DU1_DR2_MARK, LCDOUT2_MARK /* R8A779x only */, SSI_SCK0129_B_MARK,
+ DU1_DR3_MARK, LCDOUT3_MARK /* R8A779x only */, SSI_WS0129_B_MARK,
+ DU1_DR4_MARK, LCDOUT4_MARK /* R8A779x only */, SSI_SDATA0_B_MARK,
+ DU1_DR5_MARK, LCDOUT5_MARK /* R8A779x only */, SSI_SCK1_B_MARK,
+ DU1_DR6_MARK, LCDOUT6_MARK /* R8A779x only */, SSI_WS1_B_MARK,
+ DU1_DR7_MARK, LCDOUT7_MARK /* R8A779x only */, SSI_SDATA1_B_MARK,
+ DU1_DG0_MARK, LCDOUT8_MARK /* R8A779x only */, VI1_DATA2_B_MARK,
+ TX1_B_MARK, SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
+ DU1_DG1_MARK, LCDOUT9_MARK /* R8A779x only */, VI1_DATA3_B_MARK,
+ RX1_B_MARK, SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
+ DU1_DG2_MARK, LCDOUT10_MARK /* R8A779x only */, VI1_DATA4_B_MARK,
+ SCIF1_SCK_B_MARK, SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
/* IPSR8 */
- DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
- DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
- SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
- DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
- SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
- DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
+ DU1_DG3_MARK, LCDOUT11_MARK /* R8A779x only */, VI1_DATA5_B_MARK,
+ SSI_WS78_B_MARK,
+ DU1_DG4_MARK, LCDOUT12_MARK /* R8A779x only */, VI1_DATA6_B_MARK,
+ HRX0_B_MARK, SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
+ DU1_DG5_MARK, LCDOUT13_MARK /* R8A779x only */, VI1_DATA7_B_MARK,
+ HCTS0_N_B_MARK, SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
+ DU1_DG6_MARK, LCDOUT14_MARK /* R8A779x only */, HRTS0_N_B_MARK,
SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
- DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
+ DU1_DG7_MARK, LCDOUT15_MARK /* R8A779x only */, HTX0_B_MARK,
SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
- DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
- SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
- DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
- SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
- DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
- SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
- DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
- DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
- DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
+ DU1_DB0_MARK, LCDOUT16_MARK /* R8A779x only */, VI1_CLK_B_MARK,
+ TX2_B_MARK, SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
+ DU1_DB1_MARK, LCDOUT17_MARK /* R8A779x only */, VI1_HSYNC_N_B_MARK,
+ RX2_B_MARK, SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
+ DU1_DB2_MARK, LCDOUT18_MARK /* R8A779x only */, VI1_VSYNC_N_B_MARK,
+ SCIF2_SCK_B_MARK, SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
+ DU1_DB3_MARK, LCDOUT19_MARK /* R8A779x only */, VI1_CLKENB_B_MARK,
+ DU1_DB4_MARK, LCDOUT20_MARK /* R8A779x only */, VI1_FIELD_B_MARK,
+ CAN1_RX_MARK,
+ DU1_DB5_MARK, LCDOUT21_MARK /* R8A779x only */, TX3_MARK,
+ SCIFA3_TXD_MARK, CAN1_TX_MARK,
/* IPSR9 */
- DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
- DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK,
+ DU1_DB6_MARK, LCDOUT22_MARK /* R8A779x only */, I2C3_SCL_C_MARK,
+ RX3_MARK, SCIFA3_RXD_MARK,
+ DU1_DB7_MARK, LCDOUT23_MARK /* R8A779x only */, I2C3_SDA_C_MARK,
SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
- DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
- DU1_DOTCLKOUT0_MARK, QCLK_MARK,
- DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
+ DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK /* R8A779x only */,
+ DU1_DOTCLKOUT0_MARK, QCLK_MARK /* R8A779x only */,
+ DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK /* R8A779x only */, CAN0_TX_MARK,
TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK,
- DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
- DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
- DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
+ DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK /* R8A779x only */,
+ DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK /* R8A779x only */,
+ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK /* R8A779x only */,
CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK,
- DU1_DISP_MARK, QPOLA_MARK,
- DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
+ DU1_DISP_MARK, QPOLA_MARK /* R8A779x only */,
+ DU1_CDE_MARK, QPOLB_MARK /* R8A779x only */, PWM4_B_MARK,
VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
- VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK,
- HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
+ VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK /* R8A779x only */,
+ I2C4_SCL_MARK, HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
/* IPSR10 */
- VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK,
- HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
- VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK,
- HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
- VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK,
- HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
- VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
+ VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK /* R8A779x only */,
+ I2C4_SDA_MARK, HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
+ VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK /* R8A779x only */,
+ I2C3_SCL_B_MARK, HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
+ VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK /* R8A779x only */,
+ I2C3_SDA_B_MARK, HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
+ VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK /* R8A779x only */,
HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
- VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
- CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
- VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
- VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
- VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
+ VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK,
+ FMCLK_D_MARK /* R8A779x only */, CAN0_TX_E_MARK, HTX1_D_MARK,
+ SCIFB0_TXD_D_MARK,
+ VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK /* R8A779x only */,
+ VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK /* R8A779x only */,
+ VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK /* R8A779x only */,
TS_SDATA0_C_MARK, ATACS11_N_MARK,
- VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
+ VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK /* R8A779x only */,
TS_SCK0_C_MARK, ATAG1_N_MARK,
- VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
- VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
- VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK,
- I2C1_SCL_D_MARK,
+ VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK /* R8A779x only */,
+ TS_SDEN0_C_MARK,
+ VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK /* R8A779x only */,
+ TS_SPSYNC0_C_MARK,
+ VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK /* R8A779x only */,
+ TX0_C_MARK, I2C1_SCL_D_MARK,
/* IPSR11 */
- VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK,
- I2C1_SDA_D_MARK,
- VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK,
- VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
- I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
+ VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK /* R8A779x only */,
+ RX0_C_MARK, I2C1_SDA_D_MARK,
+ VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK /* R8A779x only */,
+ TX1_C_MARK, I2C4_SCL_B_MARK,
+ VI0_R7_MARK, GLO_RFON_B_MARK /* R8A779x only */, RX1_C_MARK,
+ CAN0_RX_E_MARK, I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
TX4_B_MARK, SCIFA4_TXD_B_MARK,
VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
@@ -710,31 +783,35 @@ enum {
ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
- ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
- ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
- ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
- STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
- ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
- STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
- ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
+ ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK /* R8A779x only */,
+ ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK /* R8A779x only */,
+ ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK /* R8A779x only */,
+ STP_IVCXO27_0_MARK /* R8A779x only */, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
+ ADIDATA_B_MARK /* R8A779x only */, MSIOF0_SYNC_C_MARK,
+ STP_ISCLK_0_MARK /* R8A779x only */, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
+ ADICS_SAMP_B_MARK /* R8A779x only */, MSIOF0_SCK_C_MARK,
/* IPSR13 */
- STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
- ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
- STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
- STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
- STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
- ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
+ STP_ISD_0_MARK /* R8A779x only */, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
+ ADICLK_B_MARK /* R8A779x only */, MSIOF0_SS1_C_MARK,
+ STP_ISEN_0_MARK /* R8A779x only */, AVB_TX_CLK_MARK,
+ ADICHS0_B_MARK /* R8A779x only */, MSIOF0_SS2_C_MARK,
+ STP_ISSYNC_0_MARK /* R8A779x only */, AVB_COL_MARK,
+ ADICHS1_B_MARK /* R8A779x only */, MSIOF0_RXD_C_MARK,
+ STP_OPWM_0_MARK /* R8A779x only */, AVB_GTX_CLK_MARK, PWM0_B_MARK,
+ ADICHS2_B_MARK /* R8A779x only */, MSIOF0_TXD_C_MARK,
SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
- SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
- SCIFA5_TXD_B_MARK, TX3_C_MARK,
- SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
- SCIFA5_RXD_B_MARK, RX3_C_MARK,
- SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
- SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
- SD1_DATA3_MARK, IERX_B_MARK,
+ SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK /* R8A779x only */,
+ CAN0_RX_F_MARK, SCIFA5_TXD_B_MARK, TX3_C_MARK,
+ SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK /* R8A779x only */,
+ CAN0_TX_F_MARK, SCIFA5_RXD_B_MARK, RX3_C_MARK,
+ SD1_CMD_MARK, REMOCON_B_MARK /* R8A779x only */,
+ SD1_DATA0_MARK, SPEEDIN_B_MARK /* R8A779x only */,
+ SD1_DATA1_MARK, IETX_B_MARK /* R8A779x only */,
+ SD1_DATA2_MARK, IECLK_B_MARK /* R8A779x only */,
+ SD1_DATA3_MARK, IERX_B_MARK /* R8A779x only */,
SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK,
/* IPSR14 */
@@ -746,45 +823,55 @@ enum {
SCIFA5_TXD_C_MARK,
SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK,
SCIFA5_RXD_C_MARK,
- MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
+ MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK /* R8A779x only */,
VI1_CLK_C_MARK, VI1_G0_B_MARK,
- MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
+ MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK /* R8A779x only */,
VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
- MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
- MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
- MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
- VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
- MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
- VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
+ MSIOF0_TXD_MARK, ADICLK_MARK /* R8A779x only */, VI1_FIELD_C_MARK,
+ VI1_G2_B_MARK,
+ MSIOF0_RXD_MARK, ADICHS0_MARK /* R8A779x only */, VI1_DATA0_C_MARK,
+ VI1_G3_B_MARK,
+ MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK /* R8A779x only */,
+ TX0_E_MARK, VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
+ MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK /* R8A779x only */,
+ RX0_E_MARK, VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
/* IPSR15 */
- SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
- SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
- SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
- GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
+ SIM0_RST_MARK /* R8A779x only */, IETX_MARK /* R8A779x only */,
+ CAN1_TX_D_MARK,
+ SIM0_CLK_MARK /* R8A779x only */, IECLK_MARK /* R8A779x only */,
+ CAN_CLK_C_MARK,
+ SIM0_D_MARK /* R8A779x only */, IERX_MARK /* R8A779x only */,
+ CAN1_RX_D_MARK,
+ GPS_CLK_MARK /* R8A779x only */, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
PWM5_B_MARK, SCIFA3_TXD_C_MARK,
- GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
- VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
- GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
- VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
- HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
+ GPS_SIGN_MARK /* R8A779x only */, TX4_C_MARK, SCIFA4_TXD_C_MARK,
+ PWM5_MARK, VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
+ GPS_MAG_MARK /* R8A779x only */, RX4_C_MARK, SCIFA4_RXD_C_MARK,
+ PWM6_MARK, VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
+ HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK /* R8A779x only */,
TCLK1_MARK, VI1_DATA1_C_MARK,
- HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
- HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
- TCLK2_MARK, VI1_DATA3_C_MARK,
- HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
+ HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK /* R8A779x only */,
+ VI1_DATA2_C_MARK,
+ HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK /* R8A779x only */,
+ CAN_CLK_MARK, TCLK2_MARK, VI1_DATA3_C_MARK,
+ HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK /* R8A779x only */,
CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
- HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
+ HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK /* R8A779x only */,
CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
/* IPSR16 */
HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
- GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
+ GLO_SDATA_C_MARK /* R8A779x only */, VI1_DATA6_C_MARK,
HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
- GLO_SS_C_MARK, VI1_DATA7_C_MARK,
- HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
- HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
- HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
+ GLO_SS_C_MARK /* R8A779x only */, VI1_DATA7_C_MARK,
+ HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK /* R8A779x only */,
+ GLO_RFON_C_MARK /* R8A779x only */,
+ HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK /* R8A779x only */,
+ CAN1_TX_B_MARK,
+ HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK /* R8A779x only */,
+ CAN1_RX_B_MARK,
+
PINMUX_MARK_END,
};
@@ -861,23 +948,23 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3),
PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
PINMUX_IPSR_GPSR(IP1_13_11, A12),
- PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
+ PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3),
PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
PINMUX_IPSR_GPSR(IP1_16_14, A13),
PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
- PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
+ PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
PINMUX_IPSR_GPSR(IP1_19_17, A14),
PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
- PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
- PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
+ PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0), /* R8A779x only */
+ PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
PINMUX_IPSR_GPSR(IP1_22_20, A15),
- PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
+ PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2), /* R8A779x only */
PINMUX_IPSR_GPSR(IP1_25_23, A16),
PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
- PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
+ PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
PINMUX_IPSR_GPSR(IP1_28_26, A17),
PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
@@ -900,12 +987,12 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
PINMUX_IPSR_GPSR(IP2_9_7, A22),
PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
- PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
PINMUX_IPSR_GPSR(IP2_12_10, A23),
PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
- PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
PINMUX_IPSR_GPSR(IP2_15_13, A24),
@@ -957,7 +1044,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
- PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
+ PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
@@ -975,8 +1062,8 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
- PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
- PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
+ PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0), /* R8A779x only */
+ PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
@@ -1003,44 +1090,44 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1),
PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1),
PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
- PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3), /* R8A779x only */
PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1),
PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1),
PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
- PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3), /* R8A779x only */
PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1),
PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1),
PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0),
- PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
- PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1), /* R8A779x only */
+ PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3), /* R8A779x only */
PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0),
- PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
- PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3), /* R8A779x only */
PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
- PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
- PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3), /* R8A779x only */
PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
- PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3), /* R8A779x only */
PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
- PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
@@ -1048,88 +1135,88 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
- PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
- PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
- PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
- PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
- PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
- PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1), /* R8A779x */
+ PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0), /* R8A779x only */
PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
- PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
- PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1), /* R8A779x */
+ PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
- PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
- PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1), /* R8A779x only */
+ PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
- PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
- PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1), /* R8A779x */
PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
- PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3), /* R8A779x only */
PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
- PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3), /* R8A779x only */
PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
/* IPSR6 */
PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
- PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
- PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
+ PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4), /* R8A779x only */
PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
- PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
+ PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4), /* R8A779x only */
PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
- PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
+ PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N), /* R8A779x only */
PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
- PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
+ PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N), /* R8A779x only */
PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
- PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
+ PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N), /* R8A779x only */
PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
- PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
+ PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N), /* R8A779x only */
PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
- PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
+ PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N), /* R8A779x only */
PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
@@ -1142,65 +1229,65 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
- PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
- PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2), /* R8A779x only */
+ PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3), /* R8A779x only */
PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
- PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
- PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), /* R8A779x only */
+ PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), /* R8A779x only */
/* IPSR7 */
PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
- PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
- PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3), /* R8A779x only */
PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
- PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
+ PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
- PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
+ PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
- PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
+ PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
- PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
+ PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3), /* R8A779x only */
PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
- PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
+ PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4), /* R8A779x only */
PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
- PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
+ PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5), /* R8A779x only */
PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
- PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
+ PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6), /* R8A779x only */
PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
- PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
+ PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7), /* R8A779x only */
PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
- PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
+ PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8), /* R8A779x only */
PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
- PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
+ PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9), /* R8A779x only */
PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
- PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
+ PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10), /* R8A779x only */
PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
@@ -1208,96 +1295,96 @@ static const u16 pinmux_data[] = {
/* IPSR8 */
PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
- PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
+ PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11), /* R8A779x only */
PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
- PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
+ PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12), /* R8A779x only */
PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
- PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
+ PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13), /* R8A779x only */
PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
- PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
+ PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14), /* R8A779x only */
PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
- PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
+ PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15), /* R8A779x only */
PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
- PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
+ PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16), /* R8A779x only */
PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
- PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
+ PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17), /* R8A779x only */
PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
- PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
+ PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18), /* R8A779x only */
PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
- PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
+ PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19), /* R8A779x only */
PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
- PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
+ PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20), /* R8A779x only */
PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
- PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
+ PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21), /* R8A779x only */
PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
/* IPSR9 */
PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
- PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
+ PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22), /* R8A779x only */
PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2),
PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
- PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
+ PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23), /* R8A779x only */
PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2),
PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
- PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
+ PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS), /* R8A779x only */
PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
- PINMUX_IPSR_GPSR(IP9_7, QCLK),
+ PINMUX_IPSR_GPSR(IP9_7, QCLK), /* R8A779x only */
PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
- PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
+ PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE), /* R8A779x only */
PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1),
PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
- PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
+ PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS), /* R8A779x only */
PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
- PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
+ PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE), /* R8A779x only */
PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
- PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
+ PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE), /* R8A779x only */
PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1),
PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
- PINMUX_IPSR_GPSR(IP9_16, QPOLA),
+ PINMUX_IPSR_GPSR(IP9_16, QPOLA), /* R8A779x only */
PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
- PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
+ PINMUX_IPSR_GPSR(IP9_18_17, QPOLB), /* R8A779x only */
PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
@@ -1320,7 +1407,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0),
- PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), /* R8A779x */
PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0),
PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
@@ -1329,81 +1416,81 @@ static const u16 pinmux_data[] = {
/* IPSR10 */
PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0),
- PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0),
PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
- PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1),
PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
- PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1),
PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
- PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2), /* R8A779x */
PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
- PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
- PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
+ PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2), /* R8A779x */
+ PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3), /* R8A779x only */
PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
- PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
+ PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3), /* R8A779x only */
PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
- PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
+ PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3), /* R8A779x only */
PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
- PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
- PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
- PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
- PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
- PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3),
/* IPSR11 */
PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
- PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3),
PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
- PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1),
PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
- PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1),
@@ -1485,42 +1572,42 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
- PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
+ PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2), /* R8A779x only */
PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
- PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
+ PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2), /* R8A779x only */
PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
- PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
- PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2), /* R8A779x only */
+ PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), /* R8A779x */
PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
- PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
- PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), /* R8A779x only */
PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
- PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), /* R8A779x */
PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
/* IPSR13 */
- PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0), /* R8A779x only */
PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
- PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
- PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0), /* R8A779x only */
PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
- PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
- PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), /* R8A779x only */
PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
- PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
- PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0), /* R8A779x only */
PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
- PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
@@ -1536,26 +1623,26 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
- PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
+ PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
- PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
+ PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1), /* R8A779x only */
PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
- PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
+ PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1), /* R8A779x only */
PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
- PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
+ PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1), /* R8A779x only */
PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
- PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
+ PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1), /* R8A779x only */
PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
- PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
+ PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1), /* R8A779x only */
PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
- PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
+ PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1), /* R8A779x only */
PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
@@ -1589,59 +1676,59 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
- PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
- PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
- PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
- PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
- PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2),
PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
- PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2),
PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
/* IPSR15 */
- PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
- PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0), /* R8A779x only */
+ PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
- PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
- PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
+ PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK), /* R8A779x only */
+ PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
- PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
- PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0), /* R8A779x only */
+ PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
- PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
- PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
- PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0), /* R8A779x only */
PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
@@ -1649,27 +1736,27 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
- PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
- PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
- PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
- PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
- PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
@@ -1677,24 +1764,24 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
- PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
- PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
- PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
- PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
+ PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK), /* R8A779x only */
+ PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2), /* R8A779x only */
PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
- PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
+ PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG), /* R8A779x only */
PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
- PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
+ PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT), /* R8A779x only */
PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
};
@@ -1702,7 +1789,7 @@ static const struct sh_pfc_pin pinmux_pi
PINMUX_GPIO_GP_ALL(),
};
-/* - ADI -------------------------------------------------------------------- */
+/* - ADI (R8A779x only) ----------------------------------------------------- */
static const unsigned int adi_common_pins[] = {
/* ADIDATA, ADICS/SAMP, ADICLK */
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
@@ -2555,7 +2642,7 @@ static const unsigned int intc_irq3_pins
static const unsigned int intc_irq3_mux[] = {
IRQ3_MARK,
};
-/* - MLB+ ------------------------------------------------------------------- */
+/* - MLB+ (R8A779x only) ---------------------------------------------------- */
static const unsigned int mlb_3pin_pins[] = {
RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
};
@@ -4419,359 +4506,367 @@ static const unsigned int vin2_clk_mux[]
VI2_CLK_MARK,
};
-static const struct sh_pfc_pin_group pinmux_groups[] = {
- SH_PFC_PIN_GROUP(adi_common),
- SH_PFC_PIN_GROUP(adi_chsel0),
- SH_PFC_PIN_GROUP(adi_chsel1),
- SH_PFC_PIN_GROUP(adi_chsel2),
- SH_PFC_PIN_GROUP(adi_common_b),
- SH_PFC_PIN_GROUP(adi_chsel0_b),
- SH_PFC_PIN_GROUP(adi_chsel1_b),
- SH_PFC_PIN_GROUP(adi_chsel2_b),
- SH_PFC_PIN_GROUP(audio_clk_a),
- SH_PFC_PIN_GROUP(audio_clk_b),
- SH_PFC_PIN_GROUP(audio_clk_b_b),
- SH_PFC_PIN_GROUP(audio_clk_c),
- SH_PFC_PIN_GROUP(audio_clkout),
- SH_PFC_PIN_GROUP(avb_link),
- SH_PFC_PIN_GROUP(avb_magic),
- SH_PFC_PIN_GROUP(avb_phy_int),
- SH_PFC_PIN_GROUP(avb_mdio),
- SH_PFC_PIN_GROUP(avb_mii),
- SH_PFC_PIN_GROUP(avb_gmii),
- SH_PFC_PIN_GROUP(can0_data),
- SH_PFC_PIN_GROUP(can0_data_b),
- SH_PFC_PIN_GROUP(can0_data_c),
- SH_PFC_PIN_GROUP(can0_data_d),
- SH_PFC_PIN_GROUP(can0_data_e),
- SH_PFC_PIN_GROUP(can0_data_f),
- SH_PFC_PIN_GROUP(can1_data),
- SH_PFC_PIN_GROUP(can1_data_b),
- SH_PFC_PIN_GROUP(can1_data_c),
- SH_PFC_PIN_GROUP(can1_data_d),
- SH_PFC_PIN_GROUP(can_clk),
- SH_PFC_PIN_GROUP(can_clk_b),
- SH_PFC_PIN_GROUP(can_clk_c),
- SH_PFC_PIN_GROUP(can_clk_d),
- SH_PFC_PIN_GROUP(du_rgb666),
- SH_PFC_PIN_GROUP(du_rgb888),
- SH_PFC_PIN_GROUP(du_clk_out_0),
- SH_PFC_PIN_GROUP(du_clk_out_1),
- SH_PFC_PIN_GROUP(du_sync),
- SH_PFC_PIN_GROUP(du_oddf),
- SH_PFC_PIN_GROUP(du_cde),
- SH_PFC_PIN_GROUP(du_disp),
- SH_PFC_PIN_GROUP(du0_clk_in),
- SH_PFC_PIN_GROUP(du1_clk_in),
- SH_PFC_PIN_GROUP(du1_clk_in_b),
- SH_PFC_PIN_GROUP(du1_clk_in_c),
- SH_PFC_PIN_GROUP(eth_link),
- SH_PFC_PIN_GROUP(eth_magic),
- SH_PFC_PIN_GROUP(eth_mdio),
- SH_PFC_PIN_GROUP(eth_rmii),
- SH_PFC_PIN_GROUP(hscif0_data),
- SH_PFC_PIN_GROUP(hscif0_clk),
- SH_PFC_PIN_GROUP(hscif0_ctrl),
- SH_PFC_PIN_GROUP(hscif0_data_b),
- SH_PFC_PIN_GROUP(hscif0_ctrl_b),
- SH_PFC_PIN_GROUP(hscif0_data_c),
- SH_PFC_PIN_GROUP(hscif0_clk_c),
- SH_PFC_PIN_GROUP(hscif1_data),
- SH_PFC_PIN_GROUP(hscif1_clk),
- SH_PFC_PIN_GROUP(hscif1_ctrl),
- SH_PFC_PIN_GROUP(hscif1_data_b),
- SH_PFC_PIN_GROUP(hscif1_data_c),
- SH_PFC_PIN_GROUP(hscif1_clk_c),
- SH_PFC_PIN_GROUP(hscif1_ctrl_c),
- SH_PFC_PIN_GROUP(hscif1_data_d),
- SH_PFC_PIN_GROUP(hscif1_data_e),
- SH_PFC_PIN_GROUP(hscif1_clk_e),
- SH_PFC_PIN_GROUP(hscif1_ctrl_e),
- SH_PFC_PIN_GROUP(hscif2_data),
- SH_PFC_PIN_GROUP(hscif2_clk),
- SH_PFC_PIN_GROUP(hscif2_ctrl),
- SH_PFC_PIN_GROUP(hscif2_data_b),
- SH_PFC_PIN_GROUP(hscif2_ctrl_b),
- SH_PFC_PIN_GROUP(hscif2_data_c),
- SH_PFC_PIN_GROUP(hscif2_clk_c),
- SH_PFC_PIN_GROUP(hscif2_data_d),
- SH_PFC_PIN_GROUP(i2c0),
- SH_PFC_PIN_GROUP(i2c0_b),
- SH_PFC_PIN_GROUP(i2c0_c),
- SH_PFC_PIN_GROUP(i2c1),
- SH_PFC_PIN_GROUP(i2c1_b),
- SH_PFC_PIN_GROUP(i2c1_c),
- SH_PFC_PIN_GROUP(i2c1_d),
- SH_PFC_PIN_GROUP(i2c1_e),
- SH_PFC_PIN_GROUP(i2c2),
- SH_PFC_PIN_GROUP(i2c2_b),
- SH_PFC_PIN_GROUP(i2c2_c),
- SH_PFC_PIN_GROUP(i2c2_d),
- SH_PFC_PIN_GROUP(i2c3),
- SH_PFC_PIN_GROUP(i2c3_b),
- SH_PFC_PIN_GROUP(i2c3_c),
- SH_PFC_PIN_GROUP(i2c3_d),
- SH_PFC_PIN_GROUP(i2c4),
- SH_PFC_PIN_GROUP(i2c4_b),
- SH_PFC_PIN_GROUP(i2c4_c),
- SH_PFC_PIN_GROUP(i2c7),
- SH_PFC_PIN_GROUP(i2c7_b),
- SH_PFC_PIN_GROUP(i2c7_c),
- SH_PFC_PIN_GROUP(i2c8),
- SH_PFC_PIN_GROUP(i2c8_b),
- SH_PFC_PIN_GROUP(i2c8_c),
- SH_PFC_PIN_GROUP(intc_irq0),
- SH_PFC_PIN_GROUP(intc_irq1),
- SH_PFC_PIN_GROUP(intc_irq2),
- SH_PFC_PIN_GROUP(intc_irq3),
- SH_PFC_PIN_GROUP(mlb_3pin),
- SH_PFC_PIN_GROUP(mmc_data1),
- SH_PFC_PIN_GROUP(mmc_data4),
- SH_PFC_PIN_GROUP(mmc_data8),
- SH_PFC_PIN_GROUP(mmc_ctrl),
- SH_PFC_PIN_GROUP(msiof0_clk),
- SH_PFC_PIN_GROUP(msiof0_sync),
- SH_PFC_PIN_GROUP(msiof0_ss1),
- SH_PFC_PIN_GROUP(msiof0_ss2),
- SH_PFC_PIN_GROUP(msiof0_rx),
- SH_PFC_PIN_GROUP(msiof0_tx),
- SH_PFC_PIN_GROUP(msiof0_clk_b),
- SH_PFC_PIN_GROUP(msiof0_sync_b),
- SH_PFC_PIN_GROUP(msiof0_ss1_b),
- SH_PFC_PIN_GROUP(msiof0_ss2_b),
- SH_PFC_PIN_GROUP(msiof0_rx_b),
- SH_PFC_PIN_GROUP(msiof0_tx_b),
- SH_PFC_PIN_GROUP(msiof0_clk_c),
- SH_PFC_PIN_GROUP(msiof0_sync_c),
- SH_PFC_PIN_GROUP(msiof0_ss1_c),
- SH_PFC_PIN_GROUP(msiof0_ss2_c),
- SH_PFC_PIN_GROUP(msiof0_rx_c),
- SH_PFC_PIN_GROUP(msiof0_tx_c),
- SH_PFC_PIN_GROUP(msiof1_clk),
- SH_PFC_PIN_GROUP(msiof1_sync),
- SH_PFC_PIN_GROUP(msiof1_ss1),
- SH_PFC_PIN_GROUP(msiof1_ss2),
- SH_PFC_PIN_GROUP(msiof1_rx),
- SH_PFC_PIN_GROUP(msiof1_tx),
- SH_PFC_PIN_GROUP(msiof1_clk_b),
- SH_PFC_PIN_GROUP(msiof1_sync_b),
- SH_PFC_PIN_GROUP(msiof1_ss1_b),
- SH_PFC_PIN_GROUP(msiof1_ss2_b),
- SH_PFC_PIN_GROUP(msiof1_rx_b),
- SH_PFC_PIN_GROUP(msiof1_tx_b),
- SH_PFC_PIN_GROUP(msiof1_clk_c),
- SH_PFC_PIN_GROUP(msiof1_sync_c),
- SH_PFC_PIN_GROUP(msiof1_rx_c),
- SH_PFC_PIN_GROUP(msiof1_tx_c),
- SH_PFC_PIN_GROUP(msiof1_clk_d),
- SH_PFC_PIN_GROUP(msiof1_sync_d),
- SH_PFC_PIN_GROUP(msiof1_ss1_d),
- SH_PFC_PIN_GROUP(msiof1_rx_d),
- SH_PFC_PIN_GROUP(msiof1_tx_d),
- SH_PFC_PIN_GROUP(msiof1_clk_e),
- SH_PFC_PIN_GROUP(msiof1_sync_e),
- SH_PFC_PIN_GROUP(msiof1_rx_e),
- SH_PFC_PIN_GROUP(msiof1_tx_e),
- SH_PFC_PIN_GROUP(msiof2_clk),
- SH_PFC_PIN_GROUP(msiof2_sync),
- SH_PFC_PIN_GROUP(msiof2_ss1),
- SH_PFC_PIN_GROUP(msiof2_ss2),
- SH_PFC_PIN_GROUP(msiof2_rx),
- SH_PFC_PIN_GROUP(msiof2_tx),
- SH_PFC_PIN_GROUP(msiof2_clk_b),
- SH_PFC_PIN_GROUP(msiof2_sync_b),
- SH_PFC_PIN_GROUP(msiof2_ss1_b),
- SH_PFC_PIN_GROUP(msiof2_ss2_b),
- SH_PFC_PIN_GROUP(msiof2_rx_b),
- SH_PFC_PIN_GROUP(msiof2_tx_b),
- SH_PFC_PIN_GROUP(msiof2_clk_c),
- SH_PFC_PIN_GROUP(msiof2_sync_c),
- SH_PFC_PIN_GROUP(msiof2_rx_c),
- SH_PFC_PIN_GROUP(msiof2_tx_c),
- SH_PFC_PIN_GROUP(msiof2_clk_d),
- SH_PFC_PIN_GROUP(msiof2_sync_d),
- SH_PFC_PIN_GROUP(msiof2_ss1_d),
- SH_PFC_PIN_GROUP(msiof2_ss2_d),
- SH_PFC_PIN_GROUP(msiof2_rx_d),
- SH_PFC_PIN_GROUP(msiof2_tx_d),
- SH_PFC_PIN_GROUP(msiof2_clk_e),
- SH_PFC_PIN_GROUP(msiof2_sync_e),
- SH_PFC_PIN_GROUP(msiof2_rx_e),
- SH_PFC_PIN_GROUP(msiof2_tx_e),
- SH_PFC_PIN_GROUP(pwm0),
- SH_PFC_PIN_GROUP(pwm0_b),
- SH_PFC_PIN_GROUP(pwm1),
- SH_PFC_PIN_GROUP(pwm1_b),
- SH_PFC_PIN_GROUP(pwm2),
- SH_PFC_PIN_GROUP(pwm2_b),
- SH_PFC_PIN_GROUP(pwm3),
- SH_PFC_PIN_GROUP(pwm4),
- SH_PFC_PIN_GROUP(pwm4_b),
- SH_PFC_PIN_GROUP(pwm5),
- SH_PFC_PIN_GROUP(pwm5_b),
- SH_PFC_PIN_GROUP(pwm6),
- SH_PFC_PIN_GROUP(qspi_ctrl),
- SH_PFC_PIN_GROUP(qspi_data2),
- SH_PFC_PIN_GROUP(qspi_data4),
- SH_PFC_PIN_GROUP(qspi_ctrl_b),
- SH_PFC_PIN_GROUP(qspi_data2_b),
- SH_PFC_PIN_GROUP(qspi_data4_b),
- SH_PFC_PIN_GROUP(scif0_data),
- SH_PFC_PIN_GROUP(scif0_data_b),
- SH_PFC_PIN_GROUP(scif0_data_c),
- SH_PFC_PIN_GROUP(scif0_data_d),
- SH_PFC_PIN_GROUP(scif0_data_e),
- SH_PFC_PIN_GROUP(scif1_data),
- SH_PFC_PIN_GROUP(scif1_data_b),
- SH_PFC_PIN_GROUP(scif1_clk_b),
- SH_PFC_PIN_GROUP(scif1_data_c),
- SH_PFC_PIN_GROUP(scif1_data_d),
- SH_PFC_PIN_GROUP(scif2_data),
- SH_PFC_PIN_GROUP(scif2_data_b),
- SH_PFC_PIN_GROUP(scif2_clk_b),
- SH_PFC_PIN_GROUP(scif2_data_c),
- SH_PFC_PIN_GROUP(scif2_data_e),
- SH_PFC_PIN_GROUP(scif3_data),
- SH_PFC_PIN_GROUP(scif3_clk),
- SH_PFC_PIN_GROUP(scif3_data_b),
- SH_PFC_PIN_GROUP(scif3_clk_b),
- SH_PFC_PIN_GROUP(scif3_data_c),
- SH_PFC_PIN_GROUP(scif3_data_d),
- SH_PFC_PIN_GROUP(scif4_data),
- SH_PFC_PIN_GROUP(scif4_data_b),
- SH_PFC_PIN_GROUP(scif4_data_c),
- SH_PFC_PIN_GROUP(scif5_data),
- SH_PFC_PIN_GROUP(scif5_data_b),
- SH_PFC_PIN_GROUP(scifa0_data),
- SH_PFC_PIN_GROUP(scifa0_data_b),
- SH_PFC_PIN_GROUP(scifa1_data),
- SH_PFC_PIN_GROUP(scifa1_clk),
- SH_PFC_PIN_GROUP(scifa1_data_b),
- SH_PFC_PIN_GROUP(scifa1_clk_b),
- SH_PFC_PIN_GROUP(scifa1_data_c),
- SH_PFC_PIN_GROUP(scifa2_data),
- SH_PFC_PIN_GROUP(scifa2_clk),
- SH_PFC_PIN_GROUP(scifa2_data_b),
- SH_PFC_PIN_GROUP(scifa3_data),
- SH_PFC_PIN_GROUP(scifa3_clk),
- SH_PFC_PIN_GROUP(scifa3_data_b),
- SH_PFC_PIN_GROUP(scifa3_clk_b),
- SH_PFC_PIN_GROUP(scifa3_data_c),
- SH_PFC_PIN_GROUP(scifa3_clk_c),
- SH_PFC_PIN_GROUP(scifa4_data),
- SH_PFC_PIN_GROUP(scifa4_data_b),
- SH_PFC_PIN_GROUP(scifa4_data_c),
- SH_PFC_PIN_GROUP(scifa5_data),
- SH_PFC_PIN_GROUP(scifa5_data_b),
- SH_PFC_PIN_GROUP(scifa5_data_c),
- SH_PFC_PIN_GROUP(scifb0_data),
- SH_PFC_PIN_GROUP(scifb0_clk),
- SH_PFC_PIN_GROUP(scifb0_ctrl),
- SH_PFC_PIN_GROUP(scifb0_data_b),
- SH_PFC_PIN_GROUP(scifb0_clk_b),
- SH_PFC_PIN_GROUP(scifb0_ctrl_b),
- SH_PFC_PIN_GROUP(scifb0_data_c),
- SH_PFC_PIN_GROUP(scifb0_clk_c),
- SH_PFC_PIN_GROUP(scifb0_data_d),
- SH_PFC_PIN_GROUP(scifb0_clk_d),
- SH_PFC_PIN_GROUP(scifb1_data),
- SH_PFC_PIN_GROUP(scifb1_clk),
- SH_PFC_PIN_GROUP(scifb1_ctrl),
- SH_PFC_PIN_GROUP(scifb1_data_b),
- SH_PFC_PIN_GROUP(scifb1_clk_b),
- SH_PFC_PIN_GROUP(scifb1_data_c),
- SH_PFC_PIN_GROUP(scifb1_clk_c),
- SH_PFC_PIN_GROUP(scifb1_data_d),
- SH_PFC_PIN_GROUP(scifb2_data),
- SH_PFC_PIN_GROUP(scifb2_clk),
- SH_PFC_PIN_GROUP(scifb2_ctrl),
- SH_PFC_PIN_GROUP(scifb2_data_b),
- SH_PFC_PIN_GROUP(scifb2_clk_b),
- SH_PFC_PIN_GROUP(scifb2_ctrl_b),
- SH_PFC_PIN_GROUP(scifb2_data_c),
- SH_PFC_PIN_GROUP(scifb2_clk_c),
- SH_PFC_PIN_GROUP(scifb2_data_d),
- SH_PFC_PIN_GROUP(scif_clk),
- SH_PFC_PIN_GROUP(scif_clk_b),
- SH_PFC_PIN_GROUP(sdhi0_data1),
- SH_PFC_PIN_GROUP(sdhi0_data4),
- SH_PFC_PIN_GROUP(sdhi0_ctrl),
- SH_PFC_PIN_GROUP(sdhi0_cd),
- SH_PFC_PIN_GROUP(sdhi0_wp),
- SH_PFC_PIN_GROUP(sdhi1_data1),
- SH_PFC_PIN_GROUP(sdhi1_data4),
- SH_PFC_PIN_GROUP(sdhi1_ctrl),
- SH_PFC_PIN_GROUP(sdhi1_cd),
- SH_PFC_PIN_GROUP(sdhi1_wp),
- SH_PFC_PIN_GROUP(sdhi2_data1),
- SH_PFC_PIN_GROUP(sdhi2_data4),
- SH_PFC_PIN_GROUP(sdhi2_ctrl),
- SH_PFC_PIN_GROUP(sdhi2_cd),
- SH_PFC_PIN_GROUP(sdhi2_wp),
- SH_PFC_PIN_GROUP(ssi0_data),
- SH_PFC_PIN_GROUP(ssi0_data_b),
- SH_PFC_PIN_GROUP(ssi0129_ctrl),
- SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
- SH_PFC_PIN_GROUP(ssi1_data),
- SH_PFC_PIN_GROUP(ssi1_data_b),
- SH_PFC_PIN_GROUP(ssi1_ctrl),
- SH_PFC_PIN_GROUP(ssi1_ctrl_b),
- SH_PFC_PIN_GROUP(ssi2_data),
- SH_PFC_PIN_GROUP(ssi2_ctrl),
- SH_PFC_PIN_GROUP(ssi3_data),
- SH_PFC_PIN_GROUP(ssi34_ctrl),
- SH_PFC_PIN_GROUP(ssi4_data),
- SH_PFC_PIN_GROUP(ssi4_ctrl),
- SH_PFC_PIN_GROUP(ssi5_data),
- SH_PFC_PIN_GROUP(ssi5_ctrl),
- SH_PFC_PIN_GROUP(ssi6_data),
- SH_PFC_PIN_GROUP(ssi6_ctrl),
- SH_PFC_PIN_GROUP(ssi7_data),
- SH_PFC_PIN_GROUP(ssi7_data_b),
- SH_PFC_PIN_GROUP(ssi78_ctrl),
- SH_PFC_PIN_GROUP(ssi78_ctrl_b),
- SH_PFC_PIN_GROUP(ssi8_data),
- SH_PFC_PIN_GROUP(ssi8_data_b),
- SH_PFC_PIN_GROUP(ssi9_data),
- SH_PFC_PIN_GROUP(ssi9_data_b),
- SH_PFC_PIN_GROUP(ssi9_ctrl),
- SH_PFC_PIN_GROUP(ssi9_ctrl_b),
- SH_PFC_PIN_GROUP(usb0),
- SH_PFC_PIN_GROUP(usb1),
- VIN_DATA_PIN_GROUP(vin0_data, 24),
- VIN_DATA_PIN_GROUP(vin0_data, 20),
- SH_PFC_PIN_GROUP(vin0_data18),
- VIN_DATA_PIN_GROUP(vin0_data, 16),
- VIN_DATA_PIN_GROUP(vin0_data, 12),
- VIN_DATA_PIN_GROUP(vin0_data, 10),
- VIN_DATA_PIN_GROUP(vin0_data, 8),
- SH_PFC_PIN_GROUP(vin0_sync),
- SH_PFC_PIN_GROUP(vin0_field),
- SH_PFC_PIN_GROUP(vin0_clkenb),
- SH_PFC_PIN_GROUP(vin0_clk),
- SH_PFC_PIN_GROUP(vin1_data8),
- SH_PFC_PIN_GROUP(vin1_sync),
- SH_PFC_PIN_GROUP(vin1_field),
- SH_PFC_PIN_GROUP(vin1_clkenb),
- SH_PFC_PIN_GROUP(vin1_clk),
- VIN_DATA_PIN_GROUP(vin1_b_data, 24),
- VIN_DATA_PIN_GROUP(vin1_b_data, 20),
- SH_PFC_PIN_GROUP(vin1_b_data18),
- VIN_DATA_PIN_GROUP(vin1_b_data, 16),
- VIN_DATA_PIN_GROUP(vin1_b_data, 12),
- VIN_DATA_PIN_GROUP(vin1_b_data, 10),
- VIN_DATA_PIN_GROUP(vin1_b_data, 8),
- SH_PFC_PIN_GROUP(vin1_b_sync),
- SH_PFC_PIN_GROUP(vin1_b_field),
- SH_PFC_PIN_GROUP(vin1_b_clkenb),
- SH_PFC_PIN_GROUP(vin1_b_clk),
- SH_PFC_PIN_GROUP(vin2_data8),
- SH_PFC_PIN_GROUP(vin2_sync),
- SH_PFC_PIN_GROUP(vin2_field),
- SH_PFC_PIN_GROUP(vin2_clkenb),
- SH_PFC_PIN_GROUP(vin2_clk),
+static const struct {
+ struct sh_pfc_pin_group common[341];
+ struct sh_pfc_pin_group r8a779x[9];
+} pinmux_groups = {
+ .common = {
+ SH_PFC_PIN_GROUP(audio_clk_a),
+ SH_PFC_PIN_GROUP(audio_clk_b),
+ SH_PFC_PIN_GROUP(audio_clk_b_b),
+ SH_PFC_PIN_GROUP(audio_clk_c),
+ SH_PFC_PIN_GROUP(audio_clkout),
+ SH_PFC_PIN_GROUP(avb_link),
+ SH_PFC_PIN_GROUP(avb_magic),
+ SH_PFC_PIN_GROUP(avb_phy_int),
+ SH_PFC_PIN_GROUP(avb_mdio),
+ SH_PFC_PIN_GROUP(avb_mii),
+ SH_PFC_PIN_GROUP(avb_gmii),
+ SH_PFC_PIN_GROUP(can0_data),
+ SH_PFC_PIN_GROUP(can0_data_b),
+ SH_PFC_PIN_GROUP(can0_data_c),
+ SH_PFC_PIN_GROUP(can0_data_d),
+ SH_PFC_PIN_GROUP(can0_data_e),
+ SH_PFC_PIN_GROUP(can0_data_f),
+ SH_PFC_PIN_GROUP(can1_data),
+ SH_PFC_PIN_GROUP(can1_data_b),
+ SH_PFC_PIN_GROUP(can1_data_c),
+ SH_PFC_PIN_GROUP(can1_data_d),
+ SH_PFC_PIN_GROUP(can_clk),
+ SH_PFC_PIN_GROUP(can_clk_b),
+ SH_PFC_PIN_GROUP(can_clk_c),
+ SH_PFC_PIN_GROUP(can_clk_d),
+ SH_PFC_PIN_GROUP(du_rgb666),
+ SH_PFC_PIN_GROUP(du_rgb888),
+ SH_PFC_PIN_GROUP(du_clk_out_0),
+ SH_PFC_PIN_GROUP(du_clk_out_1),
+ SH_PFC_PIN_GROUP(du_sync),
+ SH_PFC_PIN_GROUP(du_oddf),
+ SH_PFC_PIN_GROUP(du_cde),
+ SH_PFC_PIN_GROUP(du_disp),
+ SH_PFC_PIN_GROUP(du0_clk_in),
+ SH_PFC_PIN_GROUP(du1_clk_in),
+ SH_PFC_PIN_GROUP(du1_clk_in_b),
+ SH_PFC_PIN_GROUP(du1_clk_in_c),
+ SH_PFC_PIN_GROUP(eth_link),
+ SH_PFC_PIN_GROUP(eth_magic),
+ SH_PFC_PIN_GROUP(eth_mdio),
+ SH_PFC_PIN_GROUP(eth_rmii),
+ SH_PFC_PIN_GROUP(hscif0_data),
+ SH_PFC_PIN_GROUP(hscif0_clk),
+ SH_PFC_PIN_GROUP(hscif0_ctrl),
+ SH_PFC_PIN_GROUP(hscif0_data_b),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_b),
+ SH_PFC_PIN_GROUP(hscif0_data_c),
+ SH_PFC_PIN_GROUP(hscif0_clk_c),
+ SH_PFC_PIN_GROUP(hscif1_data),
+ SH_PFC_PIN_GROUP(hscif1_clk),
+ SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif1_data_b),
+ SH_PFC_PIN_GROUP(hscif1_data_c),
+ SH_PFC_PIN_GROUP(hscif1_clk_c),
+ SH_PFC_PIN_GROUP(hscif1_ctrl_c),
+ SH_PFC_PIN_GROUP(hscif1_data_d),
+ SH_PFC_PIN_GROUP(hscif1_data_e),
+ SH_PFC_PIN_GROUP(hscif1_clk_e),
+ SH_PFC_PIN_GROUP(hscif1_ctrl_e),
+ SH_PFC_PIN_GROUP(hscif2_data),
+ SH_PFC_PIN_GROUP(hscif2_clk),
+ SH_PFC_PIN_GROUP(hscif2_ctrl),
+ SH_PFC_PIN_GROUP(hscif2_data_b),
+ SH_PFC_PIN_GROUP(hscif2_ctrl_b),
+ SH_PFC_PIN_GROUP(hscif2_data_c),
+ SH_PFC_PIN_GROUP(hscif2_clk_c),
+ SH_PFC_PIN_GROUP(hscif2_data_d),
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c0_b),
+ SH_PFC_PIN_GROUP(i2c0_c),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c1_b),
+ SH_PFC_PIN_GROUP(i2c1_c),
+ SH_PFC_PIN_GROUP(i2c1_d),
+ SH_PFC_PIN_GROUP(i2c1_e),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c2_b),
+ SH_PFC_PIN_GROUP(i2c2_c),
+ SH_PFC_PIN_GROUP(i2c2_d),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c3_b),
+ SH_PFC_PIN_GROUP(i2c3_c),
+ SH_PFC_PIN_GROUP(i2c3_d),
+ SH_PFC_PIN_GROUP(i2c4),
+ SH_PFC_PIN_GROUP(i2c4_b),
+ SH_PFC_PIN_GROUP(i2c4_c),
+ SH_PFC_PIN_GROUP(i2c8),
+ SH_PFC_PIN_GROUP(i2c8_b),
+ SH_PFC_PIN_GROUP(i2c8_c),
+ SH_PFC_PIN_GROUP(i2c8),
+ SH_PFC_PIN_GROUP(i2c8_b),
+ SH_PFC_PIN_GROUP(i2c8_c),
+ SH_PFC_PIN_GROUP(intc_irq0),
+ SH_PFC_PIN_GROUP(intc_irq1),
+ SH_PFC_PIN_GROUP(intc_irq2),
+ SH_PFC_PIN_GROUP(intc_irq3),
+ SH_PFC_PIN_GROUP(mmc_data1),
+ SH_PFC_PIN_GROUP(mmc_data4),
+ SH_PFC_PIN_GROUP(mmc_data8),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_rx),
+ SH_PFC_PIN_GROUP(msiof0_tx),
+ SH_PFC_PIN_GROUP(msiof0_clk_b),
+ SH_PFC_PIN_GROUP(msiof0_sync_b),
+ SH_PFC_PIN_GROUP(msiof0_ss1_b),
+ SH_PFC_PIN_GROUP(msiof0_ss2_b),
+ SH_PFC_PIN_GROUP(msiof0_rx_b),
+ SH_PFC_PIN_GROUP(msiof0_tx_b),
+ SH_PFC_PIN_GROUP(msiof0_clk_c),
+ SH_PFC_PIN_GROUP(msiof0_sync_c),
+ SH_PFC_PIN_GROUP(msiof0_ss1_c),
+ SH_PFC_PIN_GROUP(msiof0_ss2_c),
+ SH_PFC_PIN_GROUP(msiof0_rx_c),
+ SH_PFC_PIN_GROUP(msiof0_tx_c),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_rx),
+ SH_PFC_PIN_GROUP(msiof1_tx),
+ SH_PFC_PIN_GROUP(msiof1_clk_b),
+ SH_PFC_PIN_GROUP(msiof1_sync_b),
+ SH_PFC_PIN_GROUP(msiof1_ss1_b),
+ SH_PFC_PIN_GROUP(msiof1_ss2_b),
+ SH_PFC_PIN_GROUP(msiof1_rx_b),
+ SH_PFC_PIN_GROUP(msiof1_tx_b),
+ SH_PFC_PIN_GROUP(msiof1_clk_c),
+ SH_PFC_PIN_GROUP(msiof1_sync_c),
+ SH_PFC_PIN_GROUP(msiof1_rx_c),
+ SH_PFC_PIN_GROUP(msiof1_tx_c),
+ SH_PFC_PIN_GROUP(msiof1_clk_d),
+ SH_PFC_PIN_GROUP(msiof1_sync_d),
+ SH_PFC_PIN_GROUP(msiof1_ss1_d),
+ SH_PFC_PIN_GROUP(msiof1_rx_d),
+ SH_PFC_PIN_GROUP(msiof1_tx_d),
+ SH_PFC_PIN_GROUP(msiof1_clk_e),
+ SH_PFC_PIN_GROUP(msiof1_sync_e),
+ SH_PFC_PIN_GROUP(msiof1_rx_e),
+ SH_PFC_PIN_GROUP(msiof1_tx_e),
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_rx),
+ SH_PFC_PIN_GROUP(msiof2_tx),
+ SH_PFC_PIN_GROUP(msiof2_clk_b),
+ SH_PFC_PIN_GROUP(msiof2_sync_b),
+ SH_PFC_PIN_GROUP(msiof2_ss1_b),
+ SH_PFC_PIN_GROUP(msiof2_ss2_b),
+ SH_PFC_PIN_GROUP(msiof2_rx_b),
+ SH_PFC_PIN_GROUP(msiof2_tx_b),
+ SH_PFC_PIN_GROUP(msiof2_clk_c),
+ SH_PFC_PIN_GROUP(msiof2_sync_c),
+ SH_PFC_PIN_GROUP(msiof2_rx_c),
+ SH_PFC_PIN_GROUP(msiof2_tx_c),
+ SH_PFC_PIN_GROUP(msiof2_clk_d),
+ SH_PFC_PIN_GROUP(msiof2_sync_d),
+ SH_PFC_PIN_GROUP(msiof2_ss1_d),
+ SH_PFC_PIN_GROUP(msiof2_ss2_d),
+ SH_PFC_PIN_GROUP(msiof2_rx_d),
+ SH_PFC_PIN_GROUP(msiof2_tx_d),
+ SH_PFC_PIN_GROUP(msiof2_clk_e),
+ SH_PFC_PIN_GROUP(msiof2_sync_e),
+ SH_PFC_PIN_GROUP(msiof2_rx_e),
+ SH_PFC_PIN_GROUP(msiof2_tx_e),
+ SH_PFC_PIN_GROUP(pwm0),
+ SH_PFC_PIN_GROUP(pwm0_b),
+ SH_PFC_PIN_GROUP(pwm1),
+ SH_PFC_PIN_GROUP(pwm1_b),
+ SH_PFC_PIN_GROUP(pwm2),
+ SH_PFC_PIN_GROUP(pwm2_b),
+ SH_PFC_PIN_GROUP(pwm3),
+ SH_PFC_PIN_GROUP(pwm4),
+ SH_PFC_PIN_GROUP(pwm4_b),
+ SH_PFC_PIN_GROUP(pwm5),
+ SH_PFC_PIN_GROUP(pwm5_b),
+ SH_PFC_PIN_GROUP(pwm6),
+ SH_PFC_PIN_GROUP(qspi_ctrl),
+ SH_PFC_PIN_GROUP(qspi_data2),
+ SH_PFC_PIN_GROUP(qspi_data4),
+ SH_PFC_PIN_GROUP(qspi_ctrl_b),
+ SH_PFC_PIN_GROUP(qspi_data2_b),
+ SH_PFC_PIN_GROUP(qspi_data4_b),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_data_b),
+ SH_PFC_PIN_GROUP(scif0_data_c),
+ SH_PFC_PIN_GROUP(scif0_data_d),
+ SH_PFC_PIN_GROUP(scif0_data_e),
+ SH_PFC_PIN_GROUP(scif1_data),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif1_clk_b),
+ SH_PFC_PIN_GROUP(scif1_data_c),
+ SH_PFC_PIN_GROUP(scif1_data_d),
+ SH_PFC_PIN_GROUP(scif2_data),
+ SH_PFC_PIN_GROUP(scif2_data_b),
+ SH_PFC_PIN_GROUP(scif2_clk_b),
+ SH_PFC_PIN_GROUP(scif2_data_c),
+ SH_PFC_PIN_GROUP(scif2_data_e),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_data_b),
+ SH_PFC_PIN_GROUP(scif3_clk_b),
+ SH_PFC_PIN_GROUP(scif3_data_c),
+ SH_PFC_PIN_GROUP(scif3_data_d),
+ SH_PFC_PIN_GROUP(scif4_data),
+ SH_PFC_PIN_GROUP(scif4_data_b),
+ SH_PFC_PIN_GROUP(scif4_data_c),
+ SH_PFC_PIN_GROUP(scif5_data),
+ SH_PFC_PIN_GROUP(scif5_data_b),
+ SH_PFC_PIN_GROUP(scifa0_data),
+ SH_PFC_PIN_GROUP(scifa0_data_b),
+ SH_PFC_PIN_GROUP(scifa1_data),
+ SH_PFC_PIN_GROUP(scifa1_clk),
+ SH_PFC_PIN_GROUP(scifa1_data_b),
+ SH_PFC_PIN_GROUP(scifa1_clk_b),
+ SH_PFC_PIN_GROUP(scifa1_data_c),
+ SH_PFC_PIN_GROUP(scifa2_data),
+ SH_PFC_PIN_GROUP(scifa2_clk),
+ SH_PFC_PIN_GROUP(scifa2_data_b),
+ SH_PFC_PIN_GROUP(scifa3_data),
+ SH_PFC_PIN_GROUP(scifa3_clk),
+ SH_PFC_PIN_GROUP(scifa3_data_b),
+ SH_PFC_PIN_GROUP(scifa3_clk_b),
+ SH_PFC_PIN_GROUP(scifa3_data_c),
+ SH_PFC_PIN_GROUP(scifa3_clk_c),
+ SH_PFC_PIN_GROUP(scifa4_data),
+ SH_PFC_PIN_GROUP(scifa4_data_b),
+ SH_PFC_PIN_GROUP(scifa4_data_c),
+ SH_PFC_PIN_GROUP(scifa5_data),
+ SH_PFC_PIN_GROUP(scifa5_data_b),
+ SH_PFC_PIN_GROUP(scifa5_data_c),
+ SH_PFC_PIN_GROUP(scifb0_data),
+ SH_PFC_PIN_GROUP(scifb0_clk),
+ SH_PFC_PIN_GROUP(scifb0_ctrl),
+ SH_PFC_PIN_GROUP(scifb0_data_b),
+ SH_PFC_PIN_GROUP(scifb0_clk_b),
+ SH_PFC_PIN_GROUP(scifb0_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb0_data_c),
+ SH_PFC_PIN_GROUP(scifb0_clk_c),
+ SH_PFC_PIN_GROUP(scifb0_data_d),
+ SH_PFC_PIN_GROUP(scifb0_clk_d),
+ SH_PFC_PIN_GROUP(scifb1_data),
+ SH_PFC_PIN_GROUP(scifb1_clk),
+ SH_PFC_PIN_GROUP(scifb1_ctrl),
+ SH_PFC_PIN_GROUP(scifb1_data_b),
+ SH_PFC_PIN_GROUP(scifb1_clk_b),
+ SH_PFC_PIN_GROUP(scifb1_data_c),
+ SH_PFC_PIN_GROUP(scifb1_clk_c),
+ SH_PFC_PIN_GROUP(scifb1_data_d),
+ SH_PFC_PIN_GROUP(scifb2_data),
+ SH_PFC_PIN_GROUP(scifb2_clk),
+ SH_PFC_PIN_GROUP(scifb2_ctrl),
+ SH_PFC_PIN_GROUP(scifb2_data_b),
+ SH_PFC_PIN_GROUP(scifb2_clk_b),
+ SH_PFC_PIN_GROUP(scifb2_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb2_data_c),
+ SH_PFC_PIN_GROUP(scifb2_clk_c),
+ SH_PFC_PIN_GROUP(scifb2_data_d),
+ SH_PFC_PIN_GROUP(scif_clk),
+ SH_PFC_PIN_GROUP(scif_clk_b),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_cd),
+ SH_PFC_PIN_GROUP(sdhi2_wp),
+ SH_PFC_PIN_GROUP(ssi0_data),
+ SH_PFC_PIN_GROUP(ssi0_data_b),
+ SH_PFC_PIN_GROUP(ssi0129_ctrl),
+ SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi1_data),
+ SH_PFC_PIN_GROUP(ssi1_data_b),
+ SH_PFC_PIN_GROUP(ssi1_ctrl),
+ SH_PFC_PIN_GROUP(ssi1_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi2_data),
+ SH_PFC_PIN_GROUP(ssi2_ctrl),
+ SH_PFC_PIN_GROUP(ssi3_data),
+ SH_PFC_PIN_GROUP(ssi34_ctrl),
+ SH_PFC_PIN_GROUP(ssi4_data),
+ SH_PFC_PIN_GROUP(ssi4_ctrl),
+ SH_PFC_PIN_GROUP(ssi5_data),
+ SH_PFC_PIN_GROUP(ssi5_ctrl),
+ SH_PFC_PIN_GROUP(ssi6_data),
+ SH_PFC_PIN_GROUP(ssi6_ctrl),
+ SH_PFC_PIN_GROUP(ssi7_data),
+ SH_PFC_PIN_GROUP(ssi7_data_b),
+ SH_PFC_PIN_GROUP(ssi78_ctrl),
+ SH_PFC_PIN_GROUP(ssi78_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi8_data),
+ SH_PFC_PIN_GROUP(ssi8_data_b),
+ SH_PFC_PIN_GROUP(ssi9_data),
+ SH_PFC_PIN_GROUP(ssi9_data_b),
+ SH_PFC_PIN_GROUP(ssi9_ctrl),
+ SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+ SH_PFC_PIN_GROUP(usb0),
+ SH_PFC_PIN_GROUP(usb1),
+ VIN_DATA_PIN_GROUP(vin0_data, 24),
+ VIN_DATA_PIN_GROUP(vin0_data, 20),
+ SH_PFC_PIN_GROUP(vin0_data18),
+ VIN_DATA_PIN_GROUP(vin0_data, 16),
+ VIN_DATA_PIN_GROUP(vin0_data, 12),
+ VIN_DATA_PIN_GROUP(vin0_data, 10),
+ VIN_DATA_PIN_GROUP(vin0_data, 8),
+ SH_PFC_PIN_GROUP(vin0_sync),
+ SH_PFC_PIN_GROUP(vin0_field),
+ SH_PFC_PIN_GROUP(vin0_clkenb),
+ SH_PFC_PIN_GROUP(vin0_clk),
+ SH_PFC_PIN_GROUP(vin1_data8),
+ SH_PFC_PIN_GROUP(vin1_sync),
+ SH_PFC_PIN_GROUP(vin1_field),
+ SH_PFC_PIN_GROUP(vin1_clkenb),
+ SH_PFC_PIN_GROUP(vin1_clk),
+ VIN_DATA_PIN_GROUP(vin1_b_data, 24),
+ VIN_DATA_PIN_GROUP(vin1_b_data, 20),
+ SH_PFC_PIN_GROUP(vin1_b_data18),
+ VIN_DATA_PIN_GROUP(vin1_b_data, 16),
+ VIN_DATA_PIN_GROUP(vin1_b_data, 12),
+ VIN_DATA_PIN_GROUP(vin1_b_data, 10),
+ VIN_DATA_PIN_GROUP(vin1_b_data, 8),
+ SH_PFC_PIN_GROUP(vin1_b_sync),
+ SH_PFC_PIN_GROUP(vin1_b_field),
+ SH_PFC_PIN_GROUP(vin1_b_clkenb),
+ SH_PFC_PIN_GROUP(vin1_b_clk),
+ SH_PFC_PIN_GROUP(vin2_data8),
+ SH_PFC_PIN_GROUP(vin2_sync),
+ SH_PFC_PIN_GROUP(vin2_field),
+ SH_PFC_PIN_GROUP(vin2_clkenb),
+ SH_PFC_PIN_GROUP(vin2_clk),
+ },
+ .r8a779x = {
+ SH_PFC_PIN_GROUP(adi_common),
+ SH_PFC_PIN_GROUP(adi_chsel0),
+ SH_PFC_PIN_GROUP(adi_chsel1),
+ SH_PFC_PIN_GROUP(adi_chsel2),
+ SH_PFC_PIN_GROUP(adi_common_b),
+ SH_PFC_PIN_GROUP(adi_chsel0_b),
+ SH_PFC_PIN_GROUP(adi_chsel1_b),
+ SH_PFC_PIN_GROUP(adi_chsel2_b),
+ SH_PFC_PIN_GROUP(mlb_3pin),
+ }
};
+/* R8A779x only */
static const char * const adi_groups[] = {
"adi_common",
"adi_chsel0",
@@ -4940,6 +5035,7 @@ static const char * const intc_groups[]
"intc_irq3",
};
+/* R8A779x only */
static const char * const mlb_groups[] = {
"mlb_3pin",
};
@@ -5287,65 +5383,72 @@ static const char * const vin2_groups[]
"vin2_clk",
};
-static const struct sh_pfc_function pinmux_functions[] = {
- SH_PFC_FUNCTION(adi),
- SH_PFC_FUNCTION(audio_clk),
- SH_PFC_FUNCTION(avb),
- SH_PFC_FUNCTION(can0),
- SH_PFC_FUNCTION(can1),
- SH_PFC_FUNCTION(du),
- SH_PFC_FUNCTION(du0),
- SH_PFC_FUNCTION(du1),
- SH_PFC_FUNCTION(eth),
- SH_PFC_FUNCTION(hscif0),
- SH_PFC_FUNCTION(hscif1),
- SH_PFC_FUNCTION(hscif2),
- SH_PFC_FUNCTION(i2c0),
- SH_PFC_FUNCTION(i2c1),
- SH_PFC_FUNCTION(i2c2),
- SH_PFC_FUNCTION(i2c3),
- SH_PFC_FUNCTION(i2c4),
- SH_PFC_FUNCTION(i2c7),
- SH_PFC_FUNCTION(i2c8),
- SH_PFC_FUNCTION(intc),
- SH_PFC_FUNCTION(mlb),
- SH_PFC_FUNCTION(mmc),
- SH_PFC_FUNCTION(msiof0),
- SH_PFC_FUNCTION(msiof1),
- SH_PFC_FUNCTION(msiof2),
- SH_PFC_FUNCTION(pwm0),
- SH_PFC_FUNCTION(pwm1),
- SH_PFC_FUNCTION(pwm2),
- SH_PFC_FUNCTION(pwm3),
- SH_PFC_FUNCTION(pwm4),
- SH_PFC_FUNCTION(pwm5),
- SH_PFC_FUNCTION(pwm6),
- SH_PFC_FUNCTION(qspi),
- SH_PFC_FUNCTION(scif0),
- SH_PFC_FUNCTION(scif1),
- SH_PFC_FUNCTION(scif2),
- SH_PFC_FUNCTION(scif3),
- SH_PFC_FUNCTION(scif4),
- SH_PFC_FUNCTION(scif5),
- SH_PFC_FUNCTION(scifa0),
- SH_PFC_FUNCTION(scifa1),
- SH_PFC_FUNCTION(scifa2),
- SH_PFC_FUNCTION(scifa3),
- SH_PFC_FUNCTION(scifa4),
- SH_PFC_FUNCTION(scifa5),
- SH_PFC_FUNCTION(scifb0),
- SH_PFC_FUNCTION(scifb1),
- SH_PFC_FUNCTION(scifb2),
- SH_PFC_FUNCTION(scif_clk),
- SH_PFC_FUNCTION(sdhi0),
- SH_PFC_FUNCTION(sdhi1),
- SH_PFC_FUNCTION(sdhi2),
- SH_PFC_FUNCTION(ssi),
- SH_PFC_FUNCTION(usb0),
- SH_PFC_FUNCTION(usb1),
- SH_PFC_FUNCTION(vin0),
- SH_PFC_FUNCTION(vin1),
- SH_PFC_FUNCTION(vin2),
+static const struct {
+ struct sh_pfc_function common[56];
+ struct sh_pfc_function r8a779x[2];
+} pinmux_functions = {
+ .common = {
+ SH_PFC_FUNCTION(audio_clk),
+ SH_PFC_FUNCTION(avb),
+ SH_PFC_FUNCTION(can0),
+ SH_PFC_FUNCTION(can1),
+ SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(du0),
+ SH_PFC_FUNCTION(du1),
+ SH_PFC_FUNCTION(eth),
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(hscif2),
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c4),
+ SH_PFC_FUNCTION(i2c7),
+ SH_PFC_FUNCTION(i2c8),
+ SH_PFC_FUNCTION(intc),
+ SH_PFC_FUNCTION(mmc),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
+ SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm4),
+ SH_PFC_FUNCTION(pwm5),
+ SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(qspi),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif5),
+ SH_PFC_FUNCTION(scifa0),
+ SH_PFC_FUNCTION(scifa1),
+ SH_PFC_FUNCTION(scifa2),
+ SH_PFC_FUNCTION(scifa3),
+ SH_PFC_FUNCTION(scifa4),
+ SH_PFC_FUNCTION(scifa5),
+ SH_PFC_FUNCTION(scifb0),
+ SH_PFC_FUNCTION(scifb1),
+ SH_PFC_FUNCTION(scifb2),
+ SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(ssi),
+ SH_PFC_FUNCTION(usb0),
+ SH_PFC_FUNCTION(usb1),
+ SH_PFC_FUNCTION(vin0),
+ SH_PFC_FUNCTION(vin1),
+ SH_PFC_FUNCTION(vin2),
+ },
+ .r8a779x = {
+ SH_PFC_FUNCTION(adi),
+ SH_PFC_FUNCTION(mlb),
+ }
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -6401,7 +6504,7 @@ static const struct pinmux_cfg_reg pinmu
0, 0, 0, 0,
/* SEL_ADG [1] */
FN_SEL_ADG_0, FN_SEL_ADG_1,
- /* SEL_FM [3] */
+ /* SEL_FM [3] (R8A779x only) */
FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
FN_SEL_FM_3, FN_SEL_FM_4,
0, 0, 0,
@@ -6409,13 +6512,13 @@ static const struct pinmux_cfg_reg pinmu
FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
/* RESERVED [1] */
0, 0,
- /* SEL_GPS [2] */
+ /* SEL_GPS [2] (R8A779x only) */
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
/* SEL_SCIFA4 [2] */
FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
/* SEL_SCIFA3 [2] */
FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
- /* SEL_SIM [1] */
+ /* SEL_SIM [1] (R8A779x only) */
FN_SEL_SIM_0, FN_SEL_SIM_1,
/* RESERVED [1] */
0, 0,
@@ -6441,7 +6544,7 @@ static const struct pinmux_cfg_reg pinmu
FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
/* SEL_SCIF3 [2] */
FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
- /* SEL_IEB [2] */
+ /* SEL_IEB [2] (R8A779x only) */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
/* SEL_MMC [1] */
FN_SEL_MMC_0, FN_SEL_MMC_1,
@@ -6477,11 +6580,11 @@ static const struct pinmux_cfg_reg pinmu
FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
/* RESERVED [1] */
0, 0,
- /* SEL_RAD [1] */
+ /* SEL_RAD [1] (R8A779x only) */
FN_SEL_RAD_0, FN_SEL_RAD_1,
- /* SEL_RCN [1] */
+ /* SEL_RCN [1] (R8A779x only) */
FN_SEL_RCN_0, FN_SEL_RCN_1,
- /* SEL_RSP [1] */
+ /* SEL_RSP [1] (R8A779x only) */
FN_SEL_RSP_0, FN_SEL_RSP_1,
/* SEL_SCIF2 [3] */
FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
@@ -6501,7 +6604,7 @@ static const struct pinmux_cfg_reg pinmu
FN_SEL_SSI1_0, FN_SEL_SSI1_1,
/* SEL_SSI0 [1] */
FN_SEL_SSI0_0, FN_SEL_SSI0_1,
- /* SEL_SSP [2] */
+ /* SEL_SSP [2] (R8A779x only) */
FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
/* RESERVED [2] */
0, 0, 0, 0,
@@ -6527,6 +6630,28 @@ static const struct sh_pfc_soc_operation
.pin_to_pocctrl = r8a7791_pin_to_pocctrl,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A7743
+const struct sh_pfc_soc_info r8a7743_pinmux_info = {
+ .name = "r8a77430_pfc",
+ .ops = &r8a7791_pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
+
#ifdef CONFIG_PINCTRL_PFC_R8A7791
const struct sh_pfc_soc_info r8a7791_pinmux_info = {
.name = "r8a77910_pfc",
@@ -6537,10 +6662,12 @@ const struct sh_pfc_soc_info r8a7791_pin
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
- .groups = pinmux_groups,
- .nr_groups = ARRAY_SIZE(pinmux_groups),
- .functions = pinmux_functions,
- .nr_functions = ARRAY_SIZE(pinmux_functions),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
+ ARRAY_SIZE(pinmux_groups.r8a779x),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
+ ARRAY_SIZE(pinmux_functions.r8a779x),
.cfg_regs = pinmux_config_regs,
@@ -6559,10 +6686,12 @@ const struct sh_pfc_soc_info r8a7793_pin
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
- .groups = pinmux_groups,
- .nr_groups = ARRAY_SIZE(pinmux_groups),
- .functions = pinmux_functions,
- .nr_functions = ARRAY_SIZE(pinmux_functions),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
+ ARRAY_SIZE(pinmux_groups.r8a779x),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
+ ARRAY_SIZE(pinmux_functions.r8a779x),
.cfg_regs = pinmux_config_regs,
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/sh_pfc.h
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -259,6 +259,7 @@ struct sh_pfc_soc_info {
extern const struct sh_pfc_soc_info emev2_pinmux_info;
extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
^ permalink raw reply
* Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC
From: Tyler Baker @ 2017-04-13 20:13 UTC (permalink / raw)
To: Fabio Estevam
Cc: Andrey Smirnov, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Russell King,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring,
Sascha Hauer, Fabio Estevam, Shawn Guo, linux-arm-kernel,
yurovsky-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <CAOMZO5BaKBsXean8-560HUuZbhjef9dpMNku0SRUVtkv+XsZ6w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 13 April 2017 at 12:55, Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On Thu, Apr 13, 2017 at 4:24 PM, Tyler Baker <tyler.baker-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
>
>
>> Are you referring to the following patches?
>>
>> "dt-bindings: Add GPCv2 power gating driver"
>> "soc: imx: Add GPCv2 power gating driver"
>>
>> I've pulled these patches from Shawn's tree to test with, but still
>> not able to get anything functional. Is there another series I should
>> be looking at?
>
> Yes, these are the ones I was thinking about. Maybe Andrey can help to
> clarify then.
I've rebased this series on the next-20170413 for sanity sake, and
realized there doesn't appear to be a way to select CONFIG_IMX_GPCV2.
I forced it using 'default y' and configured with imx_v6_v7_defconfig.
Now my board is booting. Before this series is applied, it may be good
to have CONFIG_IMX_GPCV2 selected specifically for iMX7 platform,
otherwise there will be boot regressions.
I'd encounter a backtrace with next-20170413 + imx_v6_v7_defconfig +
CONFIG_IMX_GPCV2=y
Backtrace:
[<c010c364>] (dump_backtrace) from [<c010c610>] (show_stack+0x18/0x1c)
r7:00000000 r6:600000d3 r5:00000000 r4:c0e273dc
[<c010c5f8>] (show_stack) from [<c04070a4>] (dump_stack+0xb4/0xe8)
[<c0406ff0>] (dump_stack) from [<c0169e04>] (register_lock_class+0x208/0x5ec)
r9:ef00d010 r8:ef00d010 r7:c1606448 r6:00000000 r5:00000000 r4:ffffe000
[<c0169bfc>] (register_lock_class) from [<c016da48>]
(__lock_acquire+0x7c/0x18d0)
r10:c0e0af40 r9:ef00d010 r8:c0e274cc r7:00000001 r6:600000d3 r5:c1606448
r4:ffffe000
[<c016d9cc>] (__lock_acquire) from [<c016fa4c>] (lock_acquire+0x70/0x90)
r10:00000000 r9:ef007e38 r8:00000001 r7:00000001 r6:600000d3 r5:00000000
r4:ffffe000
[<c016f9dc>] (lock_acquire) from [<c09accc8>] (_raw_spin_lock+0x30/0x40)
r8:600000d3 r7:ef007e10 r6:00000001 r5:ef007e10 r4:ef00d000
[<c09acc98>] (_raw_spin_lock) from [<c04403a4>] (imx_gpcv2_irq_unmask+0x1c/0x5c)
r4:ef00d000
[<c0440388>] (imx_gpcv2_irq_unmask) from [<c017e838>] (irq_enable+0x38/0x4c)
r5:00000000 r4:ef007e00
[<c017e800>] (irq_enable) from [<c017e8d0>] (irq_startup+0x84/0x88)
r5:00000000 r4:ef007e00
[<c017e84c>] (irq_startup) from [<c017cd7c>] (__setup_irq+0x538/0x5f4)
r7:ef007e60 r6:00000015 r5:ef007e00 r4:ef007d00
[<c017c844>] (__setup_irq) from [<c017ce98>] (setup_irq+0x60/0xd0)
r10:c0d5fa48 r9:efffcbc0 r8:ef007d00 r7:00000015 r6:ef007e10 r5:00000000
r4:ef007e00
[<c017ce38>] (setup_irq) from [<c0d4dfdc>] (_mxc_timer_init+0x1f8/0x248)
r9:efffcbc0 r8:00000003 r7:016e3600 r6:c0c69bbc r5:ef007c40 r4:ef007c00
[<c0d4dde4>] (_mxc_timer_init) from [<c0d4e0dc>] (mxc_timer_init_dt+0xb0/0xf8)
r7:00000000 r6:c1669e48 r5:ef7ebf7c r4:ef007c00
[<c0d4e02c>] (mxc_timer_init_dt) from [<c0d4e168>]
(imx6dl_timer_init_dt+0x14/0x18)
r9:efffcbc0 r8:c0e7b000 r7:c0c695c0 r6:c0d6fe18 r5:00000001 r4:ef7ebf7c
[<c0d4e154>] (imx6dl_timer_init_dt) from [<c0d4d158>]
(clocksource_probe+0x54/0xb0)
[<c0d4d104>] (clocksource_probe) from [<c0d04a2c>] (time_init+0x30/0x38)
r7:c0e07900 r6:c0e7b000 r5:ffffffff r4:00000000
[<c0d049fc>] (time_init) from [<c0d00bc8>] (start_kernel+0x220/0x3a0)
[<c0d009a8>] (start_kernel) from [<8000807c>] (0x8000807c)
r10:00000000 r9:410fc075 r8:8000406a r7:c0e0c958 r6:c0d5fa44 r5:c0e07918
r4:c0e7b294
Cheers,
Tyler
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^ permalink raw reply
* Re: [PATCH v5] dt-bindings: fpga: Add bindings document for Xilinx LogiCore PR Decoupler
From: Rob Herring @ 2017-04-13 20:07 UTC (permalink / raw)
To: Moritz Fischer
Cc: linux-fpga, devicetree, linux-kernel, gregkh, Michal Simek,
Sören Brinkmann
In-Reply-To: <1491757831-10510-1-git-send-email-mdf@kernel.org>
On Sun, Apr 09, 2017 at 10:10:31AM -0700, Moritz Fischer wrote:
> This adds the binding documentation for the Xilinx LogiCORE PR
> Decoupler soft core.
>
> Signed-off-by: Moritz Fischer <mdf@kernel.org>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> Acked-by: Alan Tull <atull@kernel.org>
> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com>
> Cc: linux-kernel@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
>
> Changes from v4:
> - Ssubject line
> - Replaced 'or' by 'followed by' as suggested by Rob
>
> Changes from v3:
> - Addressed Michal's comments
> - Addressed Alan's Comments
> - Added Alan's Acked-by
>
> Changes from v2:
> - Added refence to generic fpga-region bindings
> - Fixed up reg property in example
> - Added fallback to "xlnx,pr-decoupler" without version
>
> Changes from v1:
> - Added clock names & clock to example
> - Merged some of the description from Michal's version
>
> ---
> .../bindings/fpga/xilinx-pr-decoupler.txt | 36 ++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
> new file mode 100644
> index 0000000..b2c58fb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
> @@ -0,0 +1,36 @@
> +Xilinx LogiCORE Partial Reconfig Decoupler Softcore
> +
> +The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
> +decouplers / fpga bridges.
> +The controller can decouple/disable the bridges which prevents signal
> +changes from passing through the bridge. The controller can also
> +couple / enable the bridges which allows traffic to pass through the
> +bridge normally.
> +
> +The Driver supports only MMIO handling. A PR region can have multiple
> +PR Decouplers which can be handled independently or chained via decouple/
> +decouple_status signals.
> +
> +Required properties:
> +- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
> + "xlnx,pr-decoupler"
> +- regs : base address and size for decoupler module
> +- clocks : input clock to IP
> +- clock-names : should contain "aclk"
> +
> +Optional properties:
> +- bridge-enable : 0 if driver should disable bridge at startup
> + 1 if driver should enable bridge at startup
> + Default is to leave bridge in current state.
Did this get into a common location? If so, then just "see .../?.txt" is
enough of a description.
Rob
^ permalink raw reply
* Re: [PATCH 2/6] dma: pl08x: Add Faraday FTDMAC020 to compatible list
From: Rob Herring @ 2017-04-13 20:03 UTC (permalink / raw)
To: Linus Walleij
Cc: Vinod Koul, dmaengine-u79uwXL29TY76Z2rM5mHXA, Janos Laube,
Paulius Zaleckas, openwrt-devel-p3rKhJxN3npAfugRpC6u6w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Hans Ulli Kroll, Florian Fainelli, Kuo-Jung Su,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170408120457.22750-2-linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Sat, Apr 08, 2017 at 02:04:53PM +0200, Linus Walleij wrote:
> This augments the PL08x bindings to include the Faraday Technology
> FTDMAC020 DMA engine, as it is clearly a derivative of the PL08x
> PrimeCell. Also specify that it needs the special peripheral ID
> specified to work properly.
>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> Seeking a DT maintainer ACK on this.
> ---
> Documentation/devicetree/bindings/dma/arm-pl08x.txt | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v4 08/10] dt-bindings: mediatek: add MT6797 power dt-bindings
From: Rob Herring @ 2017-04-13 20:02 UTC (permalink / raw)
To: Mars Cheng
Cc: Stephen Boyd, Matthias Brugger, CC Hwang, Loda Chou, Miles Chen,
Jades Shih, Yingjoe Chen, Kevin-CW Chen,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
wsd_upstream-NuS5LvNUpcJWk0Htik3J/w
In-Reply-To: <1491614435-23754-9-git-send-email-mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Sat, Apr 08, 2017 at 09:20:33AM +0800, Mars Cheng wrote:
> This adds power dt-bindings for MT6797
>
> Signed-off-by: Mars Cheng <mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Kevin-CW Chen <kevin-cw.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> .../devicetree/bindings/soc/mediatek/scpsys.txt | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH 2/3] dt-bindings: hwmon: Add bindings for Google Chromium EC HWMON
From: Rob Herring @ 2017-04-13 20:01 UTC (permalink / raw)
To: Moritz Fischer
Cc: linux-hwmon-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
lee.jones-QSEj5FYQhm4dnm+yROfE0A, olof-nZhT3qVonbNeoWH0uzbU5w,
linux-0h96xk9xTtrk1uMJSBkQmQ, jdelvare-IBi9RG/b67k,
mark.rutland-5wv7dgnIgG8, Moritz Fischer
In-Reply-To: <1491602410-31518-2-git-send-email-moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w@public.gmane.org>
On Fri, Apr 07, 2017 at 03:00:09PM -0700, Moritz Fischer wrote:
> From: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>
> Add bindings for the Chromium EC HWMON. The Chromium EC HWMON
> allows monitoring of temperature sensors and fans attached to the
> EC.
>
> Signed-off-by: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
> .../devicetree/bindings/hwmon/cros-ec-hwmon.txt | 25 ++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/hwmon/cros-ec-hwmon.txt
>
> diff --git a/Documentation/devicetree/bindings/hwmon/cros-ec-hwmon.txt b/Documentation/devicetree/bindings/hwmon/cros-ec-hwmon.txt
> new file mode 100644
> index 0000000..4c94869
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/hwmon/cros-ec-hwmon.txt
> @@ -0,0 +1,25 @@
> +Chromium Embedded Controller EC temperature and fan control
> +-----------------------------------------------------------
> +
> +Google's Chromium EC HWMON is a hwmon implemented byimplemented by the Chromium EC
> +firmware attached to the Embedded Controller (EC) and controlled via a host-command
> +interface.
> +
> +An EC HWMON node should be only found as a sub-node of the EC node (see
> +Documentation/devicetree/bindings/mfd/cros-ec.txt).
> +
> +Required properties:
> +- compatible: Must contain "google,cros-ec-hwmon"
> +
> +Example:
> + embedded-controller@1e {
> + reg = <0x1e>;
> + compatible = "google,cros-ec-i2c";
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-parent = <&gpio0>;
> +
> + hwmon {
> + compatible = "google,cros-ec-hwmon";
This is sufficient for all devices? I don't see that DT provides
anything here other than instantiating a device, but the parent device
can just as easily do that.
Rob
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^ permalink raw reply
* Re: [PATCH v2 06/11] dt-bindings: add AXP803's regulator info
From: Rob Herring @ 2017-04-13 19:57 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Lee Jones, Chen-Yu Tsai, Maxime Ripard, Liam Girdwood,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170407183441.58750-7-icenowy-h8G6r0blFSE@public.gmane.org>
On Sat, Apr 08, 2017 at 02:34:36AM +0800, Icenowy Zheng wrote:
> AXP803 have the most regulators in currently supported AXP PMICs.
>
> Add info for the regulators in the dt-bindings document.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> ---
> Changes in v2:
> - Place AXP803 regulators before AXP806/809 ones.
>
> Documentation/devicetree/bindings/mfd/axp20x.txt | 27 ++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
^ permalink raw reply
* Re: [PATCH v2 03/11] dt-bindings: add device tree binding for X-Powers AXP803 PMIC
From: Rob Herring @ 2017-04-13 19:56 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Lee Jones, Chen-Yu Tsai, Maxime Ripard, Liam Girdwood,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170407183441.58750-4-icenowy-h8G6r0blFSE@public.gmane.org>
On Sat, Apr 08, 2017 at 02:34:33AM +0800, Icenowy Zheng wrote:
> AXP803 is a PMIC produced by Shenzhen X-Powers, with either I2C or RSB
> bus.
>
> Add a compatible for it.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> Acked-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> ---
> Changes in v2:
> - Place AXP803 before AXP806/809.
> - Added Chen-Yu's ACK.
>
> Documentation/devicetree/bindings/mfd/axp20x.txt | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt
> index b41d2601c6ba..334fb19ce605 100644
> --- a/Documentation/devicetree/bindings/mfd/axp20x.txt
> +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt
> @@ -6,12 +6,13 @@ axp202 (X-Powers)
> axp209 (X-Powers)
> axp221 (X-Powers)
> axp223 (X-Powers)
> +axp803 (X-Powers)
> axp809 (X-Powers)
>
> Required properties:
> - compatible: "x-powers,axp152", "x-powers,axp202", "x-powers,axp209",
> - "x-powers,axp221", "x-powers,axp223", "x-powers,axp806",
> - "x-powers,axp809"
> + "x-powers,axp221", "x-powers,axp223", "x-powers,axp803",
> + "x-powers,axp806", "x-powers,axp809"
If you spin another version, please make this one valid combination per
line. Otherwise,
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
^ permalink raw reply
* Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC
From: Fabio Estevam @ 2017-04-13 19:55 UTC (permalink / raw)
To: Tyler Baker
Cc: Andrey Smirnov, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Russell King,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring,
Sascha Hauer, Fabio Estevam, Shawn Guo, linux-arm-kernel,
yurovsky-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <CANMBJr4BWtU7SXEa0-4LFLx+ydVWas0Cx18kRn-=-Bz8pPZ=fg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Thu, Apr 13, 2017 at 4:24 PM, Tyler Baker <tyler.baker-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> Are you referring to the following patches?
>
> "dt-bindings: Add GPCv2 power gating driver"
> "soc: imx: Add GPCv2 power gating driver"
>
> I've pulled these patches from Shawn's tree to test with, but still
> not able to get anything functional. Is there another series I should
> be looking at?
Yes, these are the ones I was thinking about. Maybe Andrey can help to
clarify then.
Thanks
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^ permalink raw reply
* Re: [PATCH v2 2/4] gpio: aspeed: dt: Add optional clocks property
From: Rob Herring @ 2017-04-13 19:52 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Linus Walleij, Joel Stanley, Benjamin Herrenschmidt, linux-gpio,
devicetree, linux-kernel, openbmc
In-Reply-To: <20170407125902.15960-3-andrew@aj.id.au>
On Fri, Apr 07, 2017 at 10:29:00PM +0930, Andrew Jeffery wrote:
> We need a reference to the HPLL to calculate debounce cycles. If the
> clocks property is not supplied in the GPIO node then the consumer
> should deny any debounce requests.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> Documentation/devicetree/bindings/gpio/gpio-aspeed.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 10/22] ARM: dts: r7s72100: Add generic compatible string for I2C EEPROM
From: Geert Uytterhoeven @ 2017-04-13 19:52 UTC (permalink / raw)
To: Javier Martinez Canillas
Cc: linux-kernel@vger.kernel.org, Wolfram Sang, Simon Horman,
devicetree@vger.kernel.org, Russell King, Linux-Renesas,
Rob Herring, Magnus Damm, Mark Rutland,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20170413182839.25381-11-javier@osg.samsung.com>
On Thu, Apr 13, 2017 at 8:28 PM, Javier Martinez Canillas
<javier@osg.samsung.com> wrote:
> The at24 driver allows to register I2C EEPROM chips using different vendor
> and devices, but the I2C subsystem does not take the vendor into account
> when matching using the I2C table since it only has device entries.
>
> But when matching using an OF table, both the vendor and device has to be
> taken into account so the driver defines only a set of compatible strings
> using the "atmel" vendor as a generic fallback for compatible I2C devices.
>
> So add this generic fallback to the device node compatible string to make
> the device to match the driver using the OF device ID table.
>
> Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> --- a/arch/arm/boot/dts/r7s72100-genmai.dts
> +++ b/arch/arm/boot/dts/r7s72100-genmai.dts
> @@ -57,7 +57,7 @@
> clock-frequency = <400000>;
>
> eeprom@50 {
> - compatible = "renesas,24c128";
> + compatible = "renesas,24c128","atmel,24c128";
Missing space after comma.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2 11/22] ARM: dts: koelsch: Add generic compatible string for I2C EEPROM
From: Geert Uytterhoeven @ 2017-04-13 19:52 UTC (permalink / raw)
To: Javier Martinez Canillas
Cc: linux-kernel@vger.kernel.org, Wolfram Sang, Simon Horman,
devicetree@vger.kernel.org, Russell King, Linux-Renesas,
Rob Herring, Magnus Damm, Mark Rutland,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20170413182839.25381-12-javier@osg.samsung.com>
On Thu, Apr 13, 2017 at 8:28 PM, Javier Martinez Canillas
<javier@osg.samsung.com> wrote:
> The at24 driver allows to register I2C EEPROM chips using different vendor
> and devices, but the I2C subsystem does not take the vendor into account
> when matching using the I2C table since it only has device entries.
>
> But when matching using an OF table, both the vendor and device has to be
> taken into account so the driver defines only a set of compatible strings
> using the "atmel" vendor as a generic fallback for compatible I2C devices.
>
> So add this generic fallback to the device node compatible string to make
> the device to match the driver using the OF device ID table.
>
> Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> --- a/arch/arm/boot/dts/r8a7791-koelsch.dts
> +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
> @@ -702,7 +702,7 @@
> };
>
> eeprom@50 {
> - compatible = "renesas,24c02";
> + compatible = "renesas,24c02","atmel,24c02";
Missing space after comma.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2 1/4] gpio: aspeed: dt: Fix description alignment in bindings document
From: Rob Herring @ 2017-04-13 19:50 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Linus Walleij, Joel Stanley, Benjamin Herrenschmidt, linux-gpio,
devicetree, linux-kernel, openbmc
In-Reply-To: <20170407125902.15960-2-andrew@aj.id.au>
On Fri, Apr 07, 2017 at 10:28:59PM +0930, Andrew Jeffery wrote:
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> Documentation/devicetree/bindings/gpio/gpio-aspeed.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 1/4] pinctrl: aspeed: Document pinconf in devicetree bindings
From: Rob Herring @ 2017-04-13 19:49 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Linus Walleij, Joel Stanley, Benjamin Herrenschmidt,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20170407125713.15678-2-andrew-zrmu5oMJ5Fs@public.gmane.org>
On Fri, Apr 07, 2017 at 10:27:10PM +0930, Andrew Jeffery wrote:
> Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
> ---
> .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 40 +++++++++++++++++-----
> 1 file changed, 31 insertions(+), 9 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH RFC 0/5] *** SPI Slave mode support ***
From: Geert Uytterhoeven @ 2017-04-13 19:47 UTC (permalink / raw)
To: Mark Brown
Cc: jiada_wang-nmGgyN9QBj3QT0dZR+AlfA, Rob Herring, Mark Rutland,
Shawn Guo, Sascha Hauer, Fabio Estevam, linux-spi,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <20170413125929.dygodgj6c35ydh5p-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
On Thu, Apr 13, 2017 at 2:59 PM, Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Thu, Apr 13, 2017 at 05:13:59AM -0700, jiada_wang-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org wrote:
>> From: Jiada Wang <jiada_wang-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
>>
>> v1:
>> add Slave mode support in SPI core
>> spidev create slave device when SPI controller work in slave mode
>> spi-imx support to work in slave mode
>
> Adding Geert who also had a series doing this in progress that was
> getting very near to being merged.
Thank you!
Actually my plan is to fix the last remaining issues and resubmit for v4.13.
References:
- v2: https://lkml.org/lkml/2016/9/12/1065
- v1: https://lkml.org/lkml/2016/6/22/423
BTW Jiada, what's your use case? Just spidev?
Thx!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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^ permalink raw reply
* Re: [PATCH v7 3/9] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
From: Rob Herring @ 2017-04-13 19:44 UTC (permalink / raw)
To: Anurup M
Cc: mark.rutland-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
anurup.m-hv44wF8Li93QT0dZR+AlfA,
zhangshaokun-C8/M+/jPZTeaMJb+Lgu22Q,
tanxiaojun-hv44wF8Li93QT0dZR+AlfA, xuwei5-C8/M+/jPZTeaMJb+Lgu22Q,
sanil.kumar-C8/M+/jPZTeaMJb+Lgu22Q,
john.garry-hv44wF8Li93QT0dZR+AlfA,
gabriele.paoloni-hv44wF8Li93QT0dZR+AlfA,
shiju.jose-hv44wF8Li93QT0dZR+AlfA,
huangdaode-C8/M+/jPZTeaMJb+Lgu22Q,
wangkefeng.wang-hv44wF8Li93QT0dZR+AlfA,
linuxarm-hv44wF8Li93QT0dZR+AlfA, dikshit.n-hv44wF8Li93QT0dZR+AlfA,
shyju.pv-hv44wF8Li93QT0dZR+AlfA
In-Reply-To: <1491303333-140338-1-git-send-email-anurup.m-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
On Tue, Apr 04, 2017 at 06:55:33AM -0400, Anurup M wrote:
> 1) Device tree bindings for Hisilicon SoC PMU.
> 2) Add example for Hisilicon L3 cache and MN PMU.
> 3) Add child nodes of L3C and MN in djtag bindings example.
>
> Signed-off-by: Anurup M <anurup.m-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
> Signed-off-by: Shaokun Zhang <zhangshaokun-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> ---
> .../devicetree/bindings/arm/hisilicon/djtag.txt | 29 +++++++
> .../devicetree/bindings/arm/hisilicon/pmu.txt | 93 ++++++++++++++++++++++
> 2 files changed, 122 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC
From: Tyler Baker @ 2017-04-13 19:24 UTC (permalink / raw)
To: Fabio Estevam
Cc: Andrey Smirnov, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Russell King,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring,
Sascha Hauer, Fabio Estevam, Shawn Guo, linux-arm-kernel,
yurovsky-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <CAOMZO5CgLP7P+Q2Mvzpnx6u5ryb1TjAvaj9xDKXpD+8fMmn7MQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 13 April 2017 at 12:18, Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On Thu, Apr 13, 2017 at 4:03 PM, Tyler Baker <tyler.baker-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
>
>> I've been testing your GPC/PCIe patch sets against v4.11-rc5 on my
>> imx7d-cl-som-imx7, but hit a bit of a wall. When gpc is set as the
>> interrupt-parent for the soc, the kernel seems to hang and not produce
>> any output on the serial port[0]. I tried to enable earlyprintk, but
>> no luck getting a trace. Reversing this change, gets the board
>> booting[1], but obviously isn't using the gpc which is needed for PCIe
>> support as I understand it. I assume you've tested these changes on a
>> imx7d-sdb and are not seeing a similar issue? You can find the patches
>> I've picked on top of v4.11-rc5 here[2], any idea what might be the
>> issue?
>
> Thanks for the report.
No problem.
> It seems this series depends on the drivers/soc/imx/gpcv2.c patches
> that landed into linux-next.
Are you referring to the following patches?
"dt-bindings: Add GPCv2 power gating driver"
"soc: imx: Add GPCv2 power gating driver"
I've pulled these patches from Shawn's tree to test with, but still
not able to get anything functional. Is there another series I should
be looking at?
Thanks,
Tyler
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^ permalink raw reply
* Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC
From: Fabio Estevam @ 2017-04-13 19:18 UTC (permalink / raw)
To: Tyler Baker
Cc: Andrey Smirnov, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Russell King,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring,
Sascha Hauer, Fabio Estevam, Shawn Guo, linux-arm-kernel,
yurovsky-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <CANMBJr5sFeVxVq2w2uUd-ehXi9SpaJ7W9S_PTS_VN25YZEdXvQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Thu, Apr 13, 2017 at 4:03 PM, Tyler Baker <tyler.baker-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> I've been testing your GPC/PCIe patch sets against v4.11-rc5 on my
> imx7d-cl-som-imx7, but hit a bit of a wall. When gpc is set as the
> interrupt-parent for the soc, the kernel seems to hang and not produce
> any output on the serial port[0]. I tried to enable earlyprintk, but
> no luck getting a trace. Reversing this change, gets the board
> booting[1], but obviously isn't using the gpc which is needed for PCIe
> support as I understand it. I assume you've tested these changes on a
> imx7d-sdb and are not seeing a similar issue? You can find the patches
> I've picked on top of v4.11-rc5 here[2], any idea what might be the
> issue?
Thanks for the report.
It seems this series depends on the drivers/soc/imx/gpcv2.c patches
that landed into linux-next.
In this case, it would be better to re-send this series after
4.12-rc11 is out to avoid the breakage.
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* Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC
From: Tyler Baker @ 2017-04-13 19:03 UTC (permalink / raw)
To: Andrey Smirnov
Cc: Shawn Guo, yurovsky, Sascha Hauer, Fabio Estevam, Rob Herring,
Mark Rutland, Russell King, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-kernel
In-Reply-To: <20170413133242.5068-5-andrew.smirnov@gmail.com>
Hi Andrey,
On 13 April 2017 at 06:32, Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
> Add node for GPC and specify as a parent interrupt controller for SoC bus.
>
> Cc: yurovsky@gmail.com
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
> arch/arm/boot/dts/imx7s.dtsi | 27 ++++++++++++++++++++++++++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
> index 8fee299..1a7058f 100644
> --- a/arch/arm/boot/dts/imx7s.dtsi
> +++ b/arch/arm/boot/dts/imx7s.dtsi
> @@ -42,6 +42,7 @@
> */
>[0
> #include <dt-bindings/clock/imx7d-clock.h>
> +#include <dt-bindings/power/imx7-power.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -119,7 +120,7 @@
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "simple-bus";
> - interrupt-parent = <&intc>;
> + interrupt-parent = <&gpc>;
I've been testing your GPC/PCIe patch sets against v4.11-rc5 on my
imx7d-cl-som-imx7, but hit a bit of a wall. When gpc is set as the
interrupt-parent for the soc, the kernel seems to hang and not produce
any output on the serial port[0]. I tried to enable earlyprintk, but
no luck getting a trace. Reversing this change, gets the board
booting[1], but obviously isn't using the gpc which is needed for PCIe
support as I understand it. I assume you've tested these changes on a
imx7d-sdb and are not seeing a similar issue? You can find the patches
I've picked on top of v4.11-rc5 here[2], any idea what might be the
issue?
Cheers,
Tyler
[0] https://hastebin.com/zetohetuwi.coffeescript
[1] https://hastebin.com/uvacuyicuh.sql
[2] https://github.com/EmbeddedAndroid/linux/commits/tracking-ltd-imx-dev
^ permalink raw reply
* [PATCH v2 22/22] powerpc/44x: Add generic compatible string for I2C EEPROM
From: Javier Martinez Canillas @ 2017-04-13 18:28 UTC (permalink / raw)
To: linux-kernel
Cc: Wolfram Sang, Javier Martinez Canillas, devicetree,
Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Rob Herring, Mark Rutland, linuxppc-dev
In-Reply-To: <20170413182839.25381-1-javier@osg.samsung.com>
The at24 driver allows to register I2C EEPROM chips using different vendor
and devices, but the I2C subsystem does not take the vendor into account
when matching using the I2C table since it only has device entries.
But when matching using an OF table, both the vendor and device has to be
taken into account so the driver defines only a set of compatible strings
using the "atmel" vendor as a generic fallback for compatible I2C devices.
So add this generic fallback to the device node compatible string to make
the device to match the driver using the OF device ID table.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v2: None
arch/powerpc/boot/dts/warp.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/warp.dts b/arch/powerpc/boot/dts/warp.dts
index e576ee85c42f..5b36dbf6c9f4 100644
--- a/arch/powerpc/boot/dts/warp.dts
+++ b/arch/powerpc/boot/dts/warp.dts
@@ -238,7 +238,7 @@
/* This will create 52 and 53 */
at24@52 {
- compatible = "at,24c04";
+ compatible = "at,24c04","atmel,24c04";
reg = <0x52>;
};
};
--
2.9.3
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