* [PATCH v2] input: touchscreen: ar1021_i2c: highlight support for AR1020
From: Martin Kepplinger @ 2017-04-14 6:02 UTC (permalink / raw)
To: robh, dmitry.torokhov
Cc: christian.gmeiner, linux, linux-input, linux-kernel, devicetree,
Martin Kepplinger
In-Reply-To: <20170413203532.thktt4yhqsg34cvc@rob-hp-laptop>
ar1021_i2c simply also supports the ar1020 device I'm using. This is
tested. They also share the same datasheet:
http://ww1.microchip.com/downloads/en/DeviceDoc/40001393C.pdf
So let users see that they have a compatible in front of them by adding
AR1020 to the driver's description.
Signed-off-by: Martin Kepplinger <martin.kepplinger@ginzinger.com>
---
revision history
----------------
v2: leave compatible string untouched. only add description.
v1: initial idea.
drivers/input/touchscreen/Kconfig | 4 ++--
drivers/input/touchscreen/ar1021_i2c.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 33c62e5..535b91a 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -96,8 +96,8 @@ config TOUCHSCREEN_AR1021_I2C
tristate "Microchip AR1021 i2c touchscreen"
depends on I2C && OF
help
- Say Y here if you have the Microchip AR1021 touchscreen controller
- chip in your system.
+ Say Y here if you have the Microchip AR1020 or AR1021 touchscreen
+ controller chip in your system.
If unsure, say N.
diff --git a/drivers/input/touchscreen/ar1021_i2c.c b/drivers/input/touchscreen/ar1021_i2c.c
index 2e7500e..03784d2 100644
--- a/drivers/input/touchscreen/ar1021_i2c.c
+++ b/drivers/input/touchscreen/ar1021_i2c.c
@@ -1,5 +1,5 @@
/*
- * Microchip AR1021 driver for I2C
+ * Microchip AR1020 and AR1021 driver for I2C
*
* Author: Christian Gmeiner <christian.gmeiner@gmail.com>
*
@@ -175,5 +175,5 @@ static struct i2c_driver ar1021_i2c_driver = {
module_i2c_driver(ar1021_i2c_driver);
MODULE_AUTHOR("Christian Gmeiner <christian.gmeiner@gmail.com>");
-MODULE_DESCRIPTION("Microchip AR1021 I2C Driver");
+MODULE_DESCRIPTION("Microchip AR1020 and AR1021 I2C Driver");
MODULE_LICENSE("GPL");
--
2.1.4
^ permalink raw reply related
* Re: [PATCH RFC 0/5] *** SPI Slave mode support ***
From: Jiada Wang @ 2017-04-14 5:39 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Mark Brown, Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Fabio Estevam, linux-spi,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <CAMuHMdUm=90ddNWM5KWqT+W0hqZ-QO6vPHj5OisbYquDYq1ZmA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hello Geert
On 04/13/2017 12:47 PM, Geert Uytterhoeven wrote:
> On Thu, Apr 13, 2017 at 2:59 PM, Mark Brown<broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>> On Thu, Apr 13, 2017 at 05:13:59AM -0700, jiada_wang-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org wrote:
>>> From: Jiada Wang<jiada_wang-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
>>>
>>> v1:
>>> add Slave mode support in SPI core
>>> spidev create slave device when SPI controller work in slave mode
>>> spi-imx support to work in slave mode
>> Adding Geert who also had a series doing this in progress that was
>> getting very near to being merged.
> Thank you!
>
> Actually my plan is to fix the last remaining issues and resubmit for v4.13.
I noticed your patch set for SPI slave support,
(I am sure you can find out some of the change
in this patch set is based on your work).
we have similar requirement to add slave mode support to ecspi IP on
imx6 Soc.
Our use case is to use spidev as an interface to communicate with
external SPI master devices.
meanwhile the SPI bus controller can also act as master device to send
data to other
SPI slave devices on the board.
I found in your implementation, SPI bus controller is limited to either
work in master mode or
slave mode, is there any reasoning to not configure SPI mode based on
SPI devices use case?
Thanks,
Jiada
> References:
> - v2: https://lkml.org/lkml/2016/9/12/1065
> - v1: https://lkml.org/lkml/2016/6/22/423
>
> BTW Jiada, what's your use case? Just spidev?
>
> Thx!
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe linux-spi" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 3/3] arm64: dts: exynos: Add support for S6E3HA2 edge panel device on TM2e board
From: Hoegeun Kwon @ 2017-04-14 5:19 UTC (permalink / raw)
To: thierry.reding, airlied, robh+dt, mark.rutland, catalin.marinas,
will.deacon, kgene, krzk
Cc: devicetree, linux-samsung-soc, linux-kernel, dri-devel, javier,
andi.shyti, Hoegeun Kwon, linux-arm-kernel
In-Reply-To: <1492147179-7824-1-git-send-email-hoegeun.kwon@samsung.com>
This patch add the panel device tree node for S6E3HA2 edge display
controller to TM2e dts.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
index 694717a..79f22f7 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -52,6 +52,18 @@
assigned-clock-rates = <278000000>, <400000000>;
};
+&dsi {
+ panel@0 {
+ compatible = "samsung,s6e3ha2-e";
+ reg = <0>;
+ vdd3-supply = <&ldo27_reg>;
+ vci-supply = <&ldo28_reg>;
+ reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
+ te-gpios = <&gpf1 3 GPIO_ACTIVE_HIGH>;
+ };
+};
+
&ldo31_reg {
regulator-name = "TSP_VDD_1.8V_AP";
regulator-min-microvolt = <1800000>;
--
1.9.1
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH 2/3] drm/panel: s6e3ha2: Add support for S6eHEA2 edge panel on TM2e board
From: Hoegeun Kwon @ 2017-04-14 5:19 UTC (permalink / raw)
To: thierry.reding, airlied, robh+dt, mark.rutland, catalin.marinas,
will.deacon, kgene, krzk
Cc: dri-devel, devicetree, linux-arm-kernel, linux-samsung-soc,
linux-kernel, javier, a.hajda, andi.shyti, Hoegeun Kwon
In-Reply-To: <1492147179-7824-1-git-send-email-hoegeun.kwon@samsung.com>
This patch considers edge type of panel on TM2e board and The panel
has 1600x2560 resolution in 5.65" physical panel in the TM2e device.
This identify panel type with compatibility string, also invoke
display mode that matches the type. So add the check code for default
compatibility and edge type and select the drm_display_mode of default
and edge type.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
---
drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c | 62 ++++++++++++++++++++++++---
1 file changed, 56 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c b/drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c
index 4cc08d7..b4a064a 100644
--- a/drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c
+++ b/drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c
@@ -16,6 +16,7 @@
#include <drm/drm_panel.h>
#include <linux/backlight.h>
#include <linux/gpio/consumer.h>
+#include <linux/of_device.h>
#include <linux/regulator/consumer.h>
#define S6E3HA2_MIN_BRIGHTNESS 0
@@ -218,6 +219,16 @@
0x1d, 0x1e, 0x1f, 0x20, 0x21
};
+enum s6e3ha2_type {
+ DEFAULT_TYPE,
+ EDGE_TYPE,
+};
+
+struct s6e3ha2_panel_desc {
+ const struct drm_display_mode *mode;
+ enum s6e3ha2_type type;
+};
+
struct s6e3ha2 {
struct device *dev;
struct drm_panel panel;
@@ -226,6 +237,8 @@ struct s6e3ha2 {
struct regulator_bulk_data supplies[2];
struct gpio_desc *reset_gpio;
struct gpio_desc *enable_gpio;
+
+ const struct s6e3ha2_panel_desc *desc;
};
static int s6e3ha2_dcs_write(struct s6e3ha2 *ctx, const void *data, size_t len)
@@ -283,11 +296,19 @@ static int s6e3ha2_single_dsi_set(struct s6e3ha2 *ctx)
static int s6e3ha2_freq_calibration(struct s6e3ha2 *ctx)
{
s6e3ha2_dcs_write_seq_static(ctx, 0xfd, 0x1c);
+ if (ctx->desc->type == EDGE_TYPE)
+ s6e3ha2_dcs_write_seq_static(ctx, 0xf2, 0x67, 0x40, 0xc5);
s6e3ha2_dcs_write_seq_static(ctx, 0xfe, 0x20, 0x39);
s6e3ha2_dcs_write_seq_static(ctx, 0xfe, 0xa0);
s6e3ha2_dcs_write_seq_static(ctx, 0xfe, 0x20);
- s6e3ha2_dcs_write_seq_static(ctx, 0xce, 0x03, 0x3b, 0x12, 0x62, 0x40,
- 0x80, 0xc0, 0x28, 0x28, 0x28, 0x28, 0x39, 0xc5);
+
+ if (ctx->desc->type == DEFAULT_TYPE)
+ s6e3ha2_dcs_write_seq_static(ctx, 0xce, 0x03, 0x3b, 0x12, 0x62,
+ 0x40, 0x80, 0xc0, 0x28, 0x28, 0x28, 0x28, 0x39, 0xc5);
+ else
+ s6e3ha2_dcs_write_seq_static(ctx, 0xce, 0x03, 0x3b, 0x14, 0x6d,
+ 0x40, 0x80, 0xc0, 0x28, 0x28, 0x28, 0x28, 0x39, 0xc5);
+
return 0;
}
@@ -597,16 +618,41 @@ static int s6e3ha2_enable(struct drm_panel *panel)
.flags = 0,
};
+static const struct s6e3ha2_panel_desc samsung_s6e3ha2_tm2 = {
+ .mode = &default_mode,
+ .type = DEFAULT_TYPE,
+};
+
+static const struct drm_display_mode edge_mode = {
+ .clock = 247856,
+ .hdisplay = 1600,
+ .hsync_start = 1600 + 1,
+ .hsync_end = 1600 + 1 + 1,
+ .htotal = 1600 + 1 + 1 + 1,
+ .vdisplay = 2560,
+ .vsync_start = 2560 + 1,
+ .vsync_end = 2560 + 1 + 1,
+ .vtotal = 2560 + 1 + 1 + 15,
+ .vrefresh = 60,
+ .flags = 0,
+};
+
+static const struct s6e3ha2_panel_desc samsung_s6e3ha2_tm2e = {
+ .mode = &edge_mode,
+ .type = EDGE_TYPE,
+};
+
static int s6e3ha2_get_modes(struct drm_panel *panel)
{
struct drm_connector *connector = panel->connector;
+ struct s6e3ha2 *ctx = container_of(panel, struct s6e3ha2, panel);
struct drm_display_mode *mode;
- mode = drm_mode_duplicate(panel->drm, &default_mode);
+ mode = drm_mode_duplicate(panel->drm, ctx->desc->mode);
if (!mode) {
DRM_ERROR("failed to add mode %ux%ux@%u\n",
- default_mode.hdisplay, default_mode.vdisplay,
- default_mode.vrefresh);
+ ctx->desc->mode->hdisplay, ctx->desc->mode->vdisplay,
+ ctx->desc->mode->vrefresh);
return -ENOMEM;
}
@@ -642,6 +688,7 @@ static int s6e3ha2_probe(struct mipi_dsi_device *dsi)
mipi_dsi_set_drvdata(dsi, ctx);
ctx->dev = dev;
+ ctx->desc = of_device_get_match_data(dev);
dsi->lanes = 4;
dsi->format = MIPI_DSI_FMT_RGB888;
@@ -717,7 +764,10 @@ static int s6e3ha2_remove(struct mipi_dsi_device *dsi)
}
static const struct of_device_id s6e3ha2_of_match[] = {
- { .compatible = "samsung,s6e3ha2" },
+ { .compatible = "samsung,s6e3ha2",
+ .data = &samsung_s6e3ha2_tm2 },
+ { .compatible = "samsung,s6e3ha2-e",
+ .data = &samsung_s6e3ha2_tm2e },
{ }
};
MODULE_DEVICE_TABLE(of, s6e3ha2_of_match);
--
1.9.1
^ permalink raw reply related
* [PATCH 1/3] dt-bindings: Add support for samsung s6e3ha2 edge panel binding
From: Hoegeun Kwon @ 2017-04-14 5:19 UTC (permalink / raw)
To: thierry.reding, airlied, robh+dt, mark.rutland, catalin.marinas,
will.deacon, kgene, krzk
Cc: devicetree, linux-samsung-soc, linux-kernel, dri-devel, javier,
andi.shyti, Hoegeun Kwon, linux-arm-kernel
In-Reply-To: <1492147179-7824-1-git-send-email-hoegeun.kwon@samsung.com>
The Samsung s6e3ha2 edge is a 5.65" 1600x2560 AMOLED panel connected
using MIPI-DSI interfaces.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
---
.../bindings/display/panel/samsung,s6e3ha2-e.txt | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/samsung,s6e3ha2-e.txt
diff --git a/Documentation/devicetree/bindings/display/panel/samsung,s6e3ha2-e.txt b/Documentation/devicetree/bindings/display/panel/samsung,s6e3ha2-e.txt
new file mode 100644
index 0000000..09c65f6
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/samsung,s6e3ha2-e.txt
@@ -0,0 +1,28 @@
+Samsung S6E3HA2 5.65" 1600x2560 AMOLED panel
+
+Required properties:
+ - compatible: "samsung,s6e3ha2-e"
+ - reg: the virtual channel number of a DSI peripheral
+ - vdd3-supply: I/O voltage supply
+ - vci-supply: voltage supply for analog circuits
+ - reset-gpios: a GPIO spec for the reset pin (active low)
+ - enable-gpios: a GPIO spec for the panel enable pin (active high)
+
+Optional properties:
+ - te-gpios: a GPIO spec for the tearing effect synchronization signal
+ gpio pin (active high)
+
+Example:
+&dsi {
+ ...
+
+ panel@0 {
+ compatible = "samsung,s6e3ha2-e";
+ reg = <0>;
+ vdd3-supply = <&ldo27_reg>;
+ vci-supply = <&ldo28_reg>;
+ reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
+ te-gpios = <&gpf1 3 GPIO_ACTIVE_HIGH>;
+ };
+};
--
1.9.1
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH 0/3] Add support for the S6E3HA2 edge panel on TM2e board
From: Hoegeun Kwon @ 2017-04-14 5:19 UTC (permalink / raw)
To: thierry.reding, airlied, robh+dt, mark.rutland, catalin.marinas,
will.deacon, kgene, krzk
Cc: dri-devel, devicetree, linux-arm-kernel, linux-samsung-soc,
linux-kernel, javier, a.hajda, andi.shyti, Hoegeun Kwon
In-Reply-To: <CGME20170414051958epcas5p379f82e72e9239fdea0b99de88c4c39f1@epcas5p3.samsung.com>
The purpose of this patch is add support for S6E3HA2 edge AMOLED panel
on the TM2e board. The panel has 1600x2560 resolution in 5.65"
physical panel in the TM2e device.
The S6E3HA2 edge panel(5.65") is simliar to the previous S6E3HA2
panel(5.7"), but resolution and some command message are different. So
it can be distinguished as a compatiblitiy string.
Best regards,
Hoegeun
Hoegeun Kwon (3):
dt-bindings: Add support for samsung s6e3ha2 edge panel binding
drm/panel: s6e3ha2: Add support for S6eHEA2 edge panel on TM2e board
arm64: dts: exynos: Add support for S6E3HA2 edge panel device on TM2e
board
.../bindings/display/panel/samsung,s6e3ha2-e.txt | 28 ++++++++++
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 12 +++++
drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c | 62 +++++++++++++++++++---
3 files changed, 96 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/panel/samsung,s6e3ha2-e.txt
--
1.9.1
^ permalink raw reply
* Re: [PATCH 2/2] hwrng: mtk: Add driver for hardware random generator on MT7623 SoC
From: PrasannaKumar Muralidharan @ 2017-04-14 4:57 UTC (permalink / raw)
To: Sean Wang
Cc: Herbert Xu, Matt Mackall, Rob Herring, Mark Rutland,
Corentin LABBE, Romain Perier, shannon.nelson, Wei Yongjun,
devicetree, linux-crypto, linux-mediatek, linux-arm-kernel,
linux-kernel, sean wang
In-Reply-To: <1492142296.6147.19.camel@mtkswgap22>
On 14 April 2017 at 09:28, Sean Wang <sean.wang@mediatek.com> wrote:
>
> Hi PrasannaKumar,
>
> Add my comments inline
>
>>
>> Use readl_poll_timeout_atomic's return value or -EIO instead of
>> !!ready. This will simplify mtk_rng_read.
>>
>
> !!ready provided is in order to let blocking/non-blocking case could
> share same code path. And readl_poll_timeout_atomic only handles
> blocking case.
Missed this point. Makes sense. My previous comment about return value
in mtk_rng_read is invalid as I based it on a wrong assumption.
>
>> > +static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
>> > +{
>> > + struct mtk_rng *priv = to_mtk_rng(rng);
>> > + int retval = 0;
>> > +
>> > + while (max >= sizeof(u32)) {
>> > + if (!mtk_rng_wait_ready(rng, wait))
>> > + break;
>> > +
>> > + *(u32 *)buf = readl(priv->base + RNG_DATA);
>> > + retval += sizeof(u32);
>> > + buf += sizeof(u32);
>> > + max -= sizeof(u32);
>> > + }
>> > +
>> > + if (unlikely(wait && max))
>> > + dev_warn(priv->dev, "timeout might be not properly set\n");
>>
>> Is this really necessary? Better to choose proper timeout than
>> providing this warning message. In rare cases if the timeout could
>> occur due to some reason (may be a hardware fault) print appropriate
>> warning message.
>
> It is good, I will choose the proper timeout and remove the log in the
> next one.
>
>>
>> > + return retval || !wait ? retval : -EIO;
>> > +}
>>
>> Set retavl to mtk_rng_wait_ready and return retval.
>>
>
> Maybe i didn't get your points exactly. Adding some explanation about
> thoughts here.
>
> "return retval || !wait ? retval : -EIO;" I use can also help handling
> the both cases in one line which i think is elegant enough.
>
> And retval is accumulated with each round if some data's existing in
> hardware, so we don't return the value from mtk_rng_wait_ready().
retval can be 0 only when mkt_rng_wait_ready fails, returning 0 when
wait is true is confusing. Expected return value when 0 bytes is read
from device and wait is true is not clearly documented.
"return retval || !wait ? retval : -EIO;" is also fine.
Overall the code looks good to me. You can add:
Reviewed-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>.
Regards,
PrasannaKumar
^ permalink raw reply
* Re: [PATCH 2/2] hwrng: mtk: Add driver for hardware random generator on MT7623 SoC
From: Sean Wang @ 2017-04-14 3:58 UTC (permalink / raw)
To: PrasannaKumar Muralidharan
Cc: Herbert Xu, Matt Mackall, Rob Herring, Mark Rutland,
Corentin LABBE, Romain Perier, shannon.nelson, Wei Yongjun,
devicetree, linux-crypto, linux-mediatek, linux-arm-kernel,
linux-kernel, keyhaede
In-Reply-To: <CANc+2y4Oj-sbSKnsTSK+kRYNewp7Pj0fEk_=dqULxWG08L77Eg@mail.gmail.com>
Hi PrasannaKumar,
Add my comments inline
On Thu, 2017-04-13 at 14:09 +0530, PrasannaKumar Muralidharan wrote:
> Hi Sean,
>
> Mostly looks good, have few minor comments.
>
> On 13 April 2017 at 12:35, <sean.wang@mediatek.com> wrote:
> > +static bool mtk_rng_wait_ready(struct hwrng *rng, bool wait)
> > +{
> > + struct mtk_rng *priv = to_mtk_rng(rng);
> > + int ready;
> > +
> > + ready = readl(priv->base + RNG_CTRL) & RNG_READY;
> > + if (!ready && wait)
> > + readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
> > + ready & RNG_READY, USEC_POLL,
> > + TIMEOUT_POLL);
> > + return !!ready;
> > +}
>
> Use readl_poll_timeout_atomic's return value or -EIO instead of
> !!ready. This will simplify mtk_rng_read.
>
!!ready provided is in order to let blocking/non-blocking case could
share same code path. And readl_poll_timeout_atomic only handles
blocking case.
> > +static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
> > +{
> > + struct mtk_rng *priv = to_mtk_rng(rng);
> > + int retval = 0;
> > +
> > + while (max >= sizeof(u32)) {
> > + if (!mtk_rng_wait_ready(rng, wait))
> > + break;
> > +
> > + *(u32 *)buf = readl(priv->base + RNG_DATA);
> > + retval += sizeof(u32);
> > + buf += sizeof(u32);
> > + max -= sizeof(u32);
> > + }
> > +
> > + if (unlikely(wait && max))
> > + dev_warn(priv->dev, "timeout might be not properly set\n");
>
> Is this really necessary? Better to choose proper timeout than
> providing this warning message. In rare cases if the timeout could
> occur due to some reason (may be a hardware fault) print appropriate
> warning message.
It is good, I will choose the proper timeout and remove the log in the
next one.
>
> > + return retval || !wait ? retval : -EIO;
> > +}
>
> Set retavl to mtk_rng_wait_ready and return retval.
>
Maybe i didn't get your points exactly. Adding some explanation about
thoughts here.
"return retval || !wait ? retval : -EIO;" I use can also help handling
the both cases in one line which i think is elegant enough.
And retval is accumulated with each round if some data's existing in
hardware, so we don't return the value from mtk_rng_wait_ready().
> Regards,
> Prasanna
thanks for all your reviewing and suggestion
Sean
^ permalink raw reply
* Re: [PATCH 8/8] ARM: dts: imx7d-sdb: Enable PCIe peripheral
From: Shawn Guo @ 2017-04-14 3:51 UTC (permalink / raw)
To: Andrey Smirnov
Cc: yurovsky-Re5JQEeQqe8AvxtiuMwx3w, Sascha Hauer, Fabio Estevam,
Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170413133242.5068-9-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Thu, Apr 13, 2017 at 06:32:42AM -0700, Andrey Smirnov wrote:
> Enable PCIe peripheral on this board.
>
> Cc: yurovsky-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
> Cc: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/boot/dts/imx7d-sdb.dts | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
> index e0ff276..f77e26a 100644
> --- a/arch/arm/boot/dts/imx7d-sdb.dts
> +++ b/arch/arm/boot/dts/imx7d-sdb.dts
> @@ -352,6 +352,13 @@
> };
> };
>
> +&pcie {
> + pinctrl-names = "default";
> + reset-gpio = <&gpio_spi 1 GPIO_ACTIVE_LOW>;
> + disable-gpio = <&gpio_spi 0 GPIO_ACTIVE_LOW>;
I do not see this disable-gpio is documented or supported.
Shawn
> + status = "okay";
> +};
> +
> &pwm1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pwm1>;
> --
> 2.9.3
>
--
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^ permalink raw reply
* Re: [PATCH 6/8] ARM: dts: imx7d-sdb: Add GPIO expander node
From: Shawn Guo @ 2017-04-14 3:47 UTC (permalink / raw)
To: Andrey Smirnov
Cc: yurovsky-Re5JQEeQqe8AvxtiuMwx3w, Sascha Hauer, Fabio Estevam,
Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170413133242.5068-7-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Thu, Apr 13, 2017 at 06:32:40AM -0700, Andrey Smirnov wrote:
> Add node for U38, a 74LV595PW serial-in shift register that acts as a
> GPIO expander on the board.
>
> Cc: yurovsky-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
> Cc: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/boot/dts/imx7d-sdb.dts | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
> index 5be01a1..e0ff276 100644
> --- a/arch/arm/boot/dts/imx7d-sdb.dts
> +++ b/arch/arm/boot/dts/imx7d-sdb.dts
> @@ -52,6 +52,30 @@
> reg = <0x80000000 0x80000000>;
> };
>
> + spi4 {
> + compatible = "spi-gpio";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_spi1>;
> + status = "okay";
The 'status' is not needed in this case.
> + gpio-sck = <&gpio1 13 0>;
> + gpio-mosi = <&gpio1 9 0>;
> + cs-gpios = <&gpio1 12 0>;
> + num-chipselects = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio_spi: gpio_spi@0 {
gpio-expander might be a better node name?
> + compatible = "fairchild,74hc595";
> + gpio-controller;
> + #gpio-cells = <2>;
> + reg = <0>;
> + registers-number = <1>;
> + /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/
> + registers-default = /bits/ 8 <0x74>;
I do not see this property is documented or supported by kernel.
> + spi-max-frequency = <100000>;
> + };
> + };
> +
> regulators {
> compatible = "simple-bus";
> #address-cells = <1>;
> @@ -642,5 +666,13 @@
> fsl,pins = <
> MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0
> >;
> +
> + pinctrl_spi1: spi1grp {
> + fsl,pins = <
> + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
> + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
> + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
> + >;
> + };
> };
> };
> --
> 2.9.3
>
--
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^ permalink raw reply
* Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC
From: Shawn Guo @ 2017-04-14 3:40 UTC (permalink / raw)
To: Andrey Smirnov
Cc: yurovsky-Re5JQEeQqe8AvxtiuMwx3w, Sascha Hauer, Fabio Estevam,
Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170413133242.5068-5-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Thu, Apr 13, 2017 at 06:32:38AM -0700, Andrey Smirnov wrote:
> Add node for GPC and specify as a parent interrupt controller for SoC bus.
>
> Cc: yurovsky-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
> Cc: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/boot/dts/imx7s.dtsi | 27 ++++++++++++++++++++++++++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
> index 8fee299..1a7058f 100644
> --- a/arch/arm/boot/dts/imx7s.dtsi
> +++ b/arch/arm/boot/dts/imx7s.dtsi
> @@ -42,6 +42,7 @@
> */
>
> #include <dt-bindings/clock/imx7d-clock.h>
> +#include <dt-bindings/power/imx7-power.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -119,7 +120,7 @@
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "simple-bus";
> - interrupt-parent = <&intc>;
> + interrupt-parent = <&gpc>;
> ranges;
>
> funnel@30041000 {
> @@ -301,6 +302,7 @@
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> #interrupt-cells = <3>;
> interrupt-controller;
> + interrupt-parent = <&intc>;
> reg = <0x31001000 0x1000>,
> <0x31002000 0x2000>,
> <0x31004000 0x2000>,
> @@ -309,6 +311,7 @@
>
> timer {
> compatible = "arm,armv7-timer";
> + interrupt-parent = <&intc>;
> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> @@ -564,6 +567,28 @@
> interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> #reset-cells = <1>;
> };
> +
> + gpc: gpc@303a0000 {
> + compatible = "fsl,imx7d-gpc";
> + reg = <0x303a0000 0x10000>;
> + interrupt-controller;
> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&intc>;
> + #power-domain-cells = <1>;
> +
> + pgc {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pgc_pcie_phy: pgc-pcie-phy-domain {
The node name should be something generic and has a unit-address when
there is a 'reg' property in the node.
> + #power-domain-cells = <0>;
> +
Drop this newline.
Shawn
> + reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;
> + power-supply = <®_1p0d>;
> + };
> + };
> + };
> };
>
> aips2: aips-bus@30400000 {
> --
> 2.9.3
>
--
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^ permalink raw reply
* Re: [PATCH 2/2] hwrng: mtk: Add driver for hardware random generator on MT7623 SoC
From: Sean Wang @ 2017-04-14 3:38 UTC (permalink / raw)
To: Corentin Labbe
Cc: herbert-lOAM2aK0SrRLBo1qDEOMRrpzq4S04n8Q,
mpm-VDJrAJ4Gl5ZBDgjK7y7TUQ, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, prasannatsmkumar-Re5JQEeQqe8AvxtiuMwx3w,
romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
shannon.nelson-QHcLZuEGTsvQT0dZR+AlfA,
weiyongjun1-hv44wF8Li93QT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-crypto-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
keyhaede-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <20170413110643.GA413@Red>
Hi Corentin,
I all agree and appreciate your careful reviewing.
They will be added into the next one.
Sean
On Thu, 2017-04-13 at 13:06 +0200, Corentin Labbe wrote:
> Hello
>
> I have some minor comment below:
>
> On Thu, Apr 13, 2017 at 03:05:08PM +0800, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote:
> > From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> >
> > This patch adds support for hardware random generator on MT7623 SoC
> > and should also work on other similar Mediatek SoCs. Currently,
> > the driver is already tested successfully with rng-tools.
> >
> > Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> > drivers/char/hw_random/Kconfig | 16 +++-
> > drivers/char/hw_random/Makefile | 2 +-
> > drivers/char/hw_random/mtk-rng.c | 174 +++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 190 insertions(+), 2 deletions(-)
> > create mode 100644 drivers/char/hw_random/mtk-rng.c
> >
> > diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
> > index 0cafe08..af782ce 100644
> > --- a/drivers/char/hw_random/Kconfig
> > +++ b/drivers/char/hw_random/Kconfig
> > @@ -419,10 +419,24 @@ config HW_RANDOM_CAVIUM
> > Generator hardware found on Cavium SoCs.
> >
> > To compile this driver as a module, choose M here: the
> > - module will be called cavium_rng.
> > + module will be called mtk-rng.
>
> Unwanted change
>
> >
> > If unsure, say Y.
> >
> > +config HW_RANDOM_MTK
> > + tristate "Mediatek Random Number Generator support"
> > + depends on HW_RANDOM
> > + depends on ARCH_MEDIATEK || COMPILE_TEST
> > + default y
> > + ---help---
> > + This driver provides kernel-side support for the Random Number
> > + Generator hardware found on Mediatek SoCs.
> > +
> > + To compile this driver as a module, choose M here. the
> > + module will be called mtk-rng.
> > +
> > + If unsure, say Y.
> > +
> > endif # HW_RANDOM
> >
> > config UML_RANDOM
> > diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
> > index 5f52b1e..68be716 100644
> > --- a/drivers/char/hw_random/Makefile
> > +++ b/drivers/char/hw_random/Makefile
> > @@ -1,7 +1,6 @@
> > #
> > # Makefile for HW Random Number Generator (RNG) device drivers.
> > #
> > -
>
> Another unwanted change
>
> > obj-$(CONFIG_HW_RANDOM) += rng-core.o
> > rng-core-y := core.o
> > obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += timeriomem-rng.o
> > @@ -36,3 +35,4 @@ obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
> > obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
> > obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
> > obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
> > +obj-$(CONFIG_HW_RANDOM_MTK) += mtk-rng.o
> > diff --git a/drivers/char/hw_random/mtk-rng.c b/drivers/char/hw_random/mtk-rng.c
> > new file mode 100644
> > index 0000000..6561ee0
> > --- /dev/null
> > +++ b/drivers/char/hw_random/mtk-rng.c
> > @@ -0,0 +1,174 @@
> > +/*
> > + * Driver for Mediatek Hardware Random Number Generator
> > + *
> > + * Copyright (C) 2017 Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +#define MTK_RNG_DEV KBUILD_MODNAME
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/err.h>
> > +#include <linux/hw_random.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +
> > +#define USEC_POLL 2
> > +#define TIMEOUT_POLL 20
> > +
> > +#define RNG_CTRL 0x00
> > +#define RNG_EN BIT(0)
> > +#define RNG_READY BIT(31)
>
> Keep only one space between define and name
>
> > +
> > +#define RNG_DATA 0x08
> > +
> > +#define to_mtk_rng(p) container_of(p, struct mtk_rng, rng)
> > +
> > +struct mtk_rng {
> > + struct device *dev;
> > + void __iomem *base;
> > + struct clk *clk;
> > + struct hwrng rng;
> > +};
> > +
> > +static int mtk_rng_init(struct hwrng *rng)
> > +{
> > + struct mtk_rng *priv = to_mtk_rng(rng);
> > + u32 val;
> > + int err;
> > +
> > + err = clk_prepare_enable(priv->clk);
> > + if (err)
> > + return err;
> > +
> > + val = readl(priv->base + RNG_CTRL);
> > + val |= RNG_EN;
> > + writel(val, priv->base + RNG_CTRL);
> > +
> > + return 0;
> > +}
> > +
> > +static void mtk_rng_cleanup(struct hwrng *rng)
> > +{
> > + struct mtk_rng *priv = to_mtk_rng(rng);
> > + u32 val;
> > +
> > + val = readl(priv->base + RNG_CTRL);
> > + val &= ~RNG_EN;
> > + writel(val, priv->base + RNG_CTRL);
> > +
> > + clk_disable_unprepare(priv->clk);
> > +}
> > +
> > +static bool mtk_rng_wait_ready(struct hwrng *rng, bool wait)
> > +{
> > + struct mtk_rng *priv = to_mtk_rng(rng);
> > + int ready;
> > +
> > + ready = readl(priv->base + RNG_CTRL) & RNG_READY;
> > + if (!ready && wait)
> > + readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
> > + ready & RNG_READY, USEC_POLL,
> > + TIMEOUT_POLL);
> > + return !!ready;
> > +}
> > +
> > +static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
> > +{
> > + struct mtk_rng *priv = to_mtk_rng(rng);
> > + int retval = 0;
> > +
> > + while (max >= sizeof(u32)) {
> > + if (!mtk_rng_wait_ready(rng, wait))
> > + break;
> > +
> > + *(u32 *)buf = readl(priv->base + RNG_DATA);
> > + retval += sizeof(u32);
> > + buf += sizeof(u32);
> > + max -= sizeof(u32);
> > + }
> > +
> > + if (unlikely(wait && max))
> > + dev_warn(priv->dev, "timeout might be not properly set\n");
> > +
> > + return retval || !wait ? retval : -EIO;
> > +}
> > +
> > +static int mtk_rng_probe(struct platform_device *pdev)
> > +{
> > + struct resource *res;
> > + int ret;
> > + struct mtk_rng *priv;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res) {
> > + dev_err(&pdev->dev, "no iomem resource\n");
> > + return -ENXIO;
> > + }
> > +
> > + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->dev = &pdev->dev;
> > + priv->rng.name = pdev->name;
> > + priv->rng.init = mtk_rng_init;
> > + priv->rng.cleanup = mtk_rng_cleanup;
> > + priv->rng.read = mtk_rng_read;
> > +
> > + priv->clk = devm_clk_get(&pdev->dev, "rng");
> > + if (IS_ERR(priv->clk)) {
> > + ret = PTR_ERR(priv->clk);
> > + dev_err(&pdev->dev, "no clock for device: %d\n", ret);
> > + return ret;
> > + }
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>
> You get that resource twice
>
> Regards
> Corentin Labbe
--
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^ permalink raw reply
* Re: [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for 'reg_1p0d'
From: Shawn Guo @ 2017-04-14 3:28 UTC (permalink / raw)
To: Andrey Smirnov
Cc: yurovsky-Re5JQEeQqe8AvxtiuMwx3w, Sascha Hauer, Fabio Estevam,
Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170413133242.5068-4-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Thu, Apr 13, 2017 at 06:32:37AM -0700, Andrey Smirnov wrote:
> In PMU_REG_1P0Dn ENABLE_LINREG is bit 0. Bit 31 is called OVERRIDE and
> it serves the function of granting permission to GPC IP block to alter
> various bit-fields of the register. The reason why this property, that
> trickeld here from Freescale BSP, is set to 31 is because in the code
> it came from it is used in conjunction with a notifier handler for
> REGULATOR_EVENT_PRE_DO_ENABLE and REGULATOR_EVENT_PRE_DO_DISABLE
> events (not found in upstream kernel) that triggers GPC to start
> manipulating aforementioned other bitfields.
>
> Since:
> a) none of the aforementioned machinery is implemented by
> upstream
> b) using 'anatop-enable-bit' in that capacity is a bit of a
> semantic stretch
>
> simplify the situation by setting the value of 'anatop-enable-bit' to
> point to ENABLE_LINREG (same as i.MX6).
>
> Cc: yurovsky-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
> Cc: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Since patch 1 ~ 3 are all about adding anatop-enable-bit, can we squash
them into one patch?
Shawn
> ---
> arch/arm/boot/dts/imx7s.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
> index 22c9788..8fee299 100644
> --- a/arch/arm/boot/dts/imx7s.dtsi
> +++ b/arch/arm/boot/dts/imx7s.dtsi
> @@ -516,7 +516,7 @@
> anatop-min-bit-val = <8>;
> anatop-min-voltage = <800000>;
> anatop-max-voltage = <1200000>;
> - anatop-enable-bit = <31>;
> + anatop-enable-bit = <0>;
> };
> };
>
> --
> 2.9.3
>
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^ permalink raw reply
* Re: [PATCH v2 07/22] ARM: dts: imx: Add generic compatible string for I2C EEPROM
From: Shawn Guo @ 2017-04-14 3:14 UTC (permalink / raw)
To: Javier Martinez Canillas
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Wolfram Sang, Fabio Estevam,
devicetree-u79uwXL29TY76Z2rM5mHXA, Sascha Hauer, Rob Herring,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
Russell King
In-Reply-To: <20170413182839.25381-8-javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
On Thu, Apr 13, 2017 at 03:28:24PM -0300, Javier Martinez Canillas wrote:
> The at24 driver allows to register I2C EEPROM chips using different vendor
> and devices, but the I2C subsystem does not take the vendor into account
> when matching using the I2C table since it only has device entries.
>
> But when matching using an OF table, both the vendor and device has to be
> taken into account so the driver defines only a set of compatible strings
> using the "atmel" vendor as a generic fallback for compatible I2C devices.
>
> So add this generic fallback to the device node compatible string to make
> the device to match the driver using the OF device ID table.
>
> Signed-off-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
I wouldn't apply it before driver and bindings change get accepted.
Ping me when that happens.
Shawn
> ---
>
> Changes in v2: None
>
> arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi | 2 +-
> arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 2 +-
> arch/arm/boot/dts/imx28-evk.dts | 2 +-
> arch/arm/boot/dts/imx53-tqma53.dtsi | 2 +-
> arch/arm/boot/dts/imx6q-cm-fx6.dts | 2 +-
> arch/arm/boot/dts/imx6q-utilite-pro.dts | 2 +-
> 6 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
> index 4f3e0f473581..61e741092efa 100644
> --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
> +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
> @@ -40,7 +40,7 @@
> status = "okay";
>
> at24@52 {
> - compatible = "at,24c32";
> + compatible = "at,24c32","atmel,24c32";
> pagesize = <32>;
> reg = <0x52>;
> };
> diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
> index 82fec935ce83..5b6b651af18f 100644
> --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
> +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
> @@ -193,7 +193,7 @@
> status = "okay";
>
> at24@52 {
> - compatible = "at,24c32";
> + compatible = "at,24c32","atmel,24c32";
> pagesize = <32>;
> reg = <0x52>;
> };
> diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
> index a5ba669b4eaa..5ab990ac36b4 100644
> --- a/arch/arm/boot/dts/imx28-evk.dts
> +++ b/arch/arm/boot/dts/imx28-evk.dts
> @@ -203,7 +203,7 @@
> };
>
> at24@51 {
> - compatible = "at24,24c32";
> + compatible = "at24,24c32","atmel,24c32";
> pagesize = <32>;
> reg = <0x51>;
> };
> diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
> index 85972f2201c2..c8bc0522a1e9 100644
> --- a/arch/arm/boot/dts/imx53-tqma53.dtsi
> +++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
> @@ -272,7 +272,7 @@
> };
>
> eeprom: 24c64@50 {
> - compatible = "at,24c64";
> + compatible = "at,24c64","atmel,24c64";
> pagesize = <32>;
> reg = <0x50>;
> };
> diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
> index 66cac5328b86..8cf478c67f83 100644
> --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
> +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
> @@ -215,7 +215,7 @@
> clock-frequency = <100000>;
>
> eeprom@50 {
> - compatible = "at24,24c02";
> + compatible = "at24,24c02","atmel,24c02";
> reg = <0x50>;
> pagesize = <16>;
> };
> diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts
> index 69bdd82ce21f..644889d813d0 100644
> --- a/arch/arm/boot/dts/imx6q-utilite-pro.dts
> +++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts
> @@ -128,7 +128,7 @@
> #size-cells = <0>;
>
> eeprom@50 {
> - compatible = "at24,24c02";
> + compatible = "at24,24c02","atmel,24c02";
> reg = <0x50>;
> pagesize = <16>;
> };
> --
> 2.9.3
>
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^ permalink raw reply
* Re: [PATCH 1/3] mfd: cros-ec: Add functions to read mapped memory
From: Guenter Roeck @ 2017-04-14 2:49 UTC (permalink / raw)
To: Moritz Fischer
Cc: Moritz Fischer, linux-hwmon, Linux Kernel Mailing List,
Devicetree List, Lee Jones, olof, jdelvare, Rob Herring,
Mark Rutland
In-Reply-To: <CAJYdmeNXJgzgM3uTi-DjA1B10wSipqSPZ20qhboysqKY_tvVLQ@mail.gmail.com>
On 04/13/2017 03:53 PM, Moritz Fischer wrote:
> Hi Guenter,
>
> On Thu, Apr 13, 2017 at 2:03 PM, Guenter Roeck <linux@roeck-us.net> wrote:
>> On Fri, Apr 07, 2017 at 03:00:08PM -0700, Moritz Fischer wrote:
>>> From: Moritz Fischer <mdf@kernel.org>
>>>
>>> The ChromeOS EC has mapped memory regions where things like temperature
>>> sensors and fan speed are stored. Provide access to those from the
>>> cros-ec mfd device.
>>>
>>
>> Turns out struct cros_ec_device already provides a cmd_readmem callback,
>> which is widely used by other drivers. Why don't you just use it ?
>
> This is only actually set by the lpc version of the cros_ec. I2C and
> SPI connected ECs
Hmm - weird. I thought I saw it implemented for those, but I must have been
struck by lightning or something. Let me check with Gwendal to see how
this (ie its use from iio) is supposed to work on non-LPC systems.
Guenter
> emulate it. I can most certainly hook it up in the (spi,i2c) drivers,
> but the implementation
> for SPI and I2C needs to live somewhere. drivers/platform/chrome/cros_ec_proto.c
> seemed to be a good place.
>
> Thanks for the feedback!
>
> Moritz
> --
> To unsubscribe from this list: send the line "unsubscribe linux-hwmon" in
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> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH v2 15/15] [media] cxd2880 : Update MAINTAINERS file for CXD2880 driver
From: Yasunari.Takiguchi-7U/KSKJipcs @ 2017-04-14 2:48 UTC (permalink / raw)
To: akpm-de/tnXTf+JLsfHDXvbKv3WD2FQJk+8+b,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-media-u79uwXL29TY76Z2rM5mHXA
Cc: tbird20d-Re5JQEeQqe8AvxtiuMwx3w,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, Yasunari Takiguchi,
Masayuki Yamamoto, Hideki Nozawa, Kota Yonezawa,
Toshihiko Matsumoto, Satoshi Watanabe
In-Reply-To: <20170414015043.16731-1-Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
From: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
This is MAINTAINERS file update about the driver for
the Sony CXD2880 DVB-T2/T tuner + demodulator.
Signed-off-by: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Masayuki Yamamoto <Masayuki.Yamamoto-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Hideki Nozawa <Hideki.Nozawa-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Kota Yonezawa <Kota.Yonezawa-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Toshihiko Matsumoto <Toshihiko.Matsumoto-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Satoshi Watanabe <Satoshi.C.Watanabe-7U/KSKJipcs@public.gmane.org>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fdd5350fe261..62543a76d6bf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8042,6 +8042,15 @@ T: git git://linuxtv.org/media_tree.git
S: Supported
F: drivers/media/dvb-frontends/cxd2841er*
+MEDIA DRIVERS FOR CXD2880
+M: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
+L: linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+W: http://linuxtv.org/
+T: git git://linuxtv.org/media_tree.git
+S: Supported
+F: drivers/media/dvb-frontends/cxd2880/*
+F: drivers/media/spi/cxd2880*
+
MEDIA DRIVERS FOR HORUS3A
M: Sergey Kozlov <serjk-SoTE/FI7wRI@public.gmane.org>
M: Abylay Ospan <aospan-SoTE/FI7wRI@public.gmane.org>
--
2.11.0
--
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* [PATCH v2 14/15] [media] cxd2880: Add all Kconfig files for the driver
From: Yasunari.Takiguchi-7U/KSKJipcs @ 2017-04-14 2:47 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-media-u79uwXL29TY76Z2rM5mHXA
Cc: tbird20d-Re5JQEeQqe8AvxtiuMwx3w,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, Yasunari Takiguchi,
Masayuki Yamamoto, Hideki Nozawa, Kota Yonezawa,
Toshihiko Matsumoto, Satoshi Watanabe
In-Reply-To: <20170414015043.16731-1-Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
From: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
This is the Kconfig files of driver for
the Sony CXD2880 DVB-T2/T tuner + demodulator driver.
Signed-off-by: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Masayuki Yamamoto <Masayuki.Yamamoto-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Hideki Nozawa <Hideki.Nozawa-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Kota Yonezawa <Kota.Yonezawa-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Toshihiko Matsumoto <Toshihiko.Matsumoto-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Satoshi Watanabe <Satoshi.C.Watanabe-7U/KSKJipcs@public.gmane.org>
---
drivers/media/dvb-frontends/Kconfig | 2 ++
drivers/media/dvb-frontends/cxd2880/Kconfig | 6 ++++++
drivers/media/spi/Kconfig | 14 ++++++++++++++
3 files changed, 22 insertions(+)
create mode 100644 drivers/media/dvb-frontends/cxd2880/Kconfig
diff --git a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig
index e8c6554a47aa..3a3a7129a150 100644
--- a/drivers/media/dvb-frontends/Kconfig
+++ b/drivers/media/dvb-frontends/Kconfig
@@ -518,6 +518,8 @@ config DVB_GP8PSK_FE
depends on DVB_CORE
default DVB_USB_GP8PSK
+source "drivers/media/dvb-frontends/cxd2880/Kconfig"
+
comment "DVB-C (cable) frontends"
depends on DVB_CORE
diff --git a/drivers/media/dvb-frontends/cxd2880/Kconfig b/drivers/media/dvb-frontends/cxd2880/Kconfig
new file mode 100644
index 000000000000..36b8b6f7c4f7
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/Kconfig
@@ -0,0 +1,6 @@
+config DVB_CXD2880
+ tristate "Sony CXD2880 DVB-T2/T tuner + demodulator"
+ depends on DVB_CORE && SPI
+ default m if !MEDIA_SUBDRV_AUTOSELECT
+ help
+ Say Y when you want to support this frontend.
\ No newline at end of file
diff --git a/drivers/media/spi/Kconfig b/drivers/media/spi/Kconfig
index a21f5a39a440..b07ac86fc53c 100644
--- a/drivers/media/spi/Kconfig
+++ b/drivers/media/spi/Kconfig
@@ -12,3 +12,17 @@ config VIDEO_GS1662
endmenu
endif
+
+if SPI
+menu "Media SPI Adapters"
+
+config CXD2880_SPI_DRV
+ tristate "Sony CXD2880 SPI support"
+ depends on DVB_CORE && SPI
+ default m if !MEDIA_SUBDRV_AUTOSELECT
+ help
+ Choose if you would like to have SPI interface support for Sony CXD2880.
+
+endmenu
+
+endif
--
2.11.0
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^ permalink raw reply related
* [PATCH v2 13/15] [media] cxd2880: Add all Makefile files for the driver
From: Yasunari.Takiguchi-7U/KSKJipcs @ 2017-04-14 2:44 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-media-u79uwXL29TY76Z2rM5mHXA
Cc: tbird20d-Re5JQEeQqe8AvxtiuMwx3w,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, Yasunari Takiguchi,
Masayuki Yamamoto, Hideki Nozawa, Kota Yonezawa,
Toshihiko Matsumoto, Satoshi Watanabe
In-Reply-To: <20170414015043.16731-1-Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
From: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
This is the Makefile files of driver
for the Sony CXD2880 DVB-T2/T tuner + demodulator.
Signed-off-by: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Masayuki Yamamoto <Masayuki.Yamamoto-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Hideki Nozawa <Hideki.Nozawa-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Kota Yonezawa <Kota.Yonezawa-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Toshihiko Matsumoto <Toshihiko.Matsumoto-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Satoshi Watanabe <Satoshi.C.Watanabe-7U/KSKJipcs@public.gmane.org>
---
drivers/media/dvb-frontends/Makefile | 1 +
drivers/media/dvb-frontends/cxd2880/Makefile | 21 +++++++++++++++++++++
drivers/media/spi/Makefile | 5 +++++
3 files changed, 27 insertions(+)
create mode 100644 drivers/media/dvb-frontends/cxd2880/Makefile
diff --git a/drivers/media/dvb-frontends/Makefile b/drivers/media/dvb-frontends/Makefile
index 3fccaf34ef52..d298c7954699 100644
--- a/drivers/media/dvb-frontends/Makefile
+++ b/drivers/media/dvb-frontends/Makefile
@@ -126,3 +126,4 @@ obj-$(CONFIG_DVB_HORUS3A) += horus3a.o
obj-$(CONFIG_DVB_ASCOT2E) += ascot2e.o
obj-$(CONFIG_DVB_HELENE) += helene.o
obj-$(CONFIG_DVB_ZD1301_DEMOD) += zd1301_demod.o
+obj-$(CONFIG_DVB_CXD2880) += cxd2880/
diff --git a/drivers/media/dvb-frontends/cxd2880/Makefile b/drivers/media/dvb-frontends/cxd2880/Makefile
new file mode 100644
index 000000000000..2672c4a3d65c
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/Makefile
@@ -0,0 +1,21 @@
+cxd2880-objs := cxd2880_common.o \
+ cxd2880_devio_spi.o \
+ cxd2880_integ.o \
+ cxd2880_integ_dvbt2.o \
+ cxd2880_integ_dvbt.o \
+ cxd2880_io.o \
+ cxd2880_spi_device.o \
+ cxd2880_stopwatch_port.o \
+ cxd2880_tnrdmd.o \
+ cxd2880_tnrdmd_dvbt2.o \
+ cxd2880_tnrdmd_dvbt2_mon.o \
+ cxd2880_tnrdmd_dvbt.o \
+ cxd2880_tnrdmd_dvbt_mon.o\
+ cxd2880_tnrdmd_mon.o\
+ cxd2880_math.o \
+ cxd2880_top.o
+
+obj-$(CONFIG_DVB_CXD2880) += cxd2880.o
+
+ccflags-y += -Idrivers/media/dvb-core
+ccflags-y += -Idrivers/media/dvb-frontends
diff --git a/drivers/media/spi/Makefile b/drivers/media/spi/Makefile
index ea64013d16cc..40e0f88d9f6c 100644
--- a/drivers/media/spi/Makefile
+++ b/drivers/media/spi/Makefile
@@ -1 +1,6 @@
obj-$(CONFIG_VIDEO_GS1662) += gs1662.o
+obj-$(CONFIG_CXD2880_SPI_DRV) += cxd2880-spi.o
+
+ccflags-y += -Idrivers/media/dvb-core
+ccflags-y += -Idrivers/media/dvb-frontends
+ccflags-y += -Idrivers/media/dvb-frontends/cxd2880
\ No newline at end of file
--
2.11.0
--
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the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related
* Re: [PATCH v2] ARM: dts: imx: ventana: fix DTC warnings
From: Shawn Guo @ 2017-04-14 2:42 UTC (permalink / raw)
To: Tim Harvey
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Sascha Hauer,
Fabio Estevam, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1491857890-10554-1-git-send-email-tharvey-UMMOYl/HMS+akBO8gow8eQ@public.gmane.org>
On Mon, Apr 10, 2017 at 01:58:10PM -0700, Tim Harvey wrote:
> Remove the sky2 ethernet device node from the pcie controller which was
> invalid to begin with.
>
> The original intent was to allow the bootloader to populate the MAC via
> dt but this requires the PCI bus topology to be complete in dt as well
> and as these boards have an expansion connector that topology is dynamic
> and can't be represented here.
>
> Signed-off-by: Tim Harvey <tharvey-UMMOYl/HMS+akBO8gow8eQ@public.gmane.org>
Applied, thanks.
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^ permalink raw reply
* [PATCH v2 12/15] [media] cxd2880: Add DVB-T2 monitor and integration layer functions
From: Yasunari.Takiguchi-7U/KSKJipcs @ 2017-04-14 2:40 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-media-u79uwXL29TY76Z2rM5mHXA
Cc: tbird20d-Re5JQEeQqe8AvxtiuMwx3w,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, Yasunari Takiguchi,
Masayuki Yamamoto, Hideki Nozawa, Kota Yonezawa,
Toshihiko Matsumoto, Satoshi Watanabe
In-Reply-To: <20170414015043.16731-1-Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
From: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
Provide monitor and integration layer functions (DVB-T2)
for the Sony CXD2880 DVB-T2/T tuner + demodulator driver.
Signed-off-by: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Masayuki Yamamoto <Masayuki.Yamamoto-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Hideki Nozawa <Hideki.Nozawa-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Kota Yonezawa <Kota.Yonezawa-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Toshihiko Matsumoto <Toshihiko.Matsumoto-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Satoshi Watanabe <Satoshi.C.Watanabe-7U/KSKJipcs@public.gmane.org>
---
.../dvb-frontends/cxd2880/cxd2880_integ_dvbt2.c | 311 +++
.../dvb-frontends/cxd2880/cxd2880_integ_dvbt2.h | 64 +
.../cxd2880/cxd2880_tnrdmd_dvbt2_mon.c | 2523 ++++++++++++++++++++
.../cxd2880/cxd2880_tnrdmd_dvbt2_mon.h | 170 ++
4 files changed, 3068 insertions(+)
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt2.c
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt2.h
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.h
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt2.c b/drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt2.c
new file mode 100644
index 000000000000..1d60b9c236d8
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt2.c
@@ -0,0 +1,311 @@
+/*
+ * cxd2880_integ_dvbt2.c
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * integration layer functions for DVB-T2
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cxd2880_tnrdmd_dvbt2.h"
+#include "cxd2880_tnrdmd_dvbt2_mon.h"
+#include "cxd2880_integ_dvbt2.h"
+
+static enum cxd2880_ret dvbt2_wait_demod_lock(struct cxd2880_tnrdmd *tnr_dmd,
+ enum cxd2880_dvbt2_profile
+ profile);
+
+static enum cxd2880_ret dvbt2_wait_l1_post_lock(struct cxd2880_tnrdmd *tnr_dmd);
+
+enum cxd2880_ret cxd2880_integ_dvbt2_tune(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt2_tune_param
+ *tune_param)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!tune_param))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if ((tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP) &&
+ (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE))
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ cxd2880_atomic_set(&tnr_dmd->cancel, 0);
+
+ if ((tune_param->bandwidth != CXD2880_DTV_BW_1_7_MHZ) &&
+ (tune_param->bandwidth != CXD2880_DTV_BW_5_MHZ) &&
+ (tune_param->bandwidth != CXD2880_DTV_BW_6_MHZ) &&
+ (tune_param->bandwidth != CXD2880_DTV_BW_7_MHZ) &&
+ (tune_param->bandwidth != CXD2880_DTV_BW_8_MHZ)) {
+ return CXD2880_RESULT_ERROR_NOSUPPORT;
+ }
+
+ if ((tune_param->profile != CXD2880_DVBT2_PROFILE_BASE) &&
+ (tune_param->profile != CXD2880_DVBT2_PROFILE_LITE))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ ret = cxd2880_tnrdmd_dvbt2_tune1(tnr_dmd, tune_param);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ CXD2880_SLEEP(CXD2880_TNRDMD_WAIT_AGC_STABLE);
+
+ ret = cxd2880_tnrdmd_dvbt2_tune2(tnr_dmd, tune_param);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret = dvbt2_wait_demod_lock(tnr_dmd, tune_param->profile);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret = cxd2880_tnrdmd_dvbt2_diver_fef_setting(tnr_dmd);
+ if (ret == CXD2880_RESULT_ERROR_HW_STATE)
+ return CXD2880_RESULT_ERROR_UNLOCK;
+ else if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret = dvbt2_wait_l1_post_lock(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ {
+ u8 plp_not_found;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_data_plp_error(tnr_dmd,
+ &plp_not_found);
+ if (ret == CXD2880_RESULT_ERROR_HW_STATE)
+ return CXD2880_RESULT_ERROR_UNLOCK;
+ else if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (plp_not_found) {
+ ret = CXD2880_RESULT_OK_CONFIRM;
+ tune_param->tune_info =
+ CXD2880_TNRDMD_DVBT2_TUNE_INFO_INVALID_PLP_ID;
+ } else {
+ tune_param->tune_info =
+ CXD2880_TNRDMD_DVBT2_TUNE_INFO_OK;
+ }
+ }
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_integ_dvbt2_wait_ts_lock(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dvbt2_profile
+ profile)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ enum cxd2880_tnrdmd_lock_result lock =
+ CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+ u16 timeout = 0;
+ struct cxd2880_stopwatch timer;
+ u8 continue_wait = 1;
+ u32 elapsed = 0;
+
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = cxd2880_stopwatch_start(&timer);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (profile == CXD2880_DVBT2_PROFILE_BASE)
+ timeout = CXD2880_DVBT2_BASE_WAIT_TS_LOCK;
+ else if (profile == CXD2880_DVBT2_PROFILE_LITE)
+ timeout = CXD2880_DVBT2_LITE_WAIT_TS_LOCK;
+ else
+ return CXD2880_RESULT_ERROR_ARG;
+
+ for (;;) {
+ ret = cxd2880_stopwatch_elapsed(&timer, &elapsed);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (elapsed >= timeout)
+ continue_wait = 0;
+
+ ret = cxd2880_tnrdmd_dvbt2_check_ts_lock(tnr_dmd, &lock);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ switch (lock) {
+ case CXD2880_TNRDMD_LOCK_RESULT_LOCKED:
+ return CXD2880_RESULT_OK;
+
+ case CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED:
+ return CXD2880_RESULT_ERROR_UNLOCK;
+
+ default:
+ break;
+ }
+
+ ret = cxd2880_integ_check_cancellation(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (continue_wait) {
+ ret =
+ cxd2880_stopwatch_sleep(&timer,
+ CXD2880_DVBT2_WAIT_LOCK_INTVL);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ } else {
+ ret = CXD2880_RESULT_ERROR_TIMEOUT;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static enum cxd2880_ret dvbt2_wait_demod_lock(struct cxd2880_tnrdmd *tnr_dmd,
+ enum cxd2880_dvbt2_profile
+ profile)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ enum cxd2880_tnrdmd_lock_result lock =
+ CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+ u16 timeout = 0;
+ struct cxd2880_stopwatch timer;
+ u8 continue_wait = 1;
+ u32 elapsed = 0;
+
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = cxd2880_stopwatch_start(&timer);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (profile == CXD2880_DVBT2_PROFILE_BASE)
+ timeout = CXD2880_DVBT2_BASE_WAIT_DMD_LOCK;
+ else if ((profile == CXD2880_DVBT2_PROFILE_LITE) ||
+ (profile == CXD2880_DVBT2_PROFILE_ANY))
+ timeout = CXD2880_DVBT2_LITE_WAIT_DMD_LOCK;
+ else
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ for (;;) {
+ ret = cxd2880_stopwatch_elapsed(&timer, &elapsed);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (elapsed >= timeout)
+ continue_wait = 0;
+
+ ret = cxd2880_tnrdmd_dvbt2_check_demod_lock(tnr_dmd, &lock);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ switch (lock) {
+ case CXD2880_TNRDMD_LOCK_RESULT_LOCKED:
+ return CXD2880_RESULT_OK;
+
+ case CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED:
+ return CXD2880_RESULT_ERROR_UNLOCK;
+
+ default:
+ break;
+ }
+
+ ret = cxd2880_integ_check_cancellation(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (continue_wait) {
+ ret =
+ cxd2880_stopwatch_sleep(&timer,
+ CXD2880_DVBT2_WAIT_LOCK_INTVL);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ } else {
+ ret = CXD2880_RESULT_ERROR_TIMEOUT;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static enum cxd2880_ret dvbt2_wait_l1_post_lock(struct cxd2880_tnrdmd *tnr_dmd)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ struct cxd2880_stopwatch timer;
+ u8 continue_wait = 1;
+ u32 elapsed = 0;
+ u8 l1_post_valid;
+
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ ret = cxd2880_stopwatch_start(&timer);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ for (;;) {
+ ret = cxd2880_stopwatch_elapsed(&timer, &elapsed);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (elapsed >= CXD2880_DVBT2_L1POST_TIMEOUT)
+ continue_wait = 0;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_check_l1post_valid(tnr_dmd,
+ &l1_post_valid);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (l1_post_valid)
+ return CXD2880_RESULT_OK;
+
+ ret = cxd2880_integ_check_cancellation(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (continue_wait) {
+ ret =
+ cxd2880_stopwatch_sleep(&timer,
+ CXD2880_DVBT2_WAIT_LOCK_INTVL);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ } else {
+ ret = CXD2880_RESULT_ERROR_TIMEOUT;
+ break;
+ }
+ }
+
+ return ret;
+}
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt2.h b/drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt2.h
new file mode 100644
index 000000000000..bc72eb8188f2
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt2.h
@@ -0,0 +1,64 @@
+/*
+ * cxd2880_integ_dvbt2.h
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * integration layer interface for DVB-T2
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CXD2880_INTEG_DVBT2_H
+#define CXD2880_INTEG_DVBT2_H
+
+#include "cxd2880_tnrdmd.h"
+#include "cxd2880_tnrdmd_dvbt2.h"
+#include "cxd2880_integ.h"
+
+#define CXD2880_DVBT2_BASE_WAIT_DMD_LOCK 3500
+#define CXD2880_DVBT2_BASE_WAIT_TS_LOCK 1500
+#define CXD2880_DVBT2_LITE_WAIT_DMD_LOCK 5000
+#define CXD2880_DVBT2_LITE_WAIT_TS_LOCK 2300
+#define CXD2880_DVBT2_WAIT_LOCK_INTVL 10
+#define CXD2880_DVBT2_L1POST_TIMEOUT 500
+
+struct cxd2880_integ_dvbt2_scan_param {
+ u32 start_frequency_khz;
+ u32 end_frequency_khz;
+ u32 step_frequency_khz;
+ enum cxd2880_dtv_bandwidth bandwidth;
+ enum cxd2880_dvbt2_profile t2_profile;
+};
+
+struct cxd2880_integ_dvbt2_scan_result {
+ u32 center_freq_khz;
+ enum cxd2880_ret tune_result;
+ struct cxd2880_dvbt2_tune_param dvbt2_tune_param;
+};
+
+enum cxd2880_ret cxd2880_integ_dvbt2_tune(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt2_tune_param
+ *tune_param);
+
+enum cxd2880_ret cxd2880_integ_dvbt2_wait_ts_lock(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dvbt2_profile
+ profile);
+
+#endif
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c
new file mode 100644
index 000000000000..235db16f4a08
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c
@@ -0,0 +1,2523 @@
+/*
+ * cxd2880_tnrdmd_dvbt2_mon.c
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * DVB-T2 monitor functions
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cxd2880_tnrdmd_mon.h"
+#include "cxd2880_tnrdmd_dvbt2.h"
+#include "cxd2880_tnrdmd_dvbt2_mon.h"
+#include "cxd2880_math.h"
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_sync_stat(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *sync_stat,
+ u8 *ts_lock_stat,
+ u8 *unlock_detected)
+{
+ if ((!tnr_dmd) || (!sync_stat) || (!ts_lock_stat) || (!unlock_detected))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x10, &data,
+ sizeof(data)) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ *sync_stat = data & 0x07;
+ *ts_lock_stat = ((data & 0x20) ? 1 : 0);
+ *unlock_detected = ((data & 0x10) ? 1 : 0);
+ }
+
+ if (*sync_stat == 0x07)
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ u8 *sync_stat,
+ u8 *unlock_detected)
+{
+ u8 ts_lock_stat = 0;
+
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!sync_stat) || (!unlock_detected))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd->diver_sub, sync_stat,
+ &ts_lock_stat, unlock_detected);
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_carrier_offset(struct cxd2880_tnrdmd
+ *tnr_dmd, int *offset)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!offset))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 data[4];
+ u32 ctl_val = 0;
+ u8 sync_state = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
+ &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (sync_state != 6) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x30, data,
+ sizeof(data)) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ ctl_val =
+ ((data[0] & 0x0F) << 24) | (data[1] << 16) | (data[2] << 8)
+ | (data[3]);
+ *offset = cxd2880_convert2s_complement(ctl_val, 28);
+
+ switch (tnr_dmd->bandwidth) {
+ case CXD2880_DTV_BW_1_7_MHZ:
+ *offset = -1 * ((*offset) / 582);
+ break;
+ case CXD2880_DTV_BW_5_MHZ:
+ case CXD2880_DTV_BW_6_MHZ:
+ case CXD2880_DTV_BW_7_MHZ:
+ case CXD2880_DTV_BW_8_MHZ:
+ *offset =
+ -1 * ((*offset) * (u8)tnr_dmd->bandwidth / 940);
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_carrier_offset_sub(struct
+ cxd2880_tnrdmd
+ *tnr_dmd,
+ int *offset)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!offset))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_carrier_offset(tnr_dmd->diver_sub, offset);
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_l1_pre(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt2_l1pre
+ *l1_pre)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!l1_pre))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 data[37];
+ u8 sync_state = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+ u8 version = 0;
+ enum cxd2880_dvbt2_profile profile;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
+ &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return ret;
+ }
+
+ if (sync_state < 5) {
+ if (tnr_dmd->diver_mode ==
+ CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub
+ (tnr_dmd, &sync_state, &unlock_detected);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return ret;
+ }
+
+ if (sync_state < 5) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+ } else {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+ }
+
+ ret = cxd2880_tnrdmd_dvbt2_mon_profile(tnr_dmd, &profile);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return ret;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x61, data,
+ sizeof(data)) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ slvt_unfreeze_reg(tnr_dmd);
+
+ l1_pre->type = (enum cxd2880_dvbt2_l1pre_type)data[0];
+ l1_pre->bw_ext = data[1] & 0x01;
+ l1_pre->s1 = (enum cxd2880_dvbt2_s1)(data[2] & 0x07);
+ l1_pre->s2 = data[3] & 0x0F;
+ l1_pre->l1_rep = data[4] & 0x01;
+ l1_pre->gi = (enum cxd2880_dvbt2_guard)(data[5] & 0x07);
+ l1_pre->papr = (enum cxd2880_dvbt2_papr)(data[6] & 0x0F);
+ l1_pre->mod =
+ (enum cxd2880_dvbt2_l1post_constell)(data[7] & 0x0F);
+ l1_pre->cr = (enum cxd2880_dvbt2_l1post_cr)(data[8] & 0x03);
+ l1_pre->fec =
+ (enum cxd2880_dvbt2_l1post_fec_type)(data[9] & 0x03);
+ l1_pre->l1_post_size = (data[10] & 0x03) << 16;
+ l1_pre->l1_post_size |= (data[11]) << 8;
+ l1_pre->l1_post_size |= (data[12]);
+ l1_pre->l1_post_info_size = (data[13] & 0x03) << 16;
+ l1_pre->l1_post_info_size |= (data[14]) << 8;
+ l1_pre->l1_post_info_size |= (data[15]);
+ l1_pre->pp = (enum cxd2880_dvbt2_pp)(data[16] & 0x0F);
+ l1_pre->tx_id_availability = data[17];
+ l1_pre->cell_id = (data[18] << 8);
+ l1_pre->cell_id |= (data[19]);
+ l1_pre->network_id = (data[20] << 8);
+ l1_pre->network_id |= (data[21]);
+ l1_pre->sys_id = (data[22] << 8);
+ l1_pre->sys_id |= (data[23]);
+ l1_pre->num_frames = data[24];
+ l1_pre->num_symbols = (data[25] & 0x0F) << 8;
+ l1_pre->num_symbols |= data[26];
+ l1_pre->regen = data[27] & 0x07;
+ l1_pre->post_ext = data[28] & 0x01;
+ l1_pre->num_rf_freqs = data[29] & 0x07;
+ l1_pre->rf_idx = data[30] & 0x07;
+ version = (data[31] & 0x03) << 2;
+ version |= (data[32] & 0xC0) >> 6;
+ l1_pre->t2_version = (enum cxd2880_dvbt2_version)version;
+ l1_pre->l1_post_scrambled = (data[32] & 0x20) >> 5;
+ l1_pre->t2_base_lite = (data[32] & 0x10) >> 4;
+ l1_pre->crc32 = (data[33] << 24);
+ l1_pre->crc32 |= (data[34] << 16);
+ l1_pre->crc32 |= (data[35] << 8);
+ l1_pre->crc32 |= data[36];
+
+ if (profile == CXD2880_DVBT2_PROFILE_BASE) {
+ switch ((l1_pre->s2 >> 1)) {
+ case CXD2880_DVBT2_BASE_S2_M1K_G_ANY:
+ l1_pre->fft_mode = CXD2880_DVBT2_M1K;
+ break;
+ case CXD2880_DVBT2_BASE_S2_M2K_G_ANY:
+ l1_pre->fft_mode = CXD2880_DVBT2_M2K;
+ break;
+ case CXD2880_DVBT2_BASE_S2_M4K_G_ANY:
+ l1_pre->fft_mode = CXD2880_DVBT2_M4K;
+ break;
+ case CXD2880_DVBT2_BASE_S2_M8K_G_DVBT:
+ case CXD2880_DVBT2_BASE_S2_M8K_G_DVBT2:
+ l1_pre->fft_mode = CXD2880_DVBT2_M8K;
+ break;
+ case CXD2880_DVBT2_BASE_S2_M16K_G_ANY:
+ l1_pre->fft_mode = CXD2880_DVBT2_M16K;
+ break;
+ case CXD2880_DVBT2_BASE_S2_M32K_G_DVBT:
+ case CXD2880_DVBT2_BASE_S2_M32K_G_DVBT2:
+ l1_pre->fft_mode = CXD2880_DVBT2_M32K;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+ } else if (profile == CXD2880_DVBT2_PROFILE_LITE) {
+ switch ((l1_pre->s2 >> 1)) {
+ case CXD2880_DVBT2_LITE_S2_M2K_G_ANY:
+ l1_pre->fft_mode = CXD2880_DVBT2_M2K;
+ break;
+ case CXD2880_DVBT2_LITE_S2_M4K_G_ANY:
+ l1_pre->fft_mode = CXD2880_DVBT2_M4K;
+ break;
+ case CXD2880_DVBT2_LITE_S2_M8K_G_DVBT:
+ case CXD2880_DVBT2_LITE_S2_M8K_G_DVBT2:
+ l1_pre->fft_mode = CXD2880_DVBT2_M8K;
+ break;
+ case CXD2880_DVBT2_LITE_S2_M16K_G_DVBT:
+ case CXD2880_DVBT2_LITE_S2_M16K_G_DVBT2:
+ l1_pre->fft_mode = CXD2880_DVBT2_M16K;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+ } else {
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ l1_pre->mixed = l1_pre->s2 & 0x01;
+ }
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_version(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dvbt2_version
+ *ver)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ u8 version = 0;
+
+ if ((!tnr_dmd) || (!ver))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 data[2];
+ u8 sync_state = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
+ &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (sync_state < 5) {
+ if (tnr_dmd->diver_mode ==
+ CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub
+ (tnr_dmd, &sync_state, &unlock_detected);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return ret;
+ }
+
+ if (sync_state < 5) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+ } else {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x80, data,
+ sizeof(data)) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ version = ((data[0] & 0x03) << 2);
+ version |= ((data[1] & 0xC0) >> 6);
+ *ver = (enum cxd2880_dvbt2_version)version;
+ }
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_ofdm(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt2_ofdm *ofdm)
+{
+ if ((!tnr_dmd) || (!ofdm))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 data[5];
+ u8 sync_state = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
+ &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (sync_state != 6) {
+ slvt_unfreeze_reg(tnr_dmd);
+
+ ret = CXD2880_RESULT_ERROR_HW_STATE;
+
+ if (tnr_dmd->diver_mode ==
+ CXD2880_TNRDMD_DIVERMODE_MAIN)
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_ofdm(
+ tnr_dmd->diver_sub, ofdm);
+
+ return ret;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x1D, data,
+ sizeof(data)) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ ofdm->mixed = ((data[0] & 0x20) ? 1 : 0);
+ ofdm->is_miso = ((data[0] & 0x10) >> 4);
+ ofdm->mode = (enum cxd2880_dvbt2_mode)(data[0] & 0x07);
+ ofdm->gi = (enum cxd2880_dvbt2_guard)((data[1] & 0x70) >> 4);
+ ofdm->pp = (enum cxd2880_dvbt2_pp)(data[1] & 0x07);
+ ofdm->bw_ext = (data[2] & 0x10) >> 4;
+ ofdm->papr = (enum cxd2880_dvbt2_papr)(data[2] & 0x0F);
+ ofdm->num_symbols = (data[3] << 8) | data[4];
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_data_plps(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *plp_ids,
+ u8 *num_plps)
+{
+ if ((!tnr_dmd) || (!num_plps))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 l1_post_ok = 0;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x86,
+ &l1_post_ok,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (!(l1_post_ok & 0x01)) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xC1, num_plps,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (*num_plps == 0) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_OTHER;
+ }
+
+ if (!plp_ids) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_OK;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xC2, plp_ids,
+ ((*num_plps >
+ 62) ? 62 : *num_plps)) !=
+ CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (*num_plps > 62) {
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0C) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x10,
+ plp_ids + 62,
+ *num_plps - 62) !=
+ CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+ }
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_active_plp(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_dvbt2_plp_btype
+ type,
+ struct cxd2880_dvbt2_plp
+ *plp_info)
+{
+ if ((!tnr_dmd) || (!plp_info))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 data[20];
+ u8 addr = 0;
+ u8 index = 0;
+ u8 l1_post_ok = 0;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x86,
+ &l1_post_ok,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (!l1_post_ok) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (type == CXD2880_DVBT2_PLP_COMMON)
+ addr = 0xA9;
+ else
+ addr = 0x96;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, addr, data,
+ sizeof(data)) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ if ((type == CXD2880_DVBT2_PLP_COMMON) && (data[13] == 0))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ plp_info->id = data[index++];
+ plp_info->type =
+ (enum cxd2880_dvbt2_plp_type)(data[index++] & 0x07);
+ plp_info->payload =
+ (enum cxd2880_dvbt2_plp_payload)(data[index++] & 0x1F);
+ plp_info->ff = data[index++] & 0x01;
+ plp_info->first_rf_idx = data[index++] & 0x07;
+ plp_info->first_frm_idx = data[index++];
+ plp_info->group_id = data[index++];
+ plp_info->plp_cr =
+ (enum cxd2880_dvbt2_plp_code_rate)(data[index++] & 0x07);
+ plp_info->constell =
+ (enum cxd2880_dvbt2_plp_constell)(data[index++] & 0x07);
+ plp_info->rot = data[index++] & 0x01;
+ plp_info->fec =
+ (enum cxd2880_dvbt2_plp_fec)(data[index++] & 0x03);
+ plp_info->num_blocks_max = (u16)((data[index++] & 0x03)) << 8;
+ plp_info->num_blocks_max |= data[index++];
+ plp_info->frm_int = data[index++];
+ plp_info->til_len = data[index++];
+ plp_info->til_type = data[index++] & 0x01;
+
+ plp_info->in_band_a_flag = data[index++] & 0x01;
+ plp_info->rsvd = data[index++] << 8;
+ plp_info->rsvd |= data[index++];
+
+ plp_info->in_band_b_flag =
+ (u8)((plp_info->rsvd & 0x8000) >> 15);
+ plp_info->plp_mode =
+ (enum cxd2880_dvbt2_plp_mode)((plp_info->rsvd & 0x000C) >>
+ 2);
+ plp_info->static_flag = (u8)((plp_info->rsvd & 0x0002) >> 1);
+ plp_info->static_padding_flag = (u8)(plp_info->rsvd & 0x0001);
+ plp_info->rsvd = (u16)((plp_info->rsvd & 0x7FF0) >> 4);
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_data_plp_error(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ u8 *plp_error)
+{
+ if ((!tnr_dmd) || (!plp_error))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x86, &data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if ((data & 0x01) == 0x00) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xC0, &data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ *plp_error = data & 0x01;
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_l1_change(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *l1_change)
+{
+ if ((!tnr_dmd) || (!l1_change))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 data;
+ u8 sync_state = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
+ &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (sync_state < 5) {
+ if (tnr_dmd->diver_mode ==
+ CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub
+ (tnr_dmd, &sync_state, &unlock_detected);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return ret;
+ }
+
+ if (sync_state < 5) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+ } else {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x5F, &data,
+ sizeof(data)) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ *l1_change = data & 0x01;
+ if (*l1_change) {
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x22) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x16,
+ 0x01) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ }
+ slvt_unfreeze_reg(tnr_dmd);
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_l1_post(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ struct cxd2880_dvbt2_l1post
+ *l1_post)
+{
+ if ((!tnr_dmd) || (!l1_post))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 data[16];
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x86, data,
+ sizeof(data)) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (!(data[0] & 0x01))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ l1_post->sub_slices_per_frame = (data[1] & 0x7F) << 8;
+ l1_post->sub_slices_per_frame |= data[2];
+ l1_post->num_plps = data[3];
+ l1_post->num_aux = data[4] & 0x0F;
+ l1_post->aux_cfg_rfu = data[5];
+ l1_post->rf_idx = data[6] & 0x07;
+ l1_post->freq = data[7] << 24;
+ l1_post->freq |= data[8] << 16;
+ l1_post->freq |= data[9] << 8;
+ l1_post->freq |= data[10];
+ l1_post->fef_type = data[11] & 0x0F;
+ l1_post->fef_length = data[12] << 16;
+ l1_post->fef_length |= data[13] << 8;
+ l1_post->fef_length |= data[14];
+ l1_post->fef_intvl = data[15];
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_bbheader(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dvbt2_plp_btype
+ type,
+ struct cxd2880_dvbt2_bbheader
+ *bbheader)
+{
+ if ((!tnr_dmd) || (!bbheader))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ u8 sync_state = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
+ &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return ret;
+ }
+
+ if (!ts_lock) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (type == CXD2880_DVBT2_PLP_COMMON) {
+ u8 l1_post_ok;
+ u8 data;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x86,
+ &l1_post_ok,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (!(l1_post_ok & 0x01)) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xB6, &data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (data == 0) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+ }
+
+ {
+ u8 data[14];
+ u8 addr = 0;
+
+ if (type == CXD2880_DVBT2_PLP_COMMON)
+ addr = 0x51;
+ else
+ addr = 0x42;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, addr, data,
+ sizeof(data)) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ bbheader->stream_input =
+ (enum cxd2880_dvbt2_stream)((data[0] >> 6) & 0x03);
+ bbheader->is_single_input_stream = (u8)((data[0] >> 5) & 0x01);
+ bbheader->is_constant_coding_modulation =
+ (u8)((data[0] >> 4) & 0x01);
+ bbheader->issy_indicator = (u8)((data[0] >> 3) & 0x01);
+ bbheader->null_packet_deletion = (u8)((data[0] >> 2) & 0x01);
+ bbheader->ext = (u8)(data[0] & 0x03);
+
+ bbheader->input_stream_identifier = data[1];
+ bbheader->plp_mode =
+ (data[3] & 0x01) ? CXD2880_DVBT2_PLP_MODE_HEM :
+ CXD2880_DVBT2_PLP_MODE_NM;
+ bbheader->data_field_length = (u16)((data[4] << 8) | data[5]);
+
+ if (bbheader->plp_mode == CXD2880_DVBT2_PLP_MODE_NM) {
+ bbheader->user_packet_length =
+ (u16)((data[6] << 8) | data[7]);
+ bbheader->sync_byte = data[8];
+ bbheader->issy = 0;
+ } else {
+ bbheader->user_packet_length = 0;
+ bbheader->sync_byte = 0;
+ bbheader->issy =
+ (u32)((data[11] << 16) | (data[12] << 8) |
+ data[13]);
+ }
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_in_bandb_ts_rate(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_dvbt2_plp_btype
+ type,
+ u32 *ts_rate_bps)
+{
+ if ((!tnr_dmd) || (!ts_rate_bps))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ u8 sync_state = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
+ &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return ret;
+ }
+
+ if (!ts_lock) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 l1_post_ok = 0;
+ u8 addr = 0;
+ u8 data = 0;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x86,
+ &l1_post_ok,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (!(l1_post_ok & 0x01)) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (type == CXD2880_DVBT2_PLP_COMMON)
+ addr = 0xBA;
+ else
+ addr = 0xA7;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, addr, &data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if ((data & 0x80) == 0x00) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x25) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data[4];
+ u8 addr = 0;
+
+ if (type == CXD2880_DVBT2_PLP_COMMON)
+ addr = 0xA6;
+ else
+ addr = 0xAA;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, addr, &data[0],
+ 4) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ *ts_rate_bps =
+ (u32)(((data[0] & 0x07) << 24) | (data[1] << 16) |
+ (data[2] << 8) | data[3]);
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_spectrum_sense(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_tnrdmd_spectrum_sense
+ *sense)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ u8 sync_state = 0;
+ u8 ts_lock = 0;
+ u8 early_unlock = 0;
+
+ if ((!tnr_dmd) || (!sense))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state, &ts_lock,
+ &early_unlock);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return ret;
+ }
+
+ if (sync_state != 6) {
+ slvt_unfreeze_reg(tnr_dmd);
+
+ ret = CXD2880_RESULT_ERROR_HW_STATE;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_spectrum_sense(
+ tnr_dmd->diver_sub, sense);
+
+ return ret;
+ }
+
+ {
+ u8 data = 0;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x2F, &data,
+ sizeof(data)) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ *sense =
+ (data & 0x01) ? CXD2880_TNRDMD_SPECTRUM_INV :
+ CXD2880_TNRDMD_SPECTRUM_NORMAL;
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+static enum cxd2880_ret dvbt2_read_snr_reg(struct cxd2880_tnrdmd *tnr_dmd,
+ u16 *reg_value)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!reg_value))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ {
+ u8 sync_state = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+ u8 data[2];
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
+ &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (sync_state != 6) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x13, data,
+ sizeof(data)) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ *reg_value = (data[0] << 8) | data[1];
+ }
+
+ return ret;
+}
+
+static enum cxd2880_ret dvbt2_calc_snr(struct cxd2880_tnrdmd *tnr_dmd,
+ u32 reg_value, int *snr)
+{
+ if ((!tnr_dmd) || (!snr))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (reg_value == 0)
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ if (reg_value > 10876)
+ reg_value = 10876;
+
+ *snr =
+ 10 * 10 * ((int)cxd2880_math_log10(reg_value) -
+ (int)cxd2880_math_log10(12600 - reg_value));
+ *snr += 32000;
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_snr(struct cxd2880_tnrdmd *tnr_dmd,
+ int *snr)
+{
+ u16 reg_value = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!snr))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ *snr = -1000 * 1000;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
+ ret = dvbt2_read_snr_reg(tnr_dmd, ®_value);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret = dvbt2_calc_snr(tnr_dmd, reg_value, snr);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ } else {
+ int snr_main = 0;
+ int snr_sub = 0;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_snr_diver(tnr_dmd, snr, &snr_main,
+ &snr_sub);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ }
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_snr_diver(struct cxd2880_tnrdmd
+ *tnr_dmd, int *snr,
+ int *snr_main, int *snr_sub)
+{
+ u16 reg_value = 0;
+ u32 reg_value_sum = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!snr) || (!snr_main) || (!snr_sub))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ *snr = -1000 * 1000;
+ *snr_main = -1000 * 1000;
+ *snr_sub = -1000 * 1000;
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = dvbt2_read_snr_reg(tnr_dmd, ®_value);
+ if (ret == CXD2880_RESULT_OK) {
+ ret = dvbt2_calc_snr(tnr_dmd, reg_value, snr_main);
+ if (ret != CXD2880_RESULT_OK)
+ reg_value = 0;
+ } else if (ret == CXD2880_RESULT_ERROR_HW_STATE) {
+ reg_value = 0;
+ } else {
+ return ret;
+ }
+
+ reg_value_sum += reg_value;
+
+ ret = dvbt2_read_snr_reg(tnr_dmd->diver_sub, ®_value);
+ if (ret == CXD2880_RESULT_OK) {
+ ret = dvbt2_calc_snr(tnr_dmd->diver_sub, reg_value, snr_sub);
+ if (ret != CXD2880_RESULT_OK)
+ reg_value = 0;
+ } else if (ret == CXD2880_RESULT_ERROR_HW_STATE) {
+ reg_value = 0;
+ } else {
+ return ret;
+ }
+
+ reg_value_sum += reg_value;
+
+ ret = dvbt2_calc_snr(tnr_dmd, reg_value_sum, snr);
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_pre_ldpcber(struct cxd2880_tnrdmd
+ *tnr_dmd, u32 *ber)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ u32 bit_error = 0;
+ u32 period_exp = 0;
+ u32 n_ldpc = 0;
+
+ if ((!tnr_dmd) || (!ber))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data[5];
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x3C, data,
+ sizeof(data)) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (!(data[0] & 0x01)) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ bit_error =
+ ((data[1] & 0x0F) << 24) | (data[2] << 16) | (data[3] << 8)
+ | data[4];
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xA0, data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (((enum cxd2880_dvbt2_plp_fec)(data[0] & 0x03)) ==
+ CXD2880_DVBT2_FEC_LDPC_16K)
+ n_ldpc = 16200;
+ else
+ n_ldpc = 64800;
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x20) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x6F, data,
+ 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ period_exp = data[0] & 0x0F;
+ }
+
+ if (bit_error > ((1U << period_exp) * n_ldpc))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ {
+ u32 div = 0;
+ u32 Q = 0;
+ u32 R = 0;
+
+ if (period_exp >= 4) {
+ div = (1U << (period_exp - 4)) * (n_ldpc / 200);
+
+ Q = (bit_error * 5) / div;
+ R = (bit_error * 5) % div;
+
+ R *= 625;
+ Q = Q * 625 + R / div;
+ R = R % div;
+ } else {
+ div = (1U << period_exp) * (n_ldpc / 200);
+
+ Q = (bit_error * 10) / div;
+ R = (bit_error * 10) % div;
+
+ R *= 5000;
+ Q = Q * 5000 + R / div;
+ R = R % div;
+ }
+
+ if (div / 2 <= R)
+ *ber = Q + 1;
+ else
+ *ber = Q;
+ }
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_post_bchfer(struct cxd2880_tnrdmd
+ *tnr_dmd, u32 *fer)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ u32 fec_error = 0;
+ u32 period = 0;
+
+ if ((!tnr_dmd) || (!fer))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data[2];
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x1B, data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (!(data[0] & 0x80))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ fec_error = ((data[0] & 0x7F) << 8) | (data[1]);
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x20) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x72, data,
+ 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ period = (1 << (data[0] & 0x0F));
+ }
+
+ if ((period == 0) || (fec_error > period))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ {
+ u32 div = 0;
+ u32 Q = 0;
+ u32 R = 0;
+
+ div = period;
+
+ Q = (fec_error * 1000) / div;
+ R = (fec_error * 1000) % div;
+
+ R *= 1000;
+ Q = Q * 1000 + R / div;
+ R = R % div;
+
+ if ((div != 1) && (div / 2 <= R))
+ *fer = Q + 1;
+ else
+ *fer = Q;
+ }
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_pre_bchber(struct cxd2880_tnrdmd
+ *tnr_dmd, u32 *ber)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ u32 bit_error = 0;
+ u32 period_exp = 0;
+ u32 n_bch = 0;
+
+ if ((!tnr_dmd) || (!ber))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 data[3];
+ enum cxd2880_dvbt2_plp_fec plp_fec_type =
+ CXD2880_DVBT2_FEC_LDPC_16K;
+ enum cxd2880_dvbt2_plp_code_rate plp_cr = CXD2880_DVBT2_R1_2;
+
+ static const u16 n_bch_bits_lookup[2][8] = {
+ {7200, 9720, 10800, 11880, 12600, 13320, 5400, 6480},
+ {32400, 38880, 43200, 48600, 51840, 54000, 21600, 25920}
+ };
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x15, data,
+ 3) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (!(data[0] & 0x40)) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ bit_error = ((data[0] & 0x3F) << 16) | (data[1] << 8) | data[2];
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x9D, data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ plp_cr = (enum cxd2880_dvbt2_plp_code_rate)(data[0] & 0x07);
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xA0, data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ plp_fec_type = (enum cxd2880_dvbt2_plp_fec)(data[0] & 0x03);
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x20) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x72, data,
+ 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ period_exp = data[0] & 0x0F;
+
+ if ((plp_fec_type > CXD2880_DVBT2_FEC_LDPC_64K) ||
+ (plp_cr > CXD2880_DVBT2_R2_5))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ n_bch = n_bch_bits_lookup[plp_fec_type][plp_cr];
+ }
+
+ if (bit_error > ((1U << period_exp) * n_bch))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ {
+ u32 div = 0;
+ u32 Q = 0;
+ u32 R = 0;
+
+ if (period_exp >= 6) {
+ div = (1U << (period_exp - 6)) * (n_bch / 40);
+
+ Q = (bit_error * 625) / div;
+ R = (bit_error * 625) % div;
+
+ R *= 625;
+ Q = Q * 625 + R / div;
+ R = R % div;
+ } else {
+ div = (1U << period_exp) * (n_bch / 40);
+
+ Q = (bit_error * 1000) / div;
+ R = (bit_error * 1000) % div;
+
+ R *= 25000;
+ Q = Q * 25000 + R / div;
+ R = R % div;
+ }
+
+ if (div / 2 <= R)
+ *ber = Q + 1;
+ else
+ *ber = Q;
+ }
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_packet_error_number(struct
+ cxd2880_tnrdmd
+ *tnr_dmd,
+ u32 *pen)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ u8 data[3];
+
+ if ((!tnr_dmd) || (!pen))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x39, data,
+ sizeof(data)) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (!(data[0] & 0x01))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ *pen = ((data[1] << 8) | data[2]);
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_sampling_offset(struct cxd2880_tnrdmd
+ *tnr_dmd, int *ppm)
+{
+ if ((!tnr_dmd) || (!ppm))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 ctl_val_reg[5];
+ u8 nominal_rate_reg[5];
+ u32 trl_ctl_val = 0;
+ u32 trcg_nominal_rate = 0;
+ int num;
+ int den;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ u8 sync_state = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+ s8 diff_upper = 0;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
+ &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (sync_state != 6) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x34,
+ ctl_val_reg,
+ sizeof(ctl_val_reg)) !=
+ CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x04) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x10,
+ nominal_rate_reg,
+ sizeof(nominal_rate_reg)) !=
+ CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ diff_upper =
+ (ctl_val_reg[0] & 0x7F) - (nominal_rate_reg[0] & 0x7F);
+
+ if ((diff_upper < -1) || (diff_upper > 1))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ trl_ctl_val = ctl_val_reg[1] << 24;
+ trl_ctl_val |= ctl_val_reg[2] << 16;
+ trl_ctl_val |= ctl_val_reg[3] << 8;
+ trl_ctl_val |= ctl_val_reg[4];
+
+ trcg_nominal_rate = nominal_rate_reg[1] << 24;
+ trcg_nominal_rate |= nominal_rate_reg[2] << 16;
+ trcg_nominal_rate |= nominal_rate_reg[3] << 8;
+ trcg_nominal_rate |= nominal_rate_reg[4];
+
+ trl_ctl_val >>= 1;
+ trcg_nominal_rate >>= 1;
+
+ if (diff_upper == 1)
+ num =
+ (int)((trl_ctl_val + 0x80000000u) -
+ trcg_nominal_rate);
+ else if (diff_upper == -1)
+ num =
+ -(int)((trcg_nominal_rate + 0x80000000u) -
+ trl_ctl_val);
+ else
+ num = (int)(trl_ctl_val - trcg_nominal_rate);
+
+ den = (nominal_rate_reg[0] & 0x7F) << 24;
+ den |= nominal_rate_reg[1] << 16;
+ den |= nominal_rate_reg[2] << 8;
+ den |= nominal_rate_reg[3];
+ den = (den + (390625 / 2)) / 390625;
+
+ den >>= 1;
+
+ if (num >= 0)
+ *ppm = (num + (den / 2)) / den;
+ else
+ *ppm = (num - (den / 2)) / den;
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_sampling_offset_sub(struct
+ cxd2880_tnrdmd
+ *tnr_dmd,
+ int *ppm)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!ppm))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ ret = cxd2880_tnrdmd_dvbt2_mon_sampling_offset(tnr_dmd->diver_sub, ppm);
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_quality(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *quality)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ int snr = 0;
+ int snr_rel = 0;
+ u32 ber = 0;
+ u32 ber_sqi = 0;
+ enum cxd2880_dvbt2_plp_constell qam;
+ enum cxd2880_dvbt2_plp_code_rate code_rate;
+
+ static const int snr_nordig_p1_db_1000[4][8] = {
+ {3500, 4700, 5600, 6600, 7200, 7700, 1300, 2200},
+ {8700, 10100, 11400, 12500, 13300, 13800, 6000, 7200},
+ {13000, 14800, 16200, 17700, 18700, 19400, 9800, 11100},
+ {17000, 19400, 20800, 22900, 24300, 25100, 13200, 14800},
+ };
+
+ if ((!tnr_dmd) || (!quality))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = cxd2880_tnrdmd_dvbt2_mon_pre_bchber(tnr_dmd, &ber);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret = cxd2880_tnrdmd_dvbt2_mon_snr(tnr_dmd, &snr);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_qam(tnr_dmd, CXD2880_DVBT2_PLP_DATA, &qam);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_code_rate(tnr_dmd, CXD2880_DVBT2_PLP_DATA,
+ &code_rate);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if ((code_rate > CXD2880_DVBT2_R2_5) || (qam > CXD2880_DVBT2_QAM256))
+ return CXD2880_RESULT_ERROR_OTHER;
+
+ if (ber > 100000)
+ ber_sqi = 0;
+ else if (ber >= 100)
+ ber_sqi = 6667;
+ else
+ ber_sqi = 16667;
+
+ snr_rel = snr - snr_nordig_p1_db_1000[qam][code_rate];
+
+ if (snr_rel < -3000) {
+ *quality = 0;
+ } else if (snr_rel <= 3000) {
+ u32 temp_sqi =
+ (((snr_rel + 3000) * ber_sqi) + 500000) / 1000000;
+ *quality = (temp_sqi > 100) ? 100 : (u8)temp_sqi;
+ } else {
+ *quality = 100;
+ }
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_ts_rate(struct cxd2880_tnrdmd
+ *tnr_dmd, u32 *ts_rate_kbps)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ u32 rd_smooth_dp = 0;
+ u32 ep_ck_nume = 0;
+ u32 ep_ck_deno = 0;
+ u8 issy_on_data = 0;
+
+ if ((!tnr_dmd) || (!ts_rate_kbps))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 data[12];
+ u8 sync_state = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_state,
+ &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (!ts_lock) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x23, data,
+ 12) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ rd_smooth_dp = (u32)((data[0] & 0x1F) << 24);
+ rd_smooth_dp |= (u32)(data[1] << 16);
+ rd_smooth_dp |= (u32)(data[2] << 8);
+ rd_smooth_dp |= (u32)data[3];
+
+ if (rd_smooth_dp < 214958) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ ep_ck_nume = (u32)((data[4] & 0x3F) << 24);
+ ep_ck_nume |= (u32)(data[5] << 16);
+ ep_ck_nume |= (u32)(data[6] << 8);
+ ep_ck_nume |= (u32)data[7];
+
+ ep_ck_deno = (u32)((data[8] & 0x3F) << 24);
+ ep_ck_deno |= (u32)(data[9] << 16);
+ ep_ck_deno |= (u32)(data[10] << 8);
+ ep_ck_deno |= (u32)data[11];
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x41, data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ issy_on_data = data[0] & 0x01;
+
+ slvt_unfreeze_reg(tnr_dmd);
+ }
+
+ if (issy_on_data) {
+ if ((ep_ck_deno == 0) || (ep_ck_nume == 0) ||
+ (ep_ck_deno >= ep_ck_nume))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ {
+ u32 ick_x100;
+ u32 div = 0;
+ u32 Q = 0;
+ u32 R = 0;
+
+ switch (tnr_dmd->clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ ick_x100 = 8228;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ ick_x100 = 9330;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ ick_x100 = 9600;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ div = rd_smooth_dp;
+
+ Q = ick_x100 * 262144U / div;
+ R = ick_x100 * 262144U % div;
+
+ R *= 5U;
+ Q = Q * 5 + R / div;
+ R = R % div;
+
+ R *= 2U;
+ Q = Q * 2 + R / div;
+ R = R % div;
+
+ if (div / 2 <= R)
+ *ts_rate_kbps = Q + 1;
+ else
+ *ts_rate_kbps = Q;
+ }
+
+ if (issy_on_data) {
+ u32 diff = ep_ck_nume - ep_ck_deno;
+
+ while (diff > 0x7FFF) {
+ diff >>= 1;
+ ep_ck_nume >>= 1;
+ }
+
+ *ts_rate_kbps -=
+ (*ts_rate_kbps * diff + ep_ck_nume / 2) / ep_ck_nume;
+ }
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_per(struct cxd2880_tnrdmd *tnr_dmd,
+ u32 *per)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ u32 packet_error = 0;
+ u32 period = 0;
+
+ if (!tnr_dmd || !per)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 rdata[3];
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x18, rdata,
+ 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if ((rdata[0] & 0x01) == 0)
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ packet_error = (rdata[1] << 8) | rdata[2];
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x24) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xDC, rdata,
+ 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ period = 1U << (rdata[0] & 0x0F);
+ }
+
+ if ((period == 0) || (packet_error > period))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ {
+ u32 div = 0;
+ u32 Q = 0;
+ u32 R = 0;
+
+ div = period;
+
+ Q = (packet_error * 1000) / div;
+ R = (packet_error * 1000) % div;
+
+ R *= 1000;
+ Q = Q * 1000 + R / div;
+ R = R % div;
+
+ if ((div != 1) && (div / 2 <= R))
+ *per = Q + 1;
+ else
+ *per = Q;
+ }
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_qam(struct cxd2880_tnrdmd *tnr_dmd,
+ enum cxd2880_dvbt2_plp_btype type,
+ enum cxd2880_dvbt2_plp_constell
+ *qam)
+{
+ u8 data;
+ u8 l1_post_ok = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!qam))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x86, &l1_post_ok,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (!(l1_post_ok & 0x01)) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (type == CXD2880_DVBT2_PLP_COMMON) {
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xB6, &data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (data == 0) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xB1, &data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ } else {
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x9E, &data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ *qam = (enum cxd2880_dvbt2_plp_constell)(data & 0x07);
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_code_rate(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dvbt2_plp_btype
+ type,
+ enum
+ cxd2880_dvbt2_plp_code_rate
+ *code_rate)
+{
+ u8 data;
+ u8 l1_post_ok = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!code_rate))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x86, &l1_post_ok,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (!(l1_post_ok & 0x01)) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (type == CXD2880_DVBT2_PLP_COMMON) {
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xB6, &data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (data == 0) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xB0, &data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ } else {
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x9D, &data,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ *code_rate = (enum cxd2880_dvbt2_plp_code_rate)(data & 0x07);
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_profile(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dvbt2_profile
+ *profile)
+{
+ if ((!tnr_dmd) || (!profile))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x22, &data,
+ sizeof(data)) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (data & 0x02) {
+ if (data & 0x01)
+ *profile = CXD2880_DVBT2_PROFILE_LITE;
+ else
+ *profile = CXD2880_DVBT2_PROFILE_BASE;
+ } else {
+ enum cxd2880_ret ret = CXD2880_RESULT_ERROR_HW_STATE;
+
+ if (tnr_dmd->diver_mode ==
+ CXD2880_TNRDMD_DIVERMODE_MAIN)
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_profile(
+ tnr_dmd->diver_sub, profile);
+
+ return ret;
+ }
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+static enum cxd2880_ret dvbt2_calc_sdi(struct cxd2880_tnrdmd *tnr_dmd,
+ int rf_lvl, u8 *ssi)
+{
+ enum cxd2880_dvbt2_plp_constell qam;
+ enum cxd2880_dvbt2_plp_code_rate code_rate;
+ int prel;
+ int temp_ssi = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ static const int ref_dbm_1000[4][8] = {
+ {-96000, -95000, -94000, -93000, -92000, -92000, -98000,
+ -97000},
+ {-91000, -89000, -88000, -87000, -86000, -86000, -93000,
+ -92000},
+ {-86000, -85000, -83000, -82000, -81000, -80000, -89000,
+ -88000},
+ {-82000, -80000, -78000, -76000, -75000, -74000, -86000,
+ -84000},
+ };
+
+ if ((!tnr_dmd) || (!ssi))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_qam(tnr_dmd, CXD2880_DVBT2_PLP_DATA, &qam);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_code_rate(tnr_dmd, CXD2880_DVBT2_PLP_DATA,
+ &code_rate);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if ((code_rate > CXD2880_DVBT2_R2_5) || (qam > CXD2880_DVBT2_QAM256))
+ return CXD2880_RESULT_ERROR_OTHER;
+
+ prel = rf_lvl - ref_dbm_1000[qam][code_rate];
+
+ if (prel < -15000)
+ temp_ssi = 0;
+ else if (prel < 0)
+ temp_ssi = ((2 * (prel + 15000)) + 1500) / 3000;
+ else if (prel < 20000)
+ temp_ssi = (((4 * prel) + 500) / 1000) + 10;
+ else if (prel < 35000)
+ temp_ssi = (((2 * (prel - 20000)) + 1500) / 3000) + 90;
+ else
+ temp_ssi = 100;
+
+ *ssi = (temp_ssi > 100) ? 100 : (u8)temp_ssi;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_ssi(struct cxd2880_tnrdmd *tnr_dmd,
+ u8 *ssi)
+{
+ int rf_lvl = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!ssi))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = cxd2880_tnrdmd_mon_rf_lvl(tnr_dmd, &rf_lvl);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret = dvbt2_calc_sdi(tnr_dmd, rf_lvl, ssi);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_ssi_sub(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *ssi)
+{
+ int rf_lvl = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!ssi))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = cxd2880_tnrdmd_mon_rf_lvl(tnr_dmd->diver_sub, &rf_lvl);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret = dvbt2_calc_sdi(tnr_dmd, rf_lvl, ssi);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ return ret;
+}
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.h b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.h
new file mode 100644
index 000000000000..784ad2844d1b
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.h
@@ -0,0 +1,170 @@
+/*
+ * cxd2880_tnrdmd_dvbt2_mon.h
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * DVB-T2 monitor interface
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CXD2880_TNRDMD_DVBT2_MON_H
+#define CXD2880_TNRDMD_DVBT2_MON_H
+
+#include "cxd2880_tnrdmd.h"
+#include "cxd2880_dvbt2.h"
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_sync_stat(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *sync_stat,
+ u8 *ts_lock_stat,
+ u8 *unlock_detected);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ u8 *sync_stat,
+ u8 *unlock_detected);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_carrier_offset(struct cxd2880_tnrdmd
+ *tnr_dmd, int *offset);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_carrier_offset_sub(struct
+ cxd2880_tnrdmd
+ *tnr_dmd,
+ int *offset);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_l1_pre(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt2_l1pre
+ *l1_pre);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_version(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dvbt2_version
+ *ver);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_ofdm(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt2_ofdm *ofdm);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_data_plps(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *plp_ids,
+ u8 *num_plps);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_active_plp(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_dvbt2_plp_btype
+ type,
+ struct cxd2880_dvbt2_plp
+ *plp_info);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_data_plp_error(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ u8 *plp_error);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_l1_change(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *l1_change);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_l1_post(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ struct cxd2880_dvbt2_l1post
+ *l1_post);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_bbheader(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dvbt2_plp_btype
+ type,
+ struct cxd2880_dvbt2_bbheader
+ *bbheader);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_in_bandb_ts_rate(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_dvbt2_plp_btype
+ type,
+ u32 *ts_rate_bps);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_spectrum_sense(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_tnrdmd_spectrum_sense
+ *sense);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_snr(struct cxd2880_tnrdmd *tnr_dmd,
+ int *snr);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_snr_diver(struct cxd2880_tnrdmd
+ *tnr_dmd, int *snr,
+ int *snr_main,
+ int *snr_sub);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_pre_ldpcber(struct cxd2880_tnrdmd
+ *tnr_dmd, u32 *ber);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_post_bchfer(struct cxd2880_tnrdmd
+ *tnr_dmd, u32 *fer);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_pre_bchber(struct cxd2880_tnrdmd
+ *tnr_dmd, u32 *ber);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_packet_error_number(struct
+ cxd2880_tnrdmd
+ *tnr_dmd,
+ u32 *pen);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_sampling_offset(struct cxd2880_tnrdmd
+ *tnr_dmd, int *ppm);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_sampling_offset_sub(struct
+ cxd2880_tnrdmd
+ *tnr_dmd,
+ int *ppm);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_ts_rate(struct cxd2880_tnrdmd
+ *tnr_dmd, u32 *ts_rate_kbps);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_quality(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *quality);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_per(struct cxd2880_tnrdmd *tnr_dmd,
+ u32 *per);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_qam(struct cxd2880_tnrdmd *tnr_dmd,
+ enum cxd2880_dvbt2_plp_btype type,
+ enum cxd2880_dvbt2_plp_constell
+ *qam);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_code_rate(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dvbt2_plp_btype
+ type,
+ enum
+ cxd2880_dvbt2_plp_code_rate
+ *code_rate);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_profile(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dvbt2_profile
+ *profile);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_ssi(struct cxd2880_tnrdmd *tnr_dmd,
+ u8 *ssi);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_mon_ssi_sub(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *ssi);
+
+#endif
--
2.11.0
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^ permalink raw reply related
* [PATCH v2 11/15] [media] cxd2880: Add DVB-T2 control functions for the driver
From: Yasunari.Takiguchi @ 2017-04-14 2:38 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-media
Cc: tbird20d, frowand.list, Yasunari Takiguchi, Masayuki Yamamoto,
Hideki Nozawa, Kota Yonezawa, Toshihiko Matsumoto,
Satoshi Watanabe
In-Reply-To: <20170414015043.16731-1-Yasunari.Takiguchi@sony.com>
From: Yasunari Takiguchi <Yasunari.Takiguchi@sony.com>
Provide definitions, interfaces and functions needed for DVB-T2
of the Sony CXD2880 DVB-T2/T tuner + demodulator driver.
Signed-off-by: Yasunari Takiguchi <Yasunari.Takiguchi@sony.com>
Signed-off-by: Masayuki Yamamoto <Masayuki.Yamamoto@sony.com>
Signed-off-by: Hideki Nozawa <Hideki.Nozawa@sony.com>
Signed-off-by: Kota Yonezawa <Kota.Yonezawa@sony.com>
Signed-off-by: Toshihiko Matsumoto <Toshihiko.Matsumoto@sony.com>
Signed-off-by: Satoshi Watanabe <Satoshi.C.Watanabe@sony.com>
---
.../media/dvb-frontends/cxd2880/cxd2880_dvbt2.h | 402 ++++++
.../dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2.c | 1309 ++++++++++++++++++++
.../dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2.h | 82 ++
3 files changed, 1793 insertions(+)
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_dvbt2.h
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2.c
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2.h
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_dvbt2.h b/drivers/media/dvb-frontends/cxd2880/cxd2880_dvbt2.h
new file mode 100644
index 000000000000..1870398cba9d
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_dvbt2.h
@@ -0,0 +1,402 @@
+/*
+ * cxd2880_dvbt2.h
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * DVB-T2 related definitions
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CXD2880_DVBT2_H
+#define CXD2880_DVBT2_H
+
+#include "cxd2880_common.h"
+
+enum cxd2880_dvbt2_profile {
+ CXD2880_DVBT2_PROFILE_BASE,
+ CXD2880_DVBT2_PROFILE_LITE,
+ CXD2880_DVBT2_PROFILE_ANY
+};
+
+enum cxd2880_dvbt2_version {
+ CXD2880_DVBT2_V111,
+ CXD2880_DVBT2_V121,
+ CXD2880_DVBT2_V131
+};
+
+enum cxd2880_dvbt2_s1 {
+ CXD2880_DVBT2_S1_BASE_SISO = 0x00,
+ CXD2880_DVBT2_S1_BASE_MISO = 0x01,
+ CXD2880_DVBT2_S1_NON_DVBT2 = 0x02,
+ CXD2880_DVBT2_S1_LITE_SISO = 0x03,
+ CXD2880_DVBT2_S1_LITE_MISO = 0x04,
+ CXD2880_DVBT2_S1_RSVD3 = 0x05,
+ CXD2880_DVBT2_S1_RSVD4 = 0x06,
+ CXD2880_DVBT2_S1_RSVD5 = 0x07,
+ CXD2880_DVBT2_S1_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_base_s2 {
+ CXD2880_DVBT2_BASE_S2_M2K_G_ANY = 0x00,
+ CXD2880_DVBT2_BASE_S2_M8K_G_DVBT = 0x01,
+ CXD2880_DVBT2_BASE_S2_M4K_G_ANY = 0x02,
+ CXD2880_DVBT2_BASE_S2_M1K_G_ANY = 0x03,
+ CXD2880_DVBT2_BASE_S2_M16K_G_ANY = 0x04,
+ CXD2880_DVBT2_BASE_S2_M32K_G_DVBT = 0x05,
+ CXD2880_DVBT2_BASE_S2_M8K_G_DVBT2 = 0x06,
+ CXD2880_DVBT2_BASE_S2_M32K_G_DVBT2 = 0x07,
+ CXD2880_DVBT2_BASE_S2_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_lite_s2 {
+ CXD2880_DVBT2_LITE_S2_M2K_G_ANY = 0x00,
+ CXD2880_DVBT2_LITE_S2_M8K_G_DVBT = 0x01,
+ CXD2880_DVBT2_LITE_S2_M4K_G_ANY = 0x02,
+ CXD2880_DVBT2_LITE_S2_M16K_G_DVBT2 = 0x03,
+ CXD2880_DVBT2_LITE_S2_M16K_G_DVBT = 0x04,
+ CXD2880_DVBT2_LITE_S2_RSVD1 = 0x05,
+ CXD2880_DVBT2_LITE_S2_M8K_G_DVBT2 = 0x06,
+ CXD2880_DVBT2_LITE_S2_RSVD2 = 0x07,
+ CXD2880_DVBT2_LITE_S2_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_guard {
+ CXD2880_DVBT2_G1_32 = 0x00,
+ CXD2880_DVBT2_G1_16 = 0x01,
+ CXD2880_DVBT2_G1_8 = 0x02,
+ CXD2880_DVBT2_G1_4 = 0x03,
+ CXD2880_DVBT2_G1_128 = 0x04,
+ CXD2880_DVBT2_G19_128 = 0x05,
+ CXD2880_DVBT2_G19_256 = 0x06,
+ CXD2880_DVBT2_G_RSVD1 = 0x07,
+ CXD2880_DVBT2_G_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_mode {
+ CXD2880_DVBT2_M2K = 0x00,
+ CXD2880_DVBT2_M8K = 0x01,
+ CXD2880_DVBT2_M4K = 0x02,
+ CXD2880_DVBT2_M1K = 0x03,
+ CXD2880_DVBT2_M16K = 0x04,
+ CXD2880_DVBT2_M32K = 0x05,
+ CXD2880_DVBT2_M_RSVD1 = 0x06,
+ CXD2880_DVBT2_M_RSVD2 = 0x07
+};
+
+enum cxd2880_dvbt2_bw {
+ CXD2880_DVBT2_BW_8 = 0x00,
+ CXD2880_DVBT2_BW_7 = 0x01,
+ CXD2880_DVBT2_BW_6 = 0x02,
+ CXD2880_DVBT2_BW_5 = 0x03,
+ CXD2880_DVBT2_BW_10 = 0x04,
+ CXD2880_DVBT2_BW_1_7 = 0x05,
+ CXD2880_DVBT2_BW_RSVD1 = 0x06,
+ CXD2880_DVBT2_BW_RSVD2 = 0x07,
+ CXD2880_DVBT2_BW_RSVD3 = 0x08,
+ CXD2880_DVBT2_BW_RSVD4 = 0x09,
+ CXD2880_DVBT2_BW_RSVD5 = 0x0A,
+ CXD2880_DVBT2_BW_RSVD6 = 0x0B,
+ CXD2880_DVBT2_BW_RSVD7 = 0x0C,
+ CXD2880_DVBT2_BW_RSVD8 = 0x0D,
+ CXD2880_DVBT2_BW_RSVD9 = 0x0E,
+ CXD2880_DVBT2_BW_RSVD10 = 0x0F,
+ CXD2880_DVBT2_BW_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_l1pre_type {
+ CXD2880_DVBT2_L1PRE_TYPE_TS = 0x00,
+ CXD2880_DVBT2_L1PRE_TYPE_GS = 0x01,
+ CXD2880_DVBT2_L1PRE_TYPE_TS_GS = 0x02,
+ CXD2880_DVBT2_L1PRE_TYPE_RESERVED = 0x03,
+ CXD2880_DVBT2_L1PRE_TYPE_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_papr {
+ CXD2880_DVBT2_PAPR_0 = 0x00,
+ CXD2880_DVBT2_PAPR_1 = 0x01,
+ CXD2880_DVBT2_PAPR_2 = 0x02,
+ CXD2880_DVBT2_PAPR_3 = 0x03,
+ CXD2880_DVBT2_PAPR_RSVD1 = 0x04,
+ CXD2880_DVBT2_PAPR_RSVD2 = 0x05,
+ CXD2880_DVBT2_PAPR_RSVD3 = 0x06,
+ CXD2880_DVBT2_PAPR_RSVD4 = 0x07,
+ CXD2880_DVBT2_PAPR_RSVD5 = 0x08,
+ CXD2880_DVBT2_PAPR_RSVD6 = 0x09,
+ CXD2880_DVBT2_PAPR_RSVD7 = 0x0A,
+ CXD2880_DVBT2_PAPR_RSVD8 = 0x0B,
+ CXD2880_DVBT2_PAPR_RSVD9 = 0x0C,
+ CXD2880_DVBT2_PAPR_RSVD10 = 0x0D,
+ CXD2880_DVBT2_PAPR_RSVD11 = 0x0E,
+ CXD2880_DVBT2_PAPR_RSVD12 = 0x0F,
+ CXD2880_DVBT2_PAPR_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_l1post_constell {
+ CXD2880_DVBT2_L1POST_BPSK = 0x00,
+ CXD2880_DVBT2_L1POST_QPSK = 0x01,
+ CXD2880_DVBT2_L1POST_QAM16 = 0x02,
+ CXD2880_DVBT2_L1POST_QAM64 = 0x03,
+ CXD2880_DVBT2_L1POST_C_RSVD1 = 0x04,
+ CXD2880_DVBT2_L1POST_C_RSVD2 = 0x05,
+ CXD2880_DVBT2_L1POST_C_RSVD3 = 0x06,
+ CXD2880_DVBT2_L1POST_C_RSVD4 = 0x07,
+ CXD2880_DVBT2_L1POST_C_RSVD5 = 0x08,
+ CXD2880_DVBT2_L1POST_C_RSVD6 = 0x09,
+ CXD2880_DVBT2_L1POST_C_RSVD7 = 0x0A,
+ CXD2880_DVBT2_L1POST_C_RSVD8 = 0x0B,
+ CXD2880_DVBT2_L1POST_C_RSVD9 = 0x0C,
+ CXD2880_DVBT2_L1POST_C_RSVD10 = 0x0D,
+ CXD2880_DVBT2_L1POST_C_RSVD11 = 0x0E,
+ CXD2880_DVBT2_L1POST_C_RSVD12 = 0x0F,
+ CXD2880_DVBT2_L1POST_CONSTELL_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_l1post_cr {
+ CXD2880_DVBT2_L1POST_R1_2 = 0x00,
+ CXD2880_DVBT2_L1POST_R_RSVD1 = 0x01,
+ CXD2880_DVBT2_L1POST_R_RSVD2 = 0x02,
+ CXD2880_DVBT2_L1POST_R_RSVD3 = 0x03,
+ CXD2880_DVBT2_L1POST_R_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_l1post_fec_type {
+ CXD2880_DVBT2_L1POST_FEC_LDPC16K = 0x00,
+ CXD2880_DVBT2_L1POST_FEC_RSVD1 = 0x01,
+ CXD2880_DVBT2_L1POST_FEC_RSVD2 = 0x02,
+ CXD2880_DVBT2_L1POST_FEC_RSVD3 = 0x03,
+ CXD2880_DVBT2_L1POST_FEC_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_pp {
+ CXD2880_DVBT2_PP1 = 0x00,
+ CXD2880_DVBT2_PP2 = 0x01,
+ CXD2880_DVBT2_PP3 = 0x02,
+ CXD2880_DVBT2_PP4 = 0x03,
+ CXD2880_DVBT2_PP5 = 0x04,
+ CXD2880_DVBT2_PP6 = 0x05,
+ CXD2880_DVBT2_PP7 = 0x06,
+ CXD2880_DVBT2_PP8 = 0x07,
+ CXD2880_DVBT2_PP_RSVD1 = 0x08,
+ CXD2880_DVBT2_PP_RSVD2 = 0x09,
+ CXD2880_DVBT2_PP_RSVD3 = 0x0A,
+ CXD2880_DVBT2_PP_RSVD4 = 0x0B,
+ CXD2880_DVBT2_PP_RSVD5 = 0x0C,
+ CXD2880_DVBT2_PP_RSVD6 = 0x0D,
+ CXD2880_DVBT2_PP_RSVD7 = 0x0E,
+ CXD2880_DVBT2_PP_RSVD8 = 0x0F,
+ CXD2880_DVBT2_PP_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_plp_code_rate {
+ CXD2880_DVBT2_R1_2 = 0x00,
+ CXD2880_DVBT2_R3_5 = 0x01,
+ CXD2880_DVBT2_R2_3 = 0x02,
+ CXD2880_DVBT2_R3_4 = 0x03,
+ CXD2880_DVBT2_R4_5 = 0x04,
+ CXD2880_DVBT2_R5_6 = 0x05,
+ CXD2880_DVBT2_R1_3 = 0x06,
+ CXD2880_DVBT2_R2_5 = 0x07,
+ CXD2880_DVBT2_PLP_CR_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_plp_constell {
+ CXD2880_DVBT2_QPSK = 0x00,
+ CXD2880_DVBT2_QAM16 = 0x01,
+ CXD2880_DVBT2_QAM64 = 0x02,
+ CXD2880_DVBT2_QAM256 = 0x03,
+ CXD2880_DVBT2_CON_RSVD1 = 0x04,
+ CXD2880_DVBT2_CON_RSVD2 = 0x05,
+ CXD2880_DVBT2_CON_RSVD3 = 0x06,
+ CXD2880_DVBT2_CON_RSVD4 = 0x07,
+ CXD2880_DVBT2_CONSTELL_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_plp_type {
+ CXD2880_DVBT2_PLP_TYPE_COMMON = 0x00,
+ CXD2880_DVBT2_PLP_TYPE_DATA1 = 0x01,
+ CXD2880_DVBT2_PLP_TYPE_DATA2 = 0x02,
+ CXD2880_DVBT2_PLP_TYPE_RSVD1 = 0x03,
+ CXD2880_DVBT2_PLP_TYPE_RSVD2 = 0x04,
+ CXD2880_DVBT2_PLP_TYPE_RSVD3 = 0x05,
+ CXD2880_DVBT2_PLP_TYPE_RSVD4 = 0x06,
+ CXD2880_DVBT2_PLP_TYPE_RSVD5 = 0x07,
+ CXD2880_DVBT2_PLP_TYPE_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_plp_payload {
+ CXD2880_DVBT2_PLP_PAYLOAD_GFPS = 0x00,
+ CXD2880_DVBT2_PLP_PAYLOAD_GCS = 0x01,
+ CXD2880_DVBT2_PLP_PAYLOAD_GSE = 0x02,
+ CXD2880_DVBT2_PLP_PAYLOAD_TS = 0x03,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD1 = 0x04,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD2 = 0x05,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD3 = 0x06,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD4 = 0x07,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD5 = 0x08,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD6 = 0x09,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD7 = 0x0A,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD8 = 0x0B,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD9 = 0x0C,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD10 = 0x0D,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD11 = 0x0E,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD12 = 0x0F,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD13 = 0x10,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD14 = 0x11,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD15 = 0x12,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD16 = 0x13,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD17 = 0x14,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD18 = 0x15,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD19 = 0x16,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD20 = 0x17,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD21 = 0x18,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD22 = 0x19,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD23 = 0x1A,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD24 = 0x1B,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD25 = 0x1C,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD26 = 0x1D,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD27 = 0x1E,
+ CXD2880_DVBT2_PLP_PAYLOAD_RSVD28 = 0x1F,
+ CXD2880_DVBT2_PLP_PAYLOAD_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_plp_fec {
+ CXD2880_DVBT2_FEC_LDPC_16K = 0x00,
+ CXD2880_DVBT2_FEC_LDPC_64K = 0x01,
+ CXD2880_DVBT2_FEC_RSVD1 = 0x02,
+ CXD2880_DVBT2_FEC_RSVD2 = 0x03,
+ CXD2880_DVBT2_FEC_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_plp_mode {
+ CXD2880_DVBT2_PLP_MODE_NOTSPECIFIED = 0x00,
+ CXD2880_DVBT2_PLP_MODE_NM = 0x01,
+ CXD2880_DVBT2_PLP_MODE_HEM = 0x02,
+ CXD2880_DVBT2_PLP_MODE_RESERVED = 0x03,
+ CXD2880_DVBT2_PLP_MODE_UNKNOWN = 0xFF
+};
+
+enum cxd2880_dvbt2_plp_btype {
+ CXD2880_DVBT2_PLP_COMMON,
+ CXD2880_DVBT2_PLP_DATA
+};
+
+enum cxd2880_dvbt2_stream {
+ CXD2880_DVBT2_STREAM_GENERIC_PACKETIZED = 0x00,
+ CXD2880_DVBT2_STREAM_GENERIC_CONTINUOUS = 0x01,
+ CXD2880_DVBT2_STREAM_GENERIC_ENCAPSULATED = 0x02,
+ CXD2880_DVBT2_STREAM_TRANSPORT = 0x03,
+ CXD2880_DVBT2_STREAM_UNKNOWN = 0xFF
+};
+
+struct cxd2880_dvbt2_l1pre {
+ enum cxd2880_dvbt2_l1pre_type type;
+ u8 bw_ext;
+ enum cxd2880_dvbt2_s1 s1;
+ u8 s2;
+ u8 mixed;
+ enum cxd2880_dvbt2_mode fft_mode;
+ u8 l1_rep;
+ enum cxd2880_dvbt2_guard gi;
+ enum cxd2880_dvbt2_papr papr;
+ enum cxd2880_dvbt2_l1post_constell mod;
+ enum cxd2880_dvbt2_l1post_cr cr;
+ enum cxd2880_dvbt2_l1post_fec_type fec;
+ u32 l1_post_size;
+ u32 l1_post_info_size;
+ enum cxd2880_dvbt2_pp pp;
+ u8 tx_id_availability;
+ u16 cell_id;
+ u16 network_id;
+ u16 sys_id;
+ u8 num_frames;
+ u16 num_symbols;
+ u8 regen;
+ u8 post_ext;
+ u8 num_rf_freqs;
+ u8 rf_idx;
+ enum cxd2880_dvbt2_version t2_version;
+ u8 l1_post_scrambled;
+ u8 t2_base_lite;
+ u32 crc32;
+};
+
+struct cxd2880_dvbt2_plp {
+ u8 id;
+ enum cxd2880_dvbt2_plp_type type;
+ enum cxd2880_dvbt2_plp_payload payload;
+ u8 ff;
+ u8 first_rf_idx;
+ u8 first_frm_idx;
+ u8 group_id;
+ enum cxd2880_dvbt2_plp_constell constell;
+ enum cxd2880_dvbt2_plp_code_rate plp_cr;
+ u8 rot;
+ enum cxd2880_dvbt2_plp_fec fec;
+ u16 num_blocks_max;
+ u8 frm_int;
+ u8 til_len;
+ u8 til_type;
+ u8 in_band_a_flag;
+ u8 in_band_b_flag;
+ u16 rsvd;
+ enum cxd2880_dvbt2_plp_mode plp_mode;
+ u8 static_flag;
+ u8 static_padding_flag;
+};
+
+struct cxd2880_dvbt2_l1post {
+ u16 sub_slices_per_frame;
+ u8 num_plps;
+ u8 num_aux;
+ u8 aux_cfg_rfu;
+ u8 rf_idx;
+ u32 freq;
+ u8 fef_type;
+ u32 fef_length;
+ u8 fef_intvl;
+};
+
+struct cxd2880_dvbt2_ofdm {
+ u8 mixed;
+ u8 is_miso;
+ enum cxd2880_dvbt2_mode mode;
+ enum cxd2880_dvbt2_guard gi;
+ enum cxd2880_dvbt2_pp pp;
+ u8 bw_ext;
+ enum cxd2880_dvbt2_papr papr;
+ u16 num_symbols;
+};
+
+struct cxd2880_dvbt2_bbheader {
+ enum cxd2880_dvbt2_stream stream_input;
+ u8 is_single_input_stream;
+ u8 is_constant_coding_modulation;
+ u8 issy_indicator;
+ u8 null_packet_deletion;
+ u8 ext;
+ u8 input_stream_identifier;
+ u16 user_packet_length;
+ u16 data_field_length;
+ u8 sync_byte;
+ u32 issy;
+ enum cxd2880_dvbt2_plp_mode plp_mode;
+};
+
+#endif
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2.c b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2.c
new file mode 100644
index 000000000000..bdad65b7298a
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2.c
@@ -0,0 +1,1309 @@
+/*
+ * cxd2880_tnrdmd_dvbt2.c
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * control functions for DVB-T2
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cxd2880_tnrdmd_dvbt2.h"
+#include "cxd2880_tnrdmd_dvbt2_mon.h"
+
+static enum cxd2880_ret x_tune_dvbt2_demod_setting(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dtv_bandwidth
+ bandwidth,
+ enum cxd2880_tnrdmd_clockmode
+ clk_mode)
+{
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_SYS, 0x00,
+ 0x00) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_SYS, 0x31,
+ 0x02) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x04) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x5D,
+ 0x0B) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_SUB) {
+ u8 data[2] = { 0x01, 0x01 };
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x00) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xCE, data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data[14] = { 0x07, 0x06, 0x01, 0xF0,
+ 0x00, 0x00, 0x04, 0xB0, 0x00, 0x00, 0x09, 0x9C, 0x0E,
+ 0x4C
+ };
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x20) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x8A,
+ data[0]) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x90,
+ data[1]) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x25) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xF0, &data[2],
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x2A) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xDC,
+ data[4]) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xDE,
+ data[5]) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x2D) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x73, &data[6],
+ 4) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x8F, &data[10],
+ 4) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data_a_1[9] = { 0x52, 0x49, 0x2C, 0x51,
+ 0x51, 0x3D, 0x15, 0x29, 0x0C
+ };
+ u8 data_b_1[9] = { 0x5D, 0x55, 0x32, 0x5C,
+ 0x5C, 0x45, 0x17, 0x2E, 0x0D
+ };
+ u8 data_c_1[9] = { 0x60, 0x00, 0x34, 0x5E,
+ 0x5E, 0x47, 0x18, 0x2F, 0x0E
+ };
+
+ u8 data_a_2[13] = { 0x04, 0xE7, 0x94, 0x92,
+ 0x09, 0xCF, 0x7E, 0xD0, 0x49, 0xCD, 0xCD, 0x1F, 0x5B
+ };
+ u8 data_b_2[13] = { 0x05, 0x90, 0x27, 0x55,
+ 0x0B, 0x20, 0x8F, 0xD6, 0xEA, 0xC8, 0xC8, 0x23, 0x91
+ };
+ u8 data_c_2[13] = { 0x05, 0xB8, 0xD8, 0x00,
+ 0x0B, 0x72, 0x93, 0xF3, 0x00, 0xCD, 0xCD, 0x24, 0x95
+ };
+
+ u8 data_a_3[5] = { 0x0B, 0x6A, 0xC9, 0x03,
+ 0x33
+ };
+ u8 data_b_3[5] = { 0x01, 0x02, 0xE4, 0x03,
+ 0x39
+ };
+ u8 data_c_3[5] = { 0x01, 0x02, 0xEB, 0x03,
+ 0x3B
+ };
+
+ u8 *data_1 = NULL;
+ u8 *data_2 = NULL;
+ u8 *data_3 = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data_1 = data_a_1;
+ data_2 = data_a_2;
+ data_3 = data_a_3;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data_1 = data_b_1;
+ data_2 = data_b_2;
+ data_3 = data_b_3;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data_1 = data_c_1;
+ data_2 = data_c_2;
+ data_3 = data_c_3;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x04) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x1D,
+ &data_1[0], 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x22,
+ data_1[3]) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x24,
+ data_1[4]) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x26,
+ data_1[5]) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x29,
+ &data_1[6], 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x2D,
+ data_1[8]) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_SUB) {
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x2E,
+ &data_2[0],
+ 6) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x35,
+ &data_2[6],
+ 7) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x3C,
+ &data_3[0], 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x56,
+ &data_3[2], 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ switch (bandwidth) {
+ case CXD2880_DTV_BW_8_MHZ:
+
+ {
+ u8 data_ac[6] = { 0x15, 0x00, 0x00, 0x00,
+ 0x00, 0x00
+ };
+ u8 data_b[6] = { 0x14, 0x6A, 0xAA, 0xAA,
+ 0xAB, 0x00
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_ac;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x10,
+ data,
+ 6) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4A,
+ 0x00) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data_a[2] = { 0x19, 0xD2 };
+ u8 data_bc[2] = { 0x3F, 0xFF };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_bc;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x19,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data_a[2] = { 0x06, 0x2A };
+ u8 data_b[2] = { 0x06, 0x29 };
+ u8 data_c[2] = { 0x06, 0x28 };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x1B,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ u8 data_a[9] = { 0x28, 0x00, 0x50, 0x00,
+ 0x60, 0x00, 0x00, 0x90, 0x00
+ };
+ u8 data_b[9] = { 0x2D, 0x5E, 0x5A, 0xBD,
+ 0x6C, 0xE3, 0x00, 0xA3, 0x55
+ };
+ u8 data_c[9] = { 0x2E, 0xAA, 0x5D, 0x55,
+ 0x70, 0x00, 0x00, 0xA8, 0x00
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4B,
+ data,
+ 9) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ break;
+
+ case CXD2880_DTV_BW_7_MHZ:
+
+ {
+ u8 data_ac[6] = { 0x18, 0x00, 0x00, 0x00,
+ 0x00, 0x00
+ };
+ u8 data_b[6] = { 0x17, 0x55, 0x55, 0x55,
+ 0x55, 0x00
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_ac;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x10,
+ data,
+ 6) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4A,
+ 0x02) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data[2] = { 0x3F, 0xFF };
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x19,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data_a[2] = { 0x06, 0x23 };
+ u8 data_b[2] = { 0x06, 0x22 };
+ u8 data_c[2] = { 0x06, 0x21 };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x1B,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ u8 data_a[9] = { 0x2D, 0xB6, 0x5B, 0x6D,
+ 0x6D, 0xB6, 0x00, 0xA4, 0x92
+ };
+ u8 data_b[9] = { 0x33, 0xDA, 0x67, 0xB4,
+ 0x7C, 0x71, 0x00, 0xBA, 0xAA
+ };
+ u8 data_c[9] = { 0x35, 0x55, 0x6A, 0xAA,
+ 0x80, 0x00, 0x00, 0xC0, 0x00
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4B,
+ data,
+ 9) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ break;
+
+ case CXD2880_DTV_BW_6_MHZ:
+
+ {
+ u8 data_ac[6] = { 0x1C, 0x00, 0x00, 0x00,
+ 0x00, 0x00
+ };
+ u8 data_b[6] = { 0x1B, 0x38, 0xE3, 0x8E,
+ 0x39, 0x00
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_ac;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x10,
+ data,
+ 6) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4A,
+ 0x04) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data[2] = { 0x3F, 0xFF };
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x19,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data_a[2] = { 0x06, 0x1C };
+ u8 data_b[2] = { 0x06, 0x1B };
+ u8 data_c[2] = { 0x06, 0x1A };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x1B,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ u8 data_a[9] = { 0x35, 0x55, 0x6A, 0xAA,
+ 0x80, 0x00, 0x00, 0xC0, 0x00
+ };
+ u8 data_b[9] = { 0x3C, 0x7E, 0x78, 0xFC,
+ 0x91, 0x2F, 0x00, 0xD9, 0xC7
+ };
+ u8 data_c[9] = { 0x3E, 0x38, 0x7C, 0x71,
+ 0x95, 0x55, 0x00, 0xDF, 0xFF
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4B,
+ data,
+ 9) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ break;
+
+ case CXD2880_DTV_BW_5_MHZ:
+
+ {
+ u8 data_ac[6] = { 0x21, 0x99, 0x99, 0x99,
+ 0x9A, 0x00
+ };
+ u8 data_b[6] = { 0x20, 0xAA, 0xAA, 0xAA,
+ 0xAB, 0x00
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_ac;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x10,
+ data,
+ 6) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4A,
+ 0x06) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data[2] = { 0x3F, 0xFF };
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x19,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data_a[2] = { 0x06, 0x15 };
+ u8 data_b[2] = { 0x06, 0x15 };
+ u8 data_c[2] = { 0x06, 0x14 };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x1B,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ u8 data_a[9] = { 0x40, 0x00, 0x6A, 0xAA,
+ 0x80, 0x00, 0x00, 0xE6, 0x66
+ };
+ u8 data_b[9] = { 0x48, 0x97, 0x78, 0xFC,
+ 0x91, 0x2F, 0x01, 0x05, 0x55
+ };
+ u8 data_c[9] = { 0x4A, 0xAA, 0x7C, 0x71,
+ 0x95, 0x55, 0x01, 0x0C, 0xCC
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4B,
+ data,
+ 9) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ break;
+
+ case CXD2880_DTV_BW_1_7_MHZ:
+
+ {
+ u8 data_a[6] = { 0x68, 0x0F, 0xA2, 0x32,
+ 0xCF, 0x03
+ };
+ u8 data_c[6] = { 0x68, 0x0F, 0xA2, 0x32,
+ 0xCF, 0x03
+ };
+ u8 data_b[6] = { 0x65, 0x2B, 0xA4, 0xCD,
+ 0xD8, 0x03
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x10,
+ data,
+ 6) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4A,
+ 0x03) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data[2] = { 0x3F, 0xFF };
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x19,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data_a[2] = { 0x06, 0x0C };
+ u8 data_b[2] = { 0x06, 0x0C };
+ u8 data_c[2] = { 0x06, 0x0B };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x1B,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ u8 data_a[9] = { 0x40, 0x00, 0x6A, 0xAA,
+ 0x80, 0x00, 0x02, 0xC9, 0x8F
+ };
+ u8 data_b[9] = { 0x48, 0x97, 0x78, 0xFC,
+ 0x91, 0x2F, 0x03, 0x29, 0x5D
+ };
+ u8 data_c[9] = { 0x4A, 0xAA, 0x7C, 0x71,
+ 0x95, 0x55, 0x03, 0x40, 0x7D
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4B,
+ data,
+ 9) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ break;
+
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x00) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xFD,
+ 0x01) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ return CXD2880_RESULT_OK;
+}
+
+static enum cxd2880_ret x_sleep_dvbt2_demod_setting(struct cxd2880_tnrdmd
+ *tnr_dmd)
+{
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ u8 data[] = { 0, 1, 0, 2,
+ 0, 4, 0, 8, 0, 16, 0, 32
+ };
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x1D) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x47, data,
+ 12) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+static enum cxd2880_ret dvbt2_set_profile(struct cxd2880_tnrdmd *tnr_dmd,
+ enum cxd2880_dvbt2_profile profile)
+{
+ u8 t2_mode_tune_mode = 0;
+ u8 seq_not2_dtime = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ {
+ u8 dtime1 = 0;
+ u8 dtime2 = 0;
+
+ switch (tnr_dmd->clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ dtime1 = 0x27;
+ dtime2 = 0x0C;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ dtime1 = 0x2C;
+ dtime2 = 0x0D;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ dtime1 = 0x2E;
+ dtime2 = 0x0E;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ switch (profile) {
+ case CXD2880_DVBT2_PROFILE_BASE:
+ t2_mode_tune_mode = 0x01;
+ seq_not2_dtime = dtime2;
+ break;
+
+ case CXD2880_DVBT2_PROFILE_LITE:
+ t2_mode_tune_mode = 0x05;
+ seq_not2_dtime = dtime1;
+ break;
+
+ case CXD2880_DVBT2_PROFILE_ANY:
+ t2_mode_tune_mode = 0x00;
+ seq_not2_dtime = dtime1;
+ break;
+
+ default:
+ return CXD2880_RESULT_ERROR_ARG;
+ }
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x2E) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x10,
+ t2_mode_tune_mode) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x04) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x2C,
+ seq_not2_dtime) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_tune1(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt2_tune_param
+ *tune_param)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!tune_param))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if ((tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP) &&
+ (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE))
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if ((tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) &&
+ (tune_param->profile == CXD2880_DVBT2_PROFILE_ANY))
+ return CXD2880_RESULT_ERROR_NOSUPPORT;
+
+ ret =
+ cxd2880_tnrdmd_common_tune_setting1(tnr_dmd, CXD2880_DTV_SYS_DVBT2,
+ tune_param->center_freq_khz,
+ tune_param->bandwidth, 0, 0);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret =
+ x_tune_dvbt2_demod_setting(tnr_dmd, tune_param->bandwidth,
+ tnr_dmd->clk_mode);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ ret =
+ x_tune_dvbt2_demod_setting(tnr_dmd->diver_sub,
+ tune_param->bandwidth,
+ tnr_dmd->diver_sub->clk_mode);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ }
+
+ ret = dvbt2_set_profile(tnr_dmd, tune_param->profile);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ ret =
+ dvbt2_set_profile(tnr_dmd->diver_sub, tune_param->profile);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ }
+
+ if (tune_param->data_plp_id == CXD2880_DVBT2_TUNE_PARAM_PLPID_AUTO) {
+ ret = cxd2880_tnrdmd_dvbt2_set_plp_cfg(tnr_dmd, 1, 0);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ } else {
+ ret =
+ cxd2880_tnrdmd_dvbt2_set_plp_cfg(tnr_dmd, 0,
+ (u8)(tune_param->data_plp_id));
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_tune2(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt2_tune_param
+ *tune_param)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!tune_param))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if ((tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP) &&
+ (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE))
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 en_fef_intmtnt_ctrl = 1;
+
+ switch (tune_param->profile) {
+ case CXD2880_DVBT2_PROFILE_BASE:
+ en_fef_intmtnt_ctrl = tnr_dmd->en_fef_intmtnt_base;
+ break;
+ case CXD2880_DVBT2_PROFILE_LITE:
+ en_fef_intmtnt_ctrl = tnr_dmd->en_fef_intmtnt_lite;
+ break;
+ case CXD2880_DVBT2_PROFILE_ANY:
+ if (tnr_dmd->en_fef_intmtnt_base &&
+ tnr_dmd->en_fef_intmtnt_lite)
+ en_fef_intmtnt_ctrl = 1;
+ else
+ en_fef_intmtnt_ctrl = 0;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_ARG;
+ }
+
+ ret =
+ cxd2880_tnrdmd_common_tune_setting2(tnr_dmd,
+ CXD2880_DTV_SYS_DVBT2,
+ en_fef_intmtnt_ctrl);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ }
+
+ tnr_dmd->state = CXD2880_TNRDMD_STATE_ACTIVE;
+ tnr_dmd->frequency_khz = tune_param->center_freq_khz;
+ tnr_dmd->sys = CXD2880_DTV_SYS_DVBT2;
+ tnr_dmd->bandwidth = tune_param->bandwidth;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ tnr_dmd->diver_sub->state = CXD2880_TNRDMD_STATE_ACTIVE;
+ tnr_dmd->diver_sub->frequency_khz = tune_param->center_freq_khz;
+ tnr_dmd->diver_sub->sys = CXD2880_DTV_SYS_DVBT2;
+ tnr_dmd->diver_sub->bandwidth = tune_param->bandwidth;
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_sleep_setting(struct cxd2880_tnrdmd
+ *tnr_dmd)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if ((tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP) &&
+ (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE))
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = x_sleep_dvbt2_demod_setting(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ ret = x_sleep_dvbt2_demod_setting(tnr_dmd->diver_sub);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_check_demod_lock(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_tnrdmd_lock_result
+ *lock)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ u8 sync_stat = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+ u8 unlock_detected_sub = 0;
+
+ if ((!tnr_dmd) || (!lock))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_stat, &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
+ if (sync_stat == 6)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
+ else if (unlock_detected)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
+ else
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+
+ return ret;
+ }
+
+ if (sync_stat == 6) {
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
+ return ret;
+ }
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub(tnr_dmd, &sync_stat,
+ &unlock_detected_sub);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (sync_stat == 6)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
+ else if (unlock_detected && unlock_detected_sub)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
+ else
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_check_ts_lock(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_tnrdmd_lock_result
+ *lock)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ u8 sync_stat = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+ u8 unlock_detected_sub = 0;
+
+ if ((!tnr_dmd) || (!lock))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_stat, &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
+ if (ts_lock)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
+ else if (unlock_detected)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
+ else
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+
+ return ret;
+ }
+
+ if (ts_lock) {
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
+ return ret;
+ } else if (!unlock_detected) {
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+ return ret;
+ }
+
+ ret =
+ cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub(tnr_dmd, &sync_stat,
+ &unlock_detected_sub);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (unlock_detected && unlock_detected_sub)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
+ else
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_set_plp_cfg(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 auto_plp,
+ u8 plp_id)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if ((tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP) &&
+ (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE))
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x23) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (!auto_plp) {
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xAF,
+ plp_id) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xAD,
+ auto_plp ? 0x00 : 0x01) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_diver_fef_setting(struct cxd2880_tnrdmd
+ *tnr_dmd)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE)
+ return CXD2880_RESULT_OK;
+
+ {
+ struct cxd2880_dvbt2_ofdm ofdm;
+
+ ret = cxd2880_tnrdmd_dvbt2_mon_ofdm(tnr_dmd, &ofdm);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (!ofdm.mixed)
+ return CXD2880_RESULT_OK;
+ }
+
+ {
+ u8 data[] = { 0, 8, 0, 16,
+ 0, 32, 0, 64, 0, 128, 1, 0
+ };
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x1D) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x47, data,
+ 12) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_check_l1post_valid(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ u8 *l1_post_valid)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ u8 data;
+
+ if ((!tnr_dmd) || (!l1_post_valid))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if ((tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP) &&
+ (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE))
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0B) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x86, &data,
+ 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ *l1_post_valid = data & 0x01;
+
+ return ret;
+}
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2.h b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2.h
new file mode 100644
index 000000000000..8735280f0143
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2.h
@@ -0,0 +1,82 @@
+/*
+ * cxd2880_tnrdmd_dvbt2.h
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * control interface for DVB-T2
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CXD2880_TNRDMD_DVBT2_H
+#define CXD2880_TNRDMD_DVBT2_H
+
+#include "cxd2880_common.h"
+#include "cxd2880_tnrdmd.h"
+
+enum cxd2880_tnrdmd_dvbt2_tune_info {
+ CXD2880_TNRDMD_DVBT2_TUNE_INFO_OK,
+ CXD2880_TNRDMD_DVBT2_TUNE_INFO_INVALID_PLP_ID
+};
+
+struct cxd2880_dvbt2_tune_param {
+ u32 center_freq_khz;
+ enum cxd2880_dtv_bandwidth bandwidth;
+ u16 data_plp_id;
+ enum cxd2880_dvbt2_profile profile;
+ enum cxd2880_tnrdmd_dvbt2_tune_info tune_info;
+};
+
+#define CXD2880_DVBT2_TUNE_PARAM_PLPID_AUTO 0xFFFF
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_tune1(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt2_tune_param
+ *tune_param);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_tune2(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt2_tune_param
+ *tune_param);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_sleep_setting(struct cxd2880_tnrdmd
+ *tnr_dmd);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_check_demod_lock(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_tnrdmd_lock_result
+ *lock);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_check_ts_lock(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_tnrdmd_lock_result
+ *lock);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_set_plp_cfg(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 auto_plp,
+ u8 plp_id);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_diver_fef_setting(struct cxd2880_tnrdmd
+ *tnr_dmd);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt2_check_l1post_valid(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ u8 *l1_post_valid);
+
+#endif
--
2.11.0
^ permalink raw reply related
* [PATCH v2 10/15] [media] cxd2880: Add DVB-T monitor and integration layer functions
From: Yasunari.Takiguchi-7U/KSKJipcs @ 2017-04-14 2:35 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-media-u79uwXL29TY76Z2rM5mHXA
Cc: tbird20d-Re5JQEeQqe8AvxtiuMwx3w,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, Yasunari Takiguchi,
Masayuki Yamamoto, Hideki Nozawa, Kota Yonezawa,
Toshihiko Matsumoto, Satoshi Watanabe
In-Reply-To: <20170414015043.16731-1-Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
From: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
Provide monitor and integration layer functions (DVB-T)
for the Sony CXD2880 DVB-T2/T tuner + demodulator driver.
Signed-off-by: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Masayuki Yamamoto <Masayuki.Yamamoto-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Hideki Nozawa <Hideki.Nozawa-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Kota Yonezawa <Kota.Yonezawa-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Toshihiko Matsumoto <Toshihiko.Matsumoto-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Satoshi Watanabe <Satoshi.C.Watanabe-7U/KSKJipcs@public.gmane.org>
---
.../dvb-frontends/cxd2880/cxd2880_integ_dvbt.c | 197 ++++
.../dvb-frontends/cxd2880/cxd2880_integ_dvbt.h | 58 +
.../cxd2880/cxd2880_tnrdmd_dvbt_mon.c | 1190 ++++++++++++++++++++
.../cxd2880/cxd2880_tnrdmd_dvbt_mon.h | 106 ++
4 files changed, 1551 insertions(+)
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt.c
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt.h
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.h
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt.c b/drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt.c
new file mode 100644
index 000000000000..43b7da69fc6d
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt.c
@@ -0,0 +1,197 @@
+/*
+ * cxd2880_integ_dvbt.c
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * integration layer functions for DVB-T
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cxd2880_tnrdmd_dvbt.h"
+#include "cxd2880_integ_dvbt.h"
+
+static enum cxd2880_ret dvbt_wait_demod_lock(struct cxd2880_tnrdmd *tnr_dmd);
+
+enum cxd2880_ret cxd2880_integ_dvbt_tune(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt_tune_param
+ *tune_param)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!tune_param))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if ((tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP) &&
+ (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE))
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ cxd2880_atomic_set(&tnr_dmd->cancel, 0);
+
+ if ((tune_param->bandwidth != CXD2880_DTV_BW_5_MHZ) &&
+ (tune_param->bandwidth != CXD2880_DTV_BW_6_MHZ) &&
+ (tune_param->bandwidth != CXD2880_DTV_BW_7_MHZ) &&
+ (tune_param->bandwidth != CXD2880_DTV_BW_8_MHZ)) {
+ return CXD2880_RESULT_ERROR_NOSUPPORT;
+ }
+
+ ret = cxd2880_tnrdmd_dvbt_tune1(tnr_dmd, tune_param);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ CXD2880_SLEEP(CXD2880_TNRDMD_WAIT_AGC_STABLE);
+
+ ret = cxd2880_tnrdmd_dvbt_tune2(tnr_dmd, tune_param);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret = dvbt_wait_demod_lock(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_integ_dvbt_wait_ts_lock(struct cxd2880_tnrdmd *tnr_dmd)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ enum cxd2880_tnrdmd_lock_result lock =
+ CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+ struct cxd2880_stopwatch timer;
+ u8 continue_wait = 1;
+ u32 elapsed = 0;
+
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = cxd2880_stopwatch_start(&timer);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ for (;;) {
+ ret = cxd2880_stopwatch_elapsed(&timer, &elapsed);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (elapsed >= CXD2880_DVBT_WAIT_TS_LOCK)
+ continue_wait = 0;
+
+ ret = cxd2880_tnrdmd_dvbt_check_ts_lock(tnr_dmd, &lock);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ switch (lock) {
+ case CXD2880_TNRDMD_LOCK_RESULT_LOCKED:
+ return CXD2880_RESULT_OK;
+
+ case CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED:
+ return CXD2880_RESULT_ERROR_UNLOCK;
+
+ default:
+ break;
+ }
+
+ ret = cxd2880_integ_check_cancellation(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (continue_wait) {
+ ret =
+ cxd2880_stopwatch_sleep(&timer,
+ CXD2880_DVBT_WAIT_LOCK_INTVL);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ } else {
+ ret = CXD2880_RESULT_ERROR_TIMEOUT;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static enum cxd2880_ret dvbt_wait_demod_lock(struct cxd2880_tnrdmd *tnr_dmd)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ enum cxd2880_tnrdmd_lock_result lock =
+ CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+ struct cxd2880_stopwatch timer;
+ u8 continue_wait = 1;
+ u32 elapsed = 0;
+
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = cxd2880_stopwatch_start(&timer);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ for (;;) {
+ ret = cxd2880_stopwatch_elapsed(&timer, &elapsed);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (elapsed >= CXD2880_DVBT_WAIT_DMD_LOCK)
+ continue_wait = 0;
+
+ ret = cxd2880_tnrdmd_dvbt_check_demod_lock(tnr_dmd, &lock);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ switch (lock) {
+ case CXD2880_TNRDMD_LOCK_RESULT_LOCKED:
+ return CXD2880_RESULT_OK;
+
+ case CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED:
+ return CXD2880_RESULT_ERROR_UNLOCK;
+
+ default:
+ break;
+ }
+
+ ret = cxd2880_integ_check_cancellation(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (continue_wait) {
+ ret =
+ cxd2880_stopwatch_sleep(&timer,
+ CXD2880_DVBT_WAIT_LOCK_INTVL);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ } else {
+ ret = CXD2880_RESULT_ERROR_TIMEOUT;
+ break;
+ }
+ }
+
+ return ret;
+}
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt.h b/drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt.h
new file mode 100644
index 000000000000..41f35c07a15e
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_integ_dvbt.h
@@ -0,0 +1,58 @@
+/*
+ * cxd2880_integ_dvbt.h
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * integration layer interface for DVB-T
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CXD2880_INTEG_DVBT_H
+#define CXD2880_INTEG_DVBT_H
+
+#include "cxd2880_tnrdmd.h"
+#include "cxd2880_tnrdmd_dvbt.h"
+#include "cxd2880_integ.h"
+
+#define CXD2880_DVBT_WAIT_DMD_LOCK 1000
+#define CXD2880_DVBT_WAIT_TS_LOCK 1000
+#define CXD2880_DVBT_WAIT_LOCK_INTVL 10
+
+struct cxd2880_integ_dvbt_scan_param {
+ u32 start_frequency_khz;
+ u32 end_frequency_khz;
+ u32 step_frequency_khz;
+ enum cxd2880_dtv_bandwidth bandwidth;
+};
+
+struct cxd2880_integ_dvbt_scan_result {
+ u32 center_freq_khz;
+ enum cxd2880_ret tune_result;
+ struct cxd2880_dvbt_tune_param dvbt_tune_param;
+};
+
+enum cxd2880_ret cxd2880_integ_dvbt_tune(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt_tune_param
+ *tune_param);
+
+enum cxd2880_ret cxd2880_integ_dvbt_wait_ts_lock(struct cxd2880_tnrdmd
+ *tnr_dmd);
+
+#endif
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c
new file mode 100644
index 000000000000..d890081b6424
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c
@@ -0,0 +1,1190 @@
+/*
+ * cxd2880_tnrdmd_dvbt_mon.c
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * DVB-T monitor functions
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cxd2880_tnrdmd_mon.h"
+#include "cxd2880_tnrdmd_dvbt.h"
+#include "cxd2880_tnrdmd_dvbt_mon.h"
+#include "cxd2880_math.h"
+
+static enum cxd2880_ret is_tps_locked(struct cxd2880_tnrdmd *tnr_dmd);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_sync_stat(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *sync_stat,
+ u8 *ts_lock_stat,
+ u8 *unlock_detected)
+{
+ u8 rdata = 0x00;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!sync_stat) || (!ts_lock_stat) || (!unlock_detected))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0D) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x10, &rdata,
+ 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ *unlock_detected = (u8)((rdata & 0x10) ? 1 : 0);
+ *sync_stat = (u8)(rdata & 0x07);
+ *ts_lock_stat = (u8)((rdata & 0x20) ? 1 : 0);
+
+ if (*sync_stat == 0x07)
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_sync_stat_sub(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *sync_stat,
+ u8 *unlock_detected)
+{
+ u8 ts_lock_stat = 0;
+
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!sync_stat) || (!unlock_detected))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ ret =
+ cxd2880_tnrdmd_dvbt_mon_sync_stat(tnr_dmd->diver_sub, sync_stat,
+ &ts_lock_stat, unlock_detected);
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_mode_guard(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dvbt_mode
+ *mode,
+ enum cxd2880_dvbt_guard
+ *guard)
+{
+ u8 rdata = 0x00;
+
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!mode) || (!guard))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret = is_tps_locked(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
+ ret =
+ cxd2880_tnrdmd_dvbt_mon_mode_guard(
+ tnr_dmd->diver_sub, mode, guard);
+
+ return ret;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0D) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x1B, &rdata,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ *mode = (enum cxd2880_dvbt_mode)((rdata >> 2) & 0x03);
+ *guard = (enum cxd2880_dvbt_guard)(rdata & 0x03);
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_carrier_offset(struct cxd2880_tnrdmd
+ *tnr_dmd, int *offset)
+{
+ u8 rdata[4];
+ u32 ctl_val = 0;
+
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!offset))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret = is_tps_locked(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return ret;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0D) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x1D, rdata,
+ 4) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ ctl_val =
+ ((rdata[0] & 0x1F) << 24) | (rdata[1] << 16) | (rdata[2] << 8) |
+ (rdata[3]);
+ *offset = cxd2880_convert2s_complement(ctl_val, 29);
+ *offset = -1 * ((*offset) * (u8)tnr_dmd->bandwidth / 235);
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_carrier_offset_sub(struct
+ cxd2880_tnrdmd
+ *tnr_dmd,
+ int *offset)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!offset))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ ret =
+ cxd2880_tnrdmd_dvbt_mon_carrier_offset(tnr_dmd->diver_sub, offset);
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_pre_viterbiber(struct cxd2880_tnrdmd
+ *tnr_dmd, u32 *ber)
+{
+ u8 rdata[2];
+ u32 bit_error = 0;
+ u32 period = 0;
+
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!ber))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x10) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x39, rdata,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if ((rdata[0] & 0x01) == 0) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x22, rdata,
+ 2) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ bit_error = (rdata[0] << 8) | rdata[1];
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x6F, rdata,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ period = ((rdata[0] & 0x07) == 0) ? 256 : (0x1000 << (rdata[0] & 0x07));
+
+ if ((period == 0) || (bit_error > period))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ {
+ u32 div = 0;
+ u32 Q = 0;
+ u32 R = 0;
+
+ div = period / 128;
+
+ Q = (bit_error * 3125) / div;
+ R = (bit_error * 3125) % div;
+
+ R *= 25;
+ Q = Q * 25 + R / div;
+ R = R % div;
+
+ if (div / 2 <= R)
+ *ber = Q + 1;
+ else
+ *ber = Q;
+ }
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_pre_rsber(struct cxd2880_tnrdmd
+ *tnr_dmd, u32 *ber)
+{
+ u8 rdata[3];
+ u32 bit_error = 0;
+ u32 period_exp = 0;
+
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!ber))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0D) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x15, rdata,
+ 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if ((rdata[0] & 0x40) == 0)
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ bit_error = ((rdata[0] & 0x3F) << 16) | (rdata[1] << 8) | rdata[2];
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x10) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x60, rdata,
+ 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ period_exp = (rdata[0] & 0x1F);
+
+ if ((period_exp <= 11) && (bit_error > (1U << period_exp) * 204 * 8))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ {
+ u32 div = 0;
+ u32 Q = 0;
+ u32 R = 0;
+
+ if (period_exp <= 8)
+ div = (1U << period_exp) * 51;
+ else
+ div = (1U << 8) * 51;
+
+ Q = (bit_error * 250) / div;
+ R = (bit_error * 250) % div;
+
+ R *= 1250;
+ Q = Q * 1250 + R / div;
+ R = R % div;
+
+ if (period_exp > 8) {
+ *ber =
+ (Q + (1 << (period_exp - 9))) >> (period_exp - 8);
+ } else {
+ if (div / 2 <= R)
+ *ber = Q + 1;
+ else
+ *ber = Q;
+ }
+ }
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_tps_info(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ struct cxd2880_dvbt_tpsinfo
+ *info)
+{
+ u8 rdata[7];
+ u8 cell_id_ok = 0;
+
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!info))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret = is_tps_locked(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
+ ret =
+ cxd2880_tnrdmd_dvbt_mon_tps_info(tnr_dmd->diver_sub,
+ info);
+
+ return ret;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0D) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x29, rdata,
+ 7) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x11) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xD5, &cell_id_ok,
+ 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ info->constellation =
+ (enum cxd2880_dvbt_constellation)((rdata[0] >> 6) & 0x03);
+ info->hierarchy = (enum cxd2880_dvbt_hierarchy)((rdata[0] >> 3) & 0x07);
+ info->rate_hp = (enum cxd2880_dvbt_coderate)(rdata[0] & 0x07);
+ info->rate_lp = (enum cxd2880_dvbt_coderate)((rdata[1] >> 5) & 0x07);
+ info->guard = (enum cxd2880_dvbt_guard)((rdata[1] >> 3) & 0x03);
+ info->mode = (enum cxd2880_dvbt_mode)((rdata[1] >> 1) & 0x03);
+ info->fnum = (rdata[2] >> 6) & 0x03;
+ info->length_indicator = rdata[2] & 0x3F;
+ info->cell_id = (u16)((rdata[3] << 8) | rdata[4]);
+ info->reserved_even = rdata[5] & 0x3F;
+ info->reserved_odd = rdata[6] & 0x3F;
+
+ info->cell_id_ok = cell_id_ok & 0x01;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_packet_error_number(struct
+ cxd2880_tnrdmd
+ *tnr_dmd,
+ u32 *pen)
+{
+ u8 rdata[3];
+
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!pen))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0D) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x26, rdata,
+ 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (!(rdata[0] & 0x01))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ *pen = (rdata[1] << 8) | rdata[2];
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_spectrum_sense(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_tnrdmd_spectrum_sense
+ *sense)
+{
+ u8 data = 0;
+
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!sense))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret = is_tps_locked(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
+ ret =
+ cxd2880_tnrdmd_dvbt_mon_spectrum_sense(
+ tnr_dmd->diver_sub, sense);
+
+ return ret;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0D) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x1C, &data,
+ sizeof(data)) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ *sense =
+ (data & 0x01) ? CXD2880_TNRDMD_SPECTRUM_INV :
+ CXD2880_TNRDMD_SPECTRUM_NORMAL;
+
+ return ret;
+}
+
+static enum cxd2880_ret dvbt_read_snr_reg(struct cxd2880_tnrdmd *tnr_dmd,
+ u16 *reg_value)
+{
+ u8 rdata[2];
+
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!reg_value))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret = is_tps_locked(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return ret;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0D) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x13, rdata,
+ 2) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ *reg_value = (rdata[0] << 8) | rdata[1];
+
+ return ret;
+}
+
+static enum cxd2880_ret dvbt_calc_snr(struct cxd2880_tnrdmd *tnr_dmd,
+ u32 reg_value, int *snr)
+{
+ if ((!tnr_dmd) || (!snr))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (reg_value == 0)
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ if (reg_value > 4996)
+ reg_value = 4996;
+
+ *snr =
+ 10 * 10 * ((int)cxd2880_math_log10(reg_value) -
+ (int)cxd2880_math_log10(5350 - reg_value));
+ *snr += 28500;
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_snr(struct cxd2880_tnrdmd *tnr_dmd,
+ int *snr)
+{
+ u16 reg_value = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!snr))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ *snr = -1000 * 1000;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
+ ret = dvbt_read_snr_reg(tnr_dmd, ®_value);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret = dvbt_calc_snr(tnr_dmd, reg_value, snr);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ } else {
+ int snr_main = 0;
+ int snr_sub = 0;
+
+ ret =
+ cxd2880_tnrdmd_dvbt_mon_snr_diver(tnr_dmd, snr, &snr_main,
+ &snr_sub);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ }
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_snr_diver(struct cxd2880_tnrdmd
+ *tnr_dmd, int *snr,
+ int *snr_main, int *snr_sub)
+{
+ u16 reg_value = 0;
+ u32 reg_value_sum = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!snr) || (!snr_main) || (!snr_sub))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ *snr = -1000 * 1000;
+ *snr_main = -1000 * 1000;
+ *snr_sub = -1000 * 1000;
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = dvbt_read_snr_reg(tnr_dmd, ®_value);
+ if (ret == CXD2880_RESULT_OK) {
+ ret = dvbt_calc_snr(tnr_dmd, reg_value, snr_main);
+ if (ret != CXD2880_RESULT_OK)
+ reg_value = 0;
+ } else if (ret == CXD2880_RESULT_ERROR_HW_STATE) {
+ reg_value = 0;
+ } else {
+ return ret;
+ }
+
+ reg_value_sum += reg_value;
+
+ ret = dvbt_read_snr_reg(tnr_dmd->diver_sub, ®_value);
+ if (ret == CXD2880_RESULT_OK) {
+ ret = dvbt_calc_snr(tnr_dmd->diver_sub, reg_value, snr_sub);
+ if (ret != CXD2880_RESULT_OK)
+ reg_value = 0;
+ } else if (ret == CXD2880_RESULT_ERROR_HW_STATE) {
+ reg_value = 0;
+ } else {
+ return ret;
+ }
+
+ reg_value_sum += reg_value;
+
+ ret = dvbt_calc_snr(tnr_dmd, reg_value_sum, snr);
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_sampling_offset(struct cxd2880_tnrdmd
+ *tnr_dmd, int *ppm)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!ppm))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 ctl_val_reg[5];
+ u8 nominal_rate_reg[5];
+ u32 trl_ctl_val = 0;
+ u32 trcg_nominal_rate = 0;
+ int num;
+ int den;
+ s8 diff_upper = 0;
+
+ if (slvt_freeze_reg(tnr_dmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ ret = is_tps_locked(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return ret;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0D) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x21,
+ ctl_val_reg,
+ sizeof(ctl_val_reg)) !=
+ CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x04) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x60,
+ nominal_rate_reg,
+ sizeof(nominal_rate_reg)) !=
+ CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnr_dmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnr_dmd);
+
+ diff_upper =
+ (ctl_val_reg[0] & 0x7F) - (nominal_rate_reg[0] & 0x7F);
+
+ if ((diff_upper < -1) || (diff_upper > 1))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ trl_ctl_val = ctl_val_reg[1] << 24;
+ trl_ctl_val |= ctl_val_reg[2] << 16;
+ trl_ctl_val |= ctl_val_reg[3] << 8;
+ trl_ctl_val |= ctl_val_reg[4];
+
+ trcg_nominal_rate = nominal_rate_reg[1] << 24;
+ trcg_nominal_rate |= nominal_rate_reg[2] << 16;
+ trcg_nominal_rate |= nominal_rate_reg[3] << 8;
+ trcg_nominal_rate |= nominal_rate_reg[4];
+
+ trl_ctl_val >>= 1;
+ trcg_nominal_rate >>= 1;
+
+ if (diff_upper == 1)
+ num =
+ (int)((trl_ctl_val + 0x80000000u) -
+ trcg_nominal_rate);
+ else if (diff_upper == -1)
+ num =
+ -(int)((trcg_nominal_rate + 0x80000000u) -
+ trl_ctl_val);
+ else
+ num = (int)(trl_ctl_val - trcg_nominal_rate);
+
+ den = (nominal_rate_reg[0] & 0x7F) << 24;
+ den |= nominal_rate_reg[1] << 16;
+ den |= nominal_rate_reg[2] << 8;
+ den |= nominal_rate_reg[3];
+ den = (den + (390625 / 2)) / 390625;
+
+ den >>= 1;
+
+ if (num >= 0)
+ *ppm = (num + (den / 2)) / den;
+ else
+ *ppm = (num - (den / 2)) / den;
+ }
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_sampling_offset_sub(struct
+ cxd2880_tnrdmd
+ *tnr_dmd, int *ppm)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!ppm))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ ret = cxd2880_tnrdmd_dvbt_mon_sampling_offset(tnr_dmd->diver_sub, ppm);
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_quality(struct cxd2880_tnrdmd *tnr_dmd,
+ u8 *quality)
+{
+ struct cxd2880_dvbt_tpsinfo tps;
+ enum cxd2880_dvbt_profile profile = CXD2880_DVBT_PROFILE_HP;
+ u32 ber = 0;
+ int sn = 0;
+ int sn_rel = 0;
+ int ber_sqi = 0;
+
+ static const int nordig_non_hdvbt_db_1000[3][5] = {
+ {5100, 6900, 7900, 8900, 9700},
+ {10800, 13100, 14600, 15600, 16000},
+ {16500, 18700, 20200, 21600, 22500}
+ };
+
+ static const int nordig_hier_hp_dvbt_db_1000[3][2][5] = {
+ {
+ {9100, 12000, 13600, 15000, 16600},
+ {10900, 14100, 15700, 19400, 20600}
+ },
+ {
+ {6800, 9100, 10400, 11900, 12700},
+ {8500, 11000, 12800, 15000, 16000}
+ },
+ {
+ {5800, 7900, 9100, 10300, 12100},
+ {8000, 9300, 11600, 13000, 12900}
+ }
+ };
+
+ static const int nordig_hier_lp_dvbt_db_1000[3][2][5] = {
+ {
+ {12500, 14300, 15300, 16300, 16900},
+ {16700, 19100, 20900, 22500, 23700}
+ },
+ {
+ {15000, 17200, 18400, 19100, 20100},
+ {18500, 21200, 23600, 24700, 25900}
+ },
+ {
+ {19500, 21400, 22500, 23700, 24700},
+ {21900, 24200, 25600, 26900, 27800}
+ }
+ };
+
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!quality))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = cxd2880_tnrdmd_dvbt_mon_tps_info(tnr_dmd, &tps);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (tps.hierarchy != CXD2880_DVBT_HIERARCHY_NON) {
+ u8 data = 0;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x10) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x67, &data,
+ 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ profile =
+ ((data & 0x01) ==
+ 0x01) ? CXD2880_DVBT_PROFILE_LP : CXD2880_DVBT_PROFILE_HP;
+ }
+
+ ret = cxd2880_tnrdmd_dvbt_mon_pre_rsber(tnr_dmd, &ber);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret = cxd2880_tnrdmd_dvbt_mon_snr(tnr_dmd, &sn);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if ((tps.constellation >= CXD2880_DVBT_CONSTELLATION_RESERVED_3) ||
+ (tps.rate_hp >= CXD2880_DVBT_CODERATE_RESERVED_5) ||
+ (tps.rate_lp >= CXD2880_DVBT_CODERATE_RESERVED_5) ||
+ (tps.hierarchy > CXD2880_DVBT_HIERARCHY_4)) {
+ return CXD2880_RESULT_ERROR_OTHER;
+ }
+
+ if ((tps.hierarchy != CXD2880_DVBT_HIERARCHY_NON) &&
+ (tps.constellation == CXD2880_DVBT_CONSTELLATION_QPSK))
+ return CXD2880_RESULT_ERROR_OTHER;
+
+ if (tps.hierarchy == CXD2880_DVBT_HIERARCHY_NON)
+ sn_rel =
+ sn -
+ nordig_non_hdvbt_db_1000[tps.constellation][tps.rate_hp];
+ else if (profile == CXD2880_DVBT_PROFILE_LP)
+ sn_rel =
+ sn - nordig_hier_lp_dvbt_db_1000[(int)tps.hierarchy -
+ 1][(int)tps.constellation -
+ 1][tps.rate_lp];
+ else
+ sn_rel =
+ sn - nordig_hier_hp_dvbt_db_1000[(int)tps.hierarchy -
+ 1][(int)tps.constellation -
+ 1][tps.rate_hp];
+
+ if (ber > 10000) {
+ ber_sqi = 0;
+ } else if (ber > 1) {
+ ber_sqi = (int)(10 * cxd2880_math_log10(ber));
+ ber_sqi = 20 * (7 * 1000 - (ber_sqi)) - 40 * 1000;
+ } else {
+ ber_sqi = 100 * 1000;
+ }
+
+ if (sn_rel < -7 * 1000) {
+ *quality = 0;
+ } else if (sn_rel < 3 * 1000) {
+ int tmp_sqi = (((sn_rel - (3 * 1000)) / 10) + 1000);
+ *quality =
+ (u8)(((tmp_sqi * ber_sqi) +
+ (1000000 / 2)) / (1000000)) & 0xFF;
+ } else {
+ *quality = (u8)((ber_sqi + 500) / 1000);
+ }
+
+ if (*quality > 100)
+ *quality = 100;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_per(struct cxd2880_tnrdmd *tnr_dmd,
+ u32 *per)
+{
+ u32 packet_error = 0;
+ u32 period = 0;
+ u8 rdata[3];
+
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!per))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x0D) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x18, rdata,
+ 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if ((rdata[0] & 0x01) == 0)
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ packet_error = (rdata[1] << 8) | rdata[2];
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x10) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->read_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x5C, rdata,
+ 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ period = 1U << (rdata[0] & 0x0F);
+
+ if ((period == 0) || (packet_error > period))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ {
+ u32 div = 0;
+ u32 Q = 0;
+ u32 R = 0;
+
+ div = period;
+
+ Q = (packet_error * 1000) / div;
+ R = (packet_error * 1000) % div;
+
+ R *= 1000;
+ Q = Q * 1000 + R / div;
+ R = R % div;
+
+ if ((div != 1) && (div / 2 <= R))
+ *per = Q + 1;
+ else
+ *per = Q;
+ }
+
+ return ret;
+}
+
+static enum cxd2880_ret dvbt_calc_ssi(struct cxd2880_tnrdmd *tnr_dmd,
+ int rf_lvl, u8 *ssi)
+{
+ struct cxd2880_dvbt_tpsinfo tps;
+ int prel;
+ int temp_ssi = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ static const int ref_dbm_1000[3][5] = {
+ {-93000, -91000, -90000, -89000, -88000},
+ {-87000, -85000, -84000, -83000, -82000},
+ {-82000, -80000, -78000, -77000, -76000},
+ };
+
+ if ((!tnr_dmd) || (!ssi))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ ret = cxd2880_tnrdmd_dvbt_mon_tps_info(tnr_dmd, &tps);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if ((tps.constellation >= CXD2880_DVBT_CONSTELLATION_RESERVED_3) ||
+ (tps.rate_hp >= CXD2880_DVBT_CODERATE_RESERVED_5))
+ return CXD2880_RESULT_ERROR_OTHER;
+
+ prel = rf_lvl - ref_dbm_1000[tps.constellation][tps.rate_hp];
+
+ if (prel < -15000)
+ temp_ssi = 0;
+ else if (prel < 0)
+ temp_ssi = ((2 * (prel + 15000)) + 1500) / 3000;
+ else if (prel < 20000)
+ temp_ssi = (((4 * prel) + 500) / 1000) + 10;
+ else if (prel < 35000)
+ temp_ssi = (((2 * (prel - 20000)) + 1500) / 3000) + 90;
+ else
+ temp_ssi = 100;
+
+ *ssi = (temp_ssi > 100) ? 100 : (u8)temp_ssi;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_ssi(struct cxd2880_tnrdmd *tnr_dmd,
+ u8 *ssi)
+{
+ int rf_lvl = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!ssi))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = cxd2880_tnrdmd_mon_rf_lvl(tnr_dmd, &rf_lvl);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret = dvbt_calc_ssi(tnr_dmd, rf_lvl, ssi);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_ssi_sub(struct cxd2880_tnrdmd *tnr_dmd,
+ u8 *ssi)
+{
+ int rf_lvl = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!ssi))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = cxd2880_tnrdmd_mon_rf_lvl(tnr_dmd->diver_sub, &rf_lvl);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret = dvbt_calc_ssi(tnr_dmd, rf_lvl, ssi);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ return ret;
+}
+
+static enum cxd2880_ret is_tps_locked(struct cxd2880_tnrdmd *tnr_dmd)
+{
+ u8 sync = 0;
+ u8 tslock = 0;
+ u8 early_unlock = 0;
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ ret =
+ cxd2880_tnrdmd_dvbt_mon_sync_stat(tnr_dmd, &sync, &tslock,
+ &early_unlock);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (sync != 6)
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ return CXD2880_RESULT_OK;
+}
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.h b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.h
new file mode 100644
index 000000000000..486fc466272e
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.h
@@ -0,0 +1,106 @@
+/*
+ * cxd2880_tnrdmd_dvbt_mon.h
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * DVB-T monitor interface
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CXD2880_TNRDMD_DVBT_MON_H
+#define CXD2880_TNRDMD_DVBT_MON_H
+
+#include "cxd2880_tnrdmd.h"
+#include "cxd2880_dvbt.h"
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_sync_stat(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *sync_stat,
+ u8 *ts_lock_stat,
+ u8 *unlock_detected);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_sync_stat_sub(struct cxd2880_tnrdmd
+ *tnr_dmd, u8 *sync_stat,
+ u8 *unlock_detected);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_mode_guard(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dvbt_mode
+ *mode,
+ enum cxd2880_dvbt_guard
+ *guard);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_carrier_offset(struct cxd2880_tnrdmd
+ *tnr_dmd, int *offset);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_carrier_offset_sub(struct
+ cxd2880_tnrdmd
+ *tnr_dmd,
+ int *offset);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_pre_viterbiber(struct cxd2880_tnrdmd
+ *tnr_dmd, u32 *ber);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_pre_rsber(struct cxd2880_tnrdmd
+ *tnr_dmd, u32 *ber);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_tps_info(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ struct cxd2880_dvbt_tpsinfo
+ *info);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_packet_error_number(struct
+ cxd2880_tnrdmd
+ *tnr_dmd,
+ u32 *pen);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_spectrum_sense(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_tnrdmd_spectrum_sense
+ *sense);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_snr(struct cxd2880_tnrdmd *tnr_dmd,
+ int *snr);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_snr_diver(struct cxd2880_tnrdmd
+ *tnr_dmd, int *snr,
+ int *snr_main, int *snr_sub);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_sampling_offset(struct cxd2880_tnrdmd
+ *tnr_dmd, int *ppm);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_sampling_offset_sub(struct
+ cxd2880_tnrdmd
+ *tnr_dmd,
+ int *ppm);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_quality(struct cxd2880_tnrdmd *tnr_dmd,
+ u8 *quality);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_per(struct cxd2880_tnrdmd *tnr_dmd,
+ u32 *per);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_ssi(struct cxd2880_tnrdmd *tnr_dmd,
+ u8 *ssi);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_mon_ssi_sub(struct cxd2880_tnrdmd *tnr_dmd,
+ u8 *ssi);
+
+#endif
--
2.11.0
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^ permalink raw reply related
* [PATCH v2 09/15] [media] cxd2880: Add DVB-T control functions the driver
From: Yasunari.Takiguchi-7U/KSKJipcs @ 2017-04-14 2:33 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-media-u79uwXL29TY76Z2rM5mHXA
Cc: tbird20d-Re5JQEeQqe8AvxtiuMwx3w,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, Yasunari Takiguchi,
Masayuki Yamamoto, Hideki Nozawa, Kota Yonezawa,
Toshihiko Matsumoto, Satoshi Watanabe
In-Reply-To: <20170414015043.16731-1-Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
From: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
Provide definitions, interfaces and functions needed for DVB-T
of the Sony CXD2880 DVB-T2/T tuner + demodulator driver.
Signed-off-by: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Masayuki Yamamoto <Masayuki.Yamamoto-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Hideki Nozawa <Hideki.Nozawa-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Kota Yonezawa <Kota.Yonezawa-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Toshihiko Matsumoto <Toshihiko.Matsumoto-7U/KSKJipcs@public.gmane.org>
Signed-off-by: Satoshi Watanabe <Satoshi.C.Watanabe-7U/KSKJipcs@public.gmane.org>
---
drivers/media/dvb-frontends/cxd2880/cxd2880_dvbt.h | 91 ++
.../dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt.c | 1072 ++++++++++++++++++++
.../dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt.h | 62 ++
3 files changed, 1225 insertions(+)
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_dvbt.h
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt.c
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt.h
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_dvbt.h b/drivers/media/dvb-frontends/cxd2880/cxd2880_dvbt.h
new file mode 100644
index 000000000000..345c094760d2
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_dvbt.h
@@ -0,0 +1,91 @@
+/*
+ * cxd2880_dvbt.h
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * DVB-T related definitions
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CXD2880_DVBT_H
+#define CXD2880_DVBT_H
+
+#include "cxd2880_common.h"
+
+enum cxd2880_dvbt_constellation {
+ CXD2880_DVBT_CONSTELLATION_QPSK,
+ CXD2880_DVBT_CONSTELLATION_16QAM,
+ CXD2880_DVBT_CONSTELLATION_64QAM,
+ CXD2880_DVBT_CONSTELLATION_RESERVED_3
+};
+
+enum cxd2880_dvbt_hierarchy {
+ CXD2880_DVBT_HIERARCHY_NON,
+ CXD2880_DVBT_HIERARCHY_1,
+ CXD2880_DVBT_HIERARCHY_2,
+ CXD2880_DVBT_HIERARCHY_4
+};
+
+enum cxd2880_dvbt_coderate {
+ CXD2880_DVBT_CODERATE_1_2,
+ CXD2880_DVBT_CODERATE_2_3,
+ CXD2880_DVBT_CODERATE_3_4,
+ CXD2880_DVBT_CODERATE_5_6,
+ CXD2880_DVBT_CODERATE_7_8,
+ CXD2880_DVBT_CODERATE_RESERVED_5,
+ CXD2880_DVBT_CODERATE_RESERVED_6,
+ CXD2880_DVBT_CODERATE_RESERVED_7
+};
+
+enum cxd2880_dvbt_guard {
+ CXD2880_DVBT_GUARD_1_32,
+ CXD2880_DVBT_GUARD_1_16,
+ CXD2880_DVBT_GUARD_1_8,
+ CXD2880_DVBT_GUARD_1_4
+};
+
+enum cxd2880_dvbt_mode {
+ CXD2880_DVBT_MODE_2K,
+ CXD2880_DVBT_MODE_8K,
+ CXD2880_DVBT_MODE_RESERVED_2,
+ CXD2880_DVBT_MODE_RESERVED_3
+};
+
+enum cxd2880_dvbt_profile {
+ CXD2880_DVBT_PROFILE_HP = 0,
+ CXD2880_DVBT_PROFILE_LP
+};
+
+struct cxd2880_dvbt_tpsinfo {
+ enum cxd2880_dvbt_constellation constellation;
+ enum cxd2880_dvbt_hierarchy hierarchy;
+ enum cxd2880_dvbt_coderate rate_hp;
+ enum cxd2880_dvbt_coderate rate_lp;
+ enum cxd2880_dvbt_guard guard;
+ enum cxd2880_dvbt_mode mode;
+ u8 fnum;
+ u8 length_indicator;
+ u16 cell_id;
+ u8 cell_id_ok;
+ u8 reserved_even;
+ u8 reserved_odd;
+};
+
+#endif
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt.c b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt.c
new file mode 100644
index 000000000000..f36cf533ec17
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt.c
@@ -0,0 +1,1072 @@
+/*
+ * cxd2880_tnrdmd_dvbt.c
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * control functions for DVB-T
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cxd2880_tnrdmd_dvbt.h"
+#include "cxd2880_tnrdmd_dvbt_mon.h"
+
+static enum cxd2880_ret x_tune_dvbt_demod_setting(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum cxd2880_dtv_bandwidth
+ bandwidth,
+ enum cxd2880_tnrdmd_clockmode
+ clk_mode)
+{
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_SYS, 0x00,
+ 0x00) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_SYS, 0x31,
+ 0x01) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data_a[2] = { 0x52, 0x49 };
+ u8 data_b[2] = { 0x5D, 0x55 };
+ u8 data_c[2] = { 0x60, 0x00 };
+ u8 *data = NULL;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x04) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x65, data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x5D,
+ 0x07) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_SUB) {
+ u8 data[2] = { 0x01, 0x01 };
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x00) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xCE, data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x04) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x5C,
+ 0xFB) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x10) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xA4,
+ 0x03) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x14) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xB0,
+ 0x00) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x25) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data[2] = { 0x01, 0xF0 };
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xF0, data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if ((tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) ||
+ (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)) {
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x12) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x44,
+ 0x00) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB) {
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x11) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x87,
+ 0xD2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_SUB) {
+ u8 data_a[3] = { 0x73, 0xCA, 0x49 };
+ u8 data_b[3] = { 0xC8, 0x13, 0xAA };
+ u8 data_c[3] = { 0xDC, 0x6C, 0x00 };
+ u8 *data = NULL;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x04) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x68, data,
+ 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x04) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ switch (bandwidth) {
+ case CXD2880_DTV_BW_8_MHZ:
+
+ {
+ u8 data_ac[5] = { 0x15, 0x00, 0x00, 0x00,
+ 0x00
+ };
+ u8 data_b[5] = { 0x14, 0x6A, 0xAA, 0xAA,
+ 0xAA
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_ac;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x60,
+ data,
+ 5) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4A,
+ 0x00) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data_a[2] = { 0x01, 0x28 };
+ u8 data_b[2] = { 0x11, 0x44 };
+ u8 data_c[2] = { 0x15, 0x28 };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x7D,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data = 0;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = 0x35;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = 0x34;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x71,
+ data) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ u8 data_a[5] = { 0x30, 0x00, 0x00, 0x90,
+ 0x00
+ };
+ u8 data_b[5] = { 0x36, 0x71, 0x00, 0xA3,
+ 0x55
+ };
+ u8 data_c[5] = { 0x38, 0x00, 0x00, 0xA8,
+ 0x00
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4B,
+ &data[0],
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x51,
+ &data[2],
+ 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data[4] = { 0xB3, 0x00, 0x01, 0x02 };
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x72,
+ &data[0],
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x6B,
+ &data[2],
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ break;
+
+ case CXD2880_DTV_BW_7_MHZ:
+
+ {
+ u8 data_ac[5] = { 0x18, 0x00, 0x00, 0x00,
+ 0x00
+ };
+ u8 data_b[5] = { 0x17, 0x55, 0x55, 0x55,
+ 0x55
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_ac;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x60,
+ data,
+ 5) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4A,
+ 0x02) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data_a[2] = { 0x12, 0x4C };
+ u8 data_b[2] = { 0x1F, 0x15 };
+ u8 data_c[2] = { 0x1F, 0xF8 };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x7D,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data = 0;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = 0x2F;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = 0x2E;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x71,
+ data) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ u8 data_a[5] = { 0x36, 0xDB, 0x00, 0xA4,
+ 0x92
+ };
+ u8 data_b[5] = { 0x3E, 0x38, 0x00, 0xBA,
+ 0xAA
+ };
+ u8 data_c[5] = { 0x40, 0x00, 0x00, 0xC0,
+ 0x00
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4B,
+ &data[0],
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x51,
+ &data[2],
+ 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data[4] = { 0xB8, 0x00, 0x00, 0x03 };
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x72,
+ &data[0],
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x6B,
+ &data[2],
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ break;
+
+ case CXD2880_DTV_BW_6_MHZ:
+
+ {
+ u8 data_ac[5] = { 0x1C, 0x00, 0x00, 0x00,
+ 0x00
+ };
+ u8 data_b[5] = { 0x1B, 0x38, 0xE3, 0x8E,
+ 0x38
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_ac;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x60,
+ data,
+ 5) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4A,
+ 0x04) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data_a[2] = { 0x1F, 0xF8 };
+ u8 data_b[2] = { 0x24, 0x43 };
+ u8 data_c[2] = { 0x25, 0x4C };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x7D,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data = 0;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = 0x29;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = 0x2A;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x71,
+ data) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ u8 data_a[5] = { 0x40, 0x00, 0x00, 0xC0,
+ 0x00
+ };
+ u8 data_b[5] = { 0x48, 0x97, 0x00, 0xD9,
+ 0xC7
+ };
+ u8 data_c[5] = { 0x4A, 0xAA, 0x00, 0xDF,
+ 0xFF
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4B,
+ &data[0],
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x51,
+ &data[2],
+ 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data[4] = { 0xBE, 0xAB, 0x00, 0x03 };
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x72,
+ &data[0],
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x6B,
+ &data[2],
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ break;
+
+ case CXD2880_DTV_BW_5_MHZ:
+
+ {
+ u8 data_ac[5] = { 0x21, 0x99, 0x99, 0x99,
+ 0x99
+ };
+ u8 data_b[5] = { 0x20, 0xAA, 0xAA, 0xAA,
+ 0xAA
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_ac;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x60,
+ data,
+ 5) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4A,
+ 0x06) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ {
+ u8 data_a[2] = { 0x26, 0x5D };
+ u8 data_b[2] = { 0x2B, 0x84 };
+ u8 data_c[2] = { 0x2C, 0xC2 };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x7D,
+ data,
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data = 0;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = 0x24;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = 0x23;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x71,
+ data) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ u8 data_a[5] = { 0x4C, 0xCC, 0x00, 0xE6,
+ 0x66
+ };
+ u8 data_b[5] = { 0x57, 0x1C, 0x01, 0x05,
+ 0x55
+ };
+ u8 data_c[5] = { 0x59, 0x99, 0x01, 0x0C,
+ 0xCC
+ };
+ u8 *data = NULL;
+
+ switch (clk_mode) {
+ case CXD2880_TNRDMD_CLOCKMODE_A:
+ data = data_a;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_B:
+ data = data_b;
+ break;
+ case CXD2880_TNRDMD_CLOCKMODE_C:
+ data = data_c;
+ break;
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x4B,
+ &data[0],
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x51,
+ &data[2],
+ 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ {
+ u8 data[4] = { 0xC8, 0x01, 0x00, 0x03 };
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x72,
+ &data[0],
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_regs(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x6B,
+ &data[2],
+ 2) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+ break;
+
+ default:
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ }
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x00) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xFD,
+ 0x01) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ return CXD2880_RESULT_OK;
+}
+
+static enum cxd2880_ret x_sleep_dvbt_demod_setting(struct cxd2880_tnrdmd
+ *tnr_dmd)
+{
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x04) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x5C,
+ 0xD8) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x10) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0xA4,
+ 0x00) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB) {
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x11) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x87,
+ 0x04) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+static enum cxd2880_ret dvbt_set_profile(struct cxd2880_tnrdmd *tnr_dmd,
+ enum cxd2880_dvbt_profile profile)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x00,
+ 0x10) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnr_dmd->io->write_reg(tnr_dmd->io,
+ CXD2880_IO_TGT_DMD, 0x67,
+ (profile ==
+ CXD2880_DVBT_PROFILE_HP) ? 0x00 : 0x01) !=
+ CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_tune1(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt_tune_param
+ *tune_param)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!tune_param))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if ((tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP) &&
+ (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE))
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret =
+ cxd2880_tnrdmd_common_tune_setting1(tnr_dmd, CXD2880_DTV_SYS_DVBT,
+ tune_param->center_freq_khz,
+ tune_param->bandwidth, 0, 0);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret =
+ x_tune_dvbt_demod_setting(tnr_dmd, tune_param->bandwidth,
+ tnr_dmd->clk_mode);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ ret =
+ x_tune_dvbt_demod_setting(tnr_dmd->diver_sub,
+ tune_param->bandwidth,
+ tnr_dmd->diver_sub->clk_mode);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ }
+
+ ret = dvbt_set_profile(tnr_dmd, tune_param->profile);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_tune2(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt_tune_param
+ *tune_param)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if ((!tnr_dmd) || (!tune_param))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if ((tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP) &&
+ (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE))
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret =
+ cxd2880_tnrdmd_common_tune_setting2(tnr_dmd, CXD2880_DTV_SYS_DVBT,
+ 0);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ tnr_dmd->state = CXD2880_TNRDMD_STATE_ACTIVE;
+ tnr_dmd->frequency_khz = tune_param->center_freq_khz;
+ tnr_dmd->sys = CXD2880_DTV_SYS_DVBT;
+ tnr_dmd->bandwidth = tune_param->bandwidth;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ tnr_dmd->diver_sub->state = CXD2880_TNRDMD_STATE_ACTIVE;
+ tnr_dmd->diver_sub->frequency_khz = tune_param->center_freq_khz;
+ tnr_dmd->diver_sub->sys = CXD2880_DTV_SYS_DVBT;
+ tnr_dmd->diver_sub->bandwidth = tune_param->bandwidth;
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_sleep_setting(struct cxd2880_tnrdmd
+ *tnr_dmd)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if ((tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP) &&
+ (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE))
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret = x_sleep_dvbt_demod_setting(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
+ ret = x_sleep_dvbt_demod_setting(tnr_dmd->diver_sub);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ }
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_check_demod_lock(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_tnrdmd_lock_result
+ *lock)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ u8 sync_stat = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+ u8 unlock_detected_sub = 0;
+
+ if ((!tnr_dmd) || (!lock))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret =
+ cxd2880_tnrdmd_dvbt_mon_sync_stat(tnr_dmd, &sync_stat, &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
+ if (sync_stat == 6)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
+ else if (unlock_detected)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
+ else
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+
+ return ret;
+ }
+
+ if (sync_stat == 6) {
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
+ return ret;
+ }
+
+ ret =
+ cxd2880_tnrdmd_dvbt_mon_sync_stat_sub(tnr_dmd, &sync_stat,
+ &unlock_detected_sub);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (sync_stat == 6)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
+ else if (unlock_detected && unlock_detected_sub)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
+ else
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+
+ return ret;
+}
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_check_ts_lock(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_tnrdmd_lock_result
+ *lock)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+
+ u8 sync_stat = 0;
+ u8 ts_lock = 0;
+ u8 unlock_detected = 0;
+ u8 unlock_detected_sub = 0;
+
+ if ((!tnr_dmd) || (!lock))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ ret =
+ cxd2880_tnrdmd_dvbt_mon_sync_stat(tnr_dmd, &sync_stat, &ts_lock,
+ &unlock_detected);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
+ if (ts_lock)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
+ else if (unlock_detected)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
+ else
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+
+ return ret;
+ }
+
+ if (ts_lock) {
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
+ return ret;
+ } else if (!unlock_detected) {
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+ return ret;
+ }
+
+ ret =
+ cxd2880_tnrdmd_dvbt_mon_sync_stat_sub(tnr_dmd, &sync_stat,
+ &unlock_detected_sub);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (unlock_detected && unlock_detected_sub)
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
+ else
+ *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
+
+ return ret;
+}
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt.h b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt.h
new file mode 100644
index 000000000000..de394d8e27f3
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt.h
@@ -0,0 +1,62 @@
+/*
+ * cxd2880_tnrdmd_dvbt.h
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * control interface for DVB-T
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CXD2880_TNRDMD_DVBT_H
+#define CXD2880_TNRDMD_DVBT_H
+
+#include "cxd2880_common.h"
+#include "cxd2880_tnrdmd.h"
+
+struct cxd2880_dvbt_tune_param {
+ u32 center_freq_khz;
+ enum cxd2880_dtv_bandwidth bandwidth;
+ enum cxd2880_dvbt_profile profile;
+};
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_tune1(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt_tune_param
+ *tune_param);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_tune2(struct cxd2880_tnrdmd *tnr_dmd,
+ struct cxd2880_dvbt_tune_param
+ *tune_param);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_sleep_setting(struct cxd2880_tnrdmd
+ *tnr_dmd);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_check_demod_lock(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_tnrdmd_lock_result
+ *lock);
+
+enum cxd2880_ret cxd2880_tnrdmd_dvbt_check_ts_lock(struct cxd2880_tnrdmd
+ *tnr_dmd,
+ enum
+ cxd2880_tnrdmd_lock_result
+ *lock);
+
+#endif
--
2.11.0
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^ permalink raw reply related
* [PATCH v2 08/15] [media] cxd2880: Add top level of the driver
From: Yasunari.Takiguchi @ 2017-04-14 2:31 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-media
Cc: tbird20d, frowand.list, Yasunari Takiguchi, Masayuki Yamamoto,
Hideki Nozawa, Kota Yonezawa, Toshihiko Matsumoto,
Satoshi Watanabe
In-Reply-To: <20170414015043.16731-1-Yasunari.Takiguchi@sony.com>
From: Yasunari Takiguchi <Yasunari.Takiguchi@sony.com>
This provides the main dvb frontend operation functions
for the Sony CXD2880 DVB-T2/T tuner + demodulator driver.
Signed-off-by: Yasunari Takiguchi <Yasunari.Takiguchi@sony.com>
Signed-off-by: Masayuki Yamamoto <Masayuki.Yamamoto@sony.com>
Signed-off-by: Hideki Nozawa <Hideki.Nozawa@sony.com>
Signed-off-by: Kota Yonezawa <Kota.Yonezawa@sony.com>
Signed-off-by: Toshihiko Matsumoto <Toshihiko.Matsumoto@sony.com>
Signed-off-by: Satoshi Watanabe <Satoshi.C.Watanabe@sony.com>
---
drivers/media/dvb-frontends/cxd2880/cxd2880_top.c | 1550 +++++++++++++++++++++
1 file changed, 1550 insertions(+)
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_top.c
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c b/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c
new file mode 100644
index 000000000000..66d78fb93a13
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c
@@ -0,0 +1,1550 @@
+/*
+ * cxd2880_top.c
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/spi/spi.h>
+
+#include "dvb_frontend.h"
+
+#include "cxd2880.h"
+#include "cxd2880_tnrdmd_mon.h"
+#include "cxd2880_tnrdmd_dvbt2_mon.h"
+#include "cxd2880_tnrdmd_dvbt_mon.h"
+#include "cxd2880_integ_dvbt2.h"
+#include "cxd2880_integ_dvbt.h"
+#include "cxd2880_devio_spi.h"
+#include "cxd2880_spi_device.h"
+#include "cxd2880_tnrdmd_driver_version.h"
+
+struct cxd2880_priv {
+ struct cxd2880_tnrdmd tnrdmd;
+ struct spi_device *spi;
+ struct cxd2880_io regio;
+ struct cxd2880_spi_device spi_device;
+ struct cxd2880_spi cxd2880_spi;
+ struct cxd2880_dvbt_tune_param dvbt_tune_param;
+ struct cxd2880_dvbt2_tune_param dvbt2_tune_param;
+ struct mutex *spi_mutex; /* For SPI access exclusive control */
+};
+
+/*
+ * return value conversion table
+ */
+static int return_tbl[] = {
+ 0, /* CXD2880_RESULT_OK */
+ -EINVAL, /* CXD2880_RESULT_ERROR_ARG*/
+ -EIO, /* CXD2880_RESULT_ERROR_IO */
+ -EPERM, /* CXD2880_RESULT_ERROR_SW_STATE */
+ -EBUSY, /* CXD2880_RESULT_ERROR_HW_STATE */
+ -ETIME, /* CXD2880_RESULT_ERROR_TIMEOUT */
+ -EAGAIN, /* CXD2880_RESULT_ERROR_UNLOCK */
+ -ERANGE, /* CXD2880_RESULT_ERROR_RANGE */
+ -EOPNOTSUPP, /* CXD2880_RESULT_ERROR_NOSUPPORT */
+ -ECANCELED, /* CXD2880_RESULT_ERROR_CANCEL */
+ -EPERM, /* CXD2880_RESULT_ERROR_OTHER */
+ -EOVERFLOW, /* CXD2880_RESULT_ERROR_OVERFLOW */
+ 0, /* CXD2880_RESULT_OK_CONFIRM */
+};
+
+static enum cxd2880_ret cxd2880_pre_bit_err_t(
+ struct cxd2880_tnrdmd *tnrdmd, u32 *pre_bit_err,
+ u32 *pre_bit_count)
+{
+ u8 rdata[2];
+
+ if ((!tnrdmd) || (!pre_bit_err) || (!pre_bit_count))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnrdmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x00, 0x10) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x39, rdata, 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if ((rdata[0] & 0x01) == 0) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x22, rdata, 2) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ *pre_bit_err = (rdata[0] << 8) | rdata[1];
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x6F, rdata, 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ slvt_unfreeze_reg(tnrdmd);
+
+ *pre_bit_count = ((rdata[0] & 0x07) == 0) ?
+ 256 : (0x1000 << (rdata[0] & 0x07));
+
+ return CXD2880_RESULT_OK;
+}
+
+static enum cxd2880_ret cxd2880_pre_bit_err_t2(
+ struct cxd2880_tnrdmd *tnrdmd, u32 *pre_bit_err,
+ u32 *pre_bit_count)
+{
+ u32 period_exp = 0;
+ u32 n_ldpc = 0;
+ u8 data[5];
+
+ if ((!tnrdmd) || (!pre_bit_err) || (!pre_bit_count))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (slvt_freeze_reg(tnrdmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x00, 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x3C, data, sizeof(data))
+ != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (!(data[0] & 0x01)) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+ *pre_bit_err =
+ ((data[1] & 0x0F) << 24) | (data[2] << 16) | (data[3] << 8) | data[4];
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0xA0, data, 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (((enum cxd2880_dvbt2_plp_fec)(data[0] & 0x03)) ==
+ CXD2880_DVBT2_FEC_LDPC_16K)
+ n_ldpc = 16200;
+ else
+ n_ldpc = 64800;
+ slvt_unfreeze_reg(tnrdmd);
+
+ if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x00, 0x20) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x6F, data, 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ period_exp = data[0] & 0x0F;
+
+ *pre_bit_count = (1U << period_exp) * n_ldpc;
+
+ return CXD2880_RESULT_OK;
+}
+
+static enum cxd2880_ret cxd2880_post_bit_err_t(struct cxd2880_tnrdmd *tnrdmd,
+ u32 *post_bit_err,
+ u32 *post_bit_count)
+{
+ u8 rdata[3];
+ u32 bit_error = 0;
+ u32 period_exp = 0;
+
+ if ((!tnrdmd) || (!post_bit_err) || (!post_bit_count))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x00, 0x0D) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x15, rdata, 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if ((rdata[0] & 0x40) == 0)
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ *post_bit_err = ((rdata[0] & 0x3F) << 16) | (rdata[1] << 8) | rdata[2];
+
+ if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x00, 0x10) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x60, rdata, 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ period_exp = (rdata[0] & 0x1F);
+
+ if ((period_exp <= 11) && (bit_error > (1U << period_exp) * 204 * 8))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ if (period_exp == 11)
+ *post_bit_count = 3342336;
+ else
+ *post_bit_count = (1U << period_exp) * 204 * 81;
+
+ return CXD2880_RESULT_OK;
+}
+
+static enum cxd2880_ret cxd2880_post_bit_err_t2(struct cxd2880_tnrdmd *tnrdmd,
+ u32 *post_bit_err,
+ u32 *post_bit_count)
+{
+ u32 period_exp = 0;
+ u32 n_bch = 0;
+
+ if ((!tnrdmd) || (!post_bit_err) || (!post_bit_count))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 data[3];
+ enum cxd2880_dvbt2_plp_fec plp_fec_type =
+ CXD2880_DVBT2_FEC_LDPC_16K;
+ enum cxd2880_dvbt2_plp_code_rate plp_code_rate =
+ CXD2880_DVBT2_R1_2;
+
+ static const u16 n_bch_bits_lookup[2][8] = {
+ {7200, 9720, 10800, 11880, 12600, 13320, 5400, 6480},
+ {32400, 38880, 43200, 48600, 51840, 54000, 21600, 25920}
+ };
+
+ if (slvt_freeze_reg(tnrdmd) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x00, 0x0B) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x15, data, 3) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ if (!(data[0] & 0x40)) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_HW_STATE;
+ }
+
+ *post_bit_err =
+ ((data[0] & 0x3F) << 16) | (data[1] << 8) | data[2];
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x9D, data, 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ plp_code_rate =
+ (enum cxd2880_dvbt2_plp_code_rate)(data[0] & 0x07);
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0xA0, data, 1) != CXD2880_RESULT_OK) {
+ slvt_unfreeze_reg(tnrdmd);
+ return CXD2880_RESULT_ERROR_IO;
+ }
+
+ plp_fec_type = (enum cxd2880_dvbt2_plp_fec)(data[0] & 0x03);
+
+ slvt_unfreeze_reg(tnrdmd);
+
+ if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x00, 0x20) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x72, data, 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ period_exp = data[0] & 0x0F;
+
+ if ((plp_fec_type > CXD2880_DVBT2_FEC_LDPC_64K) ||
+ (plp_code_rate > CXD2880_DVBT2_R2_5))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ n_bch = n_bch_bits_lookup[plp_fec_type][plp_code_rate];
+ }
+
+ if (*post_bit_err > ((1U << period_exp) * n_bch))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ *post_bit_count = (1U << period_exp) * n_bch;
+
+ return CXD2880_RESULT_OK;
+}
+
+static enum cxd2880_ret cxd2880_read_block_err_t(
+ struct cxd2880_tnrdmd *tnrdmd,
+ u32 *block_err,
+ u32 *block_count)
+{
+ u8 rdata[3];
+
+ if ((!tnrdmd) || (!block_err) || (!block_count))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x00, 0x0D) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x18, rdata, 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if ((rdata[0] & 0x01) == 0)
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ *block_err = (rdata[1] << 8) | rdata[2];
+
+ if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x00, 0x10) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x5C, rdata, 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ *block_count = 1U << (rdata[0] & 0x0F);
+
+ if ((*block_count == 0) || (*block_err > *block_count))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ return CXD2880_RESULT_OK;
+}
+
+static enum cxd2880_ret cxd2880_read_block_err_t2(
+ struct cxd2880_tnrdmd *tnrdmd,
+ u32 *block_err,
+ u32 *block_count)
+{
+ if ((!tnrdmd) || (!block_err) || (!block_count))
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+ if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
+ return CXD2880_RESULT_ERROR_SW_STATE;
+
+ {
+ u8 rdata[3];
+
+ if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x00, 0x0B) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x18, rdata, 3) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if ((rdata[0] & 0x01) == 0)
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ *block_err = (rdata[1] << 8) | rdata[2];
+
+ if (tnrdmd->io->write_reg(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0x00, 0x24) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ if (tnrdmd->io->read_regs(tnrdmd->io, CXD2880_IO_TGT_DMD,
+ 0xDC, rdata, 1) != CXD2880_RESULT_OK)
+ return CXD2880_RESULT_ERROR_IO;
+
+ *block_count = 1U << (rdata[0] & 0x0F);
+ }
+
+ if ((*block_count == 0) || (*block_err > *block_count))
+ return CXD2880_RESULT_ERROR_HW_STATE;
+
+ return CXD2880_RESULT_OK;
+}
+
+static void cxd2880_release(struct dvb_frontend *fe)
+{
+ struct cxd2880_priv *priv = NULL;
+
+ if (!fe) {
+ pr_err("%s: invalid arg.\n", __func__);
+ return;
+ }
+ priv = (struct cxd2880_priv *)fe->demodulator_priv;
+ kfree(priv);
+}
+
+static int cxd2880_init(struct dvb_frontend *fe)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ struct cxd2880_priv *priv = NULL;
+ struct cxd2880_tnrdmd_create_param create_param;
+
+ if (!fe) {
+ pr_err("%s: invalid arg.\n", __func__);
+ return -EINVAL;
+ }
+
+ priv = (struct cxd2880_priv *)fe->demodulator_priv;
+
+ create_param.ts_output_if = CXD2880_TNRDMD_TSOUT_IF_SPI;
+ create_param.xtal_share_type = CXD2880_TNRDMD_XTAL_SHARE_NONE;
+ create_param.en_internal_ldo = 1;
+ create_param.xosc_cap = 18;
+ create_param.xosc_i = 8;
+ create_param.stationary_use = 1;
+
+ mutex_lock(priv->spi_mutex);
+ if (priv->tnrdmd.io != &priv->regio) {
+ ret = cxd2880_tnrdmd_create(&priv->tnrdmd,
+ &priv->regio, &create_param);
+ if (ret != CXD2880_RESULT_OK) {
+ mutex_unlock(priv->spi_mutex);
+ dev_info(&priv->spi->dev,
+ "%s: cxd2880 tnrdmd create failed %d\n",
+ __func__, ret);
+ return return_tbl[ret];
+ }
+ }
+ ret = cxd2880_integ_init(&priv->tnrdmd);
+ if (ret != CXD2880_RESULT_OK) {
+ mutex_unlock(priv->spi_mutex);
+ dev_err(&priv->spi->dev, "%s: cxd2880 integ init failed %d\n",
+ __func__, ret);
+ return return_tbl[ret];
+ }
+ mutex_unlock(priv->spi_mutex);
+
+ dev_dbg(&priv->spi->dev, "%s: OK.\n", __func__);
+
+ return return_tbl[ret];
+}
+
+static int cxd2880_sleep(struct dvb_frontend *fe)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ struct cxd2880_priv *priv = NULL;
+
+ if (!fe) {
+ pr_err("%s: inavlid arg\n", __func__);
+ return -EINVAL;
+ }
+
+ priv = (struct cxd2880_priv *)fe->demodulator_priv;
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_tnrdmd_sleep(&priv->tnrdmd);
+ mutex_unlock(priv->spi_mutex);
+
+ dev_dbg(&priv->spi->dev, "%s: tnrdmd_sleep ret %d\n",
+ __func__, ret);
+
+ return return_tbl[ret];
+}
+
+static int cxd2880_read_signal_strength(struct dvb_frontend *fe,
+ u16 *strength)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ struct cxd2880_priv *priv = NULL;
+ struct dtv_frontend_properties *c = NULL;
+ int level = 0;
+
+ if ((!fe) || (!strength)) {
+ pr_err("%s: inavlid arg\n", __func__);
+ return -EINVAL;
+ }
+
+ priv = (struct cxd2880_priv *)fe->demodulator_priv;
+ c = &fe->dtv_property_cache;
+
+ mutex_lock(priv->spi_mutex);
+ if ((c->delivery_system == SYS_DVBT) ||
+ (c->delivery_system == SYS_DVBT2)) {
+ ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &level);
+ } else {
+ dev_dbg(&priv->spi->dev, "%s: invalid system\n", __func__);
+ mutex_unlock(priv->spi_mutex);
+ return -EINVAL;
+ }
+ mutex_unlock(priv->spi_mutex);
+
+ level /= 125;
+ /* -105dBm - -30dBm (-105000/125 = -840, -30000/125 = -240 */
+ level = clamp(level, -840, -240);
+ /* scale value to 0x0000-0xFFFF */
+ *strength = (u16)(((level + 840) * 0xFFFF) / (-240 + 840));
+
+ if (ret != CXD2880_RESULT_OK)
+ dev_dbg(&priv->spi->dev, "%s: ret = %d\n", __func__, ret);
+
+ return return_tbl[ret];
+}
+
+static int cxd2880_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ int snrvalue = 0;
+ struct cxd2880_priv *priv = NULL;
+ struct dtv_frontend_properties *c = NULL;
+
+ if ((!fe) || (!snr)) {
+ pr_err("%s: inavlid arg\n", __func__);
+ return -EINVAL;
+ }
+
+ priv = (struct cxd2880_priv *)fe->demodulator_priv;
+ c = &fe->dtv_property_cache;
+
+ mutex_lock(priv->spi_mutex);
+ if (c->delivery_system == SYS_DVBT) {
+ ret = cxd2880_tnrdmd_dvbt_mon_snr(&priv->tnrdmd,
+ &snrvalue);
+ } else if (c->delivery_system == SYS_DVBT2) {
+ ret = cxd2880_tnrdmd_dvbt2_mon_snr(&priv->tnrdmd,
+ &snrvalue);
+ } else {
+ dev_err(&priv->spi->dev, "%s: invalid system\n", __func__);
+ mutex_unlock(priv->spi_mutex);
+ return -EINVAL;
+ }
+ mutex_unlock(priv->spi_mutex);
+
+ if (snrvalue < 0)
+ snrvalue = 0;
+ *snr = (u16)snrvalue;
+
+ if (ret != CXD2880_RESULT_OK)
+ dev_dbg(&priv->spi->dev, "%s: ret = %d\n", __func__, ret);
+
+ return return_tbl[ret];
+}
+
+static int cxd2880_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ struct cxd2880_priv *priv = NULL;
+ struct dtv_frontend_properties *c = NULL;
+
+ if ((!fe) || (!ucblocks)) {
+ pr_err("%s: inavlid arg\n", __func__);
+ return -EINVAL;
+ }
+
+ priv = (struct cxd2880_priv *)fe->demodulator_priv;
+ c = &fe->dtv_property_cache;
+
+ mutex_lock(priv->spi_mutex);
+ if (c->delivery_system == SYS_DVBT) {
+ ret = cxd2880_tnrdmd_dvbt_mon_packet_error_number(
+ &priv->tnrdmd,
+ ucblocks);
+ } else if (c->delivery_system == SYS_DVBT2) {
+ ret = cxd2880_tnrdmd_dvbt2_mon_packet_error_number(
+ &priv->tnrdmd,
+ ucblocks);
+ } else {
+ dev_err(&priv->spi->dev, "%s: invlaid system\n", __func__);
+ mutex_unlock(priv->spi_mutex);
+ return -EINVAL;
+ }
+ mutex_unlock(priv->spi_mutex);
+
+ if (ret != CXD2880_RESULT_OK)
+ dev_dbg(&priv->spi->dev, "%s: ret = %d\n", __func__, ret);
+
+ return return_tbl[ret];
+}
+
+static int cxd2880_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ struct cxd2880_priv *priv = NULL;
+ struct dtv_frontend_properties *c = NULL;
+
+ if ((!fe) || (!ber)) {
+ pr_err("%s: inavlid arg\n", __func__);
+ return -EINVAL;
+ }
+
+ priv = (struct cxd2880_priv *)fe->demodulator_priv;
+ c = &fe->dtv_property_cache;
+
+ mutex_lock(priv->spi_mutex);
+ if (c->delivery_system == SYS_DVBT) {
+ ret = cxd2880_tnrdmd_dvbt_mon_pre_rsber(&priv->tnrdmd,
+ ber);
+ /* x100 to change unit.(10^7 -> 10^9 */
+ *ber *= 100;
+ } else if (c->delivery_system == SYS_DVBT2) {
+ ret = cxd2880_tnrdmd_dvbt2_mon_pre_bchber(&priv->tnrdmd,
+ ber);
+ } else {
+ dev_err(&priv->spi->dev, "%s: invlaid system\n", __func__);
+ mutex_unlock(priv->spi_mutex);
+ return -EINVAL;
+ }
+ mutex_unlock(priv->spi_mutex);
+
+ if (ret != CXD2880_RESULT_OK)
+ dev_dbg(&priv->spi->dev, "%s: ret = %d\n", __func__, ret);
+
+ return return_tbl[ret];
+}
+
+static int cxd2880_set_frontend(struct dvb_frontend *fe)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ struct dtv_frontend_properties *c;
+ struct cxd2880_priv *priv;
+ enum cxd2880_dtv_bandwidth bw = CXD2880_DTV_BW_1_7_MHZ;
+
+ if (!fe) {
+ pr_err("%s: inavlid arg\n", __func__);
+ return -EINVAL;
+ }
+
+ priv = (struct cxd2880_priv *)fe->demodulator_priv;
+ c = &fe->dtv_property_cache;
+
+ switch (c->bandwidth_hz) {
+ case 1712000:
+ bw = CXD2880_DTV_BW_1_7_MHZ;
+ break;
+ case 5000000:
+ bw = CXD2880_DTV_BW_5_MHZ;
+ break;
+ case 6000000:
+ bw = CXD2880_DTV_BW_6_MHZ;
+ break;
+ case 7000000:
+ bw = CXD2880_DTV_BW_7_MHZ;
+ break;
+ case 8000000:
+ bw = CXD2880_DTV_BW_8_MHZ;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ dev_info(&priv->spi->dev, "%s: sys:%d freq:%d bw:%d\n", __func__,
+ c->delivery_system, c->frequency, bw);
+ mutex_lock(priv->spi_mutex);
+ if (c->delivery_system == SYS_DVBT) {
+ priv->tnrdmd.sys = CXD2880_DTV_SYS_DVBT;
+ priv->dvbt_tune_param.center_freq_khz = c->frequency / 1000;
+ priv->dvbt_tune_param.bandwidth = bw;
+ priv->dvbt_tune_param.profile = CXD2880_DVBT_PROFILE_HP;
+ ret = cxd2880_integ_dvbt_tune(&priv->tnrdmd,
+ &priv->dvbt_tune_param);
+ } else if (c->delivery_system == SYS_DVBT2) {
+ priv->tnrdmd.sys = CXD2880_DTV_SYS_DVBT2;
+ priv->dvbt2_tune_param.center_freq_khz = c->frequency / 1000;
+ priv->dvbt2_tune_param.bandwidth = bw;
+ priv->dvbt2_tune_param.data_plp_id = (u16)c->stream_id;
+ ret = cxd2880_integ_dvbt2_tune(&priv->tnrdmd,
+ &priv->dvbt2_tune_param);
+ } else {
+ dev_err(&priv->spi->dev, "%s: invalid system\n", __func__);
+ mutex_unlock(priv->spi_mutex);
+ return -EINVAL;
+ }
+ mutex_unlock(priv->spi_mutex);
+ dev_info(&priv->spi->dev, "%s: tune result %d\n", __func__, ret);
+
+ return return_tbl[ret];
+}
+
+static int cxd2880_read_status(struct dvb_frontend *fe,
+ enum fe_status *status)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ u8 sync = 0;
+ u8 lock = 0;
+ u8 unlock = 0;
+ struct cxd2880_priv *priv = NULL;
+ struct dtv_frontend_properties *c = NULL;
+
+ if ((!fe) || (!status)) {
+ pr_err("%s: invalid arg\n", __func__);
+ return -EINVAL;
+ }
+
+ priv = (struct cxd2880_priv *)fe->demodulator_priv;
+ c = &fe->dtv_property_cache;
+ *status = 0;
+
+ if (priv->tnrdmd.state == CXD2880_TNRDMD_STATE_ACTIVE) {
+ mutex_lock(priv->spi_mutex);
+ if (c->delivery_system == SYS_DVBT) {
+ ret = cxd2880_tnrdmd_dvbt_mon_sync_stat(
+ &priv->tnrdmd,
+ &sync,
+ &lock,
+ &unlock);
+ } else if (c->delivery_system == SYS_DVBT2) {
+ ret = cxd2880_tnrdmd_dvbt2_mon_sync_stat(
+ &priv->tnrdmd,
+ &sync,
+ &lock,
+ &unlock);
+ } else {
+ dev_err(&priv->spi->dev,
+ "%s: invlaid system", __func__);
+ mutex_unlock(priv->spi_mutex);
+ return -EINVAL;
+ }
+
+ mutex_unlock(priv->spi_mutex);
+ if (ret != CXD2880_RESULT_OK) {
+ dev_err(&priv->spi->dev, "%s: failed. sys = %d\n",
+ __func__, priv->tnrdmd.sys);
+ return return_tbl[ret];
+ }
+
+ if (sync == 6) {
+ *status = FE_HAS_SIGNAL |
+ FE_HAS_CARRIER;
+ }
+ if (lock)
+ *status |= FE_HAS_VITERBI |
+ FE_HAS_SYNC |
+ FE_HAS_LOCK;
+ }
+
+ dev_dbg(&priv->spi->dev, "%s: status %d result %d\n", __func__,
+ *status, ret);
+
+ return return_tbl[CXD2880_RESULT_OK];
+}
+
+static int cxd2880_tune(struct dvb_frontend *fe,
+ bool retune,
+ unsigned int mode_flags,
+ unsigned int *delay,
+ enum fe_status *status)
+{
+ int ret = 0;
+
+ if ((!fe) || (!delay) || (!status)) {
+ pr_err("%s: invalid arg.", __func__);
+ return -EINVAL;
+ }
+
+ if (retune) {
+ ret = cxd2880_set_frontend(fe);
+ if (ret) {
+ pr_err("%s: cxd2880_set_frontend failed %d\n",
+ __func__, ret);
+ return ret;
+ }
+ }
+
+ *delay = HZ / 5;
+
+ return cxd2880_read_status(fe, status);
+}
+
+static int cxd2880_get_frontend_t(struct dvb_frontend *fe,
+ struct dtv_frontend_properties *c)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ int result = 0;
+ struct cxd2880_priv *priv = NULL;
+ enum cxd2880_dvbt_mode mode = CXD2880_DVBT_MODE_2K;
+ enum cxd2880_dvbt_guard guard = CXD2880_DVBT_GUARD_1_32;
+ struct cxd2880_dvbt_tpsinfo tps;
+ enum cxd2880_tnrdmd_spectrum_sense sense;
+ u16 snr = 0;
+ int strength = 0;
+ u32 pre_bit_err = 0, pre_bit_count = 0;
+ u32 post_bit_err = 0, post_bit_count = 0;
+ u32 block_err = 0, block_count = 0;
+
+ if ((!fe) || (!c)) {
+ pr_err("%s: invalid arg\n", __func__);
+ return -EINVAL;
+ }
+
+ priv = (struct cxd2880_priv *)fe->demodulator_priv;
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_tnrdmd_dvbt_mon_mode_guard(&priv->tnrdmd,
+ &mode, &guard);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ switch (mode) {
+ case CXD2880_DVBT_MODE_2K:
+ c->transmission_mode = TRANSMISSION_MODE_2K;
+ break;
+ case CXD2880_DVBT_MODE_8K:
+ c->transmission_mode = TRANSMISSION_MODE_8K;
+ break;
+ default:
+ c->transmission_mode = TRANSMISSION_MODE_2K;
+ dev_err(&priv->spi->dev, "%s: get invalid mode %d\n",
+ __func__, mode);
+ break;
+ }
+ switch (guard) {
+ case CXD2880_DVBT_GUARD_1_32:
+ c->guard_interval = GUARD_INTERVAL_1_32;
+ break;
+ case CXD2880_DVBT_GUARD_1_16:
+ c->guard_interval = GUARD_INTERVAL_1_16;
+ break;
+ case CXD2880_DVBT_GUARD_1_8:
+ c->guard_interval = GUARD_INTERVAL_1_8;
+ break;
+ case CXD2880_DVBT_GUARD_1_4:
+ c->guard_interval = GUARD_INTERVAL_1_4;
+ break;
+ default:
+ c->guard_interval = GUARD_INTERVAL_1_32;
+ dev_err(&priv->spi->dev, "%s: get invalid guard %d\n",
+ __func__, guard);
+ break;
+ }
+ } else {
+ c->transmission_mode = TRANSMISSION_MODE_2K;
+ c->guard_interval = GUARD_INTERVAL_1_32;
+ dev_dbg(&priv->spi->dev,
+ "%s: ModeGuard err %d\n", __func__, ret);
+ }
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_tnrdmd_dvbt_mon_tps_info(&priv->tnrdmd, &tps);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ switch (tps.hierarchy) {
+ case CXD2880_DVBT_HIERARCHY_NON:
+ c->hierarchy = HIERARCHY_NONE;
+ break;
+ case CXD2880_DVBT_HIERARCHY_1:
+ c->hierarchy = HIERARCHY_1;
+ break;
+ case CXD2880_DVBT_HIERARCHY_2:
+ c->hierarchy = HIERARCHY_2;
+ break;
+ case CXD2880_DVBT_HIERARCHY_4:
+ c->hierarchy = HIERARCHY_4;
+ break;
+ default:
+ c->hierarchy = HIERARCHY_NONE;
+ dev_err(&priv->spi->dev,
+ "%s: TPSInfo hierarchy invalid %d\n",
+ __func__, tps.hierarchy);
+ break;
+ }
+
+ switch (tps.rate_hp) {
+ case CXD2880_DVBT_CODERATE_1_2:
+ c->code_rate_HP = FEC_1_2;
+ break;
+ case CXD2880_DVBT_CODERATE_2_3:
+ c->code_rate_HP = FEC_2_3;
+ break;
+ case CXD2880_DVBT_CODERATE_3_4:
+ c->code_rate_HP = FEC_3_4;
+ break;
+ case CXD2880_DVBT_CODERATE_5_6:
+ c->code_rate_HP = FEC_5_6;
+ break;
+ case CXD2880_DVBT_CODERATE_7_8:
+ c->code_rate_HP = FEC_7_8;
+ break;
+ default:
+ c->code_rate_HP = FEC_NONE;
+ dev_err(&priv->spi->dev,
+ "%s: TPSInfo rateHP invalid %d\n",
+ __func__, tps.rate_hp);
+ break;
+ }
+ switch (tps.rate_lp) {
+ case CXD2880_DVBT_CODERATE_1_2:
+ c->code_rate_LP = FEC_1_2;
+ break;
+ case CXD2880_DVBT_CODERATE_2_3:
+ c->code_rate_LP = FEC_2_3;
+ break;
+ case CXD2880_DVBT_CODERATE_3_4:
+ c->code_rate_LP = FEC_3_4;
+ break;
+ case CXD2880_DVBT_CODERATE_5_6:
+ c->code_rate_LP = FEC_5_6;
+ break;
+ case CXD2880_DVBT_CODERATE_7_8:
+ c->code_rate_LP = FEC_7_8;
+ break;
+ default:
+ c->code_rate_LP = FEC_NONE;
+ dev_err(&priv->spi->dev,
+ "%s: TPSInfo rateLP invalid %d\n",
+ __func__, tps.rate_lp);
+ break;
+ }
+ switch (tps.constellation) {
+ case CXD2880_DVBT_CONSTELLATION_QPSK:
+ c->modulation = QPSK;
+ break;
+ case CXD2880_DVBT_CONSTELLATION_16QAM:
+ c->modulation = QAM_16;
+ break;
+ case CXD2880_DVBT_CONSTELLATION_64QAM:
+ c->modulation = QAM_64;
+ break;
+ default:
+ c->modulation = QPSK;
+ dev_err(&priv->spi->dev,
+ "%s: TPSInfo constellation invalid %d\n",
+ __func__, tps.constellation);
+ break;
+ }
+ } else {
+ c->hierarchy = HIERARCHY_NONE;
+ c->code_rate_HP = FEC_NONE;
+ c->code_rate_LP = FEC_NONE;
+ c->modulation = QPSK;
+ dev_dbg(&priv->spi->dev,
+ "%s: TPS info err %d\n", __func__, ret);
+ }
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_tnrdmd_dvbt_mon_spectrum_sense(&priv->tnrdmd, &sense);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ switch (sense) {
+ case CXD2880_TNRDMD_SPECTRUM_NORMAL:
+ c->inversion = INVERSION_OFF;
+ break;
+ case CXD2880_TNRDMD_SPECTRUM_INV:
+ c->inversion = INVERSION_ON;
+ break;
+ default:
+ c->inversion = INVERSION_OFF;
+ dev_err(&priv->spi->dev,
+ "%s: spectrum sense invalid %d\n",
+ __func__, sense);
+ break;
+ }
+ } else {
+ c->inversion = INVERSION_OFF;
+ dev_dbg(&priv->spi->dev,
+ "%s: spectrum_sense %d\n", __func__, ret);
+ }
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ c->strength.len = 1;
+ c->strength.stat[0].scale = FE_SCALE_DECIBEL;
+ c->strength.stat[0].svalue = strength;
+ } else {
+ c->strength.len = 1;
+ c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ dev_dbg(&priv->spi->dev, "%s: mon_rf_lvl %d\n",
+ __func__, result);
+ }
+
+ result = cxd2880_read_snr(fe, &snr);
+ if (!result) {
+ c->cnr.len = 1;
+ c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
+ c->cnr.stat[0].svalue = snr;
+ } else {
+ c->cnr.len = 1;
+ c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ dev_dbg(&priv->spi->dev, "%s: read_snr %d\n", __func__, result);
+ }
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_pre_bit_err_t(&priv->tnrdmd, &pre_bit_err,
+ &pre_bit_count);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ c->pre_bit_error.len = 1;
+ c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
+ c->pre_bit_error.stat[0].uvalue = pre_bit_err;
+ c->pre_bit_count.len = 1;
+ c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
+ c->pre_bit_count.stat[0].uvalue = pre_bit_count;
+ } else {
+ c->pre_bit_error.len = 1;
+ c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ c->pre_bit_count.len = 1;
+ c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ dev_dbg(&priv->spi->dev,
+ "%s: pre_bit_error_t failed %d\n",
+ __func__, ret);
+ }
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_post_bit_err_t(&priv->tnrdmd,
+ &post_bit_err, &post_bit_count);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ c->post_bit_error.len = 1;
+ c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
+ c->post_bit_error.stat[0].uvalue = post_bit_err;
+ c->post_bit_count.len = 1;
+ c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
+ c->post_bit_count.stat[0].uvalue = post_bit_count;
+ } else {
+ c->post_bit_error.len = 1;
+ c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ c->post_bit_count.len = 1;
+ c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ dev_dbg(&priv->spi->dev,
+ "%s: post_bit_err_t %d\n", __func__, ret);
+ }
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_read_block_err_t(&priv->tnrdmd,
+ &block_err, &block_count);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ c->block_error.len = 1;
+ c->block_error.stat[0].scale = FE_SCALE_COUNTER;
+ c->block_error.stat[0].uvalue = block_err;
+ c->block_count.len = 1;
+ c->block_count.stat[0].scale = FE_SCALE_COUNTER;
+ c->block_count.stat[0].uvalue = block_count;
+ } else {
+ c->block_error.len = 1;
+ c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ c->block_count.len = 1;
+ c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ dev_dbg(&priv->spi->dev,
+ "%s: read_block_err_t %d\n", __func__, ret);
+ }
+
+ return 0;
+}
+
+static int cxd2880_get_frontend_t2(struct dvb_frontend *fe,
+ struct dtv_frontend_properties *c)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ int result = 0;
+ struct cxd2880_priv *priv = NULL;
+ struct cxd2880_dvbt2_l1pre l1pre;
+ enum cxd2880_dvbt2_plp_code_rate coderate;
+ enum cxd2880_dvbt2_plp_constell qam;
+ enum cxd2880_tnrdmd_spectrum_sense sense;
+ u16 snr = 0;
+ int strength = 0;
+ u32 pre_bit_err = 0, pre_bit_count = 0;
+ u32 post_bit_err = 0, post_bit_count = 0;
+ u32 block_err = 0, block_count = 0;
+
+ if ((!fe) || (!c)) {
+ pr_err("%s: invalid arg.\n", __func__);
+ return -EINVAL;
+ }
+
+ priv = (struct cxd2880_priv *)fe->demodulator_priv;
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_tnrdmd_dvbt2_mon_l1_pre(&priv->tnrdmd, &l1pre);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ switch (l1pre.fft_mode) {
+ case CXD2880_DVBT2_M2K:
+ c->transmission_mode = TRANSMISSION_MODE_2K;
+ break;
+ case CXD2880_DVBT2_M8K:
+ c->transmission_mode = TRANSMISSION_MODE_8K;
+ break;
+ case CXD2880_DVBT2_M4K:
+ c->transmission_mode = TRANSMISSION_MODE_4K;
+ break;
+ case CXD2880_DVBT2_M1K:
+ c->transmission_mode = TRANSMISSION_MODE_1K;
+ break;
+ case CXD2880_DVBT2_M16K:
+ c->transmission_mode = TRANSMISSION_MODE_16K;
+ break;
+ case CXD2880_DVBT2_M32K:
+ c->transmission_mode = TRANSMISSION_MODE_32K;
+ break;
+ default:
+ c->transmission_mode = TRANSMISSION_MODE_2K;
+ dev_err(&priv->spi->dev,
+ "%s: L1Pre fft_mode invalid %d\n",
+ __func__, l1pre.fft_mode);
+ break;
+ }
+ switch (l1pre.gi) {
+ case CXD2880_DVBT2_G1_32:
+ c->guard_interval = GUARD_INTERVAL_1_32;
+ break;
+ case CXD2880_DVBT2_G1_16:
+ c->guard_interval = GUARD_INTERVAL_1_16;
+ break;
+ case CXD2880_DVBT2_G1_8:
+ c->guard_interval = GUARD_INTERVAL_1_8;
+ break;
+ case CXD2880_DVBT2_G1_4:
+ c->guard_interval = GUARD_INTERVAL_1_4;
+ break;
+ case CXD2880_DVBT2_G1_128:
+ c->guard_interval = GUARD_INTERVAL_1_128;
+ break;
+ case CXD2880_DVBT2_G19_128:
+ c->guard_interval = GUARD_INTERVAL_19_128;
+ break;
+ case CXD2880_DVBT2_G19_256:
+ c->guard_interval = GUARD_INTERVAL_19_256;
+ break;
+ default:
+ c->guard_interval = GUARD_INTERVAL_1_32;
+ dev_err(&priv->spi->dev,
+ "%s: L1Pre gi invalid %d\n",
+ __func__, l1pre.gi);
+ break;
+ }
+ } else {
+ c->transmission_mode = TRANSMISSION_MODE_2K;
+ c->guard_interval = GUARD_INTERVAL_1_32;
+ dev_dbg(&priv->spi->dev,
+ "%s: L1Pre err %d\n", __func__, ret);
+ }
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_tnrdmd_dvbt2_mon_code_rate(&priv->tnrdmd,
+ CXD2880_DVBT2_PLP_DATA,
+ &coderate);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ switch (coderate) {
+ case CXD2880_DVBT2_R1_2:
+ c->fec_inner = FEC_1_2;
+ break;
+ case CXD2880_DVBT2_R3_5:
+ c->fec_inner = FEC_3_5;
+ break;
+ case CXD2880_DVBT2_R2_3:
+ c->fec_inner = FEC_2_3;
+ break;
+ case CXD2880_DVBT2_R3_4:
+ c->fec_inner = FEC_3_4;
+ break;
+ case CXD2880_DVBT2_R4_5:
+ c->fec_inner = FEC_4_5;
+ break;
+ case CXD2880_DVBT2_R5_6:
+ c->fec_inner = FEC_5_6;
+ break;
+ default:
+ c->fec_inner = FEC_NONE;
+ dev_err(&priv->spi->dev,
+ "%s: CodeRate invalid %d\n",
+ __func__, coderate);
+ break;
+ }
+ } else {
+ c->fec_inner = FEC_NONE;
+ dev_dbg(&priv->spi->dev, "%s: CodeRate %d\n", __func__, ret);
+ }
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_tnrdmd_dvbt2_mon_qam(&priv->tnrdmd,
+ CXD2880_DVBT2_PLP_DATA,
+ &qam);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ switch (qam) {
+ case CXD2880_DVBT2_QPSK:
+ c->modulation = QPSK;
+ break;
+ case CXD2880_DVBT2_QAM16:
+ c->modulation = QAM_16;
+ break;
+ case CXD2880_DVBT2_QAM64:
+ c->modulation = QAM_64;
+ break;
+ case CXD2880_DVBT2_QAM256:
+ c->modulation = QAM_256;
+ break;
+ default:
+ c->modulation = QPSK;
+ dev_err(&priv->spi->dev,
+ "%s: QAM invalid %d\n",
+ __func__, qam);
+ break;
+ }
+ } else {
+ c->modulation = QPSK;
+ dev_dbg(&priv->spi->dev, "%s: QAM %d\n", __func__, ret);
+ }
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_tnrdmd_dvbt2_mon_spectrum_sense(&priv->tnrdmd, &sense);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ switch (sense) {
+ case CXD2880_TNRDMD_SPECTRUM_NORMAL:
+ c->inversion = INVERSION_OFF;
+ break;
+ case CXD2880_TNRDMD_SPECTRUM_INV:
+ c->inversion = INVERSION_ON;
+ break;
+ default:
+ c->inversion = INVERSION_OFF;
+ dev_err(&priv->spi->dev,
+ "%s: spectrum sense invalid %d\n",
+ __func__, sense);
+ break;
+ }
+ } else {
+ c->inversion = INVERSION_OFF;
+ dev_dbg(&priv->spi->dev,
+ "%s: SpectrumSense %d\n", __func__, ret);
+ }
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ c->strength.len = 1;
+ c->strength.stat[0].scale = FE_SCALE_DECIBEL;
+ c->strength.stat[0].svalue = strength;
+ } else {
+ c->strength.len = 1;
+ c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ dev_dbg(&priv->spi->dev,
+ "%s: mon_rf_lvl %d\n", __func__, ret);
+ }
+
+ result = cxd2880_read_snr(fe, &snr);
+ if (!result) {
+ c->cnr.len = 1;
+ c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
+ c->cnr.stat[0].svalue = snr;
+ } else {
+ c->cnr.len = 1;
+ c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ dev_dbg(&priv->spi->dev, "%s: read_snr %d\n", __func__, result);
+ }
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_pre_bit_err_t2(&priv->tnrdmd,
+ &pre_bit_err,
+ &pre_bit_count);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ c->pre_bit_error.len = 1;
+ c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
+ c->pre_bit_error.stat[0].uvalue = pre_bit_err;
+ c->pre_bit_count.len = 1;
+ c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
+ c->pre_bit_count.stat[0].uvalue = pre_bit_count;
+ } else {
+ c->pre_bit_error.len = 1;
+ c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ c->pre_bit_count.len = 1;
+ c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ dev_dbg(&priv->spi->dev,
+ "%s: read_bit_err_t2 %d\n", __func__, ret);
+ }
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_post_bit_err_t2(&priv->tnrdmd,
+ &post_bit_err, &post_bit_count);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ c->post_bit_error.len = 1;
+ c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
+ c->post_bit_error.stat[0].uvalue = post_bit_err;
+ c->post_bit_count.len = 1;
+ c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
+ c->post_bit_count.stat[0].uvalue = post_bit_count;
+ } else {
+ c->post_bit_error.len = 1;
+ c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ c->post_bit_count.len = 1;
+ c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ dev_dbg(&priv->spi->dev,
+ "%s: post_bit_err_t2 %d\n", __func__, ret);
+ }
+
+ mutex_lock(priv->spi_mutex);
+ ret = cxd2880_read_block_err_t2(&priv->tnrdmd,
+ &block_err, &block_count);
+ mutex_unlock(priv->spi_mutex);
+ if (ret == CXD2880_RESULT_OK) {
+ c->block_error.len = 1;
+ c->block_error.stat[0].scale = FE_SCALE_COUNTER;
+ c->block_error.stat[0].uvalue = block_err;
+ c->block_count.len = 1;
+ c->block_count.stat[0].scale = FE_SCALE_COUNTER;
+ c->block_count.stat[0].uvalue = block_count;
+ } else {
+ c->block_error.len = 1;
+ c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ c->block_count.len = 1;
+ c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
+ dev_dbg(&priv->spi->dev,
+ "%s: read_block_err_t2 %d\n", __func__, ret);
+ }
+
+ return 0;
+}
+
+static int cxd2880_get_frontend(struct dvb_frontend *fe,
+ struct dtv_frontend_properties *props)
+{
+ struct cxd2880_priv *priv = NULL;
+ int result = 0;
+
+ if ((!fe) || (!props)) {
+ pr_err("%s: invalid arg.", __func__);
+ return -EINVAL;
+ }
+
+ priv = (struct cxd2880_priv *)fe->demodulator_priv;
+
+ dev_dbg(&priv->spi->dev, "%s: system=%d\n", __func__,
+ fe->dtv_property_cache.delivery_system);
+ switch (fe->dtv_property_cache.delivery_system) {
+ case SYS_DVBT:
+ result = cxd2880_get_frontend_t(fe, props);
+ break;
+ case SYS_DVBT2:
+ result = cxd2880_get_frontend_t2(fe, props);
+ break;
+ default:
+ result = -EINVAL;
+ break;
+ }
+
+ return result;
+}
+
+static enum dvbfe_algo cxd2880_get_frontend_algo(struct dvb_frontend *fe)
+{
+ return DVBFE_ALGO_HW;
+}
+
+static struct dvb_frontend_ops cxd2880_dvbt_t2_ops;
+
+struct dvb_frontend *cxd2880_attach(struct dvb_frontend *fe,
+ struct cxd2880_config *cfg)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ enum cxd2880_tnrdmd_chip_id chipid =
+ CXD2880_TNRDMD_CHIP_ID_UNKNOWN;
+ static struct cxd2880_priv *priv;
+ u8 data = 0;
+
+ if (!fe) {
+ pr_err("%s: invalid arg.\n", __func__);
+ return NULL;
+ }
+
+ priv = kzalloc(sizeof(struct cxd2880_priv), GFP_KERNEL);
+ if (!priv)
+ return NULL;
+
+ priv->spi = cfg->spi;
+ priv->spi_mutex = cfg->spi_mutex;
+ priv->spi_device.spi = cfg->spi;
+
+ memcpy(&fe->ops, &cxd2880_dvbt_t2_ops,
+ sizeof(struct dvb_frontend_ops));
+
+ ret = cxd2880_spi_device_initialize(&priv->spi_device,
+ CXD2880_SPI_MODE_0,
+ 55000000);
+ if (ret != CXD2880_RESULT_OK) {
+ dev_err(&priv->spi->dev,
+ "%s: spi_device_initialize failed. %d\n",
+ __func__, ret);
+ kfree(priv);
+ return NULL;
+ }
+
+ ret = cxd2880_spi_device_create_spi(&priv->cxd2880_spi,
+ &priv->spi_device);
+ if (ret != CXD2880_RESULT_OK) {
+ dev_err(&priv->spi->dev,
+ "%s: spi_device_create_spi failed. %d\n",
+ __func__, ret);
+ kfree(priv);
+ return NULL;
+ }
+
+ ret = cxd2880_io_spi_create(&priv->regio, &priv->cxd2880_spi, 0);
+ if (ret != CXD2880_RESULT_OK) {
+ dev_err(&priv->spi->dev,
+ "%s: io_spi_create failed. %d\n", __func__, ret);
+ kfree(priv);
+ return NULL;
+ }
+ if (priv->regio.write_reg(&priv->regio, CXD2880_IO_TGT_SYS, 0x00, 0x00)
+ != CXD2880_RESULT_OK) {
+ dev_err(&priv->spi->dev,
+ "%s: set bank to 0x00 failed.\n", __func__);
+ kfree(priv);
+ return NULL;
+ }
+ if (priv->regio.read_regs(&priv->regio,
+ CXD2880_IO_TGT_SYS, 0xFD, &data, 1)
+ != CXD2880_RESULT_OK) {
+ dev_err(&priv->spi->dev,
+ "%s: read chip id failed.\n", __func__);
+ kfree(priv);
+ return NULL;
+ }
+
+ chipid = (enum cxd2880_tnrdmd_chip_id)data;
+ if ((chipid != CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X) &&
+ (chipid != CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11)) {
+ dev_err(&priv->spi->dev,
+ "%s: chip id invalid.\n", __func__);
+ kfree(priv);
+ return NULL;
+ }
+
+ fe->demodulator_priv = priv;
+ dev_info(&priv->spi->dev,
+ "CXD2880 driver version: Ver %s\n",
+ CXD2880_TNRDMD_DRIVER_VERSION);
+
+ return fe;
+}
+EXPORT_SYMBOL(cxd2880_attach);
+
+static struct dvb_frontend_ops cxd2880_dvbt_t2_ops = {
+ .info = {
+ .name = "Sony CXD2880",
+ .frequency_min = 174000000,
+ .frequency_max = 862000000,
+ .frequency_stepsize = 1000,
+ .caps = FE_CAN_INVERSION_AUTO |
+ FE_CAN_FEC_1_2 |
+ FE_CAN_FEC_2_3 |
+ FE_CAN_FEC_3_4 |
+ FE_CAN_FEC_4_5 |
+ FE_CAN_FEC_5_6 |
+ FE_CAN_FEC_7_8 |
+ FE_CAN_FEC_AUTO |
+ FE_CAN_QPSK |
+ FE_CAN_QAM_16 |
+ FE_CAN_QAM_32 |
+ FE_CAN_QAM_64 |
+ FE_CAN_QAM_128 |
+ FE_CAN_QAM_256 |
+ FE_CAN_QAM_AUTO |
+ FE_CAN_TRANSMISSION_MODE_AUTO |
+ FE_CAN_GUARD_INTERVAL_AUTO |
+ FE_CAN_2G_MODULATION |
+ FE_CAN_RECOVER |
+ FE_CAN_MUTE_TS,
+ },
+ .delsys = { SYS_DVBT, SYS_DVBT2 },
+
+ .release = cxd2880_release,
+ .init = cxd2880_init,
+ .sleep = cxd2880_sleep,
+ .tune = cxd2880_tune,
+ .set_frontend = cxd2880_set_frontend,
+ .get_frontend = cxd2880_get_frontend,
+ .read_status = cxd2880_read_status,
+ .read_ber = cxd2880_read_ber,
+ .read_signal_strength = cxd2880_read_signal_strength,
+ .read_snr = cxd2880_read_snr,
+ .read_ucblocks = cxd2880_read_ucblocks,
+ .get_frontend_algo = cxd2880_get_frontend_algo,
+};
+
+MODULE_DESCRIPTION(
+"Sony CXD2880 DVB-T2/T tuner + demodulator drvier");
+MODULE_AUTHOR("Sony Semiconductor Solutions Corporation");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related
* [PATCH v2 07/15] [media] cxd2880: Add integration layer for the driver
From: Yasunari.Takiguchi @ 2017-04-14 2:29 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-media
Cc: tbird20d, frowand.list, Yasunari Takiguchi, Masayuki Yamamoto,
Hideki Nozawa, Kota Yonezawa, Toshihiko Matsumoto,
Satoshi Watanabe
In-Reply-To: <20170414015043.16731-1-Yasunari.Takiguchi@sony.com>
From: Yasunari Takiguchi <Yasunari.Takiguchi@sony.com>
These functions monitor the driver and watch for task completion.
This is part of the Sony CXD2880 DVB-T2/T tuner + demodulator driver.
Signed-off-by: Yasunari Takiguchi <Yasunari.Takiguchi@sony.com>
Signed-off-by: Masayuki Yamamoto <Masayuki.Yamamoto@sony.com>
Signed-off-by: Hideki Nozawa <Hideki.Nozawa@sony.com>
Signed-off-by: Kota Yonezawa <Kota.Yonezawa@sony.com>
Signed-off-by: Toshihiko Matsumoto <Toshihiko.Matsumoto@sony.com>
Signed-off-by: Satoshi Watanabe <Satoshi.C.Watanabe@sony.com>
---
.../media/dvb-frontends/cxd2880/cxd2880_integ.c | 99 ++++++++++++++++++++++
.../media/dvb-frontends/cxd2880/cxd2880_integ.h | 44 ++++++++++
2 files changed, 143 insertions(+)
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_integ.c
create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_integ.h
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_integ.c b/drivers/media/dvb-frontends/cxd2880/cxd2880_integ.c
new file mode 100644
index 000000000000..5ad6685e2a1d
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_integ.c
@@ -0,0 +1,99 @@
+/*
+ * cxd2880_integ.c
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * integration layer common functions
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cxd2880_tnrdmd.h"
+#include "cxd2880_tnrdmd_mon.h"
+#include "cxd2880_integ.h"
+
+enum cxd2880_ret cxd2880_integ_init(struct cxd2880_tnrdmd *tnr_dmd)
+{
+ enum cxd2880_ret ret = CXD2880_RESULT_OK;
+ struct cxd2880_stopwatch timer;
+ u32 elapsed_time = 0;
+ u8 cpu_task_completed = 0;
+
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ ret = cxd2880_tnrdmd_init1(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret = cxd2880_stopwatch_start(&timer);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ while (1) {
+ ret = cxd2880_stopwatch_elapsed(&timer, &elapsed_time);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ ret =
+ cxd2880_tnrdmd_check_internal_cpu_status(tnr_dmd,
+ &cpu_task_completed);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ if (cpu_task_completed)
+ break;
+
+ if (elapsed_time > CXD2880_TNRDMD_WAIT_INIT_TIMEOUT)
+ return CXD2880_RESULT_ERROR_TIMEOUT;
+ ret =
+ cxd2880_stopwatch_sleep(&timer,
+ CXD2880_TNRDMD_WAIT_INIT_INTVL);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+ }
+
+ ret = cxd2880_tnrdmd_init2(tnr_dmd);
+ if (ret != CXD2880_RESULT_OK)
+ return ret;
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_integ_cancel(struct cxd2880_tnrdmd *tnr_dmd)
+{
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ cxd2880_atomic_set(&tnr_dmd->cancel, 1);
+
+ return CXD2880_RESULT_OK;
+}
+
+enum cxd2880_ret cxd2880_integ_check_cancellation(struct cxd2880_tnrdmd
+ *tnr_dmd)
+{
+ if (!tnr_dmd)
+ return CXD2880_RESULT_ERROR_ARG;
+
+ if (cxd2880_atomic_read(&tnr_dmd->cancel) != 0)
+ return CXD2880_RESULT_ERROR_CANCEL;
+
+ return CXD2880_RESULT_OK;
+}
diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_integ.h b/drivers/media/dvb-frontends/cxd2880/cxd2880_integ.h
new file mode 100644
index 000000000000..9cfc52dbf9d4
--- /dev/null
+++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_integ.h
@@ -0,0 +1,44 @@
+/*
+ * cxd2880_integ.h
+ * Sony CXD2880 DVB-T2/T tuner + demodulator driver
+ * integration layer common interface
+ *
+ * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CXD2880_INTEG_H
+#define CXD2880_INTEG_H
+
+#include "cxd2880_tnrdmd.h"
+
+#define CXD2880_TNRDMD_WAIT_INIT_TIMEOUT 500
+#define CXD2880_TNRDMD_WAIT_INIT_INTVL 10
+
+#define CXD2880_TNRDMD_WAIT_AGC_STABLE 100
+
+enum cxd2880_ret cxd2880_integ_init(struct cxd2880_tnrdmd *tnr_dmd);
+
+enum cxd2880_ret cxd2880_integ_cancel(struct cxd2880_tnrdmd *tnr_dmd);
+
+enum cxd2880_ret cxd2880_integ_check_cancellation(struct cxd2880_tnrdmd
+ *tnr_dmd);
+
+#endif
--
2.11.0
^ permalink raw reply related
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