* [PATCH 11/13] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
From: Hauke Mehrtens @ 2017-04-17 19:29 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w, Hauke Mehrtens
In-Reply-To: <20170417192942.32219-1-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
the PHY interfaces for each core. The phy instances can be passed to the
dwc2 driver, which already supports the generic phy interface.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
.../bindings/phy/phy-lantiq-rcu-usb2.txt | 59 ++++
arch/mips/lantiq/xway/reset.c | 43 ---
arch/mips/lantiq/xway/sysctrl.c | 24 +-
drivers/phy/Kconfig | 8 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-lantiq-rcu-usb2.c | 325 +++++++++++++++++++++
6 files changed, 405 insertions(+), 55 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
new file mode 100644
index 000000000000..0ec9f790b6e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
@@ -0,0 +1,59 @@
+Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
+===========================================
+
+This binding describes the USB PHY hardware provided by the RCU module on the
+Lantiq XWAY SoCs.
+
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible : Should be one of
+ "lantiq,ase-rcu-usb2-phy"
+ "lantiq,danube-rcu-usb2-phy"
+ "lantiq,xrx100-rcu-usb2-phy"
+ "lantiq,xrx200-rcu-usb2-phy"
+ "lantiq,xrx300-rcu-usb2-phy"
+- lantiq,rcu-syscon : A phandle to the RCU module and the offsets to the
+ USB PHY configuration and USB MAC registers.
+- address-cells : should be 1
+- size-cells : should be 0
+- phy-cells : from the generic PHY bindings, must be 1
+
+Optional properties (controller (parent) node):
+- vbus-gpio : References a GPIO which enables VBUS all given USB
+ ports.
+
+Required nodes : A sub-node is required for each USB PHY port.
+
+
+-------------------------------------------------------------------------------
+Required properties (port (child) node):
+- reg : The ID of the USB port, usually 0 or 1.
+- clocks : References to the (PMU) "ctrl" and "phy" clk gates.
+- clock-names : Must be one of the following:
+ "ctrl"
+ "phy"
+- resets : References to the RCU USB configuration reset bits.
+- reset-names : Must be one of the following:
+ "analog-config" (optional)
+ "statemachine-soft" (optional)
+
+Optional properties (port (child) node):
+- vbus-gpio : References a GPIO which enables VBUS for the USB port.
+
+
+-------------------------------------------------------------------------------
+Example for the USB PHYs on an xRX200 SoC:
+ usb_phys0: rcu-usb2-phy@0 {
+ compatible = "lantiq,xrx200-rcu-usb2-phy";
+ reg = <0>;
+
+ lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
+ clocks = <&pmu PMU_GATE_USB0_CTRL>,
+ <&pmu PMU_GATE_USB0_PHY>;
+ clock-names = "ctrl", "phy";
+ vbus-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
+ resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 3f30fb81a50f..5aec1f54275b 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -124,45 +124,6 @@ static void ltq_machine_power_off(void)
unreachable();
}
-static void ltq_usb_init(void)
-{
- /* Power for USB cores 1 & 2 */
- ltq_pmu_enable(PMU_AHBM);
- ltq_pmu_enable(PMU_USB0);
- ltq_pmu_enable(PMU_USB1);
-
- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
-
- /* Enable USB PHY power for cores 1 & 2 */
- ltq_pmu_enable(PMU_USB0_P);
- ltq_pmu_enable(PMU_USB1_P);
-
- /* Configure cores to host mode */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
- RCU_USB1CFG);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
- RCU_USB2CFG);
-
- /* Select DMA endianness (Host-endian: big-endian) */
- ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
- | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
- ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
- | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
-
- /* Hard reset USB state machines */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
- udelay(50 * 1000);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
-
- /* Soft reset USB state machines */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
- | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
- udelay(50 * 1000);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
- & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
-}
-
static int __init mips_reboot_setup(void)
{
struct resource res;
@@ -186,10 +147,6 @@ static int __init mips_reboot_setup(void)
if (!ltq_rcu_membase)
panic("Failed to remap core memory");
- if (of_machine_is_compatible("lantiq,ar9") ||
- of_machine_is_compatible("lantiq,vr9"))
- ltq_usb_init();
-
_machine_restart = ltq_machine_restart;
_machine_halt = ltq_machine_halt;
pm_power_off = ltq_machine_power_off;
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 5764d3ddce69..18725f2d5b67 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -469,8 +469,8 @@ void __init ltq_soc_init(void)
if (of_machine_is_compatible("lantiq,grx390") ||
of_machine_is_compatible("lantiq,ar10")) {
- clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
- clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
+ clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 2, PMU_ANALOG_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 2, PMU_ANALOG_USB1_P);
/* rc 0 */
clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -490,8 +490,8 @@ void __init ltq_soc_init(void)
else
clkdev_add_static(CLOCK_133M, CLOCK_133M,
CLOCK_133M, CLOCK_133M);
- clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
- clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+ clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
@@ -525,10 +525,10 @@ void __init ltq_soc_init(void)
} else if (of_machine_is_compatible("lantiq,vr9")) {
clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
- clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
- clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
- clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
- clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
+ clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0 | PMU_AHBM);
+ clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 0, PMU_USB1_P);
+ clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "ctrl", 1, 0, PMU_USB1 | PMU_AHBM);
clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -548,8 +548,8 @@ void __init ltq_soc_init(void)
} else if (of_machine_is_compatible("lantiq,ar9")) {
clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
ltq_ar9_fpi_hz(), CLOCK_250M);
- clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
- clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+ clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
@@ -560,8 +560,8 @@ void __init ltq_soc_init(void)
} else {
clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
- clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
- clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+ clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 005cadb7a3f8..dbb450e3ba04 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -488,6 +488,14 @@ config PHY_CYGNUS_PCIE
Enable this to support the Broadcom Cygnus PCIe PHY.
If unsure, say N.
+config PHY_LANTIQ_RCU_USB2
+ tristate "Lantiq XWAY SoC RCU based USB PHY"
+ depends on SOC_TYPE_XWAY
+ depends on OF
+ select GENERIC_PHY
+ help
+ Support for the USB PHY(s) on the Lantiq XWAY family SoCs.
+
source "drivers/phy/tegra/Kconfig"
config PHY_NS2_PCIE
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index dd8f3b5d2918..52631f5ac470 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
obj-$(CONFIG_PHY_BRCM_SATA) += phy-brcm-sata.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
+obj-$(CONFIG_PHY_LANTIQ_RCU_USB2) += phy-lantiq-rcu-usb2.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
diff --git a/drivers/phy/phy-lantiq-rcu-usb2.c b/drivers/phy/phy-lantiq-rcu-usb2.c
new file mode 100644
index 000000000000..9bff42afd256
--- /dev/null
+++ b/drivers/phy/phy-lantiq-rcu-usb2.c
@@ -0,0 +1,325 @@
+/*
+ * Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver
+ *
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define MAX_VBUS_GPIO 2
+
+/* Transmitter HS Pre-Emphasis Enable */
+#define RCU_CFG1_TX_PEE BIT(0)
+/* Disconnect Threshold */
+#define RCU_CFG1_DIS_THR_MASK 0x00038000
+#define RCU_CFG1_DIS_THR_SHIFT 15
+
+struct ltq_rcu_usb2_bits {
+ u8 hostmode;
+ u8 slave_endianness;
+ u8 host_endianness;
+ bool have_ana_cfg;
+};
+
+struct ltq_rcu_usb2_priv {
+ struct regmap *regmap;
+ u32 phy_reg_offset;
+ u32 ana_cfg1_reg_offset;
+ const struct ltq_rcu_usb2_bits *reg_bits;
+ struct device *dev;
+ struct gpio_desc *gpiod_vbus[MAX_VBUS_GPIO];
+ struct phy *phy;
+ struct clk *ctrl_gate_clk;
+ struct clk *phy_gate_clk;
+ struct reset_control *ctrl_reset;
+ struct reset_control *phy_reset;
+};
+
+static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = {
+ .hostmode = 11,
+ .slave_endianness = 9,
+ .host_endianness = 10,
+ .have_ana_cfg = false,
+};
+
+static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = {
+ .hostmode = 11,
+ .slave_endianness = 17,
+ .host_endianness = 10,
+ .have_ana_cfg = false,
+};
+
+static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = {
+ .hostmode = 11,
+ .slave_endianness = 9,
+ .host_endianness = 10,
+ .have_ana_cfg = true,
+};
+
+static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = {
+ {
+ .compatible = "lantiq,ase-rcu-usb2-phy",
+ .data = &xway_rcu_usb2_reg_bits,
+ },
+ {
+ .compatible = "lantiq,danube-rcu-usb2-phy",
+ .data = &xway_rcu_usb2_reg_bits,
+ },
+ {
+ .compatible = "lantiq,xrx100-rcu-usb2-phy",
+ .data = &xrx100_rcu_usb2_reg_bits,
+ },
+ {
+ .compatible = "lantiq,xrx200-rcu-usb2-phy",
+ .data = &xrx200_rcu_usb2_reg_bits,
+ },
+ {
+ .compatible = "lantiq,xrx300-rcu-usb2-phy",
+ .data = &xrx200_rcu_usb2_reg_bits,
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match);
+
+static void ltq_rcu_usb2_set_vbus_gpio_value(struct gpio_desc **gpiods,
+ int value)
+{
+ int i;
+
+ for (i = 0; i < MAX_VBUS_GPIO; i++)
+ if (!IS_ERR_OR_NULL(gpiods[i]))
+ gpiod_set_value(gpiods[i], value);
+}
+
+static int ltq_rcu_usb2_phy_power_on(struct phy *phy)
+{
+ struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
+
+ if (priv->phy_reset)
+ reset_control_deassert(priv->phy_reset);
+
+ /* enable the port-specific VBUS GPIOs if available */
+ ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 1);
+
+ return 0;
+}
+
+static int ltq_rcu_usb2_phy_power_off(struct phy *phy)
+{
+ struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
+
+ /*
+ * only disable the port-specific VBUS GPIO here (if available), the
+ * shared VBUS GPIO might still be used by another port
+ */
+ ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 0);
+
+ if (priv->phy_reset)
+ reset_control_assert(priv->phy_reset);
+
+ return 0;
+}
+
+static struct phy_ops ltq_rcu_usb2_phy_ops = {
+ .power_on = ltq_rcu_usb2_phy_power_on,
+ .power_off = ltq_rcu_usb2_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ltq_rcu_usb2_priv *priv = dev_get_drvdata(dev);
+
+ /* Power on the USB core. */
+ if (clk_prepare_enable(priv->ctrl_gate_clk)) {
+ dev_err(dev, "failed to enable CTRL gate\n");
+ return;
+ }
+
+ /*
+ * Power on the USB PHY. We have to do it early because
+ * otherwise the second core won't turn on properly.
+ */
+ if (clk_prepare_enable(priv->phy_gate_clk)) {
+ dev_err(dev, "failed to enable PHY gate\n");
+ return;
+ }
+
+ if (priv->reg_bits->have_ana_cfg) {
+ regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
+ RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE);
+ regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
+ RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT);
+ }
+
+ /* Configure core to host mode */
+ regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+ BIT(priv->reg_bits->hostmode), 0);
+
+ /* Select DMA endianness (Host-endian: big-endian) */
+ regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+ BIT(priv->reg_bits->slave_endianness), 0);
+ regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+ BIT(priv->reg_bits->host_endianness),
+ BIT(priv->reg_bits->host_endianness));
+
+ /* Reset USB core throgh reset controller */
+ reset_control_deassert(priv->ctrl_reset);
+
+ if (priv->phy_reset)
+ reset_control_assert(priv->phy_reset);
+}
+
+static int ltq_rcu_usb2_get_vbus_gpios(struct device *dev,
+ struct gpio_desc **gpios)
+{
+ int i;
+
+ for (i = 0; i < MAX_VBUS_GPIO; i++) {
+ gpios[i] = devm_gpiod_get_index_optional(dev, "vbus", i,
+ GPIOD_OUT_LOW);
+ if (IS_ERR(gpios[i]))
+ return PTR_ERR(gpios[i]);
+ }
+
+ return 0;
+}
+
+static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
+ struct ltq_rcu_usb2_priv *priv)
+{
+ struct device *dev = priv->dev;
+ const struct of_device_id *match =
+ of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
+ int ret;
+
+ if (!match) {
+ dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
+ return -EINVAL;
+ }
+
+ priv->reg_bits = match->data;
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(phynode,
+ "lantiq,rcu-syscon");
+ if (IS_ERR(priv->regmap)) {
+ dev_err(dev, "Failed to lookup RCU regmap\n");
+ return PTR_ERR(priv->regmap);
+ }
+
+ ret = ltq_rcu_usb2_get_vbus_gpios(dev, priv->gpiod_vbus);
+ if (ret) {
+ dev_err(dev, "failed to request shared USB VBUS GPIO\n");
+ return ret;
+ }
+
+ priv->ctrl_gate_clk = devm_clk_get(dev, "ctrl");
+ if (IS_ERR(priv->ctrl_gate_clk)) {
+ dev_err(dev, "Unable to get USB ctrl gate clk\n");
+ return PTR_ERR(priv->ctrl_gate_clk);
+ }
+
+ priv->phy_gate_clk = devm_clk_get(dev, "phy");
+ if (IS_ERR(priv->phy_gate_clk)) {
+ dev_err(dev, "Unable to get USB phy gate clk\n");
+ return PTR_ERR(priv->phy_gate_clk);
+ }
+
+ priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl");
+ if (IS_ERR(priv->ctrl_reset)) {
+ dev_err(dev, "failed to get 'ctrl' reset\n");
+ return PTR_ERR(priv->ctrl_reset);
+ }
+
+ priv->phy_reset = devm_reset_control_get_optional(dev, "phy");
+ if (IS_ERR(priv->phy_reset)) {
+ if (PTR_ERR(priv->phy_reset) == -EPROBE_DEFER)
+ return PTR_ERR(priv->phy_reset);
+ priv->phy_reset = NULL;
+ }
+
+ ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon", 1,
+ &priv->phy_reg_offset);
+ if (ret) {
+ dev_err(dev, "Failed to get RCU PHY reg offset\n");
+ return ret;
+ }
+
+ if (priv->reg_bits->have_ana_cfg) {
+ ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon",
+ 2, &priv->ana_cfg1_reg_offset);
+ if (ret) {
+ dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev)
+{
+ struct device_node *child, *np = pdev->dev.of_node;
+ struct ltq_rcu_usb2_priv *priv;
+ struct phy_provider *provider;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = &pdev->dev;
+ dev_set_drvdata(priv->dev, priv);
+
+ ret = ltq_rcu_usb2_of_probe(np, priv);
+ if (ret)
+ return ret;
+
+ priv->phy = devm_phy_create(&pdev->dev, child,
+ <q_rcu_usb2_phy_ops);
+ if (IS_ERR(priv->phy)) {
+ dev_err(&pdev->dev, "failed to create PHY\n");
+ return PTR_ERR(priv->phy);
+ }
+
+ phy_set_drvdata(priv->phy, priv);
+
+ ltq_rcu_usb2_start_cores(pdev);
+
+ provider = devm_of_phy_provider_register(&pdev->dev,
+ of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static struct platform_driver ltq_rcu_usb2_phy_driver = {
+ .probe = ltq_rcu_usb2_phy_probe,
+ .driver = {
+ .name = "lantiq-rcu-usb2-phy",
+ .of_match_table = ltq_rcu_usb2_phy_of_match,
+ }
+};
+module_platform_driver(ltq_rcu_usb2_phy_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
+MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
--
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* [PATCH 10/13] MIPS: lantiq: remove old GPHY loader code
From: Hauke Mehrtens @ 2017-04-17 19:29 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w, Hauke Mehrtens
In-Reply-To: <20170417192942.32219-1-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
The GPHY loader was replaced by a new more flexible driver. Remove the
old driver.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
arch/mips/lantiq/xway/Makefile | 2 -
arch/mips/lantiq/xway/reset.c | 96 -----------------------------
arch/mips/lantiq/xway/xrx200_phy_fw.c | 113 ----------------------------------
3 files changed, 211 deletions(-)
delete mode 100644 arch/mips/lantiq/xway/xrx200_phy_fw.c
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index a2edc538f477..6daf3149e7ca 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,5 +1,3 @@
obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
obj-y += vmmc.o
-
-obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 5cb9309b0047..3f30fb81a50f 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -27,18 +27,6 @@
#define RCU_RST_REQ 0x0010
/* reset status register */
#define RCU_RST_STAT 0x0014
-/* vr9 gphy registers */
-#define RCU_GFS_ADD0_XRX200 0x0020
-#define RCU_GFS_ADD1_XRX200 0x0068
-/* xRX300 gphy registers */
-#define RCU_GFS_ADD0_XRX300 0x0020
-#define RCU_GFS_ADD1_XRX300 0x0058
-#define RCU_GFS_ADD2_XRX300 0x00AC
-/* xRX330 gphy registers */
-#define RCU_GFS_ADD0_XRX330 0x0020
-#define RCU_GFS_ADD1_XRX330 0x0058
-#define RCU_GFS_ADD2_XRX330 0x00AC
-#define RCU_GFS_ADD3_XRX330 0x0264
/* xbar BE flag */
#define RCU_AHB_ENDIAN 0x004C
@@ -48,15 +36,6 @@
#define RCU_RD_GPHY0_XRX200 BIT(31)
#define RCU_RD_SRST BIT(30)
#define RCU_RD_GPHY1_XRX200 BIT(29)
-/* xRX300 bits */
-#define RCU_RD_GPHY0_XRX300 BIT(31)
-#define RCU_RD_GPHY1_XRX300 BIT(29)
-#define RCU_RD_GPHY2_XRX300 BIT(28)
-/* xRX330 bits */
-#define RCU_RD_GPHY0_XRX330 BIT(31)
-#define RCU_RD_GPHY1_XRX330 BIT(29)
-#define RCU_RD_GPHY2_XRX330 BIT(28)
-#define RCU_RD_GPHY3_XRX330 BIT(10)
/* reset cause */
#define RCU_STAT_SHIFT 26
@@ -119,81 +98,6 @@ static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
spin_unlock_irqrestore(<q_rcu_lock, flags);
}
-struct ltq_gphy_reset {
- u32 rd;
- u32 addr;
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx200_gphy[] = {
- {RCU_RD_GPHY0_XRX200, RCU_GFS_ADD0_XRX200},
- {RCU_RD_GPHY1_XRX200, RCU_GFS_ADD1_XRX200},
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx300_gphy[] = {
- {RCU_RD_GPHY0_XRX300, RCU_GFS_ADD0_XRX300},
- {RCU_RD_GPHY1_XRX300, RCU_GFS_ADD1_XRX300},
- {RCU_RD_GPHY2_XRX300, RCU_GFS_ADD2_XRX300},
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx330_gphy[] = {
- {RCU_RD_GPHY0_XRX330, RCU_GFS_ADD0_XRX330},
- {RCU_RD_GPHY1_XRX330, RCU_GFS_ADD1_XRX330},
- {RCU_RD_GPHY2_XRX330, RCU_GFS_ADD2_XRX330},
- {RCU_RD_GPHY3_XRX330, RCU_GFS_ADD3_XRX330},
-};
-
-static void xrx200_gphy_boot_addr(struct ltq_gphy_reset *phy_regs,
- dma_addr_t dev_addr)
-{
- ltq_rcu_w32_mask(0, phy_regs->rd, RCU_RST_REQ);
- ltq_rcu_w32(dev_addr, phy_regs->addr);
- ltq_rcu_w32_mask(phy_regs->rd, 0, RCU_RST_REQ);
-}
-
-/* reset and boot a gphy. these phys only exist on xrx200 SoC */
-int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
-{
- struct clk *clk;
-
- if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) {
- dev_err(dev, "this SoC has no GPHY\n");
- return -EINVAL;
- }
-
- if (of_machine_is_compatible("lantiq,vr9")) {
- clk = clk_get_sys("1f203000.rcu", "gphy");
- if (IS_ERR(clk))
- return PTR_ERR(clk);
- clk_enable(clk);
- }
-
- dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr);
-
- if (of_machine_is_compatible("lantiq,vr9")) {
- if (id >= ARRAY_SIZE(xrx200_gphy)) {
- dev_err(dev, "%u is an invalid gphy id\n", id);
- return -EINVAL;
- }
- xrx200_gphy_boot_addr(&xrx200_gphy[id], dev_addr);
- } else if (of_machine_is_compatible("lantiq,ar10")) {
- if (id >= ARRAY_SIZE(xrx300_gphy)) {
- dev_err(dev, "%u is an invalid gphy id\n", id);
- return -EINVAL;
- }
- xrx200_gphy_boot_addr(&xrx300_gphy[id], dev_addr);
- } else if (of_machine_is_compatible("lantiq,grx390")) {
- if (id >= ARRAY_SIZE(xrx330_gphy)) {
- dev_err(dev, "%u is an invalid gphy id\n", id);
- return -EINVAL;
- }
- xrx200_gphy_boot_addr(&xrx330_gphy[id], dev_addr);
- }
- return 0;
-}
-
static void ltq_machine_restart(char *command)
{
u32 val = ltq_rcu_r32(RCU_RST_REQ);
diff --git a/arch/mips/lantiq/xway/xrx200_phy_fw.c b/arch/mips/lantiq/xway/xrx200_phy_fw.c
deleted file mode 100644
index f0a0f2d431b2..000000000000
--- a/arch/mips/lantiq/xway/xrx200_phy_fw.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Lantiq XRX200 PHY Firmware Loader
- * Author: John Crispin
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2012 John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
- */
-
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/firmware.h>
-#include <linux/of_platform.h>
-
-#include <lantiq_soc.h>
-
-#define XRX200_GPHY_FW_ALIGN (16 * 1024)
-
-static dma_addr_t xway_gphy_load(struct platform_device *pdev)
-{
- const struct firmware *fw;
- dma_addr_t dev_addr = 0;
- const char *fw_name;
- void *fw_addr;
- size_t size;
-
- if (of_get_property(pdev->dev.of_node, "firmware1", NULL) ||
- of_get_property(pdev->dev.of_node, "firmware2", NULL)) {
- switch (ltq_soc_type()) {
- case SOC_TYPE_VR9:
- if (of_property_read_string(pdev->dev.of_node,
- "firmware1", &fw_name)) {
- dev_err(&pdev->dev,
- "failed to load firmware filename\n");
- return 0;
- }
- break;
- case SOC_TYPE_VR9_2:
- if (of_property_read_string(pdev->dev.of_node,
- "firmware2", &fw_name)) {
- dev_err(&pdev->dev,
- "failed to load firmware filename\n");
- return 0;
- }
- break;
- }
- } else if (of_property_read_string(pdev->dev.of_node,
- "firmware", &fw_name)) {
- dev_err(&pdev->dev, "failed to load firmware filename\n");
- return 0;
- }
-
- dev_info(&pdev->dev, "requesting %s\n", fw_name);
- if (request_firmware(&fw, fw_name, &pdev->dev)) {
- dev_err(&pdev->dev, "failed to load firmware: %s\n", fw_name);
- return 0;
- }
-
- /*
- * GPHY cores need the firmware code in a persistent and contiguous
- * memory area with a 16 kB boundary aligned start address
- */
- size = fw->size + XRX200_GPHY_FW_ALIGN;
-
- fw_addr = dma_alloc_coherent(&pdev->dev, size, &dev_addr, GFP_KERNEL);
- if (fw_addr) {
- fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
- dev_addr = ALIGN(dev_addr, XRX200_GPHY_FW_ALIGN);
- memcpy(fw_addr, fw->data, fw->size);
- } else {
- dev_err(&pdev->dev, "failed to alloc firmware memory\n");
- }
-
- release_firmware(fw);
- return dev_addr;
-}
-
-static int xway_phy_fw_probe(struct platform_device *pdev)
-{
- dma_addr_t fw_addr;
- struct property *pp;
- unsigned char *phyids;
- int i, ret = 0;
-
- fw_addr = xway_gphy_load(pdev);
- if (!fw_addr)
- return -EINVAL;
- pp = of_find_property(pdev->dev.of_node, "phys", NULL);
- if (!pp)
- return -ENOENT;
- phyids = pp->value;
- for (i = 0; i < pp->length && !ret; i++)
- ret = xrx200_gphy_boot(&pdev->dev, phyids[i], fw_addr);
- if (!ret)
- mdelay(100);
- return ret;
-}
-
-static const struct of_device_id xway_phy_match[] = {
- { .compatible = "lantiq,phy-xrx200" },
- {},
-};
-
-static struct platform_driver xway_phy_driver = {
- .probe = xway_phy_fw_probe,
- .driver = {
- .name = "phy-xrx200",
- .of_match_table = xway_phy_match,
- },
-};
-builtin_platform_driver(xway_phy_driver);
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 09/13] MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd
From: Hauke Mehrtens @ 2017-04-17 19:29 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w, Hauke Mehrtens
In-Reply-To: <20170417192942.32219-1-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Compared to the old xrx200_phy_fw driver the new version has multiple
enhancements. The name of the firmware files does not have to be added
to all .dts files anymore - one now configures the GPHY mode (FE or GE)
instead. Each GPHY can now also boot separate firmware (thus mixing of
GE and FE GPHYs is now possible).
The new implementation is based on the RCU syscon-mfd and uses the
reeset_controller framework instead of raw RCU register reads/writes.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
.../devicetree/bindings/mips/lantiq/rcu-gphy.txt | 54 +++++
arch/mips/lantiq/xway/sysctrl.c | 4 +-
drivers/soc/lantiq/Makefile | 1 +
drivers/soc/lantiq/gphy.c | 242 +++++++++++++++++++++
include/dt-bindings/mips/lantiq_rcu_gphy.h | 15 ++
5 files changed, 314 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
create mode 100644 drivers/soc/lantiq/gphy.c
create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h
diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
new file mode 100644
index 000000000000..d525c7ce9f0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
@@ -0,0 +1,54 @@
+Lantiq XWAY SoC GPHY binding
+============================
+
+This binding describes a software-defined ethernet PHY, provided by the RCU
+module on newer Lantiq XWAY SoCs (xRX200 and newer).
+This depends on binary firmware blobs which must be provided by userspace.
+
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible : Should be one of
+ "lantiq,xrx200a1x-rcu-gphy"
+ "lantiq,xrx200a2x-rcu-gphy"
+ "lantiq,xrx300-rcu-gphy"
+ "lantiq,xrx330-rcu-gphy"
+- lantiq,rcu-syscon : A phandle and offset to the GPHY address registers in
+ the RCU
+- resets : Must reference the RCU GPHY reset bit
+- reset-names : One entry, value must be "gphy" or optional "gphy2"
+
+Optional properties (port (child) node):
+- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
+ <dt-bindings/mips/lantiq_xway_gphy.h>
+- clocks : A reference to the (PMU) GPHY clock gate
+- clock-names : If clocks is given then this must be "gphy"
+
+
+-------------------------------------------------------------------------------
+Example for the GPHys on the xRX200 SoCs:
+
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+ gphy0: rcu_gphy@0 {
+ compatible = "lantiq,xrx200a2x-rcu-gphy";
+ reg = <0>;
+
+ lantiq,rcu-syscon = <&rcu0 0x20>;
+ resets = <&rcu_reset0 31>, <&rcu_reset1 7>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+ clock-names = "gphy";
+ };
+
+ gphy1: rcu_gphy@1 {
+ compatible = "lantiq,xrx200a2x-rcu-gphy";
+ reg = <0>;
+
+ lantiq,rcu-syscon = <&rcu0 0x68>;
+ resets = <&rcu_reset0 29>, <&rcu_reset1 6>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_FE>;
+ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+ clock-names = "gphy";
+ };
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 706639a343bc..5764d3ddce69 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -518,7 +518,7 @@ void __init ltq_soc_init(void)
clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
PMU_PPE_DP | PMU_PPE_TC);
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
- clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203000.rcu:rcu_gphy@0", "gphy", 1, 0, PMU_GPHY);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
@@ -541,7 +541,7 @@ void __init ltq_soc_init(void)
PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
PMU_PPE_QSB | PMU_PPE_TOP);
- clkdev_add_pmu("1f203000.rcu", "gphy", 0, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203000.rcu:rcu_gphy@0", "gphy", 0, 0, PMU_GPHY);
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
diff --git a/drivers/soc/lantiq/Makefile b/drivers/soc/lantiq/Makefile
index 7411bd23d58e..c5503183740f 100644
--- a/drivers/soc/lantiq/Makefile
+++ b/drivers/soc/lantiq/Makefile
@@ -1 +1,2 @@
obj-y += xbar.o
+obj-$(CONFIG_XRX200_PHY_FW) += gphy.o
diff --git a/drivers/soc/lantiq/gphy.c b/drivers/soc/lantiq/gphy.c
new file mode 100644
index 000000000000..4218cbd9478e
--- /dev/null
+++ b/drivers/soc/lantiq/gphy.c
@@ -0,0 +1,242 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2012 John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
+ */
+
+#include <linux/delay.h>
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+#include <linux/firmware.h>
+#include <linux/dma-mapping.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/reboot.h>
+#include <linux/reset.h>
+#include <linux/of_platform.h>
+
+#include <lantiq_soc.h>
+
+#define XRX200_GPHY_FW_ALIGN (16 * 1024)
+
+struct xway_gphy_priv {
+ struct clk *gphy_clk_gate;
+ struct reset_control *gphy_reset;
+ struct reset_control *gphy_reset2;
+ struct regmap *regmap;
+ struct notifier_block gphy_reboot_nb;
+ u32 reg_offset;
+ char *fw_name;
+};
+
+struct xway_gphy_match_data {
+ char *fe_firmware_name;
+ char *ge_firmware_name;
+};
+
+static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
+};
+
+static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
+};
+
+static const struct xway_gphy_match_data xrx300_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
+ .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
+};
+
+static const struct of_device_id xway_gphy_match[] = {
+ { .compatible = "lantiq,xrx200a1x-rcu-gphy", .data = &xrx200a1x_gphy_data },
+ { .compatible = "lantiq,xrx200a2x-rcu-gphy", .data = &xrx200a2x_gphy_data },
+ { .compatible = "lantiq,xrx300-rcu-gphy", .data = &xrx300_gphy_data },
+ { .compatible = "lantiq,xrx330-rcu-gphy", .data = &xrx300_gphy_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, xway_gphy_match);
+
+static struct xway_gphy_priv *to_xway_gphy_priv(struct notifier_block *nb)
+{
+ return container_of(nb, struct xway_gphy_priv, gphy_reboot_nb);
+}
+
+static int xway_gphy_reboot_notify(struct notifier_block *reboot_nb,
+ unsigned long code, void *unused)
+{
+ struct xway_gphy_priv *priv = to_xway_gphy_priv(reboot_nb);
+
+ if (priv) {
+ reset_control_assert(priv->gphy_reset);
+ reset_control_assert(priv->gphy_reset2);
+ }
+
+ return NOTIFY_DONE;
+}
+
+static int xway_gphy_load(struct platform_device *pdev,
+ const char *fw_name, dma_addr_t *dev_addr)
+{
+ const struct firmware *fw;
+ void *fw_addr;
+ size_t size;
+ int ret;
+
+ dev_info(&pdev->dev, "requesting %s\n", fw_name);
+ ret = request_firmware(&fw, fw_name, &pdev->dev);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to load firmware: %s, error: %i\n",
+ fw_name, ret);
+ return ret;
+ }
+
+ /*
+ * GPHY cores need the firmware code in a persistent and contiguous
+ * memory area with a 16 kB boundary aligned start address
+ */
+ size = fw->size + XRX200_GPHY_FW_ALIGN;
+
+ fw_addr = dma_alloc_coherent(&pdev->dev, size, dev_addr, GFP_KERNEL);
+ if (fw_addr) {
+ fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
+ *dev_addr = ALIGN(*dev_addr, XRX200_GPHY_FW_ALIGN);
+ memcpy(fw_addr, fw->data, fw->size);
+ } else {
+ dev_err(&pdev->dev, "failed to alloc firmware memory\n");
+ ret = -ENOMEM;
+ }
+
+ release_firmware(fw);
+
+ return ret;
+}
+
+static int xway_gphy_of_probe(struct platform_device *pdev,
+ struct xway_gphy_priv *priv)
+{
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *match = of_match_node(xway_gphy_match, np);
+ const struct xway_gphy_match_data *gphy_fw_name_cfg;
+ u32 gphy_mode;
+
+ gphy_fw_name_cfg = match->data;
+
+ /* Ignore all errors since this clock is optional. */
+ priv->gphy_clk_gate = devm_clk_get(&pdev->dev, "gphy");
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(np,
+ "lantiq,rcu-syscon");
+ if (IS_ERR(priv->regmap)) {
+ dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
+ return PTR_ERR(priv->regmap);
+ }
+
+ if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
+ &priv->reg_offset)) {
+ dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+ return -EINVAL;
+ }
+
+ priv->gphy_reset = devm_reset_control_get(&pdev->dev, "gphy");
+ if (IS_ERR_OR_NULL(priv->gphy_reset)) {
+ dev_err(&pdev->dev, "Failed to lookup gphy reset\n");
+ return PTR_ERR(priv->gphy_reset);
+ }
+
+ priv->gphy_reset2 = devm_reset_control_get_optional(&pdev->dev, "gphy2");
+ if (IS_ERR(priv->gphy_reset2)) {
+ if (PTR_ERR(priv->gphy_reset2) == -EPROBE_DEFER)
+ return PTR_ERR(priv->gphy_reset2);
+ priv->gphy_reset2 = NULL;
+ }
+
+ if (of_property_read_u32(np, "lantiq,gphy-mode", &gphy_mode))
+ /* Default to GE mode */
+ gphy_mode = GPHY_MODE_GE;
+
+ switch (gphy_mode) {
+ case GPHY_MODE_FE:
+ priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
+ break;
+ case GPHY_MODE_GE:
+ priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
+ break;
+ default:
+ dev_err(&pdev->dev, "Unknown GPHY mode %d\n", gphy_mode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int xway_gphy_probe(struct platform_device *pdev)
+{
+ struct xway_gphy_priv *priv;
+ dma_addr_t fw_addr = 0;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ ret = xway_gphy_of_probe(pdev, priv);
+ if (ret)
+ return ret;
+
+ if (!IS_ERR_OR_NULL(priv->gphy_clk_gate))
+ clk_prepare_enable(priv->gphy_clk_gate);
+
+ ret = xway_gphy_load(pdev, priv->fw_name, &fw_addr);
+ if (ret)
+ return ret;
+
+ reset_control_assert(priv->gphy_reset);
+ reset_control_assert(priv->gphy_reset2);
+
+ ret = regmap_write(priv->regmap, priv->reg_offset, fw_addr);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to configure FW addr\n");
+ return ret;
+ }
+
+ reset_control_deassert(priv->gphy_reset);
+ reset_control_deassert(priv->gphy_reset2);
+
+ /* assert the gphy reset because it can hang after a reboot: */
+ priv->gphy_reboot_nb.notifier_call = xway_gphy_reboot_notify;
+ priv->gphy_reboot_nb.priority = -1;
+
+ ret = register_reboot_notifier(&priv->gphy_reboot_nb);
+ if (ret)
+ dev_warn(&pdev->dev, "Failed to register reboot notifier\n");
+
+ platform_set_drvdata(pdev, priv);
+
+ return ret;
+}
+
+static struct platform_driver xway_gphy_driver = {
+ .probe = xway_gphy_probe,
+ .driver = {
+ .name = "xway-rcu-gphy",
+ .of_match_table = xway_gphy_match,
+ },
+};
+
+module_platform_driver(xway_gphy_driver);
+
+MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
+MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
+MODULE_LICENSE("GPL");
diff --git a/include/dt-bindings/mips/lantiq_rcu_gphy.h b/include/dt-bindings/mips/lantiq_rcu_gphy.h
new file mode 100644
index 000000000000..fa1a63773342
--- /dev/null
+++ b/include/dt-bindings/mips/lantiq_rcu_gphy.h
@@ -0,0 +1,15 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
+ */
+#ifndef _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+#define _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+
+#define GPHY_MODE_GE 1
+#define GPHY_MODE_FE 2
+
+#endif /* _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H */
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 08/13] reset: Add a reset controller driver for the Lantiq XWAY based SoCs
From: Hauke Mehrtens @ 2017-04-17 19:29 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w, Hauke Mehrtens
In-Reply-To: <20170417192942.32219-1-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
The reset controllers (on xRX200 and newer SoCs have two of them) are
provided by the RCU module. This was initially implemented as a simple
reset controller. However, the RCU module provides more functionality
(ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
The old reset controller driver implementation from
arch/mips/lantiq/xway/reset.c did not honor this fact.
For some devices the request and the status bits are different.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
.../devicetree/bindings/reset/lantiq,rcu-reset.txt | 43 ++++
arch/mips/lantiq/xway/reset.c | 68 ------
drivers/reset/Kconfig | 6 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-lantiq-rcu.c | 231 +++++++++++++++++++++
5 files changed, 281 insertions(+), 68 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
create mode 100644 drivers/reset/reset-lantiq-rcu.c
diff --git a/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
new file mode 100644
index 000000000000..7f097d16bbb7
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
@@ -0,0 +1,43 @@
+Lantiq XWAY SoC RCU reset controller binding
+============================================
+
+This binding describes a reset-controller found on the RCU module on Lantiq
+XWAY SoCs.
+
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible : Should be "lantiq,rcu-reset"
+- lantiq,rcu-syscon : A phandle to the RCU syscon, the reset register
+ offset and the status register offset.
+- #reset-cells : Specifies the number of cells needed to encode the
+ reset line, should be 1.
+
+Optional properties:
+- reset-status : The request status bit. For some bits the request bit
+ and the status bit are different. This is depending
+ on the SoC. If the reset-status bit does not match
+ the reset-request bit, put the reset number into the
+ reset-request property and the status bit at the same
+ index into the reset-status property. If no
+ reset-request bit is given here, the driver assume
+ status and request bit are the same.
+- reset-request : The reset request bit, to map it to the reset-status
+ bit.
+
+
+-------------------------------------------------------------------------------
+Example for the reset-controllers on the xRX200 SoCs:
+ rcu_reset0: rcu_reset {
+ compatible = "lantiq,rcu-reset";
+ lantiq,rcu-syscon = <&rcu0 0x10 0x14>;
+ #reset-cells = <1>;
+ reset-request = <31>, <29>, <21>, <19>, <16>, <12>;
+ reset-status = <30>, <28>, <16>, <25>, <5>, <24>;
+ };
+
+ rcu_reset1: rcu_reset {
+ compatible = "lantiq,rcu-reset";
+ lantiq,rcu-syscon = <&rcu0 0x48 0x24>;
+ #reset-cells = <1>;
+ };
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 2dedcf939901..5cb9309b0047 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -194,74 +194,6 @@ int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
return 0;
}
-/* reset a io domain for u micro seconds */
-void ltq_reset_once(unsigned int module, ulong u)
-{
- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
- udelay(u);
- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
-}
-
-static int ltq_assert_device(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- u32 val;
-
- if (id < 8)
- return -1;
-
- val = ltq_rcu_r32(RCU_RST_REQ);
- val |= BIT(id);
- ltq_rcu_w32(val, RCU_RST_REQ);
-
- return 0;
-}
-
-static int ltq_deassert_device(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- u32 val;
-
- if (id < 8)
- return -1;
-
- val = ltq_rcu_r32(RCU_RST_REQ);
- val &= ~BIT(id);
- ltq_rcu_w32(val, RCU_RST_REQ);
-
- return 0;
-}
-
-static int ltq_reset_device(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- ltq_assert_device(rcdev, id);
- return ltq_deassert_device(rcdev, id);
-}
-
-static const struct reset_control_ops reset_ops = {
- .reset = ltq_reset_device,
- .assert = ltq_assert_device,
- .deassert = ltq_deassert_device,
-};
-
-static struct reset_controller_dev reset_dev = {
- .ops = &reset_ops,
- .owner = THIS_MODULE,
- .nr_resets = 32,
- .of_reset_n_cells = 1,
-};
-
-void ltq_rst_init(void)
-{
- reset_dev.of_node = of_find_compatible_node(NULL, NULL,
- "lantiq,xway-reset");
- if (!reset_dev.of_node)
- pr_err("Failed to find reset controller node");
- else
- reset_controller_register(&reset_dev);
-}
-
static void ltq_machine_restart(char *command)
{
u32 val = ltq_rcu_r32(RCU_RST_REQ);
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index f4cdfe94b9ec..8962ba44248c 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -27,6 +27,12 @@ config RESET_BERLIN
help
This enables the reset controller driver for Marvell Berlin SoCs.
+config RESET_LANTIQ_RCU
+ bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
+ default SOC_TYPE_XWAY
+ help
+ This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
+
config RESET_LPC18XX
bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
default ARCH_LPC18XX
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 2cd3f6c45165..97b0a844b849 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
+obj-$(CONFIG_RESET_LANTIQ_RCU) += reset-lantiq-rcu.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
diff --git a/drivers/reset/reset-lantiq-rcu.c b/drivers/reset/reset-lantiq-rcu.c
new file mode 100644
index 000000000000..6178112ca5b4
--- /dev/null
+++ b/drivers/reset/reset-lantiq-rcu.c
@@ -0,0 +1,231 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
+ * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/of_platform.h>
+
+#define LANTIQ_RCU_RESET_TIMEOUT 1000000
+
+struct lantiq_rcu_reset_translation {
+ int request;
+ int status;
+};
+
+struct lantiq_rcu_reset_priv {
+ struct reset_controller_dev rcdev;
+ struct device *dev;
+ struct regmap *regmap;
+ u32 reset_offset;
+ u32 status_offset;
+ int trans_number;
+ struct lantiq_rcu_reset_translation *trans;
+};
+
+static struct lantiq_rcu_reset_priv *to_lantiq_rcu_reset_priv(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct lantiq_rcu_reset_priv, rcdev);
+}
+
+static int lantiq_rcu_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
+ u32 val;
+ int ret, i;
+
+ if (id >= rcdev->nr_resets)
+ return -EINVAL;
+
+ for (i = 0; i < priv->trans_number; i++) {
+ if (id == priv->trans[i].request) {
+ id = priv->trans[i].status;
+ break;
+ }
+ }
+
+ ret = regmap_read(priv->regmap, priv->status_offset, &val);
+ if (ret)
+ return ret;
+
+ return !!(val & BIT(id));
+}
+
+static int lantiq_rcu_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
+ u32 val;
+ int ret, retry = LANTIQ_RCU_RESET_TIMEOUT;
+
+ if (id >= rcdev->nr_resets)
+ return -EINVAL;
+
+ if (assert)
+ val = BIT(id);
+ else
+ val = 0;
+
+ ret = regmap_update_bits(priv->regmap, priv->reset_offset, BIT(id),
+ val);
+ if (ret) {
+ dev_err(priv->dev, "Failed to set reset bit %lu\n", id);
+ return ret;
+ }
+
+ do {} while (--retry && lantiq_rcu_reset_status(rcdev, id) != assert);
+ if (!retry) {
+ dev_err(priv->dev, "Failed to %s bit %lu\n",
+ assert ? "assert" : "deassert", id);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int lantiq_rcu_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return lantiq_rcu_reset_update(rcdev, id, true);
+}
+
+static int lantiq_rcu_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return lantiq_rcu_reset_update(rcdev, id, false);
+}
+
+static int lantiq_rcu_reset_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ int ret;
+
+ ret = lantiq_rcu_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ return lantiq_rcu_reset_deassert(rcdev, id);
+}
+
+static struct reset_control_ops lantiq_rcu_reset_ops = {
+ .assert = lantiq_rcu_reset_assert,
+ .deassert = lantiq_rcu_reset_deassert,
+ .status = lantiq_rcu_reset_status,
+ .reset = lantiq_rcu_reset_reset,
+};
+
+static int lantiq_rcu_reset_of_probe(struct platform_device *pdev,
+ struct lantiq_rcu_reset_priv *priv)
+{
+ struct device_node *np = pdev->dev.of_node;
+ int cnt, i, ret;
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(np,
+ "lantiq,rcu-syscon");
+ if (IS_ERR(priv->regmap)) {
+ dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
+ return PTR_ERR(priv->regmap);
+ }
+
+ if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
+ &priv->reset_offset)) {
+ dev_err(&pdev->dev, "Failed to get RCU reset offset\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 2,
+ &priv->status_offset)) {
+ dev_err(&pdev->dev, "Failed to get RCU status offset\n");
+ return -EINVAL;
+ }
+
+ cnt = of_property_count_elems_of_size(np, "reset-request", sizeof(u32));
+ if (cnt <= 0)
+ return 0;
+
+ priv->trans = devm_kmalloc_array(&pdev->dev, cnt, sizeof(*priv->trans),
+ GFP_KERNEL);
+ if (!priv->trans)
+ return -ENOMEM;
+
+ for (i = 0; i < cnt; i++) {
+ ret = of_property_read_u32_index(np, "reset-request", i,
+ &priv->trans[i].request);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Failed to get reset-request at index %i\n",
+ i);
+ return ret;
+ }
+ ret = of_property_read_u32_index(np, "reset-status", i,
+ &priv->trans[i].status);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Failed to get reset-status at index %i\n",
+ i);
+ return ret;
+ }
+ }
+ priv->trans_number = cnt;
+
+ return 0;
+}
+
+static int lantiq_rcu_reset_probe(struct platform_device *pdev)
+{
+ struct lantiq_rcu_reset_priv *priv;
+ int err;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = &pdev->dev;
+ platform_set_drvdata(pdev, priv);
+
+ err = lantiq_rcu_reset_of_probe(pdev, priv);
+ if (err)
+ return err;
+
+ priv->rcdev.ops = &lantiq_rcu_reset_ops;
+ priv->rcdev.owner = THIS_MODULE;
+ priv->rcdev.of_node = pdev->dev.of_node;
+ priv->rcdev.of_reset_n_cells = 1;
+ priv->rcdev.nr_resets = 32;
+
+ err = reset_controller_register(&priv->rcdev);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static const struct of_device_id lantiq_rcu_reset_dt_ids[] = {
+ { .compatible = "lantiq,rcu-reset", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, lantiq_rcu_reset_dt_ids);
+
+static struct platform_driver lantiq_rcu_reset_driver = {
+ .probe = lantiq_rcu_reset_probe,
+ .driver = {
+ .name = "lantiq-rcu-reset",
+ .of_match_table = lantiq_rcu_reset_dt_ids,
+ },
+};
+module_platform_driver(lantiq_rcu_reset_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
+MODULE_DESCRIPTION("Lantiq XWAY RCU Reset Controller Driver");
+MODULE_LICENSE("GPL");
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 07/13] MIPS: lantiq: remove ltq_reset_cause() and ltq_boot_select()
From: Hauke Mehrtens @ 2017-04-17 19:29 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w, Hauke Mehrtens
In-Reply-To: <20170417192942.32219-1-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Do not export the ltq_reset_cause() and ltq_boot_select() function any
more. ltq_reset_cause() was accessed by the watchdog driver before to
see why the last reset happened, this is now done through direct access
of the register over regmap. The bits in this register are anyway
different between the xrx200 and the falcon SoC.
ltq_boot_select() is not used any more and was used by the flash
drivers to check if the system was booted from this flash type, now the
drivers should depend on the device tree only.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
arch/mips/include/asm/mach-lantiq/lantiq.h | 4 ----
arch/mips/lantiq/falcon/reset.c | 22 ----------------------
arch/mips/lantiq/xway/reset.c | 19 -------------------
3 files changed, 45 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index 8064d7a4b33d..fa045b4c0cdd 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -44,10 +44,6 @@ extern struct clk *clk_get_fpi(void);
extern struct clk *clk_get_io(void);
extern struct clk *clk_get_ppe(void);
-/* find out what bootsource we have */
-extern unsigned char ltq_boot_select(void);
-/* find out what caused the last cpu reset */
-extern int ltq_reset_cause(void);
/* find out the soc type */
extern int ltq_soc_type(void);
diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
index 7a535d72f541..722114d7409d 100644
--- a/arch/mips/lantiq/falcon/reset.c
+++ b/arch/mips/lantiq/falcon/reset.c
@@ -15,28 +15,6 @@
#include <lantiq_soc.h>
-/* CPU0 Reset Source Register */
-#define SYS1_CPU0RS 0x0040
-/* reset cause mask */
-#define CPU0RS_MASK 0x0003
-/* CPU0 Boot Mode Register */
-#define SYS1_BM 0x00a0
-/* boot mode mask */
-#define BM_MASK 0x0005
-
-/* allow platform code to find out what surce we booted from */
-unsigned char ltq_boot_select(void)
-{
- return ltq_sys1_r32(SYS1_BM) & BM_MASK;
-}
-
-/* allow the watchdog driver to find out what the boot reason was */
-int ltq_reset_cause(void)
-{
- return ltq_sys1_r32(SYS1_CPU0RS) & CPU0RS_MASK;
-}
-EXPORT_SYMBOL_GPL(ltq_reset_cause);
-
#define BOOT_REG_BASE (KSEG1 | 0x1F200000)
#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20)
#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24)
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index b6752c95a600..2dedcf939901 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -119,25 +119,6 @@ static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
spin_unlock_irqrestore(<q_rcu_lock, flags);
}
-/* This function is used by the watchdog driver */
-int ltq_reset_cause(void)
-{
- u32 val = ltq_rcu_r32(RCU_RST_STAT);
- return val >> RCU_STAT_SHIFT;
-}
-EXPORT_SYMBOL_GPL(ltq_reset_cause);
-
-/* allow platform code to find out what source we booted from */
-unsigned char ltq_boot_select(void)
-{
- u32 val = ltq_rcu_r32(RCU_RST_STAT);
-
- if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
- return RCU_BOOT_SEL_XRX200(val);
-
- return RCU_BOOT_SEL(val);
-}
-
struct ltq_gphy_reset {
u32 rd;
u32 addr;
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 06/13] MIPS: lantiq: Convert the xbar driver to a platform_driver
From: Hauke Mehrtens @ 2017-04-17 19:29 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w, Hauke Mehrtens
In-Reply-To: <20170417192942.32219-1-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This allows using the xbar driver on ARX300 based SoCs which require the
same xbar setup as the xRX200 chipsets because the xbar driver
initialization is not guarded by an xRX200 specific
of_machine_is_compatible condition anymore. Additionally the new driver
takes a syscon phandle to configure the XBAR endianness bits in RCU
(before this was done in arch/mips/lantiq/xway/reset.c and also
guarded by an xRX200 specific if-statement).
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
.../devicetree/bindings/mips/lantiq/xbar.txt | 22 +++++
MAINTAINERS | 1 +
arch/mips/lantiq/xway/reset.c | 4 -
arch/mips/lantiq/xway/sysctrl.c | 41 ---------
drivers/soc/Makefile | 1 +
drivers/soc/lantiq/Makefile | 1 +
drivers/soc/lantiq/xbar.c | 100 +++++++++++++++++++++
7 files changed, 125 insertions(+), 45 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
create mode 100644 drivers/soc/lantiq/Makefile
create mode 100644 drivers/soc/lantiq/xbar.c
diff --git a/Documentation/devicetree/bindings/mips/lantiq/xbar.txt b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
new file mode 100644
index 000000000000..86e53ff3b0d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
@@ -0,0 +1,22 @@
+Lantiq XWAY SoC XBAR binding
+============================
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be "lantiq,xbar-xway"
+- reg : The address and length of the XBAR registers
+
+Optional properties:
+- lantiq,rcu-syscon : A phandle and offset to the endianness configuration
+ registers in the RCU module
+
+
+-------------------------------------------------------------------------------
+Example for the XBAR on the xRX200 SoCs:
+ xbar0: xbar@400000 {
+ compatible = "lantiq,xbar-xway";
+ reg = <0x400000 0x1000>;
+ big-endian;
+ lantiq,rcu-syscon = <&rcu0 0x4c>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 676c139bc883..7c03776a56e9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7321,6 +7321,7 @@ M: John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
L: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
S: Maintained
F: arch/mips/lantiq
+F: drivers/soc/lantiq
LAPB module
L: linux-x25-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 83fd65d76e81..b6752c95a600 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -373,10 +373,6 @@ static int __init mips_reboot_setup(void)
of_machine_is_compatible("lantiq,vr9"))
ltq_usb_init();
- if (of_machine_is_compatible("lantiq,vr9"))
- ltq_rcu_w32(ltq_rcu_r32(RCU_AHB_ENDIAN) | RCU_VR9_BE_AHB1S,
- RCU_AHB_ENDIAN);
-
_machine_restart = ltq_machine_restart;
_machine_halt = ltq_machine_halt;
pm_power_off = ltq_machine_power_off;
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 95bec460b651..706639a343bc 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -145,15 +145,7 @@ static u32 pmu_clk_cr_b[] = {
#define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y))
#define pmu_r32(x) ltq_r32(pmu_membase + (x))
-#define XBAR_ALWAYS_LAST 0x430
-#define XBAR_FPI_BURST_EN BIT(1)
-#define XBAR_AHB_BURST_EN BIT(2)
-
-#define xbar_w32(x, y) ltq_w32((x), ltq_xbar_membase + (y))
-#define xbar_r32(x) ltq_r32(ltq_xbar_membase + (x))
-
static void __iomem *pmu_membase;
-static void __iomem *ltq_xbar_membase;
void __iomem *ltq_cgu_membase;
void __iomem *ltq_ebu_membase;
@@ -293,16 +285,6 @@ static void pci_ext_disable(struct clk *clk)
ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
}
-static void xbar_fpi_burst_disable(void)
-{
- u32 reg;
-
- /* bit 1 as 1 --burst; bit 1 as 0 -- single */
- reg = xbar_r32(XBAR_ALWAYS_LAST);
- reg &= ~XBAR_FPI_BURST_EN;
- xbar_w32(reg, XBAR_ALWAYS_LAST);
-}
-
/* enable a clockout source */
static int clkout_enable(struct clk *clk)
{
@@ -459,26 +441,6 @@ void __init ltq_soc_init(void)
if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
panic("Failed to remap core resources");
- if (of_machine_is_compatible("lantiq,vr9")) {
- struct resource res_xbar;
- struct device_node *np_xbar =
- of_find_compatible_node(NULL, NULL,
- "lantiq,xbar-xway");
-
- if (!np_xbar)
- panic("Failed to load xbar nodes from devicetree");
- if (of_address_to_resource(np_xbar, 0, &res_xbar))
- panic("Failed to get xbar resources");
- if (!request_mem_region(res_xbar.start, resource_size(&res_xbar),
- res_xbar.name))
- panic("Failed to get xbar resources");
-
- ltq_xbar_membase = ioremap_nocache(res_xbar.start,
- resource_size(&res_xbar));
- if (!ltq_xbar_membase)
- panic("Failed to remap xbar resources");
- }
-
/* make sure to unprotect the memory region where flash is located */
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
@@ -605,7 +567,4 @@ void __init ltq_soc_init(void)
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
}
-
- if (of_machine_is_compatible("lantiq,vr9"))
- xbar_fpi_burst_disable();
}
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 05eae52a30b4..8775d37ac158 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -6,6 +6,7 @@ obj-y += bcm/
obj-$(CONFIG_ARCH_DOVE) += dove/
obj-$(CONFIG_MACH_DOVE) += dove/
obj-y += fsl/
+obj-$(CONFIG_SOC_XWAY) += lantiq/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_ARCH_RENESAS) += renesas/
diff --git a/drivers/soc/lantiq/Makefile b/drivers/soc/lantiq/Makefile
new file mode 100644
index 000000000000..7411bd23d58e
--- /dev/null
+++ b/drivers/soc/lantiq/Makefile
@@ -0,0 +1 @@
+obj-y += xbar.o
diff --git a/drivers/soc/lantiq/xbar.c b/drivers/soc/lantiq/xbar.c
new file mode 100644
index 000000000000..dcd087817435
--- /dev/null
+++ b/drivers/soc/lantiq/xbar.c
@@ -0,0 +1,100 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2011-2015 John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ */
+
+#include <linux/ioport.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+
+#include <lantiq_soc.h>
+
+#define XBAR_ALWAYS_LAST 0x430
+#define XBAR_FPI_BURST_EN BIT(1)
+#define XBAR_AHB_BURST_EN BIT(2)
+
+#define RCU_VR9_BE_AHB1S 0x00000008
+
+static int ltq_xbar_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct resource res_xbar;
+ struct regmap *rcu_regmap;
+ void __iomem *xbar_membase;
+ u32 rcu_ahb_endianness_reg_offset;
+ u32 rcu_ahb_endianness_val;
+ int ret;
+
+ ret = of_address_to_resource(np, 0, &res_xbar);
+ if (ret) {
+ dev_err(dev, "Failed to get xbar resources");
+ return ret;
+ }
+
+ if (!devm_request_mem_region(dev, res_xbar.start,
+ resource_size(&res_xbar),
+ res_xbar.name)) {
+ dev_err(dev, "Failed to get xbar resources");
+ return -ENODEV;
+ }
+
+ xbar_membase = devm_ioremap_nocache(dev, res_xbar.start,
+ resource_size(&res_xbar));
+ if (!xbar_membase) {
+ dev_err(dev, "Failed to remap xbar resources");
+ return -ENODEV;
+ }
+
+ /* RCU configuration is optional */
+ rcu_regmap = syscon_regmap_lookup_by_phandle(np, "lantiq,rcu-syscon");
+ if (!IS_ERR_OR_NULL(rcu_regmap)) {
+ if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
+ &rcu_ahb_endianness_reg_offset)) {
+ dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+ return -EINVAL;
+ }
+
+ if (of_device_is_big_endian(np))
+ rcu_ahb_endianness_val = RCU_VR9_BE_AHB1S;
+ else
+ rcu_ahb_endianness_val = 0;
+
+ if (regmap_update_bits(rcu_regmap,
+ rcu_ahb_endianness_reg_offset,
+ RCU_VR9_BE_AHB1S,
+ rcu_ahb_endianness_val))
+ dev_warn(&pdev->dev,
+ "Failed to configure RCU AHB endianness\n");
+ }
+
+ /* disable fpi burst */
+ ltq_w32_mask(XBAR_FPI_BURST_EN, 0,
+ xbar_membase + XBAR_ALWAYS_LAST);
+
+ return 0;
+}
+
+static const struct of_device_id xbar_match[] = {
+ { .compatible = "lantiq,xbar-xway" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, xbar_match);
+
+static struct platform_driver xbar_driver = {
+ .probe = ltq_xbar_probe,
+ .driver = {
+ .name = "xbar-xway",
+ .of_match_table = xbar_match,
+ },
+};
+
+builtin_platform_driver(xbar_driver);
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 05/13] MIPS: lantiq: Enable MFD_SYSCON to be able to use it for the RCU MFD
From: Hauke Mehrtens @ 2017-04-17 19:29 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w, Hauke Mehrtens
In-Reply-To: <20170417192942.32219-1-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
arch/mips/lantiq/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index 177769dbb0e8..f5db4a426568 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -17,6 +17,7 @@ config SOC_XWAY
bool "XWAY"
select SOC_TYPE_XWAY
select HW_HAS_PCI
+ select MFD_SYSCON
config SOC_FALCON
bool "FALCON"
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 04/13] watchdog: lantiq: access boot cause register through regmap
From: Hauke Mehrtens @ 2017-04-17 19:29 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w, Hauke Mehrtens
In-Reply-To: <20170417192942.32219-1-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
This patch avoids accessing the function ltq_reset_cause() and directly
accesses the register given over the syscon interface. The syscon
interface will be implemented for the xway SoCs for the falcon SoCs the
ltq_reset_cause() function never worked, because a wrong offset was used.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
drivers/watchdog/lantiq_wdt.c | 47 +++++++++++++++++++++++++++++++++++++++----
1 file changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
index e0823677d8c1..0e349ad03fdf 100644
--- a/drivers/watchdog/lantiq_wdt.c
+++ b/drivers/watchdog/lantiq_wdt.c
@@ -17,9 +17,14 @@
#include <linux/uaccess.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
#include <lantiq_soc.h>
+#define LTQ_RST_CAUSE_WDT_XRX BIT(31)
+#define LTQ_RST_CAUSE_WDT_FALCON 0x02
+
/*
* Section 3.4 of the datasheet
* The password sequence protects the WDT control register from unintended
@@ -186,6 +191,40 @@ static struct miscdevice ltq_wdt_miscdev = {
.fops = <q_wdt_fops,
};
+static void ltq_set_wdt_bootstatus(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct regmap *rcu_regmap;
+ u32 status_reg_offset;
+ u32 val;
+ int err;
+
+ rcu_regmap = syscon_regmap_lookup_by_phandle(np,
+ "lantiq,rcu-syscon");
+ if (IS_ERR_OR_NULL(rcu_regmap))
+ return;
+
+ err = of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
+ &status_reg_offset);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+ return;
+ }
+
+ err = regmap_read(rcu_regmap, status_reg_offset, &val);
+ if (err)
+ return;
+
+ /* find out if the watchdog caused the last reboot */
+ if (of_device_is_compatible(np, "lantiq,wdt-xrx100")) {
+ if (val & LTQ_RST_CAUSE_WDT_XRX)
+ ltq_wdt_bootstatus = WDIOF_CARDRESET;
+ } else if (of_device_is_compatible(np, "lantiq,wdt-falcon")) {
+ if ((val & 0x7) == LTQ_RST_CAUSE_WDT_FALCON)
+ ltq_wdt_bootstatus = WDIOF_CARDRESET;
+ }
+}
+
static int
ltq_wdt_probe(struct platform_device *pdev)
{
@@ -205,9 +244,7 @@ ltq_wdt_probe(struct platform_device *pdev)
ltq_io_region_clk_rate = clk_get_rate(clk);
clk_put(clk);
- /* find out if the watchdog caused the last reboot */
- if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST)
- ltq_wdt_bootstatus = WDIOF_CARDRESET;
+ ltq_set_wdt_bootstatus(pdev);
dev_info(&pdev->dev, "Init done\n");
return misc_register(<q_wdt_miscdev);
@@ -222,7 +259,9 @@ ltq_wdt_remove(struct platform_device *pdev)
}
static const struct of_device_id ltq_wdt_match[] = {
- { .compatible = "lantiq,wdt" },
+ { .compatible = "lantiq,wdt"},
+ { .compatible = "lantiq,wdt-xrx100"},
+ { .compatible = "lantiq,wdt-falcon"},
{},
};
MODULE_DEVICE_TABLE(of, ltq_wdt_match);
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 03/13] mtd: spi-falcon: drop check of boot select
From: Hauke Mehrtens @ 2017-04-17 19:29 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w, Hauke Mehrtens
In-Reply-To: <20170417192942.32219-1-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Do not check which flash type the SoC was booted from before
using this driver. Assume that the device tree is correct and use this
driver when it was added to device tree. This also removes a build
dependency to the SoC code.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
drivers/spi/spi-falcon.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index 286b2c81fc6b..f8638e82e5db 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -395,11 +395,6 @@ static int falcon_sflash_probe(struct platform_device *pdev)
struct spi_master *master;
int ret;
- if (ltq_boot_select() != BS_SPI) {
- dev_err(&pdev->dev, "invalid bootstrap options\n");
- return -ENODEV;
- }
-
master = spi_alloc_master(&pdev->dev, sizeof(*priv));
if (!master)
return -ENOMEM;
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 02/13] mtd: lantiq-flash: drop check of boot select
From: Hauke Mehrtens @ 2017-04-17 19:29 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w, Hauke Mehrtens
In-Reply-To: <20170417192942.32219-1-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Do not check which flash type the SoC was booted from before
using this driver. Assume that the device tree is correct and use this
driver when it was added to device tree. This also removes a build
dependency to the SoC code.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
drivers/mtd/maps/lantiq-flash.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c
index 3e33ab66eb24..77b1d8013295 100644
--- a/drivers/mtd/maps/lantiq-flash.c
+++ b/drivers/mtd/maps/lantiq-flash.c
@@ -114,12 +114,6 @@ ltq_mtd_probe(struct platform_device *pdev)
struct cfi_private *cfi;
int err;
- if (of_machine_is_compatible("lantiq,falcon") &&
- (ltq_boot_select() != BS_FLASH)) {
- dev_err(&pdev->dev, "invalid bootstrap options\n");
- return -ENODEV;
- }
-
ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL);
if (!ltq_mtd)
return -ENOMEM;
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 01/13] MIPS: lantiq: Use of_platform_populate instead of __dt_register_buses
From: Hauke Mehrtens @ 2017-04-17 19:29 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w, Hauke Mehrtens
In-Reply-To: <20170417192942.32219-1-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This allows populating syscon devices which are using "simple-mfd"
instead of "simple-bus".
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
arch/mips/lantiq/prom.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 96773bed8a8a..72cc12f1b6a5 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -117,7 +117,8 @@ void __init prom_init(void)
int __init plat_of_setup(void)
{
- return __dt_register_buses(soc_info.compatible, "simple-bus");
+ return of_platform_populate(NULL, of_default_bus_match_table, NULL,
+ NULL);
}
arch_initcall(plat_of_setup);
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 00/13] MIPS: lantiq: handle RCU register by separate drivers
From: Hauke Mehrtens @ 2017-04-17 19:29 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w, Hauke Mehrtens
The RCU (Reset controller Unit) register block provides many different
functionalities. Before they were handed by the code in arch/mips/lantiq
/xway/reset.c, now there are separate drivers for the functionality.
This block provides support for reset controller, GPHY firmware
loading, USB PHY initialization and cross bar configuration.
These changes are making the old device tree incompatible with the
current kernel. The upstream Linux kernel supports loading the device
tree blob from the boot loader since about one year, the latest
released vendor kernel does not support loading the device tree from a
bot loader.
I would prefer if this would go through the mips tree.
There are more patches planed which would convert the Lantiq code
to the common clock framework.
Hauke Mehrtens (4):
mtd: lantiq-flash: drop check of boot select
mtd: spi-falcon: drop check of boot select
watchdog: lantiq: access boot cause register through regmap
MIPS: lantiq: remove old GPHY loader code
Martin Blumenstingl (9):
MIPS: lantiq: Use of_platform_populate instead of __dt_register_buses
MIPS: lantiq: Enable MFD_SYSCON to be able to use it for the RCU MFD
MIPS: lantiq: Convert the xbar driver to a platform_driver
MIPS: lantiq: remove ltq_reset_cause() and ltq_boot_select()
reset: Add a reset controller driver for the Lantiq XWAY based SoCs
MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd
phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings
MIPS: lantiq: Remove the arch/mips/lantiq/xway/reset.c implementation
.../devicetree/bindings/mips/lantiq/rcu-gphy.txt | 54 +++
.../devicetree/bindings/mips/lantiq/rcu.txt | 82 +++++
.../devicetree/bindings/mips/lantiq/xbar.txt | 22 ++
.../bindings/phy/phy-lantiq-rcu-usb2.txt | 59 ++++
.../devicetree/bindings/reset/lantiq,rcu-reset.txt | 43 +++
MAINTAINERS | 1 +
arch/mips/include/asm/mach-lantiq/lantiq.h | 4 -
arch/mips/lantiq/Kconfig | 2 +
arch/mips/lantiq/falcon/reset.c | 22 --
arch/mips/lantiq/prom.c | 3 +-
arch/mips/lantiq/xway/Makefile | 4 +-
arch/mips/lantiq/xway/reset.c | 387 ---------------------
arch/mips/lantiq/xway/sysctrl.c | 69 +---
arch/mips/lantiq/xway/xrx200_phy_fw.c | 113 ------
drivers/mtd/maps/lantiq-flash.c | 6 -
drivers/phy/Kconfig | 8 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-lantiq-rcu-usb2.c | 325 +++++++++++++++++
drivers/reset/Kconfig | 6 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-lantiq-rcu.c | 231 ++++++++++++
drivers/soc/Makefile | 1 +
drivers/soc/lantiq/Makefile | 2 +
drivers/soc/lantiq/gphy.c | 242 +++++++++++++
drivers/soc/lantiq/xbar.c | 100 ++++++
drivers/spi/spi-falcon.c | 5 -
drivers/watchdog/lantiq_wdt.c | 47 ++-
include/dt-bindings/mips/lantiq_rcu_gphy.h | 15 +
28 files changed, 1255 insertions(+), 600 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
delete mode 100644 arch/mips/lantiq/xway/reset.c
delete mode 100644 arch/mips/lantiq/xway/xrx200_phy_fw.c
create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
create mode 100644 drivers/reset/reset-lantiq-rcu.c
create mode 100644 drivers/soc/lantiq/Makefile
create mode 100644 drivers/soc/lantiq/gphy.c
create mode 100644 drivers/soc/lantiq/xbar.c
create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h
--
2.11.0
--
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^ permalink raw reply
* [PATCH v3 2/2] phy: meson: add USB2 PHY support for Meson GXL and GXM
From: Martin Blumenstingl @ 2017-04-17 19:11 UTC (permalink / raw)
To: kishon-l0cyMroinI0,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
carlo-KA+7E9HrN00dnm+yROfE0A, khilman-rdvid1DuHRBWk0Htik3J/w
Cc: mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
hendrik-MJglGmTD+GWCT0AhDRffsw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
Martin Blumenstingl
In-Reply-To: <20170417191142.26099-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs
(both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure
the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for this PHY. The driver
was written by reading the code from Amlogic's GPL kernel sources and
by analyzing the registers on an actual GXL and GXM device running the
kernel that was shipped on the boards I have.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
drivers/phy/Kconfig | 12 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-meson-gxl-usb2.c | 261 +++++++++++++++++++++++++++++++++++++++
3 files changed, 274 insertions(+)
create mode 100644 drivers/phy/phy-meson-gxl-usb2.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 005cadb7a3f8..fada8354c0fe 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -511,4 +511,16 @@ config PHY_MESON8B_USB2
and GXBB SoCs.
If unsure, say N.
+config PHY_MESON_GXL_USB
+ tristate "Meson GXL and GXM USB2 PHY drivers"
+ default ARCH_MESON
+ depends on OF && (ARCH_MESON || COMPILE_TEST)
+ depends on USB_SUPPORT
+ select GENERIC_PHY
+ select REGMAP_MMIO
+ help
+ Enable this to support the Meson USB2 PHYs found in Meson
+ GXL and GXM SoCs.
+ If unsure, say N.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index dd8f3b5d2918..4f5ede46b0b9 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -62,3 +62,4 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
+obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.o
diff --git a/drivers/phy/phy-meson-gxl-usb2.c b/drivers/phy/phy-meson-gxl-usb2.c
new file mode 100644
index 000000000000..f5fbd3c09542
--- /dev/null
+++ b/drivers/phy/phy-meson-gxl-usb2.c
@@ -0,0 +1,261 @@
+/*
+ * Meson GXL and GXM USB2 PHY driver
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+/* bits [31:27] are read-only */
+#define U2P_R0 0x0
+ #define U2P_R0_BYPASS_SEL BIT(0)
+ #define U2P_R0_BYPASS_DM_EN BIT(1)
+ #define U2P_R0_BYPASS_DP_EN BIT(2)
+ #define U2P_R0_TXBITSTUFF_ENH BIT(3)
+ #define U2P_R0_TXBITSTUFF_EN BIT(4)
+ #define U2P_R0_DM_PULLDOWN BIT(5)
+ #define U2P_R0_DP_PULLDOWN BIT(6)
+ #define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7)
+ #define U2P_R0_DP_VBUS_VLD_EXT BIT(8)
+ #define U2P_R0_ADP_PRB_EN BIT(9)
+ #define U2P_R0_ADP_DISCHARGE BIT(10)
+ #define U2P_R0_ADP_CHARGE BIT(11)
+ #define U2P_R0_DRV_VBUS BIT(12)
+ #define U2P_R0_ID_PULLUP BIT(13)
+ #define U2P_R0_LOOPBACK_EN_B BIT(14)
+ #define U2P_R0_OTG_DISABLE BIT(15)
+ #define U2P_R0_COMMON_ONN BIT(16)
+ #define U2P_R0_FSEL_MASK GENMASK(19, 17)
+ #define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)
+ #define U2P_R0_POWER_ON_RESET BIT(22)
+ #define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)
+ #define U2P_R0_ID_SET_ID_DQ BIT(25)
+ #define U2P_R0_ATE_RESET BIT(26)
+ #define U2P_R0_FSV_MINUS BIT(27)
+ #define U2P_R0_FSV_PLUS BIT(28)
+ #define U2P_R0_BYPASS_DM_DATA BIT(29)
+ #define U2P_R0_BYPASS_DP_DATA BIT(30)
+
+#define U2P_R1 0x4
+ #define U2P_R1_BURN_IN_TEST BIT(0)
+ #define U2P_R1_ACA_ENABLE BIT(1)
+ #define U2P_R1_DCD_ENABLE BIT(2)
+ #define U2P_R1_VDAT_SRC_EN_B BIT(3)
+ #define U2P_R1_VDAT_DET_EN_B BIT(4)
+ #define U2P_R1_CHARGES_SEL BIT(5)
+ #define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6)
+ #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)
+ #define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)
+ #define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)
+ #define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)
+ #define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)
+ #define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)
+ #define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)
+ #define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26)
+ #define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29)
+
+/* bits [31:14] are read-only */
+#define U2P_R2 0x8
+ #define U2P_R2_DATA_IN_MASK GENMASK(3, 0)
+ #define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4)
+ #define U2P_R2_ADDR_MASK GENMASK(11, 8)
+ #define U2P_R2_DATA_OUT_SEL BIT(12)
+ #define U2P_R2_CLK BIT(13)
+ #define U2P_R2_DATA_OUT_MASK GENMASK(17, 14)
+ #define U2P_R2_ACA_PIN_RANGE_C BIT(18)
+ #define U2P_R2_ACA_PIN_RANGE_B BIT(19)
+ #define U2P_R2_ACA_PIN_RANGE_A BIT(20)
+ #define U2P_R2_ACA_PIN_GND BIT(21)
+ #define U2P_R2_ACA_PIN_FLOAT BIT(22)
+ #define U2P_R2_CHARGE_DETECT BIT(23)
+ #define U2P_R2_DEVICE_SESSION_VALID BIT(24)
+ #define U2P_R2_ADP_PROBE BIT(25)
+ #define U2P_R2_ADP_SENSE BIT(26)
+ #define U2P_R2_SESSION_END BIT(27)
+ #define U2P_R2_VBUS_VALID BIT(28)
+ #define U2P_R2_B_VALID BIT(29)
+ #define U2P_R2_A_VALID BIT(30)
+ #define U2P_R2_ID_DIG BIT(31)
+
+#define U2P_R3 0xc
+
+#define RESET_COMPLETE_TIME 500
+
+struct phy_meson_gxl_usb2_priv {
+ struct regmap *regmap;
+ enum phy_mode mode;
+ int is_enabled;
+};
+
+static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = U2P_R3,
+};
+
+static int phy_meson_gxl_usb2_reset(struct phy *phy)
+{
+ struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
+
+ if (!priv->is_enabled)
+ return 0;
+
+ /* reset the PHY and wait until settings are stabilized */
+ regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET,
+ U2P_R0_POWER_ON_RESET);
+ udelay(RESET_COMPLETE_TIME);
+ regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET, 0);
+ udelay(RESET_COMPLETE_TIME);
+
+ return 0;
+}
+
+static int phy_meson_gxl_usb2_set_mode(struct phy *phy, enum phy_mode mode)
+{
+ struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
+
+ switch (mode) {
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_OTG:
+ regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DM_PULLDOWN,
+ U2P_R0_DM_PULLDOWN);
+ regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DP_PULLDOWN,
+ U2P_R0_DP_PULLDOWN);
+ regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_ID_PULLUP, 0);
+ break;
+
+ case PHY_MODE_USB_DEVICE:
+ regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DM_PULLDOWN,
+ 0);
+ regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DP_PULLDOWN,
+ 0);
+ regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_ID_PULLUP,
+ U2P_R0_ID_PULLUP);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ phy_meson_gxl_usb2_reset(phy);
+
+ priv->mode = mode;
+
+ return 0;
+}
+
+static int phy_meson_gxl_usb2_power_off(struct phy *phy)
+{
+ struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
+
+ priv->is_enabled = 0;
+
+ /* power off the PHY by putting it into reset mode */
+ regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET,
+ U2P_R0_POWER_ON_RESET);
+
+ return 0;
+}
+
+static int phy_meson_gxl_usb2_power_on(struct phy *phy)
+{
+ struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
+ int ret;
+
+ priv->is_enabled = 1;
+
+ /* power on the PHY by taking it out of reset mode */
+ regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET, 0);
+
+ ret = phy_meson_gxl_usb2_set_mode(phy, priv->mode);
+ if (ret) {
+ phy_meson_gxl_usb2_power_off(phy);
+
+ dev_err(&phy->dev, "Failed to initialize PHY with mode %d\n",
+ priv->mode);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct phy_ops phy_meson_gxl_usb2_ops = {
+ .power_on = phy_meson_gxl_usb2_power_on,
+ .power_off = phy_meson_gxl_usb2_power_off,
+ .set_mode = phy_meson_gxl_usb2_set_mode,
+ .reset = phy_meson_gxl_usb2_reset,
+ .owner = THIS_MODULE,
+};
+
+static int phy_meson_gxl_usb2_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *phy_provider;
+ struct resource *res;
+ struct phy_meson_gxl_usb2_priv *priv;
+ struct phy *phy;
+ void __iomem *base;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, priv);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->mode = PHY_MODE_USB_HOST;
+
+ priv->regmap = devm_regmap_init_mmio(dev, base,
+ &phy_meson_gxl_usb2_regmap_conf);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ phy = devm_phy_create(dev, NULL, &phy_meson_gxl_usb2_ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "failed to create PHY\n");
+ return PTR_ERR(phy);
+ }
+
+ phy_set_drvdata(phy, priv);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id phy_meson_gxl_usb2_of_match[] = {
+ { .compatible = "amlogic,meson-gxl-usb2-phy", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, phy_meson_gxl_usb2_of_match);
+
+static struct platform_driver phy_meson_gxl_usb2_driver = {
+ .probe = phy_meson_gxl_usb2_probe,
+ .driver = {
+ .name = "phy-meson-gxl-usb2",
+ .of_match_table = phy_meson_gxl_usb2_of_match,
+ },
+};
+module_platform_driver(phy_meson_gxl_usb2_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
+MODULE_DESCRIPTION("Meson GXL and GXM USB2 PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.12.2
--
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^ permalink raw reply related
* [PATCH v3 1/2] Documentation: dt-bindings: Add documentation for the Meson GXL USB2 PHY
From: Martin Blumenstingl @ 2017-04-17 19:11 UTC (permalink / raw)
To: kishon-l0cyMroinI0,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
carlo-KA+7E9HrN00dnm+yROfE0A, khilman-rdvid1DuHRBWk0Htik3J/w
Cc: mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
hendrik-MJglGmTD+GWCT0AhDRffsw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
Martin Blumenstingl
In-Reply-To: <20170417191142.26099-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This adds the DT binding documentation for the USB2 PHY(s) found in the
Meson GXL and GXM SoCs.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
.../devicetree/bindings/phy/meson-gxl-usb2-phy.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt b/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
new file mode 100644
index 000000000000..a105494a0fc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
@@ -0,0 +1,17 @@
+* Amlogic Meson GXL and GXM USB2 PHY binding
+
+Required properties:
+- compatible: Should be "amlogic,meson-gxl-usb2-phy"
+- reg: The base address and length of the registers
+- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
+
+Optional properties:
+- phy-supply: see phy-bindings.txt in this directory
+
+
+Example:
+ usb2_phy0: phy@78000 {
+ compatible = "amlogic,meson-gxl-usb2-phy";
+ #phy-cells = <0>;
+ reg = <0x0 0x78000 0x0 0x20>;
+ };
--
2.12.2
--
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^ permalink raw reply related
* [PATCH v3 0/2] Meson GXL USB2 PHY driver
From: Martin Blumenstingl @ 2017-04-17 19:11 UTC (permalink / raw)
To: kishon-l0cyMroinI0,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
carlo-KA+7E9HrN00dnm+yROfE0A, khilman-rdvid1DuHRBWk0Htik3J/w
Cc: mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
hendrik-MJglGmTD+GWCT0AhDRffsw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
Martin Blumenstingl
In-Reply-To: <20170318130013.20771-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This series adds a driver for the USB2 PHYs found in Amlogic Meson GXL
(and GXM) SoCs.
Devicetree changes are intentionally missing in this series because of
various other problems that need to be resolved before we get USB host
support working.
As usual we unfortunately don't have any documentation available. The
register definitions were taken from the vendor's GPL kernel sources
(see [5] if you are really interested). Translation to human readable
names is done using the "best effort" algorithm.
The USB situation on GXL and GXM is a bit special:
the SoCs include both, a dwc3 and a dwc2 controller. The dwc3 controller
IP only supports host-mode, while the dwc2 controller IP only supports
device mode.
The dwc3 controller has all USB3 ports disabled. GXL has two USB2 ports
enabled on dwc3's internal hub, while GXM has three USB2 ports enabled.
This makes the initialization a bit special: to enable any of the dwc3
controller's USB2 ports *ALL* PHYs have to be initialized (probably due
to the hub's routing logic).
The first USB2 PHY (hardware-wise) also supports OTG mode. The vendor
kernel implements this through the USB3 PHY by re-routing the first
USB2 PHY from the dwc3 controller to the dwc2 controller (which is
disabled by default, but if the USB3 PHY detects that the port should
enter device mode it enables the dwc2 controller).
To get USB host mode working the following steps are needed:
- xhci-plat must be able to manage more than one PHY for a controller,
this is work-in-progress, see [0]
- there are some DMA handling issues in dwc3 and the rest of the USB
stack, this is solved by the "sysdev" patches from [1]
- adding all USB related bits to meson-gxl.dtsi - this is work in
progress but depends on the previous TODOs, see [2] and [3]
This supersedes my previous series "Meson GXL and GXM USB support" [4].
Changes since v2:
- removed PHY mode parsing from phy_meson_gxl_usb2_probe (based on
of_usb_get_dr_mode_by_phy()) because this will not work with the
xhci-plat changes anyways. The driver now simply defaults to host
mode until a consumer uses phy_set_mode().
- fixed a stray newline in drivers/phy/Kconfig b/drivers/phy/Kconfig
(thanks for spotting this Kishon)
- simplified phy_meson_gxl_usb2_reset() by returning early (thanks
Kishon for suggesting this improvement)
Changes since v1:
- rebased to the next branch of Kishon's linux-phy tree (currently at
fe0134d071 "phy: phy-exynos-pcie: make it explicitly non-modular")
- added a missing call to phy_meson_gxl_usb2_power_off in the error
case in phy_meson_gxl_usb2_power_on - thanks to Hendrik v. Raven for
spotting this!
- moved the reset logic into a separate function and expose it through
phy_ops.reset so it can be used by consumers of this PHY.
phy_meson_gxl_usb2_set_mode still resets the PHY directly because
this PHY will be configured by xhci-plat (from which we cannot call
phy_reset() - see the discussion based on v1 of this patch: [6])
- added Rob Herring's ACK to patch #1 (the dt-binding documentation)
[0] https://www.spinics.net/lists/linux-usb/msg151837.html
[1] http://www.mail-archive.com/linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org/msg87077.html
[2] https://github.com/xdarklight/linux/commit/e2b83785687fe859ae4bba8da8bb2fb2d7e32bfb
[3] https://github.com/xdarklight/linux/commit/203ab9ea5d1bea0bf066b6738010c8072b821d87
[4] http://lists.infradead.org/pipermail/linux-amlogic/2016-November/001721.html
[5] https://github.com/khadas/linux/blob/76fd19ac41bb774e396ce8009ff665f29c26c535/include/linux/amlogic/usb-gxl.h
[6] http://lists.infradead.org/pipermail/linux-amlogic/2017-March/002777.html
Martin Blumenstingl (2):
Documentation: dt-bindings: Add documentation for the Meson GXL USB2
PHY
phy: meson: add USB2 PHY support for Meson GXL and GXM
.../devicetree/bindings/phy/meson-gxl-usb2-phy.txt | 17 ++
drivers/phy/Kconfig | 12 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-meson-gxl-usb2.c | 261 +++++++++++++++++++++
4 files changed, 291 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
create mode 100644 drivers/phy/phy-meson-gxl-usb2.c
--
2.12.2
--
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^ permalink raw reply
* [PATCH V4 3/3] mtd: physmap_of: drop duplicated support for linux, part-probe property
From: Rafał Miłecki @ 2017-04-17 18:28 UTC (permalink / raw)
To: David Woodhouse, Brian Norris, Boris Brezillon, Marek Vasut,
Richard Weinberger, Cyrille Pitchen
Cc: Rob Herring, Mark Rutland, Frank Rowand, Linus Walleij,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rafał Miłecki
In-Reply-To: <20170417182853.24281-1-zajec5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Rafał Miłecki <rafal-g1n6cQUeyibVItvQsEIGlw@public.gmane.org>
Now support for linux,part-probe has been added to the MTD core there is
no need to duplicate support for it in physmap_of.
Signed-off-by: Rafał Miłecki <rafal-g1n6cQUeyibVItvQsEIGlw@public.gmane.org>
Acked-by: Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/mtd/maps/physmap_of.c | 46 +------------------------------------------
1 file changed, 1 insertion(+), 45 deletions(-)
diff --git a/drivers/mtd/maps/physmap_of.c b/drivers/mtd/maps/physmap_of.c
index 14e8909c9955..49dbb7235848 100644
--- a/drivers/mtd/maps/physmap_of.c
+++ b/drivers/mtd/maps/physmap_of.c
@@ -114,47 +114,9 @@ static struct mtd_info *obsolete_probe(struct platform_device *dev,
static const char * const part_probe_types_def[] = {
"cmdlinepart", "RedBoot", "ofpart", "ofoldpart", NULL };
-static const char * const *of_get_probes(struct device_node *dp)
-{
- const char *cp;
- int cplen;
- unsigned int l;
- unsigned int count;
- const char **res;
-
- cp = of_get_property(dp, "linux,part-probe", &cplen);
- if (cp == NULL)
- return part_probe_types_def;
-
- count = 0;
- for (l = 0; l != cplen; l++)
- if (cp[l] == 0)
- count++;
-
- res = kzalloc((count + 1)*sizeof(*res), GFP_KERNEL);
- if (!res)
- return NULL;
- count = 0;
- while (cplen > 0) {
- res[count] = cp;
- l = strlen(cp) + 1;
- cp += l;
- cplen -= l;
- count++;
- }
- return res;
-}
-
-static void of_free_probes(const char * const *probes)
-{
- if (probes != part_probe_types_def)
- kfree(probes);
-}
-
static const struct of_device_id of_flash_match[];
static int of_flash_probe(struct platform_device *dev)
{
- const char * const *part_probe_types;
const struct of_device_id *match;
struct device_node *dp = dev->dev.of_node;
struct resource res;
@@ -320,14 +282,8 @@ static int of_flash_probe(struct platform_device *dev)
info->cmtd->dev.parent = &dev->dev;
mtd_set_of_node(info->cmtd, dp);
- part_probe_types = of_get_probes(dp);
- if (!part_probe_types) {
- err = -ENOMEM;
- goto err_out;
- }
- mtd_device_parse_register(info->cmtd, part_probe_types, NULL,
+ mtd_device_parse_register(info->cmtd, part_probe_types_def, NULL,
NULL, 0);
- of_free_probes(part_probe_types);
kfree(mtd_list);
--
2.11.0
--
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^ permalink raw reply related
* [PATCH V4 2/3] mtd: add core code reading DT specified part probes
From: Rafał Miłecki @ 2017-04-17 18:28 UTC (permalink / raw)
To: David Woodhouse, Brian Norris, Boris Brezillon, Marek Vasut,
Richard Weinberger, Cyrille Pitchen
Cc: Rob Herring, Mark Rutland, Frank Rowand, Linus Walleij,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rafał Miłecki
In-Reply-To: <20170417182853.24281-1-zajec5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Rafał Miłecki <rafal-g1n6cQUeyibVItvQsEIGlw@public.gmane.org>
Handling (creating) partitions for flash devices requires using a proper
driver that will read partition table (out of somewhere). We can't
simply try all existing drivers one by one:
1) It would increase boot time
2) The order could be a problem
3) In some corner cases parsers could misinterpret some data as a table
Due to this MTD subsystem allows drivers to specify a list of applicable
part probes.
So far physmap_of was the only driver with support for linux,part-probe
DT property. Other ones had list or probes hardcoded which wasn't making
them really flexible. It prevented using common flash drivers on
platforms that required some specific partition table access.
This commit adds support for mentioned DT property directly to the MTD
core. It's a rewritten implementation of physmap_of's code and it makes
original code obsolete. Thanks to calling it on device parse
registration (as suggested by Boris) all drivers gain support for it for
free.
Signed-off-by: Rafał Miłecki <rafal-g1n6cQUeyibVItvQsEIGlw@public.gmane.org>
---
V4: Rename of functions
Add comment to the of_get_mtd_part_probes
Simplify mtd_device_parse_register changes
Thanks Boris for help on all above!
---
drivers/mtd/mtdcore.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index 66a9dedd1062..07b07de7e080 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -664,6 +664,33 @@ static void mtd_set_dev_defaults(struct mtd_info *mtd)
}
}
+static const char * const *of_get_mtd_part_probes(struct device_node *np)
+{
+ const char **res;
+ int count;
+
+ count = of_property_count_strings(np, "linux,part-probe");
+ if (count < 0)
+ return NULL;
+
+ /* This looks common: consider helper function if copying */
+ res = kzalloc((count + 1) * sizeof(*res), GFP_KERNEL);
+ if (!res)
+ return NULL;
+
+ count = of_property_read_string_array(np, "linux,part-probe", res,
+ count);
+ if (count < 0)
+ return NULL;
+
+ return res;
+}
+
+static void of_free_mtd_part_probes(const char * const *probes)
+{
+ kfree(probes);
+}
+
/**
* mtd_device_parse_register - parse partitions and register an MTD device.
*
@@ -698,11 +725,16 @@ int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
const struct mtd_partition *parts,
int nr_parts)
{
+ const char * const *part_probe_types;
struct mtd_partitions parsed;
int ret;
mtd_set_dev_defaults(mtd);
+ part_probe_types = of_get_mtd_part_probes(mtd_get_of_node(mtd));
+ if (part_probe_types)
+ types = part_probe_types;
+
memset(&parsed, 0, sizeof(parsed));
ret = parse_mtd_partitions(mtd, types, &parsed, parser_data);
@@ -720,6 +752,8 @@ int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
memset(&parsed, 0, sizeof(parsed));
}
+ of_free_mtd_part_probes(part_probe_types);
+
ret = mtd_add_device_partitions(mtd, &parsed);
if (ret)
goto out;
--
2.11.0
--
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^ permalink raw reply related
* [PATCH V4 1/3] dt-bindings: mtd: document linux,part-probe property
From: Rafał Miłecki @ 2017-04-17 18:28 UTC (permalink / raw)
To: David Woodhouse, Brian Norris, Boris Brezillon, Marek Vasut,
Richard Weinberger, Cyrille Pitchen
Cc: Rob Herring, Mark Rutland, Frank Rowand, Linus Walleij,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rafał Miłecki
In-Reply-To: <20170331114016.26858-1-zajec5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Rafał Miłecki <rafal-g1n6cQUeyibVItvQsEIGlw@public.gmane.org>
Support for this property has been introduced in 2010 with commit
9d5da3a9b849 ("mtd: extend physmap_of to let the device tree specify the
parition probe") but it was never documented. Fix this by adding a
proper description and example.
Signed-off-by: Rafał Miłecki <rafal-g1n6cQUeyibVItvQsEIGlw@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Acked-by: Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
Documentation/devicetree/bindings/mtd/common.txt | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/common.txt b/Documentation/devicetree/bindings/mtd/common.txt
index fc068b923d7a..1ada70e718b2 100644
--- a/Documentation/devicetree/bindings/mtd/common.txt
+++ b/Documentation/devicetree/bindings/mtd/common.txt
@@ -6,10 +6,17 @@ Optional properties:
controller based name) in order to ease flash device identification
and/or describe what they are used for.
+- linux,part-probe: if present, this property should contain a list of strings
+ with partition probes to be used for the flash device. A role of partition
+ probe (parser) is to read/construct partition table and register found
+ partitions. Getting partition table may be platform or device specific so
+ various devices may use various Linux drivers for this purpose.
+
Example:
flash@0 {
label = "System-firmware";
+ linux,part-probe = "cmdlinepart", "ofpart";
/* flash type specific properties */
};
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 3/3] iio: adc: meson-saradc: mark all meson_sar_adc_data static and const
From: Martin Blumenstingl @ 2017-04-17 18:28 UTC (permalink / raw)
To: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-iio-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, khilman-rdvid1DuHRBWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Martin Blumenstingl
In-Reply-To: <20170417182820.26670-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
These are only passed as of_device_id.data and never modified. Thus we
can mark them as static const, just like the of_device_id instances
where they are used.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
drivers/iio/adc/meson_saradc.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index cf13691009ee..8f742b71b165 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -843,31 +843,31 @@ static const struct iio_info meson_sar_adc_iio_info = {
.driver_module = THIS_MODULE,
};
-struct meson_sar_adc_data meson_sar_adc_meson8_data = {
+static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
.has_bl30_integration = false,
.resolution = 10,
.name = "meson-meson8b-saradc",
};
-struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
+static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
.has_bl30_integration = false,
.resolution = 10,
.name = "meson-meson8b-saradc",
};
-struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
+static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
.has_bl30_integration = true,
.resolution = 10,
.name = "meson-gxbb-saradc",
};
-struct meson_sar_adc_data meson_sar_adc_gxl_data = {
+static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
.has_bl30_integration = true,
.resolution = 12,
.name = "meson-gxl-saradc",
};
-struct meson_sar_adc_data meson_sar_adc_gxm_data = {
+static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
.has_bl30_integration = true,
.resolution = 12,
.name = "meson-gxm-saradc",
--
2.12.2
^ permalink raw reply related
* [PATCH 2/3] iio: adc: meson-saradc: add Meson8b SoC compatibility
From: Martin Blumenstingl @ 2017-04-17 18:28 UTC (permalink / raw)
To: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-iio-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, khilman-rdvid1DuHRBWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Martin Blumenstingl
In-Reply-To: <20170417182820.26670-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Meson GX SoCs however use some magic bits to prevent simultaneous (=
conflicting, because only consumer should use the FIFO buffer with the
ADC results) usage by the Linux kernel and the bootloader (the BL30
bootloader uses the SAR ADC to read the CPU temperature).
This patch changes guards all BL30 functionality so it is skipped on
SoCs which don't have it. Since the hardware itself doesn't know whether
BL30 is available the internal meson_sar_adc_data is extended so this
information can be provided per of_device_id.data inside the driver.
Additionally the clocks "adc_clk" and "adc_sel" are not provided by the
clock-controller itself. "adc_sel" is not available at all. "adc_clk"
is provided by the SAR ADC IP block itself on Meson8b (and earlier).
This is already supported by the meson_saradc driver.
Finally a new of_device_id for the Meson8b SoC is added so it can be
wired up in the corresponding DT.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
drivers/iio/adc/meson_saradc.c | 80 +++++++++++++++++++++++++++++-------------
1 file changed, 56 insertions(+), 24 deletions(-)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index dd4190b50df6..cf13691009ee 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -220,6 +220,7 @@ enum meson_sar_adc_chan7_mux_sel {
};
struct meson_sar_adc_data {
+ bool has_bl30_integration;
unsigned int resolution;
const char *name;
};
@@ -437,19 +438,24 @@ static int meson_sar_adc_lock(struct iio_dev *indio_dev)
mutex_lock(&indio_dev->mlock);
- /* prevent BL30 from using the SAR ADC while we are using it */
- regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
- MESON_SAR_ADC_DELAY_KERNEL_BUSY,
- MESON_SAR_ADC_DELAY_KERNEL_BUSY);
-
- /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
- do {
- udelay(1);
- regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
- } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
-
- if (timeout < 0)
- return -ETIMEDOUT;
+ if (priv->data->has_bl30_integration) {
+ /* prevent BL30 from using the SAR ADC while we are using it */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_KERNEL_BUSY,
+ MESON_SAR_ADC_DELAY_KERNEL_BUSY);
+
+ /*
+ * wait until BL30 releases it's lock (so we can use the SAR
+ * ADC)
+ */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
+ } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+ }
return 0;
}
@@ -458,9 +464,10 @@ static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
- /* allow BL30 to use the SAR ADC again */
- regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
- MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
+ if (priv->data->has_bl30_integration)
+ /* allow BL30 to use the SAR ADC again */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
mutex_unlock(&indio_dev->mlock);
}
@@ -614,14 +621,16 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
*/
meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
- /*
- * leave sampling delay and the input clocks as configured by BL30 to
- * make sure BL30 gets the values it expects when reading the
- * temperature sensor.
- */
- regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
- if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
- return 0;
+ if (priv->data->has_bl30_integration) {
+ /*
+ * leave sampling delay and the input clocks as configured by
+ * BL30 to make sure BL30 gets the values it expects when
+ * reading the temperature sensor.
+ */
+ regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
+ if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
+ return 0;
+ }
meson_sar_adc_stop_sample_engine(indio_dev);
@@ -834,23 +843,46 @@ static const struct iio_info meson_sar_adc_iio_info = {
.driver_module = THIS_MODULE,
};
+struct meson_sar_adc_data meson_sar_adc_meson8_data = {
+ .has_bl30_integration = false,
+ .resolution = 10,
+ .name = "meson-meson8b-saradc",
+};
+
+struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
+ .has_bl30_integration = false,
+ .resolution = 10,
+ .name = "meson-meson8b-saradc",
+};
+
struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
+ .has_bl30_integration = true,
.resolution = 10,
.name = "meson-gxbb-saradc",
};
struct meson_sar_adc_data meson_sar_adc_gxl_data = {
+ .has_bl30_integration = true,
.resolution = 12,
.name = "meson-gxl-saradc",
};
struct meson_sar_adc_data meson_sar_adc_gxm_data = {
+ .has_bl30_integration = true,
.resolution = 12,
.name = "meson-gxm-saradc",
};
static const struct of_device_id meson_sar_adc_of_match[] = {
{
+ .compatible = "amlogic,meson8-saradc",
+ .data = &meson_sar_adc_meson8_data,
+ },
+ {
+ .compatible = "amlogic,meson8b-saradc",
+ .data = &meson_sar_adc_meson8b_data,
+ },
+ {
.compatible = "amlogic,meson-gxbb-saradc",
.data = &meson_sar_adc_gxbb_data,
}, {
--
2.12.2
^ permalink raw reply related
* [PATCH 1/3] Documentation: dt-bindings: iio: adc: add Meson8 and Meson8b support
From: Martin Blumenstingl @ 2017-04-17 18:28 UTC (permalink / raw)
To: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-iio-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, khilman-rdvid1DuHRBWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Martin Blumenstingl
In-Reply-To: <20170417182820.26670-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
The Amlogic Meson SAR ADC driver can be used on Meson8 and Meson8b
(probably on earlier SoC generations as well, but I don't have any
hardware available for testing that).
Add a separate compatible for Meson8 and Meson8b because it does not
need any of the BL30 magic (unlike the GX SoCs).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
index f9e3ff2c656e..08cee82e54c3 100644
--- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -2,6 +2,8 @@
Required properties:
- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson8-saradc" for Meson8
+ - "amlogic,meson8b-saradc" for Meson8b
- "amlogic,meson-gxbb-saradc" for GXBB
- "amlogic,meson-gxl-saradc" for GXL
- "amlogic,meson-gxm-saradc" for GXM
--
2.12.2
--
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^ permalink raw reply related
* [PATCH 0/3] Meson8 / Meson8b support for the meson_saradc driver
From: Martin Blumenstingl @ 2017-04-17 18:28 UTC (permalink / raw)
To: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-iio-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, khilman-rdvid1DuHRBWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Martin Blumenstingl
The SAR ADC register layout seems to be mostly the same on older SoCs.
Thus basically all functionality is already supported by the existing
driver.
There are two small differences though:
- the adc_clk and adc_div clock are not provided by the clock-controller
on Meson8b. instead the SAR ADC provides an internal "adc_clk" (this
behavior is already supported by the driver and requires no changes)
- the newer SoCs are using some register bits only the kernel or the
BL30 (bootloader) are using the SAR ADC. This is the main change of
this series: guarding all BL30 specific code with a corresponding
"if"-block.
This also adds a new DT binding for the SAR ADC in Meson8 and Meson8b
because the driver has to specify (for this older version) that there's
no BL30 integration available (and these register bits should not be
touched).
Changes since v1 at [0]:
- switched to bool data-type for has_bl30_integration
- also added a "compatible" for Meson8 SoCs (the ADC driver from
Amlogic's GPL kernel sources handles Meson8 and Meson8b identical)
- added patch #3 to constify some structs (there were supposed to be
const from the very beginning)
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-March/003081.html
Martin Blumenstingl (3):
Documentation: dt-bindings: iio: adc: add Meson8 and Meson8b support
iio: adc: meson-saradc: add Meson8b SoC compatibility
iio: adc: meson-saradc: mark all meson_sar_adc_data static and const
.../bindings/iio/adc/amlogic,meson-saradc.txt | 2 +
drivers/iio/adc/meson_saradc.c | 86 +++++++++++++++-------
2 files changed, 61 insertions(+), 27 deletions(-)
--
2.12.2
--
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^ permalink raw reply
* [PATCH V3 2/2] ARM64: dts: hi6220-hikey: Add clock binding for the pmic mfd
From: Daniel Lezcano @ 2017-04-17 17:19 UTC (permalink / raw)
To: sboyd, mturquette
Cc: lee.jones, xuwei5, linux-kernel, linux-clk, devicetree,
linux-arm-kernel
In-Reply-To: <1492449567-31399-1-git-send-email-daniel.lezcano@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt | 6 ++++++
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 1 +
2 files changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
index 0548569..9630ac0 100644
--- a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
+++ b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
@@ -16,6 +16,11 @@ Required properties:
- reg: Base address of PMIC on Hi6220 SoC.
- interrupt-controller: Hi655x has internal IRQs (has own IRQ domain).
- pmic-gpios: The GPIO used by PMIC IRQ.
+- #clock-cells: From common clock binding; shall be set to 0
+
+Optional properties:
+- clock-output-names: From common clock binding to override the
+ default output clock name
Example:
pmic: pmic@f8000000 {
@@ -24,4 +29,5 @@ Example:
interrupt-controller;
#interrupt-cells = <2>;
pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ #clock-cells = <0>;
}
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index dba3c13..e0496f7 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -325,6 +325,7 @@
pmic: pmic@f8000000 {
compatible = "hisilicon,hi655x-pmic";
reg = <0x0 0xf8000000 0x0 0x1000>;
+ #clock-cells = <0>;
interrupt-controller;
#interrupt-cells = <2>;
pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
--
1.9.1
^ permalink raw reply related
* Re: [PATCH V2] PM / OPP: Use - instead of @ for DT entries
From: Rafael J. Wysocki @ 2017-04-17 16:40 UTC (permalink / raw)
To: Masahiro Yamada, Viresh Kumar, Rob Herring
Cc: Chanwoo Choi, MyungJoo Ham, Kyungmin Park, Kukjin Kim,
Krzysztof Kozlowski, Javier Martinez Canillas, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Benoît Cousson, Tony Lindgren,
Mark Rutland, Daniel Mack, Haojian Zhuang, Robert Jarzmik,
Maxime Ripard, Chen-Yu Tsai, linaro-kernel, linux-pm
In-Reply-To: <22966574.2zMrIUgKz4@aspire.rjw.lan>
On Monday, April 17, 2017 06:35:25 PM Rafael J. Wysocki wrote:
> On Monday, April 17, 2017 11:07:51 AM Masahiro Yamada wrote:
> > 2017-04-15 7:47 GMT+09:00 Rafael J. Wysocki <rjw@rjwysocki.net>:
> > > On Monday, April 10, 2017 02:51:35 PM Viresh Kumar wrote:
> > >> Compiling the DT file with W=1, DTC warns like follows:
> > >>
> > >> Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
> > >> unit name, but no reg property
> > >>
> > >> Fix this by replacing '@' with '-' as the OPP nodes will never have a
> > >> "reg" property.
> > >>
> > >> Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
> > >> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> > >> Suggested-by: Mark Rutland <mark.rutland@arm.com>
> > >> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
> > >> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> (sunxi)
> > >> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
> > >> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> > >
> > > OK, so any ACKs from the DT side? Rob?
> > >
> > > Thanks,
> > > Rafael
> >
> >
> >
> > I see Rob's Acked-by.
> >
> > https://lkml.org/lkml/2017/4/13/648
>
> Indeed. Thanks!
But it doesn't apply on top of -rc7 for me, so I guess there is new 4.12-candidate
material in the DTS tree that conflicts with this, in which case it is better to route
it through the DTS tree IMO.
Thanks,
Rafael
^ permalink raw reply
* Re: [PATCH V2] PM / OPP: Use - instead of @ for DT entries
From: Rafael J. Wysocki @ 2017-04-17 16:35 UTC (permalink / raw)
To: Masahiro Yamada
Cc: Viresh Kumar, Rob Herring, Chanwoo Choi, MyungJoo Ham,
Kyungmin Park, Kukjin Kim, Krzysztof Kozlowski,
Javier Martinez Canillas, Viresh Kumar, Nishanth Menon,
Stephen Boyd, Benoît Cousson, Tony Lindgren, Mark Rutland,
Daniel Mack, Haojian Zhuang, Robert Jarzmik, Maxime Ripard,
Chen-Yu Tsai, linaro-kernel
In-Reply-To: <CAK7LNAQ7Uf1Jkj64-Ykdk5TSeWvkq7=BaqUMJo6KqrN7BhYvsQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Monday, April 17, 2017 11:07:51 AM Masahiro Yamada wrote:
> 2017-04-15 7:47 GMT+09:00 Rafael J. Wysocki <rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org>:
> > On Monday, April 10, 2017 02:51:35 PM Viresh Kumar wrote:
> >> Compiling the DT file with W=1, DTC warns like follows:
> >>
> >> Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
> >> unit name, but no reg property
> >>
> >> Fix this by replacing '@' with '-' as the OPP nodes will never have a
> >> "reg" property.
> >>
> >> Reported-by: Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> >> Reported-by: Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
> >> Suggested-by: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> >> Signed-off-by: Viresh Kumar <viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> >> Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> (sunxi)
> >> Reviewed-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> >> Reviewed-by: Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> >
> > OK, so any ACKs from the DT side? Rob?
> >
> > Thanks,
> > Rafael
>
>
>
> I see Rob's Acked-by.
>
> https://lkml.org/lkml/2017/4/13/648
Indeed. Thanks!
Regards,
Rafael
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