* Re: [PATCH] ARM: dts: r7s72100: add usb clocks to device tree
From: Simon Horman @ 2017-04-28 8:04 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Chris Brandt, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Linux-Renesas
In-Reply-To: <CAMuHMdXEtefpaUJbbJ7LYjYR2oHaE-epy=eZnAyE-+=GWsy9xg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Fri, Apr 28, 2017 at 09:34:54AM +0200, Geert Uytterhoeven wrote:
> On Thu, Apr 27, 2017 at 9:10 PM, Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org> wrote:
> > This adds the USB0 and USB1 clocks to the device tree.
> >
> > Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
>
> Simon: see Section 29.3.2 (BUSWAIT) for the reference to the P1 clock.
Thanks, I see that now.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2 07/30] arm: dts: mt7623: add pinctrl nodes to the mt7623 dtsi file
From: Linus Walleij @ 2017-04-28 8:03 UTC (permalink / raw)
To: sean.wang-NuS5LvNUpcJWk0Htik3J/w
Cc: Rob Herring, Matthias Brugger, John Crispin, Mark Rutland,
Russell King, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
moderated list:ARM/Mediatek SoC support,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1493198774-4478-8-git-send-email-sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Wed, Apr 26, 2017 at 11:25 AM, <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> From: John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
>
> Add pin controller node to the mt7623.dtsi file
>
> Signed-off-by: John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
> Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
(...)
> + pio: pinctrl@10005000 {
> + compatible = "mediatek,mt7623-pinctrl",
> + "mediatek,mt2701-pinctrl";
This looks right. And that is why we should not delete that compatible
string.
Reviewed-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2 02/30] pinctrl: mediatek: reuse pinctrl driver for mt7623
From: Linus Walleij @ 2017-04-28 8:01 UTC (permalink / raw)
To: sean.wang-NuS5LvNUpcJWk0Htik3J/w
Cc: Rob Herring, Matthias Brugger, John Crispin, Mark Rutland,
Russell King, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
moderated list:ARM/Mediatek SoC support,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1493198774-4478-3-git-send-email-sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Wed, Apr 26, 2017 at 11:25 AM, <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>
> mt7623 pinctrl driver can be compatible with mt2701 one,
> so the patch reuses the driver and deletes those redundant
> ones.
>
> Cc: John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
> Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Partly correct.
> "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
> - "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
NO don't do this.
"compatible" means exactly this: this hardware is compatible with
this driver. That is why we have it!
So instead of mt7623 pretending to be mt2701, let the mt2701 driver
list that it is compatible with mt7623, simple.
So patch pinctrl-mt2701.c mt2701_pctrl_match[] instead.
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2 01/30] pinctrl: mediatek: Add missing pinctrl bindings for mt7623
From: Linus Walleij @ 2017-04-28 7:55 UTC (permalink / raw)
To: sean.wang
Cc: Rob Herring, Matthias Brugger, John Crispin, Mark Rutland,
Russell King, devicetree@vger.kernel.org,
moderated list:ARM/Mediatek SoC support,
linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <1493198774-4478-2-git-send-email-sean.wang@mediatek.com>
On Wed, Apr 26, 2017 at 11:25 AM, <sean.wang@mediatek.com> wrote:
> From: Sean Wang <sean.wang@mediatek.com>
>
> Add missing pinctrl binding these which would be used in
> devicetree related files.
>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Patch applied. This way we avoid subsystem noise in the next
merge window.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2 12/18] gpio: madera: Support Cirrus Logic Madera class codecs
From: Linus Walleij @ 2017-04-28 7:46 UTC (permalink / raw)
To: Richard Fitzgerald
Cc: Alexandre Courbot, alsa-devel@alsa-project.org, Jason Cooper,
devicetree@vger.kernel.org,
open list:WOLFSON MICROELECTRONICS DRIVERS,
linux-kernel@vger.kernel.org, Rob Herring,
linux-gpio@vger.kernel.org, Mark Brown, Thomas Gleixner,
Lee Jones
In-Reply-To: <1493131461.4826.66.camel@rf-debian.wolfsonmicro.main>
On Tue, Apr 25, 2017 at 4:44 PM, Richard Fitzgerald
<rf@opensource.wolfsonmicro.com> wrote:
> On Tue, 2017-04-25 at 16:13 +0200, Linus Walleij wrote:
>> On Mon, Apr 24, 2017 at 6:08 PM, Richard Fitzgerald
>> <rf@opensource.wolfsonmicro.com> wrote:
>>
>> > This adds support for the GPIOs on Cirrus Logic Madera class codecs.
>> > Any pins not used for special functions (see the pinctrl driver) can be
>> > used as general single-bit input or output lines. The number of available
>> > GPIOs varies between codecs.
>> >
>> > Signed-off-by: Nariman Poushin <nariman@opensource.wolfsonmicro.com>
>> > Signed-off-by: Richard Fitzgerald <rf@opensource.wolfsonmicro.com>
>> > Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
>> > ---
>> > Changes from V1:
>> > - dt bindings moved to a separate patch
>> > - dependent on pinctrl driver instead of parent MFD
>> > - added get_direction function
>> > - added .request / .free / .set_config to work with pinctrl driver
>> > - register range with pinctrl driver
>>
>> Nice, but...
>>
>> > + ret = gpiochip_add_pin_range(&madera_gpio->gpio_chip, "madera-pinctrl",
>> > + 0, 0, madera_gpio->gpio_chip.ngpio);
>> > + if (ret) {
>> > + dev_warn(&pdev->dev, "Failed to add pin range (%d)\n", ret);
>> > + return ret;
>> > + }
>>
>> This is all fine, but we have generic code for adding ranges from
>> the device tree, see
>> Documentation/devicetree/bindings/gpio/gpio.txt
>>
>
> The range of gpio pins is a fixed property of the chip, and so is the
> combination of gpio+pinctrl drivers.
Well so is the IRQ number, but we still put that in the device tree.
> I think the general principle of the DT maintainers is that DT should be
> used for things that the drivers don't already know and can't figure
> out.
It's a grayzone. People use ranges in the device tree for example when
there are several instances of the same GPIO block with different
ranges into a single pin controller and then it makes sense.
But in this case you have your separate chip with one instance so
it doesn't make sense, keep it like this.
Also it is necessary to proble from boardfiles as you explained in the
pinctrl patch.
Good job, it's a nice driver. Also the pinctrl driver is very nice.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2 12/18] gpio: madera: Support Cirrus Logic Madera class codecs
From: Linus Walleij @ 2017-04-28 7:44 UTC (permalink / raw)
To: Richard Fitzgerald
Cc: Alexandre Courbot, alsa-devel@alsa-project.org, Jason Cooper,
devicetree@vger.kernel.org,
open list:WOLFSON MICROELECTRONICS DRIVERS,
linux-kernel@vger.kernel.org, Rob Herring,
linux-gpio@vger.kernel.org, Mark Brown, Thomas Gleixner,
Lee Jones
In-Reply-To: <1493050124-5970-13-git-send-email-rf@opensource.wolfsonmicro.com>
On Mon, Apr 24, 2017 at 6:08 PM, Richard Fitzgerald
<rf@opensource.wolfsonmicro.com> wrote:
> This adds support for the GPIOs on Cirrus Logic Madera class codecs.
> Any pins not used for special functions (see the pinctrl driver) can be
> used as general single-bit input or output lines. The number of available
> GPIOs varies between codecs.
>
> Signed-off-by: Nariman Poushin <nariman@opensource.wolfsonmicro.com>
> Signed-off-by: Richard Fitzgerald <rf@opensource.wolfsonmicro.com>
> Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
> ---
> Changes from V1:
> - dt bindings moved to a separate patch
> - dependent on pinctrl driver instead of parent MFD
> - added get_direction function
> - added .request / .free / .set_config to work with pinctrl driver
> - register range with pinctrl driver
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2 10/18] pinctrl: madera: Add driver for Cirrus Logic Madera codecs
From: Linus Walleij @ 2017-04-28 7:39 UTC (permalink / raw)
To: Richard Fitzgerald
Cc: Alexandre Courbot, alsa-devel@alsa-project.org, Jason Cooper,
devicetree@vger.kernel.org,
open list:WOLFSON MICROELECTRONICS DRIVERS,
linux-kernel@vger.kernel.org, Rob Herring,
linux-gpio@vger.kernel.org, Mark Brown, Thomas Gleixner,
Lee Jones
In-Reply-To: <1493050124-5970-11-git-send-email-rf@opensource.wolfsonmicro.com>
On Mon, Apr 24, 2017 at 6:08 PM, Richard Fitzgerald
<rf@opensource.wolfsonmicro.com> wrote:
> These codecs have a variable number of I/O lines each of which
> is individually selectable to a wide range of possible functions.
>
> The functionality is slightly different from the traditional muxed
> GPIO since most of the functions can be mapped to any pin (and even
> the same function to multiple pins). Most pins have a dedicated
> "alternate" function that is only available on that pin. The
> alternate functions are usually a group of signals, though it is
> not always necessary to enable the full group, depending on the
> alternate function and how it is to be used. The mapping between
> alternate functions and GPIO pins varies between codecs depending
> on the number of alternate functions and available pins.
>
> Note on the Kconfig options:
> The formula "default y if..." is used for PINCTRL_MADERA so that its
> select options will be processed, allowing us to group selects for
> pinctrl into the pinctrl Kconfig where they logically belong instead
> of accumulating under the parent MFD Kconfig.
>
> Signed-off-by: Richard Fitzgerald <rf@opensource.wolfsonmicro.com>
> ---
> Changes since V1:
> - dt binding moved to separate patch
> - moved all source into a subdirectory drivers/pinctrl/cirrus
> - split chip-specific tables into separate files
> - codec-specific build options are now selected from MFD
> - print useful information from madera_pin_dbg_show()
> - added gpio_set_direciton / gpio_request_enable / gpio_disable_free functions
> - added strict mode so GPIO and other functions are exclusive
> - replace #ifdefs with if (IS_ENABLED(...)) in probe
> - fixed bug reading registers in madera_pin_conf_get()
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
I guess you will apply this through MFD, so waiting for Lee to
pick it up. Alternatively I can apply it after the MFD core parts
are upstream.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] ARM: dts: r7s72100: add usb clocks to device tree
From: Geert Uytterhoeven @ 2017-04-28 7:34 UTC (permalink / raw)
To: Chris Brandt
Cc: Simon Horman, Rob Herring, Mark Rutland,
devicetree@vger.kernel.org, Linux-Renesas
In-Reply-To: <20170427191045.21199-1-chris.brandt@renesas.com>
On Thu, Apr 27, 2017 at 9:10 PM, Chris Brandt <chris.brandt@renesas.com> wrote:
> This adds the USB0 and USB1 clocks to the device tree.
>
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Simon: see Section 29.3.2 (BUSWAIT) for the reference to the P1 clock.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH/RFC 0/5] arm64: dts: renesas: Break out common board support
From: Simon Horman @ 2017-04-28 7:32 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Geert Uytterhoeven, Magnus Damm, Kuninori Morimoto,
Yoshihiro Shimoda, Rob Herring, Mark Rutland, Linux-Renesas,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Vladimir Barinov
In-Reply-To: <CAMuHMdVypXM59rk50Guc90ktD2PKHsVHgXyN34Cz3EC1hMTs8g@mail.gmail.com>
On Fri, Apr 28, 2017 at 09:11:36AM +0200, Geert Uytterhoeven wrote:
> Hi SImon,
>
> On Fri, Apr 28, 2017 at 9:04 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Thu, Apr 27, 2017 at 03:32:49PM +0200, Geert Uytterhoeven wrote:
> >> On Wed, Apr 26, 2017 at 10:11 AM, Geert Uytterhoeven
> >> <geert@linux-m68k.org> wrote:
> >> > CC Vladimir (which I forgot to CC initially, sorry for that)
> >> >
> >> > On Wed, Apr 26, 2017 at 10:06 AM, Simon Horman <horms@verge.net.au> wrote:
> >> >> On Fri, Apr 21, 2017 at 02:55:16PM +0200, Geert Uytterhoeven wrote:
> >> >>> The Renesas Salvator-X and ULCB development board can be equipped with
> >> >>> either an R-Car H3 or M3-W SiP, which are pin-compatible. All boards
> >> >>> use separate DTBs, but currently there's no sharing of board-specific
> >> >>> devices in DTS.
> >> >>>
> >> >>> This series reduces duplication by extracting common board support into
> >> >>> their own .dtsi files. As the level of support varies across boards and
> >> >>> SoCs, this requires the addition of a few external clocks and
> >> >>> placeholder devices on R-Car M3-W, so the common board support DTS can
> >> >>> refer to them.
> >> >>>
> >> >>> - Patches 1 and 2 add the external audio and PCIe bus clocks on R-Car
> >> >>> M3-W, which are present in r8a7795.dtsi, and used in
> >> >>> r8a7795-salvator-x.dts,
> >> >>> - RFC patch 3 adds placeholders for devices that are not yet supported
> >> >>> and/or tested on R-Car M3-W, but used on R-Car H3,
> >> >>> - RFC patch 4 extracts common Salvator-X board support,
> >> >>> - RFC patch 5 extracts common ULCB board support.
> >> >>>
> >> >>> For R-Car H3 based boards, there are no functional changes.
> >> >>> For R-Car M3-W based boards, some new devices are now described in DT.
> >> >>>
> >> >>> Dependencies:
> >> >>> - renesas-devel-20170420-v4.11-rc7,
> >> >>> - Patches 1 and 2 can be applied as-is,
> >> >>> - Patches 4 and 5 depend on "[PATCH 0/8] arm64: dts: renesas: Break
> >> >>> out R-Car H3 and M3-W SiP"
> >> >>> (http://www.spinics.net/lists/devicetree/msg173820.html).
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
> >> >>> DTB changes have been inspected using scripts/dtc/dtx_diff.
> >> >>> This has been tested on Salvator-X (both H3 and M3-W).
> >> >>> This has not been tested on H3ULCB and M3ULCB due to lack of hardware.
> >> >>>
> >> >>> Thanks for your comments!
> >> >>
> >> >> Thanks for tackling this important problem. I have looked over the changes
> >> >> and they seem nice to me. I would, however, be more comfortable applying
> >> >> them if they were rested on the ULCB boards.
> >> >
> >> > tested?
> >> >
> >> > I've pushed a branch for testing to topic/rcar3-dtsi-sharing in
> >> > git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git.
> >>
> >> I managed to test it on the new H3ULCB and M3ULCB baords in Magnus' farm.
> >> No issues detected.
> >
> > Great! Any objections to me queuing this up?
>
> The dependency above (no feedback about the SiP types yet).
>
> I can respin without that dependency, if that is preferred...
It seems to me that it would be nice to get these in sooner than later - in
particular earlier rather than later in the (v4.13) development cycle. But
I defer to your judgement on what is best.
^ permalink raw reply
* Re: [PATCH v5 00/10] Renesas RZ/A1 pin and gpio controller
From: Simon Horman @ 2017-04-28 7:31 UTC (permalink / raw)
To: jmondi
Cc: Geert Uytterhoeven, Jacopo Mondi, Linus Walleij,
Geert Uytterhoeven, Laurent Pinchart, Chris Brandt, Rob Herring,
Mark Rutland, Russell King, Linux-Renesas,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20170428072457.GA4911@w540>
On Fri, Apr 28, 2017 at 09:24:57AM +0200, jmondi wrote:
> Hi Geert, Simon,
>
> On Thu, Apr 27, 2017 at 10:42:02AM +0200, Geert Uytterhoeven wrote:
> > Hi Jacopo,
> >
> > On Thu, Apr 27, 2017 at 10:19 AM, Jacopo Mondi
> > <jacopo+renesas@jmondi.org> wrote:
> > > this is 5th round of gpio/pincontroller for RZ/A1 devices.
> > >
> > > I have updated the pin controller driver to use the newly introduced
> > > "pinctrl_enable()" function.
> > > This is required since v4.11-rc7 as otherwise, as reported by Chris Brandt,
> > > the pin controller does not start.
> > >
> > > I have incorporated your comments on the device tree bindings documentation,
> > > and added to pinctrl-generic.h header file two macros to unpack generic
> > > properties and their arguments.
> > >
> > > Tested with SCIF, RIIC, ETHER and gpio-leds on Genmai board.
> >
> > Thanks for the update!
> >
> > > Jacopo Mondi (10):
> > > pinctrl: generic: Add bi-directional and output-enable
> >
> > Already applied by LinusW.
> >
> > > pinctrl: generic: Add macros to unpack properties
> >
> > LinusW: do you want me to queue this together with the driver for v4.13,
> > or will you take this single patch for v4.12?
> >
> > > pinctrl: Renesas RZ/A1 pin and gpio controller
> > > dt-bindings: pinctrl: Add RZ/A1 bindings doc
> >
> > Will queue in sh-pfc-for-v4.13.
> >
> > > arm: dts: dt-bindings: Add Renesas RZ/A1 pinctrl header
> > > arm: dts: r7s72100: Add pin controller node
> > > arm: dts: genmai: Add SCIF2 pin group
> > > arm: dts: genmai: Add RIIC2 pin group
> > > arm: dts: genmai: Add user led device nodes
> > > arm: dts: genmai: Add ethernet pin group
> >
> > These are for Simon.
> >
> > Does applying the DTS changes before the driver introduce regressions?
> > If no, Simon can queue them for v4.13.
> > If yes, they'll have to wait for v4.14.
> >
>
> I tried reverting patch [03/10] which introduces the driver, and I
> lose serial output on Genmai. So I guess the dts patches have to be
> taken after the driver has been merged.
>
> One question: why can't they be taken at the same time? (eg. for
> v4.13?)
The problem is that the changes go through different trees. It may,
however, be possible to arrange for both sets of changes to go into v4.13
by negotiating with the ARM-SoC maintainers.
^ permalink raw reply
* Re: [PATCH v5 00/10] Renesas RZ/A1 pin and gpio controller
From: Geert Uytterhoeven @ 2017-04-28 7:30 UTC (permalink / raw)
To: jmondi
Cc: Jacopo Mondi, Linus Walleij, Geert Uytterhoeven, Laurent Pinchart,
Chris Brandt, Rob Herring, Mark Rutland, Russell King,
Linux-Renesas, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <20170428072457.GA4911@w540>
Hi Jacopo,
On Fri, Apr 28, 2017 at 9:24 AM, jmondi <jacopo@jmondi.org> wrote:
> On Thu, Apr 27, 2017 at 10:42:02AM +0200, Geert Uytterhoeven wrote:
>> On Thu, Apr 27, 2017 at 10:19 AM, Jacopo Mondi
>> <jacopo+renesas@jmondi.org> wrote:
>> > this is 5th round of gpio/pincontroller for RZ/A1 devices.
>> >
>> > I have updated the pin controller driver to use the newly introduced
>> > "pinctrl_enable()" function.
>> > This is required since v4.11-rc7 as otherwise, as reported by Chris Brandt,
>> > the pin controller does not start.
>> >
>> > I have incorporated your comments on the device tree bindings documentation,
>> > and added to pinctrl-generic.h header file two macros to unpack generic
>> > properties and their arguments.
>> >
>> > Tested with SCIF, RIIC, ETHER and gpio-leds on Genmai board.
>>
>> Thanks for the update!
>>
>> > Jacopo Mondi (10):
>> > pinctrl: generic: Add bi-directional and output-enable
>>
>> Already applied by LinusW.
>>
>> > pinctrl: generic: Add macros to unpack properties
>>
>> LinusW: do you want me to queue this together with the driver for v4.13,
>> or will you take this single patch for v4.12?
>>
>> > pinctrl: Renesas RZ/A1 pin and gpio controller
>> > dt-bindings: pinctrl: Add RZ/A1 bindings doc
>>
>> Will queue in sh-pfc-for-v4.13.
>>
>> > arm: dts: dt-bindings: Add Renesas RZ/A1 pinctrl header
>> > arm: dts: r7s72100: Add pin controller node
>> > arm: dts: genmai: Add SCIF2 pin group
>> > arm: dts: genmai: Add RIIC2 pin group
>> > arm: dts: genmai: Add user led device nodes
>> > arm: dts: genmai: Add ethernet pin group
>>
>> These are for Simon.
>>
>> Does applying the DTS changes before the driver introduce regressions?
>> If no, Simon can queue them for v4.13.
>> If yes, they'll have to wait for v4.14.
>>
>
> I tried reverting patch [03/10] which introduces the driver, and I
> lose serial output on Genmai. So I guess the dts patches have to be
> taken after the driver has been merged.
>
> One question: why can't they be taken at the same time? (eg. for
> v4.13?)
Because the driver goes in through me and LinusW, while the DTS goes in
through Simon and arm-soc.
If Simon applies the DTS patches, it will regress genmai in renesas-devel
until the release of v4.13-rc1.
An immutable branch would solve that, but for adding PFC we usuable just
postpone the DT part by one cycle.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v5 00/10] Renesas RZ/A1 pin and gpio controller
From: jmondi @ 2017-04-28 7:24 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Jacopo Mondi, Linus Walleij, Geert Uytterhoeven, Laurent Pinchart,
Chris Brandt, Rob Herring, Mark Rutland, Russell King,
Linux-Renesas, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <CAMuHMdWw1JpFLT0QY4yQK6VH0oSeQOHUWMuKFSj6b6vrhHPCdA@mail.gmail.com>
Hi Geert, Simon,
On Thu, Apr 27, 2017 at 10:42:02AM +0200, Geert Uytterhoeven wrote:
> Hi Jacopo,
>
> On Thu, Apr 27, 2017 at 10:19 AM, Jacopo Mondi
> <jacopo+renesas@jmondi.org> wrote:
> > this is 5th round of gpio/pincontroller for RZ/A1 devices.
> >
> > I have updated the pin controller driver to use the newly introduced
> > "pinctrl_enable()" function.
> > This is required since v4.11-rc7 as otherwise, as reported by Chris Brandt,
> > the pin controller does not start.
> >
> > I have incorporated your comments on the device tree bindings documentation,
> > and added to pinctrl-generic.h header file two macros to unpack generic
> > properties and their arguments.
> >
> > Tested with SCIF, RIIC, ETHER and gpio-leds on Genmai board.
>
> Thanks for the update!
>
> > Jacopo Mondi (10):
> > pinctrl: generic: Add bi-directional and output-enable
>
> Already applied by LinusW.
>
> > pinctrl: generic: Add macros to unpack properties
>
> LinusW: do you want me to queue this together with the driver for v4.13,
> or will you take this single patch for v4.12?
>
> > pinctrl: Renesas RZ/A1 pin and gpio controller
> > dt-bindings: pinctrl: Add RZ/A1 bindings doc
>
> Will queue in sh-pfc-for-v4.13.
>
> > arm: dts: dt-bindings: Add Renesas RZ/A1 pinctrl header
> > arm: dts: r7s72100: Add pin controller node
> > arm: dts: genmai: Add SCIF2 pin group
> > arm: dts: genmai: Add RIIC2 pin group
> > arm: dts: genmai: Add user led device nodes
> > arm: dts: genmai: Add ethernet pin group
>
> These are for Simon.
>
> Does applying the DTS changes before the driver introduce regressions?
> If no, Simon can queue them for v4.13.
> If yes, they'll have to wait for v4.14.
>
I tried reverting patch [03/10] which introduces the driver, and I
lose serial output on Genmai. So I guess the dts patches have to be
taken after the driver has been merged.
One question: why can't they be taken at the same time? (eg. for
v4.13?)
Thanks
j
> Thanks!
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply
* Re: [PATCH] ARM: dts: r7s72100: add usb clocks to device tree
From: Simon Horman @ 2017-04-28 7:24 UTC (permalink / raw)
To: Chris Brandt
Cc: Geert Uytterhoeven, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170427191045.21199-1-chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
On Thu, Apr 27, 2017 at 12:10:45PM -0700, Chris Brandt wrote:
> This adds the USB0 and USB1 clocks to the device tree.
>
> Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> ---
> arch/arm/boot/dts/r7s72100.dtsi | 6 +++---
> include/dt-bindings/clock/r7s72100-clock.h | 2 ++
> 2 files changed, 5 insertions(+), 3 deletions(-)
Hi Chris,
could you break the .h patch out into a separate patch so that I can apply
it to my dt-bindings branch? The reason for that branch is to allow better
management of dependencies; something I got burnt by a few releases back.
>
> diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
> index fb54cb5d3fad..4ed12a4d9d51 100644
> --- a/arch/arm/boot/dts/r7s72100.dtsi
> +++ b/arch/arm/boot/dts/r7s72100.dtsi
> @@ -144,9 +144,9 @@
> #clock-cells = <1>;
> compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
> reg = <0xfcfe0430 4>;
> - clocks = <&b_clk>;
> - clock-indices = <R7S72100_CLK_ETHER>;
> - clock-output-names = "ether";
> + clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
> + clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
> + clock-output-names = "ether", "usb0", "usb1";
The above looks fine to me although I was unable to find the USB parent
clock in the documentation I have available.
> };
>
> mstp8_clks: mstp8_clks@fcfe0434 {
> diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h
> index bc256d31099a..dcd2072151fc 100644
> --- a/include/dt-bindings/clock/r7s72100-clock.h
> +++ b/include/dt-bindings/clock/r7s72100-clock.h
> @@ -34,6 +34,8 @@
>
> /* MSTP7 */
> #define R7S72100_CLK_ETHER 4
> +#define R7S72100_CLK_USB0 1
> +#define R7S72100_CLK_USB1 0
>
> /* MSTP8 */
> #define R7S72100_CLK_MMCIF 4
The above also looks fine to me.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* RE: [PATCH] arm64: dts: freescale: ls2081ardb: Add DTS support for NXP LS2081ARDB
From: Priyanka Jain @ 2017-04-28 7:20 UTC (permalink / raw)
To: Yang Li
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring,
Mark Rutland, Shawn Guo,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Leo Li
In-Reply-To: <CADRPPNRM9Orc=RtRJstA-qpCcdCvrgab0n3d=CC7i6O7ua8nNg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 7895 bytes --]
> -----Original Message-----
> From: Yang Li [mailto:pku.leo@gmail.com]
> Sent: Monday, April 24, 2017 10:51 PM
> To: Priyanka Jain <priyanka.jain@nxp.com>
> Cc: devicetree@vger.kernel.org; Rob Herring <robh@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Shawn Guo <shawnguo@kernel.org>; linux-arm-
> kernel@lists.infradead.org; Leo Li <leoyang.li@nxp.com>
> Subject: Re: [PATCH] arm64: dts: freescale: ls2081ardb: Add DTS support for NXP
> LS2081ARDB
>
> We probably should rename the freescale folder to nxp with a separate patch,
> but it is better to stop using the name in the patch title right now.
>
OK, I will correct this
> On Wed, Apr 19, 2017 at 11:37 PM, Priyanka Jain <priyanka.jain@nxp.com>
> wrote:
> > This patch add support for NXP LS2081ARDB board which has LS2081A SoC.
> >
> > LS2081A SoC is 40-pin derivative of LS2088A SoC So, from functional
> > perspective both are same.
> > Hence,ls2088a SoC dtsi files are included from ls2081ARDB dts
> >
> > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/Makefile | 1 +
> > arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts | 139
> > +++++++++++++++++++++
> > 2 files changed, 140 insertions(+), 0 deletions(-) create mode
> > 100755 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile
> > b/arch/arm64/boot/dts/freescale/Makefile
> > index 72c4b52..58b80de 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb diff --git
> > a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
> > new file mode 100444
> > index 0000000..7ae408e
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
> > @@ -0,0 +1,139 @@
> > +/*
> > + * Device Tree file for NXP LS2081A RDB Board.
> > + *
> > + * Copyright (C) 2017, NXP Semiconductors
>
> The formal copyright claim formal should be Copyright 2017 NXP
>
OK, I will correct this
Priyanka
> > + *
> > + * Priyanka Jain <priyanka.jain@nxp.com>
> > + *
> > + * This file is dual-licensed: you can use it either under the terms
> > + * of the GPLv2 or the X11 license, at your option. Note that this
> > + dual
> > + * licensing only applies to this file, and not this project as a
> > + * whole.
> > + *
> > + * a) This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of the
> > + * License, or (at your option) any later version.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * Or, alternatively,
> > + *
> > + * b) Permission is hereby granted, free of charge, to any person
> > + * obtaining a copy of this software and associated documentation
> > + * files (the "Software"), to deal in the Software without
> > + * restriction, including without limitation the rights to use,
> > + * copy, modify, merge, publish, distribute, sublicense, and/or
> > + * sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following
> > + * conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
> > + * included in all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> WARRANTIES
> > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
> COPYRIGHT
> > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "fsl-ls2088a.dtsi"
> > +
> > +/ {
> > + model = "NXP Layerscape 2081A RDB Board";
> > + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
> > +
> > + aliases {
> > + serial0 = &serial0;
> > + serial1 = &serial1;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial1:115200n8";
> > + };
> > +};
> > +
> > +&esdhc {
> > + status = "okay";
> > +};
> > +
> > +&ifc {
> > + status = "disabled";
> > +};
> > +
> > +&i2c0 {
> > + status = "okay";
> > + pca9547@75 {
> > + compatible = "nxp,pca9547";
> > + reg = <0x75>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + i2c@1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x01>;
> > + rtc@51 {
> > + compatible = "nxp,pcf2129";
> > + reg = <0x51>;
> > + };
> > + };
> > +
> > + i2c@3 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x3>;
> > +
> > + adt7481@4c {
> > + compatible = "adi,adt7461";
> > + reg = <0x4c>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&dspi {
> > + status = "okay";
> > + dflash0: n25q512a {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "st,m25p80";
> > + spi-max-frequency = <3000000>;
> > + reg = <0>;
> > + };
> > +};
> > +
> > +
> > +&qspi {
> > + status = "okay";
> > + flash0: n25q512a@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "st,m25p80";
> > + spi-max-frequency = <20000000>;
> > + reg = <0>;
> > + };
> > + flash1: n25q512a@1 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "st,m25p80";
> > + spi-max-frequency = <20000000>;
> > + reg = <0>;
> > + };
> > +};
> > +
> > +&usb0 {
> > + status = "okay";
> > +};
> > +
> > +&usb1 {
> > + status = "okay";
> > +};
> > --
> > 1.7.4.1
> >
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe devicetree"
> > in the body of a message to majordomo@vger.kernel.org More majordomo
> > info at http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> - Leo
N‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·zøœzÚÞz)í…æèw*\x1fjg¬±¨\x1e¶‰šŽŠÝ¢j.ïÛ°\½½MŽúgjÌæa×\x02››–' ™©Þ¢¸\f¢·¦j:+v‰¨ŠwèjØm¶Ÿÿ¾\a«‘êçzZ+ƒùšŽŠÝ¢j"ú!¶i
^ permalink raw reply
* Re: [PATCH v5 10/10] arm: dts: genmai: Add ethernet pin group
From: Geert Uytterhoeven @ 2017-04-28 7:18 UTC (permalink / raw)
To: Chris Brandt
Cc: Jacopo Mondi, Linus Walleij, Geert Uytterhoeven, Laurent Pinchart,
Rob Herring, Mark Rutland, Russell King, Linux-Renesas,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <SG2PR06MB1165D46E83254B1757C790498A100@SG2PR06MB1165.apcprd06.prod.outlook.com>
Hi Chris,
On Thu, Apr 27, 2017 at 12:48 PM, Chris Brandt <Chris.Brandt@renesas.com> wrote:
> On Thursday, April 27, 2017, Geert Uytterhoeven wrote:
>> > +ðer {
>> > + pinctrl-names = "default";
>> > + pinctrl-0 = <ðer_pins>;
>> > +
>> > + status = "okay";
>> > +
>> > + renesas,no-ether-link;
>> > + phy-handle = <&phy0>;
>> > + phy0: ethernet-phy@0 {
>> > + reg = <0>;
>>
>> Shouldn't the interrupt (connected to P1_15) be described?
>
> That interrupt pin from the PHY is not used. It did not need to be connected.
But it is connected, according to the schematics.
DT describes hardware, not software limitations.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH/RFC 0/5] arm64: dts: renesas: Break out common board support
From: Geert Uytterhoeven @ 2017-04-28 7:11 UTC (permalink / raw)
To: Simon Horman
Cc: Geert Uytterhoeven, Magnus Damm, Kuninori Morimoto,
Yoshihiro Shimoda, Rob Herring, Mark Rutland, Linux-Renesas,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Vladimir Barinov
In-Reply-To: <20170428070458.GB10196@verge.net.au>
Hi SImon,
On Fri, Apr 28, 2017 at 9:04 AM, Simon Horman <horms@verge.net.au> wrote:
> On Thu, Apr 27, 2017 at 03:32:49PM +0200, Geert Uytterhoeven wrote:
>> On Wed, Apr 26, 2017 at 10:11 AM, Geert Uytterhoeven
>> <geert@linux-m68k.org> wrote:
>> > CC Vladimir (which I forgot to CC initially, sorry for that)
>> >
>> > On Wed, Apr 26, 2017 at 10:06 AM, Simon Horman <horms@verge.net.au> wrote:
>> >> On Fri, Apr 21, 2017 at 02:55:16PM +0200, Geert Uytterhoeven wrote:
>> >>> The Renesas Salvator-X and ULCB development board can be equipped with
>> >>> either an R-Car H3 or M3-W SiP, which are pin-compatible. All boards
>> >>> use separate DTBs, but currently there's no sharing of board-specific
>> >>> devices in DTS.
>> >>>
>> >>> This series reduces duplication by extracting common board support into
>> >>> their own .dtsi files. As the level of support varies across boards and
>> >>> SoCs, this requires the addition of a few external clocks and
>> >>> placeholder devices on R-Car M3-W, so the common board support DTS can
>> >>> refer to them.
>> >>>
>> >>> - Patches 1 and 2 add the external audio and PCIe bus clocks on R-Car
>> >>> M3-W, which are present in r8a7795.dtsi, and used in
>> >>> r8a7795-salvator-x.dts,
>> >>> - RFC patch 3 adds placeholders for devices that are not yet supported
>> >>> and/or tested on R-Car M3-W, but used on R-Car H3,
>> >>> - RFC patch 4 extracts common Salvator-X board support,
>> >>> - RFC patch 5 extracts common ULCB board support.
>> >>>
>> >>> For R-Car H3 based boards, there are no functional changes.
>> >>> For R-Car M3-W based boards, some new devices are now described in DT.
>> >>>
>> >>> Dependencies:
>> >>> - renesas-devel-20170420-v4.11-rc7,
>> >>> - Patches 1 and 2 can be applied as-is,
>> >>> - Patches 4 and 5 depend on "[PATCH 0/8] arm64: dts: renesas: Break
>> >>> out R-Car H3 and M3-W SiP"
>> >>> (http://www.spinics.net/lists/devicetree/msg173820.html).
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>> >>> DTB changes have been inspected using scripts/dtc/dtx_diff.
>> >>> This has been tested on Salvator-X (both H3 and M3-W).
>> >>> This has not been tested on H3ULCB and M3ULCB due to lack of hardware.
>> >>>
>> >>> Thanks for your comments!
>> >>
>> >> Thanks for tackling this important problem. I have looked over the changes
>> >> and they seem nice to me. I would, however, be more comfortable applying
>> >> them if they were rested on the ULCB boards.
>> >
>> > tested?
>> >
>> > I've pushed a branch for testing to topic/rcar3-dtsi-sharing in
>> > git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git.
>>
>> I managed to test it on the new H3ULCB and M3ULCB baords in Magnus' farm.
>> No issues detected.
>
> Great! Any objections to me queuing this up?
The dependency above (no feedback about the SiP types yet).
I can respin without that dependency, if that is preferred...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH/RFC 0/5] arm64: dts: renesas: Break out common board support
From: Simon Horman @ 2017-04-28 7:04 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Geert Uytterhoeven, Magnus Damm, Kuninori Morimoto,
Yoshihiro Shimoda, Rob Herring, Mark Rutland, Linux-Renesas,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Vladimir Barinov
In-Reply-To: <CAMuHMdV1SQoeEACaNLZbByRLbosMj5oxEysNDVevYgxqStDaug-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Thu, Apr 27, 2017 at 03:32:49PM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Wed, Apr 26, 2017 at 10:11 AM, Geert Uytterhoeven
> <geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org> wrote:
> > CC Vladimir (which I forgot to CC initially, sorry for that)
> >
> > On Wed, Apr 26, 2017 at 10:06 AM, Simon Horman <horms-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org> wrote:
> >> On Fri, Apr 21, 2017 at 02:55:16PM +0200, Geert Uytterhoeven wrote:
> >>> The Renesas Salvator-X and ULCB development board can be equipped with
> >>> either an R-Car H3 or M3-W SiP, which are pin-compatible. All boards
> >>> use separate DTBs, but currently there's no sharing of board-specific
> >>> devices in DTS.
> >>>
> >>> This series reduces duplication by extracting common board support into
> >>> their own .dtsi files. As the level of support varies across boards and
> >>> SoCs, this requires the addition of a few external clocks and
> >>> placeholder devices on R-Car M3-W, so the common board support DTS can
> >>> refer to them.
> >>>
> >>> - Patches 1 and 2 add the external audio and PCIe bus clocks on R-Car
> >>> M3-W, which are present in r8a7795.dtsi, and used in
> >>> r8a7795-salvator-x.dts,
> >>> - RFC patch 3 adds placeholders for devices that are not yet supported
> >>> and/or tested on R-Car M3-W, but used on R-Car H3,
> >>> - RFC patch 4 extracts common Salvator-X board support,
> >>> - RFC patch 5 extracts common ULCB board support.
> >>>
> >>> For R-Car H3 based boards, there are no functional changes.
> >>> For R-Car M3-W based boards, some new devices are now described in DT.
> >>>
> >>> Dependencies:
> >>> - renesas-devel-20170420-v4.11-rc7,
> >>> - Patches 1 and 2 can be applied as-is,
> >>> - Patches 4 and 5 depend on "[PATCH 0/8] arm64: dts: renesas: Break
> >>> out R-Car H3 and M3-W SiP"
> >>> (http://www.spinics.net/lists/devicetree/msg173820.html).
> >>>
> >>> DTB changes have been inspected using scripts/dtc/dtx_diff.
> >>> This has been tested on Salvator-X (both H3 and M3-W).
> >>> This has not been tested on H3ULCB and M3ULCB due to lack of hardware.
> >>>
> >>> Thanks for your comments!
> >>
> >> Thanks for tackling this important problem. I have looked over the changes
> >> and they seem nice to me. I would, however, be more comfortable applying
> >> them if they were rested on the ULCB boards.
> >
> > tested?
> >
> > I've pushed a branch for testing to topic/rcar3-dtsi-sharing in
> > git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git.
>
> I managed to test it on the new H3ULCB and M3ULCB baords in Magnus' farm.
> No issues detected.
Great! Any objections to me queuing this up?
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v5 00/10] Renesas RZ/A1 pin and gpio controller
From: Simon Horman @ 2017-04-28 5:22 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Jacopo Mondi, Linus Walleij, Geert Uytterhoeven, Laurent Pinchart,
Chris Brandt, Rob Herring, Mark Rutland, Russell King,
Linux-Renesas, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <CAMuHMdWw1JpFLT0QY4yQK6VH0oSeQOHUWMuKFSj6b6vrhHPCdA@mail.gmail.com>
On Thu, Apr 27, 2017 at 10:42:02AM +0200, Geert Uytterhoeven wrote:
> Hi Jacopo,
>
> On Thu, Apr 27, 2017 at 10:19 AM, Jacopo Mondi
> <jacopo+renesas@jmondi.org> wrote:
> > this is 5th round of gpio/pincontroller for RZ/A1 devices.
> >
> > I have updated the pin controller driver to use the newly introduced
> > "pinctrl_enable()" function.
> > This is required since v4.11-rc7 as otherwise, as reported by Chris Brandt,
> > the pin controller does not start.
> >
> > I have incorporated your comments on the device tree bindings documentation,
> > and added to pinctrl-generic.h header file two macros to unpack generic
> > properties and their arguments.
> >
> > Tested with SCIF, RIIC, ETHER and gpio-leds on Genmai board.
>
> Thanks for the update!
>
> > Jacopo Mondi (10):
> > pinctrl: generic: Add bi-directional and output-enable
>
> Already applied by LinusW.
>
> > pinctrl: generic: Add macros to unpack properties
>
> LinusW: do you want me to queue this together with the driver for v4.13,
> or will you take this single patch for v4.12?
>
> > pinctrl: Renesas RZ/A1 pin and gpio controller
> > dt-bindings: pinctrl: Add RZ/A1 bindings doc
>
> Will queue in sh-pfc-for-v4.13.
>
> > arm: dts: dt-bindings: Add Renesas RZ/A1 pinctrl header
> > arm: dts: r7s72100: Add pin controller node
> > arm: dts: genmai: Add SCIF2 pin group
> > arm: dts: genmai: Add RIIC2 pin group
> > arm: dts: genmai: Add user led device nodes
> > arm: dts: genmai: Add ethernet pin group
>
> These are for Simon.
>
> Does applying the DTS changes before the driver introduce regressions?
> If no, Simon can queue them for v4.13.
> If yes, they'll have to wait for v4.14.
That is my question too.
^ permalink raw reply
* Re: [PATCH v5 10/10] arm: dts: genmai: Add ethernet pin group
From: Simon Horman @ 2017-04-28 5:22 UTC (permalink / raw)
To: Chris Brandt
Cc: Geert Uytterhoeven, Jacopo Mondi, Linus Walleij,
Geert Uytterhoeven, Laurent Pinchart, Rob Herring, Mark Rutland,
Russell King, Linux-Renesas, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <SG2PR06MB1165D46E83254B1757C790498A100@SG2PR06MB1165.apcprd06.prod.outlook.com>
On Thu, Apr 27, 2017 at 10:48:45AM +0000, Chris Brandt wrote:
> Hi Geert,
>
> On Thursday, April 27, 2017, Geert Uytterhoeven wrote:
> > > +ðer {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <ðer_pins>;
> > > +
> > > + status = "okay";
> > > +
> > > + renesas,no-ether-link;
> > > + phy-handle = <&phy0>;
> > > + phy0: ethernet-phy@0 {
> > > + reg = <0>;
> >
> > Shouldn't the interrupt (connected to P1_15) be described?
>
>
> That interrupt pin from the PHY is not used. It did not need to be connected.
So things are fine as above or should I expect to see v6?
^ permalink raw reply
* Re: [PATCH v5 07/10] arm: dts: genmai: Add SCIF2 pin group
From: Simon Horman @ 2017-04-28 5:21 UTC (permalink / raw)
To: Jacopo Mondi
Cc: linus.walleij, geert+renesas, laurent.pinchart, chris.brandt,
robh+dt, mark.rutland, linux, linux-renesas-soc, linux-gpio,
devicetree, linux-kernel
In-Reply-To: <1493281194-5200-8-git-send-email-jacopo+renesas@jmondi.org>
On Thu, Apr 27, 2017 at 10:19:51AM +0200, Jacopo Mondi wrote:
> Add pin configuration subnode for SCIF2 serial debug interface.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
As the dt-bindings (documentation) has been acked by Geert I'd be happy
to queue up this and other "arm: dts: genmai" DT patches in this series
which do not have any outstanding review comments. Is it safe to do so
without the PFC driver patches in place?
> ---
> arch/arm/boot/dts/r7s72100-genmai.dts | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
> index 118a8e2..c28d74b 100644
> --- a/arch/arm/boot/dts/r7s72100-genmai.dts
> +++ b/arch/arm/boot/dts/r7s72100-genmai.dts
> @@ -11,6 +11,7 @@
>
> /dts-v1/;
> #include "r7s72100.dtsi"
> +#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
>
> / {
> model = "Genmai";
> @@ -36,6 +37,14 @@
> };
> };
>
> +&pinctrl {
> +
> + scif2_pins: serial2 {
> + /* P3_0 as TxD2; P3_2 as RxD2 */
> + pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
> + };
> +};
> +
> &extal_clk {
> clock-frequency = <13330000>;
> };
> @@ -60,6 +69,9 @@
> };
>
> &scif2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&scif2_pins>;
> +
> status = "okay";
> };
>
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v5 05/10] arm: dts: dt-bindings: Add Renesas RZ/A1 pinctrl header
From: Simon Horman @ 2017-04-28 5:19 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Jacopo Mondi, Linus Walleij, Geert Uytterhoeven, Laurent Pinchart,
Chris Brandt, Rob Herring, Mark Rutland, Russell King,
Linux-Renesas, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <CAMuHMdWwT6et+vRzeY1GiGYW-hS4w4ukWK8bUL+w-npMmdPkag@mail.gmail.com>
On Thu, Apr 27, 2017 at 10:38:39AM +0200, Geert Uytterhoeven wrote:
> On Thu, Apr 27, 2017 at 10:19 AM, Jacopo Mondi
> <jacopo+renesas@jmondi.org> wrote:
> > Add dt-bindings for Renesas r7s72100 pin controller header file.
> >
> > Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, I have queued this up.
^ permalink raw reply
* Re: [PATCH v2] arm: dts: sun7i-a20-bananapi: name the GPIO lines
From: Oleksij Rempel @ 2017-04-28 5:11 UTC (permalink / raw)
To: Linus Walleij
Cc: devicetree@vger.kernel.org, Chen-Yu Tsai, Oleksij Rempel,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <CACRpkdZn7-SL5kmGn7Pysz=QiQFBEm8+c6bw=hE5F0CV4ct0RQ@mail.gmail.com>
[-- Attachment #1.1.1: Type: text/plain, Size: 1137 bytes --]
Am 08.08.2016 um 19:51 schrieb Linus Walleij:
> On Fri, Aug 5, 2016 at 10:06 AM, Oleksij Rempel <linux@rempel-privat.de> wrote:
>
>> This names the GPIO lines on the Banana Pi board in accordance with
>> the A20_Banana_Pi v1.4 Specification.
>>
>> This will make these line names reflect through to userspace
>> so that they can easily be identified and used with the new
>> character device ABI.
>>
>> Some care has been taken to name all lines, not just those used
>> by the external connectors, also lines that are muxed into some
>> other function than GPIO: these are named "[FOO]" so that users
>> can see with lsgpio what all lines are used for.
>>
>> Ps: most of the text was taken from Linus Wallej patch.
>>
>> Cc: devicetree@vger.kernel.org
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: Chen-Yu Tsai <wens@csie.org>
>> Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> Yours,
> Linus Walleij
Hm... i assume this patch was lost. Should i resend it?
--
Regards,
Oleksij
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 213 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH V4 1/9] PM / OPP: Allow OPP table to be used for power-domains
From: Viresh Kumar @ 2017-04-28 5:00 UTC (permalink / raw)
To: Sudeep Holla, Rajendra Nayak
Cc: Mark Brown, Rafael Wysocki, ulf.hansson, Kevin Hilman,
Viresh Kumar, Nishanth Menon, Stephen Boyd, linaro-kernel,
linux-pm, linux-kernel, Vincent Guittot, robh+dt, lina.iyer,
devicetree
In-Reply-To: <9019aebe-95ba-b1b8-65a9-5be927934218@codeaurora.org>
On 27-04-17, 16:20, Rajendra Nayak wrote:
>
> On 04/27/2017 03:12 PM, Sudeep Holla wrote:
> []..
>
> >>
> >>> At qualcomm, we have an external M3 core (running its own firmware) which controls
> >>> a few voltage rails (including AVS on those). The devices vote for the voltage levels
> >
> > Thanks for explicitly mentioning this, but ...
> >
> >>> (or performance levels) they need by passing an integer value to the M3 (not actual
> >
> > you contradict here, is it just voltage or performance(i.e. frequency)
> > or both ? We need clarity there to choose the right representation.
>
> Its just voltage.
Right. Its just voltage in this case, but we can't speak of future
platforms here and we have to consider this thing as an operating
performance point only. I still think that this thread is moving in
the right direction, specially after V6 which looks much better.
If we have anything strong against the way V6 is trying to solve it, I
want to talk about it right now and get inputs from all the parties
involved. Scrapping all this work is fine, but I would like to do it
ASAP in that case :)
--
viresh
^ permalink raw reply
* [PATCH] of: unittest, fix possible use of unitialized variable
From: frowand.list-Re5JQEeQqe8AvxtiuMwx3w @ 2017-04-28 4:31 UTC (permalink / raw)
To: Rob Herring, stephen.boyd-QSEj5FYQhm4dnm+yROfE0A
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
From: Frank Rowand <frank.rowand-7U/KSKJipcs@public.gmane.org>
Fix problem reported in the linux-next build. last_sibling may be
unitialized in of_unittest() if the device tree is empty.
Signed-off-by: Frank Rowand <frank.rowand-7U/KSKJipcs@public.gmane.org>
---
drivers/of/unittest.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
index 12597ff8cfb0..8f14a43f48e5 100644
--- a/drivers/of/unittest.c
+++ b/drivers/of/unittest.c
@@ -2119,7 +2119,7 @@ static int __init overlay_data_add(int onum)
*/
static __init void of_unittest_overlay_high_level(void)
{
- struct device_node *last_sibling;
+ struct device_node *last_sibling = NULL;
struct device_node *np;
struct device_node *of_symbols;
struct device_node *overlay_base_symbols;
--
Frank Rowand <frank.rowand-7U/KSKJipcs@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH 1/2] PCI: mediatek: Add Mediatek PCIe host controller support
From: Ryder Lee @ 2017-04-28 2:46 UTC (permalink / raw)
To: Arnd Bergmann
Cc: devicetree, linux-pci, Linux Kernel Mailing List, Rob Herring,
linux-mediatek, Bjorn Helgaas, Linux ARM
In-Reply-To: <CAK8P3a0DjPL8uWuXfCmEwt05SCPJ0yEQTAJmZAPtFDEfsn4a1Q@mail.gmail.com>
Hi,
On Thu, 2017-04-27 at 20:55 +0200, Arnd Bergmann wrote:
> On Wed, Apr 26, 2017 at 10:10 AM, Ryder Lee <ryder.lee@mediatek.com> wrote:
> > On Tue, 2017-04-25 at 14:38 +0200, Arnd Bergmann wrote:
> >> On Sun, Apr 23, 2017 at 10:19 AM, Ryder Lee <ryder.lee@mediatek.com> wrote:
>
> >> > +static int mtk_pcie_enable_ports(struct mtk_pcie *pcie)
> >> > +{
> >> > + struct device *dev = pcie->dev;
> >> > + struct mtk_pcie_port *port, *tmp;
> >> > + int err, linkup = 0;
> >> > +
> >> > + list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
> >> > + err = clk_prepare_enable(port->sys_ck);
> >> > + if (err) {
> >> > + dev_err(dev, "failed to enable port%d clock\n",
> >> > + port->index);
> >> > + continue;
> >> > + }
> >> > +
> >> > + /* assert RC */
> >> > + reset_control_assert(port->reset);
> >> > + /* de-assert RC */
> >> > + reset_control_deassert(port->reset);
> >> > +
> >> > + /* power on PHY */
> >> > + err = phy_power_on(port->phy);
> >> > + if (err) {
> >> > + dev_err(dev, "failed to power on port%d phy\n",
> >> > + port->index);
> >> > + goto err_phy_on;
> >> > + }
> >> > +
> >> > + mtk_pcie_assert_ports(port);
> >> > +
> >>
> >> Similar to the comment I had for the binding, I wonder if it would be
> >> better to keep all the information about the ports in one place and
> >> then just deal with it at the root level.
> >>
> >> Alternatively, we could decide to standardize on the properties
> >> you have added to the pcie port node, but then I would handle
> >> them in the pcieport driver rather than in the host bridge driver.
> >
> > Sorry, I'm not sure what you want me to do here.
> >
> > I could move all clock operation in root level. But we need to keep the
> > reset and PHY operation sequence in the loop, In addition, we could
> > easily free resources if ports link fail.
> >
> > How about moving this function to mtk_pcie_parse_and_add_res()?
>
> That could work, please try it out and see if the code gets better or
> worse. This may depend on what we end up doing with the DT
> properties.
I will try it on next version, and we can continue our discussion on
that series.
> >> > +/*
> >> > + * This IP lacks interrupt status register to check or map INTx from
> >> > + * different devices at the same time.
> >> > + */
> >> > +static int __init mtk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
> >> > +{
> >> > + struct mtk_pcie *pcie = dev->bus->sysdata;
> >> > + struct mtk_pcie_port *port;
> >> > +
> >> > + list_for_each_entry(port, &pcie->ports, list)
> >> > + if (port->index == slot)
> >> > + return port->irq;
> >> > +
> >> > + return -1;
> >> > +}
> >>
> >> This looks odd, what is it needed for specifically? It looks like
> >> it's broken for devices behind bridges, and the interrupt mapping
> >> should normally come from the interrupt-map property, without
> >> the need for a driver specific map_irq override.
> >
> > Our hardware just has a GIC for each port and lacks interrupt status for
> > host driver to distinguish INTx. So I return port IRQ here.
>
> You should still be able to express this with standard interrupt-map
> DT property, without having to resort to your own map_irq
> callback handler.
>
> In the interrupt-map-mask, you can ignore the interrupt line
> only list the devfn of the root ports for each entry.
Okay, I will fix it.
> >> > +static int mtk_pcie_register_ports(struct mtk_pcie *pcie)
> >> > +{
> >> > + struct pci_bus *bus, *child;
> >> > +
> >> > + bus = pci_scan_root_bus(pcie->dev, 0, &mtk_pcie_ops, pcie,
> >> > + &pcie->resources);
> >>
> >> Can you use the new pci_register_host_bridge() method instead of
> >> pci_scan_root_bus() here?
> >
> > May I know what's difference between pci_scan_root_bus() and using
> > pci_register_host_bridge() directly? What situation should we use it?
> > It seems that just tegra use this new method currently.
>
> We introduced the new function for tegra for now, in the long run
> I would hope we can convert all other drivers to it as well, to make it
> easier to add further parameters.
>
> The new function also has a cleaner way of dealing with the memory
> allocations, similar to how other subsystems work.
Sounds good. I will change to use that.
Thanks!
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox