* Re: [PATCH v7 1/5] irqchip/aspeed-i2c-ic: binding docs for Aspeed I2C Interrupt Controller
From: Rob Herring @ 2017-04-28 18:19 UTC (permalink / raw)
To: Brendan Higgins
Cc: wsa-z923LK4zBo2bacvFa/9K2g, mark.rutland-5wv7dgnIgG8,
tglx-hfZtesqFncYOwBW4kG4KsQ, jason-NLaQJdtUoK4Be96aLqz0jA,
marc.zyngier-5wv7dgnIgG8, joel-U3u1mxZcP9KHXe+LvDLADg,
vz-ChpfBGZJDbMAvxtiuMwx3w, mouse-Pma6HLj0uuo, clg-Bxea+6Xhats,
benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20170424181818.2754-2-brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
On Mon, Apr 24, 2017 at 11:18:14AM -0700, Brendan Higgins wrote:
> Added device tree binding documentation for Aspeed I2C Interrupt
> Controller.
>
> Signed-off-by: Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
> ---
> Added in v6:
> - Pulled "aspeed_i2c_controller" out into a interrupt controller since that is
> what it actually does.
> Changes for v7:
> - None
> ---
> .../interrupt-controller/aspeed,ast2400-i2c-ic.txt | 25 ++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v7 3/5] i2c: aspeed: added documentation for Aspeed I2C driver
From: Rob Herring @ 2017-04-28 18:21 UTC (permalink / raw)
To: Brendan Higgins
Cc: wsa, mark.rutland, tglx, jason, marc.zyngier, joel, vz, mouse,
clg, benh, linux-i2c, devicetree, linux-kernel, openbmc
In-Reply-To: <20170424181818.2754-4-brendanhiggins@google.com>
On Mon, Apr 24, 2017 at 11:18:16AM -0700, Brendan Higgins wrote:
> Added device tree binding documentation for Aspeed I2C busses.
>
> Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
> ---
> Changes for v2:
> - None
> Changes for v3:
> - Removed reference to "bus" device tree param
> Changes for v4:
> - None
> Changes for v5:
> - None
> Changes for v6:
> - Replaced the controller property with and interrupt controller, leaving only
> the busses in the I2C documentation.
> Changes for v7:
> - Changed clock-frequency to bus-frequency in device tree
> ---
> .../devicetree/bindings/i2c/i2c-aspeed.txt | 47 ++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/i2c/i2c-aspeed.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 1/2] clk: Add bindings for the Gemini Clock Controller
From: Rob Herring @ 2017-04-28 18:24 UTC (permalink / raw)
To: Linus Walleij
Cc: Michael Turquette, Stephen Boyd, linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Janos Laube, Paulius Zaleckas,
openwrt-devel-p3rKhJxN3npAfugRpC6u6w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Hans Ulli Kroll, Florian Fainelli
In-Reply-To: <20170424185545.26608-1-linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Mon, Apr 24, 2017 at 08:55:45PM +0200, Linus Walleij wrote:
> This adds device tree bindings and a header for the Gemini SoC
> Clock Controller.
>
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> .../clock/cortina,gemini-clock-controller.txt | 25 +++++++++++++++++++
> include/dt-bindings/clock/cortina,gemini-clock.h | 29 ++++++++++++++++++++++
> 2 files changed, 54 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/cortina,gemini-clock-controller.txt
> create mode 100644 include/dt-bindings/clock/cortina,gemini-clock.h
>
> diff --git a/Documentation/devicetree/bindings/clock/cortina,gemini-clock-controller.txt b/Documentation/devicetree/bindings/clock/cortina,gemini-clock-controller.txt
> new file mode 100644
> index 000000000000..7af84acfcbce
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/cortina,gemini-clock-controller.txt
> @@ -0,0 +1,25 @@
> +Clock bindings for the Cortina Systems Gemini SoC Clock Controller
> +
> +Required properties :
> +- compatible : shall contain the following:
> + "cortina,gemini-clock-controller"
> +- #clock-cells should be <1>
> +
> +The Gemini clock controller needs to be placed as a subnode of the
> +system controller.
> +
> +All available clocks are defined as preprocessor macros in
> +dt-bindings/clock/cortina,gemini-clock.h header and can be used in device
> +tree sources.
> +
> +Example:
> +
> +syscon: syscon@40000000 {
> + compatible = "cortina,gemini-syscon", "syscon", "simple-mfd";
> + reg = <0x40000000 0x1000>;
> +
> + clock-controller {
> + compatible = "cortina,gemini-clock-controller";
> + #clock-cells = <1>;
There's not really much reason to have a child node here. The parent can
be the clock provider.
Rob
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* Re: [PATCH 1/2] reset: Add DT bindings for the Gemini reset controller
From: Rob Herring @ 2017-04-28 18:27 UTC (permalink / raw)
To: Linus Walleij
Cc: Philipp Zabel, devicetree-u79uwXL29TY76Z2rM5mHXA, Janos Laube,
Paulius Zaleckas, openwrt-devel-p3rKhJxN3npAfugRpC6u6w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Hans Ulli Kroll, Florian Fainelli
In-Reply-To: <20170424192746.27378-1-linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Mon, Apr 24, 2017 at 09:27:46PM +0200, Linus Walleij wrote:
> This is a simple reset controller in a single 32bit
> register.
>
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> .../bindings/reset/cortina,gemini-reset.txt | 59 ++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/cortina,gemini-reset.txt
>
> diff --git a/Documentation/devicetree/bindings/reset/cortina,gemini-reset.txt b/Documentation/devicetree/bindings/reset/cortina,gemini-reset.txt
> new file mode 100644
> index 000000000000..21aa12901774
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/cortina,gemini-reset.txt
> @@ -0,0 +1,59 @@
> +Cortina Gemini Reset Controller
> +
> +This reset controller is found in Cortina Systems CS3516 and
> +the predecessor StorLink SL3516.
> +
> +Required properties:
> +- compatible: "cortina,gemini-reset"
> +- #reset-cells: Must be 1
> +
> +The Gemini reset controller must be a child node of the
> +system controller. Apart from this it follows the standard reset
> +controller bindings.
Same comment as clocks. The parent can be the provider.
> +
> +Valid reset line values:
> +
> +0: DRAM controller
Why no header like clocks?
> +1: Flash controller
> +2: IDE controller
> +3: RAID controller
> +4: Security module
> +5: GMAC0 (ethernet)
> +6: GMAC1 (ethernet)
> +7: PCI host bridge
> +8: USB0 USB host controller
> +9: USB1 USB host controller
> +10: General DMA controller
> +11: APB bridge
> +12: LPC (Low Pin Count) controller
> +13: LCD module
> +14: Interrupt controller 0
> +15: Interrupt controller 1
> +16: RTC module
> +17: Timer module
> +18: UART controller
> +19: SSP controller
> +20: GPIO0 GPIO controller
> +21: GPIO1 GPIO controller
> +22: GPIO2 GPIO controller
> +23: Watchdog timer
> +24: External device reset
> +25: CIR module (infrared)
> +26: SATA0 SATA bridge
> +27: SATA1 SATA bridge
> +28: TVE TV Encoder module
> +29: Reserved
> +30: CPU1 reset
> +31: Global soft reset
> +
> +Example:
> +
> +syscon: syscon@40000000 {
> + compatible = "cortina,gemini-syscon", "syscon", "simple-mfd";
> + reg = <0x40000000 0x1000>;
> +
> + reset-controller {
> + compatible = "cortina,gemini-reset";
> + #reset-cells = <1>;
> + };
> +};
> --
> 2.9.3
>
> --
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^ permalink raw reply
* Re: [PATCH 1/3 v3] drm/vc4: Turn the V3D clock on at runtime.
From: Rob Herring @ 2017-04-28 18:29 UTC (permalink / raw)
To: Eric Anholt; +Cc: Mark Rutland, devicetree, linux-kernel, dri-devel
In-Reply-To: <20170424201209.31148-1-eric@anholt.net>
On Mon, Apr 24, 2017 at 01:12:09PM -0700, Eric Anholt wrote:
> For the Raspberry Pi's bindings, the power domain also implicitly
> turns on the clock and deasserts reset, but for the new Cygnus port we
> start representing the clock in the devicetree.
>
> v2: Document the clock-names property, check for -ENOENT for no clock
> in DT.
> v3: Drop NULL checks around clk calls which embed NULL checks.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
> ---
> .../devicetree/bindings/display/brcm,bcm-vc4.txt | 4 +++
> drivers/gpu/drm/vc4/vc4_drv.h | 1 +
> drivers/gpu/drm/vc4/vc4_v3d.c | 31 +++++++++++++++++++++-
> 3 files changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt b/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
> index ca02d3e4db91..2318266f6481 100644
> --- a/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
> +++ b/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
> @@ -59,6 +59,10 @@ Required properties for V3D:
> - interrupts: The interrupt number
> See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
>
> +Optional properties for V3D:
> +- clocks: The clock the unit runs on
> +- clock-names: Must be "v3d_clk"
clock-names is pointless for a single clock.
> +
> Required properties for DSI:
> - compatible: Should be "brcm,bcm2835-dsi0" or "brcm,bcm2835-dsi1"
> - reg: Physical base address and length of the DSI block's registers
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCHv2 1/3] dt-bindings: display: Intel FPGA VIP drm driver Devicetree bindings
From: Rob Herring @ 2017-04-28 18:32 UTC (permalink / raw)
To: hean.loong.ong
Cc: devicetree, tien.hock.loh, dri-devel, dinguyen, daniel.vetter,
Ong
In-Reply-To: <1493086006-4392-2-git-send-email-hean.loong.ong@intel.com>
On Tue, Apr 25, 2017 at 10:06:44AM +0800, hean.loong.ong@intel.com wrote:
> From: "Ong, Hean Loong" <hean.loong.ong@intel.com>
>
> Device tree binding for Intel FPGA Video and Image
> Processing Suite. The binding involved would be generated
> from the Altera (Intel) Qsys system. The bindings would
> set the max width, max height, buts per pixel and memory
> port width. The device tree binding only supports the Intel
> Arria10 devkit and its variants. Vendor name retained as
> altr.
>
> Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
> ---
> v2:
> * Moved Device Tree bindings to Documentation/devicetree/bindings/display/
> * Added vendor name altr, to description
> ---
> .../devicetree/bindings/display/altr,vip-fb2.txt | 30 ++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt
>
> diff --git a/Documentation/devicetree/bindings/display/altr,vip-fb2.txt b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt
> new file mode 100644
> index 0000000..bdffefb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt
> @@ -0,0 +1,30 @@
> +Intel Video and Image Processing(VIP) Frame Buffer II bindings
> +
> +Supported hardware: Arria 10 and above with display port IP
> +
> +The drm driver for the Arria 10 devkit would require the display resolution
Bindings describe h/w. DRM driver is a Linux term.
> +and pixel information to be included as these values are generated based
> +on the FPGA design that drives the video connector attached to the drm driver
> +Information the FPGA video IP component can be acquired from
> +https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_vip.pdf
> +
> +Required properties:
> +
> +- compatible: "altr,vip-frame-buffer-2.0"
> +- reg: Physical base address and length of the framebuffer controller's
> + registers.
> +- altr,max-width: The width of the framebuffer in pixels.
> +- altr,max-height: The height of the framebuffer in pixels.
> +- altr,bits-per-symbol: only "8" is currently supported
Supported in the driver or IP? The former isn't relevant to the binding.
In the latter case, you don't need it if that's the only thing
supported.
> +- altr,mem-port-width = the bus width of the avalon master port on the frame reader
In bits or bytes?
> +
> +Example:
> +
> + dp_0_frame_buf: vip@100000280 {
> + compatible = "altr,vip-frame-buffer-2.0";
> + reg = <0x00000001 0x00000280 0x00000040>;
> + altr,max-width = <1280>;
> + altr,max-height = <720>;
> + altr,bits-per-symbol = <8>;
> + altr,mem-port-width = <128>;
> + };
> --
> 2.7.4
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH] PM / Domains: Fix DT example
From: Rob Herring @ 2017-04-28 18:37 UTC (permalink / raw)
To: Viresh Kumar
Cc: Rafael Wysocki, Kevin Hilman, Ulf Hansson,
linaro-kernel-cunTk1MwBs8s++Sfvej+rw,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Vincent Guittot,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <533b52e0ea175bf6bb893370c7f8c0309aae235a.1493104411.git.viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Tue, Apr 25, 2017 at 12:48:21PM +0530, Viresh Kumar wrote:
> The power-domain provider's #power-domain-cells field is set to 0 and
> yet the children is using an index to point the power domain. Fix it by
> removing the index field.
>
> Fixes: 70bb510e4279 ("dt/bindings / PM/Domains: Update binding for PM domain idle states")
> Signed-off-by: Viresh Kumar <viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> Documentation/devicetree/bindings/power/power_domain.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* [PATCH v3] pinctrl: sh-pfc: r8a7794: add R8A7745 support
From: Sergei Shtylyov @ 2017-04-28 18:52 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Laurent Pinchart, Geert Uytterhoeven,
Linus Walleij, devicetree, linux-renesas-soc, linux-gpio
Cc: Sergei Shtylyov
[-- Attachment #1: pinctrl-sh-pfc-r8a7794-add-R8A7745-support-v3.patch --]
[-- Type: text/plain, Size: 57548 bytes --]
Renesas RZ/G1E (R8A7745) is pin compatible with R-Car E2 (R8A7794),
however it doesn't have several automotive specific peripherals.
Annotate all the items that only exist on the R-Car SoCs...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git'
repo plus 3 R8A7794 PFC driver fixes/cleanups posted today and the R8A7743 PFC
support patch posted last week...
Changes in version 3:
- resolved rejects atop of the new R8A7794 driver patches renaming the IIC0/1
signals and removing reserved groups/signals;
- undid splitting of 'pinmux_{groups|functions}' arrays into the common and
R8A7794 specfic parts, updated the patch description accordingly;
- kill double spaces in the patch description.
Changes in version 2:
- fixed indentation to use tabs instead of spaces;
- updated the PFC bindings.
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1
drivers/pinctrl/sh-pfc/Kconfig | 5
drivers/pinctrl/sh-pfc/Makefile | 1
drivers/pinctrl/sh-pfc/core.c | 6
drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 640 +++++-----
drivers/pinctrl/sh-pfc/sh_pfc.h | 1
6 files changed, 369 insertions(+), 285 deletions(-)
Index: linux-pinctrl/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
===================================================================
--- linux-pinctrl.orig/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ linux-pinctrl/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -14,6 +14,7 @@ Required Properties:
- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
+ - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/Kconfig
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/Kconfig
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/Kconfig
@@ -39,6 +39,11 @@ config PINCTRL_PFC_R8A7743
depends on ARCH_R8A7743
select PINCTRL_SH_PFC
+config PINCTRL_PFC_R8A7745
+ def_bool y
+ depends on ARCH_R8A7745
+ select PINCTRL_SH_PFC
+
config PINCTRL_PFC_R8A7778
def_bool y
depends on ARCH_R8A7778
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/Makefile
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/Makefile
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-e
obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o
obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/core.c
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/core.c
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/core.c
@@ -491,6 +491,12 @@ static const struct of_device_id sh_pfc_
.data = &r8a7743_pinmux_info,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7745
+ {
+ .compatible = "renesas,pfc-r8a7745",
+ .data = &r8a7745_pinmux_info,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7778
{
.compatible = "renesas,pfc-r8a7778",
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -1,9 +1,9 @@
/*
- * r8a7794 processor support - PFC hardware block.
+ * r8a7794/r8a7745 processor support - PFC hardware block.
*
* Copyright (C) 2014-2015 Renesas Electronics Corporation
* Copyright (C) 2015 Renesas Solutions Corp.
- * Copyright (C) 2015-2016 Cogent Embedded, Inc., <source@cogentembedded.com>
+ * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
@@ -132,8 +132,8 @@ enum {
FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
- FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
- FN_TPUTO2_B,
+ FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN /* R8A7794 only */,
+ FN_CAN_CLK_C, FN_TPUTO2_B,
FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
@@ -149,13 +149,16 @@ enum {
FN_CS1_N_A26, FN_VI1_DATA9,
FN_EX_CS0_N, FN_VI1_DATA10,
FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
- FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
- FN_SCIFB2_TXD,
- FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
+ FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B /* R8A7794 only */,
+ FN_TPUTO3, FN_SCIFB2_TXD,
+ FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C,
+ FN_TS_SCK_B /* R8A7794 only */, FN_BPFCLK /* R8A7794 only */,
FN_SCIFB2_SCK,
- FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
+ FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E,
+ FN_TS_SDEN_B /* R8A7794 only */, FN_FMCLK /* R8A7794 only */,
FN_SCIFB2_CTS_N,
- FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
+ FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E,
+ FN_TS_SPSYNC_B /* R8A7794 only */, FN_FMIN /* R8A7794 only */,
FN_SCIFB2_RTS_N,
FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
FN_RD_N, FN_ATACS11_N,
@@ -163,42 +166,48 @@ enum {
/* IPSR4 */
FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
- FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
- FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
- FN_DU0_DR2, FN_LCDOUT18,
- FN_DU0_DR3, FN_LCDOUT19,
- FN_DU0_DR4, FN_LCDOUT20,
- FN_DU0_DR5, FN_LCDOUT21,
- FN_DU0_DR6, FN_LCDOUT22,
- FN_DU0_DR7, FN_LCDOUT23,
- FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
- FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
- FN_DU0_DG2, FN_LCDOUT10,
- FN_DU0_DG3, FN_LCDOUT11,
- FN_DU0_DG4, FN_LCDOUT12,
+ FN_DU0_DR0, FN_LCDOUT16 /* R8A7794 only */, FN_SCIF5_RXD_C,
+ FN_I2C2_SCL_D,
+ FN_DU0_DR1, FN_LCDOUT17 /* R8A7794 only */, FN_SCIF5_TXD_C,
+ FN_I2C2_SDA_D,
+ FN_DU0_DR2, FN_LCDOUT18 /* R8A7794 only */,
+ FN_DU0_DR3, FN_LCDOUT19 /* R8A7794 only */,
+ FN_DU0_DR4, FN_LCDOUT20 /* R8A7794 only */,
+ FN_DU0_DR5, FN_LCDOUT21 /* R8A7794 only */,
+ FN_DU0_DR6, FN_LCDOUT22 /* R8A7794 only */,
+ FN_DU0_DR7, FN_LCDOUT23 /* R8A7794 only */,
+ FN_DU0_DG0, FN_LCDOUT8 /* R8A7794 only */, FN_SCIFA0_RXD_C,
+ FN_I2C3_SCL_D,
+ FN_DU0_DG1, FN_LCDOUT9 /* R8A7794 only */, FN_SCIFA0_TXD_C,
+ FN_I2C3_SDA_D,
+ FN_DU0_DG2, FN_LCDOUT10 /* R8A7794 only */,
+ FN_DU0_DG3, FN_LCDOUT11 /* R8A7794 only */,
+ FN_DU0_DG4, FN_LCDOUT12 /* R8A7794 only */,
/* IPSR5 */
- FN_DU0_DG5, FN_LCDOUT13,
- FN_DU0_DG6, FN_LCDOUT14,
- FN_DU0_DG7, FN_LCDOUT15,
- FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
- FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
- FN_DU0_DB2, FN_LCDOUT2,
- FN_DU0_DB3, FN_LCDOUT3,
- FN_DU0_DB4, FN_LCDOUT4,
- FN_DU0_DB5, FN_LCDOUT5,
- FN_DU0_DB6, FN_LCDOUT6,
- FN_DU0_DB7, FN_LCDOUT7,
- FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
- FN_DU0_DOTCLKOUT0, FN_QCLK,
- FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
- FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
+ FN_DU0_DG5, FN_LCDOUT13 /* R8A7794 only */,
+ FN_DU0_DG6, FN_LCDOUT14 /* R8A7794 only */,
+ FN_DU0_DG7, FN_LCDOUT15 /* R8A7794 only */,
+ FN_DU0_DB0, FN_LCDOUT0 /* R8A7794 only */, FN_SCIFA4_RXD_C,
+ FN_I2C4_SCL_D, FN_CAN0_RX_C,
+ FN_DU0_DB1, FN_LCDOUT1 /* R8A7794 only */, FN_SCIFA4_TXD_C,
+ FN_I2C4_SDA_D, FN_CAN0_TX_C,
+ FN_DU0_DB2, FN_LCDOUT2 /* R8A7794 only */,
+ FN_DU0_DB3, FN_LCDOUT3 /* R8A7794 only */,
+ FN_DU0_DB4, FN_LCDOUT4 /* R8A7794 only */,
+ FN_DU0_DB5, FN_LCDOUT5 /* R8A7794 only */,
+ FN_DU0_DB6, FN_LCDOUT6 /* R8A7794 only */,
+ FN_DU0_DB7, FN_LCDOUT7 /* R8A7794 only */,
+ FN_DU0_DOTCLKIN, FN_QSTVA_QVS /* R8A7794 only */,
+ FN_DU0_DOTCLKOUT0, FN_QCLK /* R8A7794 only */,
+ FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE /* R8A7794 only */,
+ FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS /* R8A7794 only */,
/* IPSR6 */
- FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
- FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
- FN_DU0_DISP, FN_QPOLA,
- FN_DU0_CDE, FN_QPOLB,
+ FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE /* R8A7794 only */,
+ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE /* R8A7794 only */,
+ FN_DU0_DISP, FN_QPOLA /* R8A7794 only */,
+ FN_DU0_CDE, FN_QPOLB /* R8A7794 only */,
FN_VI0_CLK, FN_AVB_RX_CLK,
FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
@@ -208,25 +217,28 @@ enum {
FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
- FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
- FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
- FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
+ FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C,
+ FN_IETX_C /* R8A7794 only */, FN_AVB_RXD7,
+ FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C,
+ FN_IECLK_C /* R8A7794 only */, FN_AVB_RX_ER,
+ FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C,
+ FN_IERX_C /* R8A7794 only */, FN_AVB_COL,
FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
FN_AVB_TX_EN,
FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
- FN_ADIDATA,
+ FN_ADIDATA /* R8A7794 only */,
/* IPSR7 */
FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
- FN_ADICS_SAMP,
+ FN_ADICS_SAMP /* R8A7794 only */,
FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
- FN_ADICLK,
+ FN_ADICLK /* R8A7794 only */,
FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
- FN_ADICHS0,
+ FN_ADICHS0 /* R8A7794 only */,
FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
- FN_ADICHS1,
+ FN_ADICHS1 /* R8A7794 only */,
FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
- FN_ADICHS2,
+ FN_ADICHS2 /* R8A7794 only */,
FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
FN_SSI_WS5_B,
@@ -253,26 +265,32 @@ enum {
FN_CAN1_RX_D, FN_TPUTO0_B,
FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
FN_CAN1_TX_D,
- FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
- FN_TPUTO1_B,
- FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
- FN_BPFCLK_C,
- FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
- FN_FMCLK_C,
+ FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
+ FN_TS_SDATA_D /* R8A7794 only */, FN_TPUTO1_B,
+ FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
+ FN_TS_SCK_D /* R8A7794 only */, FN_BPFCLK_C /* R8A7794 only */,
+ FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
+ FN_TS_SDEN_D /* R8A7794 only */, FN_FMCLK_C /* R8A7794 only */,
/* IPSR9 */
- FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
- FN_FMIN_C,
- FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
- FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
- FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
- FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
+ FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
+ FN_TS_SPSYNC_D /* R8A7794 only */, FN_FMIN_C /* R8A7794 only */,
+ FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA /* R8A7794 only */, FN_DU1_DR4,
+ FN_TPUTO1_C,
+ FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK /* R8A7794 only */, FN_DU1_DR5,
+ FN_BPFCLK_B /* R8A7794 only */,
+ FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN /* R8A7794 only */, FN_DU1_DR6,
+ FN_FMCLK_B /* R8A7794 only */,
+ FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC /* R8A7794 only */,
+ FN_DU1_DR7, FN_FMIN_B /* R8A7794 only */,
FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
- FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
- FN_SPEEDIN_B,
- FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
- FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
+ FN_HSCIF1_HSCK, FN_PWM2, FN_IETX /* R8A7794 only */, FN_DU1_DG2,
+ FN_REMOCON_B /* R8A7794 only */, FN_SPEEDIN_B /* R8A7794 only */,
+ FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK /* R8A7794 only */,
+ FN_DU1_DG3, FN_SSI_SCK1_B,
+ FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX /* R8A7794 only */,
+ FN_DU1_DG4, FN_SSI_WS1_B,
FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
/* IPSR10 */
@@ -281,11 +299,12 @@ enum {
FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
- FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
- FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
- FN_SSI_SCK4_B,
- FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
- FN_SSI_WS4_B,
+ FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D /* R8A7794 only */, FN_DU1_DB3,
+ FN_SSI_SDATA9_B,
+ FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D /* R8A7794 only */, FN_DU1_DB4,
+ FN_AUDIO_CLKA_C, FN_SSI_SCK4_B,
+ FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D /* R8A7794 only */, FN_DU1_DB5,
+ FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
FN_SSI_SDATA4_B,
FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
@@ -301,21 +320,28 @@ enum {
FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
- FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
- FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
- FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
+ FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D,
+ FN_ADIDATA_B /* R8A7794 only */,
+ FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
+ FN_ADICS_SAMP_B /* R8A7794 only */,
+ FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
+ FN_ADICLK_B /* R8A7794 only */,
/* IPSR12 */
- FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
- FN_DREQ1_N_B,
- FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
- FN_CAN1_RX_C, FN_DACK1_B,
- FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
- FN_CAN1_TX_C, FN_DREQ2_N,
- FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
- FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
- FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
- FN_DACK2, FN_ETH_MDIO_B,
+ FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C,
+ FN_ADICHS0_B /* R8A7794 only */, FN_DREQ1_N_B,
+ FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C,
+ FN_ADICHS1_B /* R8A7794 only */, FN_CAN1_RX_C, FN_DACK1_B,
+ FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C,
+ FN_ADICHS2_B /* R8A7794 only */, FN_CAN1_TX_C, FN_DREQ2_N,
+ FN_SSI_SCK4, FN_MLB_CLK /* R8A7794 only */,
+ FN_IETX_B /* R8A7794 only */,
+ FN_SSI_WS4, FN_MLB_SIG /* R8A7794 only */,
+ FN_IECLK_B /* R8A7794 only */,
+ FN_SSI_SDATA4, FN_MLB_DAT /* R8A7794 only */,
+ FN_IERX_B /* R8A7794 only */,
+ FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
+ FN_REMOCON /* R8A7794 only */, FN_DACK2, FN_ETH_MDIO_B,
FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
FN_ETH_CRS_DV_B,
FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
@@ -336,19 +362,20 @@ enum {
FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
FN_ATADIR0_N, FN_ETH_MAGIC_B,
FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
- FN_TS_SDATA_C, FN_ETH_TXD0_B,
+ FN_TS_SDATA_C /* R8A7794 only */, FN_ETH_TXD0_B,
FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
- FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
+ FN_TS_SCK_C /* R8A7794 only */, FN_BPFCLK_E /* R8A7794 only */,
+ FN_ETH_MDC_B,
FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
- FN_TS_SDEN_C, FN_FMCLK_E,
+ FN_TS_SDEN_C /* R8A7794 only */, FN_FMCLK_E /* R8A7794 only */,
FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
- FN_TS_SPSYNC_C, FN_FMIN_E,
+ FN_TS_SPSYNC_C /* R8A7794 only */, FN_FMIN_E /* R8A7794 only */,
/* MOD_SEL */
FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
- FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
- FN_SEL_DARC_4,
+ /* R8A7794 only */ FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2,
+ /* R8A7794 only */ FN_SEL_DARC_3, FN_SEL_DARC_4,
FN_SEL_ETH_0, FN_SEL_ETH_1,
FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
FN_SEL_I2C00_4,
@@ -363,18 +390,20 @@ enum {
FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
/* MOD_SEL2 */
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+ /* R8A7794 only */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
- FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
+ /* R8A7794 only */ FN_SEL_RCN_0, FN_SEL_RCN_1,
+ /* R8A7794 only */ FN_SEL_RSP_0, FN_SEL_RSP_1,
FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
FN_SEL_TMU_0, FN_SEL_TMU_1,
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+ /* R8A7794 only */ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2,
+ /* R8A7794 only */ FN_SEL_TSIF0_3,
FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
@@ -443,8 +472,8 @@ enum {
A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
- A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
- CAN_CLK_C_MARK, TPUTO2_B_MARK,
+ A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK,
+ SPEEDIN_MARK /* R8A7794 only */, CAN_CLK_C_MARK, TPUTO2_B_MARK,
A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
@@ -460,57 +489,65 @@ enum {
CS1_N_A26_MARK, VI1_DATA9_MARK,
EX_CS0_N_MARK, VI1_DATA10_MARK,
EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
- EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
- TPUTO3_MARK, SCIFB2_TXD_MARK,
- EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
- BPFCLK_MARK, SCIFB2_SCK_MARK,
- EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
- FMCLK_MARK, SCIFB2_CTS_N_MARK,
- EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
- FMIN_MARK, SCIFB2_RTS_N_MARK,
+ EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK,
+ TS_SDATA_B_MARK /* R8A7794 only */, TPUTO3_MARK, SCIFB2_TXD_MARK,
+ EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK,
+ TS_SCK_B_MARK /* R8A7794 only */, BPFCLK_MARK /* R8A7794 only */,
+ SCIFB2_SCK_MARK,
+ EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK,
+ TS_SDEN_B_MARK /* R8A7794 only */, FMCLK_MARK /* R8A7794 only */,
+ SCIFB2_CTS_N_MARK,
+ EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK,
+ TS_SPSYNC_B_MARK /* R8A7794 only */, FMIN_MARK /* R8A7794 only */,
+ SCIFB2_RTS_N_MARK,
BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
RD_N_MARK, ATACS11_N_MARK,
RD_WR_N_MARK, ATAG1_N_MARK,
/* IPSR4 */
EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
- DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
- DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
- DU0_DR2_MARK, LCDOUT18_MARK,
- DU0_DR3_MARK, LCDOUT19_MARK,
- DU0_DR4_MARK, LCDOUT20_MARK,
- DU0_DR5_MARK, LCDOUT21_MARK,
- DU0_DR6_MARK, LCDOUT22_MARK,
- DU0_DR7_MARK, LCDOUT23_MARK,
- DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
- DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
- DU0_DG2_MARK, LCDOUT10_MARK,
- DU0_DG3_MARK, LCDOUT11_MARK,
- DU0_DG4_MARK, LCDOUT12_MARK,
+ DU0_DR0_MARK, LCDOUT16_MARK /* R8A7794 only */, SCIF5_RXD_C_MARK,
+ I2C2_SCL_D_MARK,
+ DU0_DR1_MARK, LCDOUT17_MARK /* R8A7794 only */, SCIF5_TXD_C_MARK,
+ I2C2_SDA_D_MARK,
+ DU0_DR2_MARK, LCDOUT18_MARK /* R8A7794 only */,
+ DU0_DR3_MARK, LCDOUT19_MARK /* R8A7794 only */,
+ DU0_DR4_MARK, LCDOUT20_MARK /* R8A7794 only */,
+ DU0_DR5_MARK, LCDOUT21_MARK /* R8A7794 only */,
+ DU0_DR6_MARK, LCDOUT22_MARK /* R8A7794 only */,
+ DU0_DR7_MARK, LCDOUT23_MARK /* R8A7794 only */,
+ DU0_DG0_MARK, LCDOUT8_MARK /* R8A7794 only */, SCIFA0_RXD_C_MARK,
+ I2C3_SCL_D_MARK,
+ DU0_DG1_MARK, LCDOUT9_MARK /* R8A7794 only */, SCIFA0_TXD_C_MARK,
+ I2C3_SDA_D_MARK,
+ DU0_DG2_MARK, LCDOUT10_MARK /* R8A7794 only */,
+ DU0_DG3_MARK, LCDOUT11_MARK /* R8A7794 only */,
+ DU0_DG4_MARK, LCDOUT12_MARK /* R8A7794 only */,
/* IPSR5 */
- DU0_DG5_MARK, LCDOUT13_MARK,
- DU0_DG6_MARK, LCDOUT14_MARK,
- DU0_DG7_MARK, LCDOUT15_MARK,
- DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
- CAN0_RX_C_MARK,
- DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
- CAN0_TX_C_MARK,
- DU0_DB2_MARK, LCDOUT2_MARK,
- DU0_DB3_MARK, LCDOUT3_MARK,
- DU0_DB4_MARK, LCDOUT4_MARK,
- DU0_DB5_MARK, LCDOUT5_MARK,
- DU0_DB6_MARK, LCDOUT6_MARK,
- DU0_DB7_MARK, LCDOUT7_MARK,
- DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
- DU0_DOTCLKOUT0_MARK, QCLK_MARK,
- DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
- DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
+ DU0_DG5_MARK, LCDOUT13_MARK /* R8A7794 only */,
+ DU0_DG6_MARK, LCDOUT14_MARK /* R8A7794 only */,
+ DU0_DG7_MARK, LCDOUT15_MARK /* R8A7794 only */,
+ DU0_DB0_MARK, LCDOUT0_MARK /* R8A7794 only */, SCIFA4_RXD_C_MARK,
+ I2C4_SCL_D_MARK, CAN0_RX_C_MARK,
+ DU0_DB1_MARK, LCDOUT1_MARK /* R8A7794 only */, SCIFA4_TXD_C_MARK,
+ I2C4_SDA_D_MARK, CAN0_TX_C_MARK,
+ DU0_DB2_MARK, LCDOUT2_MARK /* R8A7794 only */,
+ DU0_DB3_MARK, LCDOUT3_MARK /* R8A7794 only */,
+ DU0_DB4_MARK, LCDOUT4_MARK /* R8A7794 only */,
+ DU0_DB5_MARK, LCDOUT5_MARK /* R8A7794 only */,
+ DU0_DB6_MARK, LCDOUT6_MARK /* R8A7794 only */,
+ DU0_DB7_MARK, LCDOUT7_MARK /* R8A7794 only */,
+ DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK /* R8A7794 only */,
+ DU0_DOTCLKOUT0_MARK, QCLK_MARK /* R8A7794 only */,
+ DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK /* R8A7794 only */,
+ DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK /* R8A7794 only */,
/* IPSR6 */
- DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
- DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
- DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
+ DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK /* R8A7794 only */,
+ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK /* R8A7794 only */,
+ DU0_DISP_MARK, QPOLA_MARK /* R8A7794 only */,
+ DU0_CDE_MARK, QPOLB_MARK /* R8A7794 only */,
VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
@@ -519,28 +556,28 @@ enum {
VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
- VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
- AVB_RXD7_MARK,
- VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
- AVB_RX_ER_MARK,
- VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
- AVB_COL_MARK,
+ VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK,
+ IETX_C_MARK /* R8A7794 only */, AVB_RXD7_MARK,
+ VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK,
+ IECLK_C_MARK /* R8A7794 only */, AVB_RX_ER_MARK,
+ VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
+ IERX_C_MARK /* R8A7794 only */, AVB_COL_MARK,
VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
- AVB_TX_CLK_MARK, ADIDATA_MARK,
+ AVB_TX_CLK_MARK, ADIDATA_MARK /* R8A7794 only */,
/* IPSR7 */
ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
- AVB_TXD0_MARK, ADICS_SAMP_MARK,
+ AVB_TXD0_MARK, ADICS_SAMP_MARK /* R8A7794 only */,
ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
- AVB_TXD1_MARK, ADICLK_MARK,
+ AVB_TXD1_MARK, ADICLK_MARK /* R8A7794 only */,
ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
- AVB_TXD2_MARK, ADICHS0_MARK,
+ AVB_TXD2_MARK, ADICHS0_MARK /* R8A7794 only */,
ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
- AVB_TXD3_MARK, ADICHS1_MARK,
+ AVB_TXD3_MARK, ADICHS1_MARK /* R8A7794 only */,
ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
- AVB_TXD4_MARK, ADICHS2_MARK,
+ AVB_TXD4_MARK, ADICHS2_MARK /* R8A7794 only */,
ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
SSI_SCK5_B_MARK,
ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
@@ -568,31 +605,34 @@ enum {
SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
CAN1_TX_D_MARK,
I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
- TS_SDATA_D_MARK, TPUTO1_B_MARK,
- I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK,
- BPFCLK_C_MARK,
+ TS_SDATA_D_MARK /* R8A7794 only */, TPUTO1_B_MARK,
+ I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK,
+ TS_SCK_D_MARK /* R8A7794 only */, BPFCLK_C_MARK /* R8A7794 only */,
MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
- TS_SDEN_D_MARK, FMCLK_C_MARK,
+ TS_SDEN_D_MARK /* R8A7794 only */, FMCLK_C_MARK /* R8A7794 only */,
/* IPSR9 */
MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
- TS_SPSYNC_D_MARK, FMIN_C_MARK,
- MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
- MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
- MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
- FMCLK_B_MARK,
- MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
- FMIN_B_MARK,
+ TS_SPSYNC_D_MARK /* R8A7794 only */, FMIN_C_MARK /* R8A7794 only */,
+ MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK /* R8A7794 only */,
+ DU1_DR4_MARK, TPUTO1_C_MARK,
+ MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK /* R8A7794 only */,
+ DU1_DR5_MARK, BPFCLK_B_MARK /* R8A7794 only */,
+ MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK /* R8A7794 only */,
+ DU1_DR6_MARK, FMCLK_B_MARK /* R8A7794 only */,
+ MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK /* R8A7794 only */,
+ DU1_DR7_MARK, FMIN_B_MARK /* R8A7794 only */,
HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
- HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
- SPEEDIN_B_MARK,
- HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
- SSI_SCK1_B_MARK,
- HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
- SSI_WS1_B_MARK,
+ HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK /* R8A7794 only */,
+ DU1_DG2_MARK, REMOCON_B_MARK /* R8A7794 only */,
+ SPEEDIN_B_MARK /* R8A7794 only */,
+ HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK /* R8A7794 only */,
+ DU1_DG3_MARK, SSI_SCK1_B_MARK,
+ HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK /* R8A7794 only */,
+ DU1_DG4_MARK, SSI_WS1_B_MARK,
SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
- CAN_TXCLK_MARK,
+ CAN_TXCLK_MARK /* R8A7794 only */,
/* IPSR10 */
SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
@@ -600,12 +640,12 @@ enum {
SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
- SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
- SSI_SDATA9_B_MARK,
- SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
- AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
- SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
- AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
+ SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK /* R8A7794 only */,
+ DU1_DB3_MARK, SSI_SDATA9_B_MARK,
+ SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK /* R8A7794 only */,
+ DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
+ SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK /* R8A7794 only */,
+ DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
SSI_SDATA4_B_MARK,
I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
@@ -623,22 +663,28 @@ enum {
SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
CAN_CLK_D_MARK,
- SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
- SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
- SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
+ SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK,
+ ADIDATA_B_MARK /* R8A7794 only */,
+ SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
+ ADICS_SAMP_B_MARK /* R8A7794 only */,
+ SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK,
+ ADICLK_B_MARK /* R8A7794 only */,
/* IPSR12 */
- SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
- DREQ1_N_B_MARK,
- SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
- CAN1_RX_C_MARK, DACK1_B_MARK,
- SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
- CAN1_TX_C_MARK, DREQ2_N_MARK,
- SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
- SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
- SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
- SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
- DACK2_MARK, ETH_MDIO_B_MARK,
+ SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK,
+ ADICHS0_B_MARK /* R8A7794 only */, DREQ1_N_B_MARK,
+ SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK,
+ ADICHS1_B_MARK /* R8A7794 only */, CAN1_RX_C_MARK, DACK1_B_MARK,
+ SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK,
+ ADICHS2_B_MARK /* R8A7794 only */, CAN1_TX_C_MARK, DREQ2_N_MARK,
+ SSI_SCK4_MARK, MLB_CLK_MARK /* R8A7794 only */,
+ IETX_B_MARK /* R8A7794 only */,
+ SSI_WS4_MARK, MLB_SIG_MARK /* R8A7794 only */,
+ IECLK_B_MARK /* R8A7794 only */,
+ SSI_SDATA4_MARK, MLB_DAT_MARK /* R8A7794 only */,
+ IERX_B_MARK /* R8A7794 only */,
+ SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK,
+ REMOCON_MARK /* R8A7794 only */, DACK2_MARK, ETH_MDIO_B_MARK,
SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
@@ -660,13 +706,14 @@ enum {
SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
- TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
+ TS_SDATA_C_MARK /* R8A7794 only */, ETH_TXD0_B_MARK,
AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
- TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
+ TS_SCK_C_MARK /* R8A7794 only */, BPFCLK_E_MARK /* R8A7794 only */,
+ ETH_MDC_B_MARK,
AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
- TS_SDEN_C_MARK, FMCLK_E_MARK,
+ TS_SDEN_C_MARK /* R8A7794 only */, FMCLK_E_MARK /* R8A7794 only */,
AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
- TS_SPSYNC_C_MARK, FMIN_E_MARK,
+ TS_SPSYNC_C_MARK /* R8A7794 only */, FMIN_E_MARK /* R8A7794 only */,
PINMUX_MARK_END,
};
@@ -831,7 +878,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2_20_18, A16),
PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
- PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
+ PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
PINMUX_IPSR_GPSR(IP2_23_21, A17),
@@ -877,26 +924,26 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
- PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
- PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
- PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
+ PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
- PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
- PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
+ PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
- PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
- PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
+ PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), /* R8A7794 */
+ PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
@@ -913,87 +960,87 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
- PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
+ PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
- PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
+ PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
- PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
+ PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
- PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
+ PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
- PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
+ PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
- PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
+ PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
- PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
+ PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
- PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
+ PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
- PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
+ PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
- PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
+ PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
- PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
+ PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
- PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
+ PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
- PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
+ PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12), /* R8A7794 only */
/* IPSR5 */
PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
- PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
+ PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
- PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
+ PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
- PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
+ PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
- PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
+ PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
- PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
+ PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
- PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
+ PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
- PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
+ PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
- PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
+ PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
- PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
+ PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
- PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
+ PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
- PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
+ PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
- PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
+ PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
- PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
+ PINMUX_IPSR_GPSR(IP5_27_26, QCLK), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
- PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
+ PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
- PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
+ PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS), /* R8A7794 only */
/* IPSR6 */
PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
- PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
+ PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
- PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
+ PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
- PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
+ PINMUX_IPSR_GPSR(IP6_5_4, QPOLA), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
- PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
+ PINMUX_IPSR_GPSR(IP6_7_6, QPOLB), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
@@ -1015,17 +1062,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
- PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
+ PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
- PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
+ PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
- PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
+ PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
@@ -1037,7 +1084,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
- PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0), /* R8A7794 only */
/* IPSR7 */
PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
@@ -1045,7 +1092,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
- PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
@@ -1057,19 +1104,19 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
- PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
- PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
- PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
@@ -1153,48 +1200,48 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
- PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
- PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
- PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
+ PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
- PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
- PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
+ PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2), /* R8A7794 only */
/* IPSR9 */
PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
- PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
- PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
+ PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
- PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
- PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
- PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
+ PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
- PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
- PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
+ PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
- PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
- PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
+ PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
@@ -1205,18 +1252,18 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
- PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
- PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
- PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
+ PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
- PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
- PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
@@ -1248,18 +1295,18 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
- PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
+ PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
- PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
+ PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
- PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
+ PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
@@ -1312,48 +1359,48 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
- PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
- PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), /* R8A7794 */
PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
- PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1), /* R8A7794 only */
/* IPSR12 */
PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
- PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
- PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
- PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
- PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
- PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
+ PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
- PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
- PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
+ PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
- PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
- PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
+ PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
- PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
+ PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0), /* R8A7794 only */
PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
@@ -1414,27 +1461,27 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
- PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), /* R8A7794 */
PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
- PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
- PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
+ PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
- PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
- PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
+ PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), /* R8A7794 only */
+ PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4), /* R8A7794 only */
PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
- PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
- PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
+ PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), /* R8A7794 */
+ PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), /* R8A7794 only */
};
static const struct sh_pfc_pin pinmux_pins[] = {
@@ -4931,7 +4978,7 @@ static const struct pinmux_cfg_reg pinmu
0, 0,
/* SEL_CAN [2] */
FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
- /* SEL_DARC [3] */
+ /* SEL_DARC [3] (R8A7794 only) */
FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
FN_SEL_DARC_4, 0, 0, 0,
/* RESERVED [4] */
@@ -4963,7 +5010,7 @@ static const struct pinmux_cfg_reg pinmu
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
2, 2, 2, 1, 1, 2) {
- /* SEL_IEB [2] */
+ /* SEL_IEB [2] (R8A7794 only) */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
/* SEL_IIC0 [2] */
FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
@@ -4975,9 +5022,9 @@ static const struct pinmux_cfg_reg pinmu
FN_SEL_MSI2_0, FN_SEL_MSI2_1,
/* SEL_RAD [1] */
FN_SEL_RAD_0, FN_SEL_RAD_1,
- /* SEL_RCN [1] */
+ /* SEL_RCN [1] (R8A7794 only) */
FN_SEL_RCN_0, FN_SEL_RCN_1,
- /* SEL_RSP [1] */
+ /* SEL_RSP [1] (R8A7794 only) */
FN_SEL_RSP_0, FN_SEL_RSP_1,
/* SEL_SCIFA0 [2] */
FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
@@ -4998,7 +5045,7 @@ static const struct pinmux_cfg_reg pinmu
0, 0,
/* SEL_TMU [1] */
FN_SEL_TMU_0, FN_SEL_TMU_1,
- /* SEL_TSIF0 [2] */
+ /* SEL_TSIF0 [2] (R8A7794 only) */
FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
/* SEL_CAN0 [2] */
FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
@@ -5094,6 +5141,28 @@ static const struct sh_pfc_soc_operation
.pin_to_pocctrl = r8a7794_pin_to_pocctrl,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A7745
+const struct sh_pfc_soc_info r8a7745_pinmux_info = {
+ .name = "r8a77450_pfc",
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
+
+#ifdef CONFIG_PINCTRL_PFC_R8A7794
const struct sh_pfc_soc_info r8a7794_pinmux_info = {
.name = "r8a77940_pfc",
.ops = &r8a7794_pinmux_ops,
@@ -5113,3 +5182,4 @@ const struct sh_pfc_soc_info r8a7794_pin
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
+#endif
Index: linux-pinctrl/drivers/pinctrl/sh-pfc/sh_pfc.h
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -260,6 +260,7 @@ extern const struct sh_pfc_soc_info emev
extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
^ permalink raw reply
* Re: [PATCH 4/5] arm64: dts: Add ipq8074 SoC and MTP board support
From: Stephen Boyd @ 2017-04-28 18:53 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
mturquette-rdvid1DuHRBWk0Htik3J/w,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
andy.gross-QSEj5FYQhm4dnm+yROfE0A,
david.brown-QSEj5FYQhm4dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
sricharan-sgV2jX0FEOL9JmXXK+q4OQ, absahu-sgV2jX0FEOL9JmXXK+q4OQ,
sjaganat-sgV2jX0FEOL9JmXXK+q4OQ, Manoharan Vijaya Raghavan
In-Reply-To: <1493373403-23462-5-git-send-email-varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On 04/28, Varadarajan Narayanan wrote:
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
> new file mode 100644
> index 0000000..c150bea
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
> @@ -0,0 +1,48 @@
> +/dts-v1/;
> +/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +#include "ipq8074.dtsi"
> +
> +/ {
> + #address-cells = <0x2>;
> + #size-cells = <0x2>;
> + model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
> + compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
> + interrupt-parent = <&intc>;
> +
> + chosen {
> + bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw init=/init";
Add an aliases node for serial0 and use a chosen node with stdout-path = "serial0" instead please.
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0x0 0x20000000>;
> + };
> +
> + soc: soc {
Do you need the soc label here? Please remove.
> + pinctrl@1000000 {
> + serial_4_pins: serial4_pinmux {
> + mux {
> + pins = "gpio23", "gpio24";
> + function = "blsp4_uart1";
> + bias-disable;
> + };
> + };
> + };
> +
> + serial@78b3000 {
> + pinctrl-0 = <&serial_4_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> new file mode 100644
> index 0000000..f910cc0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -0,0 +1,153 @@
> +/*
> + * Copyright (c) 2017, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ8074";
> + compatible = "qcom,ipq8074";
> +
> + soc: soc {
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> + ranges = <0 0 0 0xffffffff>;
> + compatible = "simple-bus";
> +
> + pinctrl@1000000 {
> + compatible = "qcom,ipq8074-pinctrl";
> + reg = <0x1000000 0x300000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <0x2>;
> + interrupt-controller;
> + #interrupt-cells = <0x2>;
> + };
> +
> + intc: interrupt-controller@b000000 {
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <0x3>;
> + reg = <0xb000000 0x1000>,
> + <0xb002000 0x1000>;
Please align this up with previous reg property.
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + };
Is there an mmio timer as well? We should add it too.
> +
> + gcc: gcc@1800000 {
> + compatible = "qcom,gcc-ipq8074";
> + reg = <0x1800000 0x80000>;
Wow that is a huge area! Is it really that large?
> + #clock-cells = <0x1>;
> + #reset-cells = <0x1>;
> + };
> +
> + serial@78b3000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x78b3000 0x200>;
> + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> + };
> +
> + cpus {
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> +
> + cpu-map {
> +
> + cluster0 {
> +
> + core0 {
> + cpu = <&CPU0>;
> + };
> +
> + core1 {
> + cpu = <&CPU1>;
> + };
> +
> + core2 {
> + cpu = <&CPU2>;
> + };
> +
> + core3 {
> + cpu = <&CPU3>;
> + };
> + };
> + };
Is this needed? Looks ok, but just curious if we need to do it
for other arm64 platforms we support.
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0>;
> + next-level-cache = <&L2_0>;
> + enable-method = "psci";
> + };
> +
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x1>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x2>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x3>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <0x2>;
> + };
This should be inside some CPU? CPU0?
> + };
We should be able to add the performance monitor node too?
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + clocks {
> + sleep_clk: sleep_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
Not 32765 or 32768?
> + #clock-cells = <0>;
> + };
> +
> + xo: xo {
> + compatible = "fixed-clock";
> + clock-frequency = <19200000>;
> + #clock-cells = <0>;
> + };
> + };
--
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a Linux Foundation Collaborative Project
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* Re: [PATCH 4/5] arm64: dts: Add ipq8074 SoC and MTP board support
From: Jonathan Neuschäfer @ 2017-04-28 18:58 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: mark.rutland, devicetree, Manoharan Vijaya Raghavan, linux-gpio,
catalin.marinas, mturquette, sjaganat, sboyd, linux-kernel,
will.deacon, linux-clk, david.brown, absahu, robh+dt,
linux-arm-msm, andy.gross, sricharan, linux-soc, linus.walleij,
linux-arm-kernel
In-Reply-To: <1493373403-23462-5-git-send-email-varada@codeaurora.org>
[-- Attachment #1.1: Type: text/plain, Size: 1451 bytes --]
Hi,
On Fri, Apr 28, 2017 at 03:26:42PM +0530, Varadarajan Narayanan wrote:
> Subject: [PATCH 4/5] arm64: dts: Add ipq8074 SoC and MTP board support
s/MTP/HK01/ ?
> Add initial device tree support for the Qualcomm IPQ8074 SoC and
> HK01 evaluation board.
>
> Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 48 ++++++++++
> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 153 ++++++++++++++++++++++++++++++
> 3 files changed, 202 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
> create mode 100644 arch/arm64/boot/dts/qcom/ipq8074.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index cc0f02d..7c6963e 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
Maybe this list should be alphabetically sorted ('i' before 'm').
(I have no strong preference)
Thanks,
Jonathan Neuschäfer
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^ permalink raw reply
* [PATCH v2 1/2] dt-bindings: clk: r7s72100: add USB bit definitions
From: Chris Brandt @ 2017-04-28 19:01 UTC (permalink / raw)
To: Simon Horman, Geert Uytterhoeven, Rob Herring, Mark Rutland
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Chris Brandt
Add the bit locations that correspond to the USB clocks.
Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
include/dt-bindings/clock/r7s72100-clock.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h
index bc256d31099a..dcd2072151fc 100644
--- a/include/dt-bindings/clock/r7s72100-clock.h
+++ b/include/dt-bindings/clock/r7s72100-clock.h
@@ -34,6 +34,8 @@
/* MSTP7 */
#define R7S72100_CLK_ETHER 4
+#define R7S72100_CLK_USB0 1
+#define R7S72100_CLK_USB1 0
/* MSTP8 */
#define R7S72100_CLK_MMCIF 4
--
2.11.0
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* [PATCH v2 2/2] ARM: dts: r7s72100: add usb clocks to device tree
From: Chris Brandt @ 2017-04-28 19:01 UTC (permalink / raw)
To: Simon Horman, Geert Uytterhoeven, Rob Herring, Mark Rutland
Cc: devicetree, linux-renesas-soc, Chris Brandt
In-Reply-To: <20170428190134.63895-1-chris.brandt@renesas.com>
This adds the USB0 and USB1 clocks to the device tree.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
* moved bit defines to a separate patch
* added Reviewed-by
---
arch/arm/boot/dts/r7s72100.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index fb54cb5d3fad..4ed12a4d9d51 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -144,9 +144,9 @@
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0430 4>;
- clocks = <&b_clk>;
- clock-indices = <R7S72100_CLK_ETHER>;
- clock-output-names = "ether";
+ clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
+ clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
+ clock-output-names = "ether", "usb0", "usb1";
};
mstp8_clks: mstp8_clks@fcfe0434 {
--
2.11.0
^ permalink raw reply related
* Re: [PATCH 1/2] Add DT bindings documentation for the max7360 mfd driver
From: Rob Herring @ 2017-04-28 19:23 UTC (permalink / raw)
To: Valentin Sitdikov
Cc: lee.jones-QSEj5FYQhm4dnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andrei Dranitca
In-Reply-To: <20170425081557.13941-2-valentin_sitdikov-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
On Tue, Apr 25, 2017 at 11:15:56AM +0300, Valentin Sitdikov wrote:
dt-bindings: mfd: ... for subject.
And you need a commit msg.
> Signed-off-by: Valentin Sitdikov <valentin_sitdikov-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
> Signed-off-by: Andrei Dranitca <Andrei_Dranitca-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
> ---
> Documentation/devicetree/bindings/mfd/max7360.txt | 72 +++++++++++++++++++++++
> 1 file changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/max7360.txt
>
> diff --git a/Documentation/devicetree/bindings/mfd/max7360.txt b/Documentation/devicetree/bindings/mfd/max7360.txt
> new file mode 100644
> index 0000000..359073a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/max7360.txt
> @@ -0,0 +1,72 @@
> +* Maxim MAX7360 multi-function device
> +
> +The Maxim MAX7360 is a multifunction device which includes
> +64 key switches, eight LED drivers/GPIOs, PWM intensity control,
> +and rotary switch control.
> +
> +Required properties:
> +- compatible: Should be the following: "maxim,max7360"
> +- reg: Specifies the i2c slave address of the max7360 block. It can be 0x38, 0x3a, 0x3c or 0x3e IIUC.
> +
> +Optional properties:
> +- interrupt-parent: Specifies the phandle of the interrupt controller to which
> + the interrupts from MAX7360 are routed to.
> +- interrupt-names: might be "int-shared" or list of "inti" and "intk"
I don't see anything in the datasheet about shared irq. If you connect
both lines together on a board, just repeat the same connection.
> +- interrupt-controller: Identifies the device as an interrupt controller.
> +- #interrupt-cells : Number of cells to encode an interrupt source, shall be 1.
> +
> +Examples:
> +
> +Without subnodes:
> + max7360@38 {
> + compatible = "maxim,max7360";
> + reg = <0x38>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-names = "int-shared";
> + interrupt-controller;
> + #interrupt-cells = <0x1>;
> +
> + };
> +
> +With subnodes:
> + max7360@38 {
> + compatible = "maxim,max7360";
> + reg = <0x38>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-names = "int-shared";
> + interrupt-controller;
> + #interrupt-cells = <0x1>;
> +
> + max7360_gpio: max7360_gpio@0 {
Use generic names and no unit address when no reg prop:
gpio {
> + compatible = "maxim,max7360-gpio";
> + gpio-controller;
> + #gpio-cells = <0x2>;
> + interrupt-controller;
> + #interrupt-cells = <0x2>;
> + interrupts = <0>;
> + };
> +
> + max7360_keypad {
keypad {
> + compatible = "maxim,max7360-keypad";
> + maxim,debounce_reg = /bits/ 8 <0xef>;
> + maxim,ports_reg = /bits/ 8 <0xae>;
> + linux,keymap = < MATRIX_KEY(0, 0, KEY_F5)
> + MATRIX_KEY(1, 0, KEY_F4) >;
> + keypad,num-rows = <2>;
> + keypad,num-columns = <1>;
> + interrupts = <1>;
> + };
> +
> + max7360_pwm: max7360_pwm {
pwm {
> + compatible = "maxim,max7360-pwm";
> + #pwm-cells = <0x2>;
> + };
> +
> + max7360_rotary_encoder {
rotary-encoder {
> + compatible = "maxim,max7360-rotary";
> + interrupts = <2>;
> + };
> +
> + };
> --
> 2.9.3
>
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* Re: [PATCH v4 1/5] dt-bindings: gpu: add bindings for the ARM Mali Midgard GPU
From: Rob Herring @ 2017-04-28 19:27 UTC (permalink / raw)
To: Guillaume Tucker
Cc: Mark Rutland, Heiko Stübner, Neil Armstrong, Sjoerd Simons,
Enric Balletbo i Serra, John Reitan, Wookey,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <9349c8ae9091fbd93e9410f4cfae770ac850bf6b.1493125299.git.guillaume.tucker-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
On Tue, Apr 25, 2017 at 02:16:16PM +0100, Guillaume Tucker wrote:
> The ARM Mali Midgard GPU family is present in a number of SoCs
> from many different vendors such as Samsung Exynos and Rockchip.
>
> Import the device tree bindings documentation from the r16p0
> release of the Mali Midgard GPU kernel driver:
>
> https://developer.arm.com/-/media/Files/downloads/mali-drivers/kernel/mali-midgard-gpu/TX011-SW-99002-r16p0-00rel0.tgz
>
> Remove the copyright and GPL licence header as deemed not necessary.
>
> Redesign the "compatible" property strings to list all the Mali
> Midgard GPU types and include optional vendor ones.
>
> Drop the "clock-names" property as only one clock is used by the Mali
> Midgard driver (which now needs to call clk_get with NULL).
>
> Convert the "interrupt-names" property values to lower-case: "job",
> "mmu" and "gpu".
>
> Replace the deprecated "operating-points" optional property with
> "operating-points-v2".
>
> Omit the following optional properties in this initial version as they
> are only used in very specific cases:
>
> * snoop_enable_smc
> * snoop_disable_smc
> * jm_config
> * power_model
> * system-coherency
> * ipa-model
>
> Update the example accordingly to reflect all these changes.
>
> CC: John Reitan <john.reitan-5wv7dgnIgG8@public.gmane.org>
> Tested-by: Enric Balletbo i Serra <enric.balletbo-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> Signed-off-by: Guillaume Tucker <guillaume.tucker-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> ---
> .../devicetree/bindings/gpu/arm,mali-midgard.txt | 82 ++++++++++++++++++++++
> 1 file changed, 82 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
>
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
> new file mode 100644
> index 000000000000..547ddeceb498
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
> @@ -0,0 +1,82 @@
> +ARM Mali Midgard GPU
> +====================
> +
> +Required properties:
> +
> +- compatible :
> + * Must be one of the following:
> + + "arm,mali-t60x"
> + + "arm,mali-t62x"
Don't use wildcards.
> + + "arm,mali-t720"
> + + "arm,mali-t760"
> + + "arm,mali-t820"
> + + "arm,mali-t830"
> + + "arm,mali-t860"
> + + "arm,mali-t880"
> + * And, optionally, one of the vendor specific compatible:
IMO, these should not be optional.
> + + "amlogic,meson-gxm-mali"
> + + "rockchip,rk3288-mali"
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* Re: [PATCH v7 5/9][resend] ASoC: soc-core: enable "dai-format" on snd_soc_of_parse_daifmt()
From: Rob Herring @ 2017-04-28 19:27 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Mark Brown, Linux-ALSA, Simon, Linux-DT
In-Reply-To: <87r30er4qt.wl%kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
On Wed, Apr 26, 2017 at 9:02 PM, Kuninori Morimoto
<kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
>
> Current snd_soc_of_parse_daifmt() detects [prefix]format, but
> "format" was unclear in some case. This patch checks "dai-format"
> first, and try to check "[prefix]format" if "dai-format" was not
> exist.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> ---
> v6 -> v7
>
> - no change
>
> sound/soc/soc-core.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH v7 6/9][resend] ASoC: simple-card-utils: enable "label" on asoc_simple_card_parse_card_name
From: Rob Herring @ 2017-04-28 19:29 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Mark Brown, Linux-ALSA, Simon, Linux-DT
In-Reply-To: <87pofyr4qc.wl%kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
On Wed, Apr 26, 2017 at 9:02 PM, Kuninori Morimoto
<kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
>
> Current asoc_simple_card_parse_card_name() detects [prefix]name,
> but in generally, we uses "label" for user visible names.
> This patch enables it.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> ---
> v6 -> v7
>
> - don't allow "[prefix]label"
>
> sound/soc/generic/simple-card-utils.c | 16 +++++++++++-----
> 1 file changed, 11 insertions(+), 5 deletions(-)
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH v7 2/9] of_graph: add of_graph_get_remote_endpoint()
From: Rob Herring @ 2017-04-28 19:33 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Mark Brown, Linux-ALSA, Simon, Linux-DT
In-Reply-To: <87d1c7ool6.wl%kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
On Wed, Apr 19, 2017 at 8:31 PM, Kuninori Morimoto
<kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org> wrote:
>
> From: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
>
> It should use same method to get same result.
> To getting remote-endpoint node,
> let's use of_graph_get_remote_endpoint()
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> ---
> v6 -> v7
>
> - no change
>
> drivers/of/base.c | 18 ++++++++++++++++--
> include/linux/of_graph.h | 8 ++++++++
> 2 files changed, 24 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH v7 3/9] of_graph: add of_graph_get_port_parent()
From: Rob Herring @ 2017-04-28 19:34 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Mark Brown, Linux-ALSA, Simon, Linux-DT
In-Reply-To: <87bmrrooka.wl%kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
On Wed, Apr 19, 2017 at 8:32 PM, Kuninori Morimoto
<kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org> wrote:
>
> From: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
>
> Linux kernel already has of_graph_get_remote_port_parent(),
> but, sometimes we want to get own port parent.
> This patch adds of_graph_get_port_parent()
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> ---
> v6 -> v7
>
> - no change
>
> drivers/of/base.c | 30 ++++++++++++++++++++++--------
> include/linux/of_graph.h | 7 +++++++
> 2 files changed, 29 insertions(+), 8 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH v7 5/9] ASoC: soc-core: enable "dai-format" on snd_soc_of_parse_daifmt()
From: Rob Herring @ 2017-04-28 19:34 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Mark Brown, Linux-ALSA, Simon, Linux-DT
In-Reply-To: <878tmvooif.wl%kuninori.morimoto.gx@renesas.com>
On Wed, Apr 19, 2017 at 8:33 PM, Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> Current snd_soc_of_parse_daifmt() detects [prefix]format, but
> "format" was unclear in some case. This patch checks "dai-format"
> first, and try to check "[prefix]format" if "dai-format" was not
> exist.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> ---
> v6 -> v7
>
> - no change
>
> sound/soc/soc-core.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
> index 8be2ce1..e84a820 100644
> --- a/sound/soc/soc-core.c
> +++ b/sound/soc/soc-core.c
> @@ -3955,11 +3955,15 @@ unsigned int snd_soc_of_parse_daifmt(struct device_node *np,
> prefix = "";
>
> /*
> - * check "[prefix]format = xxx"
> + * check "dai-format = xxx"
> + * or "[prefix]format = xxx"
> * SND_SOC_DAIFMT_FORMAT_MASK area
> */
> - snprintf(prop, sizeof(prop), "%sformat", prefix);
> - ret = of_property_read_string(np, prop, &str);
> + ret = of_property_read_string(np, "dai-format", &str);
> + if (ret < 0) {
> + snprintf(prop, sizeof(prop), "%sformat", prefix);
> + ret = of_property_read_string(np, prop, &str);
> + }
> if (ret == 0) {
> for (i = 0; i < ARRAY_SIZE(of_fmt_table); i++) {
> if (strcmp(str, of_fmt_table[i].name) == 0) {
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v7 4/9] of_graph: add of_graph_get_endpoint_count()
From: Rob Herring @ 2017-04-28 19:35 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Mark Brown, Linux-ALSA, Simon, Linux-DT
In-Reply-To: <87a87boojg.wl%kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
On Wed, Apr 19, 2017 at 8:32 PM, Kuninori Morimoto
<kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org> wrote:
>
> From: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
>
> OF graph want to count its endpoint number, same as
> of_get_child_count(). This patch adds of_graph_get_endpoint_count()
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> ---
> v6 -> v7
>
> - no change
>
> drivers/of/base.c | 12 ++++++++++++
> include/linux/of_graph.h | 6 ++++++
> 2 files changed, 18 insertions(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH 01/10] clk: renesas: cpg-mssr: Document R-Car Gen2 support
From: Rob Herring @ 2017-04-28 19:42 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1493139200-27396-2-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
On Tue, Apr 25, 2017 at 06:53:11PM +0200, Geert Uytterhoeven wrote:
> Document use of the Renesas Clock Pulse Generator / Module Standby and
> Software Reset DT Bindings for various member of the R-Car Gen2 family
> (H2, M2-W, V2H, M2-N, and E2).
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
> Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [RESEND][PATCH V2 1/4] mfd: Add ROHM BD9571MWV-M PMIC DT bindings
From: Rob Herring @ 2017-04-28 19:43 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-renesas-soc, lee.jones, Marek Vasut, devicetree,
Geert Uytterhoeven
In-Reply-To: <20170425183210.30594-1-marek.vasut+renesas@gmail.com>
On Tue, Apr 25, 2017 at 08:32:07PM +0200, Marek Vasut wrote:
> Add DT bindings for the ROHM BD9571MWV-M PMIC. This PMIC has
> the following features:
> - multiple voltage monitors for 1V8, 2V5, 3V3 voltage rail
> - one voltage regulator for DVFS
> - two GPIOs
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: devicetree@vger.kernel.org
> Cc: Rob Herring <robh@kernel.org>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: linux-renesas-soc@vger.kernel.org
> ---
> V2: - Drop the compatible = "regulator-fixed" from the binding example,
> it should not be there.
> - List the VD09 regulator
> ---
> .../devicetree/bindings/mfd/bd9571mwv.txt | 49 ++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/bd9571mwv.txt
>
> diff --git a/Documentation/devicetree/bindings/mfd/bd9571mwv.txt b/Documentation/devicetree/bindings/mfd/bd9571mwv.txt
> new file mode 100644
> index 000000000000..ce24231edd7d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/bd9571mwv.txt
> @@ -0,0 +1,49 @@
> +* ROHM BD9571MWV Power Management Integrated Circuit (PMIC) bindings
> +
> +Required properties:
> + - compatible : Should be "rohm,bd9571mwv".
> + - reg : I2C slave address.
> + - interrupt-parent : Phandle to the parent interrupt controller.
> + - interrupts : The interrupt line the device is connected to.
> + - interrupt-controller : Marks the device node as an interrupt controller.
> + - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
> + The first cell is the IRQ number.
> + The second cell is the flags, encoded as trigger
> + masks from ../interrupt-controller/interrupts.txt.
> + - gpio-controller : Marks the device node as a GPIO Controller.
> + - #gpio-cells : Should be two. The first cell is the pin number and
> + the second cell is used to specify flags.
> + See ../gpio/gpio.txt for more information.
> + - regulators: : List of child nodes that specify the regulator
> + initialization data. Child nodes must be named
> + after their hardware counterparts:
> + - vd09
> + - vd18
> + - vd25
> + - vd33
> + - dvfs
> + Each child node is defined using the standard
> + binding for regulators.
> +
> +Example:
> +
> + pmic: bd9571mwv@30 {
pmic@30 ...
Otherwise,
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v4 00/14] Ingenic JZ4740 / JZ4780 pinctrl driver
From: Paul Cercueil @ 2017-04-28 20:08 UTC (permalink / raw)
To: Linus Walleij, Alexandre Courbot, Rob Herring, Mark Rutland,
Ralf Baechle
Cc: Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, james.hogan,
linux-gpio, devicetree, linux-kernel, linux-mips, linux-mmc,
linux-mtd, linux-pwm, linux-fbdev
In-Reply-To: <20170402204244.14216-2-paul@crapouillou.net>
Hi,
This is the v5 of my Ingenic pinctrl / GPIO patch set.
The pinctrl driver now probes its children devices without using the MFD
subsystem; the GPIO driver now uses the 'reg' property to know the bank
number.
Best regards,
- Paul
^ permalink raw reply
* [PATCH v5 01/14] dt/bindings: Document pinctrl-ingenic
From: Paul Cercueil @ 2017-04-28 20:08 UTC (permalink / raw)
To: Linus Walleij, Alexandre Courbot, Rob Herring, Mark Rutland,
Ralf Baechle
Cc: Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton,
james.hogan-1AXoQHu6uovQT0dZR+AlfA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA, Paul Cercueil
In-Reply-To: <20170428200824.10906-1-paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
This commit adds documentation for the devicetree bindings of the
pinctrl-ingenic driver, which handles pin configuration and pin
muxing of the Ingenic SoCs currently supported by the Linux kernel.
Signed-off-by: Paul Cercueil <paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
.../bindings/pinctrl/ingenic,pinctrl.txt | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
v2: Rewrote the documentation for the new pinctrl-ingenic driver
v3: No changes
v4: Update for the v4 version of the pinctrl-ingenic driver
v5: Rename 'ingenic-pinctrl@...' to 'pin-controller@...' in example
diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
new file mode 100644
index 000000000000..ca313a7aeaff
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
@@ -0,0 +1,41 @@
+Ingenic jz47xx pin controller
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may
+be used as GPIOs, multiplexed device functions are configured within the
+GPIO port configuration registers and it is typical to refer to pins using the
+naming scheme "PxN" where x is a character identifying the GPIO port with
+which the pin is associated and N is an integer from 0 to 31 identifying the
+pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
+PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to
+PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a
+total of 192 pins.
+
+
+Required properties:
+--------------------
+
+ - compatible: One of:
+ - "ingenic,jz4740-pinctrl"
+ - "ingenic,jz4770-pinctrl"
+ - "ingenic,jz4780-pinctrl"
+ - reg: Address range of the pinctrl registers.
+
+
+GPIO sub-nodes
+--------------
+
+The pinctrl node can have optional sub-nodes for the Ingenic GPIO driver;
+please refer to ../gpio/ingenic,gpio.txt.
+
+
+Example:
+--------
+
+pinctrl: pin-controller@10010000 {
+ compatible = "ingenic,jz4740-pinctrl";
+ reg = <0x10010000 0x400>;
+};
--
2.11.0
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* [PATCH v5 02/14] dt/bindings: Document gpio-ingenic
From: Paul Cercueil @ 2017-04-28 20:08 UTC (permalink / raw)
To: Linus Walleij, Alexandre Courbot, Rob Herring, Mark Rutland,
Ralf Baechle
Cc: Boris Brezillon, Thierry Reding, Bartlomiej Zolnierkiewicz,
Maarten ter Huurne, Lars-Peter Clausen, Paul Burton, james.hogan,
linux-gpio, devicetree, linux-kernel, linux-mips, linux-mmc,
linux-mtd, linux-pwm, linux-fbdev, Paul Cercueil
In-Reply-To: <20170428200824.10906-1-paul@crapouillou.net>
This commit adds documentation for the devicetree bindings of the
gpio-ingenic driver, which handles GPIOs of the Ingenic SoCs
currently supported by the Linux kernel.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
.../devicetree/bindings/gpio/ingenic,gpio.txt | 46 ++++++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/ingenic,gpio.txt
v2: New patch
v3: No changes
v4: Update for the v4 version of the gpio-ingenic driver
v5: Remove gpio-bank-... compatible strings, and add 'reg' property
diff --git a/Documentation/devicetree/bindings/gpio/ingenic,gpio.txt b/Documentation/devicetree/bindings/gpio/ingenic,gpio.txt
new file mode 100644
index 000000000000..7988aeb725f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/ingenic,gpio.txt
@@ -0,0 +1,46 @@
+Ingenic jz47xx GPIO controller
+
+That the Ingenic GPIO driver node must be a sub-node of the Ingenic pinctrl
+driver node.
+
+Required properties:
+--------------------
+
+ - compatible: Must contain one of:
+ - "ingenic,jz4740-gpio"
+ - "ingenic,jz4770-gpio"
+ - "ingenic,jz4780-gpio"
+ - reg: The GPIO bank number.
+ - interrupt-controller: Marks the device node as an interrupt controller.
+ - interrupts: Interrupt specifier for the controllers interrupt.
+ - #interrupt-cells: Should be 2. Refer to
+ ../interrupt-controller/interrupts.txt for more details.
+ - gpio-controller: Marks the device node as a GPIO controller.
+ - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
+ cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
+ GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
+ - gpio-ranges: Range of pins managed by the GPIO controller. Refer to
+ 'gpio.txt' in this directory for more details.
+
+Example:
+--------
+
+&pinctrl {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpa: gpio@0 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <0>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <28>;
+ };
+};
--
2.11.0
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