* [PATCH v3 0/3] thermal: broadcom: Add NSP Thermal Support
From: Jon Mason @ 2017-04-28 20:11 UTC (permalink / raw)
To: Florian Fainelli, Zhang Rui, Eduardo Valentin, Rob Herring,
Mark Rutland
Cc: bcm-kernel-feedback-list, linux-arm-kernel, linux-kernel,
linux-pm, devicetree
Changes in v3:
* Enable THERMAL on NSP, not all iProc Chips (per Scott Branden)
* Correct the Kconfig syntax in patch 2 (per Eduardo Valentin)
Changes in v2:
* Split SoC enablement into a separate patch (per Eduardo Valentin)
* Added Eduardo Valentin's Acked-by to the DTS patch
This adds support for NSP to the existing Northstar thermal driver.
This code is based on patches currently in the Linux SoC Thermal git
tree. Specfically,
https://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git/commit/?h=linus&id=a94cb7eeecc4104a6874339f90c5d0647359c102
Jon Mason (3):
ARM: BCM: Enable thermal support for NSP SoCs
thermal: broadcom: ns-thermal: default on iProc SoCs
ARM: dts: NSP: Add Thermal Support
arch/arm/boot/dts/bcm-nsp.dtsi | 26 ++++++++++++++++++++++++++
arch/arm/mach-bcm/Kconfig | 2 ++
drivers/thermal/broadcom/Kconfig | 9 +++++----
3 files changed, 33 insertions(+), 4 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH v3 1/3] ARM: BCM: Enable thermal support for NSP SoCs
From: Jon Mason @ 2017-04-28 20:11 UTC (permalink / raw)
To: Florian Fainelli, Zhang Rui, Eduardo Valentin, Rob Herring,
Mark Rutland
Cc: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1493410291-16679-1-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Change the Northstar Plus Kconfig to select THERMAL and THERMAL_OF,
which allows the ns-thermal driver to be selected via menuconfig.
Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
arch/arm/mach-bcm/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index a0e66d8..93a61d0 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -44,6 +44,8 @@ config ARCH_BCM_NSP
select ARM_ERRATA_775420
select ARM_ERRATA_764369 if SMP
select HAVE_SMP
+ select THERMAL
+ select THERMAL_OF
help
Support for Broadcom Northstar Plus SoC.
Broadcom Northstar Plus family of SoCs are used for switching control
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 2/3] thermal: broadcom: ns-thermal: default on iProc SoCs
From: Jon Mason @ 2017-04-28 20:11 UTC (permalink / raw)
To: Florian Fainelli, Zhang Rui, Eduardo Valentin, Rob Herring,
Mark Rutland
Cc: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1493410291-16679-1-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Tweak the Kconfig description to mention support for NSP and make the
default on for iProc based platforms.
Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
drivers/thermal/broadcom/Kconfig | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/thermal/broadcom/Kconfig b/drivers/thermal/broadcom/Kconfig
index f0dea8a..b6f4b85 100644
--- a/drivers/thermal/broadcom/Kconfig
+++ b/drivers/thermal/broadcom/Kconfig
@@ -1,8 +1,9 @@
config BCM_NS_THERMAL
tristate "Northstar thermal driver"
depends on ARCH_BCM_IPROC || COMPILE_TEST
+ default y if ARCH_BCM_IPROC
help
- Northstar is a family of SoCs that includes e.g. BCM4708, BCM47081,
- BCM4709 and BCM47094. It contains DMU (Device Management Unit) block
- with a thermal sensor that allows checking CPU temperature. This
- driver provides support for it.
+ Support for the Northstar and Northstar Plus family of SoCs (e.g.
+ BCM4708, BCM4709, BCM5301x, BCM95852X, etc). It contains DMU (Device
+ Management Unit) block with a thermal sensor that allows checking CPU
+ temperature.
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 3/3] ARM: dts: NSP: Add Thermal Support
From: Jon Mason @ 2017-04-28 20:11 UTC (permalink / raw)
To: Florian Fainelli, Zhang Rui, Eduardo Valentin, Rob Herring,
Mark Rutland
Cc: bcm-kernel-feedback-list, linux-arm-kernel, linux-kernel,
linux-pm, devicetree
In-Reply-To: <1493410291-16679-1-git-send-email-jon.mason@broadcom.com>
Add thermal support via the ns-thermal driver and create a single
thermal zone for the entire SoC.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 832795b..be6fcfb 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -383,6 +383,12 @@
<0x3f408 0x04>;
};
+ thermal: thermal@3f2c0 {
+ compatible = "brcm,ns-thermal";
+ reg = <0x3f2c0 0x10>;
+ #thermal-sensor-cells = <0>;
+ };
+
sata_phy: sata_phy@40100 {
compatible = "brcm,iproc-nsp-sata-phy";
reg = <0x40100 0x340>;
@@ -533,4 +539,24 @@
brcm,pcie-msi-inten;
};
};
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ coefficients = <(-556) 418000>;
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
};
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v5 6/9] NFC: trf7970a: Remove support for 'vin-voltage-override' DT property
From: Rob Herring @ 2017-04-28 20:23 UTC (permalink / raw)
To: Mark Greer
Cc: Samuel Ortiz, linux-wireless-u79uwXL29TY76Z2rM5mHXA,
linux-nfc-hn68Rpc1hR1g9hUCZPvPmw,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170425224356.11498-7-mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
On Tue, Apr 25, 2017 at 03:43:53PM -0700, Mark Greer wrote:
> The 'vin-voltage-override' DT property is used by the trf7970a
> driver to override the voltage presented to the driver by the
> regulator subsystem. This is unnecessary as properly specifying
> the regulator chain via DT properties will accomplish the same
> thing. Therefore, remove support for 'vin-voltage-override'.
>
> Signed-off-by: Mark Greer <mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
> ---
> Documentation/devicetree/bindings/net/nfc/trf7970a.txt | 2 --
> drivers/nfc/trf7970a.c | 11 +----------
> 2 files changed, 1 insertion(+), 12 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH v2 1/2] net: dsa: b53: Add compatible strings for the Cygnus-family BCM11360.
From: Rob Herring @ 2017-04-28 20:25 UTC (permalink / raw)
To: Eric Anholt
Cc: Florian Fainelli, Vivien Didelot, Andrew Lunn,
netdev-u79uwXL29TY76Z2rM5mHXA, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Ray Jui,
Scott Branden, Jon Mason
In-Reply-To: <20170425235357.7690-1-eric-WhKQ6XTQaPysTnJN9+BGXg@public.gmane.org>
On Tue, Apr 25, 2017 at 04:53:56PM -0700, Eric Anholt wrote:
> Cygnus is a small family of SoCs, of which we currently have
> devicetree for BCM11360 and BCM58300. The 11360's B53 is mostly the
> same as 58xx, just requiring a tiny bit of setup that was previously
> missing.
>
> Signed-off-by: Eric Anholt <eric-WhKQ6XTQaPysTnJN9+BGXg@public.gmane.org>
> Reviewed-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>
> v2: Reorder the entry in the docs (suggestion by Scott Branden), add
> missing '"'
>
> Documentation/devicetree/bindings/net/dsa/b53.txt | 3 +++
> drivers/net/dsa/b53/b53_srab.c | 2 ++
> 2 files changed, 5 insertions(+)
Everyone learns the hard way that specific compatibles are needed.
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Rob
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* [PATCH 0/3] USB3 support for Broadcom NS2 SoC
From: Jon Mason @ 2017-04-28 20:29 UTC (permalink / raw)
To: Florian Fainelli, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland
Cc: bcm-kernel-feedback-list, linux-arm-kernel, linux-kernel,
devicetree
This patch set contains the USB3 support for Broadcom NS2 SoC. The USB3
PHY is connected through the MDIO interface.
Yendapally Reddy Dhananjaya Reddy (3):
dt-bindings: phy: Add documentation for NS2 USB3 PHY
phy: Add USB3 PHY support for Broadcom NS2 SoC
arm64: dts: ns2: Add USB3 Support
.../devicetree/bindings/phy/brcm,ns2-usb3-phy.txt | 82 +++
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 16 +
arch/arm64/boot/dts/broadcom/ns2-xmc.dts | 8 +
arch/arm64/boot/dts/broadcom/ns2.dtsi | 62 +++
drivers/phy/Kconfig | 9 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-bcm-ns2-usb3.c | 596 +++++++++++++++++++++
7 files changed, 774 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/brcm,ns2-usb3-phy.txt
create mode 100644 drivers/phy/phy-bcm-ns2-usb3.c
--
2.7.4
^ permalink raw reply
* [PATCH 1/3] dt-bindings: phy: Add documentation for NS2 USB3 PHY
From: Jon Mason @ 2017-04-28 20:29 UTC (permalink / raw)
To: Florian Fainelli, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland
Cc: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1493411381-16833-1-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
From: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Add documentation for USB3 PHY available in NS2 SoC
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
.../devicetree/bindings/phy/brcm,ns2-usb3-phy.txt | 82 ++++++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/brcm,ns2-usb3-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/brcm,ns2-usb3-phy.txt b/Documentation/devicetree/bindings/phy/brcm,ns2-usb3-phy.txt
new file mode 100644
index 0000000..5bb8d53
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/brcm,ns2-usb3-phy.txt
@@ -0,0 +1,82 @@
+Broadcom USB3 dual port phy for Northstar2 SoC
+This is a child bus node of "brcm,mdio-mux-iproc" node.
+
+Required mdio bus properties:
+- reg: MDIO Bus number for the MDIO interface
+- #address-cells: must be 1
+- #size-cells: must be 0
+
+Required PHY properties:
+- compatible: should be "brcm,ns2-usb3-phy"
+- reg: Phy address in the MDIO interface
+- usb3-ctrl-syscon: handler of syscon node defining physical address
+ of usb3 control register.
+- usb3-phy-cfg-syscon: handler of syscon node defining physical base
+ address and length of usb3 phy config region.
+- usb3-rst-ctrl-syscon: handler of syscon node defining physical base
+ address and length of idm reset control of two ports.
+- #phy-cells: must be 0
+- #address-cells: must be 1
+- #size-cells: must be 0
+
+Sub-nodes:
+ Each port's PHY should be represented as a sub-node.
+
+Sub-nodes required properties:
+ - reg: the PHY number
+ - phy-cells: from the generic PHY bindings, must be 0
+
+Required usb3 control properties:
+- compatible: should be "brcm,ns2-usb3-ctrl"
+- reg: offset and length of the control registers
+
+Required usb3 phy config properties:
+- compatible: should be "brcm,ns2-usb3-phy-cfg"
+- reg: offset and length of the phy config registers
+
+Required usb3 reset control properties:
+- compatible: should be "brcm,ns2-usb3-rst-ctrl"
+- reg: offset and length of the reset control registers
+
+Example:
+
+mdio@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3phy: usb3phy@0 {
+ compatible = "brcm,ns2-usb3-phy";
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ usb3-ctrl-syscon = <&usb3_ctrl>;
+ usb3-phy-cfg-syscon = <&usb3_phy_cfg>;
+ usb3-rst-ctrl-syscon = <&usb3_rst_ctrl>;
+
+ usb3phy0: usbphy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ usb3phy1: usbphy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+};
+
+usb3_ctrl: syscon@6501d144 {
+ compatible = "brcm,ns2-usb3-ctrl", "syscon";
+ reg = <0x6501d144 0x4>;
+};
+
+usb3_phy_cfg: syscon@66000910 {
+ compatible = "brcm,ns2-usb3-phy-cfg", "syscon";
+ reg = <0x66000910 0x14>;
+};
+
+usb3_rst_ctrl: syscon@67000800 {
+ compatible = "brcm,ns2-usb3-rst-ctrl", "syscon";
+ reg = <0x67000800 0x1808>;
+};
--
2.7.4
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* [PATCH 2/3] phy: Add USB3 PHY support for Broadcom NS2 SoC
From: Jon Mason @ 2017-04-28 20:29 UTC (permalink / raw)
To: Florian Fainelli, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland
Cc: bcm-kernel-feedback-list, linux-arm-kernel, linux-kernel,
devicetree
In-Reply-To: <1493411381-16833-1-git-send-email-jon.mason@broadcom.com>
From: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
This patch adds support for Broadcom NS2 USB3 PHY
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
drivers/phy/Kconfig | 9 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-bcm-ns2-usb3.c | 596 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 606 insertions(+)
create mode 100644 drivers/phy/phy-bcm-ns2-usb3.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index dc5277a..c86f47c 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -498,6 +498,15 @@ config PHY_NS2_PCIE
Enable this to support the Broadcom Northstar2 PCIe PHY.
If unsure, say N.
+config PHY_NS2_USB3
+ tristate "Broadcom NorthStar2 USB3 PHY driver"
+ depends on OF && (ARCH_BCM_IPROC || COMPILE_TEST)
+ select GENERIC_PHY
+ default ARCH_BCM_IPROC
+ help
+ Enable this to support the Broadcom Northstar2 USB3 PHY.
+ If unsure, say N.
+
config PHY_MESON8B_USB2
tristate "Meson8b and GXBB USB2 PHY driver"
default ARCH_MESON
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index e7b0feb..8ad8920 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -61,5 +61,6 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
+obj-$(CONFIG_PHY_NS2_USB3) += phy-bcm-ns2-usb3.o
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
obj-$(CONFIG_PHY_NSP_USB3) += phy-bcm-nsp-usb3.o
diff --git a/drivers/phy/phy-bcm-ns2-usb3.c b/drivers/phy/phy-bcm-ns2-usb3.c
new file mode 100644
index 0000000..203f509
--- /dev/null
+++ b/drivers/phy/phy-bcm-ns2-usb3.c
@@ -0,0 +1,596 @@
+/*
+ * Copyright (C) 2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mdio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+#define NS2_USB3_PHY_MAX 0x02
+
+#define NS2_USB3_PHY_CONFIG_CTRL_REG 0x00
+#define NS2_USB3_PHY_CONFIG_CTRL_MASK (BIT(3) | BIT(4) | BIT(5))
+#define NS2_USB3_PHY_CONFIG_CTRL_PLL_SEQ_START BIT(6)
+
+#define NS2_USB3_PHY_P0CTL_REG 0x04
+#define NS2_USB3_PHY_P1CTL_REG 0x08
+#define NS2_USB3_PHY_PXCTL_I_BIT BIT(1)
+
+#define NS2_USB3_PHY_MISC_STATUS_REG 0x10
+
+#define NS2_IDM_RST_CTRL_P0_OFFSET 0x3f8
+#define NS2_IDM_RST_CTRL_P1_OFFSET 0x13f8
+#define NS2_IDM_RESET_CONTROL_BIT BIT(0)
+
+#define NS2_IDM_IO_CTRL_P0_OFFSET 0x0
+#define NS2_IDM_IO_CTRL_P1_OFFSET 0x1000
+/* Bit 23 for PPC Polarity, Bit 24 for PPC NANDNOR select */
+#define NS2_IDM_IO_CTRL_PPC_CFG (BIT(23) | BIT(24))
+
+#define NS2_PHY_RESET_BIT BIT(5)
+#define NS2_PHY_PLL_RESET_BIT BIT(6)
+
+/* NS2 USB3 MDIO */
+#define NS2_USB3_MDIO_PLL30_ADDR 0x8000
+#define NS2_USB3_MDIO_BLK_ACCESS 0x1F
+#define NS2_USB3_MDIO_PLL30_ANAPLL_CTRL 0x14
+#define NS2_USB3_MDIO_PLL30_ANAPLL_CTRL_VAL 0x23
+#define NS2_USB3_MDIO_PLL30_GEN_PLL 0xF
+#define NS2_USB3_MDIO_PLL30_GEN_PLL_PCLK_SEL BIT(11)
+#define NS2_USB3_MDIO_P0_AFE30_ADDR 0x8080
+#define NS2_USB3_MDIO_P1_AFE30_ADDR 0x9080
+#define NS2_USB3_MDIO_AFE30_RX_SIG_DETECT 0x5
+#define NS2_USB3_MDIO_AFE30_RX_SIG_DETECT_VAL 0xAC0D
+
+#define NS2_USB3_MDIO_P0_PIPE_BLK_ADDR 0x8060
+#define NS2_USB3_MDIO_P1_PIPE_BLK_ADDR 0x9060
+#define NS2_USB3_MDIO_PIPE_BLK_REG_1_OFFSET 0x1
+#define NS2_USB3_MDIO_PIPE_BLK_REG_1_VAL 0x207
+
+#define NS2_USB3_MDIO_P0_AEQ_BLK_ADDR 0x80E0
+#define NS2_USB3_MDIO_P1_AEQ_BLK_ADDR 0x90E0
+#define NS2_USB3_MDIO_AEQ_BLK_REG_1_OFFSET 0x1
+#define NS2_USB3_MDIO_AEQ_BLK_REG_1_VAL 0x3000
+
+/* USB3 Histogram Programming */
+#define NS2_USB3_IRAADR_OFFSET 0x198
+#define NS2_USB3_IRADAT_OFFSET 0x19c
+#define USB3_HISTOGRAM_OFFSET_VAL 0xA200
+#define USB3_BYPASS_VBUS_INPUTS BIT(2)
+#define USB3_OVERRIDE_VBU_PRESENT BIT(3)
+#define USB3_OVERRIDE_CURRENT_MASK (~(BIT(4)))
+#define NS2_USB3_MDIO_RESET_BIT (BIT(12))
+
+enum ns2_phy_block {
+ PHY_RESET,
+ PHY_PLL_RESET,
+ PHY_SOFT_RESET,
+ PHY_PIPE_RESET,
+ PHY_REF_CLOCK,
+ PHY_PLL_SEQ_START,
+ PHY_PLL_STATUS,
+ PHY_VBUS_PPC,
+};
+
+enum ns2_reg_base {
+ NS2_USB3_CTRL = 1,
+ NS2_USB3_PHY_CFG,
+ NS2_USB3_RST_CTRL,
+ NS2_USB3_REG_BASE_MAX
+};
+
+struct ns2_usb3_phy {
+ void __iomem *reg_base[NS2_USB3_REG_BASE_MAX];
+ struct ns2_usb3_phy_master *mphy;
+ struct phy *phy;
+ int port_no;
+};
+
+struct ns2_usb3_phy_master {
+ struct ns2_usb3_phy iphys[NS2_USB3_PHY_MAX];
+ struct mdio_device *mdiodev;
+ struct mutex phy_mutex;
+ int init_count; /* PHY is dual port phy, so init once*/
+};
+
+static int iproc_ns2_phy_action(struct ns2_usb3_phy *iphy,
+ enum ns2_phy_block block, bool assert)
+{
+ void __iomem *addr;
+ u32 data, count;
+ u32 offset = 0;
+ int ret = 0;
+
+ switch (block) {
+ case PHY_RESET:
+ addr = iphy->reg_base[NS2_USB3_CTRL];
+
+ ret = regmap_read(addr, offset, &data);
+ if (ret != 0)
+ return ret;
+
+ if (assert)
+ data &= ~NS2_PHY_RESET_BIT;
+ else
+ data |= NS2_PHY_RESET_BIT;
+
+ ret = regmap_write(addr, offset, data);
+ break;
+
+ case PHY_PLL_RESET:
+ addr = iphy->reg_base[NS2_USB3_CTRL];
+
+ ret = regmap_read(addr, offset, &data);
+ if (ret != 0)
+ return ret;
+
+ if (assert)
+ data &= ~NS2_PHY_PLL_RESET_BIT;
+ else
+ data |= NS2_PHY_PLL_RESET_BIT;
+
+ ret = regmap_write(addr, offset, data);
+ break;
+
+ case PHY_SOFT_RESET:
+ addr = iphy->reg_base[NS2_USB3_PHY_CFG];
+ offset = NS2_USB3_PHY_P0CTL_REG;
+
+ ret = regmap_read(addr, offset, &data);
+ if (ret != 0)
+ return ret;
+
+ if (assert)
+ data &= ~NS2_USB3_PHY_PXCTL_I_BIT;
+ else
+ data |= NS2_USB3_PHY_PXCTL_I_BIT;
+
+ ret = regmap_write(addr, offset, data);
+ if (ret != 0)
+ return ret;
+
+ offset = NS2_USB3_PHY_P1CTL_REG;
+
+ ret = regmap_read(addr, offset, &data);
+ if (ret != 0)
+ return ret;
+
+ if (assert)
+ data &= ~NS2_USB3_PHY_PXCTL_I_BIT;
+ else
+ data |= NS2_USB3_PHY_PXCTL_I_BIT;
+
+ ret = regmap_write(addr, offset, data);
+ break;
+
+ case PHY_PIPE_RESET:
+ addr = iphy->reg_base[NS2_USB3_RST_CTRL];
+ offset = NS2_IDM_RST_CTRL_P0_OFFSET;
+
+ ret = regmap_read(addr, offset, &data);
+ if (ret != 0)
+ return ret;
+
+ if (assert)
+ data |= NS2_IDM_RESET_CONTROL_BIT;
+ else
+ data &= ~NS2_IDM_RESET_CONTROL_BIT;
+
+ ret = regmap_write(addr, offset, data);
+ if (ret != 0)
+ return ret;
+
+ offset = NS2_IDM_RST_CTRL_P1_OFFSET;
+ ret = regmap_read(addr, offset, &data);
+ if (ret != 0)
+ return ret;
+
+ if (assert)
+ data |= NS2_IDM_RESET_CONTROL_BIT;
+ else
+ data &= ~NS2_IDM_RESET_CONTROL_BIT;
+
+ ret = regmap_write(addr, offset, data);
+ break;
+
+ case PHY_VBUS_PPC:
+ addr = iphy->reg_base[NS2_USB3_RST_CTRL];
+ offset = NS2_IDM_IO_CTRL_P0_OFFSET;
+
+ ret = regmap_read(addr, offset, &data);
+ if (ret != 0)
+ return ret;
+
+ if (assert)
+ data |= NS2_IDM_IO_CTRL_PPC_CFG;
+ else
+ data &= ~NS2_IDM_IO_CTRL_PPC_CFG;
+
+ ret = regmap_write(addr, offset, data);
+ if (ret != 0)
+ return ret;
+
+ offset = NS2_IDM_IO_CTRL_P1_OFFSET;
+ ret = regmap_read(addr, offset, &data);
+ if (ret != 0)
+ return ret;
+
+ if (assert)
+ data |= NS2_IDM_IO_CTRL_PPC_CFG;
+ else
+ data &= ~NS2_IDM_IO_CTRL_PPC_CFG;
+
+ ret = regmap_write(addr, offset, data);
+ break;
+
+ case PHY_REF_CLOCK:
+ addr = iphy->reg_base[NS2_USB3_PHY_CFG];
+ offset = NS2_USB3_PHY_CONFIG_CTRL_REG;
+
+ ret = regmap_read(addr, offset, &data);
+ if (ret != 0)
+ return ret;
+
+ data &= ~NS2_USB3_PHY_CONFIG_CTRL_MASK;
+
+ ret = regmap_write(addr, offset, data);
+ break;
+
+ case PHY_PLL_SEQ_START:
+ addr = iphy->reg_base[NS2_USB3_PHY_CFG];
+ offset = NS2_USB3_PHY_CONFIG_CTRL_REG;
+
+ ret = regmap_read(addr, offset, &data);
+ if (ret != 0)
+ return ret;
+
+ data |= NS2_USB3_PHY_CONFIG_CTRL_PLL_SEQ_START;
+
+ ret = regmap_write(addr, offset, data);
+ break;
+
+ case PHY_PLL_STATUS:
+ count = 2000;
+ addr = iphy->reg_base[NS2_USB3_PHY_CFG];
+ offset = NS2_USB3_PHY_MISC_STATUS_REG;
+
+ do {
+ udelay(1);
+ ret = regmap_read(addr, offset, &data);
+ if (ret != 0)
+ return ret;
+
+ if (data == 1)
+ break;
+ } while (--count);
+
+ if (!count)
+ ret = -ETIMEDOUT;
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static int ns2_usb3_phy_exit(struct phy *phy)
+{
+ struct ns2_usb3_phy *iphy = phy_get_drvdata(phy);
+ int rc = 0;
+
+ mutex_lock(&iphy->mphy->phy_mutex);
+
+ if (iphy->mphy->init_count <= 0) {
+ mutex_unlock(&iphy->mphy->phy_mutex);
+ return 0;
+ } else if (iphy->mphy->init_count == 1) {
+ /* Only put in to reset for last port to exit */
+ rc = iproc_ns2_phy_action(iphy, PHY_PLL_RESET, true);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_SOFT_RESET, true);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_RESET, true);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_PIPE_RESET, true);
+ if (rc)
+ goto out;
+ }
+
+out:
+ iphy->mphy->init_count--;
+ mutex_unlock(&iphy->mphy->phy_mutex);
+
+ return rc;
+}
+
+static int ns2_usb3_phy_init(struct phy *phy)
+{
+ struct ns2_usb3_phy *iphy = phy_get_drvdata(phy);
+ u16 addr;
+ u16 reg_val;
+ int rc;
+
+ mutex_lock(&iphy->mphy->phy_mutex);
+
+ if (iphy->mphy->init_count) {
+ /* Use count to identify last port to call phy_exit. */
+ iphy->mphy->init_count++;
+ mutex_unlock(&iphy->mphy->phy_mutex);
+ return 0;
+ }
+
+ rc = iproc_ns2_phy_action(iphy, PHY_RESET, false);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_SOFT_RESET, true);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_PIPE_RESET, true);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_REF_CLOCK, true);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_PLL_RESET, true);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_RESET, true);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_RESET, false);
+ if (rc)
+ goto out;
+
+ /* PLL programming */
+ /* PHY PLL30 Block */
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_BLK_ACCESS,
+ NS2_USB3_MDIO_PLL30_ADDR);
+ if (rc)
+ goto out;
+
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_PLL30_ANAPLL_CTRL,
+ NS2_USB3_MDIO_PLL30_ANAPLL_CTRL_VAL);
+ if (rc)
+ goto out;
+
+ reg_val = (u16) mdiobus_read(iphy->mphy->mdiodev->bus,
+ iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_PLL30_GEN_PLL);
+ reg_val |= NS2_USB3_MDIO_PLL30_GEN_PLL_PCLK_SEL;
+
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_PLL30_GEN_PLL, reg_val);
+ if (rc)
+ goto out;
+
+ /* PHY AFE30 Block */
+ addr = NS2_USB3_MDIO_P0_AFE30_ADDR;
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_BLK_ACCESS, addr);
+ if (rc)
+ goto out;
+
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_AFE30_RX_SIG_DETECT,
+ NS2_USB3_MDIO_AFE30_RX_SIG_DETECT_VAL);
+ if (rc)
+ goto out;
+
+ addr = NS2_USB3_MDIO_P1_AFE30_ADDR;
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_BLK_ACCESS, addr);
+ if (rc)
+ goto out;
+
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_AFE30_RX_SIG_DETECT,
+ NS2_USB3_MDIO_AFE30_RX_SIG_DETECT_VAL);
+ if (rc)
+ goto out;
+
+ /* PHY PIPE Block */
+ addr = NS2_USB3_MDIO_P0_PIPE_BLK_ADDR;
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_BLK_ACCESS, addr);
+ if (rc)
+ goto out;
+
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_PIPE_BLK_REG_1_OFFSET,
+ NS2_USB3_MDIO_PIPE_BLK_REG_1_VAL);
+ if (rc)
+ goto out;
+
+ addr = NS2_USB3_MDIO_P1_PIPE_BLK_ADDR;
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_BLK_ACCESS, addr);
+ if (rc)
+ goto out;
+
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_PIPE_BLK_REG_1_OFFSET,
+ NS2_USB3_MDIO_PIPE_BLK_REG_1_VAL);
+ if (rc)
+ goto out;
+
+ /* AEQ Block */
+ addr = NS2_USB3_MDIO_P0_AEQ_BLK_ADDR;
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_BLK_ACCESS, addr);
+ if (rc)
+ goto out;
+
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_AEQ_BLK_REG_1_OFFSET,
+ NS2_USB3_MDIO_AEQ_BLK_REG_1_VAL);
+ if (rc)
+ goto out;
+
+ /* PHY PORT_1 */
+ addr = NS2_USB3_MDIO_P1_AEQ_BLK_ADDR;
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_BLK_ACCESS, addr);
+ if (rc)
+ goto out;
+
+ rc = mdiobus_write(iphy->mphy->mdiodev->bus, iphy->mphy->mdiodev->addr,
+ NS2_USB3_MDIO_AEQ_BLK_REG_1_OFFSET,
+ NS2_USB3_MDIO_AEQ_BLK_REG_1_VAL);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_PLL_SEQ_START, true);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_PIPE_RESET, false);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_SOFT_RESET, false);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_PLL_RESET, false);
+ if (rc)
+ goto out;
+
+ rc = iproc_ns2_phy_action(iphy, PHY_PLL_STATUS, true);
+ if (rc)
+ goto out;
+
+ /* Set USB3H VBUS PPC Polarity and NandNor select */
+ rc = iproc_ns2_phy_action(iphy, PHY_VBUS_PPC, true);
+
+out:
+ iphy->mphy->init_count++;
+ mutex_unlock(&iphy->mphy->phy_mutex);
+
+ return rc;
+}
+
+static struct phy_ops ns2_usb3_phy_ops = {
+ .init = ns2_usb3_phy_init,
+ .exit = ns2_usb3_phy_exit,
+ .owner = THIS_MODULE,
+};
+
+static int ns2_usb3_phy_probe(struct mdio_device *mdiodev)
+{
+ struct device *dev = &mdiodev->dev;
+ struct device_node *dn = dev->of_node, *child;
+ struct ns2_usb3_phy_master *mphy;
+ struct phy_provider *provider;
+ int cnt;
+
+ mphy = devm_kzalloc(dev, sizeof(*mphy), GFP_KERNEL);
+ if (!mphy)
+ return -ENOMEM;
+ mphy->mdiodev = mdiodev;
+ mutex_init(&mphy->phy_mutex);
+ mphy->init_count = 0;
+
+ cnt = 0;
+ for_each_available_child_of_node(dn, child) {
+ struct ns2_usb3_phy *iphy;
+ unsigned int val;
+ struct regmap *io;
+
+ iphy = &mphy->iphys[cnt];
+ if (of_property_read_u32(child, "reg", &val)) {
+ dev_err(dev, "missing reg property in node %s\n",
+ child->name);
+ return -EINVAL;
+ }
+ iphy->port_no = val;
+ iphy->mphy = mphy;
+
+ io = syscon_regmap_lookup_by_phandle(dn, "usb3-ctrl-syscon");
+ if (IS_ERR(io))
+ return PTR_ERR(io);
+ iphy->reg_base[NS2_USB3_CTRL] = io;
+
+ io = syscon_regmap_lookup_by_phandle(dn, "usb3-phy-cfg-syscon");
+ if (IS_ERR(io))
+ return PTR_ERR(io);
+ iphy->reg_base[NS2_USB3_PHY_CFG] = io;
+
+ io = syscon_regmap_lookup_by_phandle(dn,
+ "usb3-rst-ctrl-syscon");
+ if (IS_ERR(io))
+ return PTR_ERR(io);
+ iphy->reg_base[NS2_USB3_RST_CTRL] = io;
+
+ iphy->phy = devm_phy_create(dev, child, &ns2_usb3_phy_ops);
+ if (IS_ERR(iphy->phy)) {
+ dev_err(dev, "failed to create PHY\n");
+ return PTR_ERR(iphy->phy);
+ }
+
+ phy_set_drvdata(iphy->phy, iphy);
+ cnt++;
+ }
+
+ dev_set_drvdata(dev, mphy);
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(provider)) {
+ dev_err(dev, "could not register PHY provider\n");
+ return PTR_ERR(provider);
+ }
+
+ dev_info(dev, "registered %d phy(s)\n", cnt);
+ return 0;
+}
+
+static const struct of_device_id ns2_usb3_phy_of_match[] = {
+ {.compatible = "brcm,ns2-usb3-phy",},
+ { /* sentinel */ }
+};
+
+static struct mdio_driver ns2_usb3_phy_driver = {
+ .mdiodrv = {
+ .driver = {
+ .name = "ns2-usb3-phy",
+ .of_match_table = ns2_usb3_phy_of_match,
+ },
+ },
+ .probe = ns2_usb3_phy_probe,
+};
+mdio_module_driver(ns2_usb3_phy_driver);
+
+MODULE_DESCRIPTION("Broadcom NS2 USB3 PHY driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Broadcom");
--
2.7.4
^ permalink raw reply related
* [PATCH 3/3] arm64: dts: ns2: Add USB3 Support
From: Jon Mason @ 2017-04-28 20:29 UTC (permalink / raw)
To: Florian Fainelli, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland
Cc: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1493411381-16833-1-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
From: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Add USB3 support to the Northstar2 Device tree files
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 16 +++++++++
arch/arm64/boot/dts/broadcom/ns2-xmc.dts | 8 +++++
arch/arm64/boot/dts/broadcom/ns2.dtsi | 62 ++++++++++++++++++++++++++++++++
3 files changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
index ec19fbf..7cd2ef7 100644
--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -234,3 +234,19 @@
};
};
};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/ns2-xmc.dts
index ab4ae1a..8e8feb7 100644
--- a/arch/arm64/boot/dts/broadcom/ns2-xmc.dts
+++ b/arch/arm64/boot/dts/broadcom/ns2-xmc.dts
@@ -189,3 +189,11 @@
&uart3 {
status = "okay";
};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 35a309a..2360ff5 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -343,6 +343,11 @@
<0x660009b0 0x40>;
};
+ usb3_ctrl: syscon@6501d144 {
+ compatible = "brcm,ns2-usb3-ctrl", "syscon";
+ reg = <0x6501d144 0x4>;
+ };
+
gpio_aon: gpio@65024800 {
compatible = "brcm,iproc-gpio";
reg = <0x65024800 0x50>,
@@ -460,6 +465,11 @@
};
};
+ usb3_phy_cfg: syscon@66000910 {
+ compatible = "brcm,ns2-usb3-phy-cfg", "syscon";
+ reg = <0x66000910 0x14>;
+ };
+
pwm: pwm@66010000 {
compatible = "brcm,iproc-pwm";
reg = <0x66010000 0x28>;
@@ -487,6 +497,34 @@
};
};
+ mdio@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_phy: usb3_phy@0 {
+ compatible = "brcm,ns2-usb3-phy";
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ usb3-ctrl-syscon = <&usb3_ctrl>;
+ usb3-phy-cfg-syscon = <&usb3_phy_cfg>;
+ usb3-rst-ctrl-syscon = <&usb3_rst_ctrl>;
+
+ usb3_phy0: usb3_phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb3_phy1: usb_phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
mdio@7 {
reg = <0x7>;
#address-cells = <1>;
@@ -652,6 +690,26 @@
reg = <0x66220000 0x28>;
};
+ xhci0: usb@66300000 {
+ compatible = "generic-xhci";
+ reg = <0x66300000 0x1000>;
+ interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy0>;
+ phy-names = "usb";
+ dma-coherent;
+ status = "disabled";
+ };
+
+ xhci1: usb@66310000 {
+ compatible = "generic-xhci";
+ reg = <0x66310000 0x1000>;
+ interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy1>;
+ phy-names = "usb";
+ dma-coherent;
+ status = "disabled";
+ };
+
sata_phy: sata_phy@663f0100 {
compatible = "brcm,iproc-ns2-sata-phy";
reg = <0x663f0100 0x1f00>,
@@ -747,5 +805,9 @@
#size-cells = <0>;
};
+ usb3_rst_ctrl: syscon@67000408 {
+ compatible = "brcm,ns2-usb3-rst-ctrl", "syscon";
+ reg = <0x67000408 0x1808>;
+ };
};
};
--
2.7.4
--
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* Re: [PATCH v2 25/30] arm: dts: mt7623: rename mt7623-evb.dts to arch/arm/boot/dts/mt7623n-rfb.dtsi
From: Rob Herring @ 2017-04-28 20:30 UTC (permalink / raw)
To: sean.wang-NuS5LvNUpcJWk0Htik3J/w
Cc: matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w, john-Pj+rj9U5foFAfugRpC6u6w,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1493198774-4478-26-git-send-email-sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Wed, Apr 26, 2017 at 05:26:09PM +0800, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote:
> From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>
> There are 2 versions of the SoC. MT7623N is almost identical to MT7623A
> but has some additional multimedia features. The reference boards are
> available as NAND or MMC and might have a different ethernet setup. In
> order to reduce the duplication of devicetree code we add an intermediate
> dtsi file for these reference boards. Additionally Mediatek pointed out,
> that the EVB is yet another board and the board in question is infact the
> RFB. Take this into account while renaming the files.
You are breaking compatibility with existing DTs. Just document which
flavor you want "mediatek,mt7623" to refer to and add the new one. Or
just add 2 new strings but keep the old one.
>
> Signed-off-by: John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
> Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>
> ---
> Documentation/devicetree/bindings/arm/mediatek.txt | 6 ++--
> arch/arm/boot/dts/Makefile | 2 +-
> arch/arm/boot/dts/mt7623-evb.dts | 33 ----------------------
> arch/arm/boot/dts/mt7623n-rfb-nand.dts | 21 ++++++++++++++
> arch/arm/boot/dts/mt7623n-rfb.dtsi | 29 +++++++++++++++++++
> arch/arm/mach-mediatek/mediatek.c | 4 +--
> arch/arm/mach-mediatek/platsmp.c | 2 +-
> 7 files changed, 57 insertions(+), 40 deletions(-)
> delete mode 100644 arch/arm/boot/dts/mt7623-evb.dts
> create mode 100644 arch/arm/boot/dts/mt7623n-rfb-nand.dts
> create mode 100644 arch/arm/boot/dts/mt7623n-rfb.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
> index c860b24..7f7c804 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek.txt
> @@ -12,7 +12,7 @@ compatible: Must contain one of
> "mediatek,mt6592"
> "mediatek,mt6755"
> "mediatek,mt6795"
> - "mediatek,mt7623"
> + "mediatek,mt7623n"
> "mediatek,mt8127"
> "mediatek,mt8135"
> "mediatek,mt8173"
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^ permalink raw reply
* Re: [PATCH v3 2/3] thermal: broadcom: ns-thermal: default on iProc SoCs
From: Scott Branden @ 2017-04-28 20:36 UTC (permalink / raw)
To: Jon Mason, Florian Fainelli, Zhang Rui, Eduardo Valentin,
Rob Herring, Mark Rutland
Cc: bcm-kernel-feedback-list, linux-arm-kernel, linux-kernel,
linux-pm, devicetree
In-Reply-To: <1493410291-16679-3-git-send-email-jon.mason@broadcom.com>
On 17-04-28 01:11 PM, Jon Mason wrote:
> Tweak the Kconfig description to mention support for NSP and make the
> default on for iProc based platforms.
>
> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
> ---
> drivers/thermal/broadcom/Kconfig | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/thermal/broadcom/Kconfig b/drivers/thermal/broadcom/Kconfig
> index f0dea8a..b6f4b85 100644
> --- a/drivers/thermal/broadcom/Kconfig
> +++ b/drivers/thermal/broadcom/Kconfig
> @@ -1,8 +1,9 @@
> config BCM_NS_THERMAL
> tristate "Northstar thermal driver"
> depends on ARCH_BCM_IPROC || COMPILE_TEST
If this driver is used on these SoCs then it:
depends on ARCH_BCM_NSP || ARCH_BCM_5301X || COMPILE_TEST
?
> + default y if ARCH_BCM_IPROC
> help
> - Northstar is a family of SoCs that includes e.g. BCM4708, BCM47081,
> - BCM4709 and BCM47094. It contains DMU (Device Management Unit) block
> - with a thermal sensor that allows checking CPU temperature. This
> - driver provides support for it.
> + Support for the Northstar and Northstar Plus family of SoCs (e.g.
> + BCM4708, BCM4709, BCM5301x, BCM95852X, etc). It contains DMU (Device
> + Management Unit) block with a thermal sensor that allows checking CPU
> + temperature.
>
^ permalink raw reply
* Re: [PATCH v2 29/30] dt-bindings: add vendor prefix for bananapi
From: Rob Herring @ 2017-04-28 20:37 UTC (permalink / raw)
To: sean.wang-NuS5LvNUpcJWk0Htik3J/w
Cc: matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w, john-Pj+rj9U5foFAfugRpC6u6w,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1493198774-4478-30-git-send-email-sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Wed, Apr 26, 2017 at 05:26:13PM +0800, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote:
> From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>
> Banana Pi team in Sinovoip Co., Limited which are dedicated to
> design and manufacture open hardware product.
>
> Website: http://www.banana-pi.org/
>
> Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index ec0bfb9..8ca0f3c 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -44,6 +44,7 @@ avia avia semiconductor
> avic Shanghai AVIC Optoelectronics Co., Ltd.
> axentia Axentia Technologies AB
> axis Axis Communications AB
> +bananapi Banana Pi SINOVOP CO., LIMITED
s/SINOVOP/SINOVOIP/
> boe BOE Technology Group Co., Ltd.
> bosch Bosch Sensortec GmbH
> boundary Boundary Devices Inc.
> --
> 1.9.1
>
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^ permalink raw reply
* Re: [PATCH V6 1/9] PM / OPP: Introduce "power-domain-opp" property
From: Rob Herring @ 2017-04-28 20:48 UTC (permalink / raw)
To: Viresh Kumar
Cc: Rafael Wysocki, ulf.hansson-QSEj5FYQhm4dnm+yROfE0A, Kevin Hilman,
Viresh Kumar, Nishanth Menon, Stephen Boyd,
linaro-kernel-cunTk1MwBs8s++Sfvej+rw,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Vincent Guittot,
lina.iyer-QSEj5FYQhm4dnm+yROfE0A, rnayak-sgV2jX0FEOL9JmXXK+q4OQ,
sudeep.holla-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <025acedb263eaa6089d354d9630214ada8013990.1493203884.git.viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Wed, Apr 26, 2017 at 04:27:05PM +0530, Viresh Kumar wrote:
> Power-domains need to express their active states in DT and the devices
> within the power-domain need to express their dependency on those active
> states. The power-domains can use the OPP tables without any
> modifications to the bindings.
>
> Add a new property "power-domain-opp", which will contain phandle to the
> OPP node of the parent power domain. This is required for devices which
> have dependency on the configured active state of the power domain for
> their working.
>
> For some platforms the actual frequency and voltages of the power
> domains are managed by the firmware and are so hidden from the high
> level operating system. The "opp-hz" property is relaxed a bit to
> contain indexes instead of actual frequency values to support such
> platforms.
>
> Signed-off-by: Viresh Kumar <viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> Documentation/devicetree/bindings/opp/opp.txt | 74 ++++++++++++++++++++++++++-
> 1 file changed, 73 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt
> index 63725498bd20..6e30cae2a936 100644
> --- a/Documentation/devicetree/bindings/opp/opp.txt
> +++ b/Documentation/devicetree/bindings/opp/opp.txt
> @@ -77,7 +77,10 @@ This defines voltage-current-frequency combinations along with other related
> properties.
>
> Required properties:
> -- opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer.
> +- opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. In some
> + cases the exact frequency in Hz may be hidden from the OS by the firmware and
> + this field may contain values that represent the frequency in a firmware
> + dependent way, for example an index of an array in the firmware.
Not really sure OPP binding makes sense here. What about all the other
properties. We expose voltage, but not freq?
>
> Optional properties:
> - opp-microvolt: voltage in micro Volts.
> @@ -154,6 +157,13 @@ properties.
>
> - status: Marks the node enabled/disabled.
>
> +- power-domain-opp: Phandle to the OPP node of the parent power-domain. The
> + parent power-domain should be configured to the OPP whose node is pointed by
> + the phandle, in order to configure the device for the OPP node that contains
> + this property. The order in which the device and power domain should be
> + configured is implementation defined. The OPP table of a device can set this
> + property only if the device node contains "power-domains" property.
> +
I don't even know what to say on this. The continual evolution of
OPP bindings continues. This seems like further abuse of DT
power-domains (being a region in a chip that can be powergated) with
Linux PM domains.
Rob
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^ permalink raw reply
* Re: [PATCH v3 2/3] thermal: broadcom: ns-thermal: default on iProc SoCs
From: Jon Mason @ 2017-04-28 20:50 UTC (permalink / raw)
To: Scott Branden
Cc: Florian Fainelli, Zhang Rui, Eduardo Valentin, Rob Herring,
Mark Rutland, BCM Kernel Feedback, linux-arm-kernel, open list,
linux-pm,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <6628a958-087d-1221-7717-c07eeaec3cce@broadcom.com>
On Fri, Apr 28, 2017 at 4:36 PM, Scott Branden
<scott.branden@broadcom.com> wrote:
>
>
> On 17-04-28 01:11 PM, Jon Mason wrote:
>>
>> Tweak the Kconfig description to mention support for NSP and make the
>> default on for iProc based platforms.
>>
>> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
>> ---
>> drivers/thermal/broadcom/Kconfig | 9 +++++----
>> 1 file changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/thermal/broadcom/Kconfig
>> b/drivers/thermal/broadcom/Kconfig
>> index f0dea8a..b6f4b85 100644
>> --- a/drivers/thermal/broadcom/Kconfig
>> +++ b/drivers/thermal/broadcom/Kconfig
>> @@ -1,8 +1,9 @@
>> config BCM_NS_THERMAL
>> tristate "Northstar thermal driver"
>> depends on ARCH_BCM_IPROC || COMPILE_TEST
>
> If this driver is used on these SoCs then it:
> depends on ARCH_BCM_NSP || ARCH_BCM_5301X || COMPILE_TEST
> ?
The code referenced is outside of this patch, as that code was already
existing from when the driver was submitted.
I did some checking and NS2 and Cygnus do not have the registers in
use by this driver. So, you are correct in that this driver will
never be used for them. So, this is slightly over-permissive in
allowing a driver to be selected that could not ever be used on
non-NS/NSP hardware. But barring an incorrect DT string, it would
only result in an slightly larger kernel than necessary.
I'll do a follow-on patch to correct this with your suggestion above,
and push it separately (unless a v4 is needed on this series).
Thanks,
Jon
>> + default y if ARCH_BCM_IPROC
>> help
>> - Northstar is a family of SoCs that includes e.g. BCM4708,
>> BCM47081,
>> - BCM4709 and BCM47094. It contains DMU (Device Management Unit)
>> block
>> - with a thermal sensor that allows checking CPU temperature. This
>> - driver provides support for it.
>> + Support for the Northstar and Northstar Plus family of SoCs
>> (e.g.
>> + BCM4708, BCM4709, BCM5301x, BCM95852X, etc). It contains DMU
>> (Device
>> + Management Unit) block with a thermal sensor that allows
>> checking CPU
>> + temperature.
>>
>
^ permalink raw reply
* Re: [PATCH v5 02/10] irqchip/sunxi-nmi: add A64 R_INTC to the binding doc
From: Rob Herring @ 2017-04-28 20:51 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Thomas Gleixner, Maxime Ripard, Chen-Yu Tsai, Lee Jones,
Liam Girdwood, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20170426152023.41567-3-icenowy-h8G6r0blFSE@public.gmane.org>
On Wed, Apr 26, 2017 at 11:20:15PM +0800, Icenowy Zheng wrote:
> The A31 NMI driver seems to be using wrong base address.
>
> As we're going to convert to use a correct NMI base address (and
> correctly name it to R_INTC as the datasheet suggests), add a new
> compatible string for the "correct" R_INTC, which we will use for A64
> SoC.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> ---
> .../bindings/interrupt-controller/allwinner,sunxi-nmi.txt | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
^ permalink raw reply
* Re: [PATCH v3 1/2] ASoC: stm32: add bindings for SAI
From: Rob Herring @ 2017-04-28 20:53 UTC (permalink / raw)
To: olivier moysan
Cc: lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, broonie-DgEjT+Ai2ygdnm+yROfE0A,
perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w,
alexandre.torgue-qxv4g6HH51o, alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-F5mvAk5X5gdBDgjK7y7TUQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, arnaud.pouliquen-qxv4g6HH51o,
benjamin.gaignard-qxv4g6HH51o
In-Reply-To: <1491837596-2924-2-git-send-email-olivier.moysan-qxv4g6HH51o@public.gmane.org>
On Mon, Apr 10, 2017 at 05:19:55PM +0200, olivier moysan wrote:
> This patch adds documentation of device tree bindings for the
> STM32 SAI ASoC driver.
>
> Signed-off-by: olivier moysan <olivier.moysan-qxv4g6HH51o@public.gmane.org>
> ---
> .../devicetree/bindings/sound/st,stm32-sai.txt | 89 ++++++++++++++++++++++
> 1 file changed, 89 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/sound/st,stm32-sai.txt
>
> diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.txt b/Documentation/devicetree/bindings/sound/st,stm32-sai.txt
> new file mode 100644
> index 0000000..c59a3d7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.txt
> @@ -0,0 +1,89 @@
> +STMicroelectronics STM32 Serial Audio Interface (SAI).
[...]
> + sai1b: audio-controller@40015824 {
> + #sound-dai-cells = <0>;
> + compatible = "st,stm32-sai-sub-b";
> + reg = <0x40015824 0x1C>;
> + clocks = <&rcc 1 CLK_SAI2>;
> + clock-names = "sai_ck";
> + dmas = <&dma2 5 0 0x400 0x0>;
> + dma-names = "tx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sai1b>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + sai1b_port: port@0 {
> + reg = <0>;
> + cpu_endpoint: endpoint {
> + remote-endpoint = <&codec_endpoint>;
> + audio-graph-card,format = "i2s";
> + audio-graph-card,bitclock-master = <&codec_endpoint>;
> + audio-graph-card,frame-master = <&codec_endpoint>;
These property names are wrong.
> + };
> + };
> + };
> + };
> +};
> +
> +audio-codec {
> + codec_port: port {
> + codec_endpoint: endpoint {
> + remote-endpoint = <&cpu_endpoint>;
> + };
> + };
> +};
> --
> 1.9.1
>
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^ permalink raw reply
* Re: [PATCH 1/9] usb: host: add DT bindings for faraday fotg2
From: Rob Herring @ 2017-04-28 20:58 UTC (permalink / raw)
To: Hans Ulli Kroll
Cc: Linus Walleij, devicetree-u79uwXL29TY76Z2rM5mHXA, Linus Walleij
In-Reply-To: <20170426194120.26304-2-ulli.kroll-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
On Wed, Apr 26, 2017 at 09:41:12PM +0200, Hans Ulli Kroll wrote:
> This adds device tree bindings for the Faraday FOTG2
> dual-mode host controller.
>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Hans Ulli Kroll <ulli.kroll-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> .../devicetree/bindings/usb/faraday,fotg210.txt | 40 ++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/faraday,fotg210.txt
>
> diff --git a/Documentation/devicetree/bindings/usb/faraday,fotg210.txt b/Documentation/devicetree/bindings/usb/faraday,fotg210.txt
> new file mode 100644
> index 000000000000..dc2cdaf20d9f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/faraday,fotg210.txt
> @@ -0,0 +1,40 @@
> +Faraday FOTG Dual role controller
> +
> +This OTG-capable host/device mode USB controller is found in Cortina Systems
> +Gemini and other SoC products.
> +On Gemini currently host mode is used
> +
> +Required properties:
> +- compatible: should be one of:
> + "faraday,fotg210-dr"
> + "cortina,gemini-usb", "faraday,fotg210-dr"
> +- reg: should contain one register range i.e. start and length
> +- interrupts: description of the interrupt line
> +
> +Optional properties:
> +- clocks: should contain the IP block clock
> +- clock-names: should be "PCLK" for the IP block clock
> +- dr_mode : indicates the working mode for "faraday,fotg210-dr" compatible
> + controllers. Can be "host" or "peripheral"
> + Default to "host" if not defined for backward compatibility.
> +
> +
> +Required properties for "cortina,gemini-usb" compatible:
> +- syscon: a phandle to the system controller to access PHY registers
> +
> +Optional properties for "cortina,gemini-usb" compatible:
> +- cortina,gemini-mini-b: boolean property that indicates that a Mini-B
> + OTH connector is in use
s/OTH/OTG/
With that,
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v5 04/10] dt-bindings: pinctrl: Add RZ/A1 bindings doc
From: Rob Herring @ 2017-04-28 21:03 UTC (permalink / raw)
To: Jacopo Mondi
Cc: linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw,
chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ, mark.rutland-5wv7dgnIgG8,
linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1493281194-5200-5-git-send-email-jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
On Thu, Apr 27, 2017 at 10:19:48AM +0200, Jacopo Mondi wrote:
> Add device tree bindings documentation for Renesas RZ/A1 gpio and pin
> controller.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
> ---
> .../bindings/pinctrl/renesas,rza1-pinctrl.txt | 219 +++++++++++++++++++++
> 1 file changed, 219 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v1 2/2] dt-bindings: pcie: Add documentation for Mediatek PCIe
From: Rob Herring @ 2017-04-28 21:09 UTC (permalink / raw)
To: Ryder Lee
Cc: Bjorn Helgaas, Arnd Bergmann, linux-pci-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Red Hung
In-Reply-To: <1493370634-7038-3-git-send-email-ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Fri, Apr 28, 2017 at 05:10:34PM +0800, Ryder Lee wrote:
> Add binding document for Mediatek PCIe Gen2 v1 host controller driver.
>
> Signed-off-by: Ryder Lee <ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> .../bindings/pci/mediatek,gen2v1-pcie.txt | 174 +++++++++++++++++++++
> 1 file changed, 174 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> new file mode 100644
> index 0000000..545d8cf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> @@ -0,0 +1,174 @@
> +Mediatek Gen2 V1 PCIe controller
> +
> +PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
> +ports supports a Gen2 1-lane Link. It includes one Host/PCI bridge and 3
> +PCIe MAC. Each port has PIPE interface to PHY. There are 3 bus master for
> +data access and 1 bus slave for Configuration and Status Register access.
> +
> +This controller is available on MT7623 series SoCs.
> +
> +Required properties:
> +- compatible: Should contain "mediatek,gen2v1-pcie".
> +- device_type: Must be "pci"
> +- reg: Base addresses and lengths of the PCIe controller.
> +- #address-cells: Address representation for root ports (must be 3)
> + - cell 0 specifies the bus and device numbers of the root port:
> + [23:16]: bus number
> + [15:11]: device number
> + - cell 1 denotes the upper 32 address bits and should be 0
> + - cell 2 contains the lower 32 address bits and is used to translate to the
> + CPU address space
This is all standard PCI bus binding. You don't need to define it here.
"must be 3" is sufficient.
> +- #size-cells: Size representation for root ports (must be 2)
> +- #interrupt-cells: Size representation for interrupts (must be 1)
> +- interrupts: Three interrupt outputs of the controller. Must contain an
> + entry for each entry in the interrupt-names property.
Where's interrupt-names?
> +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
> + Please refer to the standard PCI bus binding document for a more detailed
> + explanation.
> +- clocks: Must contain an entry for each entry in clock-names.
> + See ../clocks/clock-bindings.txt for details.
> +- clock-names: Must include the following entries:
> + - free_ck :for reference clock of PCIe subsys
> + - sys_ck0 :for clock of Port0 MAC
> + - sys_ck1 :for clock of Port1 MAC
> + - sys_ck2 :for clock of Port2 MAC
> +- resets: Must contain an entry for each entry in reset-names.
> + See ../reset/reset.txt for details.
> +- reset-names: Must include the following entries:
> + - pcie-rst0 :port0 reset
> + - pcie-rst1 :port1 reset
> + - pcie-rst2 :port2 reset
> +- phys: list of PHY specifiers (used by generic PHY framework)
> +- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
> + number of PHYs as specified in *phys* property.
> +- power-domains: A phandle and power domain specifier pair to the power domain
> + which is responsible for collapsing and restoring power to the peripheral
> +- bus-range: Range of bus numbers associated with this controller
> +- ranges: Describes the translation of addresses for root ports and standard
> + PCI regions. The entries must be 6 cells each, where the first three cells
> + correspond to the address as described for the #address-cells property
> + above, the fourth cell is the physical CPU address to translate to and the
> + fifth and six cells are as described for the #size-cells property above.
Don't need to define what ranges is here, just what the entries should
be:
> + - The first three entries are expected to translate the addresses for the root
> + port registers, which are referenced by the assigned-addresses property of
> + the root port nodes (see below).
> + - The remaining entries setup the mapping for the standard I/O and memory
> + regions.
> + Please refer to the standard PCI bus binding document for a more detailed
> + explanation.
> +
> +In addition, the device tree node must have sub-nodes describing each
> +PCIe port interface, having the following mandatory properties:
> +
> +Required properties:
> +- device_type: Must be "pci"
> +- assigned-addresses: Address and size of the port configuration registers
> +- reg: Only the first four bytes are used to refer to the correct bus number
> + and device number.
> +- #address-cells: Must be 3
> +- #size-cells: Must be 2
> +- #interrupt-cells: Size representation for interrupts (must be 1)
> +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
> + Please refer to the standard PCI bus binding document for a more detailed
> + explanation.
> +- ranges: Sub-ranges distributed from the PCIe controller node. An empty
> + property is sufficient.
> +- num-lanes: Number of lanes to use for this port.
> +
> +Examples:
> +
> +SoC dtsi:
Don't show the board vs. SoC split in examples. And drop all the status
properties.
> +
> + hifsys: syscon@1a000000 {
> + compatible = "mediatek,mt7623-hifsys", "syscon";
> + reg = <0 0x1a000000 0 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + pcie: pcie-controller@1a140000 {
> + compatible = "mediatek,gen2v1-pcie";
> + device_type = "pci";
> + reg = <0 0x1a140000 0 0x1000>; /* PCIe shared registers */
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-map-mask = <0xf800 0 0 0>;
> + interrupt-map = <0x0000 0 0 0 &gic GIC_SPI 193 IRQ_TYPE_NONE>,
> + <0x0800 0 0 0 &gic GIC_SPI 194 IRQ_TYPE_NONE>,
> + <0x1000 0 0 0 &gic GIC_SPI 195 IRQ_TYPE_NONE>;
> + clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
> + <&hifsys CLK_HIFSYS_PCIE0>,
> + <&hifsys CLK_HIFSYS_PCIE1>,
> + <&hifsys CLK_HIFSYS_PCIE2>;
> + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
> + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
> + <&hifsys MT2701_HIFSYS_PCIE1_RST>,
> + <&hifsys MT2701_HIFSYS_PCIE2_RST>;
> + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
> + phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>;
> + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
> + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
> + bus-range = <0x00 0xff>;
> + ranges = <0x82000000 0 0x1a142000 0 0x1a142000 0 0x1000 /* Port0 registers */
> + 0x82000000 0 0x1a143000 0 0x1a143000 0 0x1000 /* Port1 registers */
> + 0x82000000 0 0x1a144000 0 0x1a144000 0 0x1000 /* Port2 registers */
> + 0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
> + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
> + status = "disabled";
> +
> + pcie@1,0 {
> + device_type = "pci";
> + assigned-addresses = <0x82000000 0 0x1a142000 0 0x1000>;
> + reg = <0x0000 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 193 IRQ_TYPE_NONE>;
> + ranges;
> + num-lanes = <1>;
> + status = "disabled";
> + };
> +
> + pcie@2,0 {
> + device_type = "pci";
> + assigned-addresses = <0x82000800 0 0x1a143000 0 0x1000>;
> + reg = <0x0800 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 194 IRQ_TYPE_NONE>;
> + ranges;
> + num-lanes = <1>;
> + status = "disabled";
> + };
> +
> + pcie@3,0 {
> + device_type = "pci";
> + assigned-addresses = <0x82001000 0 0x1a144000 0 0x1000>;
> + reg = <0x1000 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 195 IRQ_TYPE_NONE>;
> + ranges;
> + num-lanes = <1>;
> + status = "disabled";
> + };
> + };
> +
> +Board dts:
> +
> + &pcie {
> + status = "okay";
> +
> + pcie@1,0 {
> + status = "okay";
> + };
> + };
> --
> 1.9.1
>
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^ permalink raw reply
* Re: [PATCH 2/2] of: fix unittest build without CONFIG_OF_OVERLAY
From: Rob Herring @ 2017-04-28 21:18 UTC (permalink / raw)
To: Frank Rowand
Cc: Arnd Bergmann, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <59036282.3050502-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Fri, Apr 28, 2017 at 08:40:50AM -0700, Frank Rowand wrote:
> On 04/28/17 02:44, Arnd Bergmann wrote:
> > We get a link error when the new tests are used by overlays
> > are not:
> >
> > drivers/of/built-in.o: In function `unflatten_device_tree':
> > (.init.text+0x967): undefined reference to `unittest_unflatten_overlay_base'
> >
> > This makes the #ifdef check match the symbols that lead to building
> > the unittest_unflatten_overlay_base function.
> >
> > Fixes: 81d0848fc8d2 ("of: Add unit tests for applying overlays")
> > Signed-off-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
> > ---
> > drivers/of/of_private.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h
> > index de5c604f5cc4..4ebb0149d118 100644
> > --- a/drivers/of/of_private.h
> > +++ b/drivers/of/of_private.h
> > @@ -55,7 +55,7 @@ static inline int of_property_notify(int action, struct device_node *np,
> > }
> > #endif /* CONFIG_OF_DYNAMIC */
> >
> > -#ifdef CONFIG_OF_UNITTEST
> > +#if defined(CONFIG_OF_UNITTEST) && defined(CONFIG_OF_OVERLAY)
> > extern void __init unittest_unflatten_overlay_base(void);
> > #else
> > static inline void unittest_unflatten_overlay_base(void) {};
> >
>
> I thought I had tested that OF_UNITTEST forced OF_OVERLAY. But
> going back and trying again, I can confirm your results that it
> does not. Thanks for catching this!
>
> Reviewed-by: Frank Rowand <frank.rowand-7U/KSKJipcs@public.gmane.org>
> Tested-by: Frank Rowand <frank.rowand-7U/KSKJipcs@public.gmane.org>
Both applied, thanks.
Rob
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^ permalink raw reply
* Re: [PATCH 1/3 v3] drm/vc4: Turn the V3D clock on at runtime.
From: Eric Anholt @ 2017-04-28 21:41 UTC (permalink / raw)
To: Rob Herring; +Cc: Mark Rutland, devicetree, linux-kernel, dri-devel
In-Reply-To: <20170428182913.pv73xj45onxlnd3c@rob-hp-laptop>
[-- Attachment #1.1: Type: text/plain, Size: 1608 bytes --]
Rob Herring <robh@kernel.org> writes:
> On Mon, Apr 24, 2017 at 01:12:09PM -0700, Eric Anholt wrote:
>> For the Raspberry Pi's bindings, the power domain also implicitly
>> turns on the clock and deasserts reset, but for the new Cygnus port we
>> start representing the clock in the devicetree.
>>
>> v2: Document the clock-names property, check for -ENOENT for no clock
>> in DT.
>> v3: Drop NULL checks around clk calls which embed NULL checks.
>>
>> Signed-off-by: Eric Anholt <eric@anholt.net>
>> ---
>> .../devicetree/bindings/display/brcm,bcm-vc4.txt | 4 +++
>> drivers/gpu/drm/vc4/vc4_drv.h | 1 +
>> drivers/gpu/drm/vc4/vc4_v3d.c | 31 +++++++++++++++++++++-
>> 3 files changed, 35 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt b/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
>> index ca02d3e4db91..2318266f6481 100644
>> --- a/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
>> +++ b/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
>> @@ -59,6 +59,10 @@ Required properties for V3D:
>> - interrupts: The interrupt number
>> See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
>>
>> +Optional properties for V3D:
>> +- clocks: The clock the unit runs on
>> +- clock-names: Must be "v3d_clk"
>
> clock-names is pointless for a single clock.
I thought the "-names" was the current style of future-proofing against
finding another clock to put in the list. If I drop it, is the DT
change acked?
[-- Attachment #1.2: signature.asc --]
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^ permalink raw reply
* [PATCH v3 1/2] net: dsa: b53: Add compatible strings for the Cygnus-family BCM11360.
From: Eric Anholt @ 2017-04-28 22:22 UTC (permalink / raw)
To: Florian Fainelli, Vivien Didelot, Andrew Lunn, netdev,
Rob Herring, Mark Rutland, devicetree
Cc: linux-arm-kernel, linux-kernel, bcm-kernel-feedback-list, Ray Jui,
Scott Branden, Jon Mason, Eric Anholt
Cygnus is a small family of SoCs, of which we currently have
devicetree for BCM11360 and BCM58300. The 11360's B53 is mostly the
same as 58xx, just requiring a tiny bit of setup that was previously
missing.
v2: Reorder the entry in the docs (suggestion by Scott Branden), add
missing '"'
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/net/dsa/b53.txt | 3 +++
drivers/net/dsa/b53/b53_srab.c | 2 ++
2 files changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/b53.txt b/Documentation/devicetree/bindings/net/dsa/b53.txt
index d6c6e41648d4..eb679e92d525 100644
--- a/Documentation/devicetree/bindings/net/dsa/b53.txt
+++ b/Documentation/devicetree/bindings/net/dsa/b53.txt
@@ -13,6 +13,9 @@ Required properties:
"brcm,bcm5397"
"brcm,bcm5398"
+ For the BCM11360 SoC, must be:
+ "brcm,bcm11360-srab" and the mandatory "brcm,cygnus-srab" string
+
For the BCM5310x SoCs with an integrated switch, must be one of:
"brcm,bcm53010-srab"
"brcm,bcm53011-srab"
diff --git a/drivers/net/dsa/b53/b53_srab.c b/drivers/net/dsa/b53/b53_srab.c
index 8a62b6a69703..c37ffd1b6833 100644
--- a/drivers/net/dsa/b53/b53_srab.c
+++ b/drivers/net/dsa/b53/b53_srab.c
@@ -364,6 +364,7 @@ static const struct of_device_id b53_srab_of_match[] = {
{ .compatible = "brcm,bcm53018-srab" },
{ .compatible = "brcm,bcm53019-srab" },
{ .compatible = "brcm,bcm5301x-srab" },
+ { .compatible = "brcm,bcm11360-srab", .data = (void *)BCM58XX_DEVICE_ID },
{ .compatible = "brcm,bcm58522-srab", .data = (void *)BCM58XX_DEVICE_ID },
{ .compatible = "brcm,bcm58525-srab", .data = (void *)BCM58XX_DEVICE_ID },
{ .compatible = "brcm,bcm58535-srab", .data = (void *)BCM58XX_DEVICE_ID },
@@ -371,6 +372,7 @@ static const struct of_device_id b53_srab_of_match[] = {
{ .compatible = "brcm,bcm58623-srab", .data = (void *)BCM58XX_DEVICE_ID },
{ .compatible = "brcm,bcm58625-srab", .data = (void *)BCM58XX_DEVICE_ID },
{ .compatible = "brcm,bcm88312-srab", .data = (void *)BCM58XX_DEVICE_ID },
+ { .compatible = "brcm,cygnus-srab", .data = (void *)BCM58XX_DEVICE_ID },
{ .compatible = "brcm,nsp-srab", .data = (void *)BCM58XX_DEVICE_ID },
{ /* sentinel */ },
};
--
2.11.0
^ permalink raw reply related
* [PATCH v3 2/2] ARM: dts: Add the ethernet and ethernet PHY to the cygnus core DT.
From: Eric Anholt @ 2017-04-28 22:22 UTC (permalink / raw)
To: Florian Fainelli, Vivien Didelot, Andrew Lunn, netdev,
Rob Herring, Mark Rutland, devicetree
Cc: linux-arm-kernel, linux-kernel, bcm-kernel-feedback-list, Ray Jui,
Scott Branden, Jon Mason, Eric Anholt
In-Reply-To: <20170428222204.7103-1-eric@anholt.net>
Cygnus has a single amac controller connected to the B53 switch with 2
PHYs. On the BCM911360_EP platform, those two PHYs are connected to
the external ethernet jacks.
v2: Call the node "switch", just call the ports "port" (suggestions by
Florian), drop max-speed on the phys (suggestion by Andrew Lunn),
call the other nodes "ethernet" and "ethernet-phy" (suggestions by
Sergei Shtylyov)
v3: Drop another max-speed (Andrew), keep mdio disabled in the shared
dtsi (Florian)
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 58 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm911360_entphn.dts | 12 +++++++
2 files changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 34603bfed46a..687f5fe8aa0f 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -142,6 +142,55 @@
interrupts = <0>;
};
+ mdio: mdio@18002000 {
+ compatible = "brcm,iproc-mdio";
+ reg = <0x18002000 0x8>;
+ #size-cells = <1>;
+ #address-cells = <0>;
+ status = "disabled";
+
+ gphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ gphy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+
+ switch: switch@18007000 {
+ compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab";
+ reg = <0x18007000 0x1000>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ phy-handle = <&gphy0>;
+ phy-mode = "rgmii";
+ };
+
+ port@1 {
+ reg = <1>;
+ phy-handle = <&gphy1>;
+ phy-mode = "rgmii";
+ };
+
+ port@8 {
+ reg = <8>;
+ label = "cpu";
+ ethernet = <ð0>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
i2c0: i2c@18008000 {
compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
reg = <0x18008000 0x100>;
@@ -295,6 +344,15 @@
status = "disabled";
};
+ eth0: ethernet@18042000 {
+ compatible = "brcm,amac";
+ reg = <0x18042000 0x1000>,
+ <0x18110000 0x1000>;
+ reg-names = "amac_base", "idm_base";
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
nand: nand@18046000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x18046000 0x600>, <0xf8105408 0x600>,
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
index 037621c13290..000f5f19215e 100644
--- a/arch/arm/boot/dts/bcm911360_entphn.dts
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -57,6 +57,18 @@
};
};
+ð0 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+};
+
+&switch {
+ status = "okay";
+};
+
&v3d {
assigned-clocks =
<&mipipll BCM_CYGNUS_MIPIPLL>,
--
2.11.0
^ permalink raw reply related
* [PATCH v4 1/3] drm/vc4: Turn the V3D clock on at runtime.
From: Eric Anholt @ 2017-04-28 22:42 UTC (permalink / raw)
To: dri-devel, Rob Herring, Mark Rutland, devicetree; +Cc: linux-kernel
For the Raspberry Pi's bindings, the power domain also implicitly
turns on the clock and deasserts reset, but for the new Cygnus port we
start representing the clock in the devicetree.
v2: Document the clock-names property, check for -ENOENT for no clock
in DT.
v3: Drop NULL checks around clk calls which embed NULL checks.
v4: Drop clk-names (feedback by Rob Herring)
Signed-off-by: Eric Anholt <eric@anholt.net>
---
.../devicetree/bindings/display/brcm,bcm-vc4.txt | 3 +++
drivers/gpu/drm/vc4/vc4_drv.h | 1 +
drivers/gpu/drm/vc4/vc4_v3d.c | 31 +++++++++++++++++++++-
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt b/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
index ca02d3e4db91..bc1756f4f791 100644
--- a/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
+++ b/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
@@ -59,6 +59,9 @@ Required properties for V3D:
- interrupts: The interrupt number
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+Optional properties for V3D:
+- clocks: The clock the unit runs on
+
Required properties for DSI:
- compatible: Should be "brcm,bcm2835-dsi0" or "brcm,bcm2835-dsi1"
- reg: Physical base address and length of the DSI block's registers
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index b0967e2f7e88..92eb7d811bf2 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -200,6 +200,7 @@ struct vc4_v3d {
struct vc4_dev *vc4;
struct platform_device *pdev;
void __iomem *regs;
+ struct clk *clk;
};
struct vc4_hvs {
diff --git a/drivers/gpu/drm/vc4/vc4_v3d.c b/drivers/gpu/drm/vc4/vc4_v3d.c
index a88078d7c9d1..7500820e5cd5 100644
--- a/drivers/gpu/drm/vc4/vc4_v3d.c
+++ b/drivers/gpu/drm/vc4/vc4_v3d.c
@@ -16,6 +16,7 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#include "linux/clk.h"
#include "linux/component.h"
#include "linux/pm_runtime.h"
#include "vc4_drv.h"
@@ -305,6 +306,8 @@ static int vc4_v3d_runtime_suspend(struct device *dev)
drm_gem_object_put_unlocked(&vc4->bin_bo->base.base);
vc4->bin_bo = NULL;
+ clk_disable_unprepare(v3d->clk);
+
return 0;
}
@@ -318,6 +321,10 @@ static int vc4_v3d_runtime_resume(struct device *dev)
if (ret)
return ret;
+ ret = clk_prepare_enable(v3d->clk);
+ if (ret != 0)
+ return ret;
+
vc4_v3d_init_hw(vc4->dev);
vc4_irq_postinstall(vc4->dev);
@@ -348,15 +355,37 @@ static int vc4_v3d_bind(struct device *dev, struct device *master, void *data)
vc4->v3d = v3d;
v3d->vc4 = vc4;
+ v3d->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(v3d->clk)) {
+ int ret = PTR_ERR(v3d->clk);
+
+ if (ret == -ENOENT) {
+ /* bcm2835 didn't have a clock reference in the DT. */
+ ret = 0;
+ v3d->clk = NULL;
+ } else {
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to get V3D clock: %d\n",
+ ret);
+ return ret;
+ }
+ }
+
if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) {
DRM_ERROR("V3D_IDENT0 read 0x%08x instead of 0x%08x\n",
V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0);
return -EINVAL;
}
+ ret = clk_prepare_enable(v3d->clk);
+ if (ret != 0)
+ return ret;
+
ret = vc4_allocate_bin_bo(drm);
- if (ret)
+ if (ret) {
+ clk_disable_unprepare(v3d->clk);
return ret;
+ }
/* Reset the binner overflow address/size at setup, to be sure
* we don't reuse an old one.
--
2.11.0
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