* [PATCH v3 1/3] media: V3s: Add support for Allwinner CSI.
From: Yong Deng @ 2017-11-13 7:30 UTC (permalink / raw)
To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8
Cc: Yong Deng, Mauro Carvalho Chehab, Rob Herring, Mark Rutland,
Chen-Yu Tsai, David S. Miller, Greg Kroah-Hartman, Hans Verkuil,
Randy Dunlap, Benoit Parrot, Stanimir Varbanov, Arnd Bergmann,
Hugues Fruchet, Philipp Zabel, Benjamin Gaignard,
Ramesh Shanmugasundaram, Yannick Fertre, Sakari Ailus, Rick Chang,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
and CSI1 is used for parallel interface. This is not documented in
datasheet but by testing and guess.
This patch implement a v4l2 framework driver for it.
Currently, the driver only support the parallel interface. MIPI-CSI2,
ISP's support are not included in this patch.
Signed-off-by: Yong Deng <yong.deng-+3dxTMOEIRNWk0Htik3J/w@public.gmane.org>
---
drivers/media/platform/Kconfig | 1 +
drivers/media/platform/Makefile | 2 +
drivers/media/platform/sunxi/sun6i-csi/Kconfig | 9 +
drivers/media/platform/sunxi/sun6i-csi/Makefile | 3 +
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 918 +++++++++++++++++++++
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h | 146 ++++
.../media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h | 203 +++++
.../media/platform/sunxi/sun6i-csi/sun6i_video.c | 722 ++++++++++++++++
.../media/platform/sunxi/sun6i-csi/sun6i_video.h | 61 ++
9 files changed, 2065 insertions(+)
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/Kconfig
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/Makefile
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/sun6i_video.c
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/sun6i_video.h
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index fd0c998..41017e3 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -150,6 +150,7 @@ source "drivers/media/platform/am437x/Kconfig"
source "drivers/media/platform/xilinx/Kconfig"
source "drivers/media/platform/rcar-vin/Kconfig"
source "drivers/media/platform/atmel/Kconfig"
+source "drivers/media/platform/sunxi/sun6i-csi/Kconfig"
config VIDEO_TI_CAL
tristate "TI CAL (Camera Adaptation Layer) driver"
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index 012eb47..1cc806a 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -96,3 +96,5 @@ obj-$(CONFIG_VIDEO_QCOM_CAMSS) += qcom/camss-8x16/
obj-$(CONFIG_VIDEO_QCOM_VENUS) += qcom/venus/
obj-y += meson/
+
+obj-$(CONFIG_VIDEO_SUN6I_CSI) += sunxi/sun6i-csi/
diff --git a/drivers/media/platform/sunxi/sun6i-csi/Kconfig b/drivers/media/platform/sunxi/sun6i-csi/Kconfig
new file mode 100644
index 0000000..314188a
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-csi/Kconfig
@@ -0,0 +1,9 @@
+config VIDEO_SUN6I_CSI
+ tristate "Allwinner V3s Camera Sensor Interface driver"
+ depends on VIDEO_V4L2 && COMMON_CLK && VIDEO_V4L2_SUBDEV_API && HAS_DMA
+ depends on ARCH_SUNXI || COMPILE_TEST
+ select VIDEOBUF2_DMA_CONTIG
+ select REGMAP_MMIO
+ select V4L2_FWNODE
+ ---help---
+ Support for the Allwinner Camera Sensor Interface Controller on V3s.
diff --git a/drivers/media/platform/sunxi/sun6i-csi/Makefile b/drivers/media/platform/sunxi/sun6i-csi/Makefile
new file mode 100644
index 0000000..213cb6b
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-csi/Makefile
@@ -0,0 +1,3 @@
+sun6i-csi-y += sun6i_video.o sun6i_csi.o
+
+obj-$(CONFIG_VIDEO_SUN6I_CSI) += sun6i-csi.o
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
new file mode 100644
index 0000000..3f4de09
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -0,0 +1,918 @@
+/*
+ * Copyright (c) 2017 Magewell Electronics Co., Ltd. (Nanjing).
+ * All rights reserved.
+ * Author: Yong Deng <yong.deng-+3dxTMOEIRNWk0Htik3J/w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ioctl.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/sched.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+
+#include "sun6i_csi.h"
+#include "sun6i_csi_reg.h"
+
+#define MODULE_NAME "sun6i-csi"
+
+struct sun6i_csi_dev {
+ struct sun6i_csi csi;
+ struct device *dev;
+
+ struct regmap *regmap;
+ struct clk *clk_mod;
+ struct clk *clk_ram;
+ struct reset_control *rstc_bus;
+
+ int planar_offset[3];
+};
+
+static const u32 supported_pixformats[] = {
+ V4L2_PIX_FMT_SBGGR8,
+ V4L2_PIX_FMT_SGBRG8,
+ V4L2_PIX_FMT_SGRBG8,
+ V4L2_PIX_FMT_SRGGB8,
+ V4L2_PIX_FMT_SBGGR10,
+ V4L2_PIX_FMT_SGBRG10,
+ V4L2_PIX_FMT_SGRBG10,
+ V4L2_PIX_FMT_SRGGB10,
+ V4L2_PIX_FMT_SBGGR12,
+ V4L2_PIX_FMT_SGBRG12,
+ V4L2_PIX_FMT_SGRBG12,
+ V4L2_PIX_FMT_SRGGB12,
+ V4L2_PIX_FMT_YUYV,
+ V4L2_PIX_FMT_YVYU,
+ V4L2_PIX_FMT_UYVY,
+ V4L2_PIX_FMT_VYUY,
+ V4L2_PIX_FMT_HM12,
+ V4L2_PIX_FMT_NV12,
+ V4L2_PIX_FMT_NV21,
+ V4L2_PIX_FMT_YUV420,
+ V4L2_PIX_FMT_YVU420,
+ V4L2_PIX_FMT_NV16,
+ V4L2_PIX_FMT_NV61,
+ V4L2_PIX_FMT_YUV422P,
+};
+
+static inline struct sun6i_csi_dev *sun6i_csi_to_dev(struct sun6i_csi *csi)
+{
+ return container_of(csi, struct sun6i_csi_dev, csi);
+}
+
+/* TODO add 10&12 bit YUV, RGB support */
+static bool __is_format_support(struct sun6i_csi_dev *sdev,
+ u32 fourcc, u32 mbus_code)
+{
+ /*
+ * Some video receiver have capability both 8bit and 16bit.
+ * Identify the media bus format from device tree.
+ */
+ if ((sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_PARALLEL
+ || sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_BT656)
+ && sdev->csi.v4l2_ep.bus.parallel.bus_width == 16) {
+ switch (fourcc) {
+ case V4L2_PIX_FMT_HM12:
+ case V4L2_PIX_FMT_NV12:
+ case V4L2_PIX_FMT_NV21:
+ case V4L2_PIX_FMT_NV16:
+ case V4L2_PIX_FMT_NV61:
+ case V4L2_PIX_FMT_YUV420:
+ case V4L2_PIX_FMT_YVU420:
+ case V4L2_PIX_FMT_YUV422P:
+ switch (mbus_code) {
+ case MEDIA_BUS_FMT_UYVY8_1X16:
+ case MEDIA_BUS_FMT_VYUY8_1X16:
+ case MEDIA_BUS_FMT_YUYV8_1X16:
+ case MEDIA_BUS_FMT_YVYU8_1X16:
+ return true;
+ }
+ break;
+ }
+ return false;
+ }
+
+ switch (fourcc) {
+ case V4L2_PIX_FMT_SBGGR8:
+ if (mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
+ return true;
+ break;
+ case V4L2_PIX_FMT_SGBRG8:
+ if (mbus_code == MEDIA_BUS_FMT_SGBRG8_1X8)
+ return true;
+ break;
+ case V4L2_PIX_FMT_SGRBG8:
+ if (mbus_code == MEDIA_BUS_FMT_SGRBG8_1X8)
+ return true;
+ break;
+ case V4L2_PIX_FMT_SRGGB8:
+ if (mbus_code == MEDIA_BUS_FMT_SRGGB8_1X8)
+ return true;
+ break;
+ case V4L2_PIX_FMT_SBGGR10:
+ if (mbus_code == MEDIA_BUS_FMT_SBGGR10_1X10)
+ return true;
+ break;
+ case V4L2_PIX_FMT_SGBRG10:
+ if (mbus_code == MEDIA_BUS_FMT_SGBRG10_1X10)
+ return true;
+ break;
+ case V4L2_PIX_FMT_SGRBG10:
+ if (mbus_code == MEDIA_BUS_FMT_SGRBG10_1X10)
+ return true;
+ break;
+ case V4L2_PIX_FMT_SRGGB10:
+ if (mbus_code == MEDIA_BUS_FMT_SRGGB10_1X10)
+ return true;
+ break;
+ case V4L2_PIX_FMT_SBGGR12:
+ if (mbus_code == MEDIA_BUS_FMT_SBGGR12_1X12)
+ return true;
+ break;
+ case V4L2_PIX_FMT_SGBRG12:
+ if (mbus_code == MEDIA_BUS_FMT_SGBRG12_1X12)
+ return true;
+ break;
+ case V4L2_PIX_FMT_SGRBG12:
+ if (mbus_code == MEDIA_BUS_FMT_SGRBG12_1X12)
+ return true;
+ break;
+ case V4L2_PIX_FMT_SRGGB12:
+ if (mbus_code == MEDIA_BUS_FMT_SRGGB12_1X12)
+ return true;
+ break;
+
+ case V4L2_PIX_FMT_YUYV:
+ if (mbus_code == MEDIA_BUS_FMT_YUYV8_2X8)
+ return true;
+ break;
+ case V4L2_PIX_FMT_YVYU:
+ if (mbus_code == MEDIA_BUS_FMT_YVYU8_2X8)
+ return true;
+ break;
+ case V4L2_PIX_FMT_UYVY:
+ if (mbus_code == MEDIA_BUS_FMT_UYVY8_2X8)
+ return true;
+ break;
+ case V4L2_PIX_FMT_VYUY:
+ if (mbus_code == MEDIA_BUS_FMT_VYUY8_2X8)
+ return true;
+ break;
+
+ case V4L2_PIX_FMT_HM12:
+ case V4L2_PIX_FMT_NV12:
+ case V4L2_PIX_FMT_NV21:
+ case V4L2_PIX_FMT_NV16:
+ case V4L2_PIX_FMT_NV61:
+ case V4L2_PIX_FMT_YUV420:
+ case V4L2_PIX_FMT_YVU420:
+ case V4L2_PIX_FMT_YUV422P:
+ switch (mbus_code) {
+ case MEDIA_BUS_FMT_UYVY8_2X8:
+ case MEDIA_BUS_FMT_VYUY8_2X8:
+ case MEDIA_BUS_FMT_YUYV8_2X8:
+ case MEDIA_BUS_FMT_YVYU8_2X8:
+ return true;
+ }
+ break;
+ }
+
+ return false;
+}
+
+static enum csi_input_fmt get_csi_input_format(u32 mbus_code, u32 pixformat)
+{
+ /* bayer */
+ if ((mbus_code & 0xF000) == 0x3000)
+ return CSI_INPUT_FORMAT_RAW;
+
+ switch (pixformat) {
+ case V4L2_PIX_FMT_YUYV:
+ case V4L2_PIX_FMT_YVYU:
+ case V4L2_PIX_FMT_UYVY:
+ case V4L2_PIX_FMT_VYUY:
+ return CSI_INPUT_FORMAT_RAW;
+ }
+
+ /* not support YUV420 input format yet */
+ return CSI_INPUT_FORMAT_YUV422;
+}
+
+static enum csi_output_fmt get_csi_output_format(u32 pixformat, u32 field)
+{
+ bool buf_interlaced = false;
+
+ if (field == V4L2_FIELD_INTERLACED
+ || field == V4L2_FIELD_INTERLACED_TB
+ || field == V4L2_FIELD_INTERLACED_BT)
+ buf_interlaced = true;
+
+ switch (pixformat) {
+ case V4L2_PIX_FMT_SBGGR8:
+ case V4L2_PIX_FMT_SGBRG8:
+ case V4L2_PIX_FMT_SGRBG8:
+ case V4L2_PIX_FMT_SRGGB8:
+ return buf_interlaced ? CSI_FRAME_RAW_8 : CSI_FIELD_RAW_8;
+ case V4L2_PIX_FMT_SBGGR10:
+ case V4L2_PIX_FMT_SGBRG10:
+ case V4L2_PIX_FMT_SGRBG10:
+ case V4L2_PIX_FMT_SRGGB10:
+ return buf_interlaced ? CSI_FRAME_RAW_10 : CSI_FIELD_RAW_10;
+ case V4L2_PIX_FMT_SBGGR12:
+ case V4L2_PIX_FMT_SGBRG12:
+ case V4L2_PIX_FMT_SGRBG12:
+ case V4L2_PIX_FMT_SRGGB12:
+ return buf_interlaced ? CSI_FRAME_RAW_12 : CSI_FIELD_RAW_12;
+
+ case V4L2_PIX_FMT_YUYV:
+ case V4L2_PIX_FMT_YVYU:
+ case V4L2_PIX_FMT_UYVY:
+ case V4L2_PIX_FMT_VYUY:
+ return buf_interlaced ? CSI_FRAME_RAW_8 : CSI_FIELD_RAW_8;
+
+ case V4L2_PIX_FMT_HM12:
+ return buf_interlaced ? CSI_FRAME_MB_YUV420 :
+ CSI_FIELD_MB_YUV420;
+ case V4L2_PIX_FMT_NV12:
+ case V4L2_PIX_FMT_NV21:
+ return buf_interlaced ? CSI_FRAME_UV_CB_YUV420 :
+ CSI_FIELD_UV_CB_YUV420;
+ case V4L2_PIX_FMT_YUV420:
+ case V4L2_PIX_FMT_YVU420:
+ return buf_interlaced ? CSI_FRAME_PLANAR_YUV420 :
+ CSI_FIELD_PLANAR_YUV420;
+ case V4L2_PIX_FMT_NV16:
+ case V4L2_PIX_FMT_NV61:
+ return buf_interlaced ? CSI_FRAME_UV_CB_YUV422 :
+ CSI_FIELD_UV_CB_YUV422;
+ case V4L2_PIX_FMT_YUV422P:
+ return buf_interlaced ? CSI_FRAME_PLANAR_YUV422 :
+ CSI_FIELD_PLANAR_YUV422;
+ }
+
+ return 0;
+}
+
+static enum csi_input_seq get_csi_input_seq(u32 mbus_code, u32 pixformat)
+{
+
+ switch (pixformat) {
+ case V4L2_PIX_FMT_HM12:
+ case V4L2_PIX_FMT_NV12:
+ case V4L2_PIX_FMT_NV16:
+ case V4L2_PIX_FMT_YUV420:
+ case V4L2_PIX_FMT_YUV422P:
+ switch (mbus_code) {
+ case MEDIA_BUS_FMT_UYVY8_2X8:
+ case MEDIA_BUS_FMT_UYVY8_1X16:
+ return CSI_INPUT_SEQ_UYVY;
+ case MEDIA_BUS_FMT_VYUY8_2X8:
+ case MEDIA_BUS_FMT_VYUY8_1X16:
+ return CSI_INPUT_SEQ_VYUY;
+ case MEDIA_BUS_FMT_YUYV8_2X8:
+ case MEDIA_BUS_FMT_YUYV8_1X16:
+ return CSI_INPUT_SEQ_YUYV;
+ case MEDIA_BUS_FMT_YVYU8_1X16:
+ case MEDIA_BUS_FMT_YVYU8_2X8:
+ return CSI_INPUT_SEQ_YVYU;
+ }
+ break;
+ case V4L2_PIX_FMT_NV21:
+ case V4L2_PIX_FMT_NV61:
+ case V4L2_PIX_FMT_YVU420:
+ switch (mbus_code) {
+ case MEDIA_BUS_FMT_UYVY8_2X8:
+ case MEDIA_BUS_FMT_UYVY8_1X16:
+ return CSI_INPUT_SEQ_VYUY;
+ case MEDIA_BUS_FMT_VYUY8_2X8:
+ case MEDIA_BUS_FMT_VYUY8_1X16:
+ return CSI_INPUT_SEQ_UYVY;
+ case MEDIA_BUS_FMT_YUYV8_2X8:
+ case MEDIA_BUS_FMT_YUYV8_1X16:
+ return CSI_INPUT_SEQ_YVYU;
+ case MEDIA_BUS_FMT_YVYU8_1X16:
+ case MEDIA_BUS_FMT_YVYU8_2X8:
+ return CSI_INPUT_SEQ_YUYV;
+ }
+ break;
+ }
+
+ return CSI_INPUT_SEQ_YUYV;
+}
+
+static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
+{
+ struct v4l2_fwnode_endpoint *endpoint = &sdev->csi.v4l2_ep;
+ unsigned char bus_width;
+ u32 flags;
+ u32 cfg;
+
+ bus_width = endpoint->bus.parallel.bus_width;
+
+ regmap_read(sdev->regmap, CSI_IF_CFG_REG, &cfg);
+
+ cfg &= ~(CSI_IF_CFG_CSI_IF_MASK | CSI_IF_CFG_MIPI_IF_MASK |
+ CSI_IF_CFG_IF_DATA_WIDTH_MASK |
+ CSI_IF_CFG_CLK_POL_MASK | CSI_IF_CFG_VREF_POL_MASK |
+ CSI_IF_CFG_HREF_POL_MASK | CSI_IF_CFG_FIELD_MASK);
+
+ switch (endpoint->bus_type) {
+ case V4L2_MBUS_CSI2:
+ cfg |= CSI_IF_CFG_MIPI_IF_MIPI;
+ break;
+ case V4L2_MBUS_PARALLEL:
+ cfg |= CSI_IF_CFG_MIPI_IF_CSI;
+
+ flags = endpoint->bus.parallel.flags;
+
+ cfg |= (bus_width == 16) ? CSI_IF_CFG_CSI_IF_YUV422_16BIT :
+ CSI_IF_CFG_CSI_IF_YUV422_INTLV;
+
+ if (flags & V4L2_MBUS_FIELD_EVEN_LOW)
+ cfg |= CSI_IF_CFG_FIELD_POSITIVE;
+
+ if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
+ cfg |= CSI_IF_CFG_VREF_POL_POSITIVE;
+ if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
+ cfg |= CSI_IF_CFG_HREF_POL_POSITIVE;
+
+ if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
+ cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE;
+ break;
+ case V4L2_MBUS_BT656:
+ cfg |= CSI_IF_CFG_MIPI_IF_CSI;
+
+ flags = endpoint->bus.parallel.flags;
+
+ cfg |= (bus_width == 16) ? CSI_IF_CFG_CSI_IF_BT1120 :
+ CSI_IF_CFG_CSI_IF_BT656;
+
+ if (flags & V4L2_MBUS_FIELD_EVEN_LOW)
+ cfg |= CSI_IF_CFG_FIELD_POSITIVE;
+
+ if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
+ cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE;
+ break;
+ default:
+ WARN_ON(1);
+ break;
+ }
+
+ switch (bus_width) {
+ case 8:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
+ break;
+ case 10:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
+ break;
+ case 12:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
+ break;
+ default:
+ break;
+ }
+
+ regmap_write(sdev->regmap, CSI_IF_CFG_REG, cfg);
+}
+
+static void sun6i_csi_set_format(struct sun6i_csi_dev *sdev)
+{
+ struct sun6i_csi *csi = &sdev->csi;
+ u32 cfg;
+ u32 val;
+
+ regmap_read(sdev->regmap, CSI_CH_CFG_REG, &cfg);
+
+ cfg &= ~(CSI_CH_CFG_INPUT_FMT_MASK |
+ CSI_CH_CFG_OUTPUT_FMT_MASK | CSI_CH_CFG_VFLIP_EN |
+ CSI_CH_CFG_HFLIP_EN | CSI_CH_CFG_FIELD_SEL_MASK |
+ CSI_CH_CFG_INPUT_SEQ_MASK);
+
+ val = get_csi_input_format(csi->config.code, csi->config.pixelformat);
+ cfg |= CSI_CH_CFG_INPUT_FMT(val);
+
+ val = get_csi_output_format(csi->config.pixelformat, csi->config.field);
+ cfg |= CSI_CH_CFG_OUTPUT_FMT(val);
+
+ val = get_csi_input_seq(csi->config.code, csi->config.pixelformat);
+ cfg |= CSI_CH_CFG_INPUT_SEQ(val);
+
+ if (csi->config.field == V4L2_FIELD_TOP)
+ cfg |= CSI_CH_CFG_FIELD_SEL_FIELD0;
+ else if (csi->config.field == V4L2_FIELD_BOTTOM)
+ cfg |= CSI_CH_CFG_FIELD_SEL_FIELD1;
+ else
+ cfg |= CSI_CH_CFG_FIELD_SEL_BOTH;
+
+ regmap_write(sdev->regmap, CSI_CH_CFG_REG, cfg);
+}
+
+static void sun6i_csi_set_window(struct sun6i_csi_dev *sdev)
+{
+ struct sun6i_csi_config *config = &sdev->csi.config;
+ u32 bytesperline_y;
+ u32 bytesperline_c;
+ int *planar_offset = sdev->planar_offset;
+ u32 width = config->width;
+ u32 height = config->height;
+ u32 hor_len = width;
+
+ switch (config->pixelformat) {
+ case V4L2_PIX_FMT_YUYV:
+ case V4L2_PIX_FMT_YVYU:
+ case V4L2_PIX_FMT_UYVY:
+ case V4L2_PIX_FMT_VYUY:
+ hor_len = width * 2;
+ break;
+ }
+
+ regmap_write(sdev->regmap, CSI_CH_HSIZE_REG,
+ CSI_CH_HSIZE_HOR_LEN(hor_len) |
+ CSI_CH_HSIZE_HOR_START(0));
+ regmap_write(sdev->regmap, CSI_CH_VSIZE_REG,
+ CSI_CH_VSIZE_VER_LEN(height) |
+ CSI_CH_VSIZE_VER_START(0));
+
+ planar_offset[0] = 0;
+ switch (config->pixelformat) {
+ case V4L2_PIX_FMT_HM12:
+ case V4L2_PIX_FMT_NV12:
+ case V4L2_PIX_FMT_NV21:
+ case V4L2_PIX_FMT_NV16:
+ case V4L2_PIX_FMT_NV61:
+ bytesperline_y = width;
+ bytesperline_c = width;
+ planar_offset[1] = bytesperline_y * height;
+ planar_offset[2] = -1;
+ break;
+ case V4L2_PIX_FMT_YUV420:
+ case V4L2_PIX_FMT_YVU420:
+ bytesperline_y = width;
+ bytesperline_c = width / 2;
+ planar_offset[1] = bytesperline_y * height;
+ planar_offset[2] = planar_offset[1] +
+ bytesperline_c * height / 2;
+ break;
+ case V4L2_PIX_FMT_YUV422P:
+ bytesperline_y = width;
+ bytesperline_c = width / 2;
+ planar_offset[1] = bytesperline_y * height;
+ planar_offset[2] = planar_offset[1] +
+ bytesperline_c * height;
+ break;
+ default: /* raw */
+ bytesperline_y = (v4l2_pixformat_get_bpp(config->pixelformat) *
+ config->width) / 8;
+ bytesperline_c = 0;
+ planar_offset[1] = -1;
+ planar_offset[2] = -1;
+ break;
+ }
+
+ regmap_write(sdev->regmap, CSI_CH_BUF_LEN_REG,
+ CSI_CH_BUF_LEN_BUF_LEN_C(bytesperline_c) |
+ CSI_CH_BUF_LEN_BUF_LEN_Y(bytesperline_y));
+}
+
+int sun6i_csi_get_supported_pixformats(struct sun6i_csi *csi,
+ const u32 **pixformats)
+{
+ if (pixformats != NULL)
+ *pixformats = supported_pixformats;
+
+ return ARRAY_SIZE(supported_pixformats);
+}
+
+bool sun6i_csi_is_format_support(struct sun6i_csi *csi, u32 pixformat,
+ u32 mbus_code)
+{
+ struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
+
+ return __is_format_support(sdev, pixformat, mbus_code);
+}
+
+int sun6i_csi_set_power(struct sun6i_csi *csi, bool enable)
+{
+ struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
+ struct regmap *regmap = sdev->regmap;
+ int ret;
+
+ if (!enable) {
+ regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN, 0);
+
+ clk_disable_unprepare(sdev->clk_ram);
+ clk_disable_unprepare(sdev->clk_mod);
+ reset_control_assert(sdev->rstc_bus);
+ return 0;
+ }
+
+ ret = clk_prepare_enable(sdev->clk_mod);
+ if (ret) {
+ dev_err(sdev->dev, "Enable csi clk err %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(sdev->clk_ram);
+ if (ret) {
+ dev_err(sdev->dev, "Enable clk_dram_csi clk err %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_control_deassert(sdev->rstc_bus);
+ if (ret) {
+ dev_err(sdev->dev, "reset err %d\n", ret);
+ return ret;
+ }
+
+ regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN, CSI_EN_CSI_EN);
+
+ return 0;
+}
+
+int sun6i_csi_update_config(struct sun6i_csi *csi,
+ struct sun6i_csi_config *config)
+{
+ struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
+
+ if (config == NULL)
+ return -EINVAL;
+
+ memcpy(&csi->config, config, sizeof(csi->config));
+
+ sun6i_csi_setup_bus(sdev);
+ sun6i_csi_set_format(sdev);
+ sun6i_csi_set_window(sdev);
+
+ return 0;
+}
+
+int sun6i_csi_update_buf_addr(struct sun6i_csi *csi, dma_addr_t addr)
+{
+ struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
+ /* transform physical address to bus address */
+ dma_addr_t bus_addr = addr - PHYS_OFFSET;
+
+ regmap_write(sdev->regmap, CSI_CH_F0_BUFA_REG,
+ (bus_addr + sdev->planar_offset[0]) >> 2);
+ if (sdev->planar_offset[1] != -1)
+ regmap_write(sdev->regmap, CSI_CH_F1_BUFA_REG,
+ (bus_addr + sdev->planar_offset[1]) >> 2);
+ if (sdev->planar_offset[2] != -1)
+ regmap_write(sdev->regmap, CSI_CH_F2_BUFA_REG,
+ (bus_addr + sdev->planar_offset[2]) >> 2);
+
+ return 0;
+}
+
+int sun6i_csi_set_stream(struct sun6i_csi *csi, bool enable)
+{
+ struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
+ struct regmap *regmap = sdev->regmap;
+
+ if (!enable) {
+ regmap_update_bits(regmap, CSI_CAP_REG, CSI_CAP_CH0_VCAP_ON, 0);
+ regmap_write(regmap, CSI_CH_INT_EN_REG, 0);
+ return 0;
+ }
+
+ regmap_write(regmap, CSI_CH_INT_STA_REG, 0xFF);
+ regmap_write(regmap, CSI_CH_INT_EN_REG,
+ CSI_CH_INT_EN_HB_OF_INT_EN |
+ CSI_CH_INT_EN_FIFO2_OF_INT_EN |
+ CSI_CH_INT_EN_FIFO1_OF_INT_EN |
+ CSI_CH_INT_EN_FIFO0_OF_INT_EN |
+ CSI_CH_INT_EN_FD_INT_EN |
+ CSI_CH_INT_EN_CD_INT_EN);
+
+ regmap_update_bits(regmap, CSI_CAP_REG, CSI_CAP_CH0_VCAP_ON,
+ CSI_CAP_CH0_VCAP_ON);
+
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * Media Controller and V4L2
+ */
+static int sun6i_csi_link_entity(struct sun6i_csi *csi,
+ struct media_entity *entity)
+{
+ struct media_entity *sink;
+ struct media_pad *sink_pad;
+ int ret;
+ int i;
+
+ if (!entity->num_pads) {
+ dev_err(csi->dev, "%s: invalid entity\n", entity->name);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < entity->num_pads; i++) {
+ if (entity->pads[i].flags & MEDIA_PAD_FL_SOURCE)
+ break;
+ }
+
+ if (i == entity->num_pads) {
+ dev_err(csi->dev, "%s: no source pad in external entity %s\n",
+ __func__, entity->name);
+ return -EINVAL;
+ }
+
+ sink = &csi->video.vdev.entity;
+ sink_pad = &csi->video.pad;
+
+ dev_dbg(csi->dev, "creating %s:%u -> %s:%u link\n",
+ entity->name, i, sink->name, sink_pad->index);
+ ret = media_create_pad_link(entity, i, sink, sink_pad->index,
+ MEDIA_LNK_FL_ENABLED);
+ if (ret < 0) {
+ dev_err(csi->dev, "failed to create %s:%u -> %s:%u link\n",
+ entity->name, i, sink->name, sink_pad->index);
+ return ret;
+ }
+
+ return media_entity_call(sink, link_setup, sink_pad, &entity->pads[i],
+ MEDIA_LNK_FL_ENABLED);
+}
+
+static int sun6i_subdev_notify_complete(struct v4l2_async_notifier *notifier)
+{
+ struct sun6i_csi *csi = container_of(notifier, struct sun6i_csi,
+ notifier);
+ struct v4l2_device *v4l2_dev = &csi->v4l2_dev;
+ struct v4l2_subdev *sd;
+ int ret;
+
+ dev_dbg(csi->dev, "notify complete, all subdevs registered\n");
+
+ if (notifier->num_subdevs != 1)
+ return -EINVAL;
+
+ sd = list_first_entry(&v4l2_dev->subdevs, struct v4l2_subdev, list);
+ if (sd == NULL)
+ return -EINVAL;
+
+ ret = sun6i_csi_link_entity(csi, &sd->entity);
+ if (ret < 0)
+ return ret;
+
+ ret = v4l2_device_register_subdev_nodes(&csi->v4l2_dev);
+ if (ret < 0)
+ return ret;
+
+ return media_device_register(&csi->media_dev);
+}
+
+static const struct v4l2_async_notifier_operations sun6i_csi_async_ops = {
+ .complete = sun6i_subdev_notify_complete,
+};
+
+static int sun6i_csi_fwnode_parse(struct device *dev,
+ struct v4l2_fwnode_endpoint *vep,
+ struct v4l2_async_subdev *asd)
+{
+ struct sun6i_csi *csi = dev_get_drvdata(dev);
+
+ if (vep->base.port || vep->base.id) {
+ dev_warn(dev, "Only support a single port with one endpoint\n");
+ return -ENOTCONN;
+ }
+
+ switch (vep->bus_type) {
+ case V4L2_MBUS_PARALLEL:
+ case V4L2_MBUS_BT656:
+ csi->v4l2_ep = *vep;
+ return 0;
+ default:
+ dev_err(dev, "Unsupported media bus type\n");
+ return -ENOTCONN;
+ }
+}
+
+static void sun6i_csi_v4l2_cleanup(struct sun6i_csi *csi)
+{
+ v4l2_async_notifier_cleanup(&csi->notifier);
+ v4l2_async_notifier_unregister(&csi->notifier);
+ sun6i_video_cleanup(&csi->video);
+ v4l2_device_unregister(&csi->v4l2_dev);
+ media_device_unregister(&csi->media_dev);
+ media_device_cleanup(&csi->media_dev);
+}
+
+static int sun6i_csi_v4l2_init(struct sun6i_csi *csi)
+{
+ int ret;
+
+ csi->media_dev.dev = csi->dev;
+ strlcpy(csi->media_dev.model, "Allwinner Video Capture Device",
+ sizeof(csi->media_dev.model));
+ csi->media_dev.hw_revision = 0;
+
+ media_device_init(&csi->media_dev);
+
+ csi->v4l2_dev.mdev = &csi->media_dev;
+ ret = v4l2_device_register(csi->dev, &csi->v4l2_dev);
+ if (ret) {
+ dev_err(csi->dev, "V4L2 device registration failed (%d)\n",
+ ret);
+ goto v4l2_reg_err;
+ }
+
+ ret = sun6i_video_init(&csi->video, csi, "sun6i-csi");
+ if (ret)
+ goto video_init_err;
+
+ ret = v4l2_async_notifier_parse_fwnode_endpoints(
+ csi->dev, &csi->notifier, sizeof(struct v4l2_async_subdev),
+ sun6i_csi_fwnode_parse);
+ if (ret)
+ goto fwnode_parse_err;
+
+ csi->notifier.ops = &sun6i_csi_async_ops;
+
+ ret = v4l2_async_notifier_register(&csi->v4l2_dev, &csi->notifier);
+ if (ret) {
+ dev_err(csi->dev, "notifier registration failed\n");
+ goto notifier_reg_err;
+ }
+
+ return 0;
+
+notifier_reg_err:
+ v4l2_async_notifier_cleanup(&csi->notifier);
+fwnode_parse_err:
+ sun6i_video_cleanup(&csi->video);
+video_init_err:
+ v4l2_device_unregister(&csi->v4l2_dev);
+v4l2_reg_err:
+ media_device_cleanup(&csi->media_dev);
+
+ return ret;
+}
+
+/* -----------------------------------------------------------------------------
+ * Resources and IRQ
+ */
+static irqreturn_t sun6i_csi_isr(int irq, void *dev_id)
+{
+ struct sun6i_csi_dev *sdev = (struct sun6i_csi_dev *)dev_id;
+ struct regmap *regmap = sdev->regmap;
+ u32 status;
+
+ regmap_read(regmap, CSI_CH_INT_STA_REG, &status);
+
+ if (!(status & 0xFF))
+ return IRQ_NONE;
+
+ if ((status & CSI_CH_INT_STA_FIFO0_OF_PD) ||
+ (status & CSI_CH_INT_STA_FIFO1_OF_PD) ||
+ (status & CSI_CH_INT_STA_FIFO2_OF_PD) ||
+ (status & CSI_CH_INT_STA_HB_OF_PD)) {
+ regmap_write(regmap, CSI_CH_INT_STA_REG, status);
+ regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN, 0);
+ regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN,
+ CSI_EN_CSI_EN);
+ return IRQ_HANDLED;
+ }
+
+ if (status & CSI_CH_INT_STA_FD_PD)
+ sun6i_video_frame_done(&sdev->csi.video);
+
+ regmap_write(regmap, CSI_CH_INT_STA_REG, status);
+
+ return IRQ_HANDLED;
+}
+
+static const struct regmap_config sun6i_csi_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1000,
+};
+
+static int sun6i_csi_resource_request(struct sun6i_csi_dev *sdev,
+ struct platform_device *pdev)
+{
+ struct resource *res;
+ void __iomem *io_base;
+ int ret;
+ int irq;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ io_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(io_base))
+ return PTR_ERR(io_base);
+
+ sdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "bus", io_base,
+ &sun6i_csi_regmap_config);
+ if (IS_ERR(sdev->regmap)) {
+ dev_err(&pdev->dev, "Failed to init register map\n");
+ return PTR_ERR(sdev->regmap);
+ }
+
+ sdev->clk_mod = devm_clk_get(&pdev->dev, "mod");
+ if (IS_ERR(sdev->clk_mod)) {
+ dev_err(&pdev->dev, "Unable to acquire csi clock\n");
+ return PTR_ERR(sdev->clk_mod);
+ }
+
+ sdev->clk_ram = devm_clk_get(&pdev->dev, "ram");
+ if (IS_ERR(sdev->clk_ram)) {
+ dev_err(&pdev->dev, "Unable to acquire dram-csi clock\n");
+ return PTR_ERR(sdev->clk_ram);
+ }
+
+ sdev->rstc_bus = devm_reset_control_get_shared(&pdev->dev, NULL);
+ if (IS_ERR(sdev->rstc_bus)) {
+ dev_err(&pdev->dev, "Cannot get reset controller\n");
+ return PTR_ERR(sdev->rstc_bus);
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "No csi IRQ specified\n");
+ ret = -ENXIO;
+ return ret;
+ }
+
+ ret = devm_request_irq(&pdev->dev, irq, sun6i_csi_isr, 0, MODULE_NAME,
+ sdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Cannot request csi IRQ\n");
+ return ret;
+ }
+ return 0;
+}
+
+static int sun6i_csi_probe(struct platform_device *pdev)
+{
+ struct sun6i_csi_dev *sdev;
+ int ret;
+
+ sdev = devm_kzalloc(&pdev->dev, sizeof(*sdev), GFP_KERNEL);
+ if (!sdev)
+ return -ENOMEM;
+
+ sdev->dev = &pdev->dev;
+
+ ret = sun6i_csi_resource_request(sdev, pdev);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, sdev);
+
+ sdev->csi.dev = &pdev->dev;
+ ret = sun6i_csi_v4l2_init(&sdev->csi);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int sun6i_csi_remove(struct platform_device *pdev)
+{
+ struct sun6i_csi_dev *sdev = platform_get_drvdata(pdev);
+
+ sun6i_csi_v4l2_cleanup(&sdev->csi);
+
+ return 0;
+}
+
+static const struct of_device_id sun6i_csi_of_match[] = {
+ { .compatible = "allwinner,sun8i-v3s-csi", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, sun6i_csi_of_match);
+
+static struct platform_driver sun6i_csi_platform_driver = {
+ .probe = sun6i_csi_probe,
+ .remove = sun6i_csi_remove,
+ .driver = {
+ .name = MODULE_NAME,
+ .of_match_table = of_match_ptr(sun6i_csi_of_match),
+ },
+};
+module_platform_driver(sun6i_csi_platform_driver);
+
+MODULE_DESCRIPTION("Allwinner V3s Camera Sensor Interface driver");
+MODULE_AUTHOR("Yong Deng <yong.deng-+3dxTMOEIRNWk0Htik3J/w@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
new file mode 100644
index 0000000..12508ff
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2017 Yong Deng <yong.deng-+3dxTMOEIRNWk0Htik3J/w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SUN6I_CSI_H__
+#define __SUN6I_CSI_H__
+
+#include <media/v4l2-device.h>
+#include <media/v4l2-fwnode.h>
+
+#include "sun6i_video.h"
+
+struct sun6i_csi;
+
+/**
+ * struct sun6i_csi_config - configs for sun6i csi
+ * @pixelformat: v4l2 pixel format (V4L2_PIX_FMT_*)
+ * @code: media bus format code (MEDIA_BUS_FMT_*)
+ * @field: used interlacing type (enum v4l2_field)
+ * @width: frame width
+ * @height: frame height
+ */
+struct sun6i_csi_config {
+ u32 pixelformat;
+ u32 code;
+ u32 field;
+ u32 width;
+ u32 height;
+};
+
+struct sun6i_csi {
+ struct device *dev;
+ struct v4l2_device v4l2_dev;
+ struct media_device media_dev;
+
+ struct v4l2_async_notifier notifier;
+
+ /* video port settings */
+ struct v4l2_fwnode_endpoint v4l2_ep;
+
+ struct sun6i_csi_config config;
+
+ struct sun6i_video video;
+};
+
+/**
+ * sun6i_csi_get_supported_pixformats() - get csi supported pixformats
+ * @csi: pointer to the csi
+ * @pixformats: supported pixformats return from csi
+ *
+ * @return the count of pixformats or error(< 0)
+ */
+int sun6i_csi_get_supported_pixformats(struct sun6i_csi *csi,
+ const u32 **pixformats);
+
+/**
+ * sun6i_csi_is_format_support() - check if the format supported by csi
+ * @csi: pointer to the csi
+ * @pixformat: v4l2 pixel format (V4L2_PIX_FMT_*)
+ * @mbus_code: media bus format code (MEDIA_BUS_FMT_*)
+ */
+bool sun6i_csi_is_format_support(struct sun6i_csi *csi, u32 pixformat,
+ u32 mbus_code);
+
+/**
+ * sun6i_csi_set_power() - power on/off the csi
+ * @csi: pointer to the csi
+ * @enable: on/off
+ */
+int sun6i_csi_set_power(struct sun6i_csi *csi, bool enable);
+
+/**
+ * sun6i_csi_update_config() - update the csi register setttings
+ * @csi: pointer to the csi
+ * @config: see struct sun6i_csi_config
+ */
+int sun6i_csi_update_config(struct sun6i_csi *csi,
+ struct sun6i_csi_config *config);
+
+/**
+ * sun6i_csi_update_buf_addr() - update the csi frame buffer address
+ * @csi: pointer to the csi
+ * @addr: frame buffer's physical address
+ */
+int sun6i_csi_update_buf_addr(struct sun6i_csi *csi, dma_addr_t addr);
+
+/**
+ * sun6i_csi_set_stream() - start/stop csi streaming
+ * @csi: pointer to the csi
+ * @enable: start/stop
+ */
+int sun6i_csi_set_stream(struct sun6i_csi *csi, bool enable);
+
+static inline int v4l2_pixformat_get_bpp(unsigned int pixformat)
+{
+ switch (pixformat) {
+ case V4L2_PIX_FMT_SBGGR8:
+ case V4L2_PIX_FMT_SGBRG8:
+ case V4L2_PIX_FMT_SGRBG8:
+ case V4L2_PIX_FMT_SRGGB8:
+ return 8;
+ case V4L2_PIX_FMT_SBGGR10:
+ case V4L2_PIX_FMT_SGBRG10:
+ case V4L2_PIX_FMT_SGRBG10:
+ case V4L2_PIX_FMT_SRGGB10:
+ return 10;
+ case V4L2_PIX_FMT_SBGGR12:
+ case V4L2_PIX_FMT_SGBRG12:
+ case V4L2_PIX_FMT_SGRBG12:
+ case V4L2_PIX_FMT_SRGGB12:
+ case V4L2_PIX_FMT_HM12:
+ case V4L2_PIX_FMT_NV12:
+ case V4L2_PIX_FMT_NV21:
+ case V4L2_PIX_FMT_YUV420:
+ case V4L2_PIX_FMT_YVU420:
+ return 12;
+ case V4L2_PIX_FMT_YUYV:
+ case V4L2_PIX_FMT_YVYU:
+ case V4L2_PIX_FMT_UYVY:
+ case V4L2_PIX_FMT_VYUY:
+ case V4L2_PIX_FMT_NV16:
+ case V4L2_PIX_FMT_NV61:
+ case V4L2_PIX_FMT_YUV422P:
+ return 16;
+ case V4L2_PIX_FMT_RGB24:
+ case V4L2_PIX_FMT_BGR24:
+ return 24;
+ case V4L2_PIX_FMT_RGB32:
+ case V4L2_PIX_FMT_BGR32:
+ return 32;
+ }
+
+ return 0;
+}
+
+#endif /* __SUN6I_CSI_H__ */
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
new file mode 100644
index 0000000..8e80467
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2017 Yong Deng <yong.deng-+3dxTMOEIRNWk0Htik3J/w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SUN6I_CSI_V3S_H__
+#define __SUN6I_CSI_V3S_H__
+
+#include <linux/kernel.h>
+
+#define CSI_EN_REG 0x0
+#define CSI_EN_VER_EN BIT(30)
+#define CSI_EN_CSI_EN BIT(0)
+
+#define CSI_IF_CFG_REG 0x4
+#define CSI_IF_CFG_SRC_TYPE_MASK BIT(21)
+#define CSI_IF_CFG_SRC_TYPE_PROGRESSED ((0 << 21) & CSI_IF_CFG_SRC_TYPE_MASK)
+#define CSI_IF_CFG_SRC_TYPE_INTERLACED ((1 << 21) & CSI_IF_CFG_SRC_TYPE_MASK)
+#define CSI_IF_CFG_FPS_DS_EN BIT(20)
+#define CSI_IF_CFG_FIELD_MASK BIT(19)
+#define CSI_IF_CFG_FIELD_NEGATIVE ((0 << 19) & CSI_IF_CFG_FIELD_MASK)
+#define CSI_IF_CFG_FIELD_POSITIVE ((1 << 19) & CSI_IF_CFG_FIELD_MASK)
+#define CSI_IF_CFG_VREF_POL_MASK BIT(18)
+#define CSI_IF_CFG_VREF_POL_NEGATIVE ((0 << 18) & CSI_IF_CFG_VREF_POL_MASK)
+#define CSI_IF_CFG_VREF_POL_POSITIVE ((1 << 18) & CSI_IF_CFG_VREF_POL_MASK)
+#define CSI_IF_CFG_HREF_POL_MASK BIT(17)
+#define CSI_IF_CFG_HREF_POL_NEGATIVE ((0 << 17) & CSI_IF_CFG_HREF_POL_MASK)
+#define CSI_IF_CFG_HREF_POL_POSITIVE ((1 << 17) & CSI_IF_CFG_HREF_POL_MASK)
+#define CSI_IF_CFG_CLK_POL_MASK BIT(16)
+#define CSI_IF_CFG_CLK_POL_RISING_EDGE ((0 << 16) & CSI_IF_CFG_CLK_POL_MASK)
+#define CSI_IF_CFG_CLK_POL_FALLING_EDGE ((1 << 16) & CSI_IF_CFG_CLK_POL_MASK)
+#define CSI_IF_CFG_IF_DATA_WIDTH_MASK GENMASK(10, 8)
+#define CSI_IF_CFG_IF_DATA_WIDTH_8BIT ((0 << 8) & CSI_IF_CFG_IF_DATA_WIDTH_MASK)
+#define CSI_IF_CFG_IF_DATA_WIDTH_10BIT ((1 << 8) & CSI_IF_CFG_IF_DATA_WIDTH_MASK)
+#define CSI_IF_CFG_IF_DATA_WIDTH_12BIT ((2 << 8) & CSI_IF_CFG_IF_DATA_WIDTH_MASK)
+#define CSI_IF_CFG_MIPI_IF_MASK BIT(7)
+#define CSI_IF_CFG_MIPI_IF_CSI (0 << 7)
+#define CSI_IF_CFG_MIPI_IF_MIPI (1 << 7)
+#define CSI_IF_CFG_CSI_IF_MASK GENMASK(4, 0)
+#define CSI_IF_CFG_CSI_IF_YUV422_INTLV ((0 << 0) & CSI_IF_CFG_CSI_IF_MASK)
+#define CSI_IF_CFG_CSI_IF_YUV422_16BIT ((1 << 0) & CSI_IF_CFG_CSI_IF_MASK)
+#define CSI_IF_CFG_CSI_IF_BT656 ((4 << 0) & CSI_IF_CFG_CSI_IF_MASK)
+#define CSI_IF_CFG_CSI_IF_BT1120 ((5 << 0) & CSI_IF_CFG_CSI_IF_MASK)
+
+#define CSI_CAP_REG 0x8
+#define CSI_CAP_CH0_CAP_MASK_MASK GENMASK(5, 2)
+#define CSI_CAP_CH0_CAP_MASK(count) ((count << 2) & CSI_CAP_CH0_CAP_MASK_MASK)
+#define CSI_CAP_CH0_VCAP_ON BIT(1)
+#define CSI_CAP_CH0_SCAP_ON BIT(0)
+
+#define CSI_SYNC_CNT_REG 0xc
+#define CSI_FIFO_THRS_REG 0x10
+#define CSI_BT656_HEAD_CFG_REG 0x14
+#define CSI_PTN_LEN_REG 0x30
+#define CSI_PTN_ADDR_REG 0x34
+#define CSI_VER_REG 0x3c
+
+#define CSI_CH_CFG_REG 0x44
+#define CSI_CH_CFG_INPUT_FMT_MASK GENMASK(23, 20)
+#define CSI_CH_CFG_INPUT_FMT(fmt) ((fmt << 20) & CSI_CH_CFG_INPUT_FMT_MASK)
+#define CSI_CH_CFG_OUTPUT_FMT_MASK GENMASK(19, 16)
+#define CSI_CH_CFG_OUTPUT_FMT(fmt) ((fmt << 16) & CSI_CH_CFG_OUTPUT_FMT_MASK)
+#define CSI_CH_CFG_VFLIP_EN BIT(13)
+#define CSI_CH_CFG_HFLIP_EN BIT(12)
+#define CSI_CH_CFG_FIELD_SEL_MASK GENMASK(11, 10)
+#define CSI_CH_CFG_FIELD_SEL_FIELD0 ((0 << 10) & CSI_CH_CFG_FIELD_SEL_MASK)
+#define CSI_CH_CFG_FIELD_SEL_FIELD1 ((1 << 10) & CSI_CH_CFG_FIELD_SEL_MASK)
+#define CSI_CH_CFG_FIELD_SEL_BOTH ((2 << 10) & CSI_CH_CFG_FIELD_SEL_MASK)
+#define CSI_CH_CFG_INPUT_SEQ_MASK GENMASK(9, 8)
+#define CSI_CH_CFG_INPUT_SEQ(seq) ((seq << 8) & CSI_CH_CFG_INPUT_SEQ_MASK)
+
+#define CSI_CH_SCALE_REG 0x4c
+#define CSI_CH_SCALE_QUART_EN BIT(0)
+
+#define CSI_CH_F0_BUFA_REG 0x50
+
+#define CSI_CH_F1_BUFA_REG 0x58
+
+#define CSI_CH_F2_BUFA_REG 0x60
+
+#define CSI_CH_STA_REG 0x6c
+#define CSI_CH_STA_FIELD_STA_MASK BIT(2)
+#define CSI_CH_STA_FIELD_STA_FIELD0 ((0 << 2) & CSI_CH_STA_FIELD_STA_MASK)
+#define CSI_CH_STA_FIELD_STA_FIELD1 ((1 << 2) & CSI_CH_STA_FIELD_STA_MASK)
+#define CSI_CH_STA_VCAP_STA BIT(1)
+#define CSI_CH_STA_SCAP_STA BIT(0)
+
+#define CSI_CH_INT_EN_REG 0x70
+#define CSI_CH_INT_EN_VS_INT_EN BIT(7)
+#define CSI_CH_INT_EN_HB_OF_INT_EN BIT(6)
+#define CSI_CH_INT_EN_MUL_ERR_INT_EN BIT(5)
+#define CSI_CH_INT_EN_FIFO2_OF_INT_EN BIT(4)
+#define CSI_CH_INT_EN_FIFO1_OF_INT_EN BIT(3)
+#define CSI_CH_INT_EN_FIFO0_OF_INT_EN BIT(2)
+#define CSI_CH_INT_EN_FD_INT_EN BIT(1)
+#define CSI_CH_INT_EN_CD_INT_EN BIT(0)
+
+#define CSI_CH_INT_STA_REG 0x74
+#define CSI_CH_INT_STA_VS_PD BIT(7)
+#define CSI_CH_INT_STA_HB_OF_PD BIT(6)
+#define CSI_CH_INT_STA_MUL_ERR_PD BIT(5)
+#define CSI_CH_INT_STA_FIFO2_OF_PD BIT(4)
+#define CSI_CH_INT_STA_FIFO1_OF_PD BIT(3)
+#define CSI_CH_INT_STA_FIFO0_OF_PD BIT(2)
+#define CSI_CH_INT_STA_FD_PD BIT(1)
+#define CSI_CH_INT_STA_CD_PD BIT(0)
+
+#define CSI_CH_FLD1_VSIZE_REG 0x78
+
+#define CSI_CH_HSIZE_REG 0x80
+#define CSI_CH_HSIZE_HOR_LEN_MASK GENMASK(28, 16)
+#define CSI_CH_HSIZE_HOR_LEN(len) ((len << 16) & CSI_CH_HSIZE_HOR_LEN_MASK)
+#define CSI_CH_HSIZE_HOR_START_MASK GENMASK(12, 0)
+#define CSI_CH_HSIZE_HOR_START(start) ((start << 0) & CSI_CH_HSIZE_HOR_START_MASK)
+
+#define CSI_CH_VSIZE_REG 0x84
+#define CSI_CH_VSIZE_VER_LEN_MASK GENMASK(28, 16)
+#define CSI_CH_VSIZE_VER_LEN(len) ((len << 16) & CSI_CH_VSIZE_VER_LEN_MASK)
+#define CSI_CH_VSIZE_VER_START_MASK GENMASK(12, 0)
+#define CSI_CH_VSIZE_VER_START(start) ((start << 0) & CSI_CH_VSIZE_VER_START_MASK)
+
+#define CSI_CH_BUF_LEN_REG 0x88
+#define CSI_CH_BUF_LEN_BUF_LEN_C_MASK GENMASK(29, 16)
+#define CSI_CH_BUF_LEN_BUF_LEN_C(len) ((len << 16) & CSI_CH_BUF_LEN_BUF_LEN_C_MASK)
+#define CSI_CH_BUF_LEN_BUF_LEN_Y_MASK GENMASK(13, 0)
+#define CSI_CH_BUF_LEN_BUF_LEN_Y(len) ((len << 0) & CSI_CH_BUF_LEN_BUF_LEN_Y_MASK)
+
+#define CSI_CH_FLIP_SIZE_REG 0x8c
+#define CSI_CH_FLIP_SIZE_VER_LEN_MASK GENMASK(28, 16)
+#define CSI_CH_FLIP_SIZE_VER_LEN(len) ((len << 16) & CSI_CH_FLIP_SIZE_VER_LEN_MASK)
+#define CSI_CH_FLIP_SIZE_VALID_LEN_MASK GENMASK(12, 0)
+#define CSI_CH_FLIP_SIZE_VALID_LEN(len) ((len << 0) & CSI_CH_FLIP_SIZE_VALID_LEN_MASK)
+
+#define CSI_CH_FRM_CLK_CNT_REG 0x90
+#define CSI_CH_ACC_ITNL_CLK_CNT_REG 0x94
+#define CSI_CH_FIFO_STAT_REG 0x98
+#define CSI_CH_PCLK_STAT_REG 0x9c
+
+/*
+ * csi input data format
+ */
+enum csi_input_fmt {
+ CSI_INPUT_FORMAT_RAW = 0,
+ CSI_INPUT_FORMAT_YUV422 = 3,
+ CSI_INPUT_FORMAT_YUV420 = 4,
+};
+
+/*
+ * csi output data format
+ */
+enum csi_output_fmt {
+ /* only when input format is RAW */
+ CSI_FIELD_RAW_8 = 0,
+ CSI_FIELD_RAW_10 = 1,
+ CSI_FIELD_RAW_12 = 2,
+ CSI_FIELD_RGB565 = 4,
+ CSI_FIELD_RGB888 = 5,
+ CSI_FIELD_PRGB888 = 6,
+ CSI_FRAME_RAW_8 = 8,
+ CSI_FRAME_RAW_10 = 9,
+ CSI_FRAME_RAW_12 = 10,
+ CSI_FRAME_RGB565 = 12,
+ CSI_FRAME_RGB888 = 13,
+ CSI_FRAME_PRGB888 = 14,
+
+ /* only when input format is YUV422 */
+ CSI_FIELD_PLANAR_YUV422 = 0,
+ CSI_FIELD_PLANAR_YUV420 = 1,
+ CSI_FRAME_PLANAR_YUV420 = 2,
+ CSI_FRAME_PLANAR_YUV422 = 3,
+ CSI_FIELD_UV_CB_YUV422 = 4,
+ CSI_FIELD_UV_CB_YUV420 = 5,
+ CSI_FRAME_UV_CB_YUV420 = 6,
+ CSI_FRAME_UV_CB_YUV422 = 7,
+ CSI_FIELD_MB_YUV422 = 8,
+ CSI_FIELD_MB_YUV420 = 9,
+ CSI_FRAME_MB_YUV420 = 10,
+ CSI_FRAME_MB_YUV422 = 11,
+ CSI_FIELD_UV_CB_YUV422_10 = 12,
+ CSI_FIELD_UV_CB_YUV420_10 = 13,
+};
+
+/*
+ * csi YUV input data sequence
+ */
+enum csi_input_seq {
+ /* only when input format is YUV422 */
+ CSI_INPUT_SEQ_YUYV = 0,
+ CSI_INPUT_SEQ_YVYU,
+ CSI_INPUT_SEQ_UYVY,
+ CSI_INPUT_SEQ_VYUY,
+};
+
+#endif /* __SUN6I_CSI_V3S_H__ */
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_video.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_video.c
new file mode 100644
index 0000000..0cebcbd
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_video.c
@@ -0,0 +1,722 @@
+/*
+ * Copyright (c) 2017 Magewell Electronics Co., Ltd. (Nanjing).
+ * All rights reserved.
+ * Author: Yong Deng <yong.deng-+3dxTMOEIRNWk0Htik3J/w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/of.h>
+
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mc.h>
+#include <media/videobuf2-dma-contig.h>
+#include <media/videobuf2-v4l2.h>
+
+#include "sun6i_csi.h"
+#include "sun6i_video.h"
+
+struct sun6i_csi_buffer {
+ struct vb2_v4l2_buffer vb;
+ struct list_head list;
+
+ dma_addr_t dma_addr;
+};
+
+static struct sun6i_csi_format *
+find_format_by_fourcc(struct sun6i_video *video, unsigned int fourcc)
+{
+ unsigned int num_formats = video->num_formats;
+ struct sun6i_csi_format *fmt;
+ unsigned int i;
+
+ for (i = 0; i < num_formats; i++) {
+ fmt = &video->formats[i];
+ if (fmt->fourcc == fourcc)
+ return fmt;
+ }
+
+ return NULL;
+}
+
+static struct v4l2_subdev *
+sun6i_video_remote_subdev(struct sun6i_video *video, u32 *pad)
+{
+ struct media_pad *remote;
+
+ remote = media_entity_remote_pad(&video->pad);
+
+ if (!remote || !is_media_entity_v4l2_subdev(remote->entity))
+ return NULL;
+
+ if (pad)
+ *pad = remote->index;
+
+ return media_entity_to_v4l2_subdev(remote->entity);
+}
+
+static int sun6i_video_queue_setup(struct vb2_queue *vq,
+ unsigned int *nbuffers, unsigned int *nplanes,
+ unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ struct sun6i_video *video = vb2_get_drv_priv(vq);
+ unsigned int size = video->fmt.fmt.pix.sizeimage;
+
+ if (*nplanes)
+ return sizes[0] < size ? -EINVAL : 0;
+
+ *nplanes = 1;
+ sizes[0] = size;
+
+ return 0;
+}
+
+static int sun6i_video_buffer_prepare(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct sun6i_csi_buffer *buf =
+ container_of(vbuf, struct sun6i_csi_buffer, vb);
+ struct sun6i_video *video = vb2_get_drv_priv(vb->vb2_queue);
+ unsigned long size = video->fmt.fmt.pix.sizeimage;
+
+ if (vb2_plane_size(vb, 0) < size) {
+ v4l2_err(video->vdev.v4l2_dev, "buffer too small (%lu < %lu)\n",
+ vb2_plane_size(vb, 0), size);
+ return -EINVAL;
+ }
+
+ vb2_set_plane_payload(vb, 0, size);
+
+ buf->dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
+
+ vbuf->field = video->fmt.fmt.pix.field;
+
+ return 0;
+}
+
+static int sun6i_pipeline_set_stream(struct sun6i_video *video, bool enable)
+{
+ struct media_entity *entity;
+ struct media_pad *pad;
+ struct v4l2_subdev *subdev;
+ int ret;
+
+ entity = &video->vdev.entity;
+ while (1) {
+ pad = &entity->pads[0];
+ if (!(pad->flags & MEDIA_PAD_FL_SINK))
+ break;
+
+ pad = media_entity_remote_pad(pad);
+ if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
+ break;
+
+ entity = pad->entity;
+ subdev = media_entity_to_v4l2_subdev(entity);
+
+ ret = v4l2_subdev_call(subdev, video, s_stream, enable);
+ if (enable && ret < 0 && ret != -ENOIOCTLCMD)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sun6i_video_start_streaming(struct vb2_queue *vq, unsigned int count)
+{
+ struct sun6i_video *video = vb2_get_drv_priv(vq);
+ struct sun6i_csi_buffer *buf;
+ struct sun6i_csi_config config;
+ unsigned long flags;
+ int ret;
+
+ video->sequence = 0;
+
+ ret = media_pipeline_start(&video->vdev.entity, &video->vdev.pipe);
+ if (ret < 0)
+ goto err_start_pipeline;
+
+ ret = sun6i_pipeline_set_stream(video, true);
+ if (ret < 0)
+ goto err_start_stream;
+
+ config.pixelformat = video->fmt.fmt.pix.pixelformat;
+ config.code = video->current_fmt->mbus_code;
+ config.field = video->fmt.fmt.pix.field;
+ config.width = video->fmt.fmt.pix.width;
+ config.height = video->fmt.fmt.pix.height;
+
+ ret = sun6i_csi_update_config(video->csi, &config);
+ if (ret < 0)
+ goto err_update_config;
+
+ spin_lock_irqsave(&video->dma_queue_lock, flags);
+ video->cur_frm = list_first_entry(&video->dma_queue,
+ struct sun6i_csi_buffer, list);
+ list_del(&video->cur_frm->list);
+ spin_unlock_irqrestore(&video->dma_queue_lock, flags);
+
+ ret = sun6i_csi_update_buf_addr(video->csi, video->cur_frm->dma_addr);
+ if (ret < 0)
+ goto err_update_addr;
+
+ ret = sun6i_csi_set_stream(video->csi, true);
+ if (ret < 0)
+ goto err_csi_stream;
+
+ return 0;
+
+err_csi_stream:
+err_update_addr:
+err_update_config:
+ sun6i_pipeline_set_stream(video, false);
+err_start_stream:
+ media_pipeline_stop(&video->vdev.entity);
+err_start_pipeline:
+ spin_lock_irqsave(&video->dma_queue_lock, flags);
+ list_for_each_entry(buf, &video->dma_queue, list)
+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
+ INIT_LIST_HEAD(&video->dma_queue);
+ spin_unlock_irqrestore(&video->dma_queue_lock, flags);
+
+ return ret;
+}
+
+static void sun6i_video_stop_streaming(struct vb2_queue *vq)
+{
+ struct sun6i_video *video = vb2_get_drv_priv(vq);
+ unsigned long flags;
+ struct sun6i_csi_buffer *buf;
+
+ sun6i_pipeline_set_stream(video, false);
+
+ sun6i_csi_set_stream(video->csi, false);
+
+ media_pipeline_stop(&video->vdev.entity);
+
+ /* Release all active buffers */
+ spin_lock_irqsave(&video->dma_queue_lock, flags);
+ if (unlikely(video->cur_frm)) {
+ vb2_buffer_done(&video->cur_frm->vb.vb2_buf,
+ VB2_BUF_STATE_ERROR);
+ video->cur_frm = NULL;
+ }
+ list_for_each_entry(buf, &video->dma_queue, list)
+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
+ INIT_LIST_HEAD(&video->dma_queue);
+ spin_unlock_irqrestore(&video->dma_queue_lock, flags);
+}
+
+static void sun6i_video_buffer_queue(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct sun6i_csi_buffer *buf =
+ container_of(vbuf, struct sun6i_csi_buffer, vb);
+ struct sun6i_video *video = vb2_get_drv_priv(vb->vb2_queue);
+ unsigned long flags;
+
+ spin_lock_irqsave(&video->dma_queue_lock, flags);
+ if (!video->cur_frm && list_empty(&video->dma_queue) &&
+ vb2_is_streaming(vb->vb2_queue)) {
+ video->cur_frm = buf;
+ sun6i_csi_update_buf_addr(video->csi, video->cur_frm->dma_addr);
+ sun6i_csi_set_stream(video->csi, 1);
+ } else
+ list_add_tail(&buf->list, &video->dma_queue);
+ spin_unlock_irqrestore(&video->dma_queue_lock, flags);
+}
+
+void sun6i_video_frame_done(struct sun6i_video *video)
+{
+ spin_lock(&video->dma_queue_lock);
+
+ if (video->cur_frm) {
+ struct vb2_v4l2_buffer *vbuf = &video->cur_frm->vb;
+ struct vb2_buffer *vb = &vbuf->vb2_buf;
+
+ vb->timestamp = ktime_get_ns();
+ vbuf->sequence = video->sequence++;
+ vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
+ video->cur_frm = NULL;
+ }
+
+ if (!list_empty(&video->dma_queue)
+ && vb2_is_streaming(&video->vb2_vidq)) {
+ video->cur_frm = list_first_entry(&video->dma_queue,
+ struct sun6i_csi_buffer, list);
+ list_del(&video->cur_frm->list);
+ sun6i_csi_update_buf_addr(video->csi, video->cur_frm->dma_addr);
+ } else
+ sun6i_csi_set_stream(video->csi, 0);
+
+ spin_unlock(&video->dma_queue_lock);
+}
+
+static struct vb2_ops sun6i_csi_vb2_ops = {
+ .queue_setup = sun6i_video_queue_setup,
+ .wait_prepare = vb2_ops_wait_prepare,
+ .wait_finish = vb2_ops_wait_finish,
+ .buf_prepare = sun6i_video_buffer_prepare,
+ .start_streaming = sun6i_video_start_streaming,
+ .stop_streaming = sun6i_video_stop_streaming,
+ .buf_queue = sun6i_video_buffer_queue,
+};
+
+static int vidioc_querycap(struct file *file, void *priv,
+ struct v4l2_capability *cap)
+{
+ struct sun6i_video *video = video_drvdata(file);
+
+ strlcpy(cap->driver, "sun6i-video", sizeof(cap->driver));
+ strlcpy(cap->card, video->vdev.name, sizeof(cap->card));
+ snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
+ video->csi->dev->of_node->name);
+
+ return 0;
+}
+
+static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ struct sun6i_video *video = video_drvdata(file);
+ u32 index = f->index;
+
+ if (index >= video->num_formats)
+ return -EINVAL;
+
+ f->pixelformat = video->formats[index].fourcc;
+
+ return 0;
+}
+
+static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *fmt)
+{
+ struct sun6i_video *video = video_drvdata(file);
+
+ *fmt = video->fmt;
+
+ return 0;
+}
+
+static int sun6i_video_try_fmt(struct sun6i_video *video, struct v4l2_format *f,
+ struct sun6i_csi_format **current_fmt)
+{
+ struct sun6i_csi_format *csi_fmt;
+ struct v4l2_pix_format *pixfmt = &f->fmt.pix;
+ struct v4l2_subdev_format format;
+ struct v4l2_subdev *subdev;
+ u32 pad;
+ int ret;
+
+ subdev = sun6i_video_remote_subdev(video, &pad);
+ if (subdev == NULL)
+ return -ENXIO;
+
+ csi_fmt = find_format_by_fourcc(video, pixfmt->pixelformat);
+ if (csi_fmt == NULL) {
+ if (video->num_formats > 0) {
+ csi_fmt = &video->formats[0];
+ pixfmt->pixelformat = csi_fmt->fourcc;
+ } else
+ return -EINVAL;
+ }
+
+ format.pad = pad;
+ format.which = V4L2_SUBDEV_FORMAT_TRY;
+ v4l2_fill_mbus_format(&format.format, pixfmt, csi_fmt->mbus_code);
+ ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &format);
+ if (ret)
+ return ret;
+
+ v4l2_fill_pix_format(pixfmt, &format.format);
+
+ pixfmt->bytesperline = (pixfmt->width * csi_fmt->bpp) >> 3;
+ pixfmt->sizeimage = (pixfmt->width * csi_fmt->bpp * pixfmt->height) / 8;
+
+ if (current_fmt)
+ *current_fmt = csi_fmt;
+
+ return 0;
+}
+
+static int sun6i_video_set_fmt(struct sun6i_video *video, struct v4l2_format *f)
+{
+ struct v4l2_subdev_format format;
+ struct sun6i_csi_format *current_fmt;
+ struct v4l2_subdev *subdev;
+ u32 pad;
+ int ret;
+
+ subdev = sun6i_video_remote_subdev(video, &pad);
+ if (subdev == NULL)
+ return -ENXIO;
+
+ ret = sun6i_video_try_fmt(video, f, ¤t_fmt);
+ if (ret)
+ return ret;
+
+ format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+ v4l2_fill_mbus_format(&format.format, &f->fmt.pix,
+ current_fmt->mbus_code);
+ ret = v4l2_subdev_call(subdev, pad, set_fmt, NULL, &format);
+ if (ret < 0)
+ return ret;
+
+ video->fmt = *f;
+ video->current_fmt = current_fmt;
+
+ return 0;
+}
+
+static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct sun6i_video *video = video_drvdata(file);
+
+ if (vb2_is_busy(&video->vb2_vidq))
+ return -EBUSY;
+
+ return sun6i_video_set_fmt(video, f);
+}
+
+static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct sun6i_video *video = video_drvdata(file);
+
+ return sun6i_video_try_fmt(video, f, NULL);
+}
+
+static int vidioc_enum_input(struct file *file, void *fh,
+ struct v4l2_input *inp)
+{
+ struct sun6i_video *video = video_drvdata(file);
+ struct v4l2_subdev *subdev;
+ u32 pad;
+ int ret;
+
+ if (inp->index != 0)
+ return -EINVAL;
+
+ subdev = sun6i_video_remote_subdev(video, &pad);
+ if (subdev == NULL)
+ return -ENXIO;
+
+ ret = v4l2_subdev_call(subdev, video, g_input_status, &inp->status);
+ if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
+ return ret;
+
+ inp->type = V4L2_INPUT_TYPE_CAMERA;
+
+ if (v4l2_subdev_has_op(subdev, pad, dv_timings_cap)) {
+ inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
+ inp->std = 0;
+ } else {
+ inp->capabilities = 0;
+ inp->std = 0;
+ }
+
+ strlcpy(inp->name, subdev->name, sizeof(inp->name));
+
+ return 0;
+}
+
+static int vidioc_g_input(struct file *file, void *fh, unsigned int *i)
+{
+ *i = 0;
+
+ return 0;
+}
+
+static int vidioc_s_input(struct file *file, void *fh, unsigned int i)
+{
+ if (i != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct v4l2_ioctl_ops sun6i_video_ioctl_ops = {
+ .vidioc_querycap = vidioc_querycap,
+ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
+ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
+ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
+ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
+
+ .vidioc_enum_input = vidioc_enum_input,
+ .vidioc_s_input = vidioc_s_input,
+ .vidioc_g_input = vidioc_g_input,
+
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+};
+
+/* -----------------------------------------------------------------------------
+ * V4L2 file operations
+ */
+static int sun6i_video_open(struct file *file)
+{
+ struct sun6i_video *video = video_drvdata(file);
+ int ret;
+
+ if (mutex_lock_interruptible(&video->lock))
+ return -ERESTARTSYS;
+
+ ret = v4l2_fh_open(file);
+ if (ret < 0)
+ goto unlock;
+
+ ret = v4l2_pipeline_pm_use(&video->vdev.entity, 1);
+ if (ret < 0)
+ goto fh_release;
+
+ if (!v4l2_fh_is_singular_file(file))
+ goto unlock;
+
+ ret = sun6i_csi_set_power(video->csi, true);
+ if (ret < 0)
+ goto fh_release;
+
+ mutex_unlock(&video->lock);
+ return 0;
+
+fh_release:
+ v4l2_fh_release(file);
+unlock:
+ mutex_unlock(&video->lock);
+ return ret;
+}
+
+static int sun6i_video_close(struct file *file)
+{
+ struct sun6i_video *video = video_drvdata(file);
+ bool last_fh;
+
+ mutex_lock(&video->lock);
+
+ last_fh = v4l2_fh_is_singular_file(file);
+
+ _vb2_fop_release(file, NULL);
+
+ v4l2_pipeline_pm_use(&video->vdev.entity, 0);
+
+ if (last_fh)
+ sun6i_csi_set_power(video->csi, false);
+
+ mutex_unlock(&video->lock);
+
+ return 0;
+}
+
+static const struct v4l2_file_operations sun6i_video_fops = {
+ .owner = THIS_MODULE,
+ .open = sun6i_video_open,
+ .release = sun6i_video_close,
+ .unlocked_ioctl = video_ioctl2,
+ .mmap = vb2_fop_mmap,
+ .poll = vb2_fop_poll
+};
+
+/* -----------------------------------------------------------------------------
+ * Media Operations
+ */
+static int sun6i_video_formats_init(struct sun6i_video *video)
+{
+ struct v4l2_subdev_mbus_code_enum mbus_code = { 0 };
+ struct sun6i_csi *csi = video->csi;
+ struct v4l2_format format;
+ struct v4l2_subdev *subdev;
+ u32 pad;
+ const u32 *pixformats;
+ int pixformat_count = 0;
+ u32 subdev_codes[32]; /* subdev format codes, 32 should be enough */
+ int codes_count = 0;
+ int num_fmts = 0;
+ int i, j;
+
+ subdev = sun6i_video_remote_subdev(video, &pad);
+ if (subdev == NULL)
+ return -ENXIO;
+
+ /* Get supported pixformats of CSI */
+ pixformat_count = sun6i_csi_get_supported_pixformats(csi, &pixformats);
+ if (pixformat_count <= 0)
+ return -ENXIO;
+
+ /* Get subdev formats codes */
+ mbus_code.pad = pad;
+ mbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+ while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL,
+ &mbus_code)) {
+ if (codes_count >= ARRAY_SIZE(subdev_codes)) {
+ dev_warn(video->csi->dev,
+ "subdev_codes array is full!\n");
+ break;
+ }
+ subdev_codes[codes_count] = mbus_code.code;
+ codes_count++;
+ mbus_code.index++;
+ }
+
+ if (!codes_count)
+ return -ENXIO;
+
+ /* Get supported formats count */
+ for (i = 0; i < codes_count; i++) {
+ for (j = 0; j < pixformat_count; j++) {
+ if (!sun6i_csi_is_format_support(csi, pixformats[j],
+ mbus_code.code)) {
+ continue;
+ }
+ num_fmts++;
+ }
+ }
+
+ if (!num_fmts)
+ return -ENXIO;
+
+ video->num_formats = num_fmts;
+ video->formats = devm_kcalloc(video->csi->dev, num_fmts,
+ sizeof(struct sun6i_csi_format), GFP_KERNEL);
+ if (!video->formats)
+ return -ENOMEM;
+
+ /* Get supported formats */
+ num_fmts = 0;
+ for (i = 0; i < codes_count; i++) {
+ for (j = 0; j < pixformat_count; j++) {
+ if (!sun6i_csi_is_format_support(csi, pixformats[j],
+ mbus_code.code)) {
+ continue;
+ }
+
+ video->formats[num_fmts].fourcc = pixformats[j];
+ video->formats[num_fmts].mbus_code =
+ mbus_code.code;
+ video->formats[num_fmts].bpp =
+ v4l2_pixformat_get_bpp(pixformats[j]);
+ num_fmts++;
+ }
+ }
+
+ /* setup default format */
+ format.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ format.fmt.pix.width = 1280;
+ format.fmt.pix.height = 720;
+ format.fmt.pix.pixelformat = video->formats[0].fourcc;
+ sun6i_video_set_fmt(video, &format);
+
+ return 0;
+}
+
+static int sun6i_video_link_setup(struct media_entity *entity,
+ const struct media_pad *local,
+ const struct media_pad *remote, u32 flags)
+{
+ struct video_device *vdev = media_entity_to_video_device(entity);
+ struct sun6i_video *video = video_get_drvdata(vdev);
+
+ if (WARN_ON(video == NULL))
+ return 0;
+
+ return sun6i_video_formats_init(video);
+}
+
+static const struct media_entity_operations sun6i_video_media_ops = {
+ .link_setup = sun6i_video_link_setup,
+};
+
+int sun6i_video_init(struct sun6i_video *video, struct sun6i_csi *csi,
+ const char *name)
+{
+ struct video_device *vdev = &video->vdev;
+ struct vb2_queue *vidq = &video->vb2_vidq;
+ int ret;
+
+ video->csi = csi;
+
+ /* Initialize the media entity... */
+ video->pad.flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
+ vdev->entity.ops = &sun6i_video_media_ops;
+ ret = media_entity_pads_init(&vdev->entity, 1, &video->pad);
+ if (ret < 0)
+ return ret;
+
+ mutex_init(&video->lock);
+
+ INIT_LIST_HEAD(&video->dma_queue);
+ spin_lock_init(&video->dma_queue_lock);
+
+ video->cur_frm = NULL;
+ video->sequence = 0;
+ video->num_formats = 0;
+
+ /* Initialize videobuf2 queue */
+ vidq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ vidq->io_modes = VB2_MMAP | VB2_DMABUF;
+ vidq->drv_priv = video;
+ vidq->buf_struct_size = sizeof(struct sun6i_csi_buffer);
+ vidq->ops = &sun6i_csi_vb2_ops;
+ vidq->mem_ops = &vb2_dma_contig_memops;
+ vidq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+ vidq->lock = &video->lock;
+ vidq->min_buffers_needed = 1;
+ vidq->dev = csi->dev;
+
+ ret = vb2_queue_init(vidq);
+ if (ret) {
+ v4l2_err(&csi->v4l2_dev, "vb2_queue_init failed: %d\n", ret);
+ goto error;
+ }
+
+ /* Register video device */
+ strlcpy(vdev->name, name, sizeof(vdev->name));
+ vdev->release = video_device_release_empty;
+ vdev->fops = &sun6i_video_fops;
+ vdev->ioctl_ops = &sun6i_video_ioctl_ops;
+ vdev->vfl_type = VFL_TYPE_GRABBER;
+ vdev->vfl_dir = VFL_DIR_RX;
+ vdev->v4l2_dev = &csi->v4l2_dev;
+ vdev->queue = vidq;
+ vdev->lock = &video->lock;
+ vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE;
+ video_set_drvdata(vdev, video);
+
+ ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
+ if (ret < 0) {
+ v4l2_err(&csi->v4l2_dev,
+ "video_register_device failed: %d\n", ret);
+ goto error;
+ }
+
+ return 0;
+
+error:
+ sun6i_video_cleanup(video);
+ return ret;
+}
+
+void sun6i_video_cleanup(struct sun6i_video *video)
+{
+ if (video_is_registered(&video->vdev))
+ video_unregister_device(&video->vdev);
+
+ media_entity_cleanup(&video->vdev.entity);
+}
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_video.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_video.h
new file mode 100644
index 0000000..14eac6e
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_video.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2017 Yong Deng <yong.deng-+3dxTMOEIRNWk0Htik3J/w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SUN6I_VIDEO_H__
+#define __SUN6I_VIDEO_H__
+
+#include <media/v4l2-dev.h>
+#include <media/videobuf2-core.h>
+
+/*
+ * struct sun6i_csi_format - CSI media bus format information
+ * @fourcc: Fourcc code for this format
+ * @mbus_code: V4L2 media bus format code.
+ * @bpp: Bytes per pixel (when stored in memory)
+ */
+struct sun6i_csi_format {
+ u32 fourcc;
+ u32 mbus_code;
+ u8 bpp;
+};
+
+struct sun6i_csi;
+
+struct sun6i_video {
+ struct video_device vdev;
+ struct media_pad pad;
+ struct sun6i_csi *csi;
+
+ struct mutex lock;
+
+ struct vb2_queue vb2_vidq;
+ spinlock_t dma_queue_lock;
+ struct list_head dma_queue;
+
+ struct sun6i_csi_buffer *cur_frm;
+ unsigned int sequence;
+
+ struct sun6i_csi_format *formats;
+ unsigned int num_formats;
+ struct sun6i_csi_format *current_fmt;
+ struct v4l2_format fmt;
+};
+
+int sun6i_video_init(struct sun6i_video *video, struct sun6i_csi *csi,
+ const char *name);
+void sun6i_video_cleanup(struct sun6i_video *video);
+
+void sun6i_video_frame_done(struct sun6i_video *video);
+
+#endif /* __SUN6I_VIDEO_H__ */
--
1.8.3.1
^ permalink raw reply related
* [PATCH v3 0/3] Initial Allwinner V3s CSI Support
From: Yong Deng @ 2017-11-13 7:22 UTC (permalink / raw)
Cc: Yong Deng, Mauro Carvalho Chehab, Rob Herring, Mark Rutland,
Maxime Ripard, Chen-Yu Tsai, David S. Miller, Greg Kroah-Hartman,
Hans Verkuil, Randy Dunlap, Benoit Parrot, Stanimir Varbanov,
Arnd Bergmann, Hugues Fruchet, Philipp Zabel, Benjamin Gaignard,
Ramesh Shanmugasundaram, Yannick Fertre, Sakari Ailus, Rick Chang,
linux-media-u79uwXL29TY76Z2rM5mHXA, devicetree
This patchset add initial support for Allwinner V3s CSI.
Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
and CSI1 is used for parallel interface. This is not documented in
datasheet but by testing and guess.
This patchset implement a v4l2 framework driver and add a binding
documentation for it.
Currently, the driver only support the parallel interface. And has been
tested with a BT1120 signal which generating from FPGA. The following
fetures are not support with this patchset:
- ISP
- MIPI-CSI2
- Master clock for camera sensor
- Power regulator for the front end IC
Changes in v3:
* get rid of struct sun6i_csi_ops
* move sun6i-csi to new directory drivers/media/platform/sunxi
* merge sun6i_csi.c and sun6i_csi_v3s.c into sun6i_csi.c
* use generic fwnode endpoints parser
* only support a single subdev to make things simple
* many complaintion fix
Changes in v2:
* Change sunxi-csi to sun6i-csi
* Rebase to media_tree master branch
Following is the 'v4l2-compliance -s -f' output, I have test this
with both interlaced and progressive signal:
# ./v4l2-compliance -s -f
v4l2-compliance SHA : 7b2d48ff594dcc2c9b395463441e5abb4f5e9439
Driver Info:
Driver name : sun6i-video
Card type : sun6i-csi
Bus info : platform:csi
Driver version: 4.14.0
Capabilities : 0x84200001
Video Capture
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04200001
Video Capture
Streaming
Extended Pix Format
Compliance test for device /dev/video0 (not using libv4l2):
Required ioctls:
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second video open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 1 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Test input 0:
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK (Not Supported)
test VIDIOC_QUERYCTRL: OK (Not Supported)
test VIDIOC_G/S_CTRL: OK (Not Supported)
test VIDIOC_G/S/TRY_EXT_CTRLS: OK (Not Supported)
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK (Not Supported)
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 0 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
Test input 0:
Streaming ioctls:
test read/write: OK (Not Supported)
test MMAP: OK
test USERPTR: OK (Not Supported)
test DMABUF: Cannot test, specify --expbuf-device
Stream using all formats:
test MMAP for Format HM12, Frame Size 1920x1080:
Stride 2880, Field None: OK
test MMAP for Format NV12, Frame Size 1920x1080:
Stride 2880, Field None: OK
test MMAP for Format NV21, Frame Size 1920x1080:
Stride 2880, Field None: OK
test MMAP for Format YU12, Frame Size 1920x1080:
Stride 2880, Field None: OK
test MMAP for Format YV12, Frame Size 1920x1080:
Stride 2880, Field None: OK
test MMAP for Format NV16, Frame Size 1920x1080:
Stride 3840, Field None: OK
test MMAP for Format NV61, Frame Size 1920x1080:
Stride 3840, Field None: OK
test MMAP for Format 422P, Frame Size 1920x1080:
Stride 3840, Field None: OK
Total: 54, Succeeded: 54, Failed: 0, Warnings: 0
Yong Deng (3):
media: V3s: Add support for Allwinner CSI.
dt-bindings: media: Add Allwinner V3s Camera Sensor Interface (CSI)
media: MAINTAINERS: add entries for Allwinner V3s CSI
.../devicetree/bindings/media/sun6i-csi.txt | 51 ++
MAINTAINERS | 8 +
drivers/media/platform/Kconfig | 1 +
drivers/media/platform/Makefile | 2 +
drivers/media/platform/sunxi/sun6i-csi/Kconfig | 9 +
drivers/media/platform/sunxi/sun6i-csi/Makefile | 3 +
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 918 +++++++++++++++++++++
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h | 146 ++++
.../media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h | 203 +++++
.../media/platform/sunxi/sun6i-csi/sun6i_video.c | 722 ++++++++++++++++
.../media/platform/sunxi/sun6i-csi/sun6i_video.h | 61 ++
11 files changed, 2124 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/sun6i-csi.txt
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/Kconfig
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/Makefile
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/sun6i_video.c
create mode 100644 drivers/media/platform/sunxi/sun6i-csi/sun6i_video.h
--
1.8.3.1
^ permalink raw reply
* Re: Question about "unit address format error" of DTC
From: David Gibson @ 2017-11-13 5:27 UTC (permalink / raw)
To: Rob Herring
Cc: Masahiro Yamada, Devicetree Compiler,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAL_JsqLXRxz-VpFe5AC6NHu5UBvi8frt1CtEFSJH_JhaLDk8QQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
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On Fri, Nov 10, 2017 at 09:48:46AM -0600, Rob Herring wrote:
> On Thu, Nov 9, 2017 at 7:48 PM, Masahiro Yamada
> <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org> wrote:
> > Hi Rob,
> >
> > 2017-11-10 3:04 GMT+09:00 Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>:
> >> On Thu, Nov 9, 2017 at 9:09 AM, Masahiro Yamada
> >> <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org> wrote:
> >>> Hi Rob,
> >>>
> >>> 2017-11-09 23:15 GMT+09:00 Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>:
> >>>> On Thu, Nov 9, 2017 at 6:14 AM, Masahiro Yamada
> >>>> <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org> wrote:
> >>>>> Hi Rob, David,
> >>>>>
> >>>>>
> >>>>> I am just curious about a DTC warning.
> >>>>>
> >>>>>
> >>>>> For example,
> >>>>>
> >>>>> soc {
> >>>>> compatible = "simple-bus";
> >>>>> #address-cells = <1>;
> >>>>> #size-cells = <1>;
> >>>>> ranges;
> >>>>>
> >>>>> foo@11111111 {
> >>>>> compatible = "foo";
> >>>>> reg = <0x54006800 0x40>;
> >>>>> };
> >>>>> };
> >>>>>
> >>>>> This emits the following warning.
> >>>>>
> >>>>> Warning (simple_bus_reg): Node /soc/foo@11111111 simple-bus unit
> >>>>> address format error, expected "54006800"
> >>>>>
> >>>>>
> >>>>> But, if I replace "simple-bus" with "simple-mfd",
> >>>>> DTC is completely happy.
> >>>>
> >>>> We could probably add simple-mfd to the check. Though, if you have
> >>>> addresses, then you probably should use simple-bus. I'm not a bit fan
> >>>> of simple-mfd in general.
> >>>>
> >>>>> Why is this check limited to simple bus / PCI bus?
> >>>>
> >>>> Because bus types are free to define their own unit address format to
> >>>> some extent.
> >>>>
> >>>>> For other cases, is mismatching @<address> allowed?
> >>>>
> >>>> No, but it is not checked. Most other cases such as I2C and SPI buses
> >>>> aren't checked because we have no generic way to key off of them. We
> >>>> need schema data with compatible strings of those bus controllers to
> >>>> do the checking.
> >>>>
> >>>> Any bus type needs to define its unit address format. Generally, it
> >>>> must match data fields in reg property and distinct fields are
> >>>> separated by commas.
> >>>>
> >>>
> >>> Thanks.
> >>> I had a more specific example I wanted to ask,
> >>> but your last comment "distinct fields are separated by commas"
> >>> probably answered the question.
> >>>
> >>>
> >>> The following is an example of NVMEM data cells.
> >>> The generic binding is Documentation/devicetree/binding/nvmem/nvmem.txt
> >>>
> >>>
> >>> reg: specifies the offset in byte within the storage device.
> >>>
> >>> bits: Is pair of bit location and number of bits, which specifies offset
> >>> in bit and number of bits within the address range specified
> >>> by reg property.
> >>> Offset takes values from 0-7.
> >>>
> >>> So, it is possible to have multiple data cells
> >>> that share the same "reg".
> >>
> >> In hindsight, I think I'd do away with bits and just define that reg
> >> is the offset and size in bits. Maybe we did discuss that and I've
> >> just forgotten the reasons not to do that.
> >
> >
> > Yeah, I like the idea, but "in hindsight".
> >
> >
> >
> >>>
> >>> @<reg-offset>,<bit-position>
> >>> was the idea in my mind, but I was not 100% sure.
> >>
> >> Yeah, this is fine. Bonus points if you write a check in dtc for it. I
> >> think we can match on #nvmem-cells in the parent node.
> >
> >
> > I have no idea when I can look into it.
> >
> > I think most (all?) of DTC checks are from your contribution.
>
> Recently, yes. Except for fixing all my bugs. :)
>
> > It would be appreciated if you care to it.
>
> I'd appreciate contributions from others. :)
>
> > One idea for generic solution might be DTC checks:
> >
> > - @* exactly matches to reg
> >
> > or
> >
> > - The first field of comma separated @*,*,... matches to reg
>
> David rejected generic checks of the unit-address beyond what we have
> now. Part of the problem is what is valid vs. what is considered best
> practice today. Or to put another way, things we'd like to check and
> discourage, but aren't something we should fix in existing
> trees/bindings.
Right.
The problem is what does "matches to reg" mean. Equals reg rendered
as a hex string? That works for simple cases, but not for more
complex busses. That won't work for PCI - even the first element
before a , has to be deciphered from the devfn bits encoded within the
various words of the 'reg' address. A similar scheme would make sense
for many complex busses.
There are other variants to, like I think you can have things like
@i80 on old ISA busses to represent things in IO space rather than
MMIO space. Not much used nowadays, though.
But the point is that the formatting of the unit address is entirely
up to the bus type. In traditional OF the unit address could be
determined automatically, but that's because it didn't include just
the device tree, but actual methods for all the devices and busses
that knew how to correctly format the address from 'reg'.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: phy: Add Cygnus usb phy binding
From: Raveendra Padasalagi @ 2017-11-13 4:23 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, Kishon Vijay Abraham I, Russell King, Scott Branden,
Ray Jui, Srinath Mannam, Vikram Prakash, Jon Mason,
Florian Fainelli, Yoshihiro Shimoda, Raviteja Garimella,
Rafal Milecki, Arnd Bergmann, Viresh Kumar, Jaehoon Chung,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, bcm-kernel-feedback-list
In-Reply-To: <20171110214439.rlt5de2c6e6k246d@rob-hp-laptop>
Hi,
On Sat, Nov 11, 2017 at 3:14 AM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Wed, Nov 08, 2017 at 01:16:41PM +0530, Raveendra Padasalagi wrote:
>> Add devicetree binding document for broadcom's
>> Cygnus SoC specific usb phy controller driver.
>>
>> Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>> ---
>> .../bindings/phy/brcm,cygnus-usb-phy.txt | 106 +++++++++++++++++++++
>> 1 file changed, 106 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/brcm,cygnus-usb-phy.txt
>>
>> diff --git a/Documentation/devicetree/bindings/phy/brcm,cygnus-usb-phy.txt b/Documentation/devicetree/bindings/phy/brcm,cygnus-usb-phy.txt
>> new file mode 100644
>> index 0000000..bbc4b94
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/brcm,cygnus-usb-phy.txt
>> @@ -0,0 +1,106 @@
>> +BROADCOM CYGNUS USB PHY
>> +
>> +Required Properties:
>> +- compatible: brcm,cygnus-usb-phy
>> +- reg : the register start address and length for
>> + crmu_usbphy_aon_ctrl,
>> + cdru usb phy control,
>> + usb host idm registers,
>> + usb device idm registers.
>> +- reg-names: a list of the names corresponding to the previous register ranges
>> + Should contain
>> + "crmu-usbphy-aon-ctrl",
>> + "cdru-usbphy",
>> + "usb2h-idm",
>> + "usb2d-idm".
>> +- address-cells: should be 1
>> +- size-cells: should be 0
>> +
>> +Sub-nodes:
>> + Each port's PHY should be represented as a sub-node.
>> +
>> +Sub-nodes required properties:
>> +- reg: the PHY number
>> +- #phy-cells must be 1
>> + The node that uses the phy must provide 1 integer argument specifying
>> + port number.
>> +
>> +Optional Properties:
>> +- vbus-p#-supply : The regulator for vbus out control for the host
>
> Is this a literal # or something else?
Yes, this is a literal. It's assumed # will replace numeric 0-2 for
each of the ports.
In the example it's not shown as the regulators specified in vbus-p#-supply
are board specific.
>> + functionality enabled ports.
>> +- vbus-gpios: vbus gpio binding
>> + This is mandatory for port 2, as port 2 is used as dual role phy.
>> + Based on the vbus and id values device or host role is determined
>> + for phy 2.
>
> These optional properties don't match with the example.
vbus-gpios is placed by mistake here in the documentation,
this is no more required. I will remove it in the next version of the patch.
>> +
>> +- extcon: extcon phandle
>> + This is mandatory for port 2, as port 2 is used as dual role phy.
>> + extcon should be phandle to external usb gpio module which provide
>> + device or host role notifications based on the ID and VBUS gpio's state.
>> +
>> +
>> +Refer to phy/phy-bindings.txt for the generic PHY binding properties
>> +
>> +NOTE: port 0 and port 1 are host only and port 2 is dual role port.
>> +
>> +Example of phy :
>> + usbphy: usb-phy@0301c028 {
>> + compatible = "brcm,cygnus-usb-phy";
>> + reg = <0x0301c028 0x4>,
>> + <0x0301d1b4 0x5c>,
>> + <0x18115000 0xa00>,
>> + <0x18111000 0xa00>;
>> + reg-names = "crmu-usbphy-aon-ctrl", "cdru-usbphy",
>> + "usb2h-idm", "usb2d-idm";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + usbphy0: usb-phy@0 {
>> + reg = <0>;
>> + #phy-cells = <1>;
>> + };
>> +
>> + usbphy1: usb-phy@1 {
>> + reg = <1>;
>> + #phy-cells = <1>;
>> + };
>> +
>> + usbphy2: usb-phy@2 {
>> + reg = <2>;
>> + #phy-cells = <1>;
>> + extcon = <&extcon_usb>;
>> + };
>> + };
>> +
>> + extcon_usb: extcon_usb {
>> + compatible = "linux,extcon-usb-gpio";
>> + vbus-gpio = <&gpio_asiu 121 0>;
>> + id-gpio = <&gpio_asiu 122 0>;
>> + status = "okay";
>> + };
>> +
>> +
>> +Example of node using the phy:
>> +
>> + /* This nodes declares all three ports, port 0
>> + and port 1 are host and port 2 is device or host */
>> +
>> + ehci0: usb@18048000 {
>> + compatible = "generic-ehci";
>> + reg = <0x18048000 0x100>;
>> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> + phys = <&usbphy0 0 &usbphy1 1 &usbphy2 2>;
>> + phy-names = "usbp0","usbp1","usbp2";
>> + status = "okay";
>
> Don't show status in examples.
Ok, Thanks. I will update it in the next version of the patch.
>> + };
>> +
>> + /* This node declares port 2 phy
>> + and configures it for device */
>> +
>> + usbd_udc_dwc1: usb@1804c000 {
>> + compatible = "iproc-udc";
>> + reg = <0x1804c000 0x2000>;
>> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
>> + phys = <&usbphy2 2>;
>> + phy-names = "usbdrd";
>> + };
>> --
>> 1.9.1
>>
--
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^ permalink raw reply
* RE: [PATCHv4 2/3] ARMv8: layerscape: add the pcie ep function support
From: Xiaowei Bao @ 2017-11-13 4:02 UTC (permalink / raw)
To: Kishon Vijay Abraham I,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
catalin.marinas-5wv7dgnIgG8@public.gmane.org,
will.deacon-5wv7dgnIgG8@public.gmane.org,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
Madalin-cristian Bucur, Sumit Garg, Y.b. Lu,
hongtao.jia-3arQi8VN3Tc@public.gmane.org, Andy Tang, Leo Li,
jingoohan1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
pbrobinson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
songxiaowei-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWOunwaRDDq4rA
In-Reply-To: <d02ec499-5de5-11fe-9d95-591513037d49-l0cyMroinI0@public.gmane.org>
> -----Original Message-----
> From: Kishon Vijay Abraham I [mailto:kishon-l0cyMroinI0@public.gmane.org]
> Sent: Friday, November 10, 2017 2:32 PM
> To: Xiaowei Bao <xiaowei.bao-3arQi8VN3Tc@public.gmane.org>; robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org;
> mark.rutland-5wv7dgnIgG8@public.gmane.org; catalin.marinas-5wv7dgnIgG8@public.gmane.org; will.deacon-5wv7dgnIgG8@public.gmane.org;
> bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org; shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; Madalin-cristian Bucur
> <madalin.bucur-3arQi8VN3Tc@public.gmane.org>; Sumit Garg <sumit.garg-3arQi8VN3Tc@public.gmane.org>; Y.b. Lu
> <yangbo.lu-3arQi8VN3Tc@public.gmane.org>; hongtao.jia-3arQi8VN3Tc@public.gmane.org; Andy Tang
> <andy.tang-3arQi8VN3Tc@public.gmane.org>; Leo Li <leoyang.li-3arQi8VN3Tc@public.gmane.org>; jingoohan1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org;
> pbrobinson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; songxiaowei-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org;
> devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; linux-
> kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-
> dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org; Z.q. Hou <zhiqiang.hou-3arQi8VN3Tc@public.gmane.org>; Mingkai Hu
> <mingkai.hu-3arQi8VN3Tc@public.gmane.org>; M.h. Lian <minghuan.lian-3arQi8VN3Tc@public.gmane.org>
> Subject: Re: [PATCHv4 2/3] ARMv8: layerscape: add the pcie ep function support
>
> Hi,
>
> On Friday 10 November 2017 09:18 AM, Bao Xiaowei wrote:
> > Add the pcie controller ep function support of layerscape base on pcie
> > ep framework.
> >
> > Signed-off-by: Bao Xiaowei <xiaowei.bao-3arQi8VN3Tc@public.gmane.org>
> > ---
> > v2:
> > - fix the ioremap function used but no ioumap issue
> > - optimize the code structure
> > - add code comments
> > v3:
> > - fix the msi outband window request failed issue
> > v4:
> > - optimize the code, adjust the format
> >
> > drivers/pci/dwc/pci-layerscape.c | 120
> > ++++++++++++++++++++++++++++++++++++---
> > 1 file changed, 113 insertions(+), 7 deletions(-)
>
> $subject should begin with
> PCI: layerscape:
> >
> > diff --git a/drivers/pci/dwc/pci-layerscape.c
> > b/drivers/pci/dwc/pci-layerscape.c
> > index 87fa486bee2c..6f3e434599e0 100644
> > --- a/drivers/pci/dwc/pci-layerscape.c
> > +++ b/drivers/pci/dwc/pci-layerscape.c
> > @@ -34,7 +34,12 @@
> > /* PEX Internal Configuration Registers */
> > #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask
> Register1 */
> >
> > +#define PCIE_DBI2_BASE 0x1000 /* DBI2 base address*/
>
> The base address should come from dt.
We get the dbi base address form dt, and this is the offset base on the dbi base address, if the follow patch is merged, this define is not needed.
> > +#define PCIE_MSI_MSG_DATA_OFF 0x5c /* MSI Data register address*/
> > +#define PCIE_MSI_OB_SIZE 4096
> > +#define PCIE_MSI_ADDR_OFFSET (1024 * 1024)
> > #define PCIE_IATU_NUM 6
> > +#define PCIE_EP_ADDR_SPACE_SIZE 0x100000000
> >
> > struct ls_pcie_drvdata {
> > u32 lut_offset;
> > @@ -44,12 +49,20 @@ struct ls_pcie_drvdata {
> > const struct dw_pcie_ops *dw_pcie_ops; };
> >
> > +struct ls_pcie_ep {
> > + dma_addr_t msi_phys_addr;
> > + void __iomem *msi_virt_addr;
> > + u64 msi_msg_addr;
> > + u16 msi_msg_data;
> > +};
> > +
> > struct ls_pcie {
> > struct dw_pcie *pci;
> > void __iomem *lut;
> > struct regmap *scfg;
> > const struct ls_pcie_drvdata *drvdata;
> > int index;
> > + struct ls_pcie_ep *pcie_ep;
> > };
> >
> > #define to_ls_pcie(x) dev_get_drvdata((x)->dev)
> > @@ -263,6 +276,99 @@ static const struct of_device_id ls_pcie_of_match[] =
> {
> > { },
> > };
> >
> > +static void ls_pcie_raise_msi_irq(struct ls_pcie_ep *pcie_ep) {
> > + iowrite32(pcie_ep->msi_msg_data, pcie_ep->msi_virt_addr); }
> > +
> > +static int ls_pcie_raise_irq(struct dw_pcie_ep *ep,
> > + enum pci_epc_irq_type type, u8 interrupt_num) {
> > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > + struct ls_pcie *pcie = to_ls_pcie(pci);
> > + struct ls_pcie_ep *pcie_ep = pcie->pcie_ep;
> > + u32 free_win;
> > +
> > + /* get the msi message address and msi message data */
> > + pcie_ep->msi_msg_addr = ioread32(pci->dbi_base +
> MSI_MESSAGE_ADDR_L32) |
> > + (((u64)ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_U32)) <<
> 32);
> > + pcie_ep->msi_msg_data = ioread16(pci->dbi_base +
> > +PCIE_MSI_MSG_DATA_OFF);
> > +
> > + /* request and config the outband window for msi */
> > + free_win = find_first_zero_bit(&ep->ob_window_map,
> > + sizeof(ep->ob_window_map));
> > + if (free_win >= ep->num_ob_windows) {
> > + dev_err(pci->dev, "no free outbound window\n");
> > + return -ENOMEM;
> > + }
> > +
> > + dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
> > + pcie_ep->msi_phys_addr,
> > + pcie_ep->msi_msg_addr,
> > + PCIE_MSI_OB_SIZE);
> > +
> > + set_bit(free_win, &ep->ob_window_map);
>
> This custom logic is not required. You can use [1] instead
>
> [1] ->
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flkml.or
> g%2Flkml%2F2017%2F11%2F3%2F318&data=02%7C01%7Cxiaowei.bao%40nxp.
> com%7Cdefeb10941b145bc81ac08d528051939%7C686ea1d3bc2b4c6fa92cd99c
> 5c301635%7C0%7C0%7C636458924733901810&sdata=3TMGeoj3L9SlNsXeAYN
> %2BSe0K1Orv3xb7Ah9G%2BD9k4Rg%3D&reserved=0
These patchs have not merged on the latest kernel, yes? I will test it when these patchs merged, analyzed the patch, it is viable for ls1046a platform.
> > +
> > + /* generate the msi interrupt */
> > + ls_pcie_raise_msi_irq(pcie_ep);
> > +
> > + /* release the outband window of msi */
> > + dw_pcie_disable_atu(pci, free_win, DW_PCIE_REGION_OUTBOUND);
> > + clear_bit(free_win, &ep->ob_window_map);
> > +
> > + return 0;
> > +}
> > +
> > +static struct dw_pcie_ep_ops pcie_ep_ops = {
> > + .raise_irq = ls_pcie_raise_irq,
> > +};
> > +
> > +static int __init ls_add_pcie_ep(struct ls_pcie *pcie,
> > + struct platform_device *pdev)
> > +{
> > + struct dw_pcie *pci = pcie->pci;
> > + struct device *dev = pci->dev;
> > + struct dw_pcie_ep *ep;
> > + struct ls_pcie_ep *pcie_ep;
> > + struct resource *cfg_res;
> > + int ret;
> > +
> > + ep = &pci->ep;
> > + ep->ops = &pcie_ep_ops;
> > +
> > + pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
> > + if (!pcie_ep)
> > + return -ENOMEM;
> > +
> > + pcie->pcie_ep = pcie_ep;
> > +
> > + cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> "config");
> > + if (cfg_res) {
> > + ep->phys_base = cfg_res->start;
> > + ep->addr_size = PCIE_EP_ADDR_SPACE_SIZE;
> > + } else {
> > + dev_err(dev, "missing *config* space\n");
> > + return -ENODEV;
> > + }
> > +
> > + pcie_ep->msi_phys_addr = ep->phys_base + PCIE_MSI_ADDR_OFFSET;
> > +
> > + pcie_ep->msi_virt_addr = ioremap(pcie_ep->msi_phys_addr,
> > + PCIE_MSI_OB_SIZE);
> > + if (!pcie_ep->msi_virt_addr) {
> > + dev_err(dev, "failed to map MSI outbound region\n");
> > + return -ENOMEM;
> > + }
> > +
> > + ret = dw_pcie_ep_init(ep);
> > + if (ret) {
> > + dev_err(dev, "failed to initialize endpoint\n");
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > static int __init ls_add_pcie_port(struct ls_pcie *pcie) {
> > struct dw_pcie *pci = pcie->pci;
> > @@ -309,18 +415,18 @@ static int __init ls_pcie_probe(struct
> platform_device *pdev)
> > if (IS_ERR(pci->dbi_base))
> > return PTR_ERR(pci->dbi_base);
> >
> > - pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
> > + pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_BASE;
> >
> > - if (!ls_pcie_is_bridge(pcie))
> > - return -ENODEV;
> > + pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
> >
> > platform_set_drvdata(pdev, pcie);
> >
> > - ret = ls_add_pcie_port(pcie);
> > - if (ret < 0)
> > - return ret;
> > + if (!ls_pcie_is_bridge(pcie))
> > + ret = ls_add_pcie_ep(pcie, pdev);
>
> HOST or EP mode should be obtained directly from dt.
The RC or EP mode can configured by the rcw, we can't obtain the RC or EP mode from the dt, we can obtain the RC or EP mode by reading the specific register in code.
>
> Thanks
> Kishon
--
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^ permalink raw reply
* [PATCH v4 3/3] hwmon: (w83773g) Add documentation
From: Lei YU @ 2017-11-13 3:27 UTC (permalink / raw)
To: Mark Rutland, Jean Delvare, Guenter Roeck, Jonathan Corbet,
Jiri Kosina
Cc: Lei YU, devicetree, linux-kernel, linux-hwmon, Joel Stanley,
Andrew Jeffery
In-Reply-To: <1510543655-27059-1-git-send-email-mine260309@gmail.com>
Add documentation for the w83773g driver.
Signed-off-by: Lei YU <mine260309@gmail.com>
---
v2:
- Add notes for offset and update_interval
---
Documentation/hwmon/w83773g | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/hwmon/w83773g
diff --git a/Documentation/hwmon/w83773g b/Documentation/hwmon/w83773g
new file mode 100644
index 0000000..4cc6c0b
--- /dev/null
+++ b/Documentation/hwmon/w83773g
@@ -0,0 +1,33 @@
+Kernel driver w83773g
+====================
+
+Supported chips:
+ * Nuvoton W83773G
+ Prefix: 'w83773g'
+ Addresses scanned: I2C 0x4c and 0x4d
+ Datasheet: https://www.nuvoton.com/resource-files/W83773G_SG_DatasheetV1_2.pdf
+
+Authors:
+ Lei YU <mine260309@gmail.com>
+
+Description
+-----------
+
+This driver implements support for Nuvoton W83773G temperature sensor
+chip. This chip implements one local and two remote sensors.
+The chip also features offsets for the two remote sensors which get added to
+the input readings. The chip does all the scaling by itself and the driver
+therefore reports true temperatures that don't need any user-space adjustments.
+Temperature is measured in degrees Celsius.
+The chip is wired over I2C/SMBus and specified over a temperature
+range of -40 to +125 degrees Celsius (for local sensor) and -40 to +127
+degrees Celsius (for remote sensors).
+Resolution for both the local and remote channels is 0.125 degree C.
+
+The chip supports only temperature measurement. The driver exports
+the temperature values via the following sysfs files:
+
+temp[1-3]_input
+temp[2-3]_fault
+temp[2-3]_offset
+update_interval
--
1.9.1
^ permalink raw reply related
* [PATCH v4 2/3] drivers: hwmon: Add W83773G driver
From: Lei YU @ 2017-11-13 3:27 UTC (permalink / raw)
To: Mark Rutland, Jean Delvare, Guenter Roeck, Jonathan Corbet,
Jiri Kosina
Cc: Lei YU, devicetree, linux-kernel, linux-hwmon, Joel Stanley,
Andrew Jeffery
In-Reply-To: <1510543655-27059-1-git-send-email-mine260309@gmail.com>
Nuvoton W83773G is a hardware monitor IC providing one local
temperature and two remote temperature sensors.
Signed-off-by: Lei YU <mine260309@gmail.com>
---
v2:
- Rewrite the driver using regmap
- Add offset and update_interval
v3:
- Use devm_hwmon_device_register_with_info() with is_visible/read/write
functions.
v4:
- Fix review comments.
---
drivers/hwmon/Kconfig | 10 ++
drivers/hwmon/Makefile | 1 +
drivers/hwmon/w83773g.c | 329 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 340 insertions(+)
create mode 100644 drivers/hwmon/w83773g.c
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index d654314..11c6248 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1710,6 +1710,16 @@ config SENSORS_VT8231
This driver can also be built as a module. If so, the module
will be called vt8231.
+config SENSORS_W83773G
+ tristate "Nuvoton W83773G"
+ depends on I2C
+ help
+ If you say yes here you get support for the Nuvoton W83773G hardware
+ monitoring chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called w83773g.
+
config SENSORS_W83781D
tristate "Winbond W83781D, W83782D, W83783S, Asus AS99127F"
depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index c84d978..0649ad8 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SENSORS_ATK0110) += asus_atk0110.o
# asb100, then w83781d go first, as they can override other drivers' addresses.
obj-$(CONFIG_SENSORS_ASB100) += asb100.o
obj-$(CONFIG_SENSORS_W83627HF) += w83627hf.o
+obj-$(CONFIG_SENSORS_W83773G) += w83773g.o
obj-$(CONFIG_SENSORS_W83792D) += w83792d.o
obj-$(CONFIG_SENSORS_W83793) += w83793.o
obj-$(CONFIG_SENSORS_W83795) += w83795.o
diff --git a/drivers/hwmon/w83773g.c b/drivers/hwmon/w83773g.c
new file mode 100644
index 0000000..0b97c28
--- /dev/null
+++ b/drivers/hwmon/w83773g.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright (C) 2017 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Driver for the Nuvoton W83773G SMBus temperature sensor IC.
+ * Supported models: W83773G
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/err.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+
+/* W83773 has 3 channels */
+#define W83773_CHANNELS 3
+
+/* The W83773 registers */
+#define W83773_CONVERSION_RATE_REG_READ 0x04
+#define W83773_CONVERSION_RATE_REG_WRITE 0x0A
+#define W83773_MANUFACTURER_ID_REG 0xFE
+#define W83773_LOCAL_TEMP 0x00
+
+static const u8 W83773_STATUS[2] = { 0x02, 0x17 };
+
+static const u8 W83773_TEMP_LSB[2] = { 0x10, 0x25 };
+static const u8 W83773_TEMP_MSB[2] = { 0x01, 0x24 };
+
+static const u8 W83773_OFFSET_LSB[2] = { 0x12, 0x16 };
+static const u8 W83773_OFFSET_MSB[2] = { 0x11, 0x15 };
+
+/* this is the number of sensors in the device */
+static const struct i2c_device_id w83773_id[] = {
+ { "w83773g" },
+ { }
+};
+
+MODULE_DEVICE_TABLE(i2c, w83773_id);
+
+static const struct of_device_id w83773_of_match[] = {
+ {
+ .compatible = "nuvoton,w83773g"
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, w83773_of_match);
+
+static inline long temp_of_local(s8 reg)
+{
+ return reg * 1000;
+}
+
+static inline long temp_of_remote(s8 hb, u8 lb)
+{
+ return (hb << 3 | lb >> 5) * 125;
+}
+
+static int get_local_temp(struct regmap *regmap, long *val)
+{
+ unsigned int regval;
+ int ret;
+
+ ret = regmap_read(regmap, W83773_LOCAL_TEMP, ®val);
+ if (ret < 0)
+ return ret;
+
+ *val = temp_of_local(regval);
+ return 0;
+}
+
+static int get_remote_temp(struct regmap *regmap, int index, long *val)
+{
+ unsigned int regval_high;
+ unsigned int regval_low;
+ int ret;
+
+ ret = regmap_read(regmap, W83773_TEMP_MSB[index], ®val_high);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_read(regmap, W83773_TEMP_LSB[index], ®val_low);
+ if (ret < 0)
+ return ret;
+
+ *val = temp_of_remote(regval_high, regval_low);
+ return 0;
+}
+
+static int get_fault(struct regmap *regmap, int index, long *val)
+{
+ unsigned int regval;
+ int ret;
+
+ ret = regmap_read(regmap, W83773_STATUS[index], ®val);
+ if (ret < 0)
+ return ret;
+
+ *val = (u8)regval & 0x04 >> 2;
+ return 0;
+}
+
+static int get_offset(struct regmap *regmap, int index, long *val)
+{
+ unsigned int regval_high;
+ unsigned int regval_low;
+ int ret;
+
+ ret = regmap_read(regmap, W83773_OFFSET_MSB[index], ®val_high);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_read(regmap, W83773_OFFSET_LSB[index], ®val_low);
+ if (ret < 0)
+ return ret;
+
+ *val = temp_of_remote(regval_high, regval_low);
+ return 0;
+}
+
+static int set_offset(struct regmap *regmap, int index, long val)
+{
+ int ret;
+ u8 high_byte;
+ u8 low_byte;
+
+ val = clamp_val(val, -127825, 127825);
+ /* offset value equals to (high_byte << 3 | low_byte >> 5) * 125 */
+ val /= 125;
+ high_byte = val >> 3;
+ low_byte = (val & 0x07) << 5;
+
+ ret = regmap_write(regmap, W83773_OFFSET_MSB[index], high_byte);
+ if (ret < 0)
+ return ret;
+
+ return regmap_write(regmap, W83773_OFFSET_LSB[index], low_byte);
+}
+
+static int get_update_interval(struct regmap *regmap, long *val)
+{
+ unsigned int regval;
+ int ret;
+
+ ret = regmap_read(regmap, W83773_CONVERSION_RATE_REG_READ, ®val);
+ if (ret < 0)
+ return ret;
+
+ *val = 16000 >> regval;
+ return 0;
+}
+
+static int set_update_interval(struct regmap *regmap, long val)
+{
+ int rate;
+
+ /*
+ * For valid rates, interval can be calculated as
+ * interval = (1 << (8 - rate)) * 62.5;
+ * Rounded rate is therefore
+ * rate = 8 - __fls(interval * 8 / (62.5 * 7));
+ * Use clamp_val() to avoid overflows, and to ensure valid input
+ * for __fls.
+ */
+ val = clamp_val(val, 62, 16000) * 10;
+ rate = 8 - __fls((val * 8 / (625 * 7)));
+ return regmap_write(regmap, W83773_CONVERSION_RATE_REG_WRITE, rate);
+}
+
+static int w83773_read(struct device *dev, enum hwmon_sensor_types type,
+ u32 attr, int channel, long *val)
+{
+ struct regmap *regmap = dev_get_drvdata(dev);
+
+ if (type == hwmon_chip) {
+ if (attr == hwmon_chip_update_interval)
+ return get_update_interval(regmap, val);
+ return -EOPNOTSUPP;
+ }
+
+ switch (attr) {
+ case hwmon_temp_input:
+ if (channel == 0)
+ return get_local_temp(regmap, val);
+ return get_remote_temp(regmap, channel - 1, val);
+ case hwmon_temp_fault:
+ return get_fault(regmap, channel - 1, val);
+ case hwmon_temp_offset:
+ return get_offset(regmap, channel - 1, val);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int w83773_write(struct device *dev, enum hwmon_sensor_types type,
+ u32 attr, int channel, long val)
+{
+ struct regmap *regmap = dev_get_drvdata(dev);
+
+ if (type == hwmon_chip && attr == hwmon_chip_update_interval)
+ return set_update_interval(regmap, val);
+
+ if (type == hwmon_temp && attr == hwmon_temp_offset)
+ return set_offset(regmap, channel - 1, val);
+
+ return -EOPNOTSUPP;
+}
+
+static umode_t w83773_is_visible(const void *data, enum hwmon_sensor_types type,
+ u32 attr, int channel)
+{
+ switch (type) {
+ case hwmon_chip:
+ switch (attr) {
+ case hwmon_chip_update_interval:
+ return 0644;
+ }
+ break;
+ case hwmon_temp:
+ switch (attr) {
+ case hwmon_temp_input:
+ case hwmon_temp_fault:
+ return 0444;
+ case hwmon_temp_offset:
+ return 0644;
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static const u32 w83773_chip_config[] = {
+ HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
+ 0
+};
+
+static const struct hwmon_channel_info w83773_chip = {
+ .type = hwmon_chip,
+ .config = w83773_chip_config,
+};
+
+static const u32 w83773_temp_config[] = {
+ HWMON_T_INPUT,
+ HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_OFFSET,
+ HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_OFFSET,
+ 0
+};
+
+static const struct hwmon_channel_info w83773_temp = {
+ .type = hwmon_temp,
+ .config = w83773_temp_config,
+};
+
+static const struct hwmon_channel_info *w83773_info[] = {
+ &w83773_chip,
+ &w83773_temp,
+ NULL
+};
+
+static const struct hwmon_ops w83773_ops = {
+ .is_visible = w83773_is_visible,
+ .read = w83773_read,
+ .write = w83773_write,
+};
+
+static const struct hwmon_chip_info w83773_chip_info = {
+ .ops = &w83773_ops,
+ .info = w83773_info,
+};
+
+static const struct regmap_config w83773_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+};
+
+static int w83773_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct device *dev = &client->dev;
+ struct device *hwmon_dev;
+ struct regmap *regmap;
+ int ret;
+
+ regmap = devm_regmap_init_i2c(client, &w83773_regmap_config);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "failed to allocate register map\n");
+ return PTR_ERR(regmap);
+ }
+
+ /* Set the conversion rate to 2 Hz */
+ ret = regmap_write(regmap, W83773_CONVERSION_RATE_REG_WRITE, 0x05);
+ if (ret < 0) {
+ dev_err(&client->dev, "error writing config rate register\n");
+ return ret;
+ }
+
+ i2c_set_clientdata(client, regmap);
+
+ hwmon_dev = devm_hwmon_device_register_with_info(dev,
+ client->name,
+ regmap,
+ &w83773_chip_info,
+ NULL);
+ return PTR_ERR_OR_ZERO(hwmon_dev);
+}
+
+static struct i2c_driver w83773_driver = {
+ .class = I2C_CLASS_HWMON,
+ .driver = {
+ .name = "w83773g",
+ .of_match_table = of_match_ptr(w83773_of_match),
+ },
+ .probe = w83773_probe,
+ .id_table = w83773_id,
+};
+
+module_i2c_driver(w83773_driver);
+
+MODULE_AUTHOR("Lei YU <mine260309@gmail.com>");
+MODULE_DESCRIPTION("W83773G temperature sensor driver");
+MODULE_LICENSE("GPL");
--
1.9.1
^ permalink raw reply related
* [PATCH v4 1/3] DT: i2c: W83773G is a trivial device
From: Lei YU @ 2017-11-13 3:27 UTC (permalink / raw)
To: Mark Rutland, Jean Delvare, Guenter Roeck, Jonathan Corbet,
Jiri Kosina
Cc: Lei YU, devicetree, linux-kernel, linux-hwmon, Joel Stanley,
Andrew Jeffery
In-Reply-To: <1510543655-27059-1-git-send-email-mine260309@gmail.com>
Signed-off-by: Lei YU <mine260309@gmail.com>
---
Documentation/devicetree/bindings/trivial-devices.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt
index af284fb..63ad2f1 100644
--- a/Documentation/devicetree/bindings/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/trivial-devices.txt
@@ -188,3 +188,4 @@ ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Inter
ti,tmp275 Digital Temperature Sensor
winbond,w83793 Winbond/Nuvoton H/W Monitor
winbond,wpct301 i2c trusted platform module (TPM)
+nuvoton,w83773g Nuvoton Temperature Sensor
--
1.9.1
^ permalink raw reply related
* [PATCH v4 0/3] Add W83773G hwmon sensor driver and doc
From: Lei YU @ 2017-11-13 3:27 UTC (permalink / raw)
To: Mark Rutland, Jean Delvare, Guenter Roeck, Jonathan Corbet,
Jiri Kosina
Cc: Lei YU, devicetree, linux-kernel, linux-hwmon, Joel Stanley,
Andrew Jeffery
Nuvoton W83773G is a hardware monitoring chip, which integrates two remote
and one local temperature sensors.
---
v2:
- The driver is re-written as v1's comment, so the author is changed to me.
- Added the device to trivial-devices.txt
v3:
- Update the driver to use new API devm_hwmon_device_register_with_info()
v4:
- Fix review comments
Lei YU (3):
DT: i2c: W83773G is a trivial device
drivers: hwmon: Add W83773G driver
hwmon: (w83773g) Add documentation
.../devicetree/bindings/trivial-devices.txt | 1 +
Documentation/hwmon/w83773g | 33 +++
drivers/hwmon/Kconfig | 10 +
drivers/hwmon/Makefile | 1 +
drivers/hwmon/w83773g.c | 329 +++++++++++++++++++++
5 files changed, 374 insertions(+)
create mode 100644 Documentation/hwmon/w83773g
create mode 100644 drivers/hwmon/w83773g.c
--
1.9.1
^ permalink raw reply
* Re: [PATCH v3 2/3] drivers: hwmon: Add W83773G driver
From: Lei YU @ 2017-11-13 2:52 UTC (permalink / raw)
To: Guenter Roeck
Cc: Mark Rutland, Jean Delvare, Jonathan Corbet, Jiri Kosina,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-hwmon-u79uwXL29TY76Z2rM5mHXA, Joel Stanley, Andrew Jeffery
In-Reply-To: <2747fc2e-0120-cc14-991e-3f5baa4a0780-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
On Fri, Nov 10, 2017 at 10:49 PM, Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org> wrote:
> On 11/08/2017 11:09 PM, Lei YU wrote:
>>
>> Nuvoton W83773G is a hardware monitor IC providing one local
>> temperature and two remote temperature sensors.
>>
>> Signed-off-by: Lei YU <mine260309-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
>
> Nicely done. Couple of nitpicks left.
>
> Thanks!
> Guenter
>
>
>> ---
>> v2:
>> - Rewrite the driver using regmap
>> - Add offset and update_interval
>> v3:
>> - Use devm_hwmon_device_register_with_info() with is_visible/read/write
>> functions.
>> ---
>> drivers/hwmon/Kconfig | 10 ++
>> drivers/hwmon/Makefile | 1 +
>> drivers/hwmon/w83773g.c | 348
>> ++++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 359 insertions(+)
>> create mode 100644 drivers/hwmon/w83773g.c
>>
>> diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
>> index d654314..11c6248 100644
>> --- a/drivers/hwmon/Kconfig
>> +++ b/drivers/hwmon/Kconfig
>> @@ -1710,6 +1710,16 @@ config SENSORS_VT8231
>> This driver can also be built as a module. If so, the module
>> will be called vt8231.
>> +config SENSORS_W83773G
>> + tristate "Nuvoton W83773G"
>> + depends on I2C
>> + help
>> + If you say yes here you get support for the Nuvoton W83773G
>> hardware
>> + monitoring chip.
>> +
>> + This driver can also be built as a module. If so, the module
>> + will be called w83773g.
>> +
>> config SENSORS_W83781D
>> tristate "Winbond W83781D, W83782D, W83783S, Asus AS99127F"
>> depends on I2C
>> diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
>> index c84d978..0649ad8 100644
>> --- a/drivers/hwmon/Makefile
>> +++ b/drivers/hwmon/Makefile
>> @@ -13,6 +13,7 @@ obj-$(CONFIG_SENSORS_ATK0110) += asus_atk0110.o
>> # asb100, then w83781d go first, as they can override other drivers'
>> addresses.
>> obj-$(CONFIG_SENSORS_ASB100) += asb100.o
>> obj-$(CONFIG_SENSORS_W83627HF) += w83627hf.o
>> +obj-$(CONFIG_SENSORS_W83773G) += w83773g.o
>> obj-$(CONFIG_SENSORS_W83792D) += w83792d.o
>> obj-$(CONFIG_SENSORS_W83793) += w83793.o
>> obj-$(CONFIG_SENSORS_W83795) += w83795.o
>> diff --git a/drivers/hwmon/w83773g.c b/drivers/hwmon/w83773g.c
>> new file mode 100644
>> index 0000000..58ac45b
>> --- /dev/null
>> +++ b/drivers/hwmon/w83773g.c
>> @@ -0,0 +1,348 @@
>> +/*
>> + * Copyright (C) 2017 IBM Corp.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * Driver for the Nuvoton W83773G SMBus temperature sensor IC.
>> + * Supported models: W83773G
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/init.h>
>> +#include <linux/i2c.h>
>> +#include <linux/hwmon.h>
>> +#include <linux/hwmon-sysfs.h>
>> +#include <linux/err.h>
>> +#include <linux/of_device.h>
>> +#include <linux/regmap.h>
>> +
>> +/* Addresses to scan */
>> +static const unsigned short normal_i2c[] = { 0x4c, 0x4d, I2C_CLIENT_END
>> };
>> +
>> +/* W83773 has 3 channels */
>> +#define W83773_CHANNELS 3
>> +
>> +/* The W83773 registers */
>> +#define W83773_CONVERSION_RATE_REG_READ 0x04
>> +#define W83773_CONVERSION_RATE_REG_WRITE 0x0A
>> +#define W83773_MANUFACTURER_ID_REG 0xFE
>> +#define W83773_LOCAL_TEMP 0x00
>> +
>> +static const u8 W83773_STATUS[2] = { 0x02, 0x17 };
>> +
>> +static const u8 W83773_TEMP_LSB[2] = { 0x10, 0x25 };
>> +static const u8 W83773_TEMP_MSB[2] = { 0x01, 0x24 };
>> +
>> +static const u8 W83773_OFFSET_LSB[2] = { 0x12, 0x16 };
>> +static const u8 W83773_OFFSET_MSB[2] = { 0x11, 0x15 };
>> +
>> +/* this is the number of sensors in the device */
>> +static const struct i2c_device_id w83773_id[] = {
>> + { "w83773g" },
>> + { }
>> +};
>> +
>> +MODULE_DEVICE_TABLE(i2c, w83773_id);
>> +
>> +static const struct of_device_id w83773_of_match[] = {
>> + {
>> + .compatible = "nuvoton,w83773g"
>> + },
>> + { },
>> +};
>> +MODULE_DEVICE_TABLE(of, w83773_of_match);
>> +
>> +static inline long temp_of_local(s8 reg)
>> +{
>> + return reg * 1000;
>> +}
>> +
>> +static inline long temp_of_remote(s8 hb, u8 lb)
>> +{
>> + return (hb << 3 | lb >> 5) * 125;
>> +}
>> +
>> +static int get_local_temp(struct regmap *regmap, long *val)
>> +{
>> + unsigned int regval;
>> + int ret;
>> +
>> + ret = regmap_read(regmap, W83773_LOCAL_TEMP, ®val);
>> + if (ret < 0)
>> + return ret;
>> +
>> + *val = temp_of_local(regval);
>> + return 0;
>> +}
>> +
>> +static int get_remote_temp(struct regmap *regmap, int index, long *val)
>> +{
>> + unsigned int regval_high;
>> + unsigned int regval_low;
>> + int ret;
>> +
>> + ret = regmap_read(regmap, W83773_TEMP_MSB[index], ®val_high);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = regmap_read(regmap, W83773_TEMP_LSB[index], ®val_low);
>> + if (ret < 0)
>> + return ret;
>> +
>> + *val = temp_of_remote(regval_high, regval_low);
>> + return 0;
>> +}
>> +
>> +static int get_fault(struct regmap *regmap, int index, long *val)
>> +{
>> + unsigned int regval;
>> + int ret;
>> +
>> + ret = regmap_read(regmap, W83773_STATUS[index], ®val);
>> +
>
> Drop the empty line please.
>
Will be fixed in v4.
>
>> + if (ret < 0)
>> + return ret;
>> +
>> + *val = (u8)regval & 0x04 >> 2;
>> + return 0;
>> +}
>> +
>> +static int get_offset(struct regmap *regmap, int index, long *val)
>> +{
>> + unsigned int regval_high;
>> + unsigned int regval_low;
>> + int ret;
>> +
>> + ret = regmap_read(regmap, W83773_OFFSET_MSB[index], ®val_high);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = regmap_read(regmap, W83773_OFFSET_LSB[index], ®val_low);
>> + if (ret < 0)
>> + return ret;
>> +
>> + *val = temp_of_remote(regval_high, regval_low);
>> + return 0;
>> +}
>> +
>> +static int set_offset(struct regmap *regmap, int index, long val)
>> +{
>> + int ret;
>> + u8 high_byte;
>> + u8 low_byte;
>> +
>> + val = clamp_val(val, -127825, 127825);
>> + /* offset value equals to (high_byte << 3 | low_byte >> 5) * 125
>> */
>> + val /= 125;
>> + high_byte = val >> 3;
>> + low_byte = (val & 0x07) << 5;
>> +
>> + ret = regmap_write(regmap, W83773_OFFSET_MSB[index], high_byte);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = regmap_write(regmap, W83773_OFFSET_LSB[index], low_byte);
>> + if (ret < 0)
>> + return ret;
>> +
>> + return 0;
>
>
> For the second call,
>
> return regmap_write(regmap, W83773_OFFSET_LSB[index], low_byte);
>
Will be fixed in v4.
>> +}
>> +
>> +static int get_update_interval(struct regmap *regmap, long *val)
>> +{
>> + unsigned int regval;
>> + int ret;
>> +
>> + ret = regmap_read(regmap, W83773_CONVERSION_RATE_REG_READ,
>> ®val);
>> + if (ret < 0)
>> + return ret;
>> +
>> + *val = 16000 >> regval;
>> + return 0;
>> +}
>> +
>> +static int set_update_interval(struct regmap *regmap, long val)
>> +{
>> + int ret;
>> + int rate;
>> +
>> + if (val <= 0)
>> + return -EINVAL;
>> +
>
> Not really needed since you are clamping below. For consistency I would
> suggest
> to drop it (otherwise 0 returns -EINVAL, 1 translates to 62).
>
My initial idea is that user should not set a value equal or less than
0, because
it does not make sense. And thus user get EINVAL for values <= 0, and get
interval 62 if he sets a value 1.
But yes, it can be removed for consistency, so user always get 62 for
values less than 62.
Will be fixed in v4.
>> + /*
>> + * For valid rates, interval can be calculated as
>> + * interval = (1 << (8 - rate)) * 62.5;
>> + * Rounded rate is therefore
>> + * rate = 8 - __fls(interval * 8 / (62.5 * 7));
>> + * Use clamp_val() to avoid overflows, and to ensure valid input
>> + * for __fls.
>> + */
>> + val = clamp_val(val, 62, 16000) * 10;
>> + rate = 8 - __fls((val * 8 / (625 * 7)));
>> + ret = regmap_write(regmap, W83773_CONVERSION_RATE_REG_WRITE,
>> rate);
>> + if (ret < 0)
>> + return ret;
>> + return 0;
>
>
> just
> return regmap_write(regmap, W83773_CONVERSION_RATE_REG_WRITE, rate);
>
Will be fixed in v4.
>> +}
>> +
>> +static int w83773_read(struct device *dev, enum hwmon_sensor_types type,
>> + u32 attr, int channel, long *val)
>> +{
>> + struct regmap *regmap = dev_get_drvdata(dev);
>> +
>> + if (type == hwmon_chip) {
>> + if (attr == hwmon_chip_update_interval)
>> + return get_update_interval(regmap, val);
>> + else
>
>
> else not needed after return
>
Will be fixed in v4.
>> + return -EOPNOTSUPP;
>> + }
>> +
>> + switch (attr) {
>> + case hwmon_temp_input:
>> + if (channel == 0)
>> + return get_local_temp(regmap, val);
>> + else
>
>
> else not needed after return
>
Will be fixed in v4.
>
>> + return get_remote_temp(regmap, channel - 1, val);
>> + case hwmon_temp_fault:
>> + return get_fault(regmap, channel - 1, val);
>> + case hwmon_temp_offset:
>> + return get_offset(regmap, channel - 1, val);
>> + default:
>> + return -EOPNOTSUPP;
>> + }
>> +}
>> +
>> +static int w83773_write(struct device *dev, enum hwmon_sensor_types type,
>> + u32 attr, int channel, long val)
>> +{
>> + struct regmap *regmap = dev_get_drvdata(dev);
>> +
>> + if (type == hwmon_chip && attr == hwmon_chip_update_interval)
>> + return set_update_interval(regmap, val);
>> +
>> + if (type == hwmon_temp && attr == hwmon_temp_offset)
>> + return set_offset(regmap, channel - 1, val);
>> +
>> + return -EOPNOTSUPP;
>> +}
>> +
>> +static umode_t w83773_is_visible(const void *data, enum
>> hwmon_sensor_types type,
>> + u32 attr, int channel)
>> +{
>> + switch (type) {
>> + case hwmon_chip:
>> + switch (attr) {
>> + case hwmon_chip_update_interval:
>> + return 0644;
>> + }
>> + break;
>> + case hwmon_temp:
>> + switch (attr) {
>> + case hwmon_temp_input:
>> + return 0444;
>> + case hwmon_temp_fault:
>
>
> The above case statements can be combined.
Will be fixed in v4.
>
>> + return 0444;
>> + case hwmon_temp_offset:
>> + return 0644;
>
>
> Wonder if static analyzers complain here and above because
> of the missing default: case. Any idea ?
hmm, I did not use static analyzer to parse this code so did not know.
My idea is that it's safe here because it always goes to the "return 0"
below so it is safe here.
>
>
>> + }
>> + break;
>> + default:
>> + break;
>> + }
>> + return 0;
>> +}
>> +
>> +static const u32 w83773_chip_config[] = {
>> + HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
>> + 0
>> +};
>> +
>> +static const struct hwmon_channel_info w83773_chip = {
>> + .type = hwmon_chip,
>> + .config = w83773_chip_config,
>> +};
>> +
>> +static const u32 w83773_temp_config[] = {
>> + HWMON_T_INPUT,
>> + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_OFFSET,
>> + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_OFFSET,
>> + 0
>> +};
>> +
>> +static const struct hwmon_channel_info w83773_temp = {
>> + .type = hwmon_temp,
>> + .config = w83773_temp_config,
>> +};
>> +
>> +static const struct hwmon_channel_info *w83773_info[] = {
>> + &w83773_chip,
>> + &w83773_temp,
>> + NULL
>> +};
>> +
>> +static const struct hwmon_ops w83773_ops = {
>> + .is_visible = w83773_is_visible,
>> + .read = w83773_read,
>> + .write = w83773_write,
>> +};
>> +
>> +static const struct hwmon_chip_info w83773_chip_info = {
>> + .ops = &w83773_ops,
>> + .info = w83773_info,
>> +};
>> +
>> +static const struct regmap_config w83773_regmap_config = {
>> + .reg_bits = 8,
>> + .val_bits = 8,
>> +};
>> +
>> +static int w83773_probe(struct i2c_client *client,
>> + const struct i2c_device_id *id)
>> +{
>> + struct device *dev = &client->dev;
>> + struct device *hwmon_dev;
>> + struct regmap *regmap;
>> + int ret;
>> +
>> + regmap = devm_regmap_init_i2c(client, &w83773_regmap_config);
>> + if (IS_ERR(regmap)) {
>> + dev_err(dev, "failed to allocate register map\n");
>> + return PTR_ERR(regmap);
>> + }
>> +
>> + /* Set the conversion rate to 2 Hz */
>> + ret = regmap_write(regmap, W83773_CONVERSION_RATE_REG_WRITE,
>> 0x05);
>> + if (ret < 0) {
>> + dev_err(&client->dev, "error writing config rate
>> register\n");
>> + return ret;
>> + }
>> +
>> + i2c_set_clientdata(client, regmap);
>> +
>> + hwmon_dev = devm_hwmon_device_register_with_info(dev,
>> + client->name,
>> + regmap,
>> +
>> &w83773_chip_info,
>> + NULL);
>> + return PTR_ERR_OR_ZERO(hwmon_dev);
>> +}
>> +
>> +static struct i2c_driver w83773_driver = {
>> + .class = I2C_CLASS_HWMON,
>> + .driver = {
>> + .name = "w83773g",
>> + .of_match_table = of_match_ptr(w83773_of_match),
>> + },
>> + .probe = w83773_probe,
>> + .id_table = w83773_id,
>> + .address_list = normal_i2c,
>
>
> address_list is only used if there is a detect function, so you can drop it.
>
Will be fixed in v4.
>
>> +};
>> +
>> +module_i2c_driver(w83773_driver);
>> +
>> +MODULE_AUTHOR("Lei YU <mine260309-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
>> +MODULE_DESCRIPTION("W83773G temperature sensor driver");
>> +MODULE_LICENSE("GPL");
>>
>
--
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^ permalink raw reply
* RE: [PATCHv4 1/3] ARMv8: dts: ls1046a: add the property of IB and OB
From: M.h. Lian @ 2017-11-13 2:35 UTC (permalink / raw)
To: Leo Li, Kishon Vijay Abraham I, Xiaowei Bao,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
catalin.marinas-5wv7dgnIgG8@public.gmane.org,
will.deacon-5wv7dgnIgG8@public.gmane.org,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
Madalin-cristian Bucur, Sumit Garg, Y.b. Lu, Andy Tang,
jingoohan1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
pbrobinson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
songxiaowei-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWOunwaRDDq4rA
In-Reply-To: <AM4PR0401MB16999BD34AFBB1362BD32EBD8F540-4rsfagO7TJzty7MPzPsMPo3W/0Ik+aLCnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
> -----Original Message-----
> From: Leo Li
> Sent: Saturday, November 11, 2017 5:21 AM
> To: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>; Xiaowei Bao
> <xiaowei.bao-3arQi8VN3Tc@public.gmane.org>; robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org;
> catalin.marinas-5wv7dgnIgG8@public.gmane.org; will.deacon-5wv7dgnIgG8@public.gmane.org; bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org;
> shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; Madalin-cristian Bucur <madalin.bucur-3arQi8VN3Tc@public.gmane.org>;
> Sumit Garg <sumit.garg-3arQi8VN3Tc@public.gmane.org>; Y.b. Lu <yangbo.lu-3arQi8VN3Tc@public.gmane.org>; Andy Tang
> <andy.tang-3arQi8VN3Tc@public.gmane.org>; jingoohan1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; pbrobinson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org;
> songxiaowei-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-
> kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-
> pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org; Z.q. Hou
> <zhiqiang.hou-3arQi8VN3Tc@public.gmane.org>; Mingkai Hu <mingkai.hu-3arQi8VN3Tc@public.gmane.org>; M.h. Lian
> <minghuan.lian-3arQi8VN3Tc@public.gmane.org>
> Subject: RE: [PATCHv4 1/3] ARMv8: dts: ls1046a: add the property of IB and OB
>
>
>
> > -----Original Message-----
> > From: Kishon Vijay Abraham I [mailto:kishon-l0cyMroinI0@public.gmane.org]
> > Sent: Friday, November 10, 2017 12:22 AM
> > To: Xiaowei Bao <xiaowei.bao-3arQi8VN3Tc@public.gmane.org>; robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org;
> > mark.rutland-5wv7dgnIgG8@public.gmane.org; catalin.marinas-5wv7dgnIgG8@public.gmane.org; will.deacon-5wv7dgnIgG8@public.gmane.org;
> > bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org; shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; Madalin-cristian Bucur
> > <madalin.bucur-3arQi8VN3Tc@public.gmane.org>; Sumit Garg <sumit.garg-3arQi8VN3Tc@public.gmane.org>; Y.b. Lu
> > <yangbo.lu-3arQi8VN3Tc@public.gmane.org>; hongtao.jia-3arQi8VN3Tc@public.gmane.org; Andy Tang
> > <andy.tang-3arQi8VN3Tc@public.gmane.org>; Leo Li <leoyang.li-3arQi8VN3Tc@public.gmane.org>;
> > jingoohan1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; pbrobinson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; songxiaowei-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org;
> > devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org;
> > linux- kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-
> > dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org; Z.q. Hou <zhiqiang.hou-3arQi8VN3Tc@public.gmane.org>; Mingkai Hu
> > <mingkai.hu-3arQi8VN3Tc@public.gmane.org>; M.h. Lian <minghuan.lian-3arQi8VN3Tc@public.gmane.org>
> > Subject: Re: [PATCHv4 1/3] ARMv8: dts: ls1046a: add the property of IB
> > and OB
> >
> > Hi Bao,
> >
> > On Friday 10 November 2017 09:18 AM, Bao Xiaowei wrote:
> > > Add the property of inbound and outbound windows number for ep driver.
> > >
> > > Signed-off-by: Bao Xiaowei <xiaowei.bao-3arQi8VN3Tc@public.gmane.org>
> > > Acked-by: Minghuan Lian <minghuan.Lian-3arQi8VN3Tc@public.gmane.org>
> > > ---
> > > v2:
> > > - no change
> > > v3:
> > > - modify the commit message
> > > v4:
> > > - no change
> > >
> > > arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
> > > 1 file changed, 6 insertions(+)
> >
> > $subject should start with something like
> > arm64: dts: ls1046a: **
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > > b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > > index 06b5e12d04d8..f8332669663c 100644
> > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > > @@ -674,6 +674,8 @@
> > > device_type = "pci";
> > > dma-coherent;
> > > num-lanes = <4>;
> > > + num-ib-windows = <6>;
> > > + num-ob-windows = <6>;
> >
> > EP specific properties shouldn't be added in RC dt node. Ideally you
> > should have a separate dt node for RC and EP.
>
> It is a single PCIe controller which can be configured to either RC mode or EP
> mode. Wouldn't it conflict with the device tree principles to have two device
> tree nodes for the same PCIe controller? And obviously the two modes cannot
> be used at the same time so we cannot have two drivers both probe on the
> same hardware.
>
[Minghuan Lian] There is only one PCIe dts node in the dts file. PCIe dts node describes the PCIe controller's hardware properties and does not have work mode. The new properties "num-ib-windows " and "num-ob-windows" are used to describe the inbound/outbound window number included in the PCIe hardware. These windows are used in both RC and EP mode. We can change work mode when resetting via RCW(reset configuration word).
> Regards,
> Leo
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^ permalink raw reply
* [RFC PATCH 3/3] arm64: dts: allwinner: enhance A64 .dtsi with new pinctrl binding
From: Andre Przywara @ 2017-11-13 1:25 UTC (permalink / raw)
To: Linus Walleij, Maxime Ripard, Chen-Yu Tsai
Cc: linux-gpio, Rob Herring, Mark Rutland, devicetree,
linux-arm-kernel, Arnd Bergmann, Icenowy Zheng
In-Reply-To: <20171113012523.2328-1-andre.przywara@arm.com>
Enhance the existing pinctrl DT nodes for the Allwinner A64 SoC to
include the new properties the generic, DT-based binding introduced.
This allows any generic driver to support this SoC as well.
The DT nodes stay fully compatible with the old binding, so existing
drivers continue to work without restrictions.
But on top of that new DT users can directly use the information here
and can do without a hardcoded table.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 27 +++++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 8c8db1b057df..58fdae32240a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -269,7 +269,8 @@
};
pio: pinctrl@1c20800 {
- compatible = "allwinner,sun50i-a64-pinctrl";
+ compatible = "allwinner,sun50i-a64-pinctrl",
+ "allwinner,sunxi-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
@@ -279,16 +280,22 @@
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
+ allwinner,gpio-pins = <0 10 17 25 18 7 14 12>;
+ allwinner,irq-pin-map = <0 0 1 0 6 10>,
+ <1 0 6 0 6 14>,
+ <2 0 7 0 6 12>;
i2c1_pins: i2c1_pins {
pins = "PH2", "PH3";
function = "i2c1";
+ pinmux = <2>;
};
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
function = "mmc0";
+ pinmux = <2>;
drive-strength = <30>;
bias-pull-up;
};
@@ -297,6 +304,7 @@
pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";
function = "mmc1";
+ pinmux = <2>;
drive-strength = <30>;
bias-pull-up;
};
@@ -306,6 +314,7 @@
"PC10","PC11", "PC12", "PC13",
"PC14", "PC15", "PC16";
function = "mmc2";
+ pinmux = <3>;
drive-strength = <30>;
bias-pull-up;
};
@@ -314,6 +323,7 @@
pins = "PD10", "PD11", "PD13", "PD14", "PD17",
"PD18", "PD19", "PD20", "PD22", "PD23";
function = "emac";
+ pinmux = <4>;
drive-strength = <40>;
};
@@ -322,42 +332,50 @@
"PD13", "PD15", "PD16", "PD17", "PD18",
"PD19", "PD20", "PD21", "PD22", "PD23";
function = "emac";
+ pinmux = <4>;
drive-strength = <40>;
};
uart0_pins_a: uart0@0 {
pins = "PB8", "PB9";
function = "uart0";
+ pinmux = <4>;
};
uart1_pins: uart1_pins {
pins = "PG6", "PG7";
function = "uart1";
+ pinmux = <2>;
};
uart1_rts_cts_pins: uart1_rts_cts_pins {
pins = "PG8", "PG9";
function = "uart1";
+ pinmux = <2>;
};
uart2_pins: uart2-pins {
pins = "PB0", "PB1";
function = "uart2";
+ pinmux = <2>;
};
uart3_pins: uart3-pins {
pins = "PD0", "PD1";
function = "uart3";
+ pinmux = <3>;
};
uart4_pins: uart4-pins {
pins = "PD2", "PD3";
function = "uart4";
+ pinmux = <3>;
};
uart4_rts_cts_pins: uart4-rts-cts-pins {
pins = "PD4", "PD5";
function = "uart4";
+ pinmux = <3>;
};
};
@@ -487,7 +505,8 @@
};
r_pio: pinctrl@01f02c00 {
- compatible = "allwinner,sun50i-a64-r-pinctrl";
+ compatible = "allwinner,sun50i-a64-r-pinctrl",
+ "allwinner,sunxi-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
@@ -496,10 +515,14 @@
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
+ allwinner,gpio-pins = <13>;
+ allwinner,port-base = <11>;
+ allwinner,irq-pin-map = <0 0 11 0 6 13>;
r_rsb_pins: rsb@0 {
pins = "PL0", "PL1";
function = "s_rsb";
+ pinmux = <2>;
};
};
--
2.14.1
^ permalink raw reply related
* [RFC PATCH 2/3] pinctrl: sunxi: introduce DT-based generic driver
From: Andre Przywara @ 2017-11-13 1:25 UTC (permalink / raw)
To: Linus Walleij, Maxime Ripard, Chen-Yu Tsai
Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Arnd Bergmann,
Icenowy Zheng
In-Reply-To: <20171113012523.2328-1-andre.przywara-5wv7dgnIgG8@public.gmane.org>
This driver (shim) allows to fully describe an Allwinner pin controller
and its GPIO ports in device tree nodes.
It will read some newly introduced properties to build a table
describing the pins and their routing. This table matches those that we
have hardcoded for various SoCs in the kernel so far.
After this table has been created, it will be handed over to the actual
pinctrl driver, which registers it with the pinctrl subsystem.
Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
---
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c | 412 +++++++++++++++++++++++++++++++
2 files changed, 413 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 12a752e836ef..06f9d924b9cf 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o
obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
+obj-y += pinctrl-sunxi-dt.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c b/drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c
new file mode 100644
index 000000000000..46a7bfbefee1
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c
@@ -0,0 +1,412 @@
+/*
+ * Generic Allwinner pinctrl driver DT shim
+ * Read all the information required by the pinctrl subsystem from the DT
+ * and build a table describing each pin. Hand this table over to the actual
+ * pinctrl driver.
+ *
+ * Copyright (C) 2017 ARM Ltd.
+ * Author: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/export.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "pinctrl-sunxi.h"
+
+#define INVALID_MUX 0xff
+
+/*
+ * Return the "index"th element from the "pinmux" property. If the property
+ * does not hold enough entries, return the last one instead.
+ * For almost every group the pinmux value is actually the same, so this
+ * allows to just list it once in the property.
+ */
+static u8 sunxi_pinctrl_dt_read_pinmux(const struct device_node *node,
+ int index)
+{
+ int ret, num_elems;
+ u32 value;
+
+ ret = of_property_read_u32_index(node, "pinmux", index, &value);
+ if (!ret)
+ return value;
+ if (ret != -EOVERFLOW)
+ return INVALID_MUX;
+
+ num_elems = of_property_count_u32_elems(node, "pinmux");
+ if (num_elems <= 0)
+ return INVALID_MUX;
+
+ ret = of_property_read_u32_index(node, "pinmux", num_elems - 1, &value);
+ if (ret)
+ return INVALID_MUX;
+
+ return value;
+}
+
+/*
+ * Allocate a table with a sunxi_desc_pin structure for every pin needed.
+ * Fills in the respective pin names ("PA0") and their pin numbers.
+ * Returns the number of pins allocated.
+ */
+static int build_pins_table(struct device *dev, struct device_node *node,
+ int port_base, struct sunxi_desc_pin **table)
+{
+ struct sunxi_desc_pin *pins, *cur_pin;
+ struct property *prop;
+ const __be32 *cur;
+ u32 pin_count;
+ int name_size = 0, npins = 0, nports = 0;
+ char *pin_names, *cur_name;
+ int i, j;
+
+ /*
+ * Find the total number of pins.
+ * Also work out how much memory we need to store all the pin names.
+ */
+ of_property_for_each_u32(node, "allwinner,gpio-pins", prop,
+ cur, pin_count) {
+ npins += pin_count;
+ if (pin_count < 10) {
+ name_size += pin_count * 4; /* 4 bytes for "PXy\0" */
+ } else {
+ /* 4 bytes for each "PXy\0" */
+ name_size += 10 * 4;
+
+ /* 5 bytes for each "PXyy\0" */
+ name_size += (pin_count - 10) * 5;
+ }
+ nports++;
+ }
+
+ if (!nports || !npins) {
+ dev_warn(dev, "%s: no pins defined\n", of_node_full_name(node));
+ return -EINVAL;
+ }
+
+ pins = devm_kzalloc(dev, npins * sizeof(*pins), GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+
+ /* Allocate memory to store the name for every pin. */
+ pin_names = devm_kmalloc(dev, name_size, GFP_KERNEL);
+ if (!pin_names)
+ return -ENOMEM;
+
+ /* Fill the pins array with the name and the number for each pin. */
+ cur_name = pin_names;
+ cur_pin = pins;
+ for (i = 0; i < nports; i++) {
+ of_property_read_u32_index(node, "allwinner,gpio-pins", i,
+ &pin_count);
+ for (j = 0; j < pin_count; j++, cur_pin++) {
+ int nchars = sprintf(cur_name, "P%c%d",
+ port_base + 'A' + i, j);
+
+ cur_pin->pin.number = (port_base + i) * 32 + j;
+ cur_pin->pin.name = cur_name;
+ cur_name += nchars + 1;
+ }
+ }
+
+ *table = pins;
+
+ return npins;
+}
+
+/* Check whether this pin can trigger interrupts. */
+static bool get_irq_pin(struct device_node *pnode,
+ struct pinctrl_pin_desc *pin,
+ u8 *irq_port, u8 *irq_pin, u8 *muxval)
+{
+ u32 gpio_firstpin, length, reg;
+ int i;
+
+ for (i = 0; ; i++) {
+ if (of_property_read_u32_index(pnode, "allwinner,irq-pin-map",
+ i * 6 + 2, ®))
+ break;
+
+ if (reg != pin->number / 32)
+ continue;
+
+ of_property_read_u32_index(pnode, "allwinner,irq-pin-map",
+ i * 6 + 3, &gpio_firstpin);
+ of_property_read_u32_index(pnode, "allwinner,irq-pin-map",
+ i * 6 + 5, &length);
+ if ((gpio_firstpin > pin->number % 32) ||
+ (gpio_firstpin + length <= pin->number % 32))
+ continue;
+
+ if (irq_port) {
+ of_property_read_u32_index(pnode,
+ "allwinner,irq-pin-map",
+ i * 6 + 0, ®);
+ *irq_port = reg;
+ }
+ if (irq_pin) {
+ of_property_read_u32_index(pnode,
+ "allwinner,irq-pin-map",
+ i * 6 + 1, ®);
+ *irq_pin = reg + (pin->number % 32) - gpio_firstpin;
+ }
+ if (muxval) {
+ of_property_read_u32_index(pnode,
+ "allwinner,irq-pin-map",
+ i * 6 + 4, ®);
+ *muxval = reg;
+ }
+
+
+ return true;
+ }
+
+ return false;
+}
+
+/*
+ * Work out the number of functions each pin has. Provide memory to hold
+ * the per-function information and assign it to the pin table.
+ * Fill in the GPIO in/out functions every pin has, also add an "irq"
+ * function for those pins in IRQ-capable ports.
+ */
+static int prepare_function_table(struct device *dev, struct device_node *pnode,
+ struct sunxi_desc_pin *pins, int npins)
+{
+ struct device_node *node;
+ struct property *prop;
+ struct sunxi_desc_function *func;
+ int num_funcs, i;
+
+ /*
+ * We need at least three functions per pin:
+ * - one for GPIO in
+ * - one for GPIO out
+ * - one for the sentinel signalling the end of the list
+ */
+ num_funcs = 3 * npins;
+
+ /* Add a function for each pin in a port supporting interrupts. */
+ for (i = 0; i < npins; i++) {
+ if (get_irq_pin(pnode, &pins[i].pin, NULL, NULL, NULL)) {
+ pins[i].variant++;
+ num_funcs++;
+ }
+ }
+
+ /*
+ * Go over each pin group (every child of the pinctrl DT node) and
+ * add the number of special functions each pins has. Also update the
+ * total number of functions required.
+ * We might slightly overshoot here in case of double definitions.
+ */
+ for_each_child_of_node(pnode, node) {
+ const char *name;
+
+ of_property_for_each_string(node, "pins", prop, name) {
+ for (i = 0; i < npins; i++) {
+ if (strcmp(pins[i].pin.name, name))
+ continue;
+
+ pins[i].variant++;
+ num_funcs++;
+ break;
+ }
+ }
+ }
+
+ /*
+ * Allocate the memory needed for the functions in one table.
+ * We later use pointers into this table to mark each pin.
+ */
+ func = devm_kzalloc(dev, num_funcs * sizeof(*func), GFP_KERNEL);
+ if (!func)
+ return -ENOMEM;
+
+ /* Assign the functions memory and fill in GPIOs, IRQ and a sentinel. */
+ for (i = 0; i < npins; i++) {
+ int lastfunc = pins[i].variant + 1;
+
+ func[0].name = "gpio_in";
+ func[0].muxval = 0;
+ func[1].name = "gpio_out";
+ func[1].muxval = 1;
+
+ if (get_irq_pin(pnode, &pins[i].pin,
+ &func[lastfunc].irqbank,
+ &func[lastfunc].irqnum,
+ &func[lastfunc].muxval))
+ func[lastfunc].name = "irq";
+
+ pins[i].functions = func;
+
+ /* Skip over the other needed functions and the sentinel. */
+ func += pins[i].variant + 3;
+
+ /*
+ * Reset the value for filling in the remaining functions
+ * behind the GPIOs later.
+ */
+ pins[i].variant = 2;
+ }
+
+ return 0;
+}
+
+/*
+ * Iterate over all pins in this group and add the function name and its
+ * mux value to the respective pin.
+ */
+static void fill_pin_function(struct device *dev, struct device_node *node,
+ struct sunxi_desc_pin *pins, int npins)
+{
+ const char *name, *funcname;
+ struct sunxi_desc_function *func;
+ struct property *prop;
+ int pin, i;
+ u8 muxval;
+
+ if (of_property_read_string(node, "function", &funcname)) {
+ dev_warn(dev, "missing \"function\" property\n");
+ return;
+ }
+
+ of_property_for_each_string(node, "pins", prop, name) {
+ /* Find the index of this pin in our table. */
+ for (pin = 0; pin < npins; pin++)
+ if (!strcmp(pins[pin].pin.name, name))
+ break;
+ if (pin == npins) {
+ dev_warn(dev, "%s: cannot find pin %s\n",
+ of_node_full_name(node), name);
+ continue;
+ }
+
+ /* Read the associated mux value. */
+ muxval = sunxi_pinctrl_dt_read_pinmux(node, pin);
+ if (muxval == INVALID_MUX) {
+ dev_warn(dev, "%s: invalid mux value for pin %s\n",
+ of_node_full_name(node), name);
+ continue;
+ }
+
+ /*
+ * Check for double definitions by comparing the to-be-added
+ * function with already assigned ones.
+ * Ignore identical pairs (function name and mux value the
+ * same), but warn about conflicting assignments.
+ */
+ for (i = 2; i < pins[pin].variant; i++) {
+ func = &pins[pin].functions[i];
+
+ /* Skip over totally unrelated functions. */
+ if (strcmp(func->name, funcname) &&
+ func->muxval != muxval)
+ continue;
+
+ /* Ignore (but skip below) any identical functions. */
+ if (!strcmp(func->name, funcname) &&
+ muxval == func->muxval)
+ break;
+
+ dev_warn(dev,
+ "pin %s: function %s redefined to mux %d\n",
+ name, funcname, muxval);
+ break;
+ }
+
+ /* Skip any pins with that function already assigned. */
+ if (i < pins[pin].variant)
+ continue;
+
+ /* Assign function and muxval to the next free slot. */
+ func = &pins[pin].functions[pins[pin].variant];
+ func->muxval = muxval;
+ func->name = funcname;
+
+ pins[pin].variant++;
+ }
+}
+
+/* Iterate over all IRQ pin maps and find out the number of distinct ports. */
+static int count_nr_irq_banks(struct device_node *node)
+{
+ u32 port_mask = 0, irq_port;
+ int i = 0;
+
+ for (i = 0;
+ !of_property_read_u32_index(node, "allwinner,irq-pin-map",
+ i * 6 + 0, &irq_port);
+ i++)
+ port_mask |= BIT(irq_port);
+
+ return hweight32(port_mask);
+}
+
+static int sunxi_generic_pinctrl_probe(struct platform_device *pdev)
+{
+ struct device_node *pnode = pdev->dev.of_node, *node;
+ struct sunxi_pinctrl_desc *desc;
+ struct sunxi_desc_pin *pins;
+ u32 port_base = 0;
+ int npins, ret, i;
+
+ of_property_read_u32(pnode, "allwinner,port-base", &port_base);
+ npins = build_pins_table(&pdev->dev, pnode, port_base, &pins);
+ if (npins < 0)
+ return npins;
+
+ ret = prepare_function_table(&pdev->dev, pnode, pins, npins);
+ if (ret)
+ return ret;
+
+ /*
+ * Now iterate over all groups and add the respective function name
+ * and mux values to each pin listed within.
+ */
+ for_each_child_of_node(pnode, node)
+ fill_pin_function(&pdev->dev, node, pins, npins);
+
+ /* Clear the temporary storage. */
+ for (i = 0; i < npins; i++)
+ pins[i].variant = 0;
+
+ desc = devm_kzalloc(&pdev->dev, sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ desc->pins = pins;
+ desc->npins = npins;
+ desc->pin_base = port_base * 32;
+
+ desc->irq_banks = count_nr_irq_banks(pnode);
+ of_property_read_u32(pnode, "allwinner,irq-bank-base",
+ &desc->irq_bank_base);
+ if (of_property_read_bool(pnode, "allwinner,irq_read_needs_mux"))
+ desc->irq_read_needs_mux = true;
+
+ return sunxi_pinctrl_init_with_variant(pdev, desc, 0);
+}
+
+static const struct of_device_id sunxi_pinctrl_match[] = {
+ { .compatible = "allwinner,sunxi-pinctrl", },
+ { },
+};
+
+static struct platform_driver sunxi_pinctrl_driver = {
+ .probe = sunxi_generic_pinctrl_probe,
+ .driver = {
+ .name = "sunxi-pinctrl",
+ .of_match_table = sunxi_pinctrl_match,
+ },
+};
+builtin_platform_driver(sunxi_pinctrl_driver);
--
2.14.1
--
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^ permalink raw reply related
* [RFC PATCH 1/3] dt-bindings: pinctrl: sunxi: document new generic binding
From: Andre Przywara @ 2017-11-13 1:25 UTC (permalink / raw)
To: Linus Walleij, Maxime Ripard, Chen-Yu Tsai
Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Arnd Bergmann,
Icenowy Zheng
In-Reply-To: <20171113012523.2328-1-andre.przywara-5wv7dgnIgG8@public.gmane.org>
So far all the Allwinner pinctrl drivers provided a table in the
kernel to describe all the pins and the link between the pinctrl functions
names (strings) and their respective mux values (register values).
Extend the binding to put those mappings in the DT, so that any SoC can
describe its pinctrl and GPIO data fully there instead of relying on
tables.
This uses a generic compatible name, to be prepended with an SoC
specific name in the node.
Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 58 ++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 6f2ec9af0de2..c1ea755229da 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -28,6 +28,7 @@ Required properties:
"allwinner,sun50i-a64-r-pinctrl"
"allwinner,sun50i-h5-pinctrl"
"nextthing,gr8-pinctrl"
+ "allwinner,sunxi-pinctrl" (see below)
- reg: Should contain the register physical address and length for the
pin controller.
@@ -69,6 +70,63 @@ Optional sub-node properties:
- bias-pull-down
- drive-strength
+** Generic pinctrl binding
+The above binding requires knowledge of the actual mux setting values for
+each supported SoC in the code parsing the DT (for instance the kernel).
+The generic binding puts this information in the DT. It uses the
+"allwinner,sunxi-pinctrl" compatible, in addition to some SoC specific string.
+It extends the above described binding as follows:
+Required properties:
+- allwinner,gpio-pins: An array of 32-bit numbers to denote the number of
+ implemented pins per pin controller port. Non-implemented ports can specify
+ 0 here. There will be as many ports as this array has elements.
+- allwinner,irq-pin-map: Contains a number of IRQ port maps, describing the
+ relationship between interrupt banks and GPIO pins. Each map has six 32-bit
+ members:
+ <[IRQ port] [1st IRQ pin] [GPIO port] [1st GPIO pin] [mux value] [length]>
+ This maps the first [length] IRQ pins starting with [IRQ port]:[1st IRQ pin]
+ to [GPIO port]:[1st GPIO pin], all using [mux value] to select the IRQ
+ functionality.
+
+Optional properties:
+- allwinner,port-base: The number of GPIO ports to skip at the beginning.
+- allwinner,irq-bank-base: The number of IRQ banks to skip at the beginning.
+- allwinner,irq-read-needs-mux: Specifies that reading the line level of
+ a pin configured as an IRQ pin is not possible. A driver needs to switch
+ to the GPIO-in function to be able to read the level.
+
+Required properties for subnodes:
+- pinmux: An array of mux values to write into the respective MMIO register
+ bits for this pin when selecting the function. If this array has less
+ elements than pins, the *last* value will be used for all pins beyond that.
+ This allows to use a single element for the (likely) case all pins use the
+ same mux value.
+
+The binding described above can be extended in this manner to be supported
+by *both* an existing driver and some generic driver. Existing drivers will
+ignore the new properties and revert to their internal table instead.
+
+Example:
+ pinctrl@1c20800 {
+ compatible = "allwinner,sun50i-a64-pinctrl",
+ "allwinner,sunxi-pinctrl";
+ reg = <0x01c20800 0x400>;
+ clocks = <&ccu 58>, <&hosc>, <&losc>;
+ /* No PortA, PB0-PB9, PC0-PC16, PD0-PD24, ... */
+ allwinner,gpio-pins = <0 10 17 25 18 7 14 12>;
+ /* banks B, G and H can trigger interrupts, using mux value 6 */
+ allwinner,irq-pin-map= <0 0 1 0 6 10>,
+ <1 0 6 0 6 14>,
+ <2 0 7 0 6 12>;
+ i2c1_pins: i2c1_pins {
+ pins = "PH2", "PH3";
+ function = "i2c1";
+ /* Both pins use a mux value of 2 to select this function. */
+ pinmux = <2>;
+ };
+ ...
+ };
+
*** Deprecated pin configuration and multiplexing binding
Required subnode-properties:
--
2.14.1
--
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^ permalink raw reply related
* [RFC PATCH 0/3] pinctrl: sunxi: Add DT-based generic pinctrl driver
From: Andre Przywara @ 2017-11-13 1:25 UTC (permalink / raw)
To: Linus Walleij, Maxime Ripard, Chen-Yu Tsai
Cc: linux-gpio, Rob Herring, Mark Rutland, devicetree,
linux-arm-kernel, Arnd Bergmann, Icenowy Zheng
Hi,
so far the pinctrl driver for supporting a particular Allwinner SoC requires
a hardcoded table in the kernel code. This table (for instance [1]) lists
all pins and puts names to each special function each pin can have, along
with the respective mux value to put into the hardware registers. That looks
like:
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
....
On top of that we have the DT, which groups the pins and refers to the
function to use *by name*:
mmc1_pins: mmc1-pins {
pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";
function = "mmc1";
drive-strength = <30>;
bias-pull-up;
};
This series here moves the data encoded in the table so far into the DT itself,
removing the need for a hardcoded table in the kernel.
The approach taken here is to parse the DT and generate the table with
the help of additional properties, then hand this table over to the existing
driver. This is covered by three basic extensions to the DT binding:
- allwinner,gpio-pins = <[nr of PA pins] [nr of PB pins] ...>;
This tells the driver how many pins each port has (0 is possible as
well). The sum of all of them is used to size the array. Also the pin
names are deduced from it and generated. Each pin gets an entry for
GPIO in and out, using mux 0 and 1, respectively.
- allwinner,irq-pin-map =
<[IRQ port] [1st IRQ pin] [GPIO port] [1st GPIO pin] [mux value] [length]>
Maps IRQ pins to their associated GPIO pins, describing the pins that can
actually trigger interrupts. There can be multiple of these maps, each
consisting of those six values.
Every IRQ capable pin in those ports gets assigned an additional function
"irq" (see the SUNXI_FUNCTION_IRQ_BANK line above).
- pinmux = <[mux value] ...>;
This property (in the pin group subnodes) tells the driver which mux value
to actually write into the hardware registers upon selecting this function.
For almost every group this mux value is the same for every pin, so we fill
remaining entries with the last entry in that property, if this property
has less members than the number of pins in this group.
For the A64, for instance, this looks like this:
pio: pinctrl@1c20800 {
compatible = "allwinner,sun50i-a64-pinctrl",
"allwinner,sunxi-pinctrl";
reg = <0x01c20800 0x400>;
...
/* No Port A, PB0..PB9, PC0..PC16, PD0..PD24, ... */
allwinner,gpio-pins = <0 10 17 25 18 7 14 12>;
/* The three ports B, G and H can trigger interrupts. */
allwinner,irq-ports = <0 0 1 0 6 10>,
<1 0 6 0 6 14>,
<2 0 7 0 6 12>;
...
mmc1_pins: mmc1-pins {
pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
function = "mmc1";
pinmux = <2>;
drive-strength = <30>;
bias-pull-up;
};
...
The benefit of this series is two-fold:
- Future SoCs don't need an in-kernel table anymore. They can describe
everything in the DT, and use the generic compatible as a fallback:
compatible = "allwinner,sun50i-h6-pinctrl", "allwinner,sunxi-pinctrl";
So this driver should be the last file added to this directory ever.
Of course we can't remove the existing tables, to keep compatiblity with
older DTs, but at least we don't need to add more tables in the future.
The Allwinner H6 will be the first user of this driver.
- New DT consumers (other than the Linux kernel) could force usage of the
new binding, if that's feasible for them. They would not need to add
any SoC specific data into their code, instead have a generic driver that
reads all information from the DT.
A prominent example is U-Boot, which at the moment has *some* pinctrl data
hardcoded, but wants to move to at DT based driver. Instead of copying the
kernel tables and blowing up the code, we can add the new properties to
U-Boot's DT copy and keep the code clean.
Please note that the new binding is indeed just an extension, the existing
driver just ignores those new properties and uses the in-kernel table, thus
working as before, without any restrictions.
So we can as well add those new properties to the kernel DT copy, which makes
it easier for other users to re-use the DT files.
The extended DT would add the generic compatible as a fallback, but keep the
existing compatible name in the first place. So existing kernel drivers
would match on the first string and use the table. U-Boot on the other hand
would not match on the specific string, but recognize the generic name and
pull the information from the DT.
This allows the very same DT to be used by both drivers (or both bindings),
triggered by the generic compatible.
Please let me know your opinion on this. The approach to generate the table
from the DT and re-using the existing driver leaves some room for optimization.
But I found it far easier to not touch the actual driver, since we need it
to stay around to support the old binding anyway.
If it seems worth the come up with a separate pinctrl driver which just
supports the new binding and makes the DT a first class citizen, let me
know - and give me some time to fully understand the inner workings of the
pinctrl and GPIO subsystem then.
Cheers,
Andre.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
Andre Przywara (3):
dt-bindings: pinctrl: sunxi: document new generic binding
pinctrl: sunxi: introduce DT-based generic driver
arm64: dts: allwinner: enhance A64 .dtsi with new pinctrl binding
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 58 +++
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 27 +-
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c | 412 +++++++++++++++++++++
4 files changed, 496 insertions(+), 2 deletions(-)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c
--
2.14.1
^ permalink raw reply
* [PATCH v2 5/5] misc: w2sg0004: add debugging code and Kconfig
From: H. Nikolaus Schaller @ 2017-11-12 20:59 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Benoît Cousson, Tony Lindgren,
Russell King, H. Nikolaus Schaller, Thierry Reding,
Jonathan Cameron, Maxime Ripard, Jarkko Sakkinen
Cc: devicetree, linux-kernel, linux-omap, letux-kernel, kernel
In-Reply-To: <cover.1510520397.git.hns@goldelico.com>
This allows to set CONFIG_W2SG0004_DEBUG which will
make the driver report more activities and it will turn on the
GPS module during boot while the driver assumes that it
is off. This can be used to debug the correct functioning of
the hardware. Therefore we add it as an option to the driver
because we think it is of general use (and a little tricky to
add by system testers).
Normally it should be off.
---
drivers/misc/Kconfig | 8 ++++++++
drivers/misc/w2sg0004.c | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 09d171d68408..f15ff5a97e42 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -528,4 +528,12 @@ config W2SG0004
is opened/closed.
It also provides a rfkill gps name to control the LNA power.
+config W2SG0004_DEBUG
+ bool "W2SG0004 on/off debugging"
+ depends on W2SG0004
+ help
+ Enable driver debugging mode of W2SG0004 GPS. If you say y here
+ this will turn on the module and you can check if it is turned
+ off by the driver.
+
endmenu
diff --git a/drivers/misc/w2sg0004.c b/drivers/misc/w2sg0004.c
index 55101aa6beeb..b6e2253a580f 100644
--- a/drivers/misc/w2sg0004.c
+++ b/drivers/misc/w2sg0004.c
@@ -22,6 +22,10 @@
*
*/
+#ifdef CONFIG_W2SG0004_DEBUG
+#define DEBUG 1
+#endif
+
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
@@ -251,6 +255,7 @@ static int w2sg_tty_install(struct tty_driver *driver, struct tty_struct *tty)
pr_debug("%s() tty = %p\n", __func__, tty);
data = w2sg_get_by_minor(tty->index);
+ pr_debug("%s() data = %p\n", __func__, data);
if (!data)
return -ENODEV;
@@ -363,6 +368,8 @@ static int w2sg_probe(struct serdev_device *serdev)
w2sg_by_minor[minor] = data;
+ pr_debug("w2sg serdev_device_set_drvdata\n");
+
serdev_device_set_drvdata(serdev, data);
data->lna_regulator = pdata->lna_regulator;
@@ -381,6 +388,8 @@ static int w2sg_probe(struct serdev_device *serdev)
INIT_DELAYED_WORK(&data->work, toggle_work);
+ pr_debug("w2sg devm_gpio_request\n");
+
err = devm_gpio_request(&serdev->dev, data->on_off_gpio,
"w2sg0004-on-off");
if (err < 0)
@@ -394,6 +403,8 @@ static int w2sg_probe(struct serdev_device *serdev)
serdev_device_set_baudrate(data->uart, 9600);
serdev_device_set_flow_control(data->uart, false);
+ pr_debug("w2sg rfkill_alloc\n");
+
rf_kill = rfkill_alloc("GPS", &serdev->dev, RFKILL_TYPE_GPS,
&w2sg0004_rfkill_ops, data);
if (rf_kill == NULL) {
@@ -401,6 +412,8 @@ static int w2sg_probe(struct serdev_device *serdev)
goto err_rfkill;
}
+ pr_debug("w2sg register rfkill\n");
+
err = rfkill_register(rf_kill);
if (err) {
dev_err(&serdev->dev, "Cannot register rfkill device\n");
@@ -409,6 +422,8 @@ static int w2sg_probe(struct serdev_device *serdev)
data->rf_kill = rf_kill;
+ pr_debug("w2sg alloc_tty_driver\n");
+
/* allocate the tty driver */
data->tty_drv = alloc_tty_driver(1);
if (!data->tty_drv)
@@ -434,6 +449,8 @@ static int w2sg_probe(struct serdev_device *serdev)
*/
tty_set_operations(data->tty_drv, &w2sg_serial_ops);
+ pr_debug("w2sg tty_register_driver\n");
+
/* register the tty driver */
err = tty_register_driver(data->tty_drv);
if (err) {
@@ -443,6 +460,8 @@ static int w2sg_probe(struct serdev_device *serdev)
goto err_rfkill;
}
+ pr_debug("w2sg call tty_port_init\n");
+
tty_port_init(&data->port);
data->port.ops = &w2sg_port_ops;
@@ -451,11 +470,27 @@ static int w2sg_probe(struct serdev_device *serdev)
* which only fails because the gpio is already assigned
*/
+ pr_debug("w2sg call tty_port_register_device\n");
+
data->dev = tty_port_register_device(&data->port,
data->tty_drv, minor, &serdev->dev);
+ pr_debug("w2sg tty_port_register_device -> %p\n", data->dev);
+ pr_debug("w2sg port.tty = %p\n", data->port.tty);
+
pr_debug("w2sg probed\n");
+#ifdef CONFIG_W2SG0004_DEBUG
+ pr_debug("w2sg DEBUGGING MODE enabled\n");
+ /* turn on for debugging rx notifications */
+ pr_debug("w2sg power gpio ON\n");
+ gpio_set_value_cansleep(data->on_off_gpio, 1);
+ mdelay(100);
+ pr_debug("w2sg power gpio OFF\n");
+ gpio_set_value_cansleep(data->on_off_gpio, 0);
+ mdelay(300);
+#endif
+
/* keep off until user space requests the device */
w2sg_set_power(data, false);
@@ -465,6 +500,8 @@ static int w2sg_probe(struct serdev_device *serdev)
rfkill_destroy(rf_kill);
serdev_device_close(data->uart);
out:
+ pr_debug("w2sg error %d\n", err);
+
return err;
}
--
2.12.2
^ permalink raw reply related
* [PATCH v2 4/5] DTS: gta04: add serdev node for w2sg00x4
From: H. Nikolaus Schaller @ 2017-11-12 20:59 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Benoît Cousson, Tony Lindgren,
Russell King, H. Nikolaus Schaller, Thierry Reding,
Jonathan Cameron, Maxime Ripard, Jarkko Sakkinen
Cc: devicetree, linux-kernel, linux-omap, letux-kernel, kernel
In-Reply-To: <cover.1510520397.git.hns@goldelico.com>
GTA04 has a W2SG0004/84 connected to UART2 of the OMAP3
processor. A GPIO can pulse the on/off toggle switch.
The VSIM regulator is used to power on/off the LNA of an external
active GPS antenna so that a driver can turn the LNA off if GPS is
not needed to save battery energy.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
arch/arm/boot/dts/omap3-gta04.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index 4504908c23fe..e967d738aaaf 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -477,6 +477,12 @@
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
+
+ gps: gps {
+ compatible = "wi2wi,w2sg0004";
+ lna-supply = <&vsim>; /* LNA regulator */
+ enable-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* GPIO_145: trigger for turning on/off w2sg0004 */
+ };
};
&uart3 {
--
2.12.2
^ permalink raw reply related
* [PATCH v2 3/5] misc: Add w2sg0004 (gps receiver) power control driver
From: H. Nikolaus Schaller @ 2017-11-12 20:59 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Benoît Cousson, Tony Lindgren,
Russell King, H. Nikolaus Schaller, Thierry Reding,
Jonathan Cameron, Maxime Ripard, Jarkko Sakkinen
Cc: devicetree, linux-kernel, linux-omap, letux-kernel, kernel
In-Reply-To: <cover.1510520397.git.hns@goldelico.com>
Add driver for Wi2Wi W2SG0004/84 GPS module connected through uart.
Use serdev API hooks to monitor and forward the UART traffic to /dev/GPSn
and turn on/off the module. It also detects if the module is turned on (sends data)
but should be off, e.g. if it was already turned on during boot or power-on-reset.
Additionally, rfkill block/unblock can be used to control an external LNA
(and power down the module if not needed).
The driver concept is based on code developed by NeilBrown <neilb@suse.de>
but simplified and adapted to use the new serdev API introduced in 4.11.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
drivers/misc/Kconfig | 10 +
drivers/misc/Makefile | 1 +
drivers/misc/w2sg0004.c | 565 +++++++++++++++++++++++++++++++++++++++++++++++
include/linux/w2sg0004.h | 27 +++
4 files changed, 603 insertions(+)
create mode 100644 drivers/misc/w2sg0004.c
create mode 100644 include/linux/w2sg0004.h
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 8136dc7e863d..09d171d68408 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -518,4 +518,14 @@ source "drivers/misc/mic/Kconfig"
source "drivers/misc/genwqe/Kconfig"
source "drivers/misc/echo/Kconfig"
source "drivers/misc/cxl/Kconfig"
+
+config W2SG0004
+ tristate "W2SG00x4 on/off control"
+ depends on GPIOLIB && SERIAL_DEV_BUS
+ help
+ Enable on/off control of W2SG00x4 GPS moduled connected
+ to some SoC UART to allow powering up/down if the /dev/ttyGPSn
+ is opened/closed.
+ It also provides a rfkill gps name to control the LNA power.
+
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ad0e64fdba34..abcb667e0ff0 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_SRAM_EXEC) += sram-exec.o
obj-y += mic/
obj-$(CONFIG_GENWQE) += genwqe/
obj-$(CONFIG_ECHO) += echo/
+obj-$(CONFIG_W2SG0004) += w2sg0004.o
obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
obj-$(CONFIG_CXL_BASE) += cxl/
obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
diff --git a/drivers/misc/w2sg0004.c b/drivers/misc/w2sg0004.c
new file mode 100644
index 000000000000..55101aa6beeb
--- /dev/null
+++ b/drivers/misc/w2sg0004.c
@@ -0,0 +1,565 @@
+/*
+ * w2sg0004.c
+ * Driver for power controlling the w2sg0004/w2sg0084 GPS receiver.
+ *
+ * This receiver has an ON/OFF pin which must be toggled to
+ * turn the device 'on' of 'off'. A high->low->high toggle
+ * will switch the device on if it is off, and off if it is on.
+ *
+ * To enable receiving on/off requests we register with the
+ * UART power management notifications.
+ *
+ * It is not possible to directly detect the state of the device.
+ * However when it is on it will send characters on a UART line
+ * regularly.
+ *
+ * To detect that the power state is out of sync (e.g. if GPS
+ * was enabled before a reboot), we register for UART data received
+ * notifications.
+ *
+ * In addition we register as a rfkill client so that we can
+ * control the LNA power.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_gpio.h>
+#include <linux/platform_device.h>
+#include <linux/rfkill.h>
+#include <linux/serdev.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/w2sg0004.h>
+#include <linux/workqueue.h>
+
+/*
+ * There seems to be restrictions on how quickly we can toggle the
+ * on/off line. data sheets says "two rtc ticks", whatever that means.
+ * If we do it too soon it doesn't work.
+ * So we have a state machine which uses the common work queue to ensure
+ * clean transitions.
+ * When a change is requested we record that request and only act on it
+ * once the previous change has completed.
+ * A change involves a 10ms low pulse, and a 990ms raised level, so only
+ * one change per second.
+ */
+
+enum w2sg_state {
+ W2SG_IDLE, /* is not changing state */
+ W2SG_PULSE, /* activate on/off impulse */
+ W2SG_NOPULSE /* deactivate on/off impulse */
+};
+
+struct w2sg_data {
+ struct rfkill *rf_kill;
+ struct regulator *lna_regulator;
+ int lna_blocked; /* rfkill block gps active */
+ int lna_is_off; /* LNA is currently off */
+ int is_on; /* current state (0/1) */
+ unsigned long last_toggle;
+ unsigned long backoff; /* time to wait since last_toggle */
+ int on_off_gpio; /* the on-off gpio number */
+ struct serdev_device *uart; /* uart connected to the chip */
+ struct tty_driver *tty_drv; /* this is the user space tty */
+ struct device *dev; /* from tty_port_register_device() */
+ struct tty_port port;
+ int open_count; /* how often we were opened */
+ enum w2sg_state state;
+ int requested; /* requested state (0/1) */
+ int suspended;
+ struct delayed_work work;
+ int discard_count;
+};
+
+static struct w2sg_data *w2sg_by_minor[1];
+
+static int w2sg_set_lna_power(struct w2sg_data *data)
+{
+ int ret = 0;
+ int off = data->suspended || !data->requested || data->lna_blocked;
+
+ pr_debug("%s: %s\n", __func__, off ? "off" : "on");
+
+ if (off != data->lna_is_off) {
+ data->lna_is_off = off;
+ if (!IS_ERR_OR_NULL(data->lna_regulator)) {
+ if (off)
+ regulator_disable(data->lna_regulator);
+ else
+ ret = regulator_enable(data->lna_regulator);
+ }
+ }
+
+ return ret;
+}
+
+static void w2sg_set_power(void *pdata, int val)
+{
+ struct w2sg_data *data = (struct w2sg_data *) pdata;
+
+ pr_debug("%s to state=%d (requested=%d)\n", __func__, val, data->requested);
+
+ if (val && !data->requested) {
+ data->requested = true;
+ } else if (!val && data->requested) {
+ data->backoff = HZ;
+ data->requested = false;
+ } else
+ return;
+
+ pr_debug("w2sg00x4 scheduled for %d\n", data->requested);
+
+ if (!data->suspended)
+ schedule_delayed_work(&data->work, 0);
+}
+
+/* called each time data is received by the UART (i.e. sent by the w2sg0004) */
+
+static int w2sg_uart_receive_buf(struct serdev_device *serdev,
+ const unsigned char *rxdata,
+ size_t count)
+{
+ struct w2sg_data *data =
+ (struct w2sg_data *) serdev_device_get_drvdata(serdev);
+
+ if (!data->requested && !data->is_on) {
+ /*
+ * we have received characters while the w2sg
+ * should have been be turned off
+ */
+ data->discard_count += count;
+ if ((data->state == W2SG_IDLE) &&
+ time_after(jiffies,
+ data->last_toggle + data->backoff)) {
+ /* Should be off by now, time to toggle again */
+ pr_debug("w2sg00x4 has sent %d characters data although it should be off!\n",
+ data->discard_count);
+
+ data->discard_count = 0;
+
+ data->is_on = true;
+ data->backoff *= 2;
+ if (!data->suspended)
+ schedule_delayed_work(&data->work, 0);
+ }
+ } else if (data->open_count > 0) {
+ int n;
+
+ pr_debug("w2sg00x4: push %d chars to tty port\n", count);
+
+ /* pass to user-space */
+ n = tty_insert_flip_string(&data->port, rxdata, count);
+ if (n != count)
+ pr_err("w2sg00x4: did loose %d characters\n", count - n);
+ tty_flip_buffer_push(&data->port);
+ return n;
+ }
+
+ /* assume we have processed everything */
+ return count;
+}
+
+/* try to toggle the power state by sending a pulse to the on-off GPIO */
+
+static void toggle_work(struct work_struct *work)
+{
+ struct w2sg_data *data = container_of(work, struct w2sg_data,
+ work.work);
+
+ switch (data->state) {
+ case W2SG_IDLE:
+ if (data->requested == data->is_on)
+ return;
+
+ w2sg_set_lna_power(data); /* update LNA power state */
+ gpio_set_value_cansleep(data->on_off_gpio, 0);
+ data->state = W2SG_PULSE;
+
+ pr_debug("w2sg: power gpio ON\n");
+
+ schedule_delayed_work(&data->work,
+ msecs_to_jiffies(10));
+ break;
+
+ case W2SG_PULSE:
+ gpio_set_value_cansleep(data->on_off_gpio, 1);
+ data->last_toggle = jiffies;
+ data->state = W2SG_NOPULSE;
+ data->is_on = !data->is_on;
+
+ pr_debug("w2sg: power gpio OFF\n");
+
+ schedule_delayed_work(&data->work,
+ msecs_to_jiffies(10));
+ break;
+
+ case W2SG_NOPULSE:
+ data->state = W2SG_IDLE;
+
+ pr_debug("w2sg: idle\n");
+
+ break;
+
+ }
+}
+
+static int w2sg_rfkill_set_block(void *pdata, bool blocked)
+{
+ struct w2sg_data *data = pdata;
+
+ pr_debug("%s: blocked: %d\n", __func__, blocked);
+
+ data->lna_blocked = blocked;
+
+ return w2sg_set_lna_power(data);
+}
+
+static struct rfkill_ops w2sg0004_rfkill_ops = {
+ .set_block = w2sg_rfkill_set_block,
+};
+
+static struct serdev_device_ops serdev_ops = {
+ .receive_buf = w2sg_uart_receive_buf,
+};
+
+/*
+ * we are a man-in the middle between the user-space visible tty port
+ * and the serdev tty where the chip is connected.
+ * This allows us to recognise when the device should be powered on
+ * or off and handle the "false" state that data arrives while no
+ * users-space tty client exists.
+ */
+
+static struct w2sg_data *w2sg_get_by_minor(unsigned int minor)
+{
+ return w2sg_by_minor[minor];
+}
+
+static int w2sg_tty_install(struct tty_driver *driver, struct tty_struct *tty)
+{
+ struct w2sg_data *data;
+ int retval;
+
+ pr_debug("%s() tty = %p\n", __func__, tty);
+
+ data = w2sg_get_by_minor(tty->index);
+
+ if (!data)
+ return -ENODEV;
+
+ retval = tty_standard_install(driver, tty);
+ if (retval)
+ goto error_init_termios;
+
+ tty->driver_data = data;
+
+ return 0;
+
+error_init_termios:
+ tty_port_put(&data->port);
+ return retval;
+}
+
+static int w2sg_tty_open(struct tty_struct *tty, struct file *file)
+{
+ struct w2sg_data *data = tty->driver_data;
+
+ pr_debug("%s() data = %p open_count = ++%d\n", __func__, data, data->open_count);
+
+ w2sg_set_power(data, ++data->open_count > 0);
+
+ return tty_port_open(&data->port, tty, file);
+}
+
+static void w2sg_tty_close(struct tty_struct *tty, struct file *file)
+{
+ struct w2sg_data *data = tty->driver_data;
+
+ pr_debug("%s()\n", __func__);
+
+ w2sg_set_power(data, --data->open_count > 0);
+
+ tty_port_close(&data->port, tty, file);
+}
+
+static int w2sg_tty_write(struct tty_struct *tty,
+ const unsigned char *buffer, int count)
+{
+ struct w2sg_data *data = tty->driver_data;
+
+ /* simply pass down to UART */
+ return serdev_device_write_buf(data->uart, buffer, count);
+}
+
+
+static const struct tty_operations w2sg_serial_ops = {
+ .install = w2sg_tty_install,
+ .open = w2sg_tty_open,
+ .close = w2sg_tty_close,
+ .write = w2sg_tty_write,
+};
+
+static const struct tty_port_operations w2sg_port_ops = {
+};
+
+static int w2sg_probe(struct serdev_device *serdev)
+{
+ struct w2sg_pdata *pdata = NULL;
+ struct w2sg_data *data;
+ struct rfkill *rf_kill;
+ int err;
+ int minor;
+
+ pr_debug("%s()\n", __func__);
+
+ minor = 0;
+ if (w2sg_by_minor[minor]) {
+ pr_err("w2sg minor is already in use!\n");
+ return -ENODEV;
+ }
+
+ if (serdev->dev.of_node) {
+ struct device *dev = &serdev->dev;
+ enum of_gpio_flags flags;
+
+ pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ pdata->on_off_gpio = of_get_named_gpio_flags(dev->of_node,
+ "enable-gpios", 0,
+ &flags);
+
+ /* defer until we have all gpios */
+ if (pdata->on_off_gpio == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ pdata->lna_regulator = devm_regulator_get_optional(dev, "lna");
+ if (IS_ERR(pdata->lna_regulator)) {
+ /* defer until we can get the regulator */
+ if (PTR_ERR(pdata->lna_regulator) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ pdata->lna_regulator = NULL;
+ }
+
+ pr_debug("%s() lna_regulator = %p\n", __func__,
+ pdata->lna_regulator);
+
+ serdev->dev.platform_data = pdata;
+ }
+
+ data = devm_kzalloc(&serdev->dev, sizeof(*data), GFP_KERNEL);
+ if (data == NULL)
+ return -ENOMEM;
+
+ w2sg_by_minor[minor] = data;
+
+ serdev_device_set_drvdata(serdev, data);
+
+ data->lna_regulator = pdata->lna_regulator;
+ data->lna_blocked = true;
+ data->lna_is_off = true;
+
+ data->on_off_gpio = pdata->on_off_gpio;
+
+ data->is_on = false;
+ data->requested = false;
+ data->state = W2SG_IDLE;
+ data->last_toggle = jiffies;
+ data->backoff = HZ;
+
+ data->uart = serdev;
+
+ INIT_DELAYED_WORK(&data->work, toggle_work);
+
+ err = devm_gpio_request(&serdev->dev, data->on_off_gpio,
+ "w2sg0004-on-off");
+ if (err < 0)
+ goto out;
+
+ gpio_direction_output(data->on_off_gpio, false);
+
+ serdev_device_set_client_ops(data->uart, &serdev_ops);
+ serdev_device_open(data->uart);
+
+ serdev_device_set_baudrate(data->uart, 9600);
+ serdev_device_set_flow_control(data->uart, false);
+
+ rf_kill = rfkill_alloc("GPS", &serdev->dev, RFKILL_TYPE_GPS,
+ &w2sg0004_rfkill_ops, data);
+ if (rf_kill == NULL) {
+ err = -ENOMEM;
+ goto err_rfkill;
+ }
+
+ err = rfkill_register(rf_kill);
+ if (err) {
+ dev_err(&serdev->dev, "Cannot register rfkill device\n");
+ goto err_rfkill;
+ }
+
+ data->rf_kill = rf_kill;
+
+ /* allocate the tty driver */
+ data->tty_drv = alloc_tty_driver(1);
+ if (!data->tty_drv)
+ return -ENOMEM;
+
+ /* initialize the tty driver */
+ data->tty_drv->owner = THIS_MODULE;
+ data->tty_drv->driver_name = "w2sg0004";
+ data->tty_drv->name = "ttyGPS";
+ data->tty_drv->major = 0;
+ data->tty_drv->minor_start = 0;
+ data->tty_drv->type = TTY_DRIVER_TYPE_SERIAL;
+ data->tty_drv->subtype = SERIAL_TYPE_NORMAL;
+ data->tty_drv->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
+ data->tty_drv->init_termios = tty_std_termios;
+ data->tty_drv->init_termios.c_cflag = B9600 | CS8 | CREAD |
+ HUPCL | CLOCAL;
+ /*
+ * optional:
+ * tty_termios_encode_baud_rate(&data->tty_drv->init_termios,
+ 115200, 115200);
+ * w2sg_tty_termios(&data->tty_drv->init_termios);
+ */
+ tty_set_operations(data->tty_drv, &w2sg_serial_ops);
+
+ /* register the tty driver */
+ err = tty_register_driver(data->tty_drv);
+ if (err) {
+ pr_err("%s - tty_register_driver failed(%d)\n",
+ __func__, err);
+ put_tty_driver(data->tty_drv);
+ goto err_rfkill;
+ }
+
+ tty_port_init(&data->port);
+ data->port.ops = &w2sg_port_ops;
+
+/*
+ * FIXME: this appears to reenter this probe() function a second time
+ * which only fails because the gpio is already assigned
+ */
+
+ data->dev = tty_port_register_device(&data->port,
+ data->tty_drv, minor, &serdev->dev);
+
+ pr_debug("w2sg probed\n");
+
+ /* keep off until user space requests the device */
+ w2sg_set_power(data, false);
+
+ return 0;
+
+err_rfkill:
+ rfkill_destroy(rf_kill);
+ serdev_device_close(data->uart);
+out:
+ return err;
+}
+
+static void w2sg_remove(struct serdev_device *serdev)
+{
+ struct w2sg_data *data = serdev_device_get_drvdata(serdev);
+ int minor;
+
+ cancel_delayed_work_sync(&data->work);
+
+ /* what is the right sequence to avoid problems? */
+ serdev_device_close(data->uart);
+
+ minor = 0;
+ tty_unregister_device(data->tty_drv, minor);
+
+ tty_unregister_driver(data->tty_drv);
+}
+
+static int w2sg_suspend(struct device *dev)
+{
+ struct w2sg_data *data = dev_get_drvdata(dev);
+
+ data->suspended = true;
+
+ cancel_delayed_work_sync(&data->work);
+
+ w2sg_set_lna_power(data); /* shuts down if needed */
+
+ if (data->state == W2SG_PULSE) {
+ msleep(10);
+ gpio_set_value_cansleep(data->on_off_gpio, 1);
+ data->last_toggle = jiffies;
+ data->is_on = !data->is_on;
+ data->state = W2SG_NOPULSE;
+ }
+
+ if (data->state == W2SG_NOPULSE) {
+ msleep(10);
+ data->state = W2SG_IDLE;
+ }
+
+ if (data->is_on) {
+ pr_info("GPS off for suspend %d %d %d\n", data->requested,
+ data->is_on, data->lna_is_off);
+
+ gpio_set_value_cansleep(data->on_off_gpio, 0);
+ msleep(10);
+ gpio_set_value_cansleep(data->on_off_gpio, 1);
+ data->is_on = 0;
+ }
+
+ return 0;
+}
+
+static int w2sg_resume(struct device *dev)
+{
+ struct w2sg_data *data = dev_get_drvdata(dev);
+
+ data->suspended = false;
+
+ pr_info("GPS resuming %d %d %d\n", data->requested,
+ data->is_on, data->lna_is_off);
+
+ schedule_delayed_work(&data->work, 0); /* enables LNA if needed */
+
+ return 0;
+}
+
+#if defined(CONFIG_OF)
+static const struct of_device_id w2sg0004_of_match[] = {
+ { .compatible = "wi2wi,w2sg0004" },
+ { .compatible = "wi2wi,w2sg0084" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, w2sg0004_of_match);
+#endif
+
+SIMPLE_DEV_PM_OPS(w2sg_pm_ops, w2sg_suspend, w2sg_resume);
+
+static struct serdev_device_driver w2sg_driver = {
+ .probe = w2sg_probe,
+ .remove = w2sg_remove,
+ .driver = {
+ .name = "w2sg0004",
+ .owner = THIS_MODULE,
+ .pm = &w2sg_pm_ops,
+ .of_match_table = of_match_ptr(w2sg0004_of_match)
+ },
+};
+
+module_serdev_device_driver(w2sg_driver);
+
+MODULE_ALIAS("w2sg0004");
+
+MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
+MODULE_DESCRIPTION("w2sg0004 GPS power management driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/w2sg0004.h b/include/linux/w2sg0004.h
new file mode 100644
index 000000000000..ad0c4a18e01d
--- /dev/null
+++ b/include/linux/w2sg0004.h
@@ -0,0 +1,27 @@
+/*
+ * UART slave to allow ON/OFF control of w2sg0004 GPS receiver.
+ *
+ * Copyright (C) 2011 Neil Brown <neil@brown.name>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+
+
+#ifndef __LINUX_W2SG0004_H
+#define __LINUX_W2SG0004_H
+
+#include <linux/regulator/consumer.h>
+
+struct w2sg_pdata {
+ struct regulator *lna_regulator; /* enable LNA power */
+ int on_off_gpio; /* on-off input of the GPS module */
+};
+#endif /* __LINUX_W2SG0004_H */
--
2.12.2
^ permalink raw reply related
* [PATCH v2 2/5] DT: misc: w2sg0004: add bindings documentation (GPS module with serdev UART)
From: H. Nikolaus Schaller @ 2017-11-12 20:59 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Benoît Cousson, Tony Lindgren,
Russell King, H. Nikolaus Schaller, Thierry Reding,
Jonathan Cameron, Maxime Ripard, Jarkko Sakkinen
Cc: devicetree, linux-kernel, linux-omap, letux-kernel, kernel
In-Reply-To: <cover.1510520397.git.hns@goldelico.com>
add bindings documentation for Wi2Wi W2SG00x4 GPS module
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
.../devicetree/bindings/misc/wi2wi,w2sg0004.txt | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/wi2wi,w2sg0004.txt
diff --git a/Documentation/devicetree/bindings/misc/wi2wi,w2sg0004.txt b/Documentation/devicetree/bindings/misc/wi2wi,w2sg0004.txt
new file mode 100644
index 000000000000..ccec9361a1a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/wi2wi,w2sg0004.txt
@@ -0,0 +1,24 @@
+Wi2Wi GPS module connected through UART
+
+Should be a subnode of the SoC UART it is connected to (serdev).
+
+Required properties:
+- compatible: should be one of (depending on precise model)
+ "wi2wi,w2sg0004"
+ "wi2wi,w2sg0084"
+- enable-gpio: the GPIO that controls the module's power toggle
+ input. A positive impulse of sufficent length toggles the
+ power state.
+
+Optional properties:
+- lna-supply: an (optional) LNA regulator that is enabled together with the GPS receiver
+
+Example:
+
+&uart2 {
+ w2sg0004: gps {
+ compatible = "wi2wi,w2sg0004";
+ lna-supply = <&vsim>; /* LNA regulator */
+ enable-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* GPIO_145: trigger for turning on/off w2sg0004 */
+ };
+};
--
2.12.2
^ permalink raw reply related
* [PATCH v2 1/5] DT: vendor prefix for Wi2Wi, Inc.
From: H. Nikolaus Schaller @ 2017-11-12 20:59 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Benoît Cousson, Tony Lindgren,
Russell King, H. Nikolaus Schaller, Thierry Reding,
Jonathan Cameron, Maxime Ripard, Jarkko Sakkinen
Cc: devicetree, linux-kernel, linux-omap, letux-kernel, kernel
In-Reply-To: <cover.1510520397.git.hns@goldelico.com>
Introduce vendor prefix for Wi2Wi, Inc. for W2SG00x4 GPS modules
and W2CBW003 Bluetooth/WiFi combo (CSR/Marvell).
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 1afd298eddd7..ad4381738954 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -366,6 +366,7 @@ voipac Voipac Technologies s.r.o.
wd Western Digital Corp.
wetek WeTek Electronics, limited.
wexler Wexler
+wi2wi Wi2Wi, Inc.
winbond Winbond Electronics corp.
winstar Winstar Display Corp.
wlf Wolfson Microelectronics
--
2.12.2
^ permalink raw reply related
* [PATCH v2 0/5] misc: new serdev based drivers for Wi2Wi w2sg00x4 GPS module
From: H. Nikolaus Schaller @ 2017-11-12 20:59 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Benoît Cousson, Tony Lindgren,
Russell King, H. Nikolaus Schaller, Thierry Reding,
Jonathan Cameron, Maxime Ripard, Jarkko Sakkinen
Cc: devicetree, linux-kernel, linux-omap, letux-kernel, kernel
Changes V2:
* reduced to submit only w2sg00x4 GPS driver code
* add DT node for GTA04 device to make use of the driver
* split into base code and a debugging Kconfig option (brings device into false power state after boot)
* worked in comments by kbuild robot and Rob Herring
2017-05-21 12:44:07: RFC V1
* RFC concerning new serdev based drivers for Wi2Wi w2sg00x4 GPS module and w2cbw003 bluetooth
H. Nikolaus Schaller (5):
DT: vendor prefix for Wi2Wi, Inc.
DT: misc: w2sg0004: add bindings documentation (GPS module with serdev
UART)
misc: Add w2sg0004 (gps receiver) power control driver
DTS: gta04: add serdev node for w2sg00x4
misc: w2sg0004: add debugging code and Kconfig
.../devicetree/bindings/misc/wi2wi,w2sg0004.txt | 24 +
.../devicetree/bindings/vendor-prefixes.txt | 1 +
arch/arm/boot/dts/omap3-gta04.dtsi | 6 +
drivers/misc/Kconfig | 18 +
drivers/misc/Makefile | 1 +
drivers/misc/w2sg0004.c | 602 +++++++++++++++++++++
include/linux/w2sg0004.h | 27 +
7 files changed, 679 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/wi2wi,w2sg0004.txt
create mode 100644 drivers/misc/w2sg0004.c
create mode 100644 include/linux/w2sg0004.h
--
2.12.2
^ permalink raw reply
* Re: [PATCH v7 usb-next 4/4] dt-bindings: usb: xhci: include the roothub and a device in the example
From: Martin Blumenstingl @ 2017-11-12 20:48 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Alan Stern, Rob Herring, linux-usb-u79uwXL29TY76Z2rM5mHXA, gregkh,
felipe.balbi-VuQAYsv1563Yd54FQh9/CA,
mathias.nyman-ral2JQCrhuEAvxtiuMwx3w, DTML, Mark Rutland,
open list:ARM/Amlogic Meson SoC support, Chunfeng Yun
In-Reply-To: <CAFBinCBJuL7J7847ZU0jO=O0WuwNZj_oBT4NO1+ge11dEbQL+w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi Arnd (and anyone else who is interested in this),
On Mon, Oct 30, 2017 at 11:59 PM, Martin Blumenstingl
<martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> wrote:
> Hi Arnd,
>
> On Mon, Oct 30, 2017 at 3:08 PM, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:
>> On Sat, Oct 28, 2017 at 3:33 PM, Martin Blumenstingl
>> <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> wrote:
>>> On Fri, Oct 27, 2017 at 9:55 PM, Alan Stern <stern-nwvwT67g6+6dFdvTe/nMLpVzexx5G7lz@public.gmane.org> wrote:
>>>> On Fri, 27 Oct 2017, Martin Blumenstingl wrote:
>>>>> >> diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
>>>>> >> index 5b49ba9f2f9a..20e5ce2b016a 100644
>>>>> >> --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
>>>>> >> +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
>>>>> >> @@ -42,4 +42,27 @@ Example:
>>>>> >> compatible = "generic-xhci";
>>>>> >> reg = <0xf0931000 0x8c8>;
>>>>> >> interrupts = <0x0 0x4e 0x0>;
>>>>> >> +
>>>>> >> + #address-cells = <1>;
>>>>> >> + #size-cells = <0>;
>>>>> >> +
>>>>> >> + /* see usb-roothub.txt */
>>>>> >> + roothub@0 {
>>>>> >> + compatible = "usb1d6b,3", "usb1d6b,2";
>>>>> >> + #address-cells = <1>;
>>>>> >> + #size-cells = <0>;
>>>>> >> + reg = <0>;
>>>>> >> +
>>>>> >> + port@1 {
>>>>> >> + reg = <1>;
>>>>> >> + phys = <&usb2_phy1>, <&usb3_phy1>;
>>>>> >> + phy-names = "usb2-phy", "usb3-phy";
>>>>> >> + };
>>>>> >> + };
>>>>> >> +
>>>>> >> + /* see usb-device.txt */
>>>>> >> + hub: genesys@1 {
>>
>>>> Two things to be aware of:
>>>>
>>>> 1. /sys/kernel/debug/usb/devices has an off-by-one error in the
>>>> "Port=" field. Every value you see should actually be one
>>>> higher than it is. It has been this way for many, many years
>>>> so we can't fix it now.
>>> here's the output of "lsusb -t" (which is easier to read I guess):
>>> # lsusb -t
>>> /: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/0p, 5000M
>>> /: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/2p, 480M
>>> |__ Port 1: Dev 2, If 0, Class=Hub, Driver=hub/4p, 480M
>>> |__ Port 3: Dev 3, If 0, Class=Mass Storage, Driver=usb-storage, 480M
>>
>> I see two possible problems here:
>>
>> * Linux does show the root hub as a parent of the external hub,
>> while the DT shows them as two unrelated children of the host
>> controller. This clearly doesn't reflect the reality, and may come
>> to bite us again later when we try to extend it in some other way.
> ok, I see your point here
>
>> * Listing the root hub as compatible="usb1d6b,3" encodes a Linux
>> implementation detail into the OS-independent DT ABI: The
>> root hub does not actually have this vendor/device ID, it's
>> just something we make up in Linux.
> I see, this would have to be more generic then (compatible =
> "usb-root-hub", etc..)
> however, let's postpone this discussion and evaluate more options (see below)
>
>> I think you mentioned that an earlier version of the patch set
>> did not have the root hub at all but instead listed the PHYs directly
>> under the host controller. Can you summarize what the problem
>> with that approach was?
> this is going on for a while now, I think it started with Rob's
> comment here: [0]
> I do not remember any explicit NACKs on that idea
>
> I took a step back and tried to figure out the
> requirements/constraints again (in no specific order):
> a) we need to initialize multiple PHYs on an xHCI controller
> b) other USB controller implementation already initialize multiple
> PHYs (see [1]) and we must not break these
> c) we need to make sure that we don't get any conflicts when specifying PHYs
> (for example: if we pass the PHY for the root-hub/controller port 1
> at &usb/device@1 then we may run into a problem where device@1 also
> requires a USB PHY. I'm not sure if such cases exist in real-life
> though)
> d) currently the devicetree phy bindings state that a phy-names
> property is mandatory (see [2], I interpret this as 'we cannot have
> "phys = <...>" without "phy-names = ...'")
> e) existing USB OF helper functions (like of_usb_get_dr_mode_by_phy)
> rely on the fact that the PHY is specified directly at the controller
> f) DT hierarchy should match the reality
> g) ...feel free to name more
>
> defining the PHYs directly under the controller node gives these
> results (my own interpretation):
> a) we can implement this similar to my current patch (the only
> difference would be where the code takes the PHYs from)
> b) I am not familiar with these other drivers, however we might be
> able to fix those by simply removing the "parse all PHYs" code from
> them (and rely on our new code)
> c) I don't see any problems, if a controller needs more than just an
> USB PHY then we could still use the "phy-names" to skip all non USB
> PHYs
> d) we would either have to make phy-names optional for this specific
> use-case or come up with a convention how the phy-names should be
> built for our case
> e) of_usb_get_dr_mode_by_phy and friends would still work - no changes required
> f) hierarchy matches the reality if we define that the root-hub is not
> specified in device-tree (this would mean that we simply treat the
> PHYs as properties of the controller, I'm not aware of any other
> "root-hub" specific properties)
>
> defining the PHYs in a root-hub node gives these results (my own
> interpretation):
> a) that's what this series does
> b) we're not touching the other implementations - however, existing
> .dts files would have to be changed to switch to this new binding
> c) the root-hub is currently separated, so there are no conflicts
> (needs more thoughts though if we need to nest the USB devices below
> the root-hub)
> d) phy-names can be specified easily and non USB PHYs are skipped by
> the current code already
> e) of_usb_get_dr_mode_by_phy and friends would have to be adjusted
> (not part of this series yet)
> f) the root-hub is now described in devicetree but the hierarchy may
> not be correct
>
> could you please let me know if you see more requirements or constraints?
> do you agree with my interpretation of the two possible solutions (and
> even more important: which are the ones you don't agree with)?
did you have time to go through this yet?
I have more time to work on this next week
>> Is it correct that roothub@0/port@1 corresponds to the same
>> connector that genesys@1 is connected to?
> yes, both refer to the same port/connector
>
>
> Regards
> Martin
>
>
> [0] http://lists.infradead.org/pipermail/linux-amlogic/2016-November/001818.html
> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-January/001947.html
> [2] http://elixir.free-electrons.com/linux/v4.13.9/source/Documentation/devicetree/bindings/phy/phy-bindings.txt#L33
Regards
Martin
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^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: orange-pi-zero-plus2: enable AP6212a WiFi/BT combo
From: Sergey Matyukevich @ 2017-11-12 20:22 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Rob Herring, Mark Rutland
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jagan Teki
In-Reply-To: <20171103195855.15283-3-geomatsi-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Enable AP6212a WiFi/BT combo chip on orange-pi-zero-plus2 board:
> - WiFi SDIO interface is connected to MMC1
> - WiFi REG_ON pin connected to gpio PA9: attach to mmc-pwrseq
> - WiFi HOST_WAKE pin connected to gpio PL7
> - BT is connected to UART1
Hi Maxime and all,
Any comments regarding this patch ?
Regards,
Sergey
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* Re: [PATCH v4 1/5] ARM: tegra: Add device tree node to describe IRAM
From: Dmitry Osipenko @ 2017-11-12 16:28 UTC (permalink / raw)
To: Vladimir Zapolskiy, Thierry Reding, Jonathan Hunter,
Greg Kroah-Hartman, Rob Herring, Mauro Carvalho Chehab,
Stephen Warren
Cc: devel, devicetree, linux-kernel, linux-tegra, Dan Carpenter,
linux-media
In-Reply-To: <ffa5f1d0-f156-0bc3-6adb-bb55a0a855c4@mleia.com>
On 11.11.2017 17:18, Vladimir Zapolskiy wrote:
> Hi Dmitry,
>
> On 10/20/2017 12:34 AM, Dmitry Osipenko wrote:
>> From: Vladimir Zapolskiy <vz@mleia.com>
>>
>> All Tegra SoCs contain 256KiB IRAM, which is used to store CPU resume code
>> and by hardware engines like a video decoder.
>>
>> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
>
> Please add also your own closing "Signed-off-by" tag, please reference
> to "Developer's Certificate of Origin 1.1", point (c), it is found in
> Documentation/process/submitting-patches.rst
>
Indeed, thanks!
>> ---
>> arch/arm/boot/dts/tegra114.dtsi | 8 ++++++++
>> arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++
>> arch/arm/boot/dts/tegra20.dtsi | 8 ++++++++
>> arch/arm/boot/dts/tegra30.dtsi | 8 ++++++++
>
> My assumption is that Thierry would prefer to get 4 separate patches,
> one for each platform, please split the patch.
>
Thierry, would you?
> Also thanks for your time and your efforts applied to push my occasional
> change, please feel free to take your own authorship for 3 out of 4 patches.
>
Okay.
>> 4 files changed, 32 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
>> index 8932ea3afd5f..13f6087790c8 100644
>> --- a/arch/arm/boot/dts/tegra114.dtsi
>> +++ b/arch/arm/boot/dts/tegra114.dtsi
>> @@ -10,6 +10,14 @@
>> compatible = "nvidia,tegra114";
>> interrupt-parent = <&lic>;
>>
>> + iram@40000000 {
>> + compatible = "mmio-sram";
>
> Unfortunately Thierry hasn't yet replied, but my assumption is that
> the list of compatibles should be extended with one more SoC specific
> value like
>
> compatible = "nvidia,tegra114-sysram", "mmio-sram";
>
> I'm not sure, if Tegra maintainers want to see a new compatible
> described in Documentation/devicetree/bindings.
>
The custom compatible string shouldn't be needed. AFAIK, IRAM doesn't have any
exposed controls, so just a generic "mmio-sram" suits well here.
>> + reg = <0x40000000 0x40000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x40000000 0x40000>;
>> + };
>> +
>> host1x@50000000 {
>> compatible = "nvidia,tegra114-host1x", "simple-bus";
>> reg = <0x50000000 0x00028000>;
>> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
>> index 8baf00b89efb..a3585ed82646 100644
>> --- a/arch/arm/boot/dts/tegra124.dtsi
>> +++ b/arch/arm/boot/dts/tegra124.dtsi
>
> The considerations from above are applicable to the rest of
> the touched platforms.
^ permalink raw reply
* Re: [PATCH v4 2/5] media: dt: bindings: Add binding for NVIDIA Tegra Video Decoder Engine
From: Dmitry Osipenko @ 2017-11-12 16:19 UTC (permalink / raw)
To: Vladimir Zapolskiy, Thierry Reding, Jonathan Hunter,
Greg Kroah-Hartman, Rob Herring, Mauro Carvalho Chehab,
Stephen Warren
Cc: Dan Carpenter, linux-media-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <6492d1af-19fa-253f-2b75-2c37ccd44cbe-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
On 11.11.2017 17:21, Vladimir Zapolskiy wrote:
> Hi Dmitry,
>
> On 10/20/2017 12:34 AM, Dmitry Osipenko wrote:
>> Add binding documentation for the Video Decoder Engine which is found
>> on NVIDIA Tegra20/30/114/124/132 SoC's.
>>
>> Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>> .../devicetree/bindings/media/nvidia,tegra-vde.txt | 55 ++++++++++++++++++++++
>> 1 file changed, 55 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
>>
>> diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
>> new file mode 100644
>> index 000000000000..470237ed6fe5
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
>> @@ -0,0 +1,55 @@
>> +NVIDIA Tegra Video Decoder Engine
>> +
>> +Required properties:
>> +- compatible : Must contain one of the following values:
>> + - "nvidia,tegra20-vde"
>> + - "nvidia,tegra30-vde"
>> + - "nvidia,tegra114-vde"
>> + - "nvidia,tegra124-vde"
>> + - "nvidia,tegra132-vde"
>> +- reg : Must contain an entry for each entry in reg-names.
>> +- reg-names : Must include the following entries:
>> + - sxe
>> + - bsev
>> + - mbe
>> + - ppe
>> + - mce
>> + - tfe
>> + - ppb
>> + - vdma
>> + - frameid
>
> I've already mentioned it in my review of the driver code, but the
> version from v3 with a single region is more preferable.
>
> Also it implies that "reg-names" property will be removed.
>
Please see my reply to the drivers code review.
>> +- iram : Must contain phandle to the mmio-sram device node that represents
>> + IRAM region used by VDE.
>> +- interrupts : Must contain an entry for each entry in interrupt-names.
>> +- interrupt-names : Must include the following entries:
>> + - sync-token
>> + - bsev
>> + - sxe
>> +- clocks : Must include the following entries:
>> + - vde
>> +- resets : Must include the following entries:
>> + - vde
>> +
>> +Example:
>> +
>> +video-codec@6001a000 {
>> + compatible = "nvidia,tegra20-vde";
>> + reg = <0x6001a000 0x1000 /* Syntax Engine */
>> + 0x6001b000 0x1000 /* Video Bitstream Engine */
>> + 0x6001c000 0x100 /* Macroblock Engine */
>> + 0x6001c200 0x100 /* Post-processing Engine */
>> + 0x6001c400 0x100 /* Motion Compensation Engine */
>> + 0x6001c600 0x100 /* Transform Engine */
>> + 0x6001c800 0x100 /* Pixel prediction block */
>> + 0x6001ca00 0x100 /* Video DMA */
>> + 0x6001d800 0x300 /* Video frame controls */>;
>> + reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
>> + "tfe", "ppb", "vdma", "frameid";
>> + iram = <&vde_pool>; /* IRAM region */
>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
>> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
>> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
>> + interrupt-names = "sync-token", "bsev", "sxe";
>> + clocks = <&tegra_car TEGRA20_CLK_VDE>;
>> + resets = <&tegra_car 61>;
>> +};
>>
^ permalink raw reply
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