* [PATCH v5 3/6] remoteproc: qcom: Push reset ops, fw ops, rproc ops in to of_match data
From: Sricharan R @ 2017-11-14 10:53 UTC (permalink / raw)
To: bjorn.andersson, ohad, robh+dt, mark.rutland, andy.gross,
david.brown, linux-remoteproc, devicetree, linux-kernel,
linux-arm-msm, linux-soc
Cc: sricharan
In-Reply-To: <1510656794-3815-1-git-send-email-sricharan@codeaurora.org>
Instead of directly assigning reset, fw and rproc ops, put them
in to of_match data and get from that. Currently same ops
are used for all compatibles, but that will change when we add
q6v5-wcss support.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 38 +++++++++++++++++++++++++-------------
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index df8723d..769c6af 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -116,16 +116,6 @@ struct qcom_mss_reg_res {
int uA;
};
-struct rproc_hexagon_res {
- const char *hexagon_mba_image;
- struct qcom_mss_reg_res *proxy_supply;
- struct qcom_mss_reg_res *active_supply;
- char **proxy_clk_names;
- char **active_clk_names;
- int version;
- bool need_mem_protection;
-};
-
struct q6v5 {
struct device *dev;
struct rproc *rproc;
@@ -174,6 +164,19 @@ struct q6v5 {
int version;
};
+struct rproc_hexagon_res {
+ const char *hexagon_mba_image;
+ struct qcom_mss_reg_res *proxy_supply;
+ struct qcom_mss_reg_res *active_supply;
+ char **proxy_clk_names;
+ char **active_clk_names;
+ int version;
+ bool need_mem_protection;
+ int (*init_reset)(struct q6v5 *qproc);
+ const struct rproc_fw_ops *fw_ops;
+ const struct rproc_ops *ops;
+};
+
enum {
MSS_MSM8916,
MSS_MSM8974,
@@ -1128,14 +1131,14 @@ static int q6v5_probe(struct platform_device *pdev)
if (!desc)
return -EINVAL;
- rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
+ rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
desc->hexagon_mba_image, sizeof(*qproc));
if (!rproc) {
dev_err(&pdev->dev, "failed to allocate rproc\n");
return -ENOMEM;
}
- rproc->fw_ops = &q6v5_fw_ops;
+ rproc->fw_ops = desc->fw_ops;
qproc = (struct q6v5 *)rproc->priv;
qproc->dev = &pdev->dev;
@@ -1185,7 +1188,7 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->active_reg_count = ret;
- ret = q6v5_init_reset(qproc);
+ ret = desc->init_reset(qproc);
if (ret)
goto free_rproc;
@@ -1258,6 +1261,9 @@ static int q6v5_remove(struct platform_device *pdev)
},
.need_mem_protection = true,
.version = MSS_MSM8996,
+ .init_reset = q6v5_init_reset,
+ .fw_ops = &q6v5_fw_ops,
+ .ops = &q6v5_ops,
};
static const struct rproc_hexagon_res msm8916_mss = {
@@ -1289,6 +1295,9 @@ static int q6v5_remove(struct platform_device *pdev)
},
.need_mem_protection = false,
.version = MSS_MSM8916,
+ .init_reset = q6v5_init_reset,
+ .fw_ops = &q6v5_fw_ops,
+ .ops = &q6v5_ops,
};
static const struct rproc_hexagon_res msm8974_mss = {
@@ -1328,6 +1337,9 @@ static int q6v5_remove(struct platform_device *pdev)
},
.need_mem_protection = false,
.version = MSS_MSM8974,
+ .init_reset = q6v5_init_reset,
+ .fw_ops = &q6v5_fw_ops,
+ .ops = &q6v5_ops,
};
static const struct of_device_id q6v5_of_match[] = {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v5 4/6] remoteproc: qcom: Split the head and tail of the q6v5-pil rproc start function
From: Sricharan R @ 2017-11-14 10:53 UTC (permalink / raw)
To: bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A,
ohad-Ix1uc/W3ht7QT0dZR+AlfA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, andy.gross-QSEj5FYQhm4dnm+yROfE0A,
david.brown-QSEj5FYQhm4dnm+yROfE0A,
linux-remoteproc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA
Cc: sricharan-sgV2jX0FEOL9JmXXK+q4OQ
In-Reply-To: <1510656794-3815-1-git-send-email-sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Most of the q6v5-pil start function is same for the q6v5-wcss rproc
that will be added later. So split and move out the common pieces
so that the same code can be reused.
Signed-off-by: Sricharan R <sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 166 ++++++++++++++++++++-----------------
1 file changed, 91 insertions(+), 75 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 769c6af..75ff02d 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -405,75 +405,107 @@ static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
return val;
}
-static int q6v5proc_reset(struct q6v5 *qproc)
+static int q6v5_reset(struct q6v5 *qproc)
{
- u32 val;
- int ret;
- int i;
+ u32 ret;
+ int val, i;
+ /* Assert resets, stop core */
+ val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
+ val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
+ writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
- if (qproc->version == MSS_MSM8996) {
- /* Override the ACC value if required */
- writel(QDSP6SS_ACC_OVERRIDE_VAL,
- qproc->reg_base + QDSP6SS_STRAP_ACC);
+ /* BHS require xo cbcr to be enabled */
+ val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
+ val |= 0x1;
+ writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
- /* Assert resets, stop core */
- val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
- val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
- writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+ /* Read CLKOFF bit to go low indicating CLK is enabled */
+ ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
+ val, !(val & BIT(31)), 1,
+ HALT_CHECK_MAX_LOOPS);
+ if (ret) {
+ dev_err(qproc->dev,
+ "xo cbcr enabling timed out (rc:%d)\n", ret);
+ return ret;
+ }
+ /* Enable power block headswitch and wait for it to stabilize */
+ val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ val |= QDSP6v56_BHS_ON;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ udelay(1);
- /* BHS require xo cbcr to be enabled */
- val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
- val |= 0x1;
- writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
+ /* Put LDO in bypass mode */
+ val |= QDSP6v56_LDO_BYP;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
- /* Read CLKOFF bit to go low indicating CLK is enabled */
- ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
- val, !(val & BIT(31)), 1,
- HALT_CHECK_MAX_LOOPS);
- if (ret) {
- dev_err(qproc->dev,
- "xo cbcr enabling timed out (rc:%d)\n", ret);
- return ret;
- }
- /* Enable power block headswitch and wait for it to stabilize */
- val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
- val |= QDSP6v56_BHS_ON;
- writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
- val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ /* Deassert QDSP6 compiler memory clamp */
+ val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ val &= ~QDSP6v56_CLAMP_QMC_MEM;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+ /* Deassert memory peripheral sleep and L2 memory standby */
+ val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+ /* Turn on L1, L2, ETB and JU memories 1 at a time */
+ val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
+ for (i = 19; i >= 0; i--) {
+ val |= BIT(i);
+ writel(val, qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
+ /*
+ * Read back value to ensure the write is done then
+ * wait for 1us for both memory peripheral and data
+ * array to turn on.
+ */
+ val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
udelay(1);
+ }
+ /* Remove word line clamp */
+ val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ val &= ~QDSP6v56_CLAMP_WL;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
- /* Put LDO in bypass mode */
- val |= QDSP6v56_LDO_BYP;
- writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ return 0;
+}
- /* Deassert QDSP6 compiler memory clamp */
- val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
- val &= ~QDSP6v56_CLAMP_QMC_MEM;
- writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+static void q6v5_reset_rest(struct q6v5 *qproc)
+{
+ u32 val;
- /* Deassert memory peripheral sleep and L2 memory standby */
- val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
- writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
- /* Turn on L1, L2, ETB and JU memories 1 at a time */
- val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
- for (i = 19; i >= 0; i--) {
- val |= BIT(i);
- writel(val, qproc->reg_base +
- QDSP6SS_MEM_PWR_CTL);
- /*
- * Read back value to ensure the write is done then
- * wait for 1us for both memory peripheral and data
- * array to turn on.
- */
- val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
- udelay(1);
- }
- /* Remove word line clamp */
- val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
- val &= ~QDSP6v56_CLAMP_WL;
- writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ /* Remove IO clamp */
+ val &= ~Q6SS_CLAMP_IO;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+ /* Bring core out of reset */
+ val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
+ val &= ~Q6SS_CORE_ARES;
+ writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+
+ /* Turn on core clock */
+ val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
+ val |= Q6SS_CLK_ENABLE;
+ writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
+
+ /* Start core execution */
+ val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
+ val &= ~Q6SS_STOP_CORE;
+ writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+}
+
+static int q6v5proc_reset(struct q6v5 *qproc)
+{
+ u32 val;
+ int ret;
+
+ if (qproc->version == MSS_MSM8996) {
+ /* Override the ACC value if required */
+ writel(QDSP6SS_ACC_OVERRIDE_VAL,
+ qproc->reg_base + QDSP6SS_STRAP_ACC);
+ q6v5_reset(qproc);
} else {
/* Assert resets, stop core */
val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
@@ -501,24 +533,8 @@ static int q6v5proc_reset(struct q6v5 *qproc)
val |= Q6SS_L2DATA_SLP_NRET_N_0;
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
}
- /* Remove IO clamp */
- val &= ~Q6SS_CLAMP_IO;
- writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-
- /* Bring core out of reset */
- val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
- val &= ~Q6SS_CORE_ARES;
- writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
- /* Turn on core clock */
- val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
- val |= Q6SS_CLK_ENABLE;
- writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
-
- /* Start core execution */
- val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
- val &= ~Q6SS_STOP_CORE;
- writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+ q6v5_reset_rest(qproc);
/* Wait for PBL status */
ret = q6v5_rmb_pbl_wait(qproc, 1000);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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^ permalink raw reply related
* [PATCH v5 5/6] remoteproc: qcom: Add support for q6v5-wcss pil
From: Sricharan R @ 2017-11-14 10:53 UTC (permalink / raw)
To: bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A,
ohad-Ix1uc/W3ht7QT0dZR+AlfA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, andy.gross-QSEj5FYQhm4dnm+yROfE0A,
david.brown-QSEj5FYQhm4dnm+yROfE0A,
linux-remoteproc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA
Cc: sricharan-sgV2jX0FEOL9JmXXK+q4OQ
In-Reply-To: <1510656794-3815-1-git-send-email-sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
IPQ8074 has an integrated Hexagon dsp core q6v5 and a wireless lan
(Lithium) IP. An mdt type single image format is used for the
firmware. So the mdt_load function can be directly used to load
the firmware. Also add the relevant resets required for this core.
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Sricharan R <sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 ++-
drivers/remoteproc/Kconfig | 1 +
drivers/remoteproc/qcom_q6v5_pil.c | 53 +++++++++++++++++++++-
3 files changed, 59 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 00d3d58..d52d05e 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -11,6 +11,7 @@ on the Qualcomm Hexagon core.
"qcom,msm8916-mss-pil",
"qcom,msm8974-mss-pil"
"qcom,msm8996-mss-pil"
+ "qcom,ipq8074-wcss-pil"
- reg:
Usage: required
@@ -49,11 +50,15 @@ on the Qualcomm Hexagon core.
Usage: required
Value type: <phandle>
Definition: reference to the reset-controller for the modem sub-system
+ reference to the list of 3 reset-controllers for the
+ wcss sub-system
- reset-names:
Usage: required
Value type: <stringlist>
- Definition: must be "mss_restart"
+ Definition: must be "mss_restart" for the modem sub-system
+ Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
+ for the wcss syb-system
- cx-supply:
- mss-supply:
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index bf04479..e7e9979 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -113,6 +113,7 @@ config QCOM_Q6V5_PIL
select MFD_SYSCON
select QCOM_RPROC_COMMON
select QCOM_SCM
+ select QCOM_MDT_LOADER
help
Say y here to support the Qualcomm Peripherial Image Loader for the
Hexagon V5 based remote processors.
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 75ff02d..3c401ff 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -129,6 +129,9 @@ struct q6v5 {
u32 halt_nc;
struct reset_control *mss_restart;
+ struct reset_control *wcss_aon_reset;
+ struct reset_control *wcss_reset;
+ struct reset_control *wcss_q6_reset;
struct qcom_smem_state *state;
unsigned stop_bit;
@@ -181,6 +184,7 @@ enum {
MSS_MSM8916,
MSS_MSM8974,
MSS_MSM8996,
+ WCSS_IPQ8074,
};
static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
@@ -354,6 +358,21 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
return 0;
}
+static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
+{
+ struct q6v5 *qproc = rproc->priv;
+
+ return qcom_mdt_load_no_init(qproc->dev, fw, rproc->firmware,
+ 0, qproc->mba_region, qproc->mba_phys,
+ qproc->mba_size);
+}
+
+static const struct rproc_fw_ops q6v5_wcss_fw_ops = {
+ .find_rsc_table = q6v5_find_rsc_table,
+ .load = q6v5_wcss_load,
+ .get_boot_addr = rproc_elf_get_boot_addr,
+};
+
static const struct rproc_fw_ops q6v5_fw_ops = {
.find_rsc_table = q6v5_find_rsc_table,
.load = q6v5_load,
@@ -1057,6 +1076,26 @@ static int q6v5_init_clocks(struct device *dev, struct clk **clks,
return i;
}
+static int q6v5_wcss_init_reset(struct q6v5 *qproc)
+{
+ qproc->wcss_aon_reset = devm_reset_control_get(qproc->dev,
+ "wcss_aon_reset");
+ if (IS_ERR(qproc->wcss_aon_reset))
+ return PTR_ERR(qproc->wcss_aon_reset);
+
+ qproc->wcss_reset = devm_reset_control_get(qproc->dev,
+ "wcss_reset");
+ if (IS_ERR(qproc->wcss_reset))
+ return PTR_ERR(qproc->wcss_reset);
+
+ qproc->wcss_q6_reset = devm_reset_control_get(qproc->dev,
+ "wcss_q6_reset");
+ if (IS_ERR(qproc->wcss_q6_reset))
+ return PTR_ERR(qproc->wcss_q6_reset);
+
+ return 0;
+}
+
static int q6v5_init_reset(struct q6v5 *qproc)
{
qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
@@ -1116,6 +1155,9 @@ static int q6v5_alloc_memory_region(struct q6v5 *qproc)
return -EBUSY;
}
+ if (qproc->version == WCSS_IPQ8074)
+ return 0;
+
child = of_get_child_by_name(qproc->dev->of_node, "mpss");
node = of_parse_phandle(child, "memory-region", 0);
ret = of_address_to_resource(node, 0, &r);
@@ -1159,6 +1201,7 @@ static int q6v5_probe(struct platform_device *pdev)
qproc = (struct q6v5 *)rproc->priv;
qproc->dev = &pdev->dev;
qproc->rproc = rproc;
+ qproc->version = desc->version;
platform_set_drvdata(pdev, qproc);
init_completion(&qproc->start_done);
@@ -1208,7 +1251,6 @@ static int q6v5_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
- qproc->version = desc->version;
qproc->need_mem_protection = desc->need_mem_protection;
ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
if (ret < 0)
@@ -1358,11 +1400,20 @@ static int q6v5_remove(struct platform_device *pdev)
.ops = &q6v5_ops,
};
+static const struct rproc_hexagon_res ipq8074_wcss = {
+ .hexagon_mba_image = "IPQ8074/q6_fw.mdt",
+ .need_mem_protection = false,
+ .version = WCSS_IPQ8074,
+ .init_reset = q6v5_wcss_init_reset,
+ .fw_ops = &q6v5_wcss_fw_ops,
+};
+
static const struct of_device_id q6v5_of_match[] = {
{ .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
+ { .compatible = "qcom,ipq8074-wcss-pil", .data = &ipq8074_wcss},
{ },
};
MODULE_DEVICE_TABLE(of, q6v5_of_match);
--
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^ permalink raw reply related
* [PATCH v5 6/6] remoteproc: qcom: Add q6v5-wcss rproc ops
From: Sricharan R @ 2017-11-14 10:53 UTC (permalink / raw)
To: bjorn.andersson, ohad, robh+dt, mark.rutland, andy.gross,
david.brown, linux-remoteproc, devicetree, linux-kernel,
linux-arm-msm, linux-soc
Cc: sricharan
In-Reply-To: <1510656794-3815-1-git-send-email-sricharan@codeaurora.org>
q6v5-wcss core's start function is mostly common
with the q6v5 of msm8996. So reuse that and add
the stop function.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 212 +++++++++++++++++++++++++++++++++++++
1 file changed, 212 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 3c401ff..1b560a6 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -104,6 +104,17 @@
#define QDSP6SS_XO_CBCR 0x0038
#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
+/* QDSP6v5-WCSS config/status registers */
+#define TCSR_GLOBAL_CFG0 0x0
+#define TCSR_GLOBAL_CFG1 0x4
+#define SSCAON_CONFIG 0x8
+#define SSCAON_STATUS 0xc
+#define QDSP6SS_BHS_STATUS 0x78
+#define QDSP6SS_RST_EVB 0x10
+
+#define BHS_EN_REST_ACK BIT(0)
+#define SSCAON_ENABLE BIT(13)
+
struct reg_info {
struct regulator *reg;
int uV;
@@ -771,6 +782,61 @@ static int q6v5_mpss_load(struct q6v5 *qproc)
return ret < 0 ? ret : 0;
}
+static int q6v5_wcss_start(struct rproc *rproc)
+{
+ struct q6v5 *qproc = rproc->priv;
+ int ret = 0;
+
+ ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
+ qproc->active_clk_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable clocks\n");
+ return ret;
+ }
+
+ /* Release Q6 and WCSS reset */
+ ret = reset_control_deassert(qproc->wcss_reset);
+ if (ret)
+ dev_err(qproc->dev, "wcss_reset failed\n");
+
+ ret = reset_control_deassert(qproc->wcss_q6_reset);
+ if (ret)
+ dev_err(qproc->dev, "wcss_q6_reset failed\n");
+
+ /* Lithium configuration - clock gating and bus arbitration */
+ ret = regmap_update_bits(qproc->halt_map,
+ qproc->halt_nc + TCSR_GLOBAL_CFG0,
+ 0x1F, 0x14);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(qproc->halt_map,
+ qproc->halt_nc + TCSR_GLOBAL_CFG1,
+ 1, 0);
+ if (ret)
+ return ret;
+
+ /* Write bootaddr to EVB so that Q6WCSS will jump there after reset */
+ writel(rproc->bootaddr >> 4, qproc->reg_base + QDSP6SS_RST_EVB);
+
+ ret = q6v5_reset(qproc);
+ if (ret)
+ return ret;
+
+ q6v5_reset_rest(qproc);
+
+ ret = wait_for_completion_timeout(&qproc->start_done,
+ msecs_to_jiffies(5000));
+ if (ret == 0) {
+ dev_err(qproc->dev, "start timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ qproc->running = true;
+
+ return 0;
+}
+
static int q6v5_start(struct rproc *rproc)
{
struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
@@ -894,6 +960,146 @@ static int q6v5_start(struct rproc *rproc)
return ret;
}
+static int q6v5_wcss_powerdown(struct q6v5 *qproc)
+{
+ unsigned int val = 0;
+ int ret;
+
+ /* 1 - Assert WCSS/Q6 HALTREQ */
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
+
+ /* 2 - Enable WCSSAON_CONFIG */
+ val = readl(qproc->rmb_base + SSCAON_CONFIG);
+ val |= SSCAON_ENABLE;
+ writel(val, qproc->rmb_base + SSCAON_CONFIG);
+
+ /* 3 - Set SSCAON_CONFIG */
+ val |= BIT(15);
+ val &= ~BIT(16);
+ val &= ~BIT(17);
+ val &= ~BIT(18);
+ writel(val, qproc->rmb_base + SSCAON_CONFIG);
+
+ /* 4 - SSCAON_CONFIG 1 */
+ val |= BIT(1);
+ writel(val, qproc->rmb_base + SSCAON_CONFIG);
+
+ /* 5 - wait for SSCAON_STATUS */
+ ret = readl_poll_timeout(qproc->rmb_base + SSCAON_STATUS,
+ val, (val & 0xffff) == 0x400, 1000,
+ HALT_CHECK_MAX_LOOPS);
+ if (ret) {
+ dev_err(qproc->dev,
+ "can't get SSCAON_STATUS rc:%d)\n", ret);
+ }
+
+ /* 6 - De-assert WCSS_AON reset */
+ reset_control_assert(qproc->wcss_aon_reset);
+
+ /* 7 - Disable WCSSAON_CONFIG 13 */
+ val = readl(qproc->rmb_base + SSCAON_CONFIG);
+ val &= ~SSCAON_ENABLE;
+ writel(val, qproc->rmb_base + SSCAON_CONFIG);
+
+ /* 8 - De-assert WCSS/Q6 HALTREQ */
+ reset_control_assert(qproc->wcss_reset);
+
+ return ret;
+}
+
+static int q6v5_q6_powerdown(struct q6v5 *qproc)
+{
+ int i = 0, ret;
+ unsigned int val = 0;
+
+ /* 1 - Halt Q6 bus interface */
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
+
+ /* 2 - Disable Q6 Core clock */
+ val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
+ val &= ~Q6SS_CLK_ENABLE;
+ writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
+
+ /* 3 - Clamp I/O */
+ val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ val |= Q6SS_CLAMP_IO;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+ /* 4 - Clamp WL */
+ val |= QDSS_BHS_ON;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+ /* 5 - Clear Erase standby */
+ val &= ~Q6SS_L2DATA_STBY_N;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+ /* 6 - Clear Sleep RTN */
+ val &= ~Q6SS_SLP_RET_N;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+ /* 7 - turn off QDSP6 memory foot/head switch one bank at a time */
+ for (i = 0; i < 20; i++) {
+ val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
+ val &= ~BIT(i);
+ writel(val, qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
+ mdelay(1);
+ }
+ /* 8 - Assert QMC memory RTN */
+ val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ val |= QDSP6v56_CLAMP_QMC_MEM;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+ /* 9 - Turn off BHS */
+ val &= ~QDSP6v56_BHS_ON;
+ writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+ udelay(1);
+ /* 10 - Wait till BHS Reset is done */
+ ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BHS_STATUS,
+ val, !(val & BHS_EN_REST_ACK), 1000,
+ HALT_CHECK_MAX_LOOPS);
+ if (ret) {
+ dev_err(qproc->dev,
+ "BHS_STATUS not OFF (rc:%d)\n", ret);
+ }
+
+ /* 11 - Enable Q6 Block reset */
+ reset_control_assert(qproc->wcss_q6_reset);
+
+ return 0;
+}
+
+static int q6v5_wcss_stop(struct rproc *rproc)
+{
+ struct q6v5 *qproc = rproc->priv;
+ int ret = 0;
+
+ qproc->running = false;
+
+ /* WCSS powerdown */
+ qcom_smem_state_update_bits(qproc->state, BIT(qproc->stop_bit),
+ BIT(qproc->stop_bit));
+
+ ret = wait_for_completion_timeout(&qproc->stop_done,
+ msecs_to_jiffies(5000));
+ if (ret == 0) {
+ dev_err(qproc->dev, "timed out on wait\n");
+ return -ETIMEDOUT;
+ }
+
+ qcom_smem_state_update_bits(qproc->state, BIT(qproc->stop_bit), 0);
+
+ ret = q6v5_wcss_powerdown(qproc);
+ if (ret)
+ return ret;
+
+ /* Q6 Power down */
+ ret = q6v5_q6_powerdown(qproc);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int q6v5_stop(struct rproc *rproc)
{
struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
@@ -956,6 +1162,11 @@ static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
.da_to_va = q6v5_da_to_va,
};
+static const struct rproc_ops q6v5_wcss_ops = {
+ .start = q6v5_wcss_start,
+ .stop = q6v5_wcss_stop,
+};
+
static irqreturn_t q6v5_wdog_interrupt(int irq, void *dev)
{
struct q6v5 *qproc = dev;
@@ -1406,6 +1617,7 @@ static int q6v5_remove(struct platform_device *pdev)
.version = WCSS_IPQ8074,
.init_reset = q6v5_wcss_init_reset,
.fw_ops = &q6v5_wcss_fw_ops,
+ .ops = &q6v5_wcss_ops,
};
static const struct of_device_id q6v5_of_match[] = {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* Re: [PATCH v5 5/6] remoteproc: qcom: Add support for q6v5-wcss pil
From: Sricharan R @ 2017-11-14 10:56 UTC (permalink / raw)
To: bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A,
ohad-Ix1uc/W3ht7QT0dZR+AlfA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, andy.gross-QSEj5FYQhm4dnm+yROfE0A,
david.brown-QSEj5FYQhm4dnm+yROfE0A,
linux-remoteproc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1510656794-3815-6-git-send-email-sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On 11/14/2017 4:23 PM, Sricharan R wrote:
> IPQ8074 has an integrated Hexagon dsp core q6v5 and a wireless lan
> (Lithium) IP. An mdt type single image format is used for the
> firmware. So the mdt_load function can be directly used to load
> the firmware. Also add the relevant resets required for this core.
>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Infact should have said,
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> (DT bindings)
Regards,
Sricharan
> Signed-off-by: Sricharan R <sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
> .../devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 ++-
> drivers/remoteproc/Kconfig | 1 +
> drivers/remoteproc/qcom_q6v5_pil.c | 53 +++++++++++++++++++++-
> 3 files changed, 59 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> index 00d3d58..d52d05e 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> @@ -11,6 +11,7 @@ on the Qualcomm Hexagon core.
> "qcom,msm8916-mss-pil",
> "qcom,msm8974-mss-pil"
> "qcom,msm8996-mss-pil"
> + "qcom,ipq8074-wcss-pil"
>
> - reg:
> Usage: required
> @@ -49,11 +50,15 @@ on the Qualcomm Hexagon core.
> Usage: required
> Value type: <phandle>
> Definition: reference to the reset-controller for the modem sub-system
> + reference to the list of 3 reset-controllers for the
> + wcss sub-system
>
> - reset-names:
> Usage: required
> Value type: <stringlist>
> - Definition: must be "mss_restart"
> + Definition: must be "mss_restart" for the modem sub-system
> + Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
> + for the wcss syb-system
>
> - cx-supply:
> - mss-supply:
> diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
> index bf04479..e7e9979 100644
> --- a/drivers/remoteproc/Kconfig
> +++ b/drivers/remoteproc/Kconfig
> @@ -113,6 +113,7 @@ config QCOM_Q6V5_PIL
> select MFD_SYSCON
> select QCOM_RPROC_COMMON
> select QCOM_SCM
> + select QCOM_MDT_LOADER
> help
> Say y here to support the Qualcomm Peripherial Image Loader for the
> Hexagon V5 based remote processors.
> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
> index 75ff02d..3c401ff 100644
> --- a/drivers/remoteproc/qcom_q6v5_pil.c
> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
> @@ -129,6 +129,9 @@ struct q6v5 {
> u32 halt_nc;
>
> struct reset_control *mss_restart;
> + struct reset_control *wcss_aon_reset;
> + struct reset_control *wcss_reset;
> + struct reset_control *wcss_q6_reset;
>
> struct qcom_smem_state *state;
> unsigned stop_bit;
> @@ -181,6 +184,7 @@ enum {
> MSS_MSM8916,
> MSS_MSM8974,
> MSS_MSM8996,
> + WCSS_IPQ8074,
> };
>
> static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
> @@ -354,6 +358,21 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
> return 0;
> }
>
> +static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
> +{
> + struct q6v5 *qproc = rproc->priv;
> +
> + return qcom_mdt_load_no_init(qproc->dev, fw, rproc->firmware,
> + 0, qproc->mba_region, qproc->mba_phys,
> + qproc->mba_size);
> +}
> +
> +static const struct rproc_fw_ops q6v5_wcss_fw_ops = {
> + .find_rsc_table = q6v5_find_rsc_table,
> + .load = q6v5_wcss_load,
> + .get_boot_addr = rproc_elf_get_boot_addr,
> +};
> +
> static const struct rproc_fw_ops q6v5_fw_ops = {
> .find_rsc_table = q6v5_find_rsc_table,
> .load = q6v5_load,
> @@ -1057,6 +1076,26 @@ static int q6v5_init_clocks(struct device *dev, struct clk **clks,
> return i;
> }
>
> +static int q6v5_wcss_init_reset(struct q6v5 *qproc)
> +{
> + qproc->wcss_aon_reset = devm_reset_control_get(qproc->dev,
> + "wcss_aon_reset");
> + if (IS_ERR(qproc->wcss_aon_reset))
> + return PTR_ERR(qproc->wcss_aon_reset);
> +
> + qproc->wcss_reset = devm_reset_control_get(qproc->dev,
> + "wcss_reset");
> + if (IS_ERR(qproc->wcss_reset))
> + return PTR_ERR(qproc->wcss_reset);
> +
> + qproc->wcss_q6_reset = devm_reset_control_get(qproc->dev,
> + "wcss_q6_reset");
> + if (IS_ERR(qproc->wcss_q6_reset))
> + return PTR_ERR(qproc->wcss_q6_reset);
> +
> + return 0;
> +}
> +
> static int q6v5_init_reset(struct q6v5 *qproc)
> {
> qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
> @@ -1116,6 +1155,9 @@ static int q6v5_alloc_memory_region(struct q6v5 *qproc)
> return -EBUSY;
> }
>
> + if (qproc->version == WCSS_IPQ8074)
> + return 0;
> +
> child = of_get_child_by_name(qproc->dev->of_node, "mpss");
> node = of_parse_phandle(child, "memory-region", 0);
> ret = of_address_to_resource(node, 0, &r);
> @@ -1159,6 +1201,7 @@ static int q6v5_probe(struct platform_device *pdev)
> qproc = (struct q6v5 *)rproc->priv;
> qproc->dev = &pdev->dev;
> qproc->rproc = rproc;
> + qproc->version = desc->version;
> platform_set_drvdata(pdev, qproc);
>
> init_completion(&qproc->start_done);
> @@ -1208,7 +1251,6 @@ static int q6v5_probe(struct platform_device *pdev)
> if (ret)
> goto free_rproc;
>
> - qproc->version = desc->version;
> qproc->need_mem_protection = desc->need_mem_protection;
> ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
> if (ret < 0)
> @@ -1358,11 +1400,20 @@ static int q6v5_remove(struct platform_device *pdev)
> .ops = &q6v5_ops,
> };
>
> +static const struct rproc_hexagon_res ipq8074_wcss = {
> + .hexagon_mba_image = "IPQ8074/q6_fw.mdt",
> + .need_mem_protection = false,
> + .version = WCSS_IPQ8074,
> + .init_reset = q6v5_wcss_init_reset,
> + .fw_ops = &q6v5_wcss_fw_ops,
> +};
> +
> static const struct of_device_id q6v5_of_match[] = {
> { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
> { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
> { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
> { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
> + { .compatible = "qcom,ipq8074-wcss-pil", .data = &ipq8074_wcss},
> { },
> };
> MODULE_DEVICE_TABLE(of, q6v5_of_match);
>
--
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^ permalink raw reply
* Re: [v11,1/4] drivers: jtag: Add JTAG core driver
From: gregkh @ 2017-11-14 11:10 UTC (permalink / raw)
To: Oleksandr Shamray
Cc: 'Chip Bilbrey', arnd@arndb.de,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
openbmc@lists.ozlabs.org, joel@jms.id.au, jiri@resnulli.us,
tklauser@distanz.ch, linux-serial@vger.kernel.org, mec@shout.net,
robh+dt@kernel.org, openocd-devel-owner@lists.sourceforge.net,
linux-api@vger.kernel.org, davem@davemloft.net
In-Reply-To: <DB6PR0501MB219753AC43515148F39CC2D0B1280@DB6PR0501MB2197.eurprd05.prod.outlook.com>
On Tue, Nov 14, 2017 at 10:34:49AM +0000, Oleksandr Shamray wrote:
> > -----Original Message-----
> > From: Chip Bilbrey [mailto:chip@bilbrey.org]
> > Sent: Monday, November 6, 2017 12:33 AM
> > To: Oleksandr Shamray <oleksandrs@mellanox.com>
> > Cc: gregkh@linuxfoundation.org; arnd@arndb.de; linux-
> > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > devicetree@vger.kernel.org; openbmc@lists.ozlabs.org; joel@jms.id.au;
> > jiri@resnulli.us; tklauser@distanz.ch; linux-serial@vger.kernel.org;
> > mec@shout.net; Vadim Pasternak <vadimp@mellanox.com>; system-sw-low-
> > level <system-sw-low-level@mellanox.com>; robh+dt@kernel.org; openocd-
> > devel-owner@lists.sourceforge.net; linux-api@vger.kernel.org;
> > davem@davemloft.net; mchehab@kernel.org; Jiri Pirko <jiri@mellanox.com>
> > Subject: Re: [v11,1/4] drivers: jtag: Add JTAG core driver
> >
> >
> > Oleksandr Shamray writes:
>
> [..]
>
> > I notice the single-open()-per-device lock was dropped by request in an earlier
> > revision of your patches, but multiple processes trying to drive a single JTAG
> > master could wreak serious havoc if transactions get interleaved. Would
> > something like an added JTAG_LOCKCHAIN/UNLOCKCHAIN
> > ioctl() for exclusive client access be reasonable to prevent this?
> >
>
> Yes, it dropped by recommendation of Greg KH <gregkh@linuxfoundation.org>.
I asked to drop it as you didn't even implement it to work correctly :)
> Greg, what you can suggest about it. May be better to add again single-open()-per-device lock with right locking way like:
>
> >if (mutex_lock_interruptible(&jtag->open_lock)) {
You would stall an open? Why not just return saying you can't do that?
Anyway, if you want to only have one access to the device at a time,
great, but do it in a way that works properly.
thanks,
greg k-h
^ permalink raw reply
* Re: [v11,1/4] drivers: jtag: Add JTAG core driver
From: Russell King - ARM Linux @ 2017-11-14 11:19 UTC (permalink / raw)
To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org
Cc: Oleksandr Shamray,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
jiri-rHqAuBHg3fBzbRFIqnYvSA@public.gmane.org,
'Chip Bilbrey', arnd-r2nGTMty4D4@public.gmane.org,
linux-api-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
openocd-devel-owner-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org,
mec-WqBc5aa1uDFeoWH0uzbU5w@public.gmane.org, Jiri Pirko,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org,
linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
tklauser-93Khv+1bN0NyDzI6CaY1VQ@public.gmane.org,
mchehab-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
In-Reply-To: <20171114111046.GA23820-U8xfFu+wG4EAvxtiuMwx3w@public.gmane.org>
On Tue, Nov 14, 2017 at 12:10:46PM +0100, gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org wrote:
> On Tue, Nov 14, 2017 at 10:34:49AM +0000, Oleksandr Shamray wrote:
> > Greg, what you can suggest about it. May be better to add again single-open()-per-device lock with right locking way like:
> >
> > >if (mutex_lock_interruptible(&jtag->open_lock)) {
>
> You would stall an open? Why not just return saying you can't do that?
Greg, I think you need to look at the code again.
>From the snippet in the email, this lock is not held while the device is
open, as you apparently think it is. It's a short-term lock that is
held to ensure atomic access to the jtag->opened member, so that two
concurrent opens are unable to operate lock-step, resulting in
jtag->opened becoming 2.
The open function snippet in the email drops the lock as soon as it has
incremented jtag->opened, or encounters an error.
It seems entirely sensible, rather than using an atomic_t counter, as
it means that other openers are held off until the current opener has
either succeeded in opening the device or failed to open it.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
* [PATCH 0/2] add support rk3126 vop support
From: Sandy Huang @ 2017-11-14 11:27 UTC (permalink / raw)
To: Mark Yao, David Airlie, Rob Herring, Mark Rutland, Heiko Stuebner
Cc: devicetree, dri-devel, linux-kernel, linux-rockchip,
linux-arm-kernel
The following patch add support RK3126 vop support, there is only one
VOP at RK3126, and the RK3126 VOP register layout is similar with RK3036,
so some feature can reuse with RK3036.
Sandy Huang (2):
dt-bindings: add document for rk3126-vop
drm/rockchip: vop: add rk3126 vop support
.../bindings/display/rockchip/rockchip-vop.txt | 1 +
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 30 ++++++++++++++++++++++
drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 6 +++++
3 files changed, 37 insertions(+)
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* [PATCH 1/2] dt-bindings: add document for rk3126-vop
From: Sandy Huang @ 2017-11-14 11:27 UTC (permalink / raw)
To: Mark Yao, David Airlie, Rob Herring, Mark Rutland, Heiko Stuebner
Cc: Sandy Huang, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1510658851-90160-1-git-send-email-hjc-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Sandy Huang <hjc-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
index 5d835d9..eeda359 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
@@ -7,6 +7,7 @@ buffer to an external LCD interface.
Required properties:
- compatible: value should be one of the following
"rockchip,rk3036-vop";
+ "rockchip,rk3126-vop";
"rockchip,rk3288-vop";
"rockchip,rk3368-vop";
"rockchip,rk3366-vop";
--
2.7.4
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^ permalink raw reply related
* Re: [v11,1/4] drivers: jtag: Add JTAG core driver
From: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r @ 2017-11-14 11:31 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Oleksandr Shamray,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
jiri-rHqAuBHg3fBzbRFIqnYvSA@public.gmane.org,
'Chip Bilbrey', arnd-r2nGTMty4D4@public.gmane.org,
linux-api-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
openocd-devel-owner-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org,
mec-WqBc5aa1uDFeoWH0uzbU5w@public.gmane.org, Jiri Pirko,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org,
linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
tklauser-93Khv+1bN0NyDzI6CaY1VQ@public.gmane.org,
mchehab-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
In-Reply-To: <20171114111916.GO12318-l+eeeJia6m9URfEZ8mYm6t73F7V6hmMc@public.gmane.org>
On Tue, Nov 14, 2017 at 11:19:16AM +0000, Russell King - ARM Linux wrote:
> On Tue, Nov 14, 2017 at 12:10:46PM +0100, gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org wrote:
> > On Tue, Nov 14, 2017 at 10:34:49AM +0000, Oleksandr Shamray wrote:
> > > Greg, what you can suggest about it. May be better to add again single-open()-per-device lock with right locking way like:
> > >
> > > >if (mutex_lock_interruptible(&jtag->open_lock)) {
> >
> > You would stall an open? Why not just return saying you can't do that?
>
> Greg, I think you need to look at the code again.
Heh, sorry, I probably got it wrong. I'll be glad to review it in a
real patch when needed, but not in the middle of the merge window :)
thanks,
greg k-h
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^ permalink raw reply
* [PATCH] arm: dts: ls1021a: Add label to USB controllers
From: Rasmus Villemoes @ 2017-11-14 12:39 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King
Cc: Rasmus Villemoes, Esben Haabendal,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
From: Esben Haabendal <eha-/iRVSOupHO4@public.gmane.org>
Add usb2 and usb3 labels to USB2 and USB3 controller device tree nodes,
for easier modification in board dts files.
Signed-off-by: Esben Haabendal <eha-/iRVSOupHO4@public.gmane.org>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes-rjjw5hvvQKZaa/9Udqfwiw@public.gmane.org>
---
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 9cdec545decc..50ad4dccb22b 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -675,7 +675,7 @@
};
};
- usb@8600000 {
+ usb2: usb@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
@@ -683,7 +683,7 @@
phy_type = "ulpi";
};
- usb3@3100000 {
+ usb3: usb3@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
--
2.7.4
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^ permalink raw reply related
* [PATCH v2 0/3] drm/omap: Support for dispc memory bandwidth limit
From: Peter Ujfalusi @ 2017-11-14 12:47 UTC (permalink / raw)
To: tomi.valkeinen-l0cyMroinI0,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw
Cc: airlied-cv59FeDIM0c, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA, daniel-/w4YWyX8dFk,
robh-DgEjT+Ai2ygdnm+yROfE0A
Hi,
Changes since v1:
- Use the crtc->mode_valid and not connector->mode_valid as the limit is really
posed by the 'crtc' (DISPC)
- Bandwidth calculation changed: do the calculation in place + extended comment
- looked for better place to document the max-memory-bandwidth, but
can not find any suitable document. Creating a new txt file for only one
property did not seemed feasable.
This series will add simple memory bandwidth limit support to reject modes
which, if used with one plane in full size would fail the limit.
Regards,
Peter
---
Peter Ujfalusi (3):
dt-bindings: display/ti: Add optional property to set memory bandwidth
limit
drm/omap: dss: Add support for reporting memory bandwidth limitation
drm/omap: Filter displays mode based on bandwidth limit
.../devicetree/bindings/display/ti/ti,dra7-dss.txt | 5 +++
.../bindings/display/ti/ti,omap2-dss.txt | 4 +++
.../bindings/display/ti/ti,omap3-dss.txt | 4 +++
.../bindings/display/ti/ti,omap4-dss.txt | 4 +++
.../bindings/display/ti/ti,omap5-dss.txt | 4 +++
drivers/gpu/drm/omapdrm/dss/dispc.c | 13 ++++++++
drivers/gpu/drm/omapdrm/dss/omapdss.h | 2 ++
drivers/gpu/drm/omapdrm/omap_crtc.c | 37 ++++++++++++++++++++++
drivers/gpu/drm/omapdrm/omap_drv.c | 5 +++
drivers/gpu/drm/omapdrm/omap_drv.h | 3 ++
10 files changed, 81 insertions(+)
--
Peter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply
* [PATCH v2 1/3] dt-bindings: display/ti: Add optional property to set memory bandwidth limit
From: Peter Ujfalusi @ 2017-11-14 12:47 UTC (permalink / raw)
To: tomi.valkeinen-l0cyMroinI0,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw
Cc: airlied-cv59FeDIM0c, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA, daniel-/w4YWyX8dFk,
robh-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <20171114124755.14277-1-peter.ujfalusi-l0cyMroinI0@public.gmane.org>
max-memory-bandwidth can be used to specify the maximum bandwidth dispc
can use when reading display data from main memory.
In some SoC (am437x for example) we have memory bandwidth limitation
which causes underflow in the display subsystem.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
---
Documentation/devicetree/bindings/display/ti/ti,dra7-dss.txt | 5 +++++
Documentation/devicetree/bindings/display/ti/ti,omap2-dss.txt | 4 ++++
Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt | 4 ++++
Documentation/devicetree/bindings/display/ti/ti,omap4-dss.txt | 4 ++++
Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt | 4 ++++
5 files changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/ti/ti,dra7-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,dra7-dss.txt
index c30f9ec189ed..91279f1060fe 100644
--- a/Documentation/devicetree/bindings/display/ti/ti,dra7-dss.txt
+++ b/Documentation/devicetree/bindings/display/ti/ti,dra7-dss.txt
@@ -47,6 +47,11 @@ Required properties:
- clocks: handle to fclk
- clock-names: "fck"
+Optional properties:
+- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
+ in bytes per second
+
+
HDMI
----
diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap2-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap2-dss.txt
index afcd5a86c6a4..ee867c4d1152 100644
--- a/Documentation/devicetree/bindings/display/ti/ti,omap2-dss.txt
+++ b/Documentation/devicetree/bindings/display/ti/ti,omap2-dss.txt
@@ -28,6 +28,10 @@ Required properties:
- ti,hwmods: "dss_dispc"
- interrupts: the DISPC interrupt
+Optional properties:
+- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
+ in bytes per second
+
RFBI
----
diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt
index dc66e1447c31..cd02516a40b6 100644
--- a/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt
+++ b/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt
@@ -37,6 +37,10 @@ Required properties:
- clocks: handle to fclk
- clock-names: "fck"
+Optional properties:
+- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
+ in bytes per second
+
RFBI
----
diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap4-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap4-dss.txt
index bc624db8888d..0f85f6b3a5a8 100644
--- a/Documentation/devicetree/bindings/display/ti/ti,omap4-dss.txt
+++ b/Documentation/devicetree/bindings/display/ti/ti,omap4-dss.txt
@@ -36,6 +36,10 @@ Required properties:
- clocks: handle to fclk
- clock-names: "fck"
+Optional properties:
+- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
+ in bytes per second
+
RFBI
----
diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt
index 118a486c47bb..20861218649f 100644
--- a/Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt
+++ b/Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt
@@ -36,6 +36,10 @@ Required properties:
- clocks: handle to fclk
- clock-names: "fck"
+Optional properties:
+- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
+ in bytes per second
+
RFBI
----
--
Peter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related
* [PATCH v2 2/3] drm/omap: dss: Add support for reporting memory bandwidth limitation
From: Peter Ujfalusi @ 2017-11-14 12:47 UTC (permalink / raw)
To: tomi.valkeinen-l0cyMroinI0,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw
Cc: airlied-cv59FeDIM0c, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA, daniel-/w4YWyX8dFk,
robh-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <20171114124755.14277-1-peter.ujfalusi-l0cyMroinI0@public.gmane.org>
The get_memory_bandwidth_limit() in dispc_ops can be used to query the
memory bandwidth limit of dispc by upper layers.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
---
drivers/gpu/drm/omapdrm/dss/dispc.c | 13 +++++++++++++
drivers/gpu/drm/omapdrm/dss/omapdss.h | 2 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 0f4fdb221498..90f9ad89af0d 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -4325,6 +4325,17 @@ static void dispc_free_irq(void *dev_id)
dispc.user_data = NULL;
}
+static u32 dispc_get_memory_bandwidth_limit(void)
+{
+ u32 limit = 0;
+
+ /* Optional maximum memory bandwidth */
+ of_property_read_u32(dispc.pdev->dev.of_node, "max-memory-bandwidth",
+ &limit);
+
+ return limit;
+}
+
/*
* Workaround for errata i734 in DSS dispc
* - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled
@@ -4497,6 +4508,8 @@ static const struct dispc_ops dispc_ops = {
.get_num_ovls = dispc_get_num_ovls,
.get_num_mgrs = dispc_get_num_mgrs,
+ .get_memory_bandwidth_limit = dispc_get_memory_bandwidth_limit,
+
.mgr_enable = dispc_mgr_enable,
.mgr_is_enabled = dispc_mgr_is_enabled,
.mgr_get_vsync_irq = dispc_mgr_get_vsync_irq,
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h
index 0bc6669d56f0..f30b3c09e1ba 100644
--- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
@@ -692,6 +692,8 @@ struct dispc_ops {
int (*get_num_ovls)(void);
int (*get_num_mgrs)(void);
+ u32 (*get_memory_bandwidth_limit)(void);
+
void (*mgr_enable)(enum omap_channel channel, bool enable);
bool (*mgr_is_enabled)(enum omap_channel channel);
u32 (*mgr_get_vsync_irq)(enum omap_channel channel);
--
Peter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related
* [PATCH v2 3/3] drm/omap: Filter displays mode based on bandwidth limit
From: Peter Ujfalusi @ 2017-11-14 12:47 UTC (permalink / raw)
To: tomi.valkeinen-l0cyMroinI0,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw
Cc: airlied-cv59FeDIM0c, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA, daniel-/w4YWyX8dFk,
robh-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <20171114124755.14277-1-peter.ujfalusi-l0cyMroinI0@public.gmane.org>
If we have memory bandwidth limit configured, reject the modes which would
require more bandwidth than the limit if it is used with one full
resolution plane (most common use case).
This filtering is not providing full protection as it is possible that
application would pick smaller crtc resolution with high resolution planes
and down scaling, or can enable more smaller planes where the sum of their
bandwidth need would be higher than the limit.
This patch only allows us to filter out modes which would need more
bandwidth if they were used with one full screen plane.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
---
drivers/gpu/drm/omapdrm/omap_crtc.c | 37 +++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/omapdrm/omap_drv.c | 5 +++++
drivers/gpu/drm/omapdrm/omap_drv.h | 3 +++
3 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c
index cc85c16cbc2a..ae2e16ed3874 100644
--- a/drivers/gpu/drm/omapdrm/omap_crtc.c
+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c
@@ -23,6 +23,7 @@
#include <drm/drm_crtc_helper.h>
#include <drm/drm_mode.h>
#include <drm/drm_plane_helper.h>
+#include <linux/math64.h>
#include "omap_drv.h"
@@ -400,6 +401,41 @@ static void omap_crtc_atomic_disable(struct drm_crtc *crtc,
drm_crtc_vblank_off(crtc);
}
+static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode)
+{
+ struct omap_drm_private *priv = crtc->dev->dev_private;
+
+ /* Check for bandwidth limit */
+ if (priv->max_bandwidth) {
+ /*
+ * Estimation for the bandwidth need of a given mode with one
+ * full screen plane:
+ * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal))
+ * ^^ Refresh rate ^^
+ *
+ * The interlaced mode is taken into account by using the
+ * pixelclock in the calculation.
+ *
+ * The equation is rearranged for 64bit arithmetic.
+ */
+ uint64_t bandwidth = mode->clock * 1000;
+ unsigned int bpp = 4;
+
+ bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp;
+ bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal);
+
+ /*
+ * Reject modes which would need more bandwidth if used with one
+ * full resolution plane (most common use case).
+ */
+ if (priv->max_bandwidth < bandwidth)
+ return MODE_BAD;
+ }
+
+ return MODE_OK;
+}
+
static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
@@ -621,6 +657,7 @@ static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
.atomic_flush = omap_crtc_atomic_flush,
.atomic_enable = omap_crtc_atomic_enable,
.atomic_disable = omap_crtc_atomic_disable,
+ .mode_valid = omap_crtc_mode_valid,
};
/* -----------------------------------------------------------------------------
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c
index 528cf5c25bec..58b4a0e149e0 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.c
+++ b/drivers/gpu/drm/omapdrm/omap_drv.c
@@ -701,6 +701,11 @@ static int pdev_probe(struct platform_device *pdev)
spin_lock_init(&priv->list_lock);
INIT_LIST_HEAD(&priv->obj_list);
+ /* Get memory bandwidth limits */
+ if (priv->dispc_ops->get_memory_bandwidth_limit)
+ priv->max_bandwidth =
+ priv->dispc_ops->get_memory_bandwidth_limit();
+
omap_gem_init(ddev);
ret = omap_modeset_init(ddev);
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h
index cccaae787a7c..d49715272080 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.h
+++ b/drivers/gpu/drm/omapdrm/omap_drv.h
@@ -86,6 +86,9 @@ struct omap_drm_private {
spinlock_t wait_lock; /* protects the wait_list */
struct list_head wait_list; /* list of omap_irq_wait */
uint32_t irq_mask; /* enabled irqs in addition to wait_list */
+
+ /* memory bandwidth limit if it is needed on the platform */
+ unsigned int max_bandwidth;
};
--
Peter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related
* Re: [PATCH 2/3] dt-bindings: iio: add Intersil isl76683 light sensor bindings
From: Christoph Fritz @ 2017-11-14 14:20 UTC (permalink / raw)
To: Rob Herring
Cc: Jonathan Cameron, Peter Meerwald-Stadler,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171110212604.bpbsgtw7zbk5qp2d@rob-hp-laptop>
Hi Rob
On Fri, 2017-11-10 at 15:26 -0600, Rob Herring wrote:
> On Tue, Nov 07, 2017 at 04:36:22PM +0100, Christoph Fritz wrote:
> > +Optional properties:
> > +
> > + - isil,external-resistor: integer in kOhm of external resistor R_ext.
> > + Valid values are from 1 to 1000.
> > + If not supplied, 100 kOhm will be assumed.
>
> Add an unit suffix as defined in property-units.txt.
Thanks, I'll use "isil,external-resistor-ohms" as defined in
property-units.txt.
What bothers me a bit is that there is no "-kilo-ohms" suffix but a
"-micro-ohms" which is pretty uncommon. Even the only use of suffix
"-micro-ohms" could have been expressed easily as "-ohms" while being
more readable:
qcom,external-resistor-micro-ohms = <10000>;
Due to stable dt-api I suppose this cannot be changed and/or extended
with "-kilo-ohms", right?
Thanks
-- Christoph
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: orange-pi-zero-plus2: fix sdcard detect
From: Maxime Ripard @ 2017-11-14 14:39 UTC (permalink / raw)
To: Sergey Matyukevich
Cc: Jagan Teki, Chen-Yu Tsai, Rob Herring, Mark Rutland, devicetree,
linux-arm-kernel
In-Reply-To: <20171113192411.kmohcthzickk4n5v-tVm4GcgtBpsfMUw/CLfKLg@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1946 bytes --]
Hi Sergey,
On Mon, Nov 13, 2017 at 10:24:11PM +0300, Sergey Matyukevich wrote:
> Hello Maxime,
>
> On Wed, Nov 08, 2017 at 04:55:32PM +0530, Jagan Teki wrote:
> > On Wed, Nov 8, 2017 at 1:42 AM, Sergey Matyukevich <geomatsi-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> > > Hi,
> > >
> > >> >>> > Did you try to boot from sdcard ? I am not able to boot my board from
> > >> >>> > sd-card without this change. As I mentioned earlier in my email
> > >> >>> > to buildroot mailing list, with mmc debug enabled I see that mmc
> > >> >>> > tries to init sd-card when I remove it from the slot.
> > >> >>> >
> > >> >>> > Maybe there is a minor differences between h/w versions or batches ?
> > >> >>> > What is you board version ? I tested on board v1.0.
> > >> >>>
> > >> >>> Looking at the schematics, it definitely looks like it's active low.
> > >> >>
> > >> >> Is it ok to merge it then ? Or using 'cd-inverted' property
> > >> >> is the preferable option ?
> > >> >
> > >> > W/o any change mainline works unstable for me, it wasn't booting
> > >> > at-all[1] did you find the same?
> > >> >
> > >> > Even tried with active LOW and cd-inverted.
> > >> >
> > >> > [1] https://paste.ubuntu.com/25909064/
> > >>
> > >> Look like something broken for H5 and A64 between v4.14-rc8 to latest
> > >
> > > Both 4.13.7 and 4.14-rc8 (synched today) kernels worked fine for me.
> > > DTS behavior is all the same:
> >
> > I've tried fresh sync [2] but still see the issue, can you check the
> > Image size of log(suspecting on that area)
>
> Do you plan to accept this patch as well ? Or you would prefer to wait
> for the confirmation from Jagan as well ?
I'm happy with the patch, but I was under the impression that the
discussion had not settled yet. If it did, then yeah I'll merge it :)
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply
* [PATCH] arm: dts: ls1021a: Specify interrupt-affinity for pmu node
From: Rasmus Villemoes @ 2017-11-14 15:09 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King
Cc: Esben Haabendal, devicetree, linux-kernel, linux-arm-kernel,
Rasmus Villemoes
From: Esben Haabendal <eha@deif.com>
This avoids the warning
hw perfevents: no interrupt-affinity property for /pmu, guessing.
Signed-off-by: Esben Haabendal <eha@deif.com>
[RV: adapt commit log to the warning emitted in current mainline]
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
---
arch/arm/boot/dts/ls1021a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 9319e1f..d62af07 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -106,6 +106,7 @@
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
};
soc {
--
2.7.4
^ permalink raw reply related
* [GIT PULL] DeviceTree updates for 4.15
From: Rob Herring @ 2017-11-14 16:00 UTC (permalink / raw)
To: Linus Torvalds
Cc: Frank Rowand, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Hi Linus,
Please pull DT updates for 4.15. A bigger diffstat than usual with the
kbuild changes and a tree wide fix in the binding documentation.
There's some trivial conflicts in dts makefiles with SPDX tags in your
current tree and there will be a couple more with arm-soc.
Rob
The following changes since commit 2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e:
Linux 4.14-rc1 (2017-09-16 15:47:51 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
tags/devicetree-for-4.15
for you to fetch changes up to aa25e446ce76c37bfd75ac06598c316af94e9a26:
dt-bindings: usb: add #phy-cells to usb-nop-xceiv (2017-11-13 16:50:01 -0600)
----------------------------------------------------------------
DeviceTree for 4.15:
- kbuild cleanups and improvements for dtbs
- Code clean-up of overlay code and fixing for some long standing memory
leak and race condition in applying overlays
- Improvements to DT memory usage making sysfs/kobjects optional and
skipping unflattening of disabled nodes. This is part of kernel
tinification efforts.
- Final piece of removing storing the full path for every DT node. The
prerequisite conversion of printk's to use device_node format
specifier happened in 4.14.
- Sync with current upstream dtc. This brings additional checks to dtb
compiling.
- Binding doc tree wide removal of leading 0s from examples
- RTC binding documentation adding missing devices and some
consolidation of duplicated bindings
- Vendor prefix documentation for nutsboard, Silicon Storage Technology,
shimafuji, Tecon Microprocessor Technologies, DH electronics GmbH,
Opal Kelly, and Next Thing
----------------------------------------------------------------
Alexandre Belloni (6):
dt-bindings: trivial: Add RTCs
dt-bindings: rtc: add stericsson,coh901331 bindings
dt-bindings: rtc: Add sirf,prima2-sysrtc bindings
dt-bindings: rtc: DS1307 and compatibles are not trivial
dt-bindings: rtc: Add bindings for m41t80 and compatibles
dt-bindings: rtc: merge ds1339 in ds1307 documentation
Dmitry Dunaev (1):
Add Tecon Microprocessor Technologies, LLC vendor prefix
Fabrizio Castro (1):
of: add vendor prefix for Silicon Storage Technology Inc.
Frank Rowand (14):
of: overlay.c: Remove comments that state the obvious, to reduce clutter
of: overlay.c: Convert comparisons to zero or NULL to logical expressions
of: overlay: rename identifiers to more reflect what they do
of: overlay: rename identifiers in dup_and_fixup_symbol_prop()
of: overlay: minor restructuring
of: overlay: detect cases where device tree may become corrupt
of: overlay: expand check of whether overlay changeset can be removed
of: overlay: loosen overly strict phandle clash check
of: overlay: avoid race condition between applying multiple overlays
of: overlay: simplify applying symbols from an overlay
of: overlay: remove a dependency on device node full_name
of: overlay: remove unneeded check for NULL kbasename()
of: overlay: pr_err from return NOTIFY_OK to overlay apply/remove
of: overlay: make pr_err() string unique
Geert Uytterhoeven (2):
v4l: vsp1: Use generic node name
dt-bindings: iommu: ipmmu-vmsa: Use generic node name
Lixin Wang (2):
of: overlay: fix memory leak related to duplicated property
of: dynamic: fix memory leak related to properties of __of_node_dup
Marco Franchi (1):
dt-bindings: Remove leading zeros from bindings notation
Marek Vasut (1):
devicetree: Add vendor-prefix for DH electronics GmbH
Martin Blumenstingl (1):
dt-bindings: add vendor prefix for Next Thing Co.
Masahiro Yamada (5):
.gitignore: sort normal pattern rules alphabetically
.gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore
kbuild: clean up *.dtb and *.dtb.S patterns from top-level Makefile
MIPS: dts: remove bogus bcm96358nb4ser.dtb from dtb-y entry
kbuild: handle dtb-y and CONFIG_OF_ALL_DTBS natively in Makefile.lib
Rob Herring (16):
powerpc: pseries: only store the device node basename in full_name
of/fdt: only store the device node basename in full_name
Merge branch 'dt-printf-v2' into HEAD
scripts/dtc: add fdt_overlay.c and fdt_addresses.c to sync script
scripts/dtc: Update to upstream version v1.4.5-3-gb1a60033c110
of: fix missing kobject init for !SYSFS && OF_DYNAMIC config
of: remove struct property.unique_id for FDT
of: make struct property _flags field configurable
of: move kobj_to_device_node() into dynamic.c
of: wrap accesses to device_node kobject
of: make kobject and bin_attribute support configurable
of/fdt: add of_fdt_device_is_available function
of/fdt: skip unflattening of disabled nodes
scripts/dtc: Update to upstream version v1.4.5-6-gc1e55a5513e9
Merge branch 'dt/kbuild' into dt/next
dt-bindings: usb: add #phy-cells to usb-nop-xceiv
Stephen Boyd (4):
of/resolver: Simplify to be32_add_cpu()
of/resolver: Replace kmalloc + memcpy with kmemdup()
of/fdt: Document detached argument to __unflatten_device_tree()
of: unittest: Remove redundant OF_DETACHED flag setting
Tom McLeod (1):
dt-bindings: Add vendor prefix for Opal Kelly Inc
Vladimir Barinov (1):
dt: Add vendor prefix 'shimafuji'
YuanCheng Cheng (1):
dt-bindings: vendor-prefixes: Add nutsboard
.gitignore | 44 +-
.../devicetree/bindings/arm/samsung/pmu.txt | 2 +-
.../bindings/arm/samsung/samsung-boards.txt | 2 +-
Documentation/devicetree/bindings/arm/sp810.txt | 2 +-
.../devicetree/bindings/arm/vexpress-sysreg.txt | 2 +-
.../devicetree/bindings/ata/ahci-platform.txt | 2 +-
Documentation/devicetree/bindings/ata/imx-sata.txt | 2 +-
Documentation/devicetree/bindings/bus/imx-weim.txt | 2 +-
.../devicetree/bindings/bus/sunxi-rsb.txt | 2 +-
.../devicetree/bindings/clock/arm-syscon-icst.txt | 2 +-
.../devicetree/bindings/clock/clk-exynos-audss.txt | 2 +-
.../bindings/clock/clk-s5pv210-audss.txt | 2 +-
.../bindings/clock/dove-divider-clock.txt | 2 +-
.../devicetree/bindings/clock/imx1-clock.txt | 4 +-
.../devicetree/bindings/clock/imx6q-clock.txt | 4 +-
.../devicetree/bindings/clock/maxim,max77686.txt | 4 +-
.../devicetree/bindings/clock/st/st,clkgen.txt | 2 +-
.../devicetree/bindings/clock/sunxi-ccu.txt | 4 +-
Documentation/devicetree/bindings/clock/sunxi.txt | 16 +-
.../devicetree/bindings/clock/ti,cdce706.txt | 2 +-
.../devicetree/bindings/crypto/sun4i-ss.txt | 2 +-
.../bindings/display/etnaviv/etnaviv-drm.txt | 2 +-
.../devicetree/bindings/display/imx/hdmi.txt | 4 +-
.../bindings/display/simple-framebuffer.txt | 2 +-
.../bindings/display/sunxi/sun4i-drm.txt | 4 +-
.../devicetree/bindings/dma/sun4i-dma.txt | 4 +-
.../devicetree/bindings/dma/sun6i-dma.txt | 2 +-
Documentation/devicetree/bindings/dma/ti-edma.txt | 6 +-
Documentation/devicetree/bindings/dma/zxdma.txt | 2 +-
.../bindings/firmware/nvidia,tegra186-bpmp.txt | 2 +-
.../devicetree/bindings/gpio/gpio-dsp-keystone.txt | 2 +-
.../devicetree/bindings/gpio/gpio-tz1090-pdc.txt | 2 +-
.../devicetree/bindings/gpio/gpio-tz1090.txt | 2 +-
.../devicetree/bindings/i2c/i2c-axxia.txt | 2 +-
.../devicetree/bindings/i2c/i2c-sunxi-p2wi.txt | 2 +-
.../bindings/iio/magnetometer/ak8974.txt | 2 +-
.../bindings/iio/magnetometer/ak8975.txt | 2 +-
.../devicetree/bindings/input/sun4i-lradc-keys.txt | 2 +-
.../bindings/input/touchscreen/egalax-ts.txt | 2 +-
.../bindings/input/touchscreen/imx6ul_tsc.txt | 2 +-
.../interrupt-controller/allwinner,sunxi-nmi.txt | 2 +-
.../interrupt-controller/ti,keystone-irq.txt | 2 +-
.../devicetree/bindings/iommu/qcom,iommu.txt | 2 +-
.../bindings/iommu/renesas,ipmmu-vmsa.txt | 2 +-
.../devicetree/bindings/leds/register-bit-led.txt | 16 +-
.../bindings/mailbox/ti,message-manager.txt | 2 +-
Documentation/devicetree/bindings/marvell.txt | 4 +-
.../devicetree/bindings/media/i2c/tc358743.txt | 2 +-
.../devicetree/bindings/media/img-ir-rev1.txt | 2 +-
.../devicetree/bindings/media/renesas,vsp1.txt | 2 +-
.../devicetree/bindings/media/stih-cec.txt | 2 +-
.../bindings/media/stih407-c8sectpfe.txt | 2 +-
.../devicetree/bindings/media/sunxi-ir.txt | 2 +-
Documentation/devicetree/bindings/mfd/max77686.txt | 2 +-
Documentation/devicetree/bindings/mfd/max77802.txt | 2 +-
Documentation/devicetree/bindings/mfd/mfd.txt | 2 +-
.../devicetree/bindings/mfd/sun4i-gpadc.txt | 4 +-
.../devicetree/bindings/mfd/sun6i-prcm.txt | 2 +-
Documentation/devicetree/bindings/mfd/syscon.txt | 2 +-
Documentation/devicetree/bindings/mmc/mmc.txt | 2 +-
Documentation/devicetree/bindings/mmc/sdhci-st.txt | 4 +-
.../devicetree/bindings/mmc/sunxi-mmc.txt | 4 +-
.../devicetree/bindings/mtd/sunxi-nand.txt | 2 +-
.../bindings/net/allwinner,sun4i-emac.txt | 2 +-
.../bindings/net/allwinner,sun4i-mdio.txt | 4 +-
.../bindings/net/allwinner,sun7i-a20-gmac.txt | 2 +-
.../devicetree/bindings/net/brcm,bcmgenet.txt | 2 +-
.../devicetree/bindings/net/can/m_can.txt | 2 +-
.../devicetree/bindings/net/can/sun4i_can.txt | 4 +-
.../bindings/net/wireless/brcm,bcm43xx-fmac.txt | 2 +-
.../bindings/nvmem/allwinner,sunxi-sid.txt | 4 +-
.../devicetree/bindings/nvmem/brcm,ocotp.txt | 2 +-
.../devicetree/bindings/nvmem/imx-ocotp.txt | 2 +-
Documentation/devicetree/bindings/nvmem/nvmem.txt | 2 +-
Documentation/devicetree/bindings/nvmem/qfprom.txt | 2 +-
.../bindings/pci/nvidia,tegra20-pcie.txt | 12 +-
.../bindings/phy/brcm,cygnus-pcie-phy.txt | 2 +-
.../devicetree/bindings/phy/mxs-usb-phy.txt | 2 +-
.../devicetree/bindings/phy/sun9i-usb-phy.txt | 2 +-
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +-
.../bindings/pinctrl/fsl,imx-pinctrl.txt | 4 +-
.../bindings/pinctrl/img,tz1090-pdc-pinctrl.txt | 4 +-
.../bindings/pinctrl/img,tz1090-pinctrl.txt | 4 +-
.../pinctrl/nvidia,tegra124-xusb-padctl.txt | 2 +-
.../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 2 +-
.../devicetree/bindings/pinctrl/pinctrl-st.txt | 2 +-
.../bindings/pinctrl/qcom,msm8996-pinctrl.txt | 2 +-
.../devicetree/bindings/power/fsl,imx-gpc.txt | 4 +-
.../bindings/power/reset/imx-snvs-poweroff.txt | 2 +-
.../bindings/power/reset/keystone-reset.txt | 4 +-
.../bindings/powerpc/fsl/mcu-mpc8349emitx.txt | 2 +-
.../devicetree/bindings/pwm/pwm-sun4i.txt | 2 +-
.../devicetree/bindings/regulator/max77686.txt | 2 +-
.../devicetree/bindings/regulator/max77802.txt | 2 +-
.../bindings/reset/allwinner,sunxi-clock-reset.txt | 2 +-
.../devicetree/bindings/reset/fsl,imx-src.txt | 6 +-
.../devicetree/bindings/reset/ti-syscon-reset.txt | 2 +-
.../devicetree/bindings/rtc/dallas,ds1339.txt | 18 -
.../devicetree/bindings/rtc/rtc-ds1307.txt | 44 +
.../devicetree/bindings/rtc/rtc-m41t80.txt | 31 +
.../devicetree/bindings/rtc/sirf,prima2-sysrtc.txt | 13 +
.../bindings/rtc/stericsson,coh901331.txt | 17 +
.../devicetree/bindings/rtc/sun6i-rtc.txt | 2 +-
.../devicetree/bindings/rtc/sunxi-rtc.txt | 2 +-
.../bindings/soc/fsl/cpm_qe/qe/par_io.txt | 2 +-
.../bindings/soc/fsl/cpm_qe/qe/pincfg.txt | 2 +-
.../devicetree/bindings/soc/ti/sci-pm-domain.txt | 2 +-
.../devicetree/bindings/sound/cdns,xtfpga-i2s.txt | 2 +-
.../devicetree/bindings/sound/fsl,asrc.txt | 2 +-
.../devicetree/bindings/sound/fsl,esai.txt | 2 +-
.../devicetree/bindings/sound/fsl,spdif.txt | 2 +-
.../devicetree/bindings/sound/imx-audmux.txt | 2 +-
.../devicetree/bindings/sound/samsung-i2s.txt | 2 +-
.../devicetree/bindings/sound/sun4i-codec.txt | 4 +-
.../devicetree/bindings/sound/sun4i-i2s.txt | 2 +-
.../devicetree/bindings/sound/sun8i-a33-codec.txt | 2 +-
.../bindings/sound/sun8i-codec-analog.txt | 2 +-
.../bindings/sound/sunxi,sun4i-spdif.txt | 2 +-
.../devicetree/bindings/sound/zte,zx-spdif.txt | 2 +-
.../devicetree/bindings/spi/spi-sun4i.txt | 2 +-
.../devicetree/bindings/spi/spi-sun6i.txt | 4 +-
.../devicetree/bindings/sram/samsung-sram.txt | 2 +-
.../devicetree/bindings/sram/sunxi-sram.txt | 4 +-
.../bindings/timer/allwinner,sun5i-a13-hstimer.txt | 2 +-
.../devicetree/bindings/trivial-devices.txt | 13 +-
.../bindings/usb/allwinner,sun4i-a10-musb.txt | 2 +-
.../devicetree/bindings/usb/am33xx-usb.txt | 2 +-
.../devicetree/bindings/usb/atmel-usb.txt | 4 +-
.../devicetree/bindings/usb/ohci-da8xx.txt | 2 +-
Documentation/devicetree/bindings/usb/usb-ehci.txt | 2 +-
.../devicetree/bindings/usb/usb-nop-xceiv.txt | 2 +
Documentation/devicetree/bindings/usb/usb-ohci.txt | 2 +-
Documentation/devicetree/bindings/usb/usb3503.txt | 2 +-
.../devicetree/bindings/usb/usbmisc-imx.txt | 2 +-
.../devicetree/bindings/vendor-prefixes.txt | 7 +
.../devicetree/bindings/watchdog/mtk-wdt.txt | 2 +-
.../devicetree/bindings/watchdog/sunxi-wdt.txt | 2 +-
Documentation/devicetree/overlay-notes.txt | 12 +-
Documentation/kbuild/makefiles.txt | 1 -
Makefile | 2 +-
arch/arc/boot/.gitignore | 1 -
arch/arc/boot/dts/Makefile | 8 +-
arch/arm/boot/.gitignore | 1 -
arch/arm/boot/dts/Makefile | 6 -
arch/arm64/boot/dts/.gitignore | 1 -
arch/arm64/boot/dts/Makefile | 58 +-
arch/arm64/boot/dts/actions/Makefile | 4 -
arch/arm64/boot/dts/al/Makefile | 4 -
arch/arm64/boot/dts/allwinner/Makefile | 4 -
arch/arm64/boot/dts/altera/Makefile | 4 -
arch/arm64/boot/dts/amd/Makefile | 4 -
arch/arm64/boot/dts/amlogic/Makefile | 4 -
arch/arm64/boot/dts/apm/Makefile | 4 -
arch/arm64/boot/dts/arm/Makefile | 4 -
arch/arm64/boot/dts/broadcom/Makefile | 7 +-
arch/arm64/boot/dts/broadcom/northstar2/Makefile | 4 -
arch/arm64/boot/dts/broadcom/stingray/Makefile | 4 -
arch/arm64/boot/dts/cavium/Makefile | 4 -
arch/arm64/boot/dts/exynos/Makefile | 4 -
arch/arm64/boot/dts/freescale/Makefile | 4 -
arch/arm64/boot/dts/hisilicon/Makefile | 4 -
arch/arm64/boot/dts/lg/Makefile | 4 -
arch/arm64/boot/dts/marvell/Makefile | 4 -
arch/arm64/boot/dts/mediatek/Makefile | 4 -
arch/arm64/boot/dts/nvidia/Makefile | 3 -
arch/arm64/boot/dts/qcom/Makefile | 4 -
arch/arm64/boot/dts/realtek/Makefile | 4 -
arch/arm64/boot/dts/renesas/Makefile | 3 -
arch/arm64/boot/dts/rockchip/Makefile | 4 -
arch/arm64/boot/dts/socionext/Makefile | 3 -
arch/arm64/boot/dts/sprd/Makefile | 4 -
arch/arm64/boot/dts/xilinx/Makefile | 4 -
arch/arm64/boot/dts/zte/Makefile | 4 -
arch/c6x/boot/dts/Makefile | 2 -
arch/cris/boot/dts/Makefile | 2 -
arch/h8300/boot/dts/Makefile | 6 -
arch/metag/boot/.gitignore | 1 -
arch/metag/boot/dts/Makefile | 6 -
arch/microblaze/boot/.gitignore | 1 -
arch/microblaze/boot/Makefile | 2 +-
arch/mips/boot/.gitignore | 1 -
arch/mips/boot/dts/Makefile | 33 +-
arch/mips/boot/dts/brcm/Makefile | 4 -
arch/mips/boot/dts/cavium-octeon/Makefile | 3 -
arch/mips/boot/dts/img/Makefile | 3 -
arch/mips/boot/dts/ingenic/Makefile | 3 -
arch/mips/boot/dts/lantiq/Makefile | 3 -
arch/mips/boot/dts/mti/Makefile | 3 -
arch/mips/boot/dts/netlogic/Makefile | 3 -
arch/mips/boot/dts/ni/Makefile | 3 -
arch/mips/boot/dts/pic32/Makefile | 3 -
arch/mips/boot/dts/qca/Makefile | 3 -
arch/mips/boot/dts/ralink/Makefile | 3 -
arch/mips/boot/dts/xilfpga/Makefile | 3 -
arch/nios2/boot/.gitignore | 1 -
arch/nios2/boot/Makefile | 2 -
arch/openrisc/boot/dts/Makefile | 2 -
arch/powerpc/boot/.gitignore | 1 -
arch/powerpc/boot/Makefile | 2 +-
arch/powerpc/platforms/pseries/dlpar.c | 24 +-
arch/powerpc/platforms/pseries/reconfig.c | 2 +-
arch/sh/boot/dts/Makefile | 2 -
arch/xtensa/boot/.gitignore | 1 -
arch/xtensa/boot/dts/Makefile | 9 +-
drivers/base/core.c | 2 +-
drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c | 14 +-
drivers/of/Kconfig | 4 +
drivers/of/Makefile | 1 +
drivers/of/base.c | 135 +--
drivers/of/dynamic.c | 190 +++-
drivers/of/fdt.c | 91 +-
drivers/of/kobj.c | 164 +++
drivers/of/of_private.h | 51 +-
drivers/of/overlay.c | 1049 +++++++++++++-------
drivers/of/resolver.c | 15 +-
drivers/of/unittest-data/.gitignore | 2 -
drivers/of/unittest.c | 83 +-
include/linux/of.h | 45 +-
scripts/Makefile.dtbinst | 6 +-
scripts/Makefile.lib | 5 +
scripts/dtc/checks.c | 291 +++++-
scripts/dtc/dtc-lexer.lex.c_shipped | 10 +-
scripts/dtc/dtc-parser.tab.c_shipped | 430 ++++----
scripts/dtc/dtc-parser.y | 20 +-
scripts/dtc/dtc.c | 2 +-
scripts/dtc/dtc.h | 3 +
scripts/dtc/libfdt/fdt_addresses.c | 96 ++
scripts/dtc/libfdt/fdt_empty_tree.c | 1 -
scripts/dtc/libfdt/fdt_overlay.c | 861 ++++++++++++++++
scripts/dtc/libfdt/fdt_ro.c | 4 +-
scripts/dtc/libfdt/fdt_rw.c | 24 +-
scripts/dtc/libfdt/fdt_sw.c | 16 +-
scripts/dtc/libfdt/fdt_wip.c | 4 +-
scripts/dtc/libfdt/libfdt.h | 47 +
scripts/dtc/livetree.c | 31 +-
scripts/dtc/update-dtc-source.sh | 4 +-
scripts/dtc/version_gen.h | 2 +-
237 files changed, 3136 insertions(+), 1439 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/rtc/dallas,ds1339.txt
create mode 100644 Documentation/devicetree/bindings/rtc/rtc-ds1307.txt
create mode 100644 Documentation/devicetree/bindings/rtc/rtc-m41t80.txt
create mode 100644 Documentation/devicetree/bindings/rtc/sirf,prima2-sysrtc.txt
create mode 100644
Documentation/devicetree/bindings/rtc/stericsson,coh901331.txt
delete mode 100644 arch/arm64/boot/dts/.gitignore
create mode 100644 drivers/of/kobj.c
delete mode 100644 drivers/of/unittest-data/.gitignore
create mode 100644 scripts/dtc/libfdt/fdt_addresses.c
create mode 100644 scripts/dtc/libfdt/fdt_overlay.c
--
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^ permalink raw reply
* [patch v12 0/4] JTAG driver introduction
From: Oleksandr Shamray @ 2017-11-14 16:11 UTC (permalink / raw)
To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, arnd-r2nGTMty4D4
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, openbmc-uLR06cmDAlY/bJ5BZ2RsiQ,
joel-U3u1mxZcP9KHXe+LvDLADg, jiri-rHqAuBHg3fBzbRFIqnYvSA,
tklauser-93Khv+1bN0NyDzI6CaY1VQ,
linux-serial-u79uwXL29TY76Z2rM5mHXA, mec-WqBc5aa1uDFeoWH0uzbU5w,
vadimp-VPRAkNaXOzVWk0Htik3J/w,
system-sw-low-level-VPRAkNaXOzVWk0Htik3J/w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
openocd-devel-owner-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
linux-api-u79uwXL29TY76Z2rM5mHXA, davem-fT/PcQaiUtIeIZ0/mPfg9Q,
mchehab-DgEjT+Ai2ygdnm+yROfE0A, Oleksandr Shamray
When a need raise up to use JTAG interface for system's devices
programming or CPU debugging, usually the user layer
application implements jtag protocol by bit-bang or using a
proprietary connection to vendor hardware.
This method can be slow and not generic.
We propose to implement general JTAG interface and infrastructure
to communicate with user layer application. In such way, we can
have the standard JTAG interface core part and separation from
specific HW implementation.
This allow new capability to debug the CPU or program system's
device via BMC without additional devices nor cost.
This patch purpose is to add JTAG master core infrastructure by
defining new JTAG class and provide generic JTAG interface
to allow hardware specific drivers to connect this interface.
This will enable all JTAG drivers to use the common interface
part and will have separate for hardware implementation.
The JTAG (Joint Test Action Group) core driver provides minimal generic
JTAG interface, which can be used by hardware specific JTAG master
controllers. By providing common interface for the JTAG controllers,
user space device programing is hardware independent.
Modern SoC which in use for embedded system' equipped with
internal JTAG master interface.
This interface is used for programming and debugging system's
hardware components, like CPLD, FPGA, CPU, voltage and
industrial controllers.
Firmware for such devices can be upgraded through JTAG interface during
Runtime. The JTAG standard support for multiple devices programming,
is in case their lines are daisy-chained together.
For example, systems which equipped with host CPU, BMC SoC or/and
number of programmable devices are capable to connect a pin and
select system components dynamically for programming and debugging,
This is using by the BMC which is equipped with internal SoC master
controller.
For example:
BMC JTAG master --> pin selected to CPLDs chain for programming (filed
upgrade, production)
BMC JTAG master --> pin selected to voltage monitors for programming
(field upgrade, production)
BMC JTAG master --> pin selected to host CPU (on-site debugging
and developers debugging)
For example, we can have application in user space which using calls
to JTAG driver executes CPLD programming directly from SVF file
The JTAG standard (IEEE 1149.1) defines the next connector pins:
- TDI (Test Data In);
- TDO (Test Data Out);
- TCK (Test Clock);
- TMS (Test Mode Select);
- TRST (Test Reset) (Optional);
The SoC equipped with JTAG master controller, performs
device programming on command or vector level. For example
a file in a standard SVF (Serial Vector Format) that contains
boundary scan vectors, can be used by sending each vector
to the JTAG interface and the JTAG controller will execute
the programming.
Initial version provides the system calls set for:
- SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
- SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardware specific driver.
Oleksandr Shamray (4):
drivers: jtag: Add JTAG core driver
drivers: jtag: Add Aspeed SoC 24xx and 25xx families JTAG master
driver
Documentation: jtag: Add bindings for Aspeed SoC 24xx and 25xx
families JTAG master driver
Documentation: jtag: Add ABI documentation
Documentation/ABI/testing/jtag-dev | 27 +
.../devicetree/bindings/jtag/aspeed-jtag.txt | 18 +
Documentation/ioctl/ioctl-number.txt | 2 +
MAINTAINERS | 10 +
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/jtag/Kconfig | 29 +
drivers/jtag/Makefile | 2 +
drivers/jtag/jtag-aspeed.c | 782 ++++++++++++++++++++
drivers/jtag/jtag.c | 292 ++++++++
include/linux/jtag.h | 46 ++
include/uapi/linux/jtag.h | 105 +++
12 files changed, 1316 insertions(+), 0 deletions(-)
create mode 100644 Documentation/ABI/testing/jtag-dev
create mode 100644 Documentation/devicetree/bindings/jtag/aspeed-jtag.txt
create mode 100644 drivers/jtag/Kconfig
create mode 100644 drivers/jtag/Makefile
create mode 100644 drivers/jtag/jtag-aspeed.c
create mode 100644 drivers/jtag/jtag.c
create mode 100644 include/linux/jtag.h
create mode 100644 include/uapi/linux/jtag.h
--
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^ permalink raw reply
* [patch v12 1/4] drivers: jtag: Add JTAG core driver
From: Oleksandr Shamray @ 2017-11-14 16:11 UTC (permalink / raw)
To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, arnd-r2nGTMty4D4
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, openbmc-uLR06cmDAlY/bJ5BZ2RsiQ,
joel-U3u1mxZcP9KHXe+LvDLADg, jiri-rHqAuBHg3fBzbRFIqnYvSA,
tklauser-93Khv+1bN0NyDzI6CaY1VQ,
linux-serial-u79uwXL29TY76Z2rM5mHXA, mec-WqBc5aa1uDFeoWH0uzbU5w,
vadimp-VPRAkNaXOzVWk0Htik3J/w,
system-sw-low-level-VPRAkNaXOzVWk0Htik3J/w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
openocd-devel-owner-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
linux-api-u79uwXL29TY76Z2rM5mHXA, davem-fT/PcQaiUtIeIZ0/mPfg9Q,
mchehab-DgEjT+Ai2ygdnm+yROfE0A, Oleksandr Shamray, Jiri Pirko
In-Reply-To: <1510675867-24276-1-git-send-email-oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
Initial patch for JTAG driver
JTAG class driver provide infrastructure to support hardware/software
JTAG platform drivers. It provide user layer API interface for flashing
and debugging external devices which equipped with JTAG interface
using standard transactions.
Driver exposes set of IOCTL to user space for:
- XFER:
- SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
- SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks).
- SIOCFREQ/GIOCFREQ for setting and reading JTAG frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray <oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
Signed-off-by: Jiri Pirko <jiri-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
---
v11->v12
Comments pointed by Greg KH <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
- Change jtag.h licence type to
SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
and reorder line with license in description
Chip Bilbrey <chip-Gz1Ta9Qd61ZAfugRpC6u6w@public.gmane.org>
- Remove Apeed reference from uapi jtag.h header
- Remove access mode from xfer and idle transactions
- Add new ioctl JTAG_SIOCMODE for set hw mode
- Add only one open per JTAG port blocking with mutex blocking
v10->v11
Notifications from kbuild test robot <lkp-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
- include types.h headeri to jtag.h
- fix incompatible type of xfer callback
- remove rdundant class defination
- Fix return order in case of xfer error
V9->v10
Comments pointed by Greg KH <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
- remove unnecessary alignment for pirv data
- move jtag_copy_to_user and jtag_copy_from_user code just to ioctl
- move int jtag_run_test_idle_op and jtag_xfer_op code
just to ioctl
- change return error codes to more applicable
- add missing error checks
- fix error check order in ioctl
- remove unnecessary blank lines
- add param validation to ioctl
- remove compat_ioctl
- remove only one open per JTAG port blocking.
User will care about this.
- Fix idr memory leak on jtag_exit
- change cdev device type to misc
V8->v9
Comments pointed by Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
- use get_user() instead of __get_user().
- change jtag->open type from int to atomic_t
- remove spinlock on jtg_open
- remove mutex on jtag_register
- add unregister_chrdev_region on jtag_init err
- add unregister_chrdev_region on jtag_exit
- remove unnecessary pointer casts
- add *data parameter to xfer function prototype
v7->v8
Comments pointed by Moritz Fischer <moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w@public.gmane.org>
- Fix misspelling s/friver/driver
v6->v7
Notifications from kbuild test robot <lkp-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
- Remove include asm/types.h from jtag.h
- Add include <linux/types.h> to jtag.c
v5->v6
v4->v5
v3->v4
Comments pointed by Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
- change transaction pointer tdio type to __u64
- change internal status type from enum to __u32
- reorder jtag_xfer members to avoid the implied padding
- add __packed attribute to jtag_xfer and jtag_run_test_idle
v2->v3
Notifications from kbuild test robot <lkp-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
- Change include path to <linux/types.h> in jtag.h
v1->v2
Comments pointed by Greg KH <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
- Change license type from GPLv2/BSD to GPLv2
- Change type of variables which crossed user/kernel to __type
- Remove "default n" from Kconfig
Comments pointed by Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
- Change list_add_tail in jtag_unregister to list_del
Comments pointed by Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
- Add SPDX-License-Identifier instead of license text
Comments pointed by Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
- Change __copy_to_user to memdup_user
- Change __put_user to put_user
- Change type of variables to __type for compatible 32 and 64-bit systems
- Add check for maximum xfer data size
- Change lookup data mechanism to get jtag data from inode
- Add .compat_ioctl to file ops
- Add mem alignment for jtag priv data
Comments pointed by Tobias Klauser <tklauser-93Khv+1bN0NyDzI6CaY1VQ@public.gmane.org>
- Change function names to avoid match with variable types
- Fix description for jtag_ru_test_idle in uapi jtag.h
- Fix misprints IDEL/IDLE, trough/through
---
Documentation/ioctl/ioctl-number.txt | 2 +
MAINTAINERS | 10 ++
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/jtag/Kconfig | 16 ++
drivers/jtag/Makefile | 1 +
drivers/jtag/jtag.c | 292 ++++++++++++++++++++++++++++++++++
include/linux/jtag.h | 46 ++++++
include/uapi/linux/jtag.h | 105 ++++++++++++
9 files changed, 475 insertions(+), 0 deletions(-)
create mode 100644 drivers/jtag/Kconfig
create mode 100644 drivers/jtag/Makefile
create mode 100644 drivers/jtag/jtag.c
create mode 100644 include/linux/jtag.h
create mode 100644 include/uapi/linux/jtag.h
diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt
index 3e3fdae..1af2508 100644
--- a/Documentation/ioctl/ioctl-number.txt
+++ b/Documentation/ioctl/ioctl-number.txt
@@ -321,6 +321,8 @@ Code Seq#(hex) Include File Comments
0xB0 all RATIO devices in development:
<mailto:vgo-/IYFIZglx74@public.gmane.org>
0xB1 00-1F PPPoX <mailto:mostrows-TTukF6hB3AoKZpuMuFhwt/d9D2ou9A/h@public.gmane.org>
+0xB2 00-0f linux/jtag.h JTAG driver
+ <mailto:oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
0xB3 00 linux/mmc/ioctl.h
0xB4 00-0F linux/gpio.h <mailto:linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
0xB5 00-0F uapi/linux/rpmsg.h <mailto:linux-remoteproc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index 205d397..dfcf49c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7292,6 +7292,16 @@ L: linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
S: Maintained
F: drivers/tty/serial/jsm/
+JTAG SUBSYSTEM
+M: Oleksandr Shamray <oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
+M: Vadim Pasternak <vadimp-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
+S: Maintained
+F: include/linux/jtag.h
+F: include/uapi/linux/jtag.h
+F: drivers/jtag/
+F: Documentation/devicetree/bindings/jtag/
+F: Documentation/ABI/testing/jtag-cdev
+
K10TEMP HARDWARE MONITORING DRIVER
M: Clemens Ladisch <clemens-P6GI/4k7KOmELgA04lAiVw@public.gmane.org>
L: linux-hwmon-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 505c676..2214678 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -208,4 +208,6 @@ source "drivers/tee/Kconfig"
source "drivers/mux/Kconfig"
+source "drivers/jtag/Kconfig"
+
endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index dfdcda0..6a2059b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -182,3 +182,4 @@ obj-$(CONFIG_FPGA) += fpga/
obj-$(CONFIG_FSI) += fsi/
obj-$(CONFIG_TEE) += tee/
obj-$(CONFIG_MULTIPLEXER) += mux/
+obj-$(CONFIG_JTAG) += jtag/
diff --git a/drivers/jtag/Kconfig b/drivers/jtag/Kconfig
new file mode 100644
index 0000000..0fad1a3
--- /dev/null
+++ b/drivers/jtag/Kconfig
@@ -0,0 +1,16 @@
+menuconfig JTAG
+ tristate "JTAG support"
+ ---help---
+ This provides basic core functionality support for jtag class devices
+ Hardware equipped with JTAG microcontroller which can be built
+ on top of this drivers. Driver exposes the set of IOCTL to the
+ user space for:
+ SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
+ SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
+ RUNTEST (Forces IEEE 1149.1 bus to a run state for specified
+ number of clocks).
+
+ If you want this support, you should say Y here.
+
+ To compile this driver as a module, choose M here: the module will
+ be called jtag.
diff --git a/drivers/jtag/Makefile b/drivers/jtag/Makefile
new file mode 100644
index 0000000..af37493
--- /dev/null
+++ b/drivers/jtag/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_JTAG) += jtag.o
diff --git a/drivers/jtag/jtag.c b/drivers/jtag/jtag.c
new file mode 100644
index 0000000..fbeba84
--- /dev/null
+++ b/drivers/jtag/jtag.c
@@ -0,0 +1,292 @@
+/*
+ * drivers/jtag/jtag.c
+ *
+ * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
+ * Copyright (c) 2017 Oleksandr Shamray <oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
+ *
+ * Released under the GPLv2 only.
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/jtag.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/rtnetlink.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <uapi/linux/jtag.h>
+
+#define JTAG_NAME "jtag0"
+#define MAX_JTAG_NAME_LEN (sizeof("jtag") + 5)
+
+struct jtag {
+ struct miscdevice miscdev;
+ struct device *dev;
+ const struct jtag_ops *ops;
+ int id;
+ bool opened;
+ struct mutex open_lock;
+ unsigned long priv[0];
+};
+
+static DEFINE_IDA(jtag_ida);
+
+void *jtag_priv(struct jtag *jtag)
+{
+ return jtag->priv;
+}
+EXPORT_SYMBOL_GPL(jtag_priv);
+
+static long jtag_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+ struct jtag *jtag = file->private_data;
+ struct jtag_run_test_idle idle;
+ struct jtag_xfer xfer;
+ u8 *xfer_data;
+ u32 data_size;
+ u32 value;
+ int err;
+
+ if (!arg)
+ return -EINVAL;
+
+ switch (cmd) {
+ case JTAG_GIOCFREQ:
+
+ if (jtag->ops->freq_get)
+ err = jtag->ops->freq_get(jtag, &value);
+ else
+ err = -EOPNOTSUPP;
+ if (err)
+ break;
+
+ if (put_user(value, (__u32 *)arg))
+ err = -EFAULT;
+ break;
+
+ case JTAG_SIOCFREQ:
+ if (get_user(value, (__u32 *)arg))
+ return -EFAULT;
+ if (value == 0)
+ return -EINVAL;
+
+ if (jtag->ops->freq_set)
+ err = jtag->ops->freq_set(jtag, value);
+ else
+ err = -EOPNOTSUPP;
+ break;
+
+ case JTAG_IOCRUNTEST:
+ if (copy_from_user(&idle, (void *)arg,
+ sizeof(struct jtag_run_test_idle)))
+ return -EFAULT;
+
+ if (idle.endstate > JTAG_STATE_PAUSEDR)
+ return -EINVAL;
+
+ if (jtag->ops->idle)
+ err = jtag->ops->idle(jtag, &idle);
+ else
+ err = -EOPNOTSUPP;
+ break;
+
+ case JTAG_IOCXFER:
+ if (copy_from_user(&xfer, (void *)arg,
+ sizeof(struct jtag_xfer)))
+ return -EFAULT;
+
+ if (xfer.length >= JTAG_MAX_XFER_DATA_LEN)
+ return -EINVAL;
+
+ if (xfer.type > JTAG_SDR_XFER)
+ return -EINVAL;
+
+ if (xfer.direction > JTAG_WRITE_XFER)
+ return -EINVAL;
+
+ if (xfer.endstate > JTAG_STATE_PAUSEDR)
+ return -EINVAL;
+
+ data_size = DIV_ROUND_UP(xfer.length, BITS_PER_BYTE);
+ xfer_data = memdup_user(u64_to_user_ptr(xfer.tdio), data_size);
+
+ if (!xfer_data)
+ return -EFAULT;
+
+ if (jtag->ops->xfer) {
+ err = jtag->ops->xfer(jtag, &xfer, xfer_data);
+ } else {
+ kfree(xfer_data);
+ return -EOPNOTSUPP;
+ }
+
+ if (err) {
+ kfree(xfer_data);
+ return -EFAULT;
+ }
+
+ err = copy_to_user(u64_to_user_ptr(xfer.tdio),
+ (void *)(xfer_data), data_size);
+
+ if (err) {
+ kfree(xfer_data);
+ return -EFAULT;
+ }
+
+ kfree(xfer_data);
+ if (copy_to_user((void *)arg, &xfer, sizeof(struct jtag_xfer)))
+ return -EFAULT;
+ break;
+
+ case JTAG_GIOCSTATUS:
+ if (jtag->ops->status_get)
+ err = jtag->ops->status_get(jtag, &value);
+ else
+ err = -EOPNOTSUPP;
+ if (err)
+ break;
+
+ err = put_user(value, (__u32 *)arg);
+ if (err)
+ err = -EFAULT;
+ break;
+ case JTAG_SIOCMODE:
+ if (get_user(value, (__u32 *)arg))
+ return -EFAULT;
+ if (value == 0)
+ return -EINVAL;
+
+ if (jtag->ops->mode_set)
+ err = jtag->ops->mode_set(jtag, value);
+ else
+ err = -EOPNOTSUPP;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+ return err;
+}
+
+static int jtag_open(struct inode *inode, struct file *file)
+{
+ struct jtag *jtag = container_of(file->private_data, struct jtag,
+ miscdev);
+
+ if (mutex_lock_interruptible(&jtag->open_lock))
+ return -ERESTARTSYS;
+
+ if (jtag->opened) {
+ mutex_unlock(&jtag->open_lock);
+ return -EINVAL;
+ }
+
+ nonseekable_open(inode, file);
+ file->private_data = jtag;
+ jtag->opened = true;
+ mutex_unlock(&jtag->open_lock);
+ return 0;
+}
+
+static int jtag_release(struct inode *inode, struct file *file)
+{
+ struct jtag *jtag = file->private_data;
+
+ mutex_lock(&jtag->open_lock);
+ jtag->opened = false;
+ mutex_unlock(&jtag->open_lock);
+ return 0;
+}
+
+static const struct file_operations jtag_fops = {
+ .owner = THIS_MODULE,
+ .open = jtag_open,
+ .release = jtag_release,
+ .llseek = noop_llseek,
+ .unlocked_ioctl = jtag_ioctl,
+};
+
+struct jtag *jtag_alloc(size_t priv_size, const struct jtag_ops *ops)
+{
+ struct jtag *jtag;
+
+ jtag = kzalloc(sizeof(*jtag) + round_up(priv_size, ARCH_DMA_MINALIGN),
+ GFP_KERNEL);
+ if (!jtag)
+ return NULL;
+
+ jtag->ops = ops;
+ return jtag;
+}
+EXPORT_SYMBOL_GPL(jtag_alloc);
+
+void jtag_free(struct jtag *jtag)
+{
+ kfree(jtag);
+}
+EXPORT_SYMBOL_GPL(jtag_free);
+
+int jtag_register(struct jtag *jtag)
+{
+ char *name;
+ int err;
+ int id;
+
+ id = ida_simple_get(&jtag_ida, 0, 0, GFP_KERNEL);
+ if (id < 0)
+ return id;
+
+ jtag->id = id;
+
+ name = kzalloc(MAX_JTAG_NAME_LEN, GFP_KERNEL);
+ if (!name) {
+ err = -ENOMEM;
+ goto err_jtag_alloc;
+ }
+
+ err = snprintf(name, MAX_JTAG_NAME_LEN, "jtag%d", id);
+ if (err < 0)
+ goto err_jtag_name;
+
+ mutex_init(&jtag->open_lock);
+ jtag->miscdev.fops = &jtag_fops;
+ jtag->miscdev.minor = MISC_DYNAMIC_MINOR;
+ jtag->miscdev.name = name;
+
+ err = misc_register(&jtag->miscdev);
+ if (err)
+ dev_err(jtag->dev, "Unable to register device\n");
+ else
+ return 0;
+ jtag->opened = false;
+
+err_jtag_name:
+ kfree(name);
+err_jtag_alloc:
+ ida_simple_remove(&jtag_ida, id);
+ return err;
+}
+EXPORT_SYMBOL_GPL(jtag_register);
+
+void jtag_unregister(struct jtag *jtag)
+{
+ misc_deregister(&jtag->miscdev);
+ kfree(jtag->miscdev.name);
+ ida_simple_remove(&jtag_ida, jtag->id);
+}
+EXPORT_SYMBOL_GPL(jtag_unregister);
+
+static void __exit jtag_exit(void)
+{
+ ida_destroy(&jtag_ida);
+}
+
+module_exit(jtag_exit);
+
+MODULE_AUTHOR("Oleksandr Shamray <oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>");
+MODULE_DESCRIPTION("Generic jtag support");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/jtag.h b/include/linux/jtag.h
new file mode 100644
index 0000000..66b6389
--- /dev/null
+++ b/include/linux/jtag.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * include/linux/jtag.h - JTAG class driver
+ *
+ * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
+ * Copyright (c) 2017 Oleksandr Shamray <oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
+ */
+
+#ifndef __JTAG_H
+#define __JTAG_H
+
+#include <uapi/linux/jtag.h>
+
+#ifndef ARCH_DMA_MINALIGN
+#define ARCH_DMA_MINALIGN 1
+#endif
+
+#define jtag_u64_to_ptr(arg) ((void *)(uintptr_t)arg)
+
+#define JTAG_MAX_XFER_DATA_LEN 65535
+
+struct jtag;
+/**
+ * struct jtag_ops - callbacks for jtag control functions:
+ *
+ * @freq_get: get frequency function. Filled by device driver
+ * @freq_set: set frequency function. Filled by device driver
+ * @status_get: set status function. Filled by device driver
+ * @idle: set JTAG to idle state function. Filled by device driver
+ * @xfer: send JTAG xfer function. Filled by device driver
+ */
+struct jtag_ops {
+ int (*freq_get)(struct jtag *jtag, u32 *freq);
+ int (*freq_set)(struct jtag *jtag, u32 freq);
+ int (*status_get)(struct jtag *jtag, u32 *state);
+ int (*idle)(struct jtag *jtag, struct jtag_run_test_idle *idle);
+ int (*xfer)(struct jtag *jtag, struct jtag_xfer *xfer, u8 *xfer_data);
+ int (*mode_set)(struct jtag *jtag, u32 mode_mask);
+};
+
+void *jtag_priv(struct jtag *jtag);
+int jtag_register(struct jtag *jtag);
+void jtag_unregister(struct jtag *jtag);
+struct jtag *jtag_alloc(size_t priv_size, const struct jtag_ops *ops);
+void jtag_free(struct jtag *jtag);
+
+#endif /* __JTAG_H */
diff --git a/include/uapi/linux/jtag.h b/include/uapi/linux/jtag.h
new file mode 100644
index 0000000..b6c4dde
--- /dev/null
+++ b/include/uapi/linux/jtag.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
+ * include/uapi/linux/jtag.h - JTAG class driver uapi
+ *
+ * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
+ * Copyright (c) 2017 Oleksandr Shamray <oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
+ */
+
+#ifndef __UAPI_LINUX_JTAG_H
+#define __UAPI_LINUX_JTAG_H
+
+#include <linux/types.h>
+/*
+ * JTAG_XFER_HW_MODE: JTAG hardware mode. Used to set HW drived or bitbang
+ * mode. This is bitmask param of ioctl JTAG_SIOCMODE command
+ */
+#define JTAG_XFER_HW_MODE 1
+
+/**
+ * enum jtag_endstate:
+ *
+ * @JTAG_STATE_IDLE: JTAG state machine IDLE state
+ * @JTAG_STATE_PAUSEIR: JTAG state machine PAUSE_IR state
+ * @JTAG_STATE_PAUSEDR: JTAG state machine PAUSE_DR state
+ */
+enum jtag_endstate {
+ JTAG_STATE_IDLE,
+ JTAG_STATE_PAUSEIR,
+ JTAG_STATE_PAUSEDR,
+};
+
+/**
+ * enum jtag_xfer_type:
+ *
+ * @JTAG_SIR_XFER: SIR transfer
+ * @JTAG_SDR_XFER: SDR transfer
+ */
+enum jtag_xfer_type {
+ JTAG_SIR_XFER,
+ JTAG_SDR_XFER,
+};
+
+/**
+ * enum jtag_xfer_direction:
+ *
+ * @JTAG_READ_XFER: read transfer
+ * @JTAG_WRITE_XFER: write transfer
+ */
+enum jtag_xfer_direction {
+ JTAG_READ_XFER,
+ JTAG_WRITE_XFER,
+};
+
+/**
+ * struct jtag_run_test_idle - forces JTAG state machine to
+ * RUN_TEST/IDLE state
+ *
+ * @reset: 0 - run IDLE/PAUSE from current state
+ * 1 - go through TEST_LOGIC/RESET state before IDLE/PAUSE
+ * @end: completion flag
+ * @tck: clock counter
+ *
+ * Structure represents interface to JTAG device for jtag idle
+ * execution.
+ */
+struct jtag_run_test_idle {
+ __u8 reset;
+ __u8 endstate;
+ __u8 tck;
+};
+
+/**
+ * struct jtag_xfer - jtag xfer:
+ *
+ * @type: transfer type
+ * @direction: xfer direction
+ * @length: xfer bits len
+ * @tdio : xfer data array
+ * @endir: xfer end state
+ *
+ * Structure represents interface to JTAG device for jtag sdr xfer
+ * execution.
+ */
+struct jtag_xfer {
+ __u8 type;
+ __u8 direction;
+ __u8 endstate;
+ __u32 length;
+ __u64 tdio;
+};
+
+/* ioctl interface */
+#define __JTAG_IOCTL_MAGIC 0xb2
+
+#define JTAG_IOCRUNTEST _IOW(__JTAG_IOCTL_MAGIC, 0,\
+ struct jtag_run_test_idle)
+#define JTAG_SIOCFREQ _IOW(__JTAG_IOCTL_MAGIC, 1, unsigned int)
+#define JTAG_GIOCFREQ _IOR(__JTAG_IOCTL_MAGIC, 2, unsigned int)
+#define JTAG_IOCXFER _IOWR(__JTAG_IOCTL_MAGIC, 3, struct jtag_xfer)
+#define JTAG_GIOCSTATUS _IOWR(__JTAG_IOCTL_MAGIC, 4, enum jtag_endstate)
+#define JTAG_SIOCMODE _IOW(__JTAG_IOCTL_MAGIC, 5, unsigned int)
+
+#define JTAG_FIRST_MINOR 0
+#define JTAG_MAX_DEVICES 32
+
+#endif /* __UAPI_LINUX_JTAG_H */
--
1.7.1
^ permalink raw reply related
* [patch v12 2/4] drivers: jtag: Add Aspeed SoC 24xx and 25xx families JTAG master driver
From: Oleksandr Shamray @ 2017-11-14 16:11 UTC (permalink / raw)
To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, arnd-r2nGTMty4D4
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, openbmc-uLR06cmDAlY/bJ5BZ2RsiQ,
joel-U3u1mxZcP9KHXe+LvDLADg, jiri-rHqAuBHg3fBzbRFIqnYvSA,
tklauser-93Khv+1bN0NyDzI6CaY1VQ,
linux-serial-u79uwXL29TY76Z2rM5mHXA, mec-WqBc5aa1uDFeoWH0uzbU5w,
vadimp-VPRAkNaXOzVWk0Htik3J/w,
system-sw-low-level-VPRAkNaXOzVWk0Htik3J/w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
openocd-devel-owner-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
linux-api-u79uwXL29TY76Z2rM5mHXA, davem-fT/PcQaiUtIeIZ0/mPfg9Q,
mchehab-DgEjT+Ai2ygdnm+yROfE0A, Oleksandr Shamray, Jiri Pirko
In-Reply-To: <1510675867-24276-1-git-send-email-oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
Driver adds support of Aspeed 2500/2400 series SOC JTAG master controller.
Driver implements the following jtag ops:
- freq_get;
- freq_set;
- status_get;
- idle;
- xfer;
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray <oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
Signed-off-by: Jiri Pirko <jiri-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
Acked-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
---
v11->v12
Comments pointed by Chip Bilbrey <chip-Gz1Ta9Qd61ZAfugRpC6u6w@public.gmane.org>
- Remove access mode from xfer and idle transactions
- Add new ioctl JTAG_SIOCMODE for set hw mode
v10->v11
v9->v10
V8->v9
Comments pointed by Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
- add *data parameter to xfer function prototype
v7->v8
Comments pointed by Joel Stanley <joel.stan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
- aspeed_jtag_init replace goto to return;
- change input variables type from __u32 to u32
in functios freq_get, freq_set, status_get
- change sm_ variables type from char to u8
- in jatg_init add disable clocks on error case
- remove release_mem_region on error case
- remove devm_free_irq on jtag_deinit
- Fix misspelling Disabe/Disable
- Change compatible string to ast2400 and ast2000
v6->v7
Notifications from kbuild test robot <lkp-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
- Add include <linux/types.h> to jtag-asapeed.c
v5->v6
v4->v5
Comments pointed by Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
- Added HAS_IOMEM dependence in Kconfig to avoid
"undefined reference to `devm_ioremap_resource'" error,
because in some arch this not supported
v3->v4
Comments pointed by Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
- change transaction pointer tdio type to __u64
- change internal status type from enum to __u32
v2->v3
v1->v2
Comments pointed by Greg KH <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
- change license type from GPLv2/BSD to GPLv2
Comments pointed by Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
- Add clk_prepare_enable/clk_disable_unprepare in clock init/deinit
- Change .compatible to soc-specific compatible names
aspeed,aspeed4000-jtag/aspeed5000-jtag
- Added dt-bindings
Comments pointed by Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
- Reorder functions and removed the forward declarations
- Add static const qualifier to state machine states transitions
- Change .compatible to soc-specific compatible names
aspeed,aspeed4000-jtag/aspeed5000-jtag
- Add dt-bindings
Comments pointed by Randy Dunlap <rdunlap-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
- Change module name jtag-aspeed in description in Kconfig
Comments pointed by kbuild test robot <lkp-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
- Remove invalid include <asm/mach-types.h>
- add resource_size instead of calculation
---
drivers/jtag/Kconfig | 13 +
drivers/jtag/Makefile | 1 +
drivers/jtag/jtag-aspeed.c | 782 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 796 insertions(+), 0 deletions(-)
create mode 100644 drivers/jtag/jtag-aspeed.c
diff --git a/drivers/jtag/Kconfig b/drivers/jtag/Kconfig
index 0fad1a3..098beb0 100644
--- a/drivers/jtag/Kconfig
+++ b/drivers/jtag/Kconfig
@@ -14,3 +14,16 @@ menuconfig JTAG
To compile this driver as a module, choose M here: the module will
be called jtag.
+
+menuconfig JTAG_ASPEED
+ tristate "Aspeed SoC JTAG controller support"
+ depends on JTAG && HAS_IOMEM
+ ---help---
+ This provides a support for Aspeed JTAG device, equipped on
+ Aspeed SoC 24xx and 25xx families. Drivers allows programming
+ of hardware devices, connected to SoC through the JTAG interface.
+
+ If you want this support, you should say Y here.
+
+ To compile this driver as a module, choose M here: the module will
+ be called jtag-aspeed.
diff --git a/drivers/jtag/Makefile b/drivers/jtag/Makefile
index af37493..04a855e 100644
--- a/drivers/jtag/Makefile
+++ b/drivers/jtag/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_JTAG) += jtag.o
+obj-$(CONFIG_JTAG_ASPEED) += jtag-aspeed.o
diff --git a/drivers/jtag/jtag-aspeed.c b/drivers/jtag/jtag-aspeed.c
new file mode 100644
index 0000000..a6e2417
--- /dev/null
+++ b/drivers/jtag/jtag-aspeed.c
@@ -0,0 +1,782 @@
+/*
+ * drivers/jtag/aspeed-jtag.c
+ *
+ * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
+ * Copyright (c) 2017 Oleksandr Shamray <oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
+ *
+ * Released under the GPLv2 only.
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/jtag.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <uapi/linux/jtag.h>
+
+#define ASPEED_JTAG_DATA 0x00
+#define ASPEED_JTAG_INST 0x04
+#define ASPEED_JTAG_CTRL 0x08
+#define ASPEED_JTAG_ISR 0x0C
+#define ASPEED_JTAG_SW 0x10
+#define ASPEED_JTAG_TCK 0x14
+#define ASPEED_JTAG_EC 0x18
+
+#define ASPEED_JTAG_DATA_MSB 0x01
+#define ASPEED_JTAG_DATA_CHUNK_SIZE 0x20
+
+/* ASPEED_JTAG_CTRL: Engine Control */
+#define ASPEED_JTAG_CTL_ENG_EN BIT(31)
+#define ASPEED_JTAG_CTL_ENG_OUT_EN BIT(30)
+#define ASPEED_JTAG_CTL_FORCE_TMS BIT(29)
+#define ASPEED_JTAG_CTL_INST_LEN(x) ((x) << 20)
+#define ASPEED_JTAG_CTL_LASPEED_INST BIT(17)
+#define ASPEED_JTAG_CTL_INST_EN BIT(16)
+#define ASPEED_JTAG_CTL_DR_UPDATE BIT(10)
+#define ASPEED_JTAG_CTL_DATA_LEN(x) ((x) << 4)
+#define ASPEED_JTAG_CTL_LASPEED_DATA BIT(1)
+#define ASPEED_JTAG_CTL_DATA_EN BIT(0)
+
+/* ASPEED_JTAG_ISR : Interrupt status and enable */
+#define ASPEED_JTAG_ISR_INST_PAUSE BIT(19)
+#define ASPEED_JTAG_ISR_INST_COMPLETE BIT(18)
+#define ASPEED_JTAG_ISR_DATA_PAUSE BIT(17)
+#define ASPEED_JTAG_ISR_DATA_COMPLETE BIT(16)
+#define ASPEED_JTAG_ISR_INST_PAUSE_EN BIT(3)
+#define ASPEED_JTAG_ISR_INST_COMPLETE_EN BIT(2)
+#define ASPEED_JTAG_ISR_DATA_PAUSE_EN BIT(1)
+#define ASPEED_JTAG_ISR_DATA_COMPLETE_EN BIT(0)
+#define ASPEED_JTAG_ISR_INT_EN_MASK GENMASK(3, 0)
+#define ASPEED_JTAG_ISR_INT_MASK GENMASK(19, 16)
+
+/* ASPEED_JTAG_SW : Software Mode and Status */
+#define ASPEED_JTAG_SW_MODE_EN BIT(19)
+#define ASPEED_JTAG_SW_MODE_TCK BIT(18)
+#define ASPEED_JTAG_SW_MODE_TMS BIT(17)
+#define ASPEED_JTAG_SW_MODE_TDIO BIT(16)
+
+/* ASPEED_JTAG_TCK : TCK Control */
+#define ASPEED_JTAG_TCK_DIVISOR_MASK GENMASK(10, 0)
+#define ASPEED_JTAG_TCK_GET_DIV(x) ((x) & ASPEED_JTAG_TCK_DIVISOR_MASK)
+
+/* ASPEED_JTAG_EC : Controller set for go to IDLE */
+#define ASPEED_JTAG_EC_GO_IDLE BIT(0)
+
+#define ASPEED_JTAG_IOUT_LEN(len) (ASPEED_JTAG_CTL_ENG_EN |\
+ ASPEED_JTAG_CTL_ENG_OUT_EN |\
+ ASPEED_JTAG_CTL_INST_LEN(len))
+
+#define ASPEED_JTAG_DOUT_LEN(len) (ASPEED_JTAG_CTL_ENG_EN |\
+ ASPEED_JTAG_CTL_ENG_OUT_EN |\
+ ASPEED_JTAG_CTL_DATA_LEN(len))
+
+#define ASPEED_JTAG_TCK_WAIT 10
+#define ASPEED_JTAG_RESET_CNTR 10
+
+#define ASPEED_JTAG_NAME "jtag-aspeed"
+
+struct aspeed_jtag {
+ void __iomem *reg_base;
+ struct device *dev;
+ struct clk *pclk;
+ enum jtag_endstate status;
+ int irq;
+ u32 flag;
+ wait_queue_head_t jtag_wq;
+ u32 mode;
+};
+
+static char *end_status_str[] = {"idle", "ir pause", "drpause"};
+
+static u32 aspeed_jtag_read(struct aspeed_jtag *aspeed_jtag, u32 reg)
+{
+ return readl(aspeed_jtag->reg_base + reg);
+}
+
+static void
+aspeed_jtag_write(struct aspeed_jtag *aspeed_jtag, u32 val, u32 reg)
+{
+ writel(val, aspeed_jtag->reg_base + reg);
+}
+
+static int aspeed_jtag_freq_set(struct jtag *jtag, u32 freq)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+ unsigned long apb_frq;
+ u32 tck_val;
+ u16 div;
+
+ apb_frq = clk_get_rate(aspeed_jtag->pclk);
+ div = (apb_frq % freq == 0) ? (apb_frq / freq) - 1 : (apb_frq / freq);
+ tck_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_TCK);
+ aspeed_jtag_write(aspeed_jtag,
+ (tck_val & ASPEED_JTAG_TCK_DIVISOR_MASK) | div,
+ ASPEED_JTAG_TCK);
+ return 0;
+}
+
+static int aspeed_jtag_freq_get(struct jtag *jtag, u32 *frq)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+ u32 pclk;
+ u32 tck;
+
+ pclk = clk_get_rate(aspeed_jtag->pclk);
+ tck = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_TCK);
+ *frq = pclk / (ASPEED_JTAG_TCK_GET_DIV(tck) + 1);
+
+ return 0;
+}
+
+static int aspeed_jtag_mode_set(struct jtag *jtag, u32 mode)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ aspeed_jtag->mode = mode;
+ return 0;
+}
+
+static void aspeed_jtag_sw_delay(struct aspeed_jtag *aspeed_jtag, int cnt)
+{
+ int i;
+
+ for (i = 0; i < cnt; i++)
+ aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_SW);
+}
+
+static char aspeed_jtag_tck_cycle(struct aspeed_jtag *aspeed_jtag,
+ u8 tms, u8 tdi)
+{
+ char tdo = 0;
+
+ /* TCK = 0 */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ (tms * ASPEED_JTAG_SW_MODE_TMS) |
+ (tdi * ASPEED_JTAG_SW_MODE_TDIO), ASPEED_JTAG_SW);
+
+ aspeed_jtag_sw_delay(aspeed_jtag, ASPEED_JTAG_TCK_WAIT);
+
+ /* TCK = 1 */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ ASPEED_JTAG_SW_MODE_TCK |
+ (tms * ASPEED_JTAG_SW_MODE_TMS) |
+ (tdi * ASPEED_JTAG_SW_MODE_TDIO), ASPEED_JTAG_SW);
+
+ if (aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_SW) &
+ ASPEED_JTAG_SW_MODE_TDIO)
+ tdo = 1;
+
+ aspeed_jtag_sw_delay(aspeed_jtag, ASPEED_JTAG_TCK_WAIT);
+
+ /* TCK = 0 */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ (tms * ASPEED_JTAG_SW_MODE_TMS) |
+ (tdi * ASPEED_JTAG_SW_MODE_TDIO), ASPEED_JTAG_SW);
+ return tdo;
+}
+
+static void aspeed_jtag_wait_instruction_pause(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq, aspeed_jtag->flag &
+ ASPEED_JTAG_ISR_INST_PAUSE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_INST_PAUSE;
+}
+
+static void
+aspeed_jtag_wait_instruction_complete(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq, aspeed_jtag->flag &
+ ASPEED_JTAG_ISR_INST_COMPLETE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_INST_COMPLETE;
+}
+
+static void
+aspeed_jtag_wait_data_pause_complete(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq, aspeed_jtag->flag &
+ ASPEED_JTAG_ISR_DATA_PAUSE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_DATA_PAUSE;
+}
+
+static void aspeed_jtag_wait_data_complete(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq, aspeed_jtag->flag &
+ ASPEED_JTAG_ISR_DATA_COMPLETE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_DATA_COMPLETE;
+}
+
+static void aspeed_jtag_sm_cycle(struct aspeed_jtag *aspeed_jtag, const u8 *tms,
+ int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ aspeed_jtag_tck_cycle(aspeed_jtag, tms[i], 0);
+}
+
+static void aspeed_jtag_run_test_idle_sw(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_run_test_idle *runtest)
+{
+ static const u8 sm_pause_irpause[] = {1, 1, 1, 1, 0, 1, 0};
+ static const u8 sm_pause_drpause[] = {1, 1, 1, 0, 1, 0};
+ static const u8 sm_idle_irpause[] = {1, 1, 0, 1, 0};
+ static const u8 sm_idle_drpause[] = {1, 0, 1, 0};
+ static const u8 sm_pause_idle[] = {1, 1, 0};
+ int i;
+
+ /* SW mode from idle/pause-> to pause/idle */
+ if (runtest->reset) {
+ for (i = 0; i < ASPEED_JTAG_RESET_CNTR; i++)
+ aspeed_jtag_tck_cycle(aspeed_jtag, 1, 0);
+ }
+
+ switch (aspeed_jtag->status) {
+ case JTAG_STATE_IDLE:
+ switch (runtest->endstate) {
+ case JTAG_STATE_PAUSEIR:
+ /* ->DRSCan->IRSCan->IRCap->IRExit1->PauseIR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_idle_irpause,
+ sizeof(sm_idle_irpause));
+
+ aspeed_jtag->status = JTAG_STATE_PAUSEIR;
+ break;
+ case JTAG_STATE_PAUSEDR:
+ /* ->DRSCan->DRCap->DRExit1->PauseDR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_idle_drpause,
+ sizeof(sm_idle_drpause));
+
+ aspeed_jtag->status = JTAG_STATE_PAUSEDR;
+ break;
+ case JTAG_STATE_IDLE:
+ /* IDLE */
+ aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0);
+ aspeed_jtag->status = JTAG_STATE_IDLE;
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case JTAG_STATE_PAUSEIR:
+ /* Fall-through */
+ case JTAG_STATE_PAUSEDR:
+ /* From IR/DR Pause */
+ switch (runtest->endstate) {
+ case JTAG_STATE_PAUSEIR:
+ /*
+ * to Exit2 IR/DR->Updt IR/DR->DRSCan->IRSCan->IRCap->
+ * IRExit1->PauseIR
+ */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_irpause,
+ sizeof(sm_pause_irpause));
+
+ aspeed_jtag->status = JTAG_STATE_PAUSEIR;
+ break;
+ case JTAG_STATE_PAUSEDR:
+ /*
+ * to Exit2 IR/DR->Updt IR/DR->DRSCan->DRCap->
+ * DRExit1->PauseDR
+ */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_drpause,
+ sizeof(sm_pause_drpause));
+ aspeed_jtag->status = JTAG_STATE_PAUSEDR;
+ break;
+ case JTAG_STATE_IDLE:
+ /* to Exit2 IR/DR->Updt IR/DR->IDLE */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_idle,
+ sizeof(sm_pause_idle));
+ aspeed_jtag->status = JTAG_STATE_IDLE;
+ break;
+ default:
+ break;
+ }
+ break;
+
+ default:
+ dev_err(aspeed_jtag->dev, "aspeed_jtag_run_test_idle error\n");
+ break;
+ }
+
+ /* Stay on IDLE for at least TCK cycle */
+ for (i = 0; i < runtest->tck; i++)
+ aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0);
+}
+
+/**
+ * aspeed_jtag_run_test_idle:
+ * JTAG reset: generates at least 9 TMS high and 1 TMS low to force
+ * devices into Run-Test/Idle State.
+ */
+static int aspeed_jtag_idle(struct jtag *jtag,
+ struct jtag_run_test_idle *runtest)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ dev_dbg(aspeed_jtag->dev, "aspeed_jtag runtest, status:%d, mode:%s, state:%s, reset:%d, tck:%d\n",
+ aspeed_jtag->status,
+ aspeed_jtag->mode & JTAG_XFER_HW_MODE ? "HW" : "SW",
+ end_status_str[runtest->endstate], runtest->reset,
+ runtest->tck);
+
+ if (!(aspeed_jtag->mode & JTAG_XFER_HW_MODE)) {
+ aspeed_jtag_run_test_idle_sw(aspeed_jtag, runtest);
+ return 0;
+ }
+
+ /* Disable sw mode */
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW);
+ /* x TMS high + 1 TMS low */
+ if (runtest->reset)
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_CTL_ENG_EN |
+ ASPEED_JTAG_CTL_ENG_OUT_EN |
+ ASPEED_JTAG_CTL_FORCE_TMS, ASPEED_JTAG_CTRL);
+ else
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_EC_GO_IDLE,
+ ASPEED_JTAG_EC);
+
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ ASPEED_JTAG_SW_MODE_TDIO, ASPEED_JTAG_SW);
+
+ aspeed_jtag->status = JTAG_STATE_IDLE;
+ return 0;
+}
+
+static void aspeed_jtag_xfer_sw(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_xfer *xfer, unsigned long *data)
+{
+ unsigned long remain_xfer = xfer->length;
+ unsigned long shift_bits = 0;
+ unsigned long index = 0;
+ unsigned long tdi;
+ char tdo;
+
+ if (xfer->direction == JTAG_READ_XFER)
+ tdi = UINT_MAX;
+ else
+ tdi = data[index];
+
+ while (remain_xfer > 1) {
+ tdo = aspeed_jtag_tck_cycle(aspeed_jtag, 0,
+ tdi & ASPEED_JTAG_DATA_MSB);
+ data[index] |= tdo << (shift_bits %
+ ASPEED_JTAG_DATA_CHUNK_SIZE);
+
+ tdi >>= 1;
+ shift_bits++;
+ remain_xfer--;
+
+ if (shift_bits % ASPEED_JTAG_DATA_CHUNK_SIZE == 0) {
+ dev_dbg(aspeed_jtag->dev, "R/W data[%lu]:%lx\n",
+ index, data[index]);
+
+ tdo = 0;
+ index++;
+
+ if (xfer->direction == JTAG_READ_XFER)
+ tdi = UINT_MAX;
+ else
+ tdi = data[index];
+ }
+ }
+
+ tdo = aspeed_jtag_tck_cycle(aspeed_jtag, 1, tdi & ASPEED_JTAG_DATA_MSB);
+ data[index] |= tdo << (shift_bits % ASPEED_JTAG_DATA_CHUNK_SIZE);
+}
+
+static void aspeed_jtag_xfer_push_data(struct aspeed_jtag *aspeed_jtag,
+ enum jtag_xfer_type type, u32 bits_len)
+{
+ dev_dbg(aspeed_jtag->dev, "shift bits %d\n", bits_len);
+
+ if (type == JTAG_SIR_XFER) {
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_IOUT_LEN(bits_len),
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_DOUT_LEN(bits_len) |
+ ASPEED_JTAG_CTL_INST_EN, ASPEED_JTAG_CTRL);
+ } else {
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_DOUT_LEN(bits_len),
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_DOUT_LEN(bits_len) |
+ ASPEED_JTAG_CTL_DATA_EN, ASPEED_JTAG_CTRL);
+ }
+}
+
+static void aspeed_jtag_xfer_push_data_last(struct aspeed_jtag *aspeed_jtag,
+ enum jtag_xfer_type type,
+ u32 shift_bits,
+ enum jtag_endstate endstate)
+{
+ if (endstate != JTAG_STATE_IDLE) {
+ if (type == JTAG_SIR_XFER) {
+ dev_dbg(aspeed_jtag->dev, "IR Keep Pause\n");
+
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits),
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_INST_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_instruction_pause(aspeed_jtag);
+ } else {
+ dev_dbg(aspeed_jtag->dev, "DR Keep Pause\n");
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_DR_UPDATE,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_DR_UPDATE |
+ ASPEED_JTAG_CTL_DATA_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_data_pause_complete(aspeed_jtag);
+ }
+ } else {
+ if (type == JTAG_SIR_XFER) {
+ dev_dbg(aspeed_jtag->dev, "IR go IDLE\n");
+
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_INST,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_INST |
+ ASPEED_JTAG_CTL_INST_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_instruction_complete(aspeed_jtag);
+ } else {
+ dev_dbg(aspeed_jtag->dev, "DR go IDLE\n");
+
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_DATA,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_DATA |
+ ASPEED_JTAG_CTL_DATA_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_data_complete(aspeed_jtag);
+ }
+ }
+}
+
+static void aspeed_jtag_xfer_hw(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_xfer *xfer, unsigned long *data)
+{
+ unsigned long remain_xfer = xfer->length;
+ unsigned long index = 0;
+ char shift_bits;
+ u32 data_reg;
+
+ data_reg = xfer->type == JTAG_SIR_XFER ?
+ ASPEED_JTAG_INST : ASPEED_JTAG_DATA;
+ while (remain_xfer) {
+ if (xfer->direction == JTAG_WRITE_XFER) {
+ dev_dbg(aspeed_jtag->dev, "W dr->dr_data[%lu]:%lx\n",
+ index, data[index]);
+
+ aspeed_jtag_write(aspeed_jtag, data[index], data_reg);
+ } else {
+ aspeed_jtag_write(aspeed_jtag, 0, data_reg);
+ }
+
+ if (remain_xfer > ASPEED_JTAG_DATA_CHUNK_SIZE) {
+ shift_bits = ASPEED_JTAG_DATA_CHUNK_SIZE;
+
+ /*
+ * Read bytes were not equals to column length
+ * and go to Pause-DR
+ */
+ aspeed_jtag_xfer_push_data(aspeed_jtag, xfer->type,
+ shift_bits);
+ } else {
+ /*
+ * Read bytes equals to column length =>
+ * Update-DR
+ */
+ shift_bits = remain_xfer;
+ aspeed_jtag_xfer_push_data_last(aspeed_jtag, xfer->type,
+ shift_bits,
+ xfer->endstate);
+ }
+
+ if (xfer->direction == JTAG_READ_XFER) {
+ if (shift_bits < ASPEED_JTAG_DATA_CHUNK_SIZE) {
+ data[index] = aspeed_jtag_read(aspeed_jtag,
+ data_reg);
+
+ data[index] >>= ASPEED_JTAG_DATA_CHUNK_SIZE -
+ shift_bits;
+ } else {
+ data[index] = aspeed_jtag_read(aspeed_jtag,
+ data_reg);
+ }
+ dev_dbg(aspeed_jtag->dev, "R dr->dr_data[%lu]:%lx\n",
+ index, data[index]);
+ }
+
+ remain_xfer = remain_xfer - shift_bits;
+ index++;
+ dev_dbg(aspeed_jtag->dev, "remain_xfer %lu\n", remain_xfer);
+ }
+}
+
+static int aspeed_jtag_xfer(struct jtag *jtag, struct jtag_xfer *xfer,
+ u8 *xfer_data)
+{
+ static const u8 sm_update_shiftir[] = {1, 1, 0, 0};
+ static const u8 sm_update_shiftdr[] = {1, 0, 0};
+ static const u8 sm_pause_idle[] = {1, 1, 0};
+ static const u8 sm_pause_update[] = {1, 1};
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+ unsigned long *data = (unsigned long *)xfer_data;
+ unsigned long remain_xfer = xfer->length;
+ unsigned long offset;
+ char dbg_str[256];
+ int pos = 0;
+ int i;
+
+ for (offset = 0, i = 0; offset < xfer->length;
+ offset += ASPEED_JTAG_DATA_CHUNK_SIZE, i++) {
+ pos += snprintf(&dbg_str[pos], sizeof(dbg_str) - pos,
+ "0x%08lx ", data[i]);
+ }
+
+ dev_dbg(aspeed_jtag->dev, "aspeed_jtag %s %s xfer, mode:%s, END:%d, len:%lu, TDI[%s]\n",
+ xfer->type == JTAG_SIR_XFER ? "SIR" : "SDR",
+ xfer->direction == JTAG_READ_XFER ? "READ" : "WRITE",
+ aspeed_jtag->mode & JTAG_XFER_HW_MODE ? "HW" : "SW",
+ xfer->endstate, remain_xfer, dbg_str);
+
+ if (!(aspeed_jtag->mode & JTAG_XFER_HW_MODE)) {
+ /* SW mode */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ ASPEED_JTAG_SW_MODE_TDIO, ASPEED_JTAG_SW);
+
+ if (aspeed_jtag->status != JTAG_STATE_IDLE) {
+ /*IR/DR Pause->Exit2 IR / DR->Update IR /DR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_update,
+ sizeof(sm_pause_update));
+ }
+
+ if (xfer->type == JTAG_SIR_XFER)
+ /* ->IRSCan->CapIR->ShiftIR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_update_shiftir,
+ sizeof(sm_update_shiftir));
+ else
+ /* ->DRScan->DRCap->DRShift */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_update_shiftdr,
+ sizeof(sm_update_shiftdr));
+
+ aspeed_jtag_xfer_sw(aspeed_jtag, xfer, data);
+
+ /* DIPause/DRPause */
+ aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0);
+
+ if (xfer->endstate == JTAG_STATE_IDLE) {
+ /* ->DRExit2->DRUpdate->IDLE */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_idle,
+ sizeof(sm_pause_idle));
+ }
+ } else {
+ /* hw mode */
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW);
+ aspeed_jtag_xfer_hw(aspeed_jtag, xfer, data);
+ }
+
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ ASPEED_JTAG_SW_MODE_TDIO, ASPEED_JTAG_SW);
+ aspeed_jtag->status = xfer->endstate;
+ return 0;
+}
+
+static int aspeed_jtag_status_get(struct jtag *jtag, u32 *status)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ *status = aspeed_jtag->status;
+ return 0;
+}
+
+static irqreturn_t aspeed_jtag_interrupt(s32 this_irq, void *dev_id)
+{
+ struct aspeed_jtag *aspeed_jtag = dev_id;
+ irqreturn_t ret;
+ u32 status;
+
+ status = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_ISR);
+ dev_dbg(aspeed_jtag->dev, "status %x\n", status);
+
+ if (status & ASPEED_JTAG_ISR_INT_MASK) {
+ aspeed_jtag_write(aspeed_jtag,
+ (status & ASPEED_JTAG_ISR_INT_MASK)
+ | (status & ASPEED_JTAG_ISR_INT_EN_MASK),
+ ASPEED_JTAG_ISR);
+ aspeed_jtag->flag |= status & ASPEED_JTAG_ISR_INT_MASK;
+ }
+
+ if (aspeed_jtag->flag) {
+ wake_up_interruptible(&aspeed_jtag->jtag_wq);
+ ret = IRQ_HANDLED;
+ } else {
+ dev_err(aspeed_jtag->dev, "aspeed_jtag irq status:%x\n",
+ status);
+ ret = IRQ_NONE;
+ }
+ return ret;
+}
+
+int aspeed_jtag_init(struct platform_device *pdev,
+ struct aspeed_jtag *aspeed_jtag)
+{
+ struct resource *res;
+ int err;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ aspeed_jtag->reg_base = devm_ioremap_resource(aspeed_jtag->dev, res);
+ if (IS_ERR(aspeed_jtag->reg_base))
+ return -ENOMEM;
+
+ aspeed_jtag->pclk = devm_clk_get(aspeed_jtag->dev, NULL);
+ if (IS_ERR(aspeed_jtag->pclk)) {
+ dev_err(aspeed_jtag->dev, "devm_clk_get failed\n");
+ return PTR_ERR(aspeed_jtag->pclk);
+ }
+
+ clk_prepare_enable(aspeed_jtag->pclk);
+
+ aspeed_jtag->irq = platform_get_irq(pdev, 0);
+ if (aspeed_jtag->irq < 0) {
+ dev_err(aspeed_jtag->dev, "no irq specified\n");
+ err = -ENOENT;
+ goto clk_unprep;
+ }
+
+ /* Enable clock */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_CTL_ENG_EN |
+ ASPEED_JTAG_CTL_ENG_OUT_EN, ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ ASPEED_JTAG_SW_MODE_TDIO, ASPEED_JTAG_SW);
+
+ err = devm_request_irq(aspeed_jtag->dev, aspeed_jtag->irq,
+ aspeed_jtag_interrupt, 0,
+ "aspeed-jtag", aspeed_jtag);
+ if (err) {
+ dev_err(aspeed_jtag->dev, "aspeed_jtag unable to get IRQ");
+ goto clk_unprep;
+ }
+ dev_dbg(&pdev->dev, "aspeed_jtag:IRQ %d.\n", aspeed_jtag->irq);
+
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_ISR_INST_PAUSE |
+ ASPEED_JTAG_ISR_INST_COMPLETE |
+ ASPEED_JTAG_ISR_DATA_PAUSE |
+ ASPEED_JTAG_ISR_DATA_COMPLETE |
+ ASPEED_JTAG_ISR_INST_PAUSE_EN |
+ ASPEED_JTAG_ISR_INST_COMPLETE_EN |
+ ASPEED_JTAG_ISR_DATA_PAUSE_EN |
+ ASPEED_JTAG_ISR_DATA_COMPLETE_EN,
+ ASPEED_JTAG_ISR);
+
+ aspeed_jtag->flag = 0;
+ aspeed_jtag->mode = 0;
+ init_waitqueue_head(&aspeed_jtag->jtag_wq);
+ return 0;
+
+clk_unprep:
+ clk_disable_unprepare(aspeed_jtag->pclk);
+ return err;
+}
+
+int aspeed_jtag_deinit(struct platform_device *pdev,
+ struct aspeed_jtag *aspeed_jtag)
+{
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_ISR);
+ /* Disable clock */
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_CTRL);
+ clk_disable_unprepare(aspeed_jtag->pclk);
+ return 0;
+}
+
+static const struct jtag_ops aspeed_jtag_ops = {
+ .freq_get = aspeed_jtag_freq_get,
+ .freq_set = aspeed_jtag_freq_set,
+ .status_get = aspeed_jtag_status_get,
+ .idle = aspeed_jtag_idle,
+ .xfer = aspeed_jtag_xfer,
+ .mode_set = aspeed_jtag_mode_set
+};
+
+static int aspeed_jtag_probe(struct platform_device *pdev)
+{
+ struct aspeed_jtag *aspeed_jtag;
+ struct jtag *jtag;
+ int err;
+
+ if (!of_device_is_compatible(pdev->dev.of_node, "aspeed,aspeed-jtag"))
+ return -ENOMEM;
+
+ jtag = jtag_alloc(sizeof(*aspeed_jtag), &aspeed_jtag_ops);
+ if (!jtag)
+ return -ENODEV;
+
+ platform_set_drvdata(pdev, jtag);
+ aspeed_jtag = jtag_priv(jtag);
+ aspeed_jtag->dev = &pdev->dev;
+
+ /* Initialize device*/
+ err = aspeed_jtag_init(pdev, aspeed_jtag);
+ if (err)
+ goto err_jtag_init;
+
+ /* Initialize JTAG core structure*/
+ err = jtag_register(jtag);
+ if (err)
+ goto err_jtag_register;
+
+ return 0;
+
+err_jtag_register:
+ aspeed_jtag_deinit(pdev, aspeed_jtag);
+err_jtag_init:
+ jtag_free(jtag);
+ return err;
+}
+
+static int aspeed_jtag_remove(struct platform_device *pdev)
+{
+ struct jtag *jtag;
+
+ jtag = platform_get_drvdata(pdev);
+ aspeed_jtag_deinit(pdev, jtag_priv(jtag));
+ jtag_unregister(jtag);
+ jtag_free(jtag);
+ return 0;
+}
+
+static const struct of_device_id aspeed_jtag_of_match[] = {
+ { .compatible = "aspeed,ast2400-jtag", },
+ { .compatible = "aspeed,ast2500-jtag", },
+ {}
+};
+
+static struct platform_driver aspeed_jtag_driver = {
+ .probe = aspeed_jtag_probe,
+ .remove = aspeed_jtag_remove,
+ .driver = {
+ .name = ASPEED_JTAG_NAME,
+ .of_match_table = aspeed_jtag_of_match,
+ },
+};
+module_platform_driver(aspeed_jtag_driver);
+
+MODULE_AUTHOR("Oleksandr Shamray <oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>");
+MODULE_DESCRIPTION("ASPEED JTAG driver");
+MODULE_LICENSE("GPL v2");
--
1.7.1
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^ permalink raw reply related
* [patch v12 3/4] Documentation: jtag: Add bindings for Aspeed SoC 24xx and 25xx families JTAG master driver
From: Oleksandr Shamray @ 2017-11-14 16:11 UTC (permalink / raw)
To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, arnd-r2nGTMty4D4
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, openbmc-uLR06cmDAlY/bJ5BZ2RsiQ,
joel-U3u1mxZcP9KHXe+LvDLADg, jiri-rHqAuBHg3fBzbRFIqnYvSA,
tklauser-93Khv+1bN0NyDzI6CaY1VQ,
linux-serial-u79uwXL29TY76Z2rM5mHXA, mec-WqBc5aa1uDFeoWH0uzbU5w,
vadimp-VPRAkNaXOzVWk0Htik3J/w,
system-sw-low-level-VPRAkNaXOzVWk0Htik3J/w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
openocd-devel-owner-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
linux-api-u79uwXL29TY76Z2rM5mHXA, davem-fT/PcQaiUtIeIZ0/mPfg9Q,
mchehab-DgEjT+Ai2ygdnm+yROfE0A, Oleksandr Shamray, Jiri Pirko
In-Reply-To: <1510675867-24276-1-git-send-email-oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray <oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
Signed-off-by: Jiri Pirko <jiri-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
v11->v12
v10->v11
v9->v10
v8->v9
v7->v8
Comments pointed by pointed by Joel Stanley <joel.stan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
- Change compatible string to ast2400 and ast2000
V6->v7
Comments pointed by Tobias Klauser <tklauser-93Khv+1bN0NyDzI6CaY1VQ@public.gmane.org>
- Fix spell "Doccumentation" -> "Documentation"
v5->v6
Comments pointed by Tobias Klauser <tklauser-93Khv+1bN0NyDzI6CaY1VQ@public.gmane.org>
- Small nit: s/documentation/Documentation/
v4->v5
V3->v4
Comments pointed by Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
- delete unnecessary "status" and "reg-shift" descriptions in
bndings file
v2->v3
Comments pointed by Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
- split Aspeed jtag driver and binding to sepatrate patches
- delete unnecessary "status" and "reg-shift" descriptions in
bndings file
---
.../devicetree/bindings/jtag/aspeed-jtag.txt | 18 ++++++++++++++++++
1 files changed, 18 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/jtag/aspeed-jtag.txt
diff --git a/Documentation/devicetree/bindings/jtag/aspeed-jtag.txt b/Documentation/devicetree/bindings/jtag/aspeed-jtag.txt
new file mode 100644
index 0000000..8cfc610
--- /dev/null
+++ b/Documentation/devicetree/bindings/jtag/aspeed-jtag.txt
@@ -0,0 +1,18 @@
+Aspeed JTAG driver for ast2400 and ast2500 SoC
+
+Required properties:
+- compatible: Should be one of
+ - "aspeed,ast2400-jtag"
+ - "aspeed,ast2500-jtag"
+- reg contains the offset and length of the JTAG memory
+ region
+- clocks root clock of bus, should reference the APB clock
+- interrupts should contain JTAG controller interrupt
+
+Example:
+jtag: jtag@1e6e4000 {
+ compatible = "aspeed,ast2500-jtag";
+ reg = <0x1e6e4000 0x1c>;
+ clocks = <&clk_apb>;
+ interrupts = <43>;
+};
--
1.7.1
^ permalink raw reply related
* [patch v12 4/4] Documentation: jtag: Add ABI documentation
From: Oleksandr Shamray @ 2017-11-14 16:11 UTC (permalink / raw)
To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, arnd-r2nGTMty4D4
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, openbmc-uLR06cmDAlY/bJ5BZ2RsiQ,
joel-U3u1mxZcP9KHXe+LvDLADg, jiri-rHqAuBHg3fBzbRFIqnYvSA,
tklauser-93Khv+1bN0NyDzI6CaY1VQ,
linux-serial-u79uwXL29TY76Z2rM5mHXA, mec-WqBc5aa1uDFeoWH0uzbU5w,
vadimp-VPRAkNaXOzVWk0Htik3J/w,
system-sw-low-level-VPRAkNaXOzVWk0Htik3J/w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
openocd-devel-owner-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
linux-api-u79uwXL29TY76Z2rM5mHXA, davem-fT/PcQaiUtIeIZ0/mPfg9Q,
mchehab-DgEjT+Ai2ygdnm+yROfE0A, Oleksandr Shamray
In-Reply-To: <1510675867-24276-1-git-send-email-oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray <oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
Acked-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
---
v11->v12
Tobias Klauser <tklauser-93Khv+1bN0NyDzI6CaY1VQ@public.gmane.org>
- rename /Documentation/ABI/testing/jatg-dev -> jtag-dev
- Typo: s/interfase/interface
v10->v11
v9->v10
Fixes added by Oleksandr:
- change jtag-cdev to jtag-dev in documentation
- update Kernel Version and Date in jtag-dev documentation;
v8->v9
v7->v8
v6->v7
Comments pointed by Pavel Machek <pavel-+ZI9xUNit7I@public.gmane.org>
- Added jtag-cdev documentation to Documentation/ABI/testing folder
---
Documentation/ABI/testing/jtag-dev | 27 +++++++++++++++++++++++++++
1 files changed, 27 insertions(+), 0 deletions(-)
create mode 100644 Documentation/ABI/testing/jtag-dev
diff --git a/Documentation/ABI/testing/jtag-dev b/Documentation/ABI/testing/jtag-dev
new file mode 100644
index 0000000..cab867d
--- /dev/null
+++ b/Documentation/ABI/testing/jtag-dev
@@ -0,0 +1,27 @@
+What: /dev/jtag[0-9]+
+Date: October 2017
+KernelVersion: 4.15
+Contact: oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org
+Description:
+ The misc device files /dev/jtag* are the interface
+ between JTAG master interface and userspace.
+
+ The ioctl(2)-based ABI is defined and documented in
+ [include/uapi]<linux/jtag.h>.
+
+ The following file operations are supported:
+
+ open(2)
+ The argument flag currently support only one access
+ mode O_RDWR.
+
+ ioctl(2)
+ Initiate various actions.
+ See the inline documentation in [include/uapi]<linux/jtag.h>
+ for descriptions of all ioctls.
+
+ close(2)
+ Stops and free up the I/O contexts that was associated
+ with the file descriptor.
+
+Users: TBD
\ No newline at end of file
--
1.7.1
^ permalink raw reply related
* Private Investition
From: Khvostova Zhanna @ 2017-11-14 17:17 UTC (permalink / raw)
Diese E-Mail fordert Sie strikt auf, sich für eine große Investition mit
mir zusammenzutun, um weitere Informationen zu erhalten.
Mit freundlichen Grüßen,
Khvostova Zhanna
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