* [PATCH v3 0/3] Qualcomm Light Pulse Generator
From: Bjorn Andersson @ 2017-11-15 7:13 UTC (permalink / raw)
To: Richard Purdie, Jacek Anaszewski, Pavel Machek
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-leds-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA, Fenglin Wu
This series introduces a generic pattern interface in the LED class and
a driver for the Qualcomm Light Pulse Generator.
Bjorn Andersson (3):
leds: core: Introduce generic pattern interface
leds: Add driver for Qualcomm LPG
DT: leds: Add Qualcomm Light Pulse Generator binding
Documentation/ABI/testing/sysfs-class-led | 20 +
.../devicetree/bindings/leds/leds-qcom-lpg.txt | 66 ++
drivers/leds/Kconfig | 7 +
drivers/leds/Makefile | 1 +
drivers/leds/led-class.c | 150 +++
drivers/leds/leds-qcom-lpg.c | 1232 ++++++++++++++++++++
include/linux/leds.h | 21 +
7 files changed, 1497 insertions(+)
create mode 100644 Documentation/devicetree/bindings/leds/leds-qcom-lpg.txt
create mode 100644 drivers/leds/leds-qcom-lpg.c
--
2.15.0
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^ permalink raw reply
* [URGENT PATCH] arm64: dts: uniphier: route on-board device IRQ to GPIO controller for PXs3
From: Masahiro Yamada @ 2017-11-15 4:15 UTC (permalink / raw)
To: arm-DgEjT+Ai2ygdnm+yROfE0A, Olof Johansson, Arnd Bergmann
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Masahiro Yamada, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Will Deacon,
Mark Rutland, Catalin Marinas
Commit 429f203eb712 ("arm64: dts: uniphier: route on-board device IRQ
to GPIO controller") missed to update this DTS. It becames a real
problem when arm and arm64 trees are merged together.
Signed-off-by: Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
---
Arnd, Olof,
I think you are sending pull-requests for v4.15-rc1 shortly.
Can you apply this on top your arm64 tree?
With DT tree merged in Linus' tree today,
I realized my mistake that was hidden before.
arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dtb: Warning (interrupts_property):
interrupts size is (12), expected multiple of 8 in /soc@0/system-bus@58c00000/support-card@1,1f00000/ethernet@0
We do not have much time, so I am sending this patch
instead of a pull-reuqest.
Please pick up.
arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
index dad4743..864feeb 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
@@ -38,7 +38,8 @@
};
ðsc {
- interrupts = <0 52 4>;
+ interrupt-parent = <&gpio>;
+ interrupts = <0 8>;
};
&serial0 {
--
2.7.4
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^ permalink raw reply related
* Re: [PATCH 2/3] arm64: dts: hisilicon: add pinctrl nodes for hi3798cv200-poplar board
From: Shawn Guo @ 2017-11-15 3:22 UTC (permalink / raw)
To: Jiancheng Xue
Cc: xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
project-aspen-dev-QSEj5FYQhm4dnm+yROfE0A,
hermit.wangheming-C8/M+/jPZTeaMJb+Lgu22Q, Younian Wang
In-Reply-To: <1508325728-55823-3-git-send-email-xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
On Wed, Oct 18, 2017 at 07:22:07AM -0400, Jiancheng Xue wrote:
> From: Younian Wang <wangyounian-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
>
> Add pinctrl nodes for hi3798cv200-poplar board
>
> Signed-off-by: Younian Wang <wangyounian-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> Signed-off-by: Jiancheng Xue <xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> ---
> .../boot/dts/hisilicon/hi3798cv200-poplar.dts | 1 +
> arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 71 +++
> arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi | 651 +++++++++++++++++++++
> 3 files changed, 723 insertions(+)
> create mode 100644 arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
> index b914287..6a0b7e9 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
> @@ -11,6 +11,7 @@
>
> #include <dt-bindings/gpio/gpio.h>
> #include "hi3798cv200.dtsi"
> +#include "poplar-pinctrl.dtsi"
>
> / {
> model = "HiSilicon Poplar Development Board";
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
> index 0d11dc7..5a73c68 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
> @@ -106,6 +106,54 @@
> #reset-cells = <2>;
> };
>
> + pmx0: pinconf@8a21000 {
> + compatible = "pinconf-single";
> + reg = <0x8a21000 0x180>;
> + pinctrl-single,register-width = <32>;
> + pinctrl-single,function-mask = <7>;
> + pinctrl-single,gpio-range = <
> + &range 0 8 2 /* GPIO 0 */
> + &range 8 1 0 /* GPIO 1 */
> + &range 9 4 2
> + &range 13 1 0
> + &range 14 1 1
> + &range 15 1 0
> + &range 16 5 0 /* GPIO 2 */
> + &range 21 3 1
> + &range 24 4 1 /* GPIO 3 */
> + &range 28 2 2
> + &range 86 1 1
> + &range 87 1 0
> + &range 30 4 2 /* GPIO 4 */
> + &range 34 3 0
> + &range 37 1 2
> + &range 38 3 2 /* GPIO 6 */
> + &range 41 5 0
> + &range 46 8 1 /* GPIO 7 */
> + &range 54 8 1 /* GPIO 8 */
> + &range 64 7 1 /* GPIO 9 */
> + &range 71 1 0
> + &range 72 6 1 /* GPIO 10 */
> + &range 78 1 0
> + &range 79 1 1
> + &range 80 6 1 /* GPIO 11 */
> + &range 70 2 1
> + &range 88 8 0 /* GPIO 12 */
> + >;
> +
> + range: gpio-range {
> + #pinctrl-single,gpio-range-cells = <3>;
> + };
> + };
> +
> + pmx1: pinconf@8000044 {
> + compatible = "pinctrl-single";
> + reg = <0x8000044 4>;
> + pinctrl-single,register-width = <32>;
> + pinctrl-single,function-mask = <1>;
> + pinctrl-single,bit-per-mux;
> + };
> +
> uart0: serial@8b00000 {
> compatible = "arm,pl011", "arm,primecell";
> reg = <0x8b00000 0x1000>;
> @@ -209,6 +257,7 @@
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + gpio-ranges = <&pmx0 0 0 8>;
> clocks = <&crg HISTB_APB_CLK>;
> clock-names = "apb_pclk";
> status = "disabled";
> @@ -222,6 +271,13 @@
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + gpio-ranges = <
> + &pmx0 0 8 1
> + &pmx0 1 9 4
> + &pmx0 5 13 1
> + &pmx0 6 14 1
> + &pmx0 7 15 1
> + >;
> clocks = <&crg HISTB_APB_CLK>;
> clock-names = "apb_pclk";
> status = "disabled";
> @@ -235,6 +291,7 @@
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
> clocks = <&crg HISTB_APB_CLK>;
> clock-names = "apb_pclk";
> status = "disabled";
> @@ -248,6 +305,12 @@
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + gpio-ranges = <
> + &pmx0 0 24 4
> + &pmx0 4 28 2
> + &pmx0 6 86 1
> + &pmx0 7 87 1
> + >;
> clocks = <&crg HISTB_APB_CLK>;
> clock-names = "apb_pclk";
> status = "disabled";
> @@ -261,6 +324,7 @@
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
> clocks = <&crg HISTB_APB_CLK>;
> clock-names = "apb_pclk";
> status = "disabled";
> @@ -287,6 +351,7 @@
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
> clocks = <&crg HISTB_APB_CLK>;
> clock-names = "apb_pclk";
> status = "disabled";
> @@ -300,6 +365,7 @@
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + gpio-ranges = <&pmx0 0 46 8>;
> clocks = <&crg HISTB_APB_CLK>;
> clock-names = "apb_pclk";
> status = "disabled";
> @@ -313,6 +379,7 @@
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + gpio-ranges = <&pmx0 0 54 8>;
> clocks = <&crg HISTB_APB_CLK>;
> clock-names = "apb_pclk";
> status = "disabled";
> @@ -326,6 +393,7 @@
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
There is one cell number missing from the second phandle. It should be:
<&pmx0 0 64 7 &pmx0 7 71 1>;
Otherwise, we will see following error message in kernel boot log when
this GPIO device gets enabled.
OF: /soc@f0000000/gpio@8b29000: arguments longer than property
> clocks = <&crg HISTB_APB_CLK>;
> clock-names = "apb_pclk";
> status = "disabled";
> @@ -339,6 +407,7 @@
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
> clocks = <&crg HISTB_APB_CLK>;
> clock-names = "apb_pclk";
> status = "disabled";
> @@ -352,6 +421,7 @@
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
> clocks = <&crg HISTB_APB_CLK>;
> clock-names = "apb_pclk";
> status = "disabled";
> @@ -365,6 +435,7 @@
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + gpio-ranges = <&pmx0 0 88 8>;
> clocks = <&crg HISTB_APB_CLK>;
> clock-names = "apb_pclk";
> status = "disabled";
> diff --git a/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi
> new file mode 100644
> index 0000000..5a87a0e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi
> @@ -0,0 +1,651 @@
> +/*
> + * pinctrl dts file for HiSilicon poplar board
> + *
> + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
> + *
> + * Released under the GPLv2 only.
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <dt-bindings/pinctrl/hisi.h>
> +
> +/* value, enable bits, disable bits, mask */
> +#define PINCTRL_PULLDOWN(value, enable, disable, mask) \
> + (value << 13) (enable << 13) (disable << 13) (mask << 13)
> +#define PINCTRL_PULLUP(value, enable, disable, mask) \
> + (value << 12) (enable << 12) (disable << 12) (mask << 12)
> +#define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8)
> +#define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4)
> +#define GPIO5_MUX_CFG(offset, value, bit) (offset) (value << bit) (1 << bit)
> +
> +&pmx0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <
There is an indent issue.
> + &emmc_p1_pmx_cfg
> + &emmc_p2_pmx_cfg
> + &emmc_p3_pmx_cfg
> + &emmc_p4_pmx_cfg
> + &gpu_pmx_cfg
> + &sim0_p1_pmx_cfg
> + &sim0_p2_pmx_cfg
> + &i2c0_pmx_cfg
> + &gpio_pmx_cfg
If we only want to configure mux mode for a GPIO pin, we do not need to
have a pinctrl group for that, as GPIO subsystem will ask PINCTRL to
set up the mux mode for the GPIO pin being requested, just like how
those LED GPIO pins work on Poplar board.
> + &bt_uart2_p1_pmx_cfg
> + &bt_uart2_p2_pmx_cfg
> + &pcm_pmx_cfg
> + &spi0_p1_pmx_cfg
> + &spi0_p2_pmx_cfg
> + &tsi0_p1_pmx_cfg
> + &tsi0_p2_pmx_cfg
> + &tsi0_p3_pmx_cfg
> + &tsi0_p4_pmx_cfg
> + &i2c2_p1_pmx_cfg
> + &i2c2_p2_pmx_cfg
> + &mute_pmx_cfg
> + &spdif_pmx_cfg
> + &rgmii1_p1_pmx_cfg
> + &rgmii1_p2_pmx_cfg
> + &rgmii1_p3_pmx_cfg
> + &sdio0_p1_pmx0_cfg
> + &sdio0_p2_pmx0_cfg
> + &sdio0_p3_pmx0_cfg
IMHO, referencing all these pinctrl groups here is not as good as having
client devices reference their pin groups as needed. These "hog" groups
will always request the pins no matter whether corresponding devices is
enabled or not. With client device referencing the phandle, the pins
will only be requested when the device is enabled and probed
successfully. Also, in that case, we can easily find out which devices
use which pins.
Shawn
> + >;
> +
> + emmc_p1_pmx_cfg: emmc_p1_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x000 MUX_M2
> + 0x004 MUX_M2
> + 0x008 MUX_M2
> + 0x00c MUX_M2
> + 0x010 MUX_M2
> + 0x014 MUX_M2
> + 0x018 MUX_M2
> + 0x01c MUX_M2
> + 0x024 MUX_M2
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(0xb, 0xf)
> + >;
> + };
> +
> + emmc_p2_pmx_cfg: emmc_p2_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x028 MUX_M2
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(0x9, 0xf)
> + >;
> + };
> +
> + emmc_p3_pmx_cfg:emmc_p3_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x02c MUX_M2
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + emmc_p4_pmx_cfg:emmc_p4_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x030 MUX_M2
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(1, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + gpu_pmx_cfg: gpu_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x038 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + sim0_p1_pmx_cfg: sim0_p1_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x054 MUX_M1
> + 0x058 MUX_M1
> + 0x05c MUX_M1
> + 0x064 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + sim0_p2_pmx_cfg: sim0_p2_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x060 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(2, 3)
> + >;
> + };
> +
> + i2c0_pmx_cfg: i2c0_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x068 MUX_M1
> + 0x06c MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + gpio_pmx_cfg: gpio_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x070 MUX_M2
> + 0x074 MUX_M2
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + bt_uart2_p1_pmx_cfg: bt_uart2_p1_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x078 MUX_M2
> + 0x07c MUX_M2
> + 0x080 MUX_M2
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + bt_uart2_p2_pmx_cfg: bt_uart2_p2_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x084 MUX_M2
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(7, 7)
> + >;
> + };
> +
> + pcm_pmx_cfg: pcm_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x094 MUX_M2
> + 0x098 MUX_M2
> + 0x09c MUX_M2
> + 0x0a0 MUX_M2
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(7, 7)
> + >;
> + };
> +
> + spi0_p1_pmx_cfg: spi0_p1_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x0b8 MUX_M1
> + 0x0bc MUX_M1
> + 0x0c0 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(7, 7)
> + >;
> + };
> +
> + spi0_p2_pmx_cfg: spi0_p2_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x0c4 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + tsi0_p1_pmx_cfg: tsi0_p1_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x0c8 MUX_M1
> + 0x0cc MUX_M1
> + 0x0d0 MUX_M1
> + 0x0d8 MUX_M1
> + 0x0dc MUX_M1
> + 0x0e0 MUX_M1
> + 0x0e4 MUX_M1
> + 0x0e8 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + tsi0_p2_pmx_cfg: tsi0_p2_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x0d4 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(7, 7)
> + >;
> + };
> +
> + tsi0_p3_pmx_cfg: tsi0_p3_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x0ec MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(1, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + tsi0_p4_pmx_cfg: tsi0_p4_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x0f0 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(1, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + i2c2_p1_pmx_cfg: i2c2_p1_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x0f4 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(1, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + i2c2_p2_pmx_cfg: i2c2_p2_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x0f8 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(1, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + mute_pmx_cfg: mute_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x100 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(1, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + spdif_pmx_cfg: spdif_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x104 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + rgmii1_p1_pmx_cfg: rgmii1_p1_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x118 MUX_M1
> + 0x11c MUX_M1
> + 0x120 MUX_M1
> + 0x144 MUX_M1
> + 0x148 MUX_M1
> + 0x14c MUX_M1
> + 0x150 MUX_M1
> + 0x154 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + rgmii1_p2_pmx_cfg: rgmii1_p2_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x124 MUX_M1
> + 0x128 MUX_M1
> + 0x12c MUX_M1
> + 0x130 MUX_M1
> + 0x134 MUX_M1
> + 0x13c MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(6, 7)
> + >;
> + };
> +
> + rgmii1_p3_pmx_cfg: rgmii1_p3_pmx_cfg {
> + pinctrl-single,pins = <
> + 0x140 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(7, 7)
> + >;
> + };
> +
> + sdio0_p1_pmx0_cfg: sdio0_p1_pmx0_cfg {
> + pinctrl-single,pins = <
> + 0x158 MUX_M1
> + 0x178 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(3, 3)
> + >;
> + };
> +
> + sdio0_p2_pmx0_cfg: sdio0_p2_pmx0_cfg {
> + pinctrl-single,pins = <
> + 0x160 MUX_M1
> + 0x164 MUX_M1
> + 0x16c MUX_M1
> + 0x170 MUX_M1
> + 0x174 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(5, 7)
> + >;
> + };
> +
> + sdio0_p3_pmx0_cfg: sdio0_p3_pmx0_cfg {
> + pinctrl-single,pins = <
> + 0x168 MUX_M1
> + >;
> + pinctrl-single,bias-pulldown = <
> + PINCTRL_PULLDOWN(0, 1, 0, 1)
> + >;
> + pinctrl-single,bias-pullup = <
> + PINCTRL_PULLUP(0, 1, 0, 1)
> + >;
> + pinctrl-single,slew-rate = <
> + PINCTRL_SLEW_RATE(1, 1)
> + >;
> + pinctrl-single,drive-strength = <
> + PINCTRL_DRV_STRENGTH(0xc, 0xf)
> + >;
> + };
> +};
> +
> +&pmx1{
> + pinctrl-names = "default";
> + pinctrl-0 = <
> + &uart0_pmx
> + &lowspeed_gpio_pmx
> + &bt_led_pmx
> + &user_led_pmx
> + &ir_pmx
> + &stb_key_pmx
> + >;
> +
> + uart0_pmx: uart0_pmx {
> + pinctrl-single,bits = <
> + GPIO5_MUX_CFG(0, 0, 0)
> + GPIO5_MUX_CFG(0, 0, 1)
> + >;
> + };
> +
> + lowspeed_gpio_pmx: lowspeed_gpio_pmx {
> + pinctrl-single,bits = <
> + GPIO5_MUX_CFG(0, 0, 4)
> + >;
> + };
> +
> + bt_led_pmx: bt_led_pmx {
> + pinctrl-single,bits = <
> + GPIO5_MUX_CFG(0, 1, 7)
> + >;
> + };
> +
> + user_led_pmx: user_led_pmx {
> + pinctrl-single,bits = <
> + GPIO5_MUX_CFG(0, 0, 3)
> + GPIO5_MUX_CFG(0, 0, 6)
> + >;
> + };
> +
> + ir_pmx: ir_pmx {
> + pinctrl-single,bits = <
> + GPIO5_MUX_CFG(0, 0, 5)
> + >;
> + };
> +
> + stb_key_pmx:stb_key_pmx {
> + pinctrl-single,bits = <
> + GPIO5_MUX_CFG(0, 0, 2)
> + >;
> + };
> +};
> --
> 2.7.4
>
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^ permalink raw reply
* Re: [PATCH 02/10] drm/sun4i: tcon: Add support for A10 TCON
From: Chen-Yu Tsai @ 2017-11-15 2:37 UTC (permalink / raw)
To: Rob Herring
Cc: Chen-Yu Tsai, Maxime Ripard, David Airlie, Mark Rutland,
Jonathan Liu, dri-devel, linux-arm-kernel, devicetree,
linux-kernel, linux-sunxi
In-Reply-To: <20171024160102.fjonpvkykyijxmow@rob-hp-laptop>
On Wed, Oct 25, 2017 at 12:01 AM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Tue, Oct 17, 2017 at 08:17:59PM +0800, Chen-Yu Tsai wrote:
>> From: Jonathan Liu <net147-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>>
>> The A10 has two TCONs that are similar to the ones found on other SoCs.
>> Like the A31, TCON0 has a register used to mux the TCON outputs to the
>> downstream encoders. The bit fields are slightly different.
>>
>> Signed-off-by: Jonathan Liu <net147-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> [wens-jdAy2FN1RRM@public.gmane.org: Reworked for A10 and fixed up commit message]
>> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
>> ---
>> .../bindings/display/sunxi/sun4i-drm.txt | 1 +
>> drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++-
>> drivers/gpu/drm/sun4i/sun4i_tcon.c | 30 ++++++++++++++++++++++
>> 3 files changed, 33 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> index 46df3b78ae9e..b2c08af73a95 100644
>> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> @@ -86,6 +86,7 @@ The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
>>
>> Required properties:
>> - compatible: value must be either:
>> + * allwinner,sun4i-a10-tcon
>> * allwinner,sun5i-a13-tcon
>> * allwinner,sun6i-a31-tcon
>> * allwinner,sun6i-a31s-tcon
>> diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
>> index b5879d4620d8..b8089ac6feef 100644
>> --- a/drivers/gpu/drm/sun4i/sun4i_drv.c
>> +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
>> @@ -184,7 +184,8 @@ static bool sun4i_drv_node_is_frontend(struct device_node *node)
>>
>> static bool sun4i_drv_node_is_tcon(struct device_node *node)
>> {
>> - return of_device_is_compatible(node, "allwinner,sun5i-a13-tcon") ||
>> + return of_device_is_compatible(node, "allwinner,sun4i-a10-tcon") ||
>> + of_device_is_compatible(node, "allwinner,sun5i-a13-tcon") ||
>
> This would be better written with of_match_node. Since there's already a
> match table in sun4i_tcon.c, it would be better to use it.
Tried this and it looks good. I'll send a patch after the merge window.
ChenYu
> Otherwise,
>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
^ permalink raw reply
* Re: [RESEND PATCH] clk: stm32h7: fix test of clock config
From: Stephen Boyd @ 2017-11-15 1:07 UTC (permalink / raw)
To: gabriel.fernandez
Cc: Rob Herring, Mark Rutland, Russell King, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Nicolas Pitre, Arnd Bergmann,
daniel.thompson, andrea.merello, radoslaw.pietrzyk, devicetree,
linux-arm-kernel, linux-kernel, linux-clk, ludovic.barre,
olivier.bideau, amelie.delaunay, gabriel.fernandez.st
In-Reply-To: <1507705044-30458-1-git-send-email-gabriel.fernandez@st.com>
On 10/11, gabriel.fernandez@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
>
> fix test of composite clock config (bad copy / past)
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> Fixes: 3e4d618b0722 ("clk: stm32h7: Add stm32h743 clock driver")
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH 4/4] arm64: dts: qcom: msm8916: add bindings for i2c1, i2c3, i2c5
From: Damien Riegel @ 2017-11-14 23:13 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andy Gross, David Brown,
Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
kernel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/
In-Reply-To: <20171111075612.GA1236@tuxbook>
On Fri, Nov 10, 2017 at 11:56:12PM -0800, Bjorn Andersson wrote:
> On Thu 09 Nov 09:14 PST 2017, Damien Riegel wrote:
>
> > Hi Bjorn,
> >
> >
> > On Thu, Nov 09, 2017 at 09:00:16AM -0800, Bjorn Andersson wrote:
> > > On Wed 01 Nov 10:53 PDT 2017, Damien Riegel wrote:
> > >
> > > I think it's better to use the word "nodes" (add nodes...)
> >
> > Will reword that.
> >
> > >
> > > > Signed-off-by: Damien Riegel <damien.riegel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org>
> > > > ---
> > > > arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 72 ++++++++++++++++++++++++++++++
> > > > arch/arm64/boot/dts/qcom/msm8916.dtsi | 45 +++++++++++++++++++
> > > > 2 files changed, 117 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
> > > > index c67ad8ed8b60..1cec5b30ed6e 100644
> > > > --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
> > > > +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
> > > > @@ -270,6 +270,30 @@
> > > > };
> > > > };
> > > >
> > > > + i2c1_default: i2c1_default {
> > > > + pinmux {
> > > > + function = "blsp_i2c1";
> > > > + pins = "gpio2", "gpio3";
> > > > + };
> > > > + pinconf {
> > > > + pins = "gpio2", "gpio3";
> > > > + drive-strength = <16>;
> > > > + bias-disable;
> > > > + };
> > >
> > > pinconf is typically board specific, so please leave these out from the
> > > base dtsi.
> >
> > I don't mind dropping that, but pinconf for i2c{2,4,6} is already in
> > msm8916-pins.dtsi, so we should either drop them all, or add pinconf for
> > i2c{1,3,5} for consistency.
>
> You're right, this needs to be consistent. So I would like us to update
> the existing nodes,
>
> > And if I read the pinctrl driver correctly,
> > I2C cannot be routed to other pins, the only properties that users may
> > want to modify are drive-strength and bias. Let me know which option you
> > prefer.
> >
>
> I discussed the matter with my colleagues and we concluded that we want
> to keep the muxing in the platform.dtsi and move the specification of
> the electrical properties (pinconf) to the board.dts(i).
>
> We did discuss having some "default values" in the platform file, but
> pushing these down to the board file gives an indication to others that
> these values are board specific.
Okay that makes sense. I'll work on a patchset to do that.
Regards,
--
Damien
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^ permalink raw reply
* [PATCH v3 8/8] MIPS: BMIPS: Enable PCI
From: Jim Quinlan @ 2017-11-14 22:12 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bjorn Helgaas,
Catalin Marinas, Will Deacon, Rob Herring, Brian Norris,
Russell King, Robin Murphy, Christoph Hellwig, Florian Fainelli,
Jonas Gorski
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Gregory Fong,
Kevin Cernekee, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Ralf Baechle, Jim Quinlan
In-Reply-To: <1510697532-32828-1-git-send-email-jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Adds the Kconfig hooks to enable the Broadcom STB PCIe root complex
driver for Broadcom MIPS systems.
Signed-off-by: Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/mips/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cb7fcc4..83ba54d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -209,6 +209,9 @@ config BMIPS_GENERIC
select BOOT_RAW
select NO_EXCEPT_FILL
select USE_OF
+ select HW_HAS_PCI
+ select PCI_DRIVERS_GENERIC
+ select PCI
select CEVT_R4K
select CSRC_R4K
select SYNC_R4K
--
1.9.0.138.g2de3478
--
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^ permalink raw reply related
* [PATCH v3 7/8] MIPS: BMIPS: Add PCI bindings for 7425, 7435
From: Jim Quinlan @ 2017-11-14 22:12 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bjorn Helgaas,
Catalin Marinas, Will Deacon, Rob Herring, Brian Norris,
Russell King, Robin Murphy, Christoph Hellwig, Florian Fainelli,
Jonas Gorski
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Gregory Fong,
Kevin Cernekee, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Ralf Baechle, Jim Quinlan
In-Reply-To: <1510697532-32828-1-git-send-email-jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Adds the PCIe nodes for the Broadcom STB PCIe root complex.
Signed-off-by: Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/mips/boot/dts/brcm/bcm7425.dtsi | 26 ++++++++++++++++++++++++++
arch/mips/boot/dts/brcm/bcm7435.dtsi | 27 +++++++++++++++++++++++++++
arch/mips/boot/dts/brcm/bcm97425svmb.dts | 4 ++++
arch/mips/boot/dts/brcm/bcm97435svmb.dts | 4 ++++
4 files changed, 61 insertions(+)
diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
index f56fb25..c7bd88b 100644
--- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -494,4 +494,30 @@
status = "disabled";
};
};
+
+ pcie: pcie@10410000 {
+ reg = <0x10410000 0x830c>;
+ compatible = "brcm,bcm7425-pcie";
+ interrupts = <37>, <37>;
+ interrupt-names = "pcie", "msi";
+ interrupt-parent = <&periph_intc>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ linux,pci-domain = <0>;
+ brcm,enable-ssc;
+ bus-range = <0x00 0xff>;
+ msi-controller;
+ #interrupt-cells = <1>;
+ /* 4x128mb windows */
+ ranges = <0x2000000 0x0 0xd0000000 0xd0000000 0 0x08000000>,
+ <0x2000000 0x0 0xd8000000 0xd8000000 0 0x08000000>,
+ <0x2000000 0x0 0xe0000000 0xe0000000 0 0x08000000>,
+ <0x2000000 0x0 0xe8000000 0xe8000000 0 0x08000000>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &periph_intc 33
+ 0 0 0 2 &periph_intc 34
+ 0 0 0 3 &periph_intc 35
+ 0 0 0 4 &periph_intc 36>;
+ };
+
};
diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi
index f2cead2..d321042 100644
--- a/arch/mips/boot/dts/brcm/bcm7435.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -509,4 +509,31 @@
status = "disabled";
};
};
+
+ pcie: pcie@10410000 {
+ reg = <0x10410000 0x930c>;
+ interrupts = <0x27>, <0x27>;
+ interrupt-names = "pcie", "msi";
+ interrupt-parent = <&periph_intc>;
+ compatible = "brcm,bcm7435-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ linux,pci-domain = <0>;
+ brcm,enable-ssc;
+ bus-range = <0x00 0xff>;
+ msi-controller;
+ #interrupt-cells = <1>;
+ /* 4x128mb windows */
+ ranges = <0x2000000 0x0 0xd0000000 0xd0000000 0 0x08000000>,
+ <0x2000000 0x0 0xd8000000 0xd8000000 0 0x08000000>,
+ <0x2000000 0x0 0xe0000000 0xe0000000 0 0x08000000>,
+ <0x2000000 0x0 0xe8000000 0xe8000000 0 0x08000000>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &periph_intc 35
+ 0 0 0 2 &periph_intc 36
+ 0 0 0 3 &periph_intc 37
+ 0 0 0 4 &periph_intc 38>;
+ status = "disabled";
+ };
+
};
diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
index 73aa006..3a87ac5 100644
--- a/arch/mips/boot/dts/brcm/bcm97425svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
@@ -143,3 +143,7 @@
&mspi {
status = "okay";
};
+
+&pcie {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97435svmb.dts b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
index 0a915f3..456d024 100644
--- a/arch/mips/boot/dts/brcm/bcm97435svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
@@ -119,3 +119,7 @@
&mspi {
status = "okay";
};
+
+&pcie {
+ status = "okay";
+};
--
1.9.0.138.g2de3478
--
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^ permalink raw reply related
* [PATCH v3 6/8] PCI: brcmstb: Add MSI capability
From: Jim Quinlan @ 2017-11-14 22:12 UTC (permalink / raw)
To: linux-kernel, Bjorn Helgaas, Catalin Marinas, Will Deacon,
Rob Herring, Brian Norris, Russell King, Robin Murphy,
Christoph Hellwig, Florian Fainelli, Jonas Gorski
Cc: linux-pci, bcm-kernel-feedback-list, Gregory Fong, Kevin Cernekee,
Mark Rutland, devicetree, linux-arm-kernel, linux-mips,
Ralf Baechle, Jim Quinlan
In-Reply-To: <1510697532-32828-1-git-send-email-jim2101024@gmail.com>
This commit adds MSI to the Broadcom STB PCIe host controller. It does
not add MSIX since that functionality is not in the HW. The MSI
controller is physically located within the PCIe block, however, there
is no reason why the MSI controller could not be moved elsewhere in
the future.
Since the internal Brcmstb MSI controller is intertwined with the PCIe
controller, it is not its own platform device but rather part of the
PCIe platform device.
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
drivers/pci/host/pcie-brcmstb.c | 372 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 359 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/host/pcie-brcmstb.c b/drivers/pci/host/pcie-brcmstb.c
index 5f4c6aa..89bad31 100644
--- a/drivers/pci/host/pcie-brcmstb.c
+++ b/drivers/pci/host/pcie-brcmstb.c
@@ -11,6 +11,7 @@
* GNU General Public License for more details.
*/
+#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/compiler.h>
#include <linux/delay.h>
@@ -18,15 +19,16 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/log2.h>
#include <linux/module.h>
+#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
-#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/pci.h>
#include <linux/printk.h>
@@ -56,6 +58,9 @@
#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
+#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
+#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
+#define PCIE_MISC_MSI_DATA_CONFIG 0x404c
#define PCIE_MISC_PCIE_CTRL 0x4064
#define PCIE_MISC_PCIE_STATUS 0x4068
#define PCIE_MISC_REVISION 0x406c
@@ -64,6 +69,7 @@
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
#define PCIE_INTR2_CPU_BASE 0x4300
+#define PCIE_MSI_INTR2_BASE 0x4500
/*
* Broadcom Settop Box PCIE Register Field shift and mask info. The
@@ -124,6 +130,8 @@
#define BRCM_NUM_PCIE_OUT_WINS 0x4
#define BRCM_MAX_SCB 0x4
+#define BRCM_INT_PCI_MSI_NR 32
+#define BRCM_PCIE_HW_REV_33 0x0303
#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
@@ -212,6 +220,30 @@ struct brcm_window {
dma_addr_t size;
};
+struct brcm_msi {
+ struct irq_domain *msi_domain;
+ struct irq_domain *inner_domain;
+ struct mutex lock; /* guards the alloc/free operations */
+ u64 target_addr;
+ int irq;
+ /* intr_base is the base pointer for interrupt status/set/clr regs */
+ void __iomem *intr_base;
+ /* intr_legacy_mask indicates how many bits are MSI interrupts */
+ u32 intr_legacy_mask;
+ /*
+ * intr_legacy_offset indicates bit position of MSI_01. It is
+ * to map the register bit position to a hwirq that starts at 0.
+ */
+ u32 intr_legacy_offset;
+ /* used indicates which MSI interrupts have been alloc'd */
+ unsigned long used;
+
+ void __iomem *base;
+ struct device *dev;
+ struct device_node *dn;
+ unsigned int rev;
+};
+
/* Internal PCIe Host Controller Information.*/
struct brcm_pcie {
struct list_head list;
@@ -227,7 +259,10 @@ struct brcm_pcie {
int num_out_wins;
bool ssc;
int gen;
+ u64 msi_target_addr;
struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
+ struct brcm_msi *msi;
+ bool msi_internal;
unsigned int rev;
const int *reg_offsets;
const int *reg_field_info;
@@ -240,6 +275,13 @@ struct pcie_cfg_data {
const enum pcie_type type;
};
+struct brcm_info {
+ int rev;
+ u64 msi_target_addr;
+ void __iomem *base;
+ struct brcm_msi *msi;
+};
+
static const int pcie_reg_field_info[] = {
[RGR1_SW_INIT_1_INIT_MASK] = 0x2,
[RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
@@ -546,6 +588,264 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
}
}
+static struct irq_chip brcm_msi_irq_chip = {
+ .name = "Brcm_MSI",
+ .irq_mask = pci_msi_mask_irq,
+ .irq_unmask = pci_msi_unmask_irq,
+};
+
+static struct msi_domain_info brcm_msi_domain_info = {
+ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+ MSI_FLAG_PCI_MSIX),
+ .chip = &brcm_msi_irq_chip,
+};
+
+static void brcm_pcie_msi_isr(struct irq_desc *desc)
+{
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct brcm_msi *msi;
+ unsigned long status, virq;
+ u32 mask, bit, hwirq;
+ struct device *dev;
+
+ chained_irq_enter(chip, desc);
+ msi = irq_desc_get_handler_data(desc);
+ mask = msi->intr_legacy_mask;
+ dev = msi->dev;
+
+ while ((status = bcm_readl(msi->intr_base + STATUS) & mask)) {
+ for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) {
+ /* clear the interrupt */
+ bcm_writel(1 << bit, msi->intr_base + CLR);
+
+ /* Account for legacy interrupt offset */
+ hwirq = bit - msi->intr_legacy_offset;
+
+ virq = irq_find_mapping(msi->inner_domain, hwirq);
+ if (virq) {
+ if (msi->used & (1 << hwirq))
+ generic_handle_irq(virq);
+ else
+ dev_info(dev, "unhandled MSI %d\n",
+ hwirq);
+ } else {
+ /* Unknown MSI, just clear it */
+ dev_dbg(dev, "unexpected MSI\n");
+ }
+ }
+ }
+ chained_irq_exit(chip, desc);
+}
+
+static void brcm_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+ struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
+ u32 temp;
+
+ msg->address_lo = lower_32_bits(msi->target_addr);
+ msg->address_hi = upper_32_bits(msi->target_addr);
+ temp = bcm_readl(msi->base + PCIE_MISC_MSI_DATA_CONFIG);
+ msg->data = ((temp >> 16) & (temp & 0xffff)) | data->hwirq;
+}
+
+static int brcm_msi_set_affinity(struct irq_data *irq_data,
+ const struct cpumask *mask, bool force)
+{
+ return -EINVAL;
+}
+
+static struct irq_chip brcm_msi_bottom_irq_chip = {
+ .name = "Brcm_MSI",
+ .irq_compose_msi_msg = brcm_compose_msi_msg,
+ .irq_set_affinity = brcm_msi_set_affinity,
+};
+
+static int brcm_msi_alloc(struct brcm_msi *msi)
+{
+ int bit, hwirq;
+
+ mutex_lock(&msi->lock);
+ bit = ~msi->used ? ffz(msi->used) : -1;
+
+ if (bit >= 0 && bit < BRCM_INT_PCI_MSI_NR) {
+ msi->used |= (1 << bit);
+ hwirq = bit - msi->intr_legacy_offset;
+ } else {
+ hwirq = -ENOSPC;
+ }
+
+ mutex_unlock(&msi->lock);
+ return hwirq;
+}
+
+static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
+{
+ mutex_lock(&msi->lock);
+ msi->used &= ~(1 << (hwirq + msi->intr_legacy_offset));
+ mutex_unlock(&msi->lock);
+}
+
+static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *args)
+{
+ struct brcm_msi *msi = domain->host_data;
+ int hwirq;
+
+ hwirq = brcm_msi_alloc(msi);
+
+ if (hwirq < 0)
+ return hwirq;
+
+ irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
+ &brcm_msi_bottom_irq_chip, domain->host_data,
+ handle_simple_irq, NULL, NULL);
+ return 0;
+}
+
+static void brcm_irq_domain_free(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs)
+{
+ struct irq_data *d = irq_domain_get_irq_data(domain, virq);
+ struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
+
+ brcm_msi_free(msi, d->hwirq);
+}
+
+void brcm_msi_set_regs(struct brcm_msi *msi)
+{
+ u32 data_val, msi_lo, msi_hi;
+
+ if (msi->rev >= BRCM_PCIE_HW_REV_33) {
+ /*
+ * ffe0 -- least sig 5 bits are 0 indicating 32 msgs
+ * 6540 -- this is our arbitrary unique data value
+ */
+ data_val = 0xffe06540;
+ } else {
+ /*
+ * fff8 -- least sig 3 bits are 0 indicating 8 msgs
+ * 6540 -- this is our arbitrary unique data value
+ */
+ data_val = 0xfff86540;
+ }
+
+ /*
+ * Make sure we are not masking MSIs. Note that MSIs can be masked,
+ * but that occurs on the PCIe EP device
+ */
+ bcm_writel(0xffffffff & msi->intr_legacy_mask,
+ msi->intr_base + MASK_CLR);
+
+ msi_lo = lower_32_bits(msi->target_addr);
+ msi_hi = upper_32_bits(msi->target_addr);
+ /*
+ * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
+ * enable, which we set to 1.
+ */
+ bcm_writel(msi_lo | 1, msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
+ bcm_writel(msi_hi, msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
+ bcm_writel(data_val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
+}
+
+static const struct irq_domain_ops msi_domain_ops = {
+ .alloc = brcm_irq_domain_alloc,
+ .free = brcm_irq_domain_free,
+};
+
+static int brcm_allocate_domains(struct brcm_msi *msi)
+{
+ struct fwnode_handle *fwnode = of_node_to_fwnode(msi->dn);
+ struct device *dev = msi->dev;
+
+ msi->inner_domain = irq_domain_add_linear(NULL, BRCM_INT_PCI_MSI_NR,
+ &msi_domain_ops, msi);
+ if (!msi->inner_domain) {
+ dev_err(dev, "failed to create IRQ domain\n");
+ return -ENOMEM;
+ }
+
+ msi->msi_domain = pci_msi_create_irq_domain(fwnode,
+ &brcm_msi_domain_info,
+ msi->inner_domain);
+ if (!msi->msi_domain) {
+ dev_err(dev, "failed to create MSI domain\n");
+ irq_domain_remove(msi->inner_domain);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static void brcm_free_domains(struct brcm_msi *msi)
+{
+ irq_domain_remove(msi->msi_domain);
+ irq_domain_remove(msi->inner_domain);
+}
+
+void brcm_msi_remove(struct brcm_msi *msi)
+{
+ if (!msi)
+ return;
+ irq_set_chained_handler(msi->irq, NULL);
+ irq_set_handler_data(msi->irq, NULL);
+ brcm_free_domains(msi);
+}
+
+int brcm_msi_probe(struct platform_device *pdev, struct brcm_info *info)
+{
+ struct brcm_msi *msi;
+ int irq, ret;
+
+ irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
+ if (irq <= 0) {
+ dev_err(&pdev->dev, "cannot map msi intr\n");
+ return -ENODEV;
+ }
+
+ msi = devm_kzalloc(&pdev->dev, sizeof(struct brcm_msi), GFP_KERNEL);
+ if (!msi)
+ return -ENOMEM;
+
+ msi->dev = &pdev->dev;
+ msi->base = info->base;
+ msi->rev = info->rev;
+ msi->dn = pdev->dev.of_node;
+ msi->target_addr = info->msi_target_addr;
+ msi->irq = irq;
+
+ ret = brcm_allocate_domains(msi);
+ if (ret)
+ return ret;
+
+ irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
+
+ if (msi->rev >= BRCM_PCIE_HW_REV_33) {
+ msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
+ /*
+ * This version of PCIe hw has only 32 intr bits
+ * starting at bit position 0.
+ */
+ msi->intr_legacy_mask = 0xffffffff;
+ msi->intr_legacy_offset = 0x0;
+ msi->used = 0x0;
+
+ } else {
+ msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
+ /*
+ * This version of PCIe hw has only 8 intr bits starting
+ * at bit position 24.
+ */
+ msi->intr_legacy_mask = 0xff000000;
+ msi->intr_legacy_offset = 24;
+ msi->used = 0x00ffffff;
+ }
+
+ brcm_msi_set_regs(msi);
+ info->msi = msi;
+
+ return 0;
+}
+
/* Configuration space read/write support */
static int cfg_index(int busnr, int devfn, int reg)
{
@@ -812,6 +1112,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
int i, j, ret, limit;
u16 nlw, cls, lnksta;
bool ssc_good = false;
+ u64 msi_target_addr;
/* reset the bridge and the endpoint device */
/* field: PCIE_BRIDGE_SW_INIT = 1 */
@@ -855,14 +1156,17 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
* The PCIe host controller by design must set the inbound
* viewport to be a contiguous arrangement of all of the
* system's memory. In addition, its size mut be a power of
- * two. To further complicate matters, the viewport must
- * start on a pcie-address that is aligned on a multiple of its
- * size. If a portion of the viewport does not represent
- * system memory -- e.g. 3GB of memory requires a 4GB viewport
- * -- we can map the outbound memory in or after 3GB and even
- * though the viewport will overlap the outbound memory the
- * controller will know to send outbound memory downstream and
- * everything else upstream.
+ * two. Further, the MSI target address must NOT be placed
+ * inside this region, as the decoding logic will consider its
+ * address to be inbound memory traffic. To further
+ * complicate matters, the viewport must start on a
+ * pcie-address that is aligned on a multiple of its size.
+ * If a portion of the viewport does not represent system
+ * memory -- e.g. 3GB of memory requires a 4GB viewport --
+ * we can map the outbound memory in or after 3GB and even
+ * though the viewport will overlap the outbound memory
+ * the controller will know to send outbound memory downstream
+ * and everything else upstream.
*/
rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
@@ -875,7 +1179,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
if (dma_ranges) {
/*
* The best-case scenario is to place the inbound
- * region in the first 4GB of pci-space, as some
+ * region in the first 4GB of pcie-space, as some
* legacy devices can only address 32bits.
* We would also like to put the MSI under 4GB
* as well, since some devices require a 32bit
@@ -884,6 +1188,14 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
if (total_mem_size <= 0xc0000000ULL &&
rc_bar2_size <= 0x100000000ULL) {
rc_bar2_offset = 0;
+ /* If the viewport is less then 4GB we can fit
+ * the MSI target address under 4GB. Otherwise
+ * put it right below 64GB.
+ */
+ msi_target_addr =
+ (rc_bar2_size == 0x100000000ULL)
+ ? BRCM_MSI_TARGET_ADDR_GT_4GB
+ : BRCM_MSI_TARGET_ADDR_LT_4GB;
} else {
/*
* The system memory is 4GB or larger so we
@@ -893,8 +1205,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
* start it at the 1x multiple of its size
*/
rc_bar2_offset = rc_bar2_size;
- }
+ /* Since we are starting the viewport at 4GB or
+ * higher, put the MSI target address below 4GB
+ */
+ msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
+ }
} else {
/*
* Set simple configuration based on memory sizes
@@ -902,7 +1218,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
* and set the MSI target address accordingly.
*/
rc_bar2_offset = 0;
+
+ msi_target_addr = (rc_bar2_size >= 0x100000000ULL)
+ ? BRCM_MSI_TARGET_ADDR_GT_4GB
+ : BRCM_MSI_TARGET_ADDR_LT_4GB;
}
+ pcie->msi_target_addr = msi_target_addr;
tmp = lower_32_bits(rc_bar2_offset);
tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
@@ -1076,6 +1397,9 @@ static int brcm_pcie_resume(struct device *dev)
if (ret)
return ret;
+ if (pcie->msi && pcie->msi_internal)
+ brcm_msi_set_regs(pcie->msi);
+
pcie->suspended = false;
return 0;
@@ -1083,6 +1407,7 @@ static int brcm_pcie_resume(struct device *dev)
static void _brcm_pcie_remove(struct brcm_pcie *pcie)
{
+ brcm_msi_remove(pcie->msi);
turn_off(pcie);
clk_disable_unprepare(pcie->clk);
clk_put(pcie->clk);
@@ -1111,7 +1436,7 @@ static int brcm_pcie_remove(struct platform_device *pdev)
static int brcm_pcie_probe(struct platform_device *pdev)
{
- struct device_node *dn = pdev->dev.of_node;
+ struct device_node *dn = pdev->dev.of_node, *msi_dn;
const struct of_device_id *of_id;
const struct pcie_cfg_data *data;
int ret;
@@ -1194,6 +1519,28 @@ static int brcm_pcie_probe(struct platform_device *pdev)
if (ret)
goto fail;
+ msi_dn = of_parse_phandle(pcie->dn, "msi-parent", 0);
+ /* Use the internal MSI if no msi-parent property */
+ if (!msi_dn)
+ msi_dn = pcie->dn;
+
+ if (pci_msi_enabled() && msi_dn == pcie->dn) {
+ struct brcm_info info;
+
+ info.rev = pcie->rev;
+ info.msi_target_addr = pcie->msi_target_addr;
+ info.base = pcie->base;
+
+ ret = brcm_msi_probe(pdev, &info);
+ if (ret)
+ dev_err(pcie->dev,
+ "probe of internal MSI failed: %d)", ret);
+ else
+ pcie->msi_internal = true;
+
+ pcie->msi = info.msi;
+ }
+
list_splice_init(&pcie->resources, &bridge->windows);
bridge->dev.parent = &pdev->dev;
bridge->busnr = 0;
@@ -1216,7 +1563,6 @@ static int brcm_pcie_probe(struct platform_device *pdev)
pcie->root_bus = bridge->bus;
return 0;
-
fail:
_brcm_pcie_remove(pcie);
return ret;
--
1.9.0.138.g2de3478
^ permalink raw reply related
* [PATCH v3 5/8] PCI/MSI: Enable PCI_MSI_IRQ_DOMAIN support for MIPS
From: Jim Quinlan @ 2017-11-14 22:12 UTC (permalink / raw)
To: linux-kernel, Bjorn Helgaas, Catalin Marinas, Will Deacon,
Rob Herring, Brian Norris, Russell King, Robin Murphy,
Christoph Hellwig, Florian Fainelli, Jonas Gorski
Cc: linux-pci, bcm-kernel-feedback-list, Gregory Fong, Kevin Cernekee,
Mark Rutland, devicetree, linux-arm-kernel, linux-mips,
Ralf Baechle, Jim Quinlan
In-Reply-To: <1510697532-32828-1-git-send-email-jim2101024@gmail.com>
Add MIPS as an arch that supports PCI_MSI_IRQ_DOMAIN and add
generation of msi.h in the MIPS arch.
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
arch/mips/include/asm/Kbuild | 1 +
drivers/pci/Kconfig | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 7c8aab2..8c78ba7 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -9,6 +9,7 @@ generic-y += irq_work.h
generic-y += local64.h
generic-y += mcs_spinlock.h
generic-y += mm-arch-hooks.h
+generic-y += msi.h
generic-y += parport.h
generic-y += percpu.h
generic-y += preempt.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index c32a77f..927c335 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -25,7 +25,7 @@ config PCI_MSI
If you don't know what to do here, say Y.
config PCI_MSI_IRQ_DOMAIN
- def_bool ARC || ARM || ARM64 || X86
+ def_bool ARC || ARM || ARM64 || MIPS || X86
depends on PCI_MSI
select GENERIC_MSI_IRQ_DOMAIN
--
1.9.0.138.g2de3478
^ permalink raw reply related
* [PATCH v3 4/8] PCI: brcmstb: Add dma-range mapping for inbound traffic
From: Jim Quinlan @ 2017-11-14 22:12 UTC (permalink / raw)
To: linux-kernel, Bjorn Helgaas, Catalin Marinas, Will Deacon,
Rob Herring, Brian Norris, Russell King, Robin Murphy,
Christoph Hellwig, Florian Fainelli, Jonas Gorski
Cc: linux-pci, bcm-kernel-feedback-list, Gregory Fong, Kevin Cernekee,
Mark Rutland, devicetree, linux-arm-kernel, linux-mips,
Ralf Baechle, Jim Quinlan
In-Reply-To: <1510697532-32828-1-git-send-email-jim2101024@gmail.com>
The Broadcom STB PCIe host controller is intimately related to the
memory subsystem. This close relationship adds complexity to how cpu
system memory is mapped to PCIe memory. Ideally, this mapping is an
identity mapping, or an identity mapping off by a constant. Not so in
this case.
Consider the Broadcom reference board BCM97445LCC_4X8 which has 6 GB
of system memory. Here is how the PCIe controller maps the
system memory to PCIe memory:
memc0-a@[ 0....3fffffff] <=> pci@[ 0....3fffffff]
memc0-b@[100000000...13fffffff] <=> pci@[ 40000000....7fffffff]
memc1-a@[ 40000000....7fffffff] <=> pci@[ 80000000....bfffffff]
memc1-b@[300000000...33fffffff] <=> pci@[ c0000000....ffffffff]
memc2-a@[ 80000000....bfffffff] <=> pci@[100000000...13fffffff]
memc2-b@[c00000000...c3fffffff] <=> pci@[140000000...17fffffff]
Although there are some "gaps" that can be added between the
individual mappings by software, the permutation of memory regions for
the most part is fixed by HW. The solution of having something close
to an identity mapping is not possible.
The idea behind this HW design is that the same PCIe module can
act as an RC or EP, and if it acts as an EP it concatenates all
of system memory into a BAR so anything can be accessed. Unfortunately,
when the PCIe block is in the role of an RC it also presents this
"BAR" to downstream PCIe devices, rather than offering an identity map
between its system memory and PCIe space.
Suppose that an endpoint driver allocs some DMA memory. Suppose this
memory is located at 0x6000_0000, which is in the middle of memc1-a.
The driver wants a dma_addr_t value that it can pass on to the EP to
use. Without doing any custom mapping, the EP will use this value for
DMA: the driver will get a dma_addr_t equal to 0x6000_0000. But this
won't work; the device needs a dma_addr_t that reflects the PCIe space
address, namely 0xa000_0000.
So, essentially the solution to this problem must modify the
dma_addr_t returned by the DMA routines routines. There are two
ways (I know of) of doing this:
(a) overriding/redefining the dma_to_phys() and phys_to_dma() calls
that are used by the dma_ops routines. This is the approach of
arch/mips/cavium-octeon/dma-octeon.c
In ARM and ARM64 these two routines are defiend in asm/dma-mapping.h
as static inline functions.
(b) Subscribe to a notifier that notifies when a device is added to a
bus. When this happens, set_dma_ops() can be called for the device.
This method is mentioned in:
http://lxr.free-electrons.com/source/drivers/of/platform.c?v=3.16#L152
where it says as a comment
"In case if platform code need to use own special DMA
configuration, it can use Platform bus notifier and
handle BUS_NOTIFY_ADD_DEVICE event to fix up DMA
configuration."
Solution (b) is what this commit does. It uses its own set of
dma_ops which are wrappers around the arch_dma_ops. The
wrappers translate the dma addresses before/after invoking
the arch_dma_ops, as appropriate.
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
drivers/pci/host/Makefile | 4 +-
drivers/pci/host/pcie-brcmstb-dma.c | 319 ++++++++++++++++++++++++++++++++++++
drivers/pci/host/pcie-brcmstb.c | 139 +++++++++++++++-
drivers/pci/host/pcie-brcmstb.h | 22 +++
4 files changed, 474 insertions(+), 10 deletions(-)
create mode 100644 drivers/pci/host/pcie-brcmstb-dma.c
create mode 100644 drivers/pci/host/pcie-brcmstb.h
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index a8b9923..6b94c9c 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -21,7 +21,9 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
obj-$(CONFIG_VMD) += vmd.o
-obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
+
+obj-$(CONFIG_PCIE_BRCMSTB) += brcmstb-pcie.o
+brcmstb-pcie-objs := pcie-brcmstb.o pcie-brcmstb-dma.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/host/pcie-brcmstb-dma.c b/drivers/pci/host/pcie-brcmstb-dma.c
new file mode 100644
index 0000000..6c397be
--- /dev/null
+++ b/drivers/pci/host/pcie-brcmstb-dma.c
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2015-2017 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/smp.h>
+
+#include "pcie-brcmstb.h"
+
+static const struct dma_map_ops *arch_dma_ops;
+static const struct dma_map_ops *brcm_dma_ops_ptr;
+
+static dma_addr_t brcm_to_pci(dma_addr_t addr)
+{
+ struct of_pci_range *p;
+
+ if (!num_dma_ranges)
+ return addr;
+
+ for (p = dma_ranges; p < &dma_ranges[num_dma_ranges]; p++)
+ if (addr >= p->cpu_addr && addr < (p->cpu_addr + p->size))
+ return addr - p->cpu_addr + p->pci_addr;
+
+ return addr;
+}
+
+static dma_addr_t brcm_to_cpu(dma_addr_t addr)
+{
+ struct of_pci_range *p;
+
+ if (!num_dma_ranges)
+ return addr;
+
+ for (p = dma_ranges; p < &dma_ranges[num_dma_ranges]; p++)
+ if (addr >= p->pci_addr && addr < (p->pci_addr + p->size))
+ return addr - p->pci_addr + p->cpu_addr;
+
+ return addr;
+}
+
+static void *brcm_alloc(struct device *dev, size_t size, dma_addr_t *handle,
+ gfp_t gfp, unsigned long attrs)
+{
+ void *ret;
+
+ ret = arch_dma_ops->alloc(dev, size, handle, gfp, attrs);
+ if (ret)
+ *handle = brcm_to_pci(*handle);
+ return ret;
+}
+
+static void brcm_free(struct device *dev, size_t size, void *cpu_addr,
+ dma_addr_t handle, unsigned long attrs)
+{
+ handle = brcm_to_cpu(handle);
+ arch_dma_ops->free(dev, size, cpu_addr, handle, attrs);
+}
+
+static int brcm_mmap(struct device *dev, struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t dma_addr, size_t size,
+ unsigned long attrs)
+{
+ dma_addr = brcm_to_cpu(dma_addr);
+ return arch_dma_ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
+}
+
+static int brcm_get_sgtable(struct device *dev, struct sg_table *sgt,
+ void *cpu_addr, dma_addr_t handle, size_t size,
+ unsigned long attrs)
+{
+ handle = brcm_to_cpu(handle);
+ return arch_dma_ops->get_sgtable(dev, sgt, cpu_addr, handle, size,
+ attrs);
+}
+
+static dma_addr_t brcm_map_page(struct device *dev, struct page *page,
+ unsigned long offset, size_t size,
+ enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ return brcm_to_pci(arch_dma_ops->map_page(dev, page, offset, size,
+ dir, attrs));
+}
+
+static void brcm_unmap_page(struct device *dev, dma_addr_t handle,
+ size_t size, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ handle = brcm_to_cpu(handle);
+ arch_dma_ops->unmap_page(dev, handle, size, dir, attrs);
+}
+
+static int brcm_map_sg(struct device *dev, struct scatterlist *sgl,
+ int nents, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ int i, j;
+ struct scatterlist *sg;
+
+ for_each_sg(sgl, sg, nents, i) {
+#ifdef CONFIG_NEED_SG_DMA_LENGTH
+ sg->dma_length = sg->length;
+#endif
+ sg->dma_address =
+ brcm_dma_ops_ptr->map_page(dev, sg_page(sg), sg->offset,
+ sg->length, dir, attrs);
+ if (dma_mapping_error(dev, sg->dma_address))
+ goto bad_mapping;
+ }
+ return nents;
+
+bad_mapping:
+ for_each_sg(sgl, sg, i, j)
+ brcm_dma_ops_ptr->unmap_page(dev, sg_dma_address(sg),
+ sg_dma_len(sg), dir, attrs);
+ return 0;
+}
+
+static void brcm_unmap_sg(struct device *dev,
+ struct scatterlist *sgl, int nents,
+ enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ int i;
+ struct scatterlist *sg;
+
+ for_each_sg(sgl, sg, nents, i)
+ brcm_dma_ops_ptr->unmap_page(dev, sg_dma_address(sg),
+ sg_dma_len(sg), dir, attrs);
+}
+
+static void brcm_sync_single_for_cpu(struct device *dev,
+ dma_addr_t handle, size_t size,
+ enum dma_data_direction dir)
+{
+ handle = brcm_to_cpu(handle);
+ arch_dma_ops->sync_single_for_cpu(dev, handle, size, dir);
+}
+
+static void brcm_sync_single_for_device(struct device *dev,
+ dma_addr_t handle, size_t size,
+ enum dma_data_direction dir)
+{
+ handle = brcm_to_cpu(handle);
+ arch_dma_ops->sync_single_for_device(dev, handle, size, dir);
+}
+
+static dma_addr_t brcm_map_resource(struct device *dev, phys_addr_t phys,
+ size_t size,
+ enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ if (arch_dma_ops->map_resource)
+ return brcm_to_pci(arch_dma_ops->map_resource
+ (dev, phys, size, dir, attrs));
+ return brcm_to_pci((dma_addr_t)phys);
+}
+
+static void brcm_unmap_resource(struct device *dev, dma_addr_t handle,
+ size_t size, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ if (arch_dma_ops->unmap_resource)
+ arch_dma_ops->unmap_resource(dev, brcm_to_cpu(handle), size,
+ dir, attrs);
+}
+
+void brcm_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl,
+ int nents, enum dma_data_direction dir)
+{
+ struct scatterlist *sg;
+ int i;
+
+ for_each_sg(sgl, sg, nents, i)
+ brcm_dma_ops_ptr->sync_single_for_cpu(dev, sg_dma_address(sg),
+ sg->length, dir);
+}
+
+void brcm_sync_sg_for_device(struct device *dev, struct scatterlist *sgl,
+ int nents, enum dma_data_direction dir)
+{
+ struct scatterlist *sg;
+ int i;
+
+ for_each_sg(sgl, sg, nents, i)
+ brcm_dma_ops_ptr->sync_single_for_device(dev,
+ sg_dma_address(sg),
+ sg->length, dir);
+}
+
+static int brcm_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+ return arch_dma_ops->mapping_error(dev, dma_addr);
+}
+
+static int brcm_dma_supported(struct device *dev, u64 mask)
+{
+ if (num_dma_ranges) {
+ /*
+ * It is our translated addresses that the EP will "see", so
+ * we check all of the ranges for the largest possible value.
+ */
+ int i;
+
+ for (i = 0; i < num_dma_ranges; i++)
+ if (dma_ranges[i].pci_addr + dma_ranges[i].size - 1
+ > mask)
+ return 0;
+ return 1;
+ }
+
+ return arch_dma_ops->dma_supported(dev, mask);
+}
+
+#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
+u64 brcm_get_required_mask)(struct device *dev)
+{
+ return arch_dma_ops->get_required_mask(dev);
+}
+#endif
+
+static const struct dma_map_ops brcm_dma_ops = {
+ .alloc = brcm_alloc,
+ .free = brcm_free,
+ .mmap = brcm_mmap,
+ .get_sgtable = brcm_get_sgtable,
+ .map_page = brcm_map_page,
+ .unmap_page = brcm_unmap_page,
+ .map_sg = brcm_map_sg,
+ .unmap_sg = brcm_unmap_sg,
+ .map_resource = brcm_map_resource,
+ .unmap_resource = brcm_unmap_resource,
+ .sync_single_for_cpu = brcm_sync_single_for_cpu,
+ .sync_single_for_device = brcm_sync_single_for_device,
+ .sync_sg_for_cpu = brcm_sync_sg_for_cpu,
+ .sync_sg_for_device = brcm_sync_sg_for_device,
+ .mapping_error = brcm_mapping_error,
+ .dma_supported = brcm_dma_supported,
+#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
+ .get_required_mask = brcm_get_required_mask,
+#endif
+};
+
+static void brcm_set_dma_ops(struct device *dev)
+{
+ int ret;
+
+ if (IS_ENABLED(CONFIG_ARM64)) {
+ /*
+ * We are going to invoke get_dma_ops(). That
+ * function, at this point in time, invokes
+ * get_arch_dma_ops(), and for ARM64 that function
+ * returns a pointer to dummy_dma_ops. So then we'd
+ * like to call arch_setup_dma_ops(), but that isn't
+ * exported. Instead, we call of_dma_configure(),
+ * which is exported, and this calls
+ * arch_setup_dma_ops(). Once we do this the call to
+ * get_dma_ops() will work properly because
+ * dev->dma_ops will be set.
+ */
+ ret = of_dma_configure(dev, dev->of_node);
+ if (ret) {
+ dev_err(dev, "of_dma_configure() failed: %d\n", ret);
+ return;
+ }
+ }
+
+ arch_dma_ops = get_dma_ops(dev);
+ if (!arch_dma_ops) {
+ dev_err(dev, "failed to get arch_dma_ops\n");
+ return;
+ }
+
+ set_dma_ops(dev, &brcm_dma_ops);
+}
+
+static int brcmstb_platform_notifier(struct notifier_block *nb,
+ unsigned long event, void *__dev)
+{
+ struct device *dev = __dev;
+
+ brcm_dma_ops_ptr = &brcm_dma_ops;
+ if (event != BUS_NOTIFY_ADD_DEVICE)
+ return NOTIFY_DONE;
+
+ brcm_set_dma_ops(dev);
+ return NOTIFY_OK;
+}
+
+static struct notifier_block brcmstb_platform_nb = {
+ .notifier_call = brcmstb_platform_notifier,
+};
+
+int brcm_register_notifier(void)
+{
+ return bus_register_notifier(&pci_bus_type, &brcmstb_platform_nb);
+}
+
+int brcm_unregister_notifier(void)
+{
+ return bus_unregister_notifier(&pci_bus_type, &brcmstb_platform_nb);
+}
diff --git a/drivers/pci/host/pcie-brcmstb.c b/drivers/pci/host/pcie-brcmstb.c
index d8a8f7a..5f4c6aa 100644
--- a/drivers/pci/host/pcie-brcmstb.c
+++ b/drivers/pci/host/pcie-brcmstb.c
@@ -35,6 +35,7 @@
#include <soc/brcmstb/memory_api.h>
#include <linux/string.h>
#include <linux/types.h>
+#include "pcie-brcmstb.h"
/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
#define BRCM_PCIE_CAP_REGS 0x00ac
@@ -332,6 +333,10 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
((val & ~reg##_##field##_MASK) | \
(reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
+/* Also used by pci-brcmstb-dma.c */
+struct of_pci_range *dma_ranges;
+int num_dma_ranges;
+
static struct list_head brcm_pcie = LIST_HEAD_INIT(brcm_pcie);
static phys_addr_t scb_size[BRCM_MAX_SCB];
static int num_memc;
@@ -642,25 +647,42 @@ static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
static int brcm_pcie_add_controller(struct brcm_pcie *pcie)
{
+ int ret = 0;
+
mutex_lock(&brcm_pcie_lock);
+ if (list_empty(&brcm_pcie)) {
+ ret = brcm_register_notifier();
+ if (ret) {
+ dev_err(pcie->dev,
+ "failed to register pci bus notifier\n");
+ goto done;
+ }
+ }
list_add_tail(&pcie->list, &brcm_pcie);
+done:
mutex_unlock(&brcm_pcie_lock);
-
- return 0;
+ return ret;
}
static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
{
struct list_head *pos, *q;
struct brcm_pcie *tmp;
+ static const char *err_msg = "failed to unregister pci bus notifier\n";
mutex_lock(&brcm_pcie_lock);
list_for_each_safe(pos, q, &brcm_pcie) {
tmp = list_entry(pos, struct brcm_pcie, list);
if (tmp == pcie) {
list_del(pos);
- if (list_empty(&brcm_pcie))
+ if (list_empty(&brcm_pcie)) {
+ if (brcm_unregister_notifier())
+ dev_err(pcie->dev, err_msg);
+ kfree(dma_ranges);
+ dma_ranges = NULL;
+ num_dma_ranges = 0;
num_memc = 0;
+ }
break;
}
}
@@ -712,6 +734,75 @@ static int brcm_pcie_parse_request_of_pci_ranges(struct brcm_pcie *pcie)
return 0;
}
+static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
+ struct device_node *node)
+{
+ const int na = 3, ns = 2;
+ int rlen;
+
+ parser->node = node;
+ parser->pna = of_n_addr_cells(node);
+ parser->np = parser->pna + na + ns;
+
+ parser->range = of_get_property(node, "dma-ranges", &rlen);
+ if (!parser->range)
+ return -ENOENT;
+
+ parser->end = parser->range + rlen / sizeof(__be32);
+
+ return 0;
+}
+
+static int brcm_pcie_parse_map_dma_ranges(struct brcm_pcie *pcie)
+{
+ int i, ret = 0;
+ struct of_pci_range_parser parser;
+ struct device_node *dn = pcie->dn;
+
+ mutex_lock(&brcm_pcie_lock);
+ if (dma_ranges)
+ goto done;
+
+ /*
+ * Parse dma-ranges property if present. If there are multiple
+ * PCI controllers, we only have to parse from one of them since
+ * the others will have an identical mapping.
+ */
+ if (!pci_dma_range_parser_init(&parser, dn)) {
+ unsigned int max_ranges
+ = (parser.end - parser.range) / parser.np;
+
+ dma_ranges = kcalloc(max_ranges, sizeof(struct of_pci_range),
+ GFP_KERNEL);
+ if (!dma_ranges) {
+ ret = -ENOMEM;
+ goto done;
+ }
+ for (i = 0; of_pci_range_parser_one(&parser, dma_ranges + i);
+ i++)
+ num_dma_ranges++;
+ }
+
+ for (i = 0, num_memc = 0; i < BRCM_MAX_SCB; i++) {
+ u64 size = brcmstb_memory_memc_size(i);
+
+ if (size == (u64)-1) {
+ dev_err(pcie->dev, "cannot get memc%d size", i);
+ ret = -EINVAL;
+ goto done;
+ } else if (size) {
+ scb_size[i] = roundup_pow_of_two_64(size);
+ num_memc++;
+ } else {
+ break;
+ }
+ }
+
+done:
+ mutex_unlock(&brcm_pcie_lock);
+ return ret;
+}
+
static int brcm_pcie_setup(struct brcm_pcie *pcie)
{
void __iomem *base = pcie->base;
@@ -781,6 +872,38 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
*/
rc_bar2_offset = 0;
+ if (dma_ranges) {
+ /*
+ * The best-case scenario is to place the inbound
+ * region in the first 4GB of pci-space, as some
+ * legacy devices can only address 32bits.
+ * We would also like to put the MSI under 4GB
+ * as well, since some devices require a 32bit
+ * MSI target address.
+ */
+ if (total_mem_size <= 0xc0000000ULL &&
+ rc_bar2_size <= 0x100000000ULL) {
+ rc_bar2_offset = 0;
+ } else {
+ /*
+ * The system memory is 4GB or larger so we
+ * cannot start the inbound region at location
+ * 0 (since we have to allow some space for
+ * outbound memory @ 3GB). So instead we
+ * start it at the 1x multiple of its size
+ */
+ rc_bar2_offset = rc_bar2_size;
+ }
+
+ } else {
+ /*
+ * Set simple configuration based on memory sizes
+ * only. We always start the viewport at address 0,
+ * and set the MSI target address accordingly.
+ */
+ rc_bar2_offset = 0;
+ }
+
tmp = lower_32_bits(rc_bar2_offset);
tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
encode_ibar_size(rc_bar2_size));
@@ -995,7 +1118,6 @@ static int brcm_pcie_probe(struct platform_device *pdev)
struct brcm_pcie *pcie;
struct resource *res;
void __iomem *base;
- u32 tmp;
struct pci_host_bridge *bridge;
struct pci_bus *child;
@@ -1012,11 +1134,6 @@ static int brcm_pcie_probe(struct platform_device *pdev)
return -EINVAL;
}
- if (of_property_read_u32(dn, "dma-ranges", &tmp) == 0) {
- dev_err(&pdev->dev, "cannot yet handle dma-ranges\n");
- return -EINVAL;
- }
-
data = of_id->data;
pcie->reg_offsets = data->offsets;
pcie->reg_field_info = data->reg_field_info;
@@ -1059,6 +1176,10 @@ static int brcm_pcie_probe(struct platform_device *pdev)
if (ret)
return ret;
+ ret = brcm_pcie_parse_map_dma_ranges(pcie);
+ if (ret)
+ return ret;
+
ret = clk_prepare_enable(pcie->clk);
if (ret) {
dev_err(&pdev->dev, "could not enable clock\n");
diff --git a/drivers/pci/host/pcie-brcmstb.h b/drivers/pci/host/pcie-brcmstb.h
new file mode 100644
index 0000000..d7233f0
--- /dev/null
+++ b/drivers/pci/host/pcie-brcmstb.h
@@ -0,0 +1,22 @@
+#ifndef __BRCMSTB_PCI_H
+#define __BRCMSTB_PCI_H
+/*
+ * Copyright (C) 2015 - 2017 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+int brcm_register_notifier(void);
+int brcm_unregister_notifier(void);
+
+extern struct of_pci_range *dma_ranges;
+extern int num_dma_ranges;
+
+#endif /* __BRCMSTB_PCI_H */
--
1.9.0.138.g2de3478
^ permalink raw reply related
* [PATCH v3 3/8] PCI: brcmstb: Add Broadcom STB PCIe host controller driver
From: Jim Quinlan @ 2017-11-14 22:12 UTC (permalink / raw)
To: linux-kernel, Bjorn Helgaas, Catalin Marinas, Will Deacon,
Rob Herring, Brian Norris, Russell King, Robin Murphy,
Christoph Hellwig, Florian Fainelli, Jonas Gorski
Cc: Mark Rutland, devicetree, linux-mips, linux-pci, Kevin Cernekee,
Ralf Baechle, Jim Quinlan, bcm-kernel-feedback-list, Gregory Fong,
linux-arm-kernel
In-Reply-To: <1510697532-32828-1-git-send-email-jim2101024@gmail.com>
This commit adds the basic Broadcom STB PCIe controller. Missing is
the ability to process MSI and also handle dma-ranges for inbound
memory accesses. These two functionalities are added in subsequent
commits.
The PCIe block contains an MDIO interface. This is a local interface
only accessible by the PCIe controller. It cannot be used or shared
by any other HW. As such, the small amount of code for this
controller is included in this driver as there is little upside to put
it elsewhere.
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
drivers/pci/host/Kconfig | 9 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-brcmstb.c | 1124 +++++++++++++++++++++++++++++++++++++++
3 files changed, 1134 insertions(+)
create mode 100644 drivers/pci/host/pcie-brcmstb.c
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index b868803..751463e 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -220,4 +220,13 @@ config VMD
To compile this driver as a module, choose M here: the
module will be called vmd.
+config PCIE_BRCMSTB
+ tristate "Broadcom Brcmstb PCIe platform host driver"
+ depends on ARCH_BRCMSTB || BMIPS_GENERIC
+ depends on OF
+ depends on SOC_BRCMSTB
+ default ARCH_BRCMSTB || BMIPS_GENERIC
+ help
+ Adds support for Broadcom Settop Box PCIe host controller.
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 1238278..a8b9923 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
obj-$(CONFIG_VMD) += vmd.o
+obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/host/pcie-brcmstb.c b/drivers/pci/host/pcie-brcmstb.c
new file mode 100644
index 0000000..d8a8f7a
--- /dev/null
+++ b/drivers/pci/host/pcie-brcmstb.c
@@ -0,0 +1,1124 @@
+/*
+ * Copyright (C) 2009 - 2017 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/compiler.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/log2.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/printk.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+#include <soc/brcmstb/memory_api.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
+#define BRCM_PCIE_CAP_REGS 0x00ac
+/*
+ * Broadcom Settop Box PCIE Register Offsets. The names are from
+ * the chip's RDB and we use them here so that a script can correlate
+ * this code and the RDB to prevent discrepancies.
+ */
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
+#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
+#define PCIE_RC_DL_MDIO_ADDR 0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
+#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
+#define PCIE_MISC_MISC_CTRL 0x4008
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
+#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
+#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
+#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
+#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
+#define PCIE_MISC_PCIE_CTRL 0x4064
+#define PCIE_MISC_PCIE_STATUS 0x4068
+#define PCIE_MISC_REVISION 0x406c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
+#define PCIE_INTR2_CPU_BASE 0x4300
+
+/*
+ * Broadcom Settop Box PCIE Register Field shift and mask info. The
+ * names are from the chip's RDB and we use them here so that a script
+ * can correlate this code and the RDB to prevent discrepancies.
+ */
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2
+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
+#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
+#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
+#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
+#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
+#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
+#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
+#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
+#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
+#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
+#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
+#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
+#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
+#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
+#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
+#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
+#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
+#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
+#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
+#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
+#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
+#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
+#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
+
+#define BRCM_NUM_PCIE_OUT_WINS 0x4
+#define BRCM_MAX_SCB 0x4
+
+#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
+#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
+
+#define BURST_SIZE_128 0
+#define BURST_SIZE_256 1
+#define BURST_SIZE_512 2
+
+/* Offsets from PCIE_INTR2_CPU_BASE */
+#define STATUS 0x0
+#define SET 0x4
+#define CLR 0x8
+#define MASK_STATUS 0xc
+#define MASK_SET 0x10
+#define MASK_CLR 0x14
+
+#define PCIE_BUSNUM_SHIFT 20
+#define PCIE_SLOT_SHIFT 15
+#define PCIE_FUNC_SHIFT 12
+
+#if defined(__BIG_ENDIAN)
+#define DATA_ENDIAN 2 /* PCIe->DDR inbound accesses */
+#define MMIO_ENDIAN 2 /* CPU->PCIe outbound accesses */
+#else
+#define DATA_ENDIAN 0
+#define MMIO_ENDIAN 0
+#endif
+
+#define MDIO_PORT0 0x0
+#define MDIO_DATA_MASK 0x7fffffff
+#define MDIO_DATA_SHIFT 0x0
+#define MDIO_PORT_MASK 0xf0000
+#define MDIO_PORT_SHIFT 0x16
+#define MDIO_REGAD_MASK 0xffff
+#define MDIO_REGAD_SHIFT 0x0
+#define MDIO_CMD_MASK 0xfff00000
+#define MDIO_CMD_SHIFT 0x14
+#define MDIO_CMD_READ 0x1
+#define MDIO_CMD_WRITE 0x0
+#define MDIO_DATA_DONE_MASK 0x80000000
+#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
+#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
+#define SSC_REGS_ADDR 0x1100
+#define SET_ADDR_OFFSET 0x1f
+#define SSC_CNTL_OFFSET 0x2
+#define SSC_CNTL_OVRD_EN_MASK 0x8000
+#define SSC_CNTL_OVRD_EN_SHIFT 0xf
+#define SSC_CNTL_OVRD_VAL_MASK 0x4000
+#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
+#define SSC_STATUS_OFFSET 0x1
+#define SSC_STATUS_SSC_MASK 0x400
+#define SSC_STATUS_SSC_SHIFT 0xa
+#define SSC_STATUS_PLL_LOCK_MASK 0x800
+#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
+
+#define IDX_ADDR(pcie) \
+ ((pcie)->reg_offsets[EXT_CFG_INDEX])
+#define DATA_ADDR(pcie) \
+ ((pcie)->reg_offsets[EXT_CFG_DATA])
+#define PCIE_RGR1_SW_INIT_1(pcie) \
+ ((pcie)->reg_offsets[RGR1_SW_INIT_1])
+
+enum {
+ RGR1_SW_INIT_1,
+ EXT_CFG_INDEX,
+ EXT_CFG_DATA,
+};
+
+enum {
+ RGR1_SW_INIT_1_INIT_MASK,
+ RGR1_SW_INIT_1_INIT_SHIFT,
+ RGR1_SW_INIT_1_PERST_MASK,
+ RGR1_SW_INIT_1_PERST_SHIFT,
+};
+
+enum pcie_type {
+ BCM7425,
+ BCM7435,
+ GENERIC,
+ BCM7278,
+};
+
+struct brcm_window {
+ dma_addr_t pcie_addr;
+ phys_addr_t cpu_addr;
+ dma_addr_t size;
+};
+
+/* Internal PCIe Host Controller Information.*/
+struct brcm_pcie {
+ struct list_head list;
+ struct device *dev;
+ void __iomem *base;
+ struct list_head resources;
+ int irq;
+ struct clk *clk;
+ struct pci_bus *root_bus;
+ struct device_node *dn;
+ int id;
+ bool suspended;
+ int num_out_wins;
+ bool ssc;
+ int gen;
+ struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
+ unsigned int rev;
+ const int *reg_offsets;
+ const int *reg_field_info;
+ enum pcie_type type;
+};
+
+struct pcie_cfg_data {
+ const int *reg_field_info;
+ const int *offsets;
+ const enum pcie_type type;
+};
+
+static const int pcie_reg_field_info[] = {
+ [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
+ [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
+};
+
+static const int pcie_reg_field_info_bcm7278[] = {
+ [RGR1_SW_INIT_1_INIT_MASK] = 0x1,
+ [RGR1_SW_INIT_1_INIT_SHIFT] = 0x0,
+};
+
+static const int pcie_offset_bcm7425[] = {
+ [RGR1_SW_INIT_1] = 0x8010,
+ [EXT_CFG_INDEX] = 0x8300,
+ [EXT_CFG_DATA] = 0x8304,
+};
+
+static const struct pcie_cfg_data bcm7425_cfg = {
+ .reg_field_info = pcie_reg_field_info,
+ .offsets = pcie_offset_bcm7425,
+ .type = BCM7425,
+};
+
+static const int pcie_offsets[] = {
+ [RGR1_SW_INIT_1] = 0x9210,
+ [EXT_CFG_INDEX] = 0x9000,
+ [EXT_CFG_DATA] = 0x9004,
+};
+
+static const struct pcie_cfg_data bcm7435_cfg = {
+ .reg_field_info = pcie_reg_field_info,
+ .offsets = pcie_offsets,
+ .type = BCM7435,
+};
+
+static const struct pcie_cfg_data generic_cfg = {
+ .reg_field_info = pcie_reg_field_info,
+ .offsets = pcie_offsets,
+ .type = GENERIC,
+};
+
+static const int pcie_offset_bcm7278[] = {
+ [RGR1_SW_INIT_1] = 0xc010,
+ [EXT_CFG_INDEX] = 0x9000,
+ [EXT_CFG_DATA] = 0x9004,
+};
+
+static const struct pcie_cfg_data bcm7278_cfg = {
+ .reg_field_info = pcie_reg_field_info_bcm7278,
+ .offsets = pcie_offset_bcm7278,
+ .type = BCM7278,
+};
+
+static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
+ int where);
+
+static struct pci_ops brcm_pcie_ops = {
+ .map_bus = brcm_pcie_map_conf,
+ .read = pci_generic_config_read,
+ .write = pci_generic_config_write,
+};
+
+#if defined(CONFIG_MIPS)
+/* Broadcom MIPs HW implicitly does the swapping if necessary */
+#define bcm_readl(a) __raw_readl(a)
+#define bcm_writel(d, a) __raw_writel(d, a)
+#define bcm_readw(a) __raw_readw(a)
+#define bcm_writew(d, a) __raw_writew(d, a)
+#else
+#define bcm_readl(a) readl(a)
+#define bcm_writel(d, a) writel(d, a)
+#define bcm_readw(a) readw(a)
+#define bcm_writew(d, a) writew(d, a)
+#endif
+
+/*
+ * These macros are designed to sxtract/insert fields to host controller's
+ * register set.
+ */
+#define RD_FLD(base, reg, field) \
+ rd_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
+#define WR_FLD(base, reg, field, val) \
+ wr_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
+#define WR_FLD_RB(base, reg, field, val) \
+ wr_fld_rb(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
+#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
+ wr_fld(base + reg + off, reg##_##field##_MASK, \
+ reg##_##field##_SHIFT, val)
+#define EXTRACT_FIELD(val, reg, field) \
+ ((val & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
+#define INSERT_FIELD(val, reg, field, field_val) \
+ ((val & ~reg##_##field##_MASK) | \
+ (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
+
+static struct list_head brcm_pcie = LIST_HEAD_INIT(brcm_pcie);
+static phys_addr_t scb_size[BRCM_MAX_SCB];
+static int num_memc;
+static DEFINE_MUTEX(brcm_pcie_lock);
+
+static u32 rd_fld(void __iomem *p, u32 mask, int shift)
+{
+ return (bcm_readl(p) & mask) >> shift;
+}
+
+static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
+{
+ u32 reg = bcm_readl(p);
+
+ reg = (reg & ~mask) | ((val << shift) & mask);
+ bcm_writel(reg, p);
+}
+
+static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
+{
+ wr_fld(p, mask, shift, val);
+ (void)bcm_readl(p);
+}
+
+static const char *link_speed_to_str(int s)
+{
+ switch (s) {
+ case 1:
+ return "2.5";
+ case 2:
+ return "5.0";
+ case 3:
+ return "8.0";
+ default:
+ break;
+ }
+ return "???";
+}
+
+/*
+ * The roundup_pow_of_two() from log2.h invokes
+ * __roundup_pow_of_two(unsigned long), but we really need a
+ * such a function to take a native u64 since unsigned long
+ * is 32 bits on some configurations. So we provide this helper
+ * function below.
+ */
+static u64 roundup_pow_of_two_64(u64 n)
+{
+ return 1ULL << fls64(n - 1);
+}
+
+/*
+ * This is to convert the size of the inbound bar region to the
+ * non-liniear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
+ */
+int encode_ibar_size(u64 size)
+{
+ int log2_in = ilog2(size);
+
+ if (log2_in >= 12 && log2_in <= 15)
+ /* Covers 4KB to 32KB (inclusive) */
+ return (log2_in - 12) + 0x1c;
+ else if (log2_in >= 16 && log2_in <= 37)
+ /* Covers 64KB to 32GB, (inclusive) */
+ return log2_in - 15;
+ /* Something is awry so disable */
+ return 0;
+}
+
+static u32 mdio_form_pkt(int port, int regad, int cmd)
+{
+ u32 pkt = 0;
+
+ pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
+ pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
+ pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
+
+ return pkt;
+}
+
+/* negative return value indicates error */
+static int mdio_read(void __iomem *base, u8 port, u8 regad)
+{
+ int tries;
+ u32 data;
+
+ bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
+ base + PCIE_RC_DL_MDIO_ADDR);
+ bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
+
+ data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
+ for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
+ udelay(10);
+ data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
+ }
+
+ return MDIO_RD_DONE(data)
+ ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
+ : -EIO;
+}
+
+/* negative return value indicates error */
+static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
+{
+ int tries;
+ u32 data;
+
+ bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
+ base + PCIE_RC_DL_MDIO_ADDR);
+ bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
+ bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
+ base + PCIE_RC_DL_MDIO_WR_DATA);
+
+ data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
+ for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
+ udelay(10);
+ data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
+ }
+
+ return MDIO_WT_DONE(data) ? 0 : -EIO;
+}
+
+/* configures device for ssc mode; negative return value indicates error */
+static int set_ssc(void __iomem *base)
+{
+ int tmp;
+ u16 wrdata;
+ int pll, ssc;
+
+ tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
+ if (tmp < 0)
+ return tmp;
+
+ tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
+ if (tmp < 0)
+ return tmp;
+
+ wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
+ wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
+ tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
+ if (tmp < 0)
+ return tmp;
+
+ usleep_range(1000, 2000);
+ tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
+ if (tmp < 0)
+ return tmp;
+
+ ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
+ pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
+
+ return (ssc && pll) ? 0 : -EIO;
+}
+
+/* limits operation to a specific generation (1, 2, or 3) */
+static void set_gen(void __iomem *base, int gen)
+{
+ u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
+ u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
+
+ lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
+ bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
+
+ lnkctl2 = (lnkctl2 & ~0xf) | gen;
+ bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
+}
+
+static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
+ unsigned int win, phys_addr_t cpu_addr,
+ dma_addr_t pcie_addr, dma_addr_t size)
+{
+ void __iomem *base = pcie->base;
+ phys_addr_t cpu_addr_mb, limit_addr_mb;
+ u32 tmp;
+
+ /* Set the base of the pcie_addr window */
+ bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
+ base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
+ bcm_writel(upper_32_bits(pcie_addr),
+ base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
+
+ cpu_addr_mb = cpu_addr >> 20;
+ limit_addr_mb = (cpu_addr + size - 1) >> 20;
+
+ /* Write the addr base low register */
+ WR_FLD_WITH_OFFSET(base, (win * 4),
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
+ BASE, cpu_addr_mb);
+ /* Write the addr limit low register */
+ WR_FLD_WITH_OFFSET(base, (win * 4),
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
+ LIMIT, limit_addr_mb);
+
+ if (pcie->type != BCM7435 && pcie->type != BCM7425) {
+ /* Write the cpu addr high register */
+ tmp = (u32)(cpu_addr_mb >>
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
+ WR_FLD_WITH_OFFSET(base, (win * 8),
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
+ BASE, tmp);
+ /* Write the cpu limit high register */
+ tmp = (u32)(limit_addr_mb >>
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
+ WR_FLD_WITH_OFFSET(base, (win * 8),
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
+ LIMIT, tmp);
+ }
+}
+
+/* Configuration space read/write support */
+static int cfg_index(int busnr, int devfn, int reg)
+{
+ return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
+ | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
+ | (busnr << PCIE_BUSNUM_SHIFT)
+ | (reg & ~3);
+}
+
+static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
+{
+ void __iomem *base = pcie->base;
+ u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
+
+ return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
+}
+
+static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
+{
+ void __iomem *base = pcie->base;
+ u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
+ u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
+ u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
+
+ return (dla && plu) ? true : false;
+}
+
+static bool brcm_pcie_valid_device(struct brcm_pcie *pcie, struct pci_bus *bus,
+ int dev)
+{
+ if (pci_is_root_bus(bus)) {
+ if (dev > 0)
+ return false;
+ } else {
+ /* If there is no link, then there is no device */
+ if (!brcm_pcie_link_up(pcie))
+ return false;
+ }
+
+ return true;
+}
+
+static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
+ int where)
+{
+ struct brcm_pcie *pcie = bus->sysdata;
+ void __iomem *base = pcie->base;
+ int idx;
+
+ if (!brcm_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
+ return NULL;
+
+ /* Accesses to the RC go right to the RC registers */
+ if (pci_is_root_bus(bus))
+ return base + where;
+
+ /* For devices, write to the config space index register */
+ idx = cfg_index(bus->number, devfn, where);
+ bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
+ return base + DATA_ADDR(pcie) + (where & 0x3);
+}
+
+static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
+ unsigned int val)
+{
+ unsigned int offset;
+ unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
+ u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
+
+ if (pcie->type != BCM7278) {
+ wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
+ val);
+ } else if (of_machine_is_compatible("brcm,bcm7278a0")) {
+ /*
+ * The two PCIe instances on 7278a0 are not even consistent with
+ * respect to each other for internal offsets, here we offset
+ * by 0x14000 + RGR1_SW_INIT_1's relative offset to account for
+ * that.
+ */
+ offset = pcie->id ? 0x14010 : pcie->reg_offsets[RGR1_SW_INIT_1];
+ wr_fld_rb(pcie->base + offset, mask, shift, val);
+ } else {
+ wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
+ val);
+ }
+}
+
+static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
+ unsigned int val)
+{
+ if (pcie->type != BCM7278)
+ wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
+ PCIE_RGR1_SW_INIT_1_PERST_MASK,
+ PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
+ else
+ /* Assert = 0, de-assert = 1 on 7278 */
+ WR_FLD_RB(pcie->base, PCIE_MISC_PCIE_CTRL, PCIE_PERSTB, !val);
+}
+
+static int brcm_pcie_add_controller(struct brcm_pcie *pcie)
+{
+ mutex_lock(&brcm_pcie_lock);
+ list_add_tail(&pcie->list, &brcm_pcie);
+ mutex_unlock(&brcm_pcie_lock);
+
+ return 0;
+}
+
+static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
+{
+ struct list_head *pos, *q;
+ struct brcm_pcie *tmp;
+
+ mutex_lock(&brcm_pcie_lock);
+ list_for_each_safe(pos, q, &brcm_pcie) {
+ tmp = list_entry(pos, struct brcm_pcie, list);
+ if (tmp == pcie) {
+ list_del(pos);
+ if (list_empty(&brcm_pcie))
+ num_memc = 0;
+ break;
+ }
+ }
+ mutex_unlock(&brcm_pcie_lock);
+}
+
+static int brcm_pcie_parse_request_of_pci_ranges(struct brcm_pcie *pcie)
+{
+ struct resource_entry *win;
+ int ret;
+
+ ret = of_pci_get_host_bridge_resources(pcie->dn, 0, 0xff,
+ &pcie->resources, NULL);
+ if (ret) {
+ dev_err(pcie->dev, "failed to get host resources\n");
+ return ret;
+ }
+
+ resource_list_for_each_entry(win, &pcie->resources) {
+ struct resource *parent, *res = win->res;
+ dma_addr_t offset = (dma_addr_t)win->offset;
+
+ if (resource_type(res) == IORESOURCE_IO) {
+ parent = &ioport_resource;
+ } else if (resource_type(res) == IORESOURCE_MEM) {
+ if (pcie->num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
+ dev_err(pcie->dev, "too many outbound wins\n");
+ return -EINVAL;
+ }
+ pcie->out_wins[pcie->num_out_wins].cpu_addr
+ = (phys_addr_t)res->start;
+ pcie->out_wins[pcie->num_out_wins].pcie_addr
+ = (dma_addr_t)(res->start
+ - (phys_addr_t)offset);
+ pcie->out_wins[pcie->num_out_wins].size
+ = (dma_addr_t)(res->end - res->start + 1);
+ pcie->num_out_wins++;
+ parent = &iomem_resource;
+ } else {
+ continue;
+ }
+
+ ret = devm_request_resource(pcie->dev, parent, res);
+ if (ret) {
+ dev_err(pcie->dev, "failed to get res %pR\n", res);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static int brcm_pcie_setup(struct brcm_pcie *pcie)
+{
+ void __iomem *base = pcie->base;
+ unsigned int scb_size_val;
+ u64 rc_bar2_size = 0, rc_bar2_offset = 0, total_mem_size = 0;
+ u32 tmp, burst;
+ int i, j, ret, limit;
+ u16 nlw, cls, lnksta;
+ bool ssc_good = false;
+
+ /* reset the bridge and the endpoint device */
+ /* field: PCIE_BRIDGE_SW_INIT = 1 */
+ brcm_pcie_bridge_sw_init_set(pcie, 1);
+
+ /* field: PCIE_SW_PERST = 1, on 7278, we start de-asserted already */
+ if (pcie->type != BCM7278)
+ brcm_pcie_perst_set(pcie, 1);
+
+ usleep_range(100, 200);
+
+ /* take the bridge out of reset */
+ /* field: PCIE_BRIDGE_SW_INIT = 0 */
+ brcm_pcie_bridge_sw_init_set(pcie, 0);
+
+ WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
+ /* wait for serdes to be stable */
+ usleep_range(100, 200);
+
+ /* Grab the PCIe hw revision number */
+ tmp = bcm_readl(base + PCIE_MISC_REVISION);
+ pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
+
+ /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
+ tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
+ tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
+ burst = (pcie->type == GENERIC || pcie->type == BCM7278)
+ ? BURST_SIZE_512 : BURST_SIZE_256;
+ tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE, burst);
+ bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
+
+ /*
+ * Set up inbound memory view for the EP (called RC_BAR2,
+ * not to be confused with the BARs that are advertised by
+ * the EP).
+ */
+ for (i = 0; i < num_memc; i++)
+ total_mem_size += scb_size[i];
+
+ /*
+ * The PCIe host controller by design must set the inbound
+ * viewport to be a contiguous arrangement of all of the
+ * system's memory. In addition, its size mut be a power of
+ * two. To further complicate matters, the viewport must
+ * start on a pcie-address that is aligned on a multiple of its
+ * size. If a portion of the viewport does not represent
+ * system memory -- e.g. 3GB of memory requires a 4GB viewport
+ * -- we can map the outbound memory in or after 3GB and even
+ * though the viewport will overlap the outbound memory the
+ * controller will know to send outbound memory downstream and
+ * everything else upstream.
+ */
+ rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
+
+ /*
+ * Set simple configuration based on memory sizes
+ * only. We always start the viewport at address 0.
+ */
+ rc_bar2_offset = 0;
+
+ tmp = lower_32_bits(rc_bar2_offset);
+ tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
+ encode_ibar_size(rc_bar2_size));
+ bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
+ bcm_writel(upper_32_bits(rc_bar2_offset),
+ base + PCIE_MISC_RC_BAR2_CONFIG_HI);
+
+ /* field: SCB0_SIZE, default = 0xf (1 GB) */
+ scb_size_val = scb_size[0]
+ ? ilog2(scb_size[0]) - 15 : 0xf;
+ WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
+
+ /* field: SCB1_SIZE, default = 0xf (1 GB) */
+ if (num_memc > 1) {
+ scb_size_val = scb_size[1]
+ ? ilog2(scb_size[1]) - 15 : 0xf;
+ WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB1_SIZE, scb_size_val);
+ }
+
+ /* field: SCB2_SIZE, default = 0xf (1 GB) */
+ if (num_memc > 2) {
+ scb_size_val = scb_size[2]
+ ? ilog2(scb_size[2]) - 15 : 0xf;
+ WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB2_SIZE, scb_size_val);
+ }
+
+ /* disable the PCIe->GISB memory window (RC_BAR1) */
+ WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
+
+ /* disable the PCIe->SCB memory window (RC_BAR3) */
+ WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
+
+ if (!pcie->suspended) {
+ /* clear any interrupts we find on boot */
+ bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
+ (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
+ }
+
+ /* Mask all interrupts since we are not handling any yet */
+ bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
+ (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
+
+ if (pcie->gen)
+ set_gen(base, pcie->gen);
+
+ /* take the EP device out of reset */
+ /* field: PCIE_SW_PERST = 0 */
+ brcm_pcie_perst_set(pcie, 0);
+
+ /*
+ * Give the RC/EP time to wake up, before trying to configure RC.
+ * Intermittently check status for link-up, up to a total of 100ms
+ * when we don't know if the device is there, and up to 1000ms if
+ * we do know the device is there.
+ */
+ limit = pcie->suspended ? 1000 : 100;
+ for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
+ j += i, i = i * 2)
+ msleep(i + j > limit ? limit - j : i);
+
+ if (!brcm_pcie_link_up(pcie)) {
+ dev_info(pcie->dev, "link down\n");
+ return -ENODEV;
+ }
+
+ if (!brcm_pcie_rc_mode(pcie)) {
+ dev_err(pcie->dev, "PCIe misconfigured; is in EP mode\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < pcie->num_out_wins; i++)
+ brcm_pcie_set_outbound_win(pcie, i, pcie->out_wins[i].cpu_addr,
+ pcie->out_wins[i].pcie_addr,
+ pcie->out_wins[i].size);
+
+ /*
+ * For config space accesses on the RC, show the right class for
+ * a PCIe-PCIe bridge (the default setting is to be EP mode).
+ */
+ WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
+
+ if (pcie->ssc) {
+ ret = set_ssc(base);
+ if (ret == 0)
+ ssc_good = true;
+ else
+ dev_err(pcie->dev,
+ "failed attempt to enter ssc mode\n");
+ }
+
+ lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
+ cls = lnksta & PCI_EXP_LNKSTA_CLS;
+ nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
+ dev_info(pcie->dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
+ nlw, ssc_good ? "(SSC)" : "(!SSC)");
+
+ /* PCIe->SCB endian mode for BAR */
+ /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
+ WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
+ ENDIAN_MODE_BAR2, DATA_ENDIAN);
+
+ /*
+ * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
+ * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
+ */
+ WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
+
+ return 0;
+}
+
+static void enter_l23(struct brcm_pcie *pcie)
+{
+ void __iomem *base = pcie->base;
+ int tries, l23;
+
+ /* assert request for L23 */
+ WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
+ /* poll L23 status */
+ for (tries = 0, l23 = 0; tries < 1000 && !l23; tries++)
+ l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
+ if (!l23)
+ dev_err(pcie->dev, "failed to enter L23\n");
+}
+
+static void turn_off(struct brcm_pcie *pcie)
+{
+ void __iomem *base = pcie->base;
+
+ if (brcm_pcie_link_up(pcie))
+ enter_l23(pcie);
+ /* Reset endpoint device */
+ brcm_pcie_perst_set(pcie, 1);
+ /* deassert request for L23 in case it was asserted */
+ WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
+ /* SERDES_IDDQ = 1 */
+ WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
+ /* Shutdown PCIe bridge */
+ brcm_pcie_bridge_sw_init_set(pcie, 1);
+}
+
+static int brcm_pcie_suspend(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+
+ turn_off(pcie);
+ clk_disable_unprepare(pcie->clk);
+ pcie->suspended = true;
+
+ return 0;
+}
+
+static int brcm_pcie_resume(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+ void __iomem *base;
+ int ret;
+
+ base = pcie->base;
+ clk_prepare_enable(pcie->clk);
+
+ /* Take bridge out of reset so we can access the SERDES reg */
+ brcm_pcie_bridge_sw_init_set(pcie, 0);
+
+ /* SERDES_IDDQ = 0 */
+ WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
+ /* wait for serdes to be stable */
+ usleep_range(100, 200);
+
+ ret = brcm_pcie_setup(pcie);
+ if (ret)
+ return ret;
+
+ pcie->suspended = false;
+
+ return 0;
+}
+
+static void _brcm_pcie_remove(struct brcm_pcie *pcie)
+{
+ turn_off(pcie);
+ clk_disable_unprepare(pcie->clk);
+ clk_put(pcie->clk);
+ brcm_pcie_remove_controller(pcie);
+}
+
+static int brcm_pcie_remove(struct platform_device *pdev)
+{
+ struct brcm_pcie *pcie = platform_get_drvdata(pdev);
+
+ pci_stop_root_bus(pcie->root_bus);
+ pci_remove_root_bus(pcie->root_bus);
+ _brcm_pcie_remove(pcie);
+
+ return 0;
+}
+
+static const struct of_device_id brcm_pcie_match[] = {
+ { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
+ { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
+ { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
+ { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
+ {},
+};
+MODULE_DEVICE_TABLE(of, brcm_pcie_match);
+
+static int brcm_pcie_probe(struct platform_device *pdev)
+{
+ struct device_node *dn = pdev->dev.of_node;
+ const struct of_device_id *of_id;
+ const struct pcie_cfg_data *data;
+ int ret;
+ struct brcm_pcie *pcie;
+ struct resource *res;
+ void __iomem *base;
+ u32 tmp;
+ struct pci_host_bridge *bridge;
+ struct pci_bus *child;
+
+ bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
+ if (!bridge)
+ return -ENOMEM;
+
+ pcie = pci_host_bridge_priv(bridge);
+ INIT_LIST_HEAD(&pcie->resources);
+
+ of_id = of_match_node(brcm_pcie_match, dn);
+ if (!of_id) {
+ dev_err(&pdev->dev, "failed to look up compatible string\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(dn, "dma-ranges", &tmp) == 0) {
+ dev_err(&pdev->dev, "cannot yet handle dma-ranges\n");
+ return -EINVAL;
+ }
+
+ data = of_id->data;
+ pcie->reg_offsets = data->offsets;
+ pcie->reg_field_info = data->reg_field_info;
+ pcie->type = data->type;
+ pcie->dn = dn;
+ pcie->dev = &pdev->dev;
+
+ pcie->id = of_get_pci_domain_nr(dn);
+ if (pcie->id < 0)
+ return pcie->id;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -EINVAL;
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
+ if (IS_ERR(pcie->clk)) {
+ dev_err(&pdev->dev, "could not get clock\n");
+ pcie->clk = NULL;
+ }
+ pcie->base = base;
+
+ ret = of_pci_get_max_link_speed(dn);
+ pcie->gen = (ret < 0) ? 0 : ret;
+
+ pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
+
+ ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
+ if (ret == 0)
+ /* keep going, as we don't use this intr yet */
+ dev_warn(pcie->dev, "cannot get pcie interrupt\n");
+ else
+ pcie->irq = ret;
+
+ ret = brcm_pcie_parse_request_of_pci_ranges(pcie);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(pcie->clk);
+ if (ret) {
+ dev_err(&pdev->dev, "could not enable clock\n");
+ return ret;
+ }
+
+ ret = brcm_pcie_add_controller(pcie);
+ if (ret)
+ return ret;
+
+ ret = brcm_pcie_setup(pcie);
+ if (ret)
+ goto fail;
+
+ list_splice_init(&pcie->resources, &bridge->windows);
+ bridge->dev.parent = &pdev->dev;
+ bridge->busnr = 0;
+ bridge->ops = &brcm_pcie_ops;
+ bridge->sysdata = pcie;
+ bridge->map_irq = of_irq_parse_and_map_pci;
+ bridge->swizzle_irq = pci_common_swizzle;
+
+ ret = pci_scan_root_bus_bridge(bridge);
+ if (ret < 0) {
+ dev_err(pcie->dev, "Scanning root bridge failed");
+ goto fail;
+ }
+
+ pci_assign_unassigned_bus_resources(bridge->bus);
+ list_for_each_entry(child, &bridge->bus->children, node)
+ pcie_bus_configure_settings(child);
+ pci_bus_add_devices(bridge->bus);
+ platform_set_drvdata(pdev, pcie);
+ pcie->root_bus = bridge->bus;
+
+ return 0;
+
+fail:
+ _brcm_pcie_remove(pcie);
+ return ret;
+}
+
+static const struct dev_pm_ops brcm_pcie_pm_ops = {
+ .suspend_noirq = brcm_pcie_suspend,
+ .resume_noirq = brcm_pcie_resume,
+};
+
+static struct platform_driver __refdata brcm_pcie_driver = {
+ .probe = brcm_pcie_probe,
+ .remove = brcm_pcie_remove,
+ .driver = {
+ .name = "brcm-pcie",
+ .owner = THIS_MODULE,
+ .of_match_table = brcm_pcie_match,
+ .pm = &brcm_pcie_pm_ops,
+ },
+};
+
+module_platform_driver(brcm_pcie_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Broadcom STB PCIE RC driver");
+MODULE_AUTHOR("Broadcom");
--
1.9.0.138.g2de3478
^ permalink raw reply related
* [PATCH v3 2/8] dt-bindings: pci: Add DT docs for Brcmstb PCIe device
From: Jim Quinlan @ 2017-11-14 22:12 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bjorn Helgaas,
Catalin Marinas, Will Deacon, Rob Herring, Brian Norris,
Russell King, Robin Murphy, Christoph Hellwig, Florian Fainelli,
Jonas Gorski
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Gregory Fong,
Kevin Cernekee, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Ralf Baechle, Jim Quinlan
In-Reply-To: <1510697532-32828-1-git-send-email-jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
The DT bindings description of the Brcmstb PCIe device is described. This
node can be used by almost all Broadcom settop box chips, using
ARM, ARM64, or MIPS CPU architectures.
Signed-off-by: Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
.../devicetree/bindings/pci/brcmstb-pcie.txt | 59 ++++++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
new file mode 100644
index 0000000..a1a9ad5
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
@@ -0,0 +1,59 @@
+Brcmstb PCIe Host Controller Device Tree Bindings
+
+Required Properties:
+- compatible
+ "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs.
+ "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs.
+ "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including
+ the 7278).
+ "brcm,bcm7278-pcie" -- for 7278 family ARM-based SOCs.
+
+- reg -- the register start address and length for the PCIe reg block.
+- interrupts -- two interrupts are specified; the first interrupt is for
+ the PCI host controller and the second is for MSI if the built-in
+ MSI controller is to be used.
+- interrupt-names -- names of the interrupts (above): "pcie" and "msi".
+- #address-cells -- set to <3>.
+- #size-cells -- set to <2>.
+- #interrupt-cells: set to <1>.
+- interrupt-map-mask and interrupt-map, standard PCI properties to define the
+ mapping of the PCIe interface to interrupt numbers.
+- ranges: ranges for the PCI memory and I/O regions.
+- linux,pci-domain -- should be unique per host controller.
+
+Optional Properties:
+- clocks -- phandle of pcie clock.
+- clock-names -- set to "sw_pcie" if clocks is used.
+- dma-ranges -- Specifies the inbound memory mapping regions when
+ an "identity map" is not possible.
+- msi-controller -- this property is typically specified to have the
+ PCIe controller use its internal MSI controller.
+- msi-parent -- set to use an external MSI interrupt controller.
+- brcm,enable-ssc -- (boolean) indicates usage of spread-spectrum clocking.
+- max-link-speed -- (integer) indicates desired generation of link:
+ 1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3).
+
+Example Node:
+
+pcie0: pcie@f0460000 {
+ reg = <0x0 0xf0460000 0x0 0x9310>;
+ interrupts = <0x0 0x0 0x4>;
+ compatible = "brcm,bcm7445-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000
+ 0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &intc 0 47 3
+ 0 0 0 2 &intc 0 48 3
+ 0 0 0 3 &intc 0 49 3
+ 0 0 0 4 &intc 0 50 3>;
+ clocks = <&sw_pcie0>;
+ clock-names = "sw_pcie";
+ msi-parent = <&pcie0>; /* use PCIe's internal MSI controller */
+ msi-controller; /* use PCIe's internal MSI controller */
+ brcm,ssc;
+ max-link-speed = <1>;
+ linux,pci-domain = <0>;
+ };
--
1.9.0.138.g2de3478
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related
* [PATCH v3 1/8] SOC: brcmstb: add memory API
From: Jim Quinlan @ 2017-11-14 22:12 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bjorn Helgaas,
Catalin Marinas, Will Deacon, Rob Herring, Brian Norris,
Russell King, Robin Murphy, Christoph Hellwig, Florian Fainelli,
Jonas Gorski
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Gregory Fong,
Kevin Cernekee, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Ralf Baechle, Jim Quinlan
In-Reply-To: <1510697532-32828-1-git-send-email-jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
This commit adds a memory API suitable for ascertaining the sizes of
each of the N memory controllers in a Broadcom STB chip. Its first
user will be the Broadcom STB PCIe root complex driver, which needs
to know these sizes to properly set up DMA mappings for inbound
regions.
We cannot use memblock here or anything like what Linux provides
because it collapses adjacent regions within a larger block, and here
we actually need per-memory controller addresses and sizes, which is
why we resort to manual DT parsing.
Signed-off-by: Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/soc/bcm/brcmstb/Makefile | 2 +-
drivers/soc/bcm/brcmstb/memory.c | 172 +++++++++++++++++++++++++++++++++++++++
include/soc/brcmstb/memory_api.h | 25 ++++++
3 files changed, 198 insertions(+), 1 deletion(-)
create mode 100644 drivers/soc/bcm/brcmstb/memory.c
create mode 100644 include/soc/brcmstb/memory_api.h
diff --git a/drivers/soc/bcm/brcmstb/Makefile b/drivers/soc/bcm/brcmstb/Makefile
index 9120b27..4cea7b6 100644
--- a/drivers/soc/bcm/brcmstb/Makefile
+++ b/drivers/soc/bcm/brcmstb/Makefile
@@ -1 +1 @@
-obj-y += common.o biuctrl.o
+obj-y += common.o biuctrl.o memory.o
diff --git a/drivers/soc/bcm/brcmstb/memory.c b/drivers/soc/bcm/brcmstb/memory.c
new file mode 100644
index 0000000..eb647ad9
--- /dev/null
+++ b/drivers/soc/bcm/brcmstb/memory.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright © 2015-2017 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * A copy of the GPL is available at
+ * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ * Foundation at https://www.gnu.org/licenses/ .
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/libfdt.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/sizes.h>
+#include <soc/brcmstb/memory_api.h>
+
+/* Macro to help extract property data */
+#define DT_PROP_DATA_TO_U32(b, offs) (fdt32_to_cpu(*(u32*)(b + offs)))
+
+/* Constants used when retrieving memc info */
+#define NUM_BUS_RANGES 10
+#define BUS_RANGE_ULIMIT_SHIFT 4
+#define BUS_RANGE_LLIMIT_SHIFT 4
+#define BUS_RANGE_PA_SHIFT 12
+
+enum {
+ BUSNUM_MCP0 = 0x4,
+ BUSNUM_MCP1 = 0x5,
+ BUSNUM_MCP2 = 0x6,
+};
+
+/*
+ * If the DT nodes are handy, determine which MEMC holds the specified
+ * physical address.
+ */
+#ifdef CONFIG_ARCH_BRCMSTB
+int __brcmstb_memory_phys_addr_to_memc(phys_addr_t pa, void __iomem *base)
+{
+ int memc = -1;
+ int i;
+
+ for (i = 0; i < NUM_BUS_RANGES; i++, base += 8) {
+ const u64 ulimit_raw = readl(base);
+ const u64 llimit_raw = readl(base + 4);
+ const u64 ulimit =
+ ((ulimit_raw >> BUS_RANGE_ULIMIT_SHIFT)
+ << BUS_RANGE_PA_SHIFT) | 0xfff;
+ const u64 llimit = (llimit_raw >> BUS_RANGE_LLIMIT_SHIFT)
+ << BUS_RANGE_PA_SHIFT;
+ const u32 busnum = (u32)(ulimit_raw & 0xf);
+
+ if (pa >= llimit && pa <= ulimit) {
+ if (busnum >= BUSNUM_MCP0 && busnum <= BUSNUM_MCP2) {
+ memc = busnum - BUSNUM_MCP0;
+ break;
+ }
+ }
+ }
+
+ return memc;
+}
+
+int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa)
+{
+ int memc = -1;
+ struct device_node *np;
+ void __iomem *cpubiuctrl;
+
+ np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
+ if (!np)
+ return memc;
+
+ cpubiuctrl = of_iomap(np, 0);
+ if (!cpubiuctrl)
+ goto cleanup;
+
+ memc = __brcmstb_memory_phys_addr_to_memc(pa, cpubiuctrl);
+ iounmap(cpubiuctrl);
+
+cleanup:
+ of_node_put(np);
+
+ return memc;
+}
+
+#elif defined(CONFIG_MIPS)
+int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa)
+{
+ /* The logic here is fairly simple and hardcoded: if pa <= 0x5000_0000,
+ * then this is MEMC0, else MEMC1.
+ *
+ * For systems with 2GB on MEMC0, MEMC1 starts at 9000_0000, with 1GB
+ * on MEMC0, MEMC1 starts at 6000_0000.
+ */
+ if (pa >= 0x50000000ULL)
+ return 1;
+ else
+ return 0;
+}
+#endif
+
+u64 brcmstb_memory_memc_size(int memc)
+{
+ const void *fdt = initial_boot_params;
+ const int mem_offset = fdt_path_offset(fdt, "/memory");
+ int addr_cells = 1, size_cells = 1;
+ const struct fdt_property *prop;
+ int proplen, cellslen;
+ u64 memc_size = 0;
+ int i;
+
+ /* Get root size and address cells if specified */
+ prop = fdt_get_property(fdt, 0, "#size-cells", &proplen);
+ if (prop)
+ size_cells = DT_PROP_DATA_TO_U32(prop->data, 0);
+
+ prop = fdt_get_property(fdt, 0, "#address-cells", &proplen);
+ if (prop)
+ addr_cells = DT_PROP_DATA_TO_U32(prop->data, 0);
+
+ if (mem_offset < 0)
+ return -1;
+
+ prop = fdt_get_property(fdt, mem_offset, "reg", &proplen);
+ cellslen = (int)sizeof(u32) * (addr_cells + size_cells);
+ if ((proplen % cellslen) != 0)
+ return -1;
+
+ for (i = 0; i < proplen / cellslen; ++i) {
+ u64 addr = 0;
+ u64 size = 0;
+ int memc_idx;
+ int j;
+
+ for (j = 0; j < addr_cells; ++j) {
+ int offset = (cellslen * i) + (sizeof(u32) * j);
+
+ addr |= (u64)DT_PROP_DATA_TO_U32(prop->data, offset) <<
+ ((addr_cells - j - 1) * 32);
+ }
+ for (j = 0; j < size_cells; ++j) {
+ int offset = (cellslen * i) +
+ (sizeof(u32) * (j + addr_cells));
+
+ size |= (u64)DT_PROP_DATA_TO_U32(prop->data, offset) <<
+ ((size_cells - j - 1) * 32);
+ }
+
+ if ((phys_addr_t)addr != addr) {
+ pr_err("phys_addr_t is smaller than provided address 0x%llx!\n",
+ addr);
+ return -1;
+ }
+
+ memc_idx = brcmstb_memory_phys_addr_to_memc((phys_addr_t)addr);
+ if (memc_idx == memc)
+ memc_size += size;
+ }
+
+ return memc_size;
+}
+EXPORT_SYMBOL_GPL(brcmstb_memory_memc_size);
+
diff --git a/include/soc/brcmstb/memory_api.h b/include/soc/brcmstb/memory_api.h
new file mode 100644
index 0000000..d922906
--- /dev/null
+++ b/include/soc/brcmstb/memory_api.h
@@ -0,0 +1,25 @@
+#ifndef __MEMORY_API_H
+#define __MEMORY_API_H
+
+/*
+ * Bus Interface Unit control register setup, must happen early during boot,
+ * before SMP is brought up, called by machine entry point.
+ */
+void brcmstb_biuctrl_init(void);
+
+#ifdef CONFIG_SOC_BRCMSTB
+int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa);
+u64 brcmstb_memory_memc_size(int memc);
+#else
+static inline int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa)
+{
+ return -EINVAL;
+}
+
+static inline u64 brcmstb_memory_memc_size(int memc)
+{
+ return -1;
+}
+#endif
+
+#endif /* __MEMORY_API_H */
--
1.9.0.138.g2de3478
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related
* [PATCH v3 0/8] PCI: brcmstb: Add Broadcom Settopbox PCIe support (V3)
From: Jim Quinlan @ 2017-11-14 22:12 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bjorn Helgaas,
Catalin Marinas, Will Deacon, Rob Herring, Brian Norris,
Russell King, Robin Murphy, Christoph Hellwig, Florian Fainelli,
Jonas Gorski
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Gregory Fong,
Kevin Cernekee, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Ralf Baechle, Jim Quinlan
This patch series adds support for the Broadcom Settopbox PCIe host
controller. It is targeted to Broadcom Settopbox chips running on
ARM, ARM64, and MIPS platforms.
V3 Changes:
- Fold pcie-brcmstb-msi.c into pcie-brcmstb.c
- Use PCI_XXX constants for PCIe capability registers
- Removal of any unused constants
- Change s/pci/pcie/ for filenames, comment text
- Config space access now uses 8/16/32 read/writes
- Use proper multi-line comment style
- Use function names, structure that are common in other host drivers
- DT binding 'brcm,ssc' is now 'brcm,enable-ssc'
- Dropped DT binding 'xyz-supply'
- Not setting CRS support as Linux does it if it is advertised.
- Removed code that was considered "debug code".
- Use of_get_pcie_domain_nr()
- Variable 'bridge_setup_done' removed.
V2 Changes:
* Patch brcmstb-add-memory-API:
- fix DT_PROP_DATA_TO_U32 macro.
- dropped one EXPORT_SYMBOL, changed the other to GPL.
* Patch DT-docs-for-Brcmstb-PCIe:
- change 'brcm,gen' prop to standard 'max-link-speed'.
- rewrite bindings commit to omit standard prop defs.
- change props "supplies", "supply-names" to "xyz-supply"
* Patch removed: export-symbol-arch_setup_dma_ops [4/9]
* Patch brcmstb-add-dma-ranges:
- use get_dma_ops(); also use a const dma_map_ops structure.
- rewrite map_sg(), unmap_sg(), other calls like syng_sg_*()
- omit brcm_mapping_error(), but added code in brcm_dma_supported()
- put all of the notifier code in one compilation unit.
Florian Fainelli (1):
SOC: brcmstb: add memory API
Jim Quinlan (7):
dt-bindings: pci: Add DT docs for Brcmstb PCIe device
PCI: brcmstb: Add Broadcom STB PCIe host controller driver
PCI: brcmstb: Add dma-range mapping for inbound traffic
PCI/MSI: Enable PCI_MSI_IRQ_DOMAIN support for MIPS
PCI: brcmstb: Add MSI capability
MIPS: BMIPS: Add PCI bindings for 7425, 7435
MIPS: BMIPS: Enable PCI
.../devicetree/bindings/pci/brcmstb-pcie.txt | 59 +
arch/mips/Kconfig | 3 +
arch/mips/boot/dts/brcm/bcm7425.dtsi | 26 +
arch/mips/boot/dts/brcm/bcm7435.dtsi | 27 +
arch/mips/boot/dts/brcm/bcm97425svmb.dts | 4 +
arch/mips/boot/dts/brcm/bcm97435svmb.dts | 4 +
arch/mips/include/asm/Kbuild | 1 +
drivers/pci/Kconfig | 2 +-
drivers/pci/host/Kconfig | 9 +
drivers/pci/host/Makefile | 3 +
drivers/pci/host/pcie-brcmstb-dma.c | 319 ++++
drivers/pci/host/pcie-brcmstb.c | 1591 ++++++++++++++++++++
drivers/pci/host/pcie-brcmstb.h | 22 +
drivers/soc/bcm/brcmstb/Makefile | 2 +-
drivers/soc/bcm/brcmstb/memory.c | 172 +++
include/soc/brcmstb/memory_api.h | 25 +
16 files changed, 2267 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
create mode 100644 drivers/pci/host/pcie-brcmstb-dma.c
create mode 100644 drivers/pci/host/pcie-brcmstb.c
create mode 100644 drivers/pci/host/pcie-brcmstb.h
create mode 100644 drivers/soc/bcm/brcmstb/memory.c
create mode 100644 include/soc/brcmstb/memory_api.h
--
1.9.0.138.g2de3478
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* Re: [PATCH 1/2] arm64: dts: orange-pi-zero-plus2: fix sdcard detect
From: Sergey Matyukevich @ 2017-11-14 18:53 UTC (permalink / raw)
To: Maxime Ripard
Cc: Jagan Teki, Chen-Yu Tsai, Rob Herring, Mark Rutland, devicetree,
linux-arm-kernel
In-Reply-To: <20171114143941.3qgdlqn4xfarfhql-ZC1Zs529Oq4@public.gmane.org>
Hello Maxime, Jagan,
> > > >> >>> > Did you try to boot from sdcard ? I am not able to boot my board from
> > > >> >>> > sd-card without this change. As I mentioned earlier in my email
> > > >> >>> > to buildroot mailing list, with mmc debug enabled I see that mmc
> > > >> >>> > tries to init sd-card when I remove it from the slot.
> > > >> >>> >
> > > >> >>> > Maybe there is a minor differences between h/w versions or batches ?
> > > >> >>> > What is you board version ? I tested on board v1.0.
> > > >> >>>
> > > >> >>> Looking at the schematics, it definitely looks like it's active low.
> > > >> >>
> > > >> >> Is it ok to merge it then ? Or using 'cd-inverted' property
> > > >> >> is the preferable option ?
> > > >> >
> > > >> > W/o any change mainline works unstable for me, it wasn't booting
> > > >> > at-all[1] did you find the same?
> > > >> >
> > > >> > Even tried with active LOW and cd-inverted.
> > > >> >
> > > >> > [1] https://paste.ubuntu.com/25909064/
> > > >>
> > > >> Look like something broken for H5 and A64 between v4.14-rc8 to latest
> > > >
> > > > Both 4.13.7 and 4.14-rc8 (synched today) kernels worked fine for me.
> > > > DTS behavior is all the same:
> > >
> > > I've tried fresh sync [2] but still see the issue, can you check the
> > > Image size of log(suspecting on that area)
> >
> > Do you plan to accept this patch as well ? Or you would prefer to wait
> > for the confirmation from Jagan as well ?
>
> I'm happy with the patch, but I was under the impression that the
> discussion had not settled yet. If it did, then yeah I'll merge it :)
Both schematics and my tests on v1.0 board confirm that this fix is ok.
However we haven't yet got the ACK from Jagan, the original submitter
of this dts file. FWIW discussion was mostly about the problems with
his setup and not about the fix itself.
Jagan,
did you have a chance to resolve the issues with your setup and verify
that boot from sd-card is fixed by this patch ?
Regards,
Sergey
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* Re: [PATCH V4 3/6] iommu/arm-smmu: Invoke pm_runtime during probe, add/remove device
From: Vivek Gautam @ 2017-11-14 18:30 UTC (permalink / raw)
To: Rob Clark, Robin Murphy, Will Deacon, Rafael J. Wysocki
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-msm, Stephen Boyd, Linux Kernel Mailing List,
Stanimir Varbanov,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
Rob Herring, linux-clk,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <CAF6AEGsw2=nERuJ8UCBr_kTBS0TigaA9LL1Hxw3JmNiu4oycOA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi,
On Mon, Aug 7, 2017 at 5:59 PM, Rob Clark <robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On Mon, Aug 7, 2017 at 4:27 AM, Vivek Gautam
> <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:
>> On Thu, Jul 13, 2017 at 5:20 PM, Rob Clark <robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>>> On Thu, Jul 13, 2017 at 1:35 AM, Sricharan R <sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:
>>>> Hi Vivek,
>>>>
>>>> On 7/13/2017 10:43 AM, Vivek Gautam wrote:
>>>>> Hi Stephen,
>>>>>
>>>>>
>>>>> On 07/13/2017 04:24 AM, Stephen Boyd wrote:
>>>>>> On 07/06, Vivek Gautam wrote:
>>>>>>> @@ -1231,12 +1237,18 @@ static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
>>>>>>> static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
>>>>>>> size_t size)
>>>>>>> {
>>>>>>> - struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops;
>>>>>>> + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
>>>>>>> + struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
>>>>>>> + size_t ret;
>>>>>>> if (!ops)
>>>>>>> return 0;
>>>>>>> - return ops->unmap(ops, iova, size);
>>>>>>> + pm_runtime_get_sync(smmu_domain->smmu->dev);
>>>>>> Can these map/unmap ops be called from an atomic context? I seem
>>>>>> to recall that being a problem before.
>>>>>
>>>>> That's something which was dropped in the following patch merged in master:
>>>>> 523d7423e21b iommu/arm-smmu: Remove io-pgtable spinlock
>>>>>
>>>>> Looks like we don't need locks here anymore?
>>>>
>>>> Apart from the locking, wonder why a explicit pm_runtime is needed
>>>> from unmap. Somehow looks like some path in the master using that
>>>> should have enabled the pm ?
>>>>
>>>
>>> Yes, there are a bunch of scenarios where unmap can happen with
>>> disabled master (but not in atomic context).
>>
>> I would like to understand whether there is a situation where an unmap is
>> called in atomic context without an enabled master?
>>
>> Let's say we have the case where all the unmap calls in atomic context happen
>> only from the master's context (in which case the device link should
>> take care of
>> the pm state of smmu), and the only unmap that happen in non-atomic context
>> is the one with master disabled. In such a case doesn it make sense to
>> distinguish
>> the atomic/non-atomic context and add pm_runtime_get_sync()/put_sync() only
>> for the non-atomic context since that would be the one with master disabled.
>>
>
> At least drm/msm needs to hold obj->lock (a mutex) in unmap, so it
> won't unmap anything in atomic ctx (but it can unmap w/ master
> disabled). I can't really comment about other non-gpu drivers. It
> seems like a reasonable constraint that either master is enabled or
> not in atomic ctx.
>
> Currently we actually wrap unmap w/ pm_runtime_get/put_sync(), but I'd
> like to drop that to avoid powering up the gpu.
Since the deferring the TLB maintenance doesn't look like the best approach [1],
how about if we try to power-up only the smmu from different client
devices such as,
GPU in the unmap path. Then we won't need to add pm_runtime_get/put() calls in
arm_smmu_unmap().
The client device can use something like - pm_runtime_get_supplier() since
we already have the device link in place with this patch series. This should
power-on the supplier (which is smmu) without turning on the consumer
(such as GPU).
pm_runtime_get_supplier() however is not exported at this moment.
Will it be useful to export this API and use it in the drivers.
Adding Rafael J. Wysocki for suggestions on pm_runtime_get_suppliers() API.
[1] https://patchwork.kernel.org/patch/9876489/
Best regards
Vivek
>
> BR,
> -R
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^ permalink raw reply
* Re: [PATCH v9 3/7] mailbox: qcom: Move the apcs struct into a separate header
From: Stephen Boyd @ 2017-11-14 18:12 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Georgi Djakov, jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171114044702.GF28761@minitux>
On 11/13, Bjorn Andersson wrote:
> On Mon 13 Nov 18:12 PST 2017, Stephen Boyd wrote:
>
> > On 10/27, Georgi Djakov wrote:
> > > Hi Bjorn,
> > >
> > > Thanks for reviewing!
> > >
> > > On 10/26/2017 07:28 AM, Bjorn Andersson wrote:
> > > > On Thu 21 Sep 09:49 PDT 2017, Georgi Djakov wrote:
> > > >
> > > >> Move the structure shared by the APCS IPC device and its subdevices
> > > >> into a separate header file.
> > > >>
> > > >
> > > > As you're creating the apcs regmap with devm_regmap_init_mmio() you can
> > > > just call dev_get_regmap(dev->parent) in your child to get the handle.
> > >
> > > Ok, thanks!
> > >
> > > >
> > > > But I would prefer that you just add the clock code to the existing
> > > > driver.
> > >
> > > This will require an ack from Stephen, and i got the impression that he
> > > prefers a separate clk driver [1].
> > >
> > > Stephen, are you ok with registering the clocks from the apcs mailbox
> > > driver?
> > >
> > > [1] https://lkml.org/lkml/2017/6/26/750
> >
> > The parent regmap "trick" was the plan. Is something wrong with
> > that?
> >
>
> Not at all, but then this patch (moving apcs context to a shared header
> file) shouldn't be needed, or am I missing something?
Agreed.
>
> > Not having random clk drivers scattered throughout the tree is
> > sort of nice because it makes for an easier time finding things
> > that are similar. Maybe that's an abuse of the driver model
> > though? Just to get things into some same directory. I'm fine
> > either way.
> >
>
> Keeping the clock driver in the clock subsystem does make sense. I see
> now that there is a include of a local header file as well, so that
> would just be messy to keep split.
>
> I'm fine with the extra driver instance, it's the DT that I don't think
> should describe the fact that we want to keep the clock-part in the
> clock subsystem.
>
> Do you see any problems spawning the clock driver programmatically and
> then calling of_clk_add_hw_provider() on the parent's of_node?
Nope. We shouldn't need to modify DT to make this work.
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^ permalink raw reply
* [PATCH 3/3] arm: dts: owl-s500: Add Sparky
From: Andreas Färber @ 2017-11-14 18:01 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Liau, Jeff Chen, 张东风,
刘炜, 张天益, 梅利,
Ioan B, Sudeep Kumar, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Andreas Färber, Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171114180114.26408-1-afaerber-l3A5Bk7waGM@public.gmane.org>
Add a Device Tree for the Allo.com Sparky SBC.
Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/owl-s500-sparky.dts | 44 +++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/owl-s500-sparky.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0381e9caf21..ad77f7656a70 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -707,7 +707,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
orion5x-rd88f5182-nas.dtb
dtb-$(CONFIG_ARCH_ACTIONS) += \
owl-s500-cubieboard6.dtb \
- owl-s500-guitar-bb-rev-b.dtb
+ owl-s500-guitar-bb-rev-b.dtb \
+ owl-s500-sparky.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
dtb-$(CONFIG_ARCH_OXNAS) += \
diff --git a/arch/arm/boot/dts/owl-s500-sparky.dts b/arch/arm/boot/dts/owl-s500-sparky.dts
new file mode 100644
index 000000000000..f620548c6c0b
--- /dev/null
+++ b/arch/arm/boot/dts/owl-s500-sparky.dts
@@ -0,0 +1,44 @@
+/*
+ * Allo.com Sparky
+ *
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include "owl-s500.dtsi"
+
+/ {
+ compatible = "allo,sparky", "actions,s500";
+ model = "Allo.com Sparky";
+
+ aliases {
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1 or 2 GiB */
+ };
+
+ uart3_clk: uart3-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <921600>;
+ #clock-cells = <0>;
+ };
+};
+
+&timer {
+ clocks = <&hosc>;
+};
+
+&uart3 {
+ status = "okay";
+ clocks = <&uart3_clk>;
+};
--
2.13.6
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* [PATCH 2/3] dt-bindings: arm: actions: Add Sparky
From: Andreas Färber @ 2017-11-14 18:01 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Liau, Jeff Chen, 张东风,
刘炜, 张天益, 梅利,
Ioan B, Sudeep Kumar, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Andreas Färber, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171114180114.26408-1-afaerber-l3A5Bk7waGM@public.gmane.org>
Define a binding for Allo.com Sparky SBC.
Cc: Ioan B. <ioan-HmMszb9TTf4@public.gmane.org>
Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
---
Documentation/devicetree/bindings/arm/actions.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/actions.txt b/Documentation/devicetree/bindings/arm/actions.txt
index 544a8855fad5..d54f33c4e0da 100644
--- a/Documentation/devicetree/bindings/arm/actions.txt
+++ b/Documentation/devicetree/bindings/arm/actions.txt
@@ -21,6 +21,7 @@ Boards:
Root node property compatible must contain, depending on board:
+ - Allo.com Sparky: "allo,sparky"
- Cubietech CubieBoard6: "cubietech,cubieboard6"
- LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar"
--
2.13.6
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* [PATCH 1/3] dt-bindings: Add vendor prefix for Allo.com
From: Andreas Färber @ 2017-11-14 18:01 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Liau, Jeff Chen, 张东风,
刘炜, 张天益, 梅利,
Ioan B, Sudeep Kumar, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Andreas Färber, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171114180114.26408-1-afaerber-l3A5Bk7waGM@public.gmane.org>
ALLO is a Canadian-Indian manufacturer of telecommunications hardware.
Cc: Ioan B. <ioan-HmMszb9TTf4@public.gmane.org>
Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 0994bdd82cd3..9bce76f3118d 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -15,6 +15,7 @@ adi Analog Devices, Inc.
advantech Advantech Corporation
aeroflexgaisler Aeroflex Gaisler AB
al Annapurna Labs
+allo Allo.com
allwinner Allwinner Technology Co., Ltd.
alphascale AlphaScale Integrated Circuits Systems, Inc.
altr Altera Corp.
--
2.13.6
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* [PATCH 0/3] arm: owl: Add initial Allo Sparky support
From: Andreas Färber @ 2017-11-14 18:01 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Thomas Liau, Jeff Chen, 张东风,
刘炜, 张天益, 梅利,
Ioan B, Sudeep Kumar, linux-kernel, Andreas Färber,
Andre M . Strul, devicetree
Hello,
This series adds a Device Tree for the Allo.com Sparky SBC.
Cf. https://en.opensuse.org/HCL:Sparky
Work branch:
https://github.com/afaerber/linux/commits/bg96-next
Have a lot of fun!
Cheers,
Andreas
Cc: Andre M. Strul <andre@allo.com>
Cc: Ioan B. <ioan@allo.com>
Cc: Sudeep Kumar <sudeepkumar@cem-solutions.net>
Cc: Jeff Chen <jeff.chen@actions-semi.com>
Cc: devicetree@vger.kernel.org
Andreas Färber (3):
dt-bindings: Add vendor prefix for Allo.com
dt-bindings: arm: actions: Add Sparky
arm: dts: owl-s500: Add Sparky
Documentation/devicetree/bindings/arm/actions.txt | 1 +
.../devicetree/bindings/vendor-prefixes.txt | 1 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/owl-s500-sparky.dts | 44 ++++++++++++++++++++++
4 files changed, 48 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/owl-s500-sparky.dts
--
2.13.6
^ permalink raw reply
* Re: [PATCH 3/3] arm64: dts: renesas: eagle: add EtherAVB pins
From: Sergei Shtylyov @ 2017-11-14 18:00 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
Linux-Renesas, devicetree@vger.kernel.org, Magnus Damm,
Mark Rutland, linux-arm-kernel@lists.infradead.org
In-Reply-To: <CAMuHMdWCj=CjA_zyC1GKr=KEk2CNMAtwvREw25R1uJktZucY4w@mail.gmail.com>
Hello.
On 11/14/2017 11:44 AM, Geert Uytterhoeven wrote:
>> Add the (previously omitted) EtherAVB pin data to the Eagle board's
>> device tree.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Thanks for your patch!
>
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
>> @@ -34,6 +34,9 @@
[...]
>> @@ -53,6 +56,11 @@
>> };
>>
>> &pfc {
>> + avb_pins: avb {
>> + groups = "avb0_mdio", "avb0_mii";
>
> Oh no, its'called "avb0_mdio" here, but "avb(0)_mdc" on all other
> R-Car Gen3 SoCs?
Can you remember the reason? I don;t want to follow the bad example. :-)
> What about "avb0_link", which is connected through "L_LNK"?
The same as for other gen3 board, the AVB node has renesas,no-ether-link".
I tried to verify that property on Eagle, and left it intact as a result...
Will re-test removing it once more.
[...]
> Gr{oetje,eeting}s,
>
> Geert
MBR, Sergei
^ permalink raw reply
* Re: [PATCH] MIPS: implement a "bootargs-append" DT property
From: Rob Herring @ 2017-11-14 17:18 UTC (permalink / raw)
To: Daniel Gimpelevich
Cc: James Hogan, Linux-MIPS, Frank Rowand,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Geert Uytterhoeven
In-Reply-To: <1510628754.14209.27.camel@chimera>
On Mon, Nov 13, 2017 at 9:05 PM, Daniel Gimpelevich
<daniel-R/FLGEdV95bo9U+Z1CfBt0SU0eOFXohjCypLqA8HKkk@public.gmane.org> wrote:
> On Mon, 2017-11-13 at 10:34 -0600, Rob Herring wrote:
>> This is a kernel problem. What's the use case where you want the DT to
>> override the kernel?
>>
>> One way you could handle this is make bootargs be multiple strings.
>> Well 2 specifically, the first string is prepended and the 2nd is
>> appended. That complicates how you'd implement /append-property/
>> though as you'd probably want to support both string cat and 2
>> strings. Though the latter works more generically without knowing the
>> data type.
>
> Let's say the bootloader tells the kernel that the command line is "foo
> bar" and that "baz" is in the dtb. Currently, there are kernel
> configuration options to control whether this means the kernel's command
> line will be "baz" or "baz foo bar" instead, but there is no way to turn
> it into "foo bar baz" without either creating new kernel configuration
> options or this patch. Implementing it via this patch would allow a
> theoretical distro to use a generic kernel across different devices that
> need the arguments from their bootloader manipulated in different ways.
I understand you can't apply random strings in any order you like. I'm
questioning the need to do that and what are the concrete example(s)
where you need that ability.
I'd generally expect that only board specific options are in the dtb,
and a distro will add it's own options common for all and the specific
arch into the bootloader config files. And generally, the last thing
loaded gets the last say in what is set.
> Ideally, the MIPS-specific kernel configuration options for how to treat
> the dtb's bootargs with respect to the bootloader's bootargs should go
> away in favor of an analogous device tree property "bootargs-prepend"
> for this reason. The kernel configuration options to supply a hard-coded
> default command line if the bootloader does not supply one, and to
> override what the bootloader and dtb supply, would remain. This would
> separate the need for an alternate or "recovery" kernel to supply its
> own bootargs to override the dtb from the need to have device-specific
> bootargs in the dtb override a legacy bootloader, where the manner its
> bootargs are overridden may be device-specific.
What h/w specific options would be needed for recovery kernel? That's
getting into putting not just Linux specifics into the dtb, but distro
specifics there. While yes, the dts files often already have bootargs
filled with Linux options, the intention is really that the bootloader
fills in bootargs. And if you have multiple kernels or OSs, then the
bootloader provides the mechanism to choose and boot with the right
options.
I think the kernel (being last) should fully decide what to do:
append, prepend, and/or override. There was some work a while back to
support more flexible command line handling and be arch neutral, but
it never got merged.
Rob
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^ permalink raw reply
* Private Investition
From: Khvostova Zhanna @ 2017-11-14 17:17 UTC (permalink / raw)
Diese E-Mail fordert Sie strikt auf, sich für eine große Investition mit
mir zusammenzutun, um weitere Informationen zu erhalten.
Mit freundlichen Grüßen,
Khvostova Zhanna
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