* [PATCH 6/7] can: rcar_can: document r8a77995 (R-Car D3) compatibility strings
From: Ulrich Hecht @ 2017-11-17 10:41 UTC (permalink / raw)
To: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
Cc: linux-can-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, wsa-z923LK4zBo2bacvFa/9K2g,
horms-/R6kz+dDXgpPR4JQBCEnsQ, geert-Td1EMuHUCqxL1ZNQvxDV9g,
magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
chris.paterson2-zM6kxYcvzFBBDgjK7y7TUQ,
ramesh.shanmugasundaram-kTT6dE0pTRh9uiUsa/gSgQ, Ulrich Hecht
In-Reply-To: <1510915289-15059-1-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
Documentation/devicetree/bindings/net/can/rcar_can.txt | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt
index 06bb7cc..f7d0358 100644
--- a/Documentation/devicetree/bindings/net/can/rcar_can.txt
+++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt
@@ -11,6 +11,7 @@ Required properties:
"renesas,can-r8a7794" if CAN controller is a part of R8A7794 SoC.
"renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC.
"renesas,can-r8a7796" if CAN controller is a part of R8A7796 SoC.
+ "renesas,can-r8a77995" if CAN controller is a part of R8A77995 SoC.
"renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible device.
"renesas,rcar-gen2-can" for a generic R-Car Gen2 compatible device.
"renesas,rcar-gen3-can" for a generic R-Car Gen3 compatible device.
@@ -25,12 +26,12 @@ Required properties:
- pinctrl-0: pin control group to be used for this controller.
- pinctrl-names: must be "default".
-Required properties for "renesas,can-r8a7795" and "renesas,can-r8a7796"
-compatible:
-In R8A7795 and R8A7796 SoCs, "clkp2" can be CANFD clock. This is a div6 clock
-and can be used by both CAN and CAN FD controller at the same time. It needs to
-be scaled to maximum frequency if any of these controllers use it. This is done
-using the below properties:
+Required properties for "renesas,can-r8a7795", "renesas,can-r8a7796" and
+"renesas,can-r8a77995" compatible:
+In R8A7795, R8A7796 and R8A77995 SoCs, "clkp2" can be CANFD clock. This is a
+div6 clock and can be used by both CAN and CAN FD controller at the same
+time. It needs to be scaled to maximum frequency if any of these
+controllers use it. This is done using the below properties:
- assigned-clocks: phandle of clkp2(CANFD) clock.
- assigned-clock-rates: maximum frequency of this clock.
--
2.7.4
--
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* [PATCH 5/7] arm64: dts: r8a77995: Add CAN FD support
From: Ulrich Hecht @ 2017-11-17 10:41 UTC (permalink / raw)
To: linux-renesas-soc
Cc: linux-can, devicetree, wsa, horms, geert, magnus.damm,
chris.paterson2, ramesh.shanmugasundaram, Ulrich Hecht
In-Reply-To: <1510915289-15059-1-git-send-email-ulrich.hecht+renesas@gmail.com>
Adds CAN FD controller node for r8a77995.
Based on a patch for r8a7796 by Chris Paterson.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index a611324..6648c9b 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -306,6 +306,31 @@
status = "disabled";
};
+ canfd: can@e66c0000 {
+ compatible = "renesas,r8a77995-canfd",
+ "renesas,rcar-gen3-canfd";
+ reg = <0 0xe66c0000 0 0x8000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 914>,
+ <&cpg CPG_CORE R8A77995_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "fck", "canfd", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 914>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+
+ channel1 {
+ status = "disabled";
+ };
+ };
+
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77995",
"renesas,etheravb-rcar-gen3";
--
2.7.4
^ permalink raw reply related
* [PATCH 4/7] arm64: dts: r8a77995: Add CAN support
From: Ulrich Hecht @ 2017-11-17 10:41 UTC (permalink / raw)
To: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
Cc: linux-can-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, wsa-z923LK4zBo2bacvFa/9K2g,
horms-/R6kz+dDXgpPR4JQBCEnsQ, geert-Td1EMuHUCqxL1ZNQvxDV9g,
magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
chris.paterson2-zM6kxYcvzFBBDgjK7y7TUQ,
ramesh.shanmugasundaram-kTT6dE0pTRh9uiUsa/gSgQ, Ulrich Hecht
In-Reply-To: <1510915289-15059-1-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Adds CAN controller nodes for r8a77995.
Based on a patch for r8a7796 by Chris Paterson.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 32 +++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index a8df296..a611324 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -274,6 +274,38 @@
resets = <&cpg 906>;
};
+ can0: can@e6c30000 {
+ compatible = "renesas,can-r8a77995",
+ "renesas,rcar-gen3-can";
+ reg = <0 0xe6c30000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>,
+ <&cpg CPG_CORE R8A77995_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
+ };
+
+ can1: can@e6c38000 {
+ compatible = "renesas,can-r8a77995",
+ "renesas,rcar-gen3-can";
+ reg = <0 0xe6c38000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>,
+ <&cpg CPG_CORE R8A77995_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
+ };
+
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77995",
"renesas,etheravb-rcar-gen3";
--
2.7.4
--
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^ permalink raw reply related
* [PATCH 3/7] arm64: dts: r8a77995: Add CAN external clock support
From: Ulrich Hecht @ 2017-11-17 10:41 UTC (permalink / raw)
To: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
Cc: linux-can-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, wsa-z923LK4zBo2bacvFa/9K2g,
horms-/R6kz+dDXgpPR4JQBCEnsQ, geert-Td1EMuHUCqxL1ZNQvxDV9g,
magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
chris.paterson2-zM6kxYcvzFBBDgjK7y7TUQ,
ramesh.shanmugasundaram-kTT6dE0pTRh9uiUsa/gSgQ, Ulrich Hecht
In-Reply-To: <1510915289-15059-1-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Adds external CAN clock node for r8a77995. This clock can be used as
fCAN clock of CAN and CAN FD controller.
Based on a patch for r8a7796 by Chris Paterson.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 788e3af..a8df296 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -51,6 +51,13 @@
clock-frequency = <0>;
};
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
--
2.7.4
--
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^ permalink raw reply related
* [PATCH 2/7] pinctrl: sh-pfc: r8a77995: Add CAN FD support
From: Ulrich Hecht @ 2017-11-17 10:41 UTC (permalink / raw)
To: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
Cc: linux-can-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, wsa-z923LK4zBo2bacvFa/9K2g,
horms-/R6kz+dDXgpPR4JQBCEnsQ, geert-Td1EMuHUCqxL1ZNQvxDV9g,
magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
chris.paterson2-zM6kxYcvzFBBDgjK7y7TUQ,
ramesh.shanmugasundaram-kTT6dE0pTRh9uiUsa/gSgQ, Ulrich Hecht
In-Reply-To: <1510915289-15059-1-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
This patch adds CAN FD[0-1] pinmux support to the r8a77995 SoC.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index 616854d..e7849a4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -1096,6 +1096,22 @@ static const unsigned int can_clk_mux[] = {
CAN_CLK_MARK,
};
+/* - CAN FD ----------------------------------------------------------------- */
+static const unsigned int canfd0_data_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
+};
+static const unsigned int canfd0_data_mux[] = {
+ CANFD0_TX_MARK, CANFD0_RX_MARK,
+};
+static const unsigned int canfd1_data_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int canfd1_data_mux[] = {
+ CANFD1_TX_MARK, CANFD1_RX_MARK,
+};
+
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
@@ -1548,6 +1564,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(can1_data_a),
SH_PFC_PIN_GROUP(can1_data_b),
SH_PFC_PIN_GROUP(can_clk),
+ SH_PFC_PIN_GROUP(canfd0_data),
+ SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c2_a),
@@ -1637,6 +1655,13 @@ static const char * const can_clk_groups[] = {
"can_clk",
};
+static const char * const canfd0_groups[] = {
+ "canfd0_data",
+};
+static const char * const canfd1_groups[] = {
+ "canfd1_data",
+};
+
static const char * const i2c0_groups[] = {
"i2c0",
};
@@ -1750,6 +1775,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
--
2.7.4
--
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^ permalink raw reply related
* [PATCH 1/7] pinctrl: sh-pfc: r8a77995: Add CAN support
From: Ulrich Hecht @ 2017-11-17 10:41 UTC (permalink / raw)
To: linux-renesas-soc
Cc: linux-can, devicetree, wsa, horms, geert, magnus.damm,
chris.paterson2, ramesh.shanmugasundaram, Ulrich Hecht
In-Reply-To: <1510915289-15059-1-git-send-email-ulrich.hecht+renesas@gmail.com>
This patch adds CAN[0-1] pinmux support to the r8a77995 SoC.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 59 +++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index 89b7541..616854d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -1057,6 +1057,45 @@ static const unsigned int avb0_avtp_capture_b_mux[] = {
AVB0_AVTP_CAPTURE_B_MARK,
};
+/* - CAN ------------------------------------------------------------------ */
+static const unsigned int can0_data_a_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
+};
+static const unsigned int can0_data_a_mux[] = {
+ CAN0_TX_A_MARK, CAN0_RX_A_MARK,
+};
+static const unsigned int can0_data_b_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int can0_data_b_mux[] = {
+ CAN0_TX_B_MARK, CAN0_RX_B_MARK,
+};
+static const unsigned int can1_data_a_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int can1_data_a_mux[] = {
+ CAN1_TX_A_MARK, CAN1_RX_A_MARK,
+};
+static const unsigned int can1_data_b_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
+};
+static const unsigned int can1_data_b_mux[] = {
+ CAN1_TX_B_MARK, CAN1_RX_B_MARK,
+};
+
+/* - CAN Clock -------------------------------------------------------------- */
+static const unsigned int can_clk_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(5, 2),
+};
+static const unsigned int can_clk_mux[] = {
+ CAN_CLK_MARK,
+};
+
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
@@ -1504,6 +1543,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
SH_PFC_PIN_GROUP(avb0_avtp_match_b),
SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
+ SH_PFC_PIN_GROUP(can0_data_a),
+ SH_PFC_PIN_GROUP(can0_data_b),
+ SH_PFC_PIN_GROUP(can1_data_a),
+ SH_PFC_PIN_GROUP(can1_data_b),
+ SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c2_a),
@@ -1581,6 +1625,18 @@ static const char * const avb0_groups[] = {
"avb0_avtp_capture_b",
};
+static const char * const can0_groups[] = {
+ "can0_data_a",
+ "can0_data_b",
+};
+static const char * const can1_groups[] = {
+ "can1_data_a",
+ "can1_data_b",
+};
+static const char * const can_clk_groups[] = {
+ "can_clk",
+};
+
static const char * const i2c0_groups[] = {
"i2c0",
};
@@ -1691,6 +1747,9 @@ static const char * const usb0_groups[] = {
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb0),
+ SH_PFC_FUNCTION(can0),
+ SH_PFC_FUNCTION(can1),
+ SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
--
2.7.4
^ permalink raw reply related
* [PATCH 0/7] R-Car D3 (r8a77995) CAN support
From: Ulrich Hecht @ 2017-11-17 10:41 UTC (permalink / raw)
To: linux-renesas-soc
Cc: linux-can, devicetree, wsa, horms, geert, magnus.damm,
chris.paterson2, ramesh.shanmugasundaram, Ulrich Hecht
Hi!
Here's CAN and CAN FD support for the R-Car D3. This is a by-the-datasheet
implementation, with the datasheet missing some bits, namely the pin map.
I filled in the gaps with frog DNA^W^W^Wby deducing the information from
pin numbers already in the PFC driver, so careful scrutiny is advised.
CU
Uli
Ulrich Hecht (7):
pinctrl: sh-pfc: r8a77995: Add CAN support
pinctrl: sh-pfc: r8a77995: Add CAN FD support
arm64: dts: r8a77995: Add CAN external clock support
arm64: dts: r8a77995: Add CAN support
arm64: dts: r8a77995: Add CAN FD support
can: rcar_can: document r8a77995 (R-Car D3) compatibility strings
can: rcar_canfd: document r8a77995 (R-Car D3) compatibility strings
.../devicetree/bindings/net/can/rcar_can.txt | 13 ++--
.../devicetree/bindings/net/can/rcar_canfd.txt | 13 ++--
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 64 ++++++++++++++++
drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 86 ++++++++++++++++++++++
4 files changed, 164 insertions(+), 12 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH 2/2] ARM: dts: Add the support for display5 equipped with Tianma (800x480) display
From: Lukasz Majewski @ 2017-11-17 10:24 UTC (permalink / raw)
To: Rob Herring
Cc: Rob Herring, Mark Rutland, Russell King, Shawn Guo, Sascha Hauer,
Fabio Estevam, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Lukasz Majewski
In-Reply-To: <20171117102404.6678-1-lukma-ynQEQJNshbs@public.gmane.org>
Signed-off-by: Lukasz Majewski <lukma-ynQEQJNshbs@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 1 +
.../dts/imx6q-display5-tianma-tm070-800x480.dts | 51 ++++++++++++++++++++++
2 files changed, 52 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-display5-tianma-tm070-800x480.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 10b3ad078dea..699c23b83b7f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -409,6 +409,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-dfi-fs700-m60.dtb \
imx6q-display5-mitsubishi-aa070-800x480.dtb \
imx6q-display5-tianma-tm070-1280x768.dtb \
+ imx6q-display5-tianma-tm070-800x480.dtb \
imx6q-dmo-edmqmx6.dtb \
imx6q-evi.dtb \
imx6q-gk802.dtb \
diff --git a/arch/arm/boot/dts/imx6q-display5-tianma-tm070-800x480.dts b/arch/arm/boot/dts/imx6q-display5-tianma-tm070-800x480.dts
new file mode 100644
index 000000000000..0c5655a08f3b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-display5-tianma-tm070-800x480.dts
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2017
+ * Lukasz Majewski, DENX Software Engineering, lukma-ynQEQJNshbs@public.gmane.org
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE
+ */
+
+/dts-v1/;
+
+#include "imx6q-display5.dtsi"
+
+&panel {
+ compatible = "tianma,tm070rvhg71";
+};
+
+&ldb {
+ lvds0: lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ };
+};
--
2.11.0
--
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* [PATCH 1/2] ARM: dts: Add the support for display5 equipped with Mitsubishi (800x480) display
From: Lukasz Majewski @ 2017-11-17 10:24 UTC (permalink / raw)
To: Rob Herring
Cc: Rob Herring, Mark Rutland, Russell King, Shawn Guo, Sascha Hauer,
Fabio Estevam, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Lukasz Majewski
This is the support for aa070mc01-ca1 Mitsubishi display.
Signed-off-by: Lukasz Majewski <lukma-ynQEQJNshbs@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 1 +
.../imx6q-display5-mitsubishi-aa070-800x480.dts | 51 ++++++++++++++++++++++
2 files changed, 52 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-display5-mitsubishi-aa070-800x480.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d9d0c82e7d20..10b3ad078dea 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -407,6 +407,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
+ imx6q-display5-mitsubishi-aa070-800x480.dtb \
imx6q-display5-tianma-tm070-1280x768.dtb \
imx6q-dmo-edmqmx6.dtb \
imx6q-evi.dtb \
diff --git a/arch/arm/boot/dts/imx6q-display5-mitsubishi-aa070-800x480.dts b/arch/arm/boot/dts/imx6q-display5-mitsubishi-aa070-800x480.dts
new file mode 100644
index 000000000000..ea4c292cb74b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-display5-mitsubishi-aa070-800x480.dts
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2017
+ * Lukasz Majewski, DENX Software Engineering, lukma-ynQEQJNshbs@public.gmane.org
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q-display5.dtsi"
+
+&panel {
+ compatible = "mitsubishi,aa070mc01-ca1";
+};
+
+&ldb {
+ lvds0: lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ };
+};
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related
* Re: [PATCH v3] display: panel: Add Mitsubishi aa070mc01 display support (800x480)
From: Lukasz Majewski @ 2017-11-17 10:03 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Thierry Reding, David Airlie
Cc: dri-devel, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAL_JsqLf2Kpbe5NK3-xLPr4kYDWXPgriA6Lwd_4huQPyKGOQ6Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
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Dear All,
> On Fri, Oct 20, 2017 at 5:18 PM, Lukasz Majewski <lukma-ynQEQJNshbs@public.gmane.org>
> wrote:
> > This commit adds support for Mitsubishi aa070mc01 TFT panel working
> > with 8 bit ISP mode (pin 19 "mode" HIGH for 20 pin TFT connector).
> >
> > Signed-off-by: Lukasz Majewski <lukma-ynQEQJNshbs@public.gmane.org>
> > ---
> > Changes for v2:
> > - Place the code sorted alphabetically
> > - Add missing ./Documentation/devicetree/binding/display properties
> > description
> >
> > Changes for v3:
> > - Fix typo in display name (in property description)
> >
> > ---
> > .../display/panel/mitsubishi,aa070mc01.txt | 7 +++++
> > drivers/gpu/drm/panel/panel-simple.c | 35
> > ++++++++++++++++++++++ 2 files changed, 42 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/panel/mitsubishi,aa070mc01.txt
>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Is there a chance that this patch will find its way to v4.15-rc1 ?
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd-ynQEQJNshbs@public.gmane.org
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^ permalink raw reply
* Re: [PATCH v2] display: panel: Add Tianma tm070rvhg71 display support (800x480)
From: Lukasz Majewski @ 2017-11-17 10:02 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Thierry Reding
Cc: David Airlie, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171110212423.jddj5kw32voms2oj@rob-hp-laptop>
[-- Attachment #1: Type: text/plain, Size: 1057 bytes --]
Dear All,
> On Tue, Nov 07, 2017 at 04:30:58PM +0100, Lukasz Majewski wrote:
> > Signed-off-by: Lukasz Majewski <lukma-ynQEQJNshbs@public.gmane.org>
> >
> > ---
> > Changes for v2:
> > - Provide more
> > detailed ./Documentation/devicetree/bindings/display/panel entry to
> > describe this panel device. ---
> > .../bindings/display/panel/tianma,tm070rvhg71.txt | 29
> > ++++++++++++++++++++++
> > drivers/gpu/drm/panel/panel-simple.c | 27
> > ++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode
> > 100644
> > Documentation/devicetree/bindings/display/panel/tianma,tm070rvhg71.txt
>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Is there a chance that this patch will find its way to v4.15-rc1 ?
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd-ynQEQJNshbs@public.gmane.org
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH V5] clk: qcom: Add spmi_pmic clock divider support
From: Tirupathi Reddy T @ 2017-11-17 10:01 UTC (permalink / raw)
To: Stephen Boyd
Cc: mturquette-rdvid1DuHRBWk0Htik3J/w, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, andy.gross-QSEj5FYQhm4dnm+yROfE0A,
david.brown-QSEj5FYQhm4dnm+yROfE0A,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171115170647.GR11955-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On 11/15/2017 10:36 PM, Stephen Boyd wrote:
> On 09/19, Tirupathi Reddy wrote:
>> diff --git a/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt b/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt
>> new file mode 100644
>> index 0000000..e37a136
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt
>> @@ -0,0 +1,56 @@
>> +Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)
>> +
>> +clkdiv configures the clock frequency of a set of outputs on the PMIC.
>> +These clocks are typically wired through alternate functions on
>> +gpio pins.
>> +
>> +=======================
>> +Properties
>> +=======================
>> +
>> +- compatible
>> + Usage: required
>> + Value type: <string>
>> + Definition: must be one of:
>> + "qcom,spmi-clkdiv"
>> + "qcom,pm8998-clkdiv"
>> +
>> +- reg
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: Addresses and sizes for the memory of this CLKDIV
> There's no size though.
Fixed in Patch version 6.
>
>> + peripheral.
>> +
>> +- clocks:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: reference to the xo clock.
>> +
>> +- clock-names:
>> + Usage: required
>> + Value type: <stringlist>
>> + Definition: must be "xo".
>> +
>> +- clock-cells:
>> + Usage: required
>> + Value type: <u32>
>> + Definition: shall contain 1.
> Can we get a property to indicate the number of clks? Something
> like "qcom,num-clkdivs" or something like that. That would make
> things easier to handle in the driver because we could match the
> generic compatible and look for the property and then populate
> that many clks. Otherwise, we're going to need a "small" driver
> update for each PMIC just because the number of clks changes.
>
> Of course we're going to need to update the binding to add the
> new PMIC compatibles as new things are created, but I'd like to
> avoid driver updates for the compatible. If someone messes up the
> number we can always fallback to matching the more specific
> compatible and fix it up in the driver, but let's hope that
> doesn't happen.
Fixed in Patch version 6.
>
>> +
>> +=======
>> +Example
>> +=======
>> +
>> +pm8998_clk_divs: qcom,clock@5b00 {
> clock-controller@5b00?
Fixed in Patch version 6.
>
>> + compatible = "qcom,pm8998-clkdiv";
>> + reg = <0x5b00>;
>> + #clock-cells = <1>;
>> + clocks = <&xo_board>;
>> + clock-names = "xo";
>> +
>> + assigned-clocks = <&pm8998_clk_divs 1>,
>> + <&pm8998_clk_divs 2>,
>> + <&pm8998_clk_divs 3>;
>> + assigned-clock-rates = <9600000>,
>> + <9600000>,
>> + <9600000>;
>> +};
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 9f6c278..dd5b18e 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -196,3 +196,12 @@ config MSM_MMCC_8996
>> Support for the multimedia clock controller on msm8996 devices.
>> Say Y if you want to support multimedia devices such as display,
>> graphics, video encode/decode, camera, etc.
>> +
>> +config SPMI_PMIC_CLKDIV
>> + tristate "spmi pmic clkdiv driver"
> Capitalize SPMI and PMIC and replace driver with something else.
Fixed in Patch version 6.
>
>> + depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
>> + help
>> + This driver supports the clkdiv functionality on the Qualcomm
>> + Technologies, Inc. SPMI PMIC. It configures the frequency of
>> + clkdiv outputs on the PMIC. These clocks are typically wired
>> + through alternate functions on gpio pins.
> I rewrote a bunch of stuff in the driver. Let me know if anything
> doesn't work.
Verified. The changes look good.
>
> ----8<----
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index dd5b18ecd9d1..20b5d6fd501d 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -198,10 +198,10 @@ config MSM_MMCC_8996
> graphics, video encode/decode, camera, etc.
>
> config SPMI_PMIC_CLKDIV
> - tristate "spmi pmic clkdiv driver"
> + tristate "SPMI PMIC clkdiv Support"
> depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
> help
> This driver supports the clkdiv functionality on the Qualcomm
> Technologies, Inc. SPMI PMIC. It configures the frequency of
> - clkdiv outputs on the PMIC. These clocks are typically wired
> - through alternate functions on gpio pins.
> + clkdiv outputs of the PMIC. These clocks are typically wired
> + through alternate functions on GPIO pins.
> diff --git a/drivers/clk/qcom/clk-spmi-pmic-div.c b/drivers/clk/qcom/clk-spmi-pmic-div.c
> index af343ad2ee0b..a7217ee9f741 100644
> --- a/drivers/clk/qcom/clk-spmi-pmic-div.c
> +++ b/drivers/clk/qcom/clk-spmi-pmic-div.c
> @@ -18,6 +18,7 @@
> #include <linux/log2.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/slab.h>
> @@ -29,29 +30,12 @@
> #define REG_EN_CTL 0x46
> #define REG_EN_MASK BIT(7)
>
> -#define ENABLE_DELAY_NS(cxo_ns, div) ((2 + 3 * div) * cxo_ns)
> -#define DISABLE_DELAY_NS(cxo_ns, div) ((3 * div) * cxo_ns)
> -
> -#define CLK_SPMI_PMIC_DIV_OFFSET 1
> -
> -#define CLKDIV_XO_DIV_1_0 0
> -#define CLKDIV_XO_DIV_1 1
> -#define CLKDIV_XO_DIV_2 2
> -#define CLKDIV_XO_DIV_4 3
> -#define CLKDIV_XO_DIV_8 4
> -#define CLKDIV_XO_DIV_16 5
> -#define CLKDIV_XO_DIV_32 6
> -#define CLKDIV_XO_DIV_64 7
> -#define CLKDIV_MAX_ALLOWED 8
> -
> struct clkdiv {
> struct regmap *regmap;
> u16 base;
> spinlock_t lock;
>
> - /* clock properties */
> struct clk_hw hw;
> - unsigned int div_factor;
> unsigned int cxo_period_ns;
> };
>
> @@ -62,94 +46,68 @@ static inline struct clkdiv *to_clkdiv(struct clk_hw *hw)
>
> static inline unsigned int div_factor_to_div(unsigned int div_factor)
> {
> - if (div_factor == CLKDIV_XO_DIV_1_0)
> - return 1;
> + if (!div_factor)
> + div_factor = 1;
>
> - return 1 << (div_factor - CLK_SPMI_PMIC_DIV_OFFSET);
> + return 1 << (div_factor - 1);
> }
>
> static inline unsigned int div_to_div_factor(unsigned int div)
> {
> - return min(ilog2(div) + CLK_SPMI_PMIC_DIV_OFFSET,
> - CLKDIV_MAX_ALLOWED - 1);
> + return min(ilog2(div) + 1, 7);
> }
>
> static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv)
> {
> unsigned int val = 0;
>
> - regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL,
> - &val);
> - return (val & REG_EN_MASK) ? true : false;
> + regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val);
> +
> + return val & REG_EN_MASK;
> }
>
> -static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv,
> - bool enable_state)
> +static int
> +__spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable,
> + unsigned int div_factor)
> {
> - int rc;
> + int ret;
> + unsigned int ns = clkdiv->cxo_period_ns;
> + unsigned int div = div_factor_to_div(div_factor);
>
> - rc = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL,
> - REG_EN_MASK,
> - (enable_state == true) ? REG_EN_MASK : 0);
> - if (rc)
> - return rc;
> + ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL,
> + REG_EN_MASK, enable ? REG_EN_MASK : 0);
> + if (ret)
> + return ret;
>
> - if (enable_state == true)
> - ndelay(ENABLE_DELAY_NS(clkdiv->cxo_period_ns,
> - div_factor_to_div(clkdiv->div_factor)));
> + if (enable)
> + ndelay((2 + 3 * div) * ns);
> else
> - ndelay(DISABLE_DELAY_NS(clkdiv->cxo_period_ns,
> - div_factor_to_div(clkdiv->div_factor)));
> + ndelay(3 * div * ns);
>
> - return rc;
> + return 0;
> }
>
> -static int spmi_pmic_clkdiv_config_freq_div(struct clkdiv *clkdiv,
> - unsigned int div)
> +static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable)
> {
> unsigned int div_factor;
> - unsigned long flags;
> - bool enabled;
> - int rc;
> -
> - div_factor = div_to_div_factor(div);
> -
> - spin_lock_irqsave(&clkdiv->lock, flags);
> -
> - enabled = is_spmi_pmic_clkdiv_enabled(clkdiv);
> - if (enabled) {
> - rc = spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
> - if (rc)
> - goto fail;
> - }
>
> - rc = regmap_update_bits(clkdiv->regmap,
> - clkdiv->base + REG_DIV_CTL1,
> - DIV_CTL1_DIV_FACTOR_MASK, div_factor);
> - if (rc)
> - goto fail;
> + regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
> + div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
>
> - clkdiv->div_factor = div_factor;
> -
> - if (enabled)
> - rc = spmi_pmic_clkdiv_set_enable_state(clkdiv, true);
> -
> -fail:
> - spin_unlock_irqrestore(&clkdiv->lock, flags);
> - return rc;
> + return __spmi_pmic_clkdiv_set_enable_state(clkdiv, enable, div_factor);
> }
>
> static int clk_spmi_pmic_div_enable(struct clk_hw *hw)
> {
> struct clkdiv *clkdiv = to_clkdiv(hw);
> unsigned long flags;
> - int rc;
> + int ret;
>
> spin_lock_irqsave(&clkdiv->lock, flags);
> - rc = spmi_pmic_clkdiv_set_enable_state(clkdiv, true);
> + ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, true);
> spin_unlock_irqrestore(&clkdiv->lock, flags);
>
> - return rc;
> + return ret;
> }
>
> static void clk_spmi_pmic_div_disable(struct clk_hw *hw)
> @@ -163,35 +121,59 @@ static void clk_spmi_pmic_div_disable(struct clk_hw *hw)
> }
>
> static long clk_spmi_pmic_div_round_rate(struct clk_hw *hw, unsigned long rate,
> - unsigned long *parent_rate)
> + unsigned long *parent_rate)
> {
> - unsigned long new_rate;
> unsigned int div, div_factor;
>
> div = DIV_ROUND_UP(*parent_rate, rate);
> div_factor = div_to_div_factor(div);
> - new_rate = *parent_rate / div_factor_to_div(div_factor);
> + div = div_factor_to_div(div_factor);
>
> - return new_rate;
> + return *parent_rate / div;
> }
>
> -static unsigned long clk_spmi_pmic_div_recalc_rate(struct clk_hw *hw,
> - unsigned long parent_rate)
> +static unsigned long
> +clk_spmi_pmic_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> {
> struct clkdiv *clkdiv = to_clkdiv(hw);
> - unsigned long rate;
> + unsigned int div_factor;
>
> - rate = parent_rate / div_factor_to_div(clkdiv->div_factor);
> + regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
> + div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
>
> - return rate;
> + return parent_rate / div_factor_to_div(div_factor);
> }
>
> static int clk_spmi_pmic_div_set_rate(struct clk_hw *hw, unsigned long rate,
> - unsigned long parent_rate)
> + unsigned long parent_rate)
> {
> struct clkdiv *clkdiv = to_clkdiv(hw);
> + unsigned int div_factor = div_to_div_factor(parent_rate / rate);
> + unsigned long flags;
> + bool enabled;
> + int ret;
> +
> + spin_lock_irqsave(&clkdiv->lock, flags);
> + enabled = is_spmi_pmic_clkdiv_enabled(clkdiv);
> + if (enabled) {
> + ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
> + if (ret)
> + goto unlock;
> + }
> +
> + ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1,
> + DIV_CTL1_DIV_FACTOR_MASK, div_factor);
> + if (ret)
> + goto unlock;
> +
> + if (enabled)
> + ret = __spmi_pmic_clkdiv_set_enable_state(clkdiv, true,
> + div_factor);
>
> - return spmi_pmic_clkdiv_config_freq_div(clkdiv, parent_rate / rate);
> +unlock:
> + spin_unlock_irqrestore(&clkdiv->lock, flags);
> +
> + return ret;
> }
>
> static const struct clk_ops clk_spmi_pmic_div_ops = {
> @@ -203,30 +185,25 @@ static const struct clk_ops clk_spmi_pmic_div_ops = {
> };
>
> struct spmi_pmic_div_clk_cc {
> - struct clk_hw **div_clks;
> int nclks;
> + struct clkdiv clks[];
> };
>
> -#define SPMI_PMIC_CLKDIV_MIN_INDEX 1
> -
> -static struct clk_hw *spmi_pmic_div_clk_hw_get(struct of_phandle_args *clkspec,
> - void *data)
> +static struct clk_hw *
> +spmi_pmic_div_clk_hw_get(struct of_phandle_args *clkspec, void *data)
> {
> - struct spmi_pmic_div_clk_cc *clk_cc = data;
> - unsigned int idx = (clkspec->args[0] - SPMI_PMIC_CLKDIV_MIN_INDEX);
> + struct spmi_pmic_div_clk_cc *cc = data;
> + int idx = clkspec->args[0] - 1; /* Start at 1 instead of 0 */
>
> - if (idx < 0 || idx >= clk_cc->nclks) {
> - pr_err("%s: index value %u is invalid; allowed range: [%d, %d]\n",
> - __func__, clkspec->args[0], SPMI_PMIC_CLKDIV_MIN_INDEX,
> - clk_cc->nclks);
> + if (idx < 0 || idx >= cc->nclks) {
> + pr_err("%s: index value %u is invalid; allowed range [1, %d]\n",
> + __func__, clkspec->args[0], cc->nclks);
> return ERR_PTR(-EINVAL);
> }
>
> - return clk_cc->div_clks[idx];
> + return &cc->clks[idx].hw;
> }
>
> -#define SPMI_PMIC_DIV_CLK_SIZE 0x100
> -
> static const struct of_device_id spmi_pmic_clkdiv_match_table[] = {
> {
> .compatible = "qcom,spmi-clkdiv",
> @@ -242,20 +219,21 @@ MODULE_DEVICE_TABLE(of, spmi_pmic_clkdiv_match_table);
>
> static int spmi_pmic_clkdiv_probe(struct platform_device *pdev)
> {
> - struct spmi_pmic_div_clk_cc *clk_cc;
> + struct spmi_pmic_div_clk_cc *cc;
> struct clk_init_data init = {};
> struct clkdiv *clkdiv;
> struct clk *cxo;
> struct regmap *regmap;
> struct device *dev = &pdev->dev;
> + struct device_node *of_node = dev->of_node;
> const char *parent_name;
> - int nclks, i, rc, cxo_hz;
> + int nclks, i, ret, cxo_hz;
> u32 start;
>
> - rc = of_property_read_u32(dev->of_node, "reg", &start);
> - if (rc < 0) {
> + ret = of_property_read_u32(of_node, "reg", &start);
> + if (ret < 0) {
> dev_err(dev, "reg property reading failed\n");
> - return rc;
> + return ret;
> }
>
> regmap = dev_get_regmap(dev->parent, NULL);
> @@ -264,62 +242,51 @@ static int spmi_pmic_clkdiv_probe(struct platform_device *pdev)
> return -EINVAL;
> }
>
> - nclks = (uintptr_t)of_match_node(spmi_pmic_clkdiv_match_table,
> - dev->of_node)->data;
> -
> - clkdiv = devm_kcalloc(dev, nclks, sizeof(*clkdiv), GFP_KERNEL);
> - if (!clkdiv)
> - return -ENOMEM;
> -
> - clk_cc = devm_kzalloc(&pdev->dev, sizeof(*clk_cc), GFP_KERNEL);
> - if (!clk_cc)
> - return -ENOMEM;
> + nclks = (uintptr_t)of_device_get_match_data(dev);
> + if (!nclks)
> + return -EINVAL;
>
> - clk_cc->div_clks = devm_kcalloc(&pdev->dev, nclks,
> - sizeof(*clk_cc->div_clks), GFP_KERNEL);
> - if (!clk_cc->div_clks)
> + cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*cc->clks) * nclks,
> + GFP_KERNEL);
> + if (!cc)
> return -ENOMEM;
> + cc->nclks = nclks;
>
> cxo = clk_get(dev, "xo");
> if (IS_ERR(cxo)) {
> - rc = PTR_ERR(cxo);
> - if (rc != -EPROBE_DEFER)
> - dev_err(dev, "failed to get xo clock");
> - return rc;
> + ret = PTR_ERR(cxo);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to get xo clock\n");
> + return ret;
> }
> cxo_hz = clk_get_rate(cxo);
> clk_put(cxo);
>
> - parent_name = of_clk_get_parent_name(dev->of_node, 0);
> + parent_name = of_clk_get_parent_name(of_node, 0);
> if (!parent_name) {
> dev_err(dev, "missing parent clock\n");
> return -ENODEV;
> }
>
> init.parent_names = &parent_name;
> - init.num_parents = parent_name ? 1 : 0;
> + init.num_parents = 1;
> init.ops = &clk_spmi_pmic_div_ops;
> - init.flags = 0;
>
> - for (i = 0; i < nclks; i++) {
> + for (i = 0, clkdiv = cc->clks; i < nclks; i++) {
> spin_lock_init(&clkdiv[i].lock);
> - clkdiv[i].base = start + i * SPMI_PMIC_DIV_CLK_SIZE;
> + clkdiv[i].base = start + i * 0x100;
> clkdiv[i].regmap = regmap;
> clkdiv[i].cxo_period_ns = NSEC_PER_SEC / cxo_hz;
> init.name = kasprintf(GFP_KERNEL, "div_clk%d", i + 1);
> clkdiv[i].hw.init = &init;
> - rc = devm_clk_hw_register(dev, &clkdiv[i].hw);
> - kfree(init.name); /* clock framework made a copy of the name */
> - if (rc)
> - return rc;
>
> - clk_cc->div_clks[i] = &clkdiv[i].hw;
> + ret = devm_clk_hw_register(dev, &clkdiv[i].hw);
> + kfree(init.name); /* clk framework made a copy */
> + if (ret)
> + return ret;
> }
>
> - clk_cc->nclks = nclks;
> - rc = of_clk_add_hw_provider(pdev->dev.of_node, spmi_pmic_div_clk_hw_get,
> - clk_cc);
> - return rc;
> + return of_clk_add_hw_provider(of_node, spmi_pmic_div_clk_hw_get, cc);
> }
>
> static int spmi_pmic_clkdiv_remove(struct platform_device *pdev)
>
>
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^ permalink raw reply
* Re: [PATCH V1 1/4] qcom: spmi-wled: Add support for qcom wled driver
From: kgunda-sgV2jX0FEOL9JmXXK+q4OQ @ 2017-11-17 9:52 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, Lee Jones, Daniel Thompson,
Jingoo Han, Richard Purdie, Jacek Anaszewski, Pavel Machek,
Rob Herring, Mark Rutland, Bartlomiej Zolnierkiewicz,
linux-leds-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-owner-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171117065640.GU28761@minitux>
On 2017-11-17 12:26, Bjorn Andersson wrote:
> On Thu 16 Nov 22:36 PST 2017, kgunda-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org wrote:
>
>> On 2017-11-16 22:25, Bjorn Andersson wrote:
>> > On Thu 16 Nov 04:18 PST 2017, Kiran Gunda wrote:
>> >
>> > > WLED driver provides the interface to the display driver to
>> > > adjust the brightness of the display backlight.
>> > >
>> >
>> > Hi Kiran,
>> >
>> > This driver has a lot in common with the already upstream pm8941-wled.c,
>> > because it's just a new revision of the same block.
>> >
>> > Please extend the existing driver rather than providing a new one
>> > (and yes, renaming the file is okay).
>> >
>> > Regards,
>> > Bjorn
>>
>> Hi Bjorn,
>>
>> Yes this driver design is similar to pm8941, however the WLED HW block
>> has undergone quite a few changes in analog and digital from PM8941 to
>> PM8998.
>
> I can see that, looking at the documentation.
>
>> Few of them include splitting one module into wled-ctrl and wled-sink
>> peripherals, changes in the register offsets and the bit
>> interpretation.
>
> This is typical and something we need to handle in all these drivers,
> to
> avoid having one driver per platform.
>
>> Hence we concluded that it was better to have a new driver to support
>> this new gen WELD module and decouple it from the pm8941.
>
> Okay, I can see how it's easier to not have to case about anything but
> pmi8998 in this driver, but where do you add the support for other WLED
> versions? What about PMI8994? Will there not be similar differences
> (registers that has moved around) in the future?
>
>> Also, going forward this driver will support AMOLED AVDD rail (not
>> supported by pm8941) touching a few more registers/configuration and
>> newer PMICs.
>
> Is this a feature that was introduced in PMI8998? Will this support not
> be dependent on the pmic version?
>
>> So spinning off a new driver would make it cleaner and easier to
>> extend further.
>>
>
> It's for sure easier at this point in time, but your argumentation
> implies that PMI8998+1 should go into it's own driver as well.
>
> I suspect that if you're going to reuse this driver for future PMIC
> versions you will have to deal with register layout differences and new
> feature set, and as such I'm not convinced that a new driver is needed.
>
>
> Can you give any concrete examples of where it is not possible or
> undesirable to maintain the pm8941 support in the same driver?
>
> Regards,
> Bjorn
Hi Bjorn,
Thanks for the inputs! Following are the reasons to go for the new
driver
and this driver can support 5 PMICs.
1.Majority of register, offsets and config values don’t match up
between
PMI8998 and PM8941
2.Feature such as – SC protection handling in SW cannot be done for 8941
as
there is no SC event/irq, AMOELD AVDD cannot supported by PM8941
3.Feature such as – string auto-calibration even if common will have to
use
different offsets/registers in the same SW logic
4.PMI8998, PMI8994, PMI8950 and PM660 all of them have this same WLED
module
(and register map) with very minor changes unlike 8941.
Thanks,
Kiran
> --
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> linux-arm-msm" in
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^ permalink raw reply
* [PATCH V6] clk: qcom: Add spmi_pmic clock divider support
From: Tirupathi Reddy @ 2017-11-17 9:48 UTC (permalink / raw)
To: sboyd-sgV2jX0FEOL9JmXXK+q4OQ
Cc: mturquette-rdvid1DuHRBWk0Htik3J/w, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, andy.gross-QSEj5FYQhm4dnm+yROfE0A,
david.brown-QSEj5FYQhm4dnm+yROfE0A,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA, Tirupathi Reddy
Clkdiv module provides a clock output on the PMIC with CXO as
the source. This clock can be routed through PMIC GPIOs. Add
a device driver to configure this clkdiv module.
Signed-off-by: Tirupathi Reddy <tirupath-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Signed-off-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
.../bindings/clock/clk-spmi-pmic-div.txt | 59 ++++
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-spmi-pmic-div.c | 308 +++++++++++++++++++++
4 files changed, 377 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt
create mode 100644 drivers/clk/qcom/clk-spmi-pmic-div.c
diff --git a/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt b/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt
new file mode 100644
index 0000000..2cf2aba
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt
@@ -0,0 +1,59 @@
+Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)
+
+clkdiv configures the clock frequency of a set of outputs on the PMIC.
+These clocks are typically wired through alternate functions on
+gpio pins.
+
+=======================
+Properties
+=======================
+
+- compatible
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,spmi-clkdiv".
+
+- reg
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: base address of CLKDIV peripherals.
+
+- qcom,num-clkdivs
+ Usage: required
+ Value type: <u32>
+ Definition: number of CLKDIV peripherals.
+
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: reference to the xo clock.
+
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "xo".
+
+- clock-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: shall contain 1.
+
+=======
+Example
+=======
+
+pm8998_clk_divs: clock-controller@5b00 {
+ compatible = "qcom,spmi-clkdiv";
+ reg = <0x5b00>;
+ #clock-cells = <1>;
+ qcom,num-clkdivs = <3>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
+
+ assigned-clocks = <&pm8998_clk_divs 1>,
+ <&pm8998_clk_divs 2>,
+ <&pm8998_clk_divs 3>;
+ assigned-clock-rates = <9600000>,
+ <9600000>,
+ <9600000>;
+};
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9f6c278..20b5d6f 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -196,3 +196,12 @@ config MSM_MMCC_8996
Support for the multimedia clock controller on msm8996 devices.
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
+
+config SPMI_PMIC_CLKDIV
+ tristate "SPMI PMIC clkdiv Support"
+ depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
+ help
+ This driver supports the clkdiv functionality on the Qualcomm
+ Technologies, Inc. SPMI PMIC. It configures the frequency of
+ clkdiv outputs of the PMIC. These clocks are typically wired
+ through alternate functions on GPIO pins.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 26410d3..602af38 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -34,3 +34,4 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
+obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/clk-spmi-pmic-div.c b/drivers/clk/qcom/clk-spmi-pmic-div.c
new file mode 100644
index 0000000..bf85a16
--- /dev/null
+++ b/drivers/clk/qcom/clk-spmi-pmic-div.c
@@ -0,0 +1,308 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/log2.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#define REG_DIV_CTL1 0x43
+#define DIV_CTL1_DIV_FACTOR_MASK GENMASK(2, 0)
+
+#define REG_EN_CTL 0x46
+#define REG_EN_MASK BIT(7)
+
+struct clkdiv {
+ struct regmap *regmap;
+ u16 base;
+ spinlock_t lock;
+
+ struct clk_hw hw;
+ unsigned int cxo_period_ns;
+};
+
+static inline struct clkdiv *to_clkdiv(struct clk_hw *hw)
+{
+ return container_of(hw, struct clkdiv, hw);
+}
+
+static inline unsigned int div_factor_to_div(unsigned int div_factor)
+{
+ if (!div_factor)
+ div_factor = 1;
+
+ return 1 << (div_factor - 1);
+}
+
+static inline unsigned int div_to_div_factor(unsigned int div)
+{
+ return min(ilog2(div) + 1, 7);
+}
+
+static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv)
+{
+ unsigned int val = 0;
+
+ regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val);
+
+ return val & REG_EN_MASK;
+}
+
+static int
+__spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable,
+ unsigned int div_factor)
+{
+ int ret;
+ unsigned int ns = clkdiv->cxo_period_ns;
+ unsigned int div = div_factor_to_div(div_factor);
+
+ ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL,
+ REG_EN_MASK, enable ? REG_EN_MASK : 0);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ndelay((2 + 3 * div) * ns);
+ else
+ ndelay(3 * div * ns);
+
+ return 0;
+}
+
+static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable)
+{
+ unsigned int div_factor;
+
+ regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
+ div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
+
+ return __spmi_pmic_clkdiv_set_enable_state(clkdiv, enable, div_factor);
+}
+
+static int clk_spmi_pmic_div_enable(struct clk_hw *hw)
+{
+ struct clkdiv *clkdiv = to_clkdiv(hw);
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&clkdiv->lock, flags);
+ ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, true);
+ spin_unlock_irqrestore(&clkdiv->lock, flags);
+
+ return ret;
+}
+
+static void clk_spmi_pmic_div_disable(struct clk_hw *hw)
+{
+ struct clkdiv *clkdiv = to_clkdiv(hw);
+ unsigned long flags;
+
+ spin_lock_irqsave(&clkdiv->lock, flags);
+ spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
+ spin_unlock_irqrestore(&clkdiv->lock, flags);
+}
+
+static long clk_spmi_pmic_div_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned int div, div_factor;
+
+ div = DIV_ROUND_UP(*parent_rate, rate);
+ div_factor = div_to_div_factor(div);
+ div = div_factor_to_div(div_factor);
+
+ return *parent_rate / div;
+}
+
+static unsigned long
+clk_spmi_pmic_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct clkdiv *clkdiv = to_clkdiv(hw);
+ unsigned int div_factor;
+
+ regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
+ div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
+
+ return parent_rate / div_factor_to_div(div_factor);
+}
+
+static int clk_spmi_pmic_div_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clkdiv *clkdiv = to_clkdiv(hw);
+ unsigned int div_factor = div_to_div_factor(parent_rate / rate);
+ unsigned long flags;
+ bool enabled;
+ int ret;
+
+ spin_lock_irqsave(&clkdiv->lock, flags);
+ enabled = is_spmi_pmic_clkdiv_enabled(clkdiv);
+ if (enabled) {
+ ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
+ if (ret)
+ goto unlock;
+ }
+
+ ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1,
+ DIV_CTL1_DIV_FACTOR_MASK, div_factor);
+ if (ret)
+ goto unlock;
+
+ if (enabled)
+ ret = __spmi_pmic_clkdiv_set_enable_state(clkdiv, true,
+ div_factor);
+
+unlock:
+ spin_unlock_irqrestore(&clkdiv->lock, flags);
+
+ return ret;
+}
+
+static const struct clk_ops clk_spmi_pmic_div_ops = {
+ .enable = clk_spmi_pmic_div_enable,
+ .disable = clk_spmi_pmic_div_disable,
+ .set_rate = clk_spmi_pmic_div_set_rate,
+ .recalc_rate = clk_spmi_pmic_div_recalc_rate,
+ .round_rate = clk_spmi_pmic_div_round_rate,
+};
+
+struct spmi_pmic_div_clk_cc {
+ int nclks;
+ struct clkdiv clks[];
+};
+
+static struct clk_hw *
+spmi_pmic_div_clk_hw_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct spmi_pmic_div_clk_cc *cc = data;
+ int idx = clkspec->args[0] - 1; /* Start at 1 instead of 0 */
+
+ if (idx < 0 || idx >= cc->nclks) {
+ pr_err("%s: index value %u is invalid; allowed range [1, %d]\n",
+ __func__, clkspec->args[0], cc->nclks);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return &cc->clks[idx].hw;
+}
+
+static int spmi_pmic_clkdiv_probe(struct platform_device *pdev)
+{
+ struct spmi_pmic_div_clk_cc *cc;
+ struct clk_init_data init = {};
+ struct clkdiv *clkdiv;
+ struct clk *cxo;
+ struct regmap *regmap;
+ struct device *dev = &pdev->dev;
+ struct device_node *of_node = dev->of_node;
+ const char *parent_name;
+ int nclks, i, ret, cxo_hz;
+ u32 start;
+
+ ret = of_property_read_u32(of_node, "reg", &start);
+ if (ret < 0) {
+ dev_err(dev, "reg property reading failed\n");
+ return ret;
+ }
+
+ regmap = dev_get_regmap(dev->parent, NULL);
+ if (!regmap) {
+ dev_err(dev, "Couldn't get parent's regmap\n");
+ return -EINVAL;
+ }
+
+ ret = of_property_read_u32(of_node, "qcom,num-clkdivs", &nclks);
+ if (ret < 0) {
+ dev_err(dev, "qcom,num-clkdivs property reading failed, ret=%d\n",
+ ret);
+ return ret;
+ }
+
+ if (!nclks)
+ return -EINVAL;
+
+ cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*cc->clks) * nclks,
+ GFP_KERNEL);
+ if (!cc)
+ return -ENOMEM;
+ cc->nclks = nclks;
+
+ cxo = clk_get(dev, "xo");
+ if (IS_ERR(cxo)) {
+ ret = PTR_ERR(cxo);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "failed to get xo clock\n");
+ return ret;
+ }
+ cxo_hz = clk_get_rate(cxo);
+ clk_put(cxo);
+
+ parent_name = of_clk_get_parent_name(of_node, 0);
+ if (!parent_name) {
+ dev_err(dev, "missing parent clock\n");
+ return -ENODEV;
+ }
+
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ init.ops = &clk_spmi_pmic_div_ops;
+
+ for (i = 0, clkdiv = cc->clks; i < nclks; i++) {
+ spin_lock_init(&clkdiv[i].lock);
+ clkdiv[i].base = start + i * 0x100;
+ clkdiv[i].regmap = regmap;
+ clkdiv[i].cxo_period_ns = NSEC_PER_SEC / cxo_hz;
+ init.name = kasprintf(GFP_KERNEL, "div_clk%d", i + 1);
+ clkdiv[i].hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &clkdiv[i].hw);
+ kfree(init.name); /* clk framework made a copy */
+ if (ret)
+ return ret;
+ }
+
+ return of_clk_add_hw_provider(of_node, spmi_pmic_div_clk_hw_get, cc);
+}
+
+static int spmi_pmic_clkdiv_remove(struct platform_device *pdev)
+{
+ of_clk_del_provider(pdev->dev.of_node);
+
+ return 0;
+}
+
+static const struct of_device_id spmi_pmic_clkdiv_match_table[] = {
+ { .compatible = "qcom,spmi-clkdiv" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, spmi_pmic_clkdiv_match_table);
+
+static struct platform_driver spmi_pmic_clkdiv_driver = {
+ .driver = {
+ .name = "qcom,spmi-pmic-clkdiv",
+ .of_match_table = spmi_pmic_clkdiv_match_table,
+ },
+ .probe = spmi_pmic_clkdiv_probe,
+ .remove = spmi_pmic_clkdiv_remove,
+};
+module_platform_driver(spmi_pmic_clkdiv_driver);
+
+MODULE_DESCRIPTION("QCOM SPMI PMIC clkdiv driver");
+MODULE_LICENSE("GPL v2");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
--
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^ permalink raw reply related
* [PATCH v3 3/3] arm64: dts: Hi3660: Add binding for stub clock
From: Xu YiPing @ 2017-11-17 9:27 UTC (permalink / raw)
To: mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q,
wenpan-C8/M+/jPZTeaMJb+Lgu22Q, leo.yan-QSEj5FYQhm4dnm+yROfE0A,
zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A,
guodong.xu-QSEj5FYQhm4dnm+yROfE0A,
zhongkaihua-hv44wF8Li93QT0dZR+AlfA,
chenjun14-hv44wF8Li93QT0dZR+AlfA
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
xuezhiliang-C8/M+/jPZTeaMJb+Lgu22Q,
kevin.wangtao-C8/M+/jPZTeaMJb+Lgu22Q
In-Reply-To: <1510910852-2175-1-git-send-email-xuyiping-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
From: Kaihua Zhong <zhongkaihua-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Add DT binding for Hi3660 stub clock driver.
Reviewed-by: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Kai Zhao <zhaokai1-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Signed-off-by: Tao Wang <kevin.wangtao-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Signed-off-by: Ruyi Wang <wangruyi-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Signed-off-by: Kaihua Zhong <zhongkaihua-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 451b6bf..cbbc7f1 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -293,6 +293,13 @@
#mbox-cells = <3>;
};
+ stub_clock: stub_clock@e896b500 {
+ compatible = "hisilicon,hi3660-stub-clk";
+ reg = <0x0 0xe896b500 0x0 0x0100>;
+ #clock-cells = <1>;
+ mboxes = <&mailbox 13 3 0>;
+ };
+
dual_timer0: timer@fff14000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x0 0xfff14000 0x0 0x1000>;
--
1.9.1
--
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^ permalink raw reply related
* [PATCH v3 2/3] clk: hisilicon: Add support for Hi3660 stub clocks
From: Xu YiPing @ 2017-11-17 9:27 UTC (permalink / raw)
To: mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q,
wenpan-C8/M+/jPZTeaMJb+Lgu22Q, leo.yan-QSEj5FYQhm4dnm+yROfE0A,
zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A,
guodong.xu-QSEj5FYQhm4dnm+yROfE0A,
zhongkaihua-hv44wF8Li93QT0dZR+AlfA,
chenjun14-hv44wF8Li93QT0dZR+AlfA
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
xuezhiliang-C8/M+/jPZTeaMJb+Lgu22Q,
kevin.wangtao-C8/M+/jPZTeaMJb+Lgu22Q
In-Reply-To: <1510910852-2175-1-git-send-email-xuyiping-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
From: Kaihua Zhong <zhongkaihua-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Hi3660 has four stub clocks, which are big and LITTLE cluster clocks,
GPU clock and DDR clock. These clocks ask MCU for frequency scaling
by sending message through mailbox.
This commit adds support for stub clocks, it requests the dedicated
mailbox channel at initialization; then later uses this channel to send
message to MCU to execute frequency scaling. The four stub clocks share
the same mailbox channel, but every stub clock has its own command id so
MCU can distinguish the requirement coming for which clock.
A shared memory is used to present effective frequency value, so the
clock driver uses I/O mapping for the memory and reads back rate value.
Reviewed-by: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Kai Zhao <zhaokai1-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Signed-off-by: Tao Wang <kevin.wangtao-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Signed-off-by: Ruyi Wang <wangruyi-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Signed-off-by: Kaihua Zhong <zhongkaihua-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
drivers/clk/hisilicon/Kconfig | 6 ++
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/clk-hi3660-stub.c | 186 ++++++++++++++++++++++++++++++++
3 files changed, 193 insertions(+)
create mode 100644 drivers/clk/hisilicon/clk-hi3660-stub.c
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index 7098bfd..1bd4355 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -49,3 +49,9 @@ config STUB_CLK_HI6220
default ARCH_HISI
help
Build the Hisilicon Hi6220 stub clock driver.
+
+config STUB_CLK_HI3660
+ bool "Hi3660 Stub Clock Driver"
+ depends on COMMON_CLK_HI3660 && MAILBOX
+ help
+ Build the Hisilicon Hi3660 stub clock driver.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 1e4c3dd..0a5b499 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
obj-$(CONFIG_RESET_HISI) += reset.o
obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
+obj-$(CONFIG_STUB_CLK_HI3660) += clk-hi3660-stub.o
diff --git a/drivers/clk/hisilicon/clk-hi3660-stub.c b/drivers/clk/hisilicon/clk-hi3660-stub.c
new file mode 100644
index 0000000..607efa4
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3660-stub.c
@@ -0,0 +1,186 @@
+/*
+ * Hisilicon clock driver
+ *
+ * Copyright (c) 2013-2017 Hisilicon Limited.
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * Author: Kai Zhao <zhaokai1-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
+ * Tao Wang <kevin.wangtao-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
+ * Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/mailbox_client.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/hi3660-clock.h>
+
+#define HI3660_STUB_CLOCK_DATA (0x70)
+#define MHZ (1000 * 1000)
+
+#define DEFINE_CLK_STUB(_id, _cmd, _name) \
+ { \
+ .id = (_id), \
+ .cmd = (_cmd), \
+ .hw.init = &(struct clk_init_data) { \
+ .name = #_name, \
+ .ops = &hi3660_stub_clk_ops, \
+ .num_parents = 0, \
+ .flags = CLK_GET_RATE_NOCACHE, \
+ }, \
+ },
+
+#define to_stub_clk(_hw) container_of(_hw, struct hi3660_stub_clk, hw)
+
+struct hi3660_stub_clk_chan {
+ struct mbox_client cl;
+ struct mbox_chan *mbox;
+};
+
+struct hi3660_stub_clk {
+ unsigned int id;
+ struct clk_hw hw;
+ unsigned int cmd;
+ unsigned int msg[8];
+ unsigned int rate;
+};
+
+static void __iomem *freq_reg;
+static struct hi3660_stub_clk_chan stub_clk_chan;
+
+static unsigned long hi3660_stub_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct hi3660_stub_clk *stub_clk = to_stub_clk(hw);
+
+ /*
+ * LPM3 writes back the CPU frequency in shared SRAM so read
+ * back the frequency.
+ */
+ stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ;
+ return stub_clk->rate;
+}
+
+static long hi3660_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ /*
+ * LPM3 handles rate rounding so just return whatever
+ * rate is requested.
+ */
+ return rate;
+}
+
+static int hi3660_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct hi3660_stub_clk *stub_clk = to_stub_clk(hw);
+
+ stub_clk->msg[0] = stub_clk->cmd;
+ stub_clk->msg[1] = rate / MHZ;
+
+ dev_dbg(stub_clk_chan.cl.dev, "set rate msg[0]=0x%x msg[1]=0x%x\n",
+ stub_clk->msg[0], stub_clk->msg[1]);
+
+ mbox_send_message(stub_clk_chan.mbox, stub_clk->msg);
+ mbox_client_txdone(stub_clk_chan.mbox, 0);
+
+ stub_clk->rate = rate;
+ return 0;
+}
+
+static const struct clk_ops hi3660_stub_clk_ops = {
+ .recalc_rate = hi3660_stub_clk_recalc_rate,
+ .round_rate = hi3660_stub_clk_round_rate,
+ .set_rate = hi3660_stub_clk_set_rate,
+};
+
+static struct hi3660_stub_clk hi3660_stub_clks[HI3660_CLK_STUB_NUM] = {
+ DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER0, 0x0001030A, "cpu-cluster.0")
+ DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER1, 0x0002030A, "cpu-cluster.1")
+ DEFINE_CLK_STUB(HI3660_CLK_STUB_GPU, 0x0003030A, "clk-g3d")
+ DEFINE_CLK_STUB(HI3660_CLK_STUB_DDR, 0x00040309, "clk-ddrc")
+};
+
+static struct clk_hw *hi3660_stub_clk_hw_get(struct of_phandle_args *clkspec,
+ void *data)
+{
+ unsigned int idx = clkspec->args[0];
+
+ if (idx > HI3660_CLK_STUB_NUM) {
+ pr_err("%s: invalid index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return &hi3660_stub_clks[idx].hw;
+}
+
+static int hi3660_stub_clk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ unsigned int i;
+ int ret;
+
+ /* Use mailbox client without blocking */
+ stub_clk_chan.cl.dev = dev;
+ stub_clk_chan.cl.tx_done = NULL;
+ stub_clk_chan.cl.tx_block = false;
+ stub_clk_chan.cl.knows_txdone = false;
+
+ /* Allocate mailbox channel */
+ stub_clk_chan.mbox = mbox_request_channel(&stub_clk_chan.cl, 0);
+ if (IS_ERR(stub_clk_chan.mbox))
+ return PTR_ERR(stub_clk_chan.mbox);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ freq_reg = devm_ioremap(dev, res->start, resource_size(res));
+ if (IS_ERR(freq_reg))
+ return -ENOMEM;
+
+ freq_reg += HI3660_STUB_CLOCK_DATA;
+
+ for (i = 0; i < HI3660_CLK_STUB_NUM; i++) {
+ ret = devm_clk_hw_register(&pdev->dev, &hi3660_stub_clks[i].hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = of_clk_add_hw_provider(pdev->dev.of_node, hi3660_stub_clk_hw_get,
+ hi3660_stub_clks);
+ return ret;
+}
+
+static const struct of_device_id hi3660_stub_clk_of_match[] = {
+ { .compatible = "hisilicon,hi3660-stub-clk", },
+ {}
+};
+
+static struct platform_driver hi3660_stub_clk_driver = {
+ .probe = hi3660_stub_clk_probe,
+ .driver = {
+ .name = "hi3660-stub-clk",
+ .of_match_table = hi3660_stub_clk_of_match,
+ },
+};
+
+static int __init hi3660_stub_clk_init(void)
+{
+ return platform_driver_register(&hi3660_stub_clk_driver);
+}
+subsys_initcall(hi3660_stub_clk_init);
--
1.9.1
--
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^ permalink raw reply related
* [PATCH v3 1/3] dt-bindings: clk: Hi3660: Document stub clock
From: Xu YiPing @ 2017-11-17 9:27 UTC (permalink / raw)
To: mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q,
wenpan-C8/M+/jPZTeaMJb+Lgu22Q, leo.yan-QSEj5FYQhm4dnm+yROfE0A,
zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A,
guodong.xu-QSEj5FYQhm4dnm+yROfE0A,
zhongkaihua-hv44wF8Li93QT0dZR+AlfA,
chenjun14-hv44wF8Li93QT0dZR+AlfA
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
xuezhiliang-C8/M+/jPZTeaMJb+Lgu22Q,
kevin.wangtao-C8/M+/jPZTeaMJb+Lgu22Q
In-Reply-To: <1510910852-2175-1-git-send-email-xuyiping-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
From: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Document the DT binding for stub clock which is used for CPU,
GPU and DDR frequency scaling.
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/clock/hi3660-clock.txt | 6 ++++++
include/dt-bindings/clock/hi3660-clock.h | 7 +++++++
2 files changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/hi3660-clock.txt b/Documentation/devicetree/bindings/clock/hi3660-clock.txt
index 0035a7e..946da7c 100644
--- a/Documentation/devicetree/bindings/clock/hi3660-clock.txt
+++ b/Documentation/devicetree/bindings/clock/hi3660-clock.txt
@@ -13,12 +13,18 @@ Required Properties:
- "hisilicon,hi3660-pmuctrl"
- "hisilicon,hi3660-sctrl"
- "hisilicon,hi3660-iomcu"
+ - "hisilicon,hi3660-stub-clk"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
+Optional Properties:
+
+- mboxes: Phandle to the mailbox for sending message to MCU.
+ (See: ../mailbox/hisilicon,hi3660-mailbox.txt for more info)
+
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
diff --git a/include/dt-bindings/clock/hi3660-clock.h b/include/dt-bindings/clock/hi3660-clock.h
index adb768d..75d583e 100644
--- a/include/dt-bindings/clock/hi3660-clock.h
+++ b/include/dt-bindings/clock/hi3660-clock.h
@@ -208,4 +208,11 @@
#define HI3660_CLK_I2C6_IOMCU 3
#define HI3660_CLK_IOMCU_PERI0 4
+/* clk in stub clock */
+#define HI3660_CLK_STUB_CLUSTER0 0
+#define HI3660_CLK_STUB_CLUSTER1 1
+#define HI3660_CLK_STUB_GPU 2
+#define HI3660_CLK_STUB_DDR 3
+#define HI3660_CLK_STUB_NUM 4
+
#endif /* __DTS_HI3660_CLOCK_H */
--
1.9.1
--
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^ permalink raw reply related
* [PATCH v3 0/3] Add support for Hi3660 stub clock
From: Xu YiPing @ 2017-11-17 9:27 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, xuejiancheng, wenpan, leo.yan, zhangfei.gao,
guodong.xu, zhongkaihua, chenjun14
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
suzhuangluan, xuezhiliang, kevin.wangtao
From: Leo Yan <leo.yan@linaro.org>
Hi3660 has stub clocks for two CPU clusters, GPU and DDR; and the stub
clocks use the mailbox to send message to MCU for frequency scaling.
This patch set adds support Hi3660 stub clock, and since it needs to
use mailbox so this patch set has dependency with Hi3660 mailbox
patch set [1].
This patch set has been tested on Hikey960 with CPUFreq enabled.
Changes from v1:
* According to Rob suggestion, moved dt header definition into DT patch;
* According to Julien suggestion, removed "dev" member from stub clock
structure and refined code for global variable "stub_clk_chan";
* Fixed DT binding patch.
[1] http://archive.armlinux.org.uk/lurker/message/20171027.061501.f895dee8.en.html
Kaihua Zhong (2):
clk: hisilicon: Add support for Hi3660 stub clocks
arm64: dts: Hi3660: Add binding for stub clock
Leo Yan (1):
dt-bindings: clk: Hi3660: Document stub clock
.../devicetree/bindings/clock/hi3660-clock.txt | 6 +
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 7 +
drivers/clk/hisilicon/Kconfig | 6 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/clk-hi3660-stub.c | 186 +++++++++++++++++++++
include/dt-bindings/clock/hi3660-clock.h | 7 +
6 files changed, 213 insertions(+)
create mode 100644 drivers/clk/hisilicon/clk-hi3660-stub.c
--
1.9.1
^ permalink raw reply
* [PATCH v3 3/3] dts: arm64: Add mailbox binding for hi3660
From: Xu YiPing @ 2017-11-17 9:24 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
guodong.xu-QSEj5FYQhm4dnm+yROfE0A,
haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
xuezhiliang-C8/M+/jPZTeaMJb+Lgu22Q,
kevin.wangtao-C8/M+/jPZTeaMJb+Lgu22Q,
zhongkaihua-hv44wF8Li93QT0dZR+AlfA
In-Reply-To: <1510910672-1409-1-git-send-email-xuyiping-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
From: Kaihua Zhong <zhongkaihua-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Add DT binding for mailbox driver.
Signed-off-by: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Ruyi Wang <wangruyi-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Signed-off-by: Kaihua Zhong <zhongkaihua-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 610990f..451b6bf 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -285,6 +285,14 @@
#reset-cells = <2>;
};
+ mailbox: mailbox@e896b000 {
+ compatible = "hisilicon,hi3660-mbox";
+ reg = <0x0 0xe896b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <3>;
+ };
+
dual_timer0: timer@fff14000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x0 0xfff14000 0x0 0x1000>;
--
1.9.1
--
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^ permalink raw reply related
* [PATCH v3 2/3] mailbox: Add support for Hi3660 mailbox
From: Xu YiPing @ 2017-11-17 9:24 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
guodong.xu-QSEj5FYQhm4dnm+yROfE0A,
haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
xuezhiliang-C8/M+/jPZTeaMJb+Lgu22Q,
kevin.wangtao-C8/M+/jPZTeaMJb+Lgu22Q,
zhongkaihua-hv44wF8Li93QT0dZR+AlfA
In-Reply-To: <1510910672-1409-1-git-send-email-xuyiping-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
From: Kaihua Zhong <zhongkaihua-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Hi3660 mailbox controller is used to send message within multiple
processors, MCU, HIFI, etc. It supports 32 mailbox channels and every
channel can only be used for single transferring direction. Once the
channel is enabled, it needs to specify the destination interrupt and
acknowledge interrupt, these two interrupt vectors are used to create
the connection between the mailbox and interrupt controllers.
The data transferring supports two modes, one is named as "automatic
acknowledge" mode so after send message the kernel doesn't need to wait
for acknowledge from remote and directly return; there have another mode
is to rely on handling interrupt for acknowledge.
This commit is for initial version driver, which only supports
"automatic acknowledge" mode to support CPU clock, which is the only
one consumer to use mailbox and has been verified. Later may enhance
this driver for interrupt mode (e.g. for supporting HIFI).
Signed-off-by: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Ruyi Wang <wangruyi-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Signed-off-by: Kaihua Zhong <zhongkaihua-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
drivers/mailbox/Kconfig | 8 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/hi3660-mailbox.c | 322 +++++++++++++++++++++++++++++++++++++++
3 files changed, 332 insertions(+)
create mode 100644 drivers/mailbox/hi3660-mailbox.c
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index c5731e5..4b5d6e9 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -108,6 +108,14 @@ config TI_MESSAGE_MANAGER
multiple processors within the SoC. Select this driver if your
platform has support for the hardware block.
+config HI3660_MBOX
+ tristate "Hi3660 Mailbox"
+ depends on ARCH_HISI && OF
+ help
+ An implementation of the hi3660 mailbox. It is used to send message
+ between application processors and other processors/MCU/DSP. Select
+ Y here if you want to use Hi3660 mailbox controller.
+
config HI6220_MBOX
tristate "Hi6220 Mailbox"
depends on ARCH_HISI
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index d54e412..7d1bd51 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -26,6 +26,8 @@ obj-$(CONFIG_TI_MESSAGE_MANAGER) += ti-msgmgr.o
obj-$(CONFIG_XGENE_SLIMPRO_MBOX) += mailbox-xgene-slimpro.o
+obj-$(CONFIG_HI3660_MBOX) += hi3660-mailbox.o
+
obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o
obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o
diff --git a/drivers/mailbox/hi3660-mailbox.c b/drivers/mailbox/hi3660-mailbox.c
new file mode 100644
index 0000000..ba80834
--- /dev/null
+++ b/drivers/mailbox/hi3660-mailbox.c
@@ -0,0 +1,322 @@
+/*
+ * Hisilicon's Hi3660 mailbox controller driver
+ *
+ * Copyright (c) 2017 Hisilicon Limited.
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * Author: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mailbox_controller.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "mailbox.h"
+
+#define MBOX_CHAN_MAX 32
+
+#define MBOX_RX (0x0)
+#define MBOX_TX (0x1)
+
+#define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x40))
+#define MBOX_SRC_REG (0x00)
+#define MBOX_DST_REG (0x04)
+#define MBOX_DCLR_REG (0x08)
+#define MBOX_DSTAT_REG (0x0c)
+#define MBOX_MODE_REG (0x10)
+#define MBOX_IMASK_REG (0x14)
+#define MBOX_ICLR_REG (0x18)
+#define MBOX_SEND_REG (0x1c)
+#define MBOX_DATA_REG (0x20)
+
+#define MBOX_IPC_LOCK_REG (0xa00)
+#define MBOX_IPC_UNLOCK (0x1acce551)
+
+#define MBOX_AUTOMATIC_ACK (1)
+
+#define MBOX_STATE_IDLE BIT(4)
+#define MBOX_STATE_ACK BIT(7)
+
+#define MBOX_MSG_LEN 8
+
+/**
+ * Hi3660 mailbox channel device data
+ *
+ * A channel can be used for TX or RX, it can trigger remote
+ * processor interrupt to notify remote processor and can receive
+ * interrupt if has incoming message.
+ *
+ * @dst_irq: Interrupt vector for remote processor
+ * @ack_irq: Interrupt vector for local processor
+ */
+struct hi3660_mbox_dev {
+ unsigned int dst_irq;
+ unsigned int ack_irq;
+};
+
+/**
+ * Hi3660 mailbox controller data
+ *
+ * Mailbox controller includes 32 channels and can allocate
+ * channel for message transferring.
+ *
+ * @dev: Device to which it is attached
+ * @base: Base address of the register mapping region
+ * @chan: Representation of channels in mailbox controller
+ * @mdev: Representation of channel device data
+ * @controller: Representation of a communication channel controller
+ */
+struct hi3660_mbox {
+ struct device *dev;
+ void __iomem *base;
+ struct mbox_chan chan[MBOX_CHAN_MAX];
+ struct hi3660_mbox_dev mdev[MBOX_CHAN_MAX];
+ struct mbox_controller controller;
+};
+
+static inline struct hi3660_mbox *to_hi3660_mbox(struct mbox_controller *mbox)
+{
+ return container_of(mbox, struct hi3660_mbox, controller);
+}
+
+static int hi3660_mbox_check_state(struct mbox_chan *chan)
+{
+ unsigned long ch = (unsigned long)chan->con_priv;
+ struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
+ struct hi3660_mbox_dev *mdev = &mbox->mdev[ch];
+ void __iomem *base = MBOX_BASE(mbox, ch);
+ unsigned long val;
+ unsigned int state, ret;
+
+ /* Mailbox is idle so directly bail out */
+ state = readl_relaxed(base + MBOX_MODE_REG);
+ if (state & MBOX_STATE_IDLE)
+ return 0;
+
+ /* Wait for acknowledge from remote */
+ ret = readx_poll_timeout_atomic(readl_relaxed, base + MBOX_MODE_REG,
+ val, (val & MBOX_STATE_ACK), 1000, 300000);
+ if (ret) {
+ dev_err(mbox->dev, "%s: timeout for receiving ack\n", __func__);
+ return ret;
+ }
+
+ /* Ensure channel is released */
+ writel_relaxed(0xffffffff, base + MBOX_IMASK_REG);
+ writel_relaxed(BIT(mdev->ack_irq), base + MBOX_SRC_REG);
+
+ return 0;
+}
+
+static int hi3660_mbox_unlock(struct mbox_chan *chan)
+{
+ struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
+ unsigned int val, retry = 3;
+
+ do {
+ writel_relaxed(MBOX_IPC_UNLOCK, mbox->base + MBOX_IPC_LOCK_REG);
+
+ val = readl_relaxed(mbox->base + MBOX_IPC_LOCK_REG);
+ if (!val)
+ break;
+
+ udelay(10);
+ } while (retry--);
+
+ return (!val) ? 0 : -ETIMEDOUT;
+}
+
+static int hi3660_mbox_acquire_channel(struct mbox_chan *chan)
+{
+ unsigned long ch = (unsigned long)chan->con_priv;
+ struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
+ struct hi3660_mbox_dev *mdev = &mbox->mdev[ch];
+ void __iomem *base = MBOX_BASE(mbox, ch);
+ unsigned int val, retry;
+
+ for (retry = 10; retry; retry--) {
+ /* Check if channel has been acquired */
+ if (readl_relaxed(base + MBOX_MODE_REG) & MBOX_STATE_IDLE) {
+ writel_relaxed(BIT(mdev->ack_irq), base + MBOX_SRC_REG);
+ val = readl_relaxed(base + MBOX_SRC_REG);
+ if (val & BIT(mdev->ack_irq))
+ break;
+ }
+ }
+
+ return retry ? 0 : -ETIMEDOUT;
+}
+
+static int hi3660_mbox_send(struct mbox_chan *chan, u32 *msg)
+{
+ unsigned long ch = (unsigned long)chan->con_priv;
+ struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
+ struct hi3660_mbox_dev *mdev = &mbox->mdev[ch];
+ void __iomem *base = MBOX_BASE(mbox, ch);
+ unsigned int i;
+
+ /* Clear mask for destination interrupt */
+ writel_relaxed(~BIT(mdev->dst_irq), base + MBOX_IMASK_REG);
+
+ /* Config destination for interrupt vector */
+ writel_relaxed(BIT(mdev->dst_irq), base + MBOX_DST_REG);
+
+ /* Automatic acknowledge mode */
+ writel_relaxed(MBOX_AUTOMATIC_ACK, base + MBOX_MODE_REG);
+
+ /* Fill message data */
+ for (i = 0; i < MBOX_MSG_LEN; i++)
+ writel_relaxed(msg[i], base + MBOX_DATA_REG + i * 4);
+
+ /* Trigger data transferring */
+ writel_relaxed(BIT(mdev->ack_irq), base + MBOX_SEND_REG);
+ return 0;
+}
+
+static int hi3660_mbox_send_data(struct mbox_chan *chan, void *msg)
+{
+ struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
+ int err;
+
+ err = hi3660_mbox_check_state(chan);
+ if (err) {
+ dev_err(mbox->dev, "checking state failed\n");
+ return err;
+ }
+
+ err = hi3660_mbox_unlock(chan);
+ if (err) {
+ dev_err(mbox->dev, "unlocking mailbox failed\n");
+ return err;
+ }
+
+ err = hi3660_mbox_acquire_channel(chan);
+ if (err) {
+ dev_err(mbox->dev, "acquiring channel failed\n");
+ return err;
+ }
+
+ return hi3660_mbox_send(chan, msg);
+}
+
+static struct mbox_chan_ops hi3660_mbox_ops = {
+ .send_data = hi3660_mbox_send_data,
+};
+
+static struct mbox_chan *hi3660_mbox_xlate(struct mbox_controller *controller,
+ const struct of_phandle_args *spec)
+{
+ struct hi3660_mbox *mbox = to_hi3660_mbox(controller);
+ struct hi3660_mbox_dev *mdev;
+ unsigned int ch = spec->args[0];
+
+ if (ch >= MBOX_CHAN_MAX) {
+ dev_err(mbox->dev, "Invalid channel idx %d\n", ch);
+ return ERR_PTR(-EINVAL);
+ }
+
+ mdev = &mbox->mdev[ch];
+ mdev->dst_irq = spec->args[1];
+ mdev->ack_irq = spec->args[2];
+
+ return &mbox->chan[ch];
+}
+
+static const struct of_device_id hi3660_mbox_of_match[] = {
+ { .compatible = "hisilicon,hi3660-mbox", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, hi3660_mbox_of_match);
+
+static int hi3660_mbox_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct hi3660_mbox *mbox;
+ struct mbox_chan *chan;
+ struct resource *res;
+ unsigned long ch;
+ int err;
+
+ mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
+ if (!mbox)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ mbox->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(mbox->base))
+ return PTR_ERR(mbox->base);
+
+ mbox->dev = dev;
+ mbox->controller.dev = dev;
+ mbox->controller.chans = mbox->chan;
+ mbox->controller.num_chans = MBOX_CHAN_MAX;
+ mbox->controller.ops = &hi3660_mbox_ops;
+ mbox->controller.of_xlate = hi3660_mbox_xlate;
+
+ /* Initialize mailbox channel data */
+ chan = mbox->chan;
+ for (ch = 0; ch < MBOX_CHAN_MAX; ch++)
+ chan[ch].con_priv = (void *)ch;
+
+ err = mbox_controller_register(&mbox->controller);
+ if (err) {
+ dev_err(dev, "Failed to register mailbox %d\n", err);
+ return err;
+ }
+
+ platform_set_drvdata(pdev, mbox);
+ dev_info(dev, "Mailbox enabled\n");
+ return 0;
+}
+
+static int hi3660_mbox_remove(struct platform_device *pdev)
+{
+ struct hi3660_mbox *mbox = platform_get_drvdata(pdev);
+
+ mbox_controller_unregister(&mbox->controller);
+ return 0;
+}
+
+static struct platform_driver hi3660_mbox_driver = {
+ .probe = hi3660_mbox_probe,
+ .remove = hi3660_mbox_remove,
+ .driver = {
+ .name = "hi3660-mbox",
+ .of_match_table = hi3660_mbox_of_match,
+ },
+};
+
+static int __init hi3660_mbox_init(void)
+{
+ return platform_driver_register(&hi3660_mbox_driver);
+}
+core_initcall(hi3660_mbox_init);
+
+static void __exit hi3660_mbox_exit(void)
+{
+ platform_driver_unregister(&hi3660_mbox_driver);
+}
+module_exit(hi3660_mbox_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Hisilicon Hi3660 Mailbox Controller");
+MODULE_AUTHOR("Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>");
--
1.9.1
--
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^ permalink raw reply related
* [PATCH v3 1/3] dt-bindings: mailbox: Introduce Hi3660 controller binding
From: Xu YiPing @ 2017-11-17 9:24 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
guodong.xu-QSEj5FYQhm4dnm+yROfE0A,
haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
xuezhiliang-C8/M+/jPZTeaMJb+Lgu22Q,
kevin.wangtao-C8/M+/jPZTeaMJb+Lgu22Q,
zhongkaihua-hv44wF8Li93QT0dZR+AlfA
In-Reply-To: <1510910672-1409-1-git-send-email-xuyiping-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
From: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Introduce a binding for the Hi3660 mailbox controller, the mailbox is
used within application processor (AP), communication processor (CP),
HIFI and MCU, etc.
Signed-off-by: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
.../bindings/mailbox/hisilicon,hi3660-mailbox.txt | 51 ++++++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt
diff --git a/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt
new file mode 100644
index 0000000..3e5b453
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt
@@ -0,0 +1,51 @@
+Hisilicon Hi3660 Mailbox Controller
+
+Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages
+are passed between processors, including application & communication
+processors, MCU, HIFI, etc. Each channel is unidirectional and accessed
+by using MMIO registers; it supports maximum to 8 words message.
+
+Controller
+----------
+
+Required properties:
+- compatible: : Shall be "hisilicon,hi3660-mbox"
+- reg: : Offset and length of the device's register set
+- #mbox-cells: : Must be 3
+ <&phandle channel dst_irq ack_irq>
+ phandle : Label name of controller
+ channel : Channel number
+ dst_irq : Remote interrupt vector
+ ack_irq : Local interrupt vector
+
+- interrupts: : Contains the two IRQ lines for mailbox.
+
+Example:
+
+mailbox: mailbox@e896b000 {
+ compatible = "hisilicon,hi3660-mbox";
+ reg = <0x0 0xe896b000 0x0 0x1000>;
+ interrupts = <0x0 0xc0 0x4>,
+ <0x0 0xc1 0x4>;
+ #mbox-cells = <3>;
+};
+
+Client
+------
+
+Required properties:
+- compatible : See the client docs
+- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt)
+ Cells must match 'mbox-cells' (See Controller docs above)
+
+Optional properties
+- mbox-names : Name given to channels seen in the 'mboxes' property.
+
+Example:
+
+stub_clock: stub_clock@e896b500 {
+ compatible = "hisilicon,hi3660-stub-clk";
+ reg = <0x0 0xe896b500 0x0 0x0100>;
+ #clock-cells = <1>;
+ mboxes = <&mailbox 13 3 0>;
+};
--
1.9.1
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^ permalink raw reply related
* [PATCH v3 0/3] Add support for Hi3660 mailbox driver
From: Xu YiPing @ 2017-11-17 9:24 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
guodong.xu-QSEj5FYQhm4dnm+yROfE0A,
haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
xuezhiliang-C8/M+/jPZTeaMJb+Lgu22Q,
kevin.wangtao-C8/M+/jPZTeaMJb+Lgu22Q,
zhongkaihua-hv44wF8Li93QT0dZR+AlfA
From: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Hi3660 mailbox controller is used to send message within multiple
processors, MCU, HIFI, etc. This patch series is to implement an
initial version for Hi3660 mailbox driver with "automatic
acknowledge" mode.
The patch set have been verified with Hi3660 stub clock driver, so
we can send message to MCU to execute CPU frequency scaling. This is
tested on 96boards Hikey960.
Changes from v2:
* According to Mark Rutland suggestions, removed sev()/wfe() from
driver, the system has no two masters sharing the same channel for
data transferring so we don't need these instructions;
* Refined DT binding and doc according to Rob suggestions;
* Refined driver according to Julien suggestions;
Changes from v1:
* Added cover letter to track the changelog;
* Added document for DT binding;
* Refactored and simplized mailbox driver with "automatic ack" mode;
* Refined commit logs for patches;
Kaihua Zhong (2):
mailbox: Add support for Hi3660 mailbox
dts: arm64: Add mailbox binding for hi3660
Leo Yan (1):
dt-bindings: mailbox: Introduce Hi3660 controller binding
.../bindings/mailbox/hisilicon,hi3660-mailbox.txt | 51 ++++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 +
drivers/mailbox/Kconfig | 8 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/hi3660-mailbox.c | 322 +++++++++++++++++++++
5 files changed, 391 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt
create mode 100644 drivers/mailbox/hi3660-mailbox.c
--
1.9.1
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^ permalink raw reply
* Re: [PATCH] gpio: pca953x: fix vendor prefix for PCA9654
From: Geert Uytterhoeven @ 2017-11-17 9:06 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Linus Walleij, Rob Herring, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, Mark Rutland, Linux-Renesas
In-Reply-To: <20171116201842.006310882@cogentembedded.com>
Hi Sergei,
On Thu, Nov 16, 2017 at 9:18 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Despite commit 55020c8056a8 ("of: Add vendor prefix for ON Semiconductor
> Corp.") was made long ago, the latter commit 9f49f6dd0473 ("gpio: pca953x:
> add onsemi,pca9654 id") made use of another, undocumented vendor prefix.
Ouch...
> Since such prefix doesn't seem to be used in any device trees, I think we
> can just fix the "compatible" string in the driver and the bindings and be
> done with that...
>
> Fixes: 9f49f6dd0473 ("gpio: pca953x: add onsemi,pca9654 id")
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> The patch is against the 'fixes' branch of LinusW's 'linux-gpio.git' repo.
>
> Documentation/devicetree/bindings/gpio/gpio-pca953x.txt | 2 +-
> drivers/gpio/gpio-pca953x.c | 2 +-
There's another (different) one in
Documentation/devicetree/bindings/misc/idt_89hpesx.txt
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH V1 1/4] qcom: spmi-wled: Add support for qcom wled driver
From: Lee Jones @ 2017-11-17 8:33 UTC (permalink / raw)
To: Bjorn Andersson
Cc: kgunda, linux-arm-msm, Daniel Thompson, Jingoo Han,
Richard Purdie, Jacek Anaszewski, Pavel Machek, Rob Herring,
Mark Rutland, Bartlomiej Zolnierkiewicz, linux-leds, devicetree,
linux-kernel, linux-fbdev, linux-arm-msm-owner
In-Reply-To: <20171117065640.GU28761@minitux>
On Thu, 16 Nov 2017, Bjorn Andersson wrote:
> On Thu 16 Nov 22:36 PST 2017, kgunda@codeaurora.org wrote:
>
> > On 2017-11-16 22:25, Bjorn Andersson wrote:
> > > On Thu 16 Nov 04:18 PST 2017, Kiran Gunda wrote:
> > >
> > > > WLED driver provides the interface to the display driver to
> > > > adjust the brightness of the display backlight.
> > > >
> > >
> > > Hi Kiran,
> > >
> > > This driver has a lot in common with the already upstream pm8941-wled.c,
> > > because it's just a new revision of the same block.
> > >
> > > Please extend the existing driver rather than providing a new one
> > > (and yes, renaming the file is okay).
> > >
> > > Regards,
> > > Bjorn
> >
> > Hi Bjorn,
> >
> > Yes this driver design is similar to pm8941, however the WLED HW block
> > has undergone quite a few changes in analog and digital from PM8941 to
> > PM8998.
>
> I can see that, looking at the documentation.
>
> > Few of them include splitting one module into wled-ctrl and wled-sink
> > peripherals, changes in the register offsets and the bit
> > interpretation.
>
> This is typical and something we need to handle in all these drivers, to
> avoid having one driver per platform.
>
> > Hence we concluded that it was better to have a new driver to support
> > this new gen WELD module and decouple it from the pm8941.
>
> Okay, I can see how it's easier to not have to case about anything but
> pmi8998 in this driver, but where do you add the support for other WLED
> versions? What about PMI8994? Will there not be similar differences
> (registers that has moved around) in the future?
>
> > Also, going forward this driver will support AMOLED AVDD rail (not
> > supported by pm8941) touching a few more registers/configuration and
> > newer PMICs.
>
> Is this a feature that was introduced in PMI8998? Will this support not
> be dependent on the pmic version?
>
> > So spinning off a new driver would make it cleaner and easier to
> > extend further.
> >
>
> It's for sure easier at this point in time, but your argumentation
> implies that PMI8998+1 should go into it's own driver as well.
>
> I suspect that if you're going to reuse this driver for future PMIC
> versions you will have to deal with register layout differences and new
> feature set, and as such I'm not convinced that a new driver is needed.
>
> Can you give any concrete examples of where it is not possible or
> undesirable to maintain the pm8941 support in the same driver?
I agree with Bjorn. If you can support multiple devices in a single
driver with a couple of simple ddata struct differences and a slightly
different regmap, you should.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH v7 04/13] slimbus: core: Add slim controllers support
From: Greg KH @ 2017-11-17 8:13 UTC (permalink / raw)
To: Vinod Koul
Cc: Srinivas Kandagatla, broonie, alsa-devel, sdharia, bp, poeschel,
treding, andreas.noever, alan, mathieu.poirier, daniel, jkosina,
sharon.dvir1, joe, davem, james.hogan, michael.opdenacker,
robh+dt, pawel.moll, mark.rutland, devicetree, linux-kernel,
linux-arm-msm, arnd
In-Reply-To: <20171117044222.GK3187@localhost>
On Fri, Nov 17, 2017 at 10:12:22AM +0530, Vinod Koul wrote:
> On Thu, Nov 16, 2017 at 05:29:35PM +0000, Srinivas Kandagatla wrote:
> > thanks for the comments.
> >
> >
> > On 16/11/17 16:42, Vinod Koul wrote:
> > >On Wed, Nov 15, 2017 at 02:10:34PM +0000, srinivas.kandagatla@linaro.org wrote:
> > >
> > >>+static void slim_dev_release(struct device *dev)
> > >>+{
> > >>+ struct slim_device *sbdev = to_slim_device(dev);
> > >>+
> > >>+ put_device(sbdev->ctrl->dev);
> > >
> > >which device would that be?
> > This is controller device
> >
> > >
> > >>+static int slim_add_device(struct slim_controller *ctrl,
> > >>+ struct slim_device *sbdev,
> > >>+ struct device_node *node)
> > >>+{
> > >>+ sbdev->dev.bus = &slimbus_bus;
> > >>+ sbdev->dev.parent = ctrl->dev;
> > >>+ sbdev->dev.release = slim_dev_release;
> > >>+ sbdev->dev.driver = NULL;
> > >>+ sbdev->ctrl = ctrl;
> > >>+
> > >>+ dev_set_name(&sbdev->dev, "%x:%x:%x:%x",
> > >>+ sbdev->e_addr.manf_id,
> > >>+ sbdev->e_addr.prod_code,
> > >>+ sbdev->e_addr.dev_index,
> > >>+ sbdev->e_addr.instance);
> > >>+
> > >>+ get_device(ctrl->dev);
> > >
> > >is this controller device and you ensuring it doesnt go away while you have
> > >slaves on it?
> >
> > Yes.
>
> I thought since you are marking ctrl->dev as parent, the device core should
> ensure that parent doesn't go off when you have child device?
>
> Greg, is that understanding correct, if so we may not need these calls.
That understanding should be correct, as the reference count is
incremented on the parent when a child is added.
It would be trivial for this to be tested, and yes, I am pretty sure you
don't need this call.
thanks,
greg k-h
^ permalink raw reply
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