* Re: [PATCH 2/5] i2c: meson: add configurable divider factors
From: Martin Blumenstingl @ 2017-11-17 20:32 UTC (permalink / raw)
To: Yixun Lan
Cc: Wolfram Sang, Rob Herring, Mark Rutland, linux-i2c, devicetree,
Kevin Hilman, Neil Armstrong, linux-kernel, Jian Hu, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jerome Brunet
In-Reply-To: <20171117080236.32504-3-yixun.lan@amlogic.com>
On Fri, Nov 17, 2017 at 9:02 AM, Yixun Lan <yixun.lan@amlogic.com> wrote:
> From: Jian Hu <jian.hu@amlogic.com>
>
> This patch try to add support for I2C controller in Meson-AXG SoC,
> Due to the IP changes between I2C controller, we need to introduce
> a compatible data to make the divider factor configurable.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> drivers/i2c/busses/i2c-meson.c | 32 ++++++++++++++++++++++++++++----
> 1 file changed, 28 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-meson.c b/drivers/i2c/busses/i2c-meson.c
> index 88d15b92ec35..517f2cddeff3 100644
> --- a/drivers/i2c/busses/i2c-meson.c
> +++ b/drivers/i2c/busses/i2c-meson.c
> @@ -16,6 +16,7 @@
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> #include <linux/types.h>
>
> @@ -57,6 +58,10 @@ enum {
> STATE_WRITE,
> };
>
> +struct meson_i2c_data {
> + unsigned char div_factor;
> +};
> +
> /**
> * struct meson_i2c - Meson I2C device private data
> *
> @@ -93,6 +98,8 @@ struct meson_i2c {
> struct completion done;
> u32 tokens[2];
> int num_tokens;
> +
> + struct meson_i2c_data *data;
shouldn't this be const (like the definitions below)?
> };
>
> static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
> @@ -128,7 +135,7 @@ static void meson_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
> unsigned long clk_rate = clk_get_rate(i2c->clk);
> unsigned int div;
>
> - div = DIV_ROUND_UP(clk_rate, freq * 4);
> + div = DIV_ROUND_UP(clk_rate, freq * i2c->data->div_factor);
>
> /* clock divider has 12 bits */
> if (div >= (1 << 12)) {
> @@ -376,6 +383,9 @@ static int meson_i2c_probe(struct platform_device *pdev)
> spin_lock_init(&i2c->lock);
> init_completion(&i2c->done);
>
> + i2c->data = (struct meson_i2c_data *)
> + of_device_get_match_data(&pdev->dev);
> +
> i2c->clk = devm_clk_get(&pdev->dev, NULL);
> if (IS_ERR(i2c->clk)) {
> dev_err(&pdev->dev, "can't get device clock\n");
> @@ -440,11 +450,25 @@ static int meson_i2c_remove(struct platform_device *pdev)
> return 0;
> }
>
> +static const struct meson_i2c_data i2c_meson6_data = {
> + .div_factor = 4,
> +};
> +
> +static const struct meson_i2c_data i2c_gxbb_data = {
> + .div_factor = 4,
> +};
> +
> +static const struct meson_i2c_data i2c_axg_data = {
> + .div_factor = 3,
> +};
> +
> static const struct of_device_id meson_i2c_match[] = {
> - { .compatible = "amlogic,meson6-i2c" },
> - { .compatible = "amlogic,meson-gxbb-i2c" },
> - { },
> + { .compatible = "amlogic,meson6-i2c", .data = &i2c_meson6_data },
> + { .compatible = "amlogic,meson-gxbb-i2c", .data = &i2c_gxbb_data },
> + { .compatible = "amlogic,meson-axg-i2c", .data = &i2c_axg_data },
> + {},
> };
> +
> MODULE_DEVICE_TABLE(of, meson_i2c_match);
>
> static struct platform_driver meson_i2c_driver = {
> --
> 2.14.1
>
>
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply
* Re: [PATCH v2 1/4] dt-bindings: media: rcar_vin: Reverse SoC part number list
From: Rob Herring @ 2017-11-17 20:31 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Mauro Carvalho Chehab, Mark Rutland, Niklas Söderlund,
linux-media, linux-renesas-soc, devicetree, Simon Horman,
Geert Uytterhoeven, Chris Paterson, Biju Das
In-Reply-To: <1510856571-30281-2-git-send-email-fabrizio.castro@bp.renesas.com>
On Thu, Nov 16, 2017 at 06:22:48PM +0000, Fabrizio Castro wrote:
> Change the sorting of the part numbers from descending to ascending to
> match with other documentation.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>
> ---
> v1->v2:
> * new patch triggered by Geert's comment, see the below link for details:
> https://www.mail-archive.com/linux-media@vger.kernel.org/msg121992.html
>
> Documentation/devicetree/bindings/media/rcar_vin.txt | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH] dt-bindings: i2c: eeprom: Add Renesas R1EX24128
From: Rob Herring @ 2017-11-17 20:30 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Mark Rutland, Wolfram Sang, Bartosz Golaszewski, devicetree,
linux-i2c, linux-renesas-soc
In-Reply-To: <1510839994-12473-1-git-send-email-geert+renesas@glider.be>
On Thu, Nov 16, 2017 at 02:46:34PM +0100, Geert Uytterhoeven wrote:
> Document the compatible value for the Renesas R1EX24128ASAS0A two-wire
> serial interface EEPROM, so it can be used in DTS files without causing
> checkpatch warnings.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Documentation/devicetree/bindings/eeprom/eeprom.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH V1 2/4] qcom: spmi-wled: Add support for short circuit handling
From: Rob Herring @ 2017-11-17 20:30 UTC (permalink / raw)
To: Kiran Gunda
Cc: bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, Lee Jones, Daniel Thompson,
Jingoo Han, Richard Purdie, Jacek Anaszewski, Pavel Machek,
Mark Rutland, Bartlomiej Zolnierkiewicz,
linux-leds-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-owner-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1510834717-21765-3-git-send-email-kgunda-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On Thu, Nov 16, 2017 at 05:48:35PM +0530, Kiran Gunda wrote:
> Handle the short circuit(SC) interrupt and check if the SC interrupt
> is valid. Re-enable the module to check if it goes away. Disable the
> module altogether if the SC event persists.
>
> Signed-off-by: Kiran Gunda <kgunda-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
> .../bindings/leds/backlight/qcom-spmi-wled.txt | 22 ++++
... and also put all the binding in one patch. I want to review the full
view of the h/w, not piecemeal.
> drivers/video/backlight/qcom-spmi-wled.c | 126 ++++++++++++++++++++-
> 2 files changed, 142 insertions(+), 6 deletions(-)
--
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^ permalink raw reply
* Re: [PATCH V1 1/4] qcom: spmi-wled: Add support for qcom wled driver
From: Rob Herring @ 2017-11-17 20:28 UTC (permalink / raw)
To: Kiran Gunda
Cc: bjorn.andersson, linux-arm-msm, Lee Jones, Daniel Thompson,
Jingoo Han, Richard Purdie, Jacek Anaszewski, Pavel Machek,
Mark Rutland, Bartlomiej Zolnierkiewicz, linux-leds, devicetree,
linux-kernel, linux-fbdev, linux-arm-msm-owner
In-Reply-To: <1510834717-21765-2-git-send-email-kgunda@codeaurora.org>
On Thu, Nov 16, 2017 at 05:48:34PM +0530, Kiran Gunda wrote:
> WLED driver provides the interface to the display driver to
> adjust the brightness of the display backlight.
>
> Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
> ---
> .../bindings/leds/backlight/qcom-spmi-wled.txt | 90 ++++
Please split bindings to separate patch.
> drivers/video/backlight/Kconfig | 9 +
> drivers/video/backlight/Makefile | 1 +
> drivers/video/backlight/qcom-spmi-wled.c | 504 +++++++++++++++++++++
> 4 files changed, 604 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/leds/backlight/qcom-spmi-wled.txt
> create mode 100644 drivers/video/backlight/qcom-spmi-wled.c
^ permalink raw reply
* Re: [PATCH] dt-bindings: rtc: imxdi: Improve the bindings text
From: Rob Herring @ 2017-11-17 20:26 UTC (permalink / raw)
To: Fabio Estevam
Cc: alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
devicetree-u79uwXL29TY76Z2rM5mHXA, jbe-bIcnvbaLZ9MEGnE8C9+IrQ,
Fabio Estevam
In-Reply-To: <1510750793-25564-1-git-send-email-festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Wed, Nov 15, 2017 at 10:59:53AM -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
>
> Improve the bindings text by doing the following changes:
>
> - Remove the i.MX53 reference, as the RTC on i.MX53 is a different hardware
> - Add 'clocks' to the list of required properties
> - Explain that the optional security violation irq is the second entry
> - Use the real unit address and irq numbers for i.MX25
>
> Signed-off-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
> ---
> Documentation/devicetree/bindings/rtc/imxdi-rtc.txt | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH V6] clk: qcom: Add spmi_pmic clock divider support
From: Rob Herring @ 2017-11-17 20:22 UTC (permalink / raw)
To: Tirupathi Reddy
Cc: sboyd, mturquette, mark.rutland, andy.gross, david.brown,
linux-clk, devicetree, linux-kernel, linux-arm-msm, linux-soc
In-Reply-To: <1510912127-4582-1-git-send-email-tirupath@codeaurora.org>
On Fri, Nov 17, 2017 at 03:18:47PM +0530, Tirupathi Reddy wrote:
> Clkdiv module provides a clock output on the PMIC with CXO as
> the source. This clock can be routed through PMIC GPIOs. Add
> a device driver to configure this clkdiv module.
>
> Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Normally your S-o-B would be last.
> ---
> .../bindings/clock/clk-spmi-pmic-div.txt | 59 ++++
Please split bindings to a separate patch.
Otherwise,
Acked-by: Rob Herring <robh@kernel.org>
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/clk-spmi-pmic-div.c | 308 +++++++++++++++++++++
> 4 files changed, 377 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt
> create mode 100644 drivers/clk/qcom/clk-spmi-pmic-div.c
^ permalink raw reply
* Re: [PATCH v10 5/8] ARM: dts: sunxi: Restore EMAC changes (boards)
From: Philipp Rossak @ 2017-11-17 20:05 UTC (permalink / raw)
To: Corentin Labbe, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8
Cc: netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171031081915.18960-6-clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hey,
Sorry for the bringing this up again.
Isn't there a: ethernet0 = &emac; for some boards missing?
Best,
Philipp
(Sorry for sending this to some persons more than once! My Thunderbird
sent mails in html and didn't reach the mailing lists. I hope it works
now :) )
On 31.10.2017 09:19, Corentin Labbe wrote:
> The original dwmac-sun8i DT bindings have some issue on how to handle
> integrated PHY and was reverted in last RC of 4.13.
> But now we have a solution so we need to get back that was reverted.
>
> This patch restore all boards DT about dwmac-sun8i
> This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
>
> Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Acked-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 +++++++++
> arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +++++++++++++++++++
> arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 19 +++++++++++++++++++
> arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 +++++++
> arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 ++++++++
> arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 ++++++++
> arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +++++
> arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 ++++++++
> arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 ++++++++++++++++++++++
> arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 ++++++++++++++++
> 10 files changed, 121 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> index b1502df7b509..6713d0f2b3f4 100644
> --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> @@ -56,6 +56,8 @@
>
> aliases {
> serial0 = &uart0;
> + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
> + ethernet0 = &emac;
> ethernet1 = &xr819;
> };
>
> @@ -102,6 +104,13 @@
> status = "okay";
> };
>
> +&emac {
> + phy-handle = <&int_mii_phy>;
> + phy-mode = "mii";
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> +
> &mmc0 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc0_pins_a>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
> index e1dba9ffa94b..f2292deaa590 100644
> --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
> @@ -52,6 +52,7 @@
> compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
>
> aliases {
> + ethernet0 = &emac;
> serial0 = &uart0;
> serial1 = &uart1;
> };
> @@ -111,6 +112,24 @@
> status = "okay";
> };
>
> +&emac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&emac_rgmii_pins>;
> + phy-supply = <®_gmac_3v3>;
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii";
> +
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> +
> +&external_mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + };
> +};
> +
> &ir {
> pinctrl-names = "default";
> pinctrl-0 = <&ir_pins_a>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> index 73766d38ee6c..cfb96da3cfef 100644
> --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> @@ -66,6 +66,25 @@
> status = "okay";
> };
>
> +&emac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&emac_rgmii_pins>;
> + phy-supply = <®_gmac_3v3>;
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii";
> +
> + allwinner,leds-active-low;
> +
> + status = "okay";
> +};
> +
> +&external_mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <7>;
> + };
> +};
> +
> &ir {
> pinctrl-names = "default";
> pinctrl-0 = <&ir_pins_a>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
> index 8d2cc6e9a03f..78f6c24952dd 100644
> --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
> @@ -46,3 +46,10 @@
> model = "FriendlyARM NanoPi NEO";
> compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
> };
> +
> +&emac {
> + phy-handle = <&int_mii_phy>;
> + phy-mode = "mii";
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
> index 1bf51802f5aa..b20be95b49d5 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
> @@ -54,6 +54,7 @@
> aliases {
> serial0 = &uart0;
> /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
> + ethernet0 = &emac;
> ethernet1 = &rtl8189;
> };
>
> @@ -117,6 +118,13 @@
> status = "okay";
> };
>
> +&emac {
> + phy-handle = <&int_mii_phy>;
> + phy-mode = "mii";
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> +
> &ir {
> pinctrl-names = "default";
> pinctrl-0 = <&ir_pins_a>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
> index a1c6ff6fd05d..82e5d28cd698 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
> @@ -52,6 +52,7 @@
> compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
>
> aliases {
> + ethernet0 = &emac;
> serial0 = &uart0;
> };
>
> @@ -97,6 +98,13 @@
> status = "okay";
> };
>
> +&emac {
> + phy-handle = <&int_mii_phy>;
> + phy-mode = "mii";
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> +
> &mmc0 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
> index 8b93f5c781a7..a10281b455f5 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
> @@ -53,6 +53,11 @@
> };
> };
>
> +&emac {
> + /* LEDs changed to active high on the plus */
> + /delete-property/ allwinner,leds-active-low;
> +};
> +
> &mmc1 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc1_pins_a>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
> index d0b80fda2f6b..6d98bcfbe877 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
> @@ -52,6 +52,7 @@
> compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
>
> aliases {
> + ethernet0 = &emac;
> serial0 = &uart0;
> };
>
> @@ -117,6 +118,13 @@
> status = "okay";
> };
>
> +&emac {
> + phy-handle = <&int_mii_phy>;
> + phy-mode = "mii";
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> +
> &ir {
> pinctrl-names = "default";
> pinctrl-0 = <&ir_pins_a>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> index 72ca01b93f1b..cbc499b04de4 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> @@ -47,6 +47,10 @@
> model = "Xunlong Orange Pi Plus / Plus 2";
> compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
>
> + aliases {
> + ethernet0 = &emac;
> + };
> +
> reg_gmac_3v3: gmac-3v3 {
> compatible = "regulator-fixed";
> regulator-name = "gmac-3v3";
> @@ -74,6 +78,24 @@
> status = "okay";
> };
>
> +&emac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&emac_rgmii_pins>;
> + phy-supply = <®_gmac_3v3>;
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii";
> +
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> +
> +&external_mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + };
> +};
> +
> &mmc2 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc2_8bit_pins>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
> index 97920b12a944..6dbf7b2e0c13 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
> @@ -61,3 +61,19 @@
> gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
> };
> };
> +
> +&emac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&emac_rgmii_pins>;
> + phy-supply = <®_gmac_3v3>;
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii";
> + status = "okay";
> +};
> +
> +&external_mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> +};
>
--
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^ permalink raw reply
* Re: [PATCH v10 5/8] ARM: dts: sunxi: Restore EMAC changes (boards)
From: Philipp Rossak @ 2017-11-17 19:56 UTC (permalink / raw)
To: Corentin Labbe
Cc: Rob Herring, mark.rutland, maxime.ripard, wens, linux,
catalin.marinas, will.deacon, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <20171031081915.18960-6-clabbe.montjoie@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 10975 bytes --]
Hey,
Sorry for the bringing this up again.
Isn't there a: ethernet0 = &emac; for some boards missing?
Best,
Philipp
On Oct 31, 2017 09:24, "Corentin Labbe" <clabbe.montjoie@gmail.com
<mailto:clabbe.montjoie@gmail.com>> wrote:
The original dwmac-sun8i DT bindings have some issue on how to handle
integrated PHY and was reverted in last RC of 4.13.
But now we have a solution so we need to get back that was reverted.
This patch restore all boards DT about dwmac-sun8i
This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert
EMAC changes")
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com
<mailto:clabbe.montjoie@gmail.com>>
Acked-by: Florian Fainelli <f.fainelli@gmail.com
<mailto:f.fainelli@gmail.com>>
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 +++++++++
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19
+++++++++++++++++++
arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 19
+++++++++++++++++++
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 +++++++
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 ++++++++
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 ++++++++
arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +++++
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 ++++++++
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22
++++++++++++++++++++++
arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16
++++++++++++++++
10 files changed, 121 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index b1502df7b509..6713d0f2b3f4 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -56,6 +56,8 @@
aliases {
serial0 = &uart0;
+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet0 = &emac;
ethernet1 = &xr819;
};
@@ -102,6 +104,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index e1dba9ffa94b..f2292deaa590 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -52,6 +52,7 @@
compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@@ -111,6 +112,24 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index 73766d38ee6c..cfb96da3cfef 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -66,6 +66,25 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ allwinner,leds-active-low;
+
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 8d2cc6e9a03f..78f6c24952dd 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -46,3 +46,10 @@
model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 1bf51802f5aa..b20be95b49d5 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -54,6 +54,7 @@
aliases {
serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in
sun8i-h3.dtsi */
+ ethernet0 = &emac;
ethernet1 = &rtl8189;
};
@@ -117,6 +118,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index a1c6ff6fd05d..82e5d28cd698 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -52,6 +52,7 @@
compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -97,6 +98,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
index 8b93f5c781a7..a10281b455f5 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
@@ -53,6 +53,11 @@
};
};
+&emac {
+ /* LEDs changed to active high on the plus */
+ /delete-property/ allwinner,leds-active-low;
+};
+
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index d0b80fda2f6b..6d98bcfbe877 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -52,6 +52,7 @@
compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -117,6 +118,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index 72ca01b93f1b..cbc499b04de4 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -47,6 +47,10 @@
model = "Xunlong Orange Pi Plus / Plus 2";
compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
+ aliases {
+ ethernet0 = &emac;
+ };
+
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
regulator-name = "gmac-3v3";
@@ -74,6 +78,24 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_pins>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
index 97920b12a944..6dbf7b2e0c13 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
@@ -61,3 +61,19 @@
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
};
};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
--
2.13.6
[-- Attachment #2: Type: text/html, Size: 15792 bytes --]
^ permalink raw reply
* Re: [PATCH] ARM: dts: bcm2835-rpi: Avoid conflicts on i2c0
From: Phil Elwell @ 2017-11-17 19:51 UTC (permalink / raw)
To: Dave Stevenson, Eric Anholt
Cc: Mark Rutland, devicetree, Scott Branden, Rob Herring,
linux-rpi-kernel, linux-arm-kernel
In-Reply-To: <CAAoAYcPz6urucU1r_uNk1kvjsGg0p7VUrZwa5GZSDeDgsD=5Fw@mail.gmail.com>
On 17/11/2017 18:30, Dave Stevenson wrote:
> On 16 November 2017 at 20:34, Eric Anholt <eric@anholt.net> wrote:
>> Stefan Wahren <stefan.wahren@i2se.com> writes:
>>
>>> The GPU firmware of the Raspberry Pi 3 uses i2c0 to communicate to
>>> the FXL6408 gpio expander. It's a bad idea to use the same interface
>>> from the ARM side. Since this interface isn't used by the other
>>> RPi boards, it's save to remove the complete node and avoid this
>>> conflict.
>>
>> It's not used by other kernel drivers currently, but should we leave it
>> in for the pi0/1/2 folks that might have userspace I2C stuff using it?
>> That's a thing people do, right? I actually don't know.
>
> The firmware hasn't used BSC0 for the GPIO expander since the end of
> January. It now bit bashes it. Sorry if that information hadn't
> filtered through.
>
> I've got a patch I was about to send to rpi-linux for comment which
> sets up the i2c-mux-pinctrl driver on BSC0 so that it can be used
> either on GPIOs 0&1, or the GPIOs connected to the DSI and CSI
> connectors (I want it to talk to the camera module, and I guess Eric
> won't complain for talking to the DSI display). I'll aim to sort it on
> Monday.
Regardless of the use (or not) of i2c0 by the VPU on Pi 3, i2c0 is the I2C interface
intended for the ARM on early Pi Model Bs. The enabling or not of the I2C
interfaces should be left to the model-specific DTS files.
Regards,
Phil
^ permalink raw reply
* Re: [PATCH v10 5/8] ARM: dts: sunxi: Restore EMAC changes (boards)
From: Philipp Rossak @ 2017-11-17 19:45 UTC (permalink / raw)
To: Corentin Labbe
Cc: Rob Herring, mark.rutland, Maxime Ripard, Chen-Yu Tsai,
Russell King, catalin.marinas, will.deacon, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <20171031081915.18960-6-clabbe.montjoie@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 9538 bytes --]
Hey,
Sorry for the bringing this up again.
Isn't there a: ethernet0 = &emac; for some boards missing?
Best,
Philipp
On Oct 31, 2017 09:24, "Corentin Labbe" <clabbe.montjoie@gmail.com> wrote:
> The original dwmac-sun8i DT bindings have some issue on how to handle
> integrated PHY and was reverted in last RC of 4.13.
> But now we have a solution so we need to get back that was reverted.
>
> This patch restore all boards DT about dwmac-sun8i
> This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC
> changes")
>
> Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 +++++++++
> arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19
> +++++++++++++++++++
> arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 19
> +++++++++++++++++++
> arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 +++++++
> arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 ++++++++
> arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 ++++++++
> arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +++++
> arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 ++++++++
> arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22
> ++++++++++++++++++++++
> arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 ++++++++++++++++
> 10 files changed, 121 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> index b1502df7b509..6713d0f2b3f4 100644
> --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> @@ -56,6 +56,8 @@
>
> aliases {
> serial0 = &uart0;
> + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
> + ethernet0 = &emac;
> ethernet1 = &xr819;
> };
>
> @@ -102,6 +104,13 @@
> status = "okay";
> };
>
> +&emac {
> + phy-handle = <&int_mii_phy>;
> + phy-mode = "mii";
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> +
> &mmc0 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc0_pins_a>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
> b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
> index e1dba9ffa94b..f2292deaa590 100644
> --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
> @@ -52,6 +52,7 @@
> compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
>
> aliases {
> + ethernet0 = &emac;
> serial0 = &uart0;
> serial1 = &uart1;
> };
> @@ -111,6 +112,24 @@
> status = "okay";
> };
>
> +&emac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&emac_rgmii_pins>;
> + phy-supply = <®_gmac_3v3>;
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii";
> +
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> +
> +&external_mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + };
> +};
> +
> &ir {
> pinctrl-names = "default";
> pinctrl-0 = <&ir_pins_a>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> index 73766d38ee6c..cfb96da3cfef 100644
> --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> @@ -66,6 +66,25 @@
> status = "okay";
> };
>
> +&emac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&emac_rgmii_pins>;
> + phy-supply = <®_gmac_3v3>;
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii";
> +
> + allwinner,leds-active-low;
> +
> + status = "okay";
> +};
> +
> +&external_mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <7>;
> + };
> +};
> +
> &ir {
> pinctrl-names = "default";
> pinctrl-0 = <&ir_pins_a>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
> b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
> index 8d2cc6e9a03f..78f6c24952dd 100644
> --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
> @@ -46,3 +46,10 @@
> model = "FriendlyARM NanoPi NEO";
> compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
> };
> +
> +&emac {
> + phy-handle = <&int_mii_phy>;
> + phy-mode = "mii";
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
> b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
> index 1bf51802f5aa..b20be95b49d5 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
> @@ -54,6 +54,7 @@
> aliases {
> serial0 = &uart0;
> /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
> + ethernet0 = &emac;
> ethernet1 = &rtl8189;
> };
>
> @@ -117,6 +118,13 @@
> status = "okay";
> };
>
> +&emac {
> + phy-handle = <&int_mii_phy>;
> + phy-mode = "mii";
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> +
> &ir {
> pinctrl-names = "default";
> pinctrl-0 = <&ir_pins_a>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
> b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
> index a1c6ff6fd05d..82e5d28cd698 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
> @@ -52,6 +52,7 @@
> compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
>
> aliases {
> + ethernet0 = &emac;
> serial0 = &uart0;
> };
>
> @@ -97,6 +98,13 @@
> status = "okay";
> };
>
> +&emac {
> + phy-handle = <&int_mii_phy>;
> + phy-mode = "mii";
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> +
> &mmc0 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
> b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
> index 8b93f5c781a7..a10281b455f5 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
> @@ -53,6 +53,11 @@
> };
> };
>
> +&emac {
> + /* LEDs changed to active high on the plus */
> + /delete-property/ allwinner,leds-active-low;
> +};
> +
> &mmc1 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc1_pins_a>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
> b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
> index d0b80fda2f6b..6d98bcfbe877 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
> @@ -52,6 +52,7 @@
> compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
>
> aliases {
> + ethernet0 = &emac;
> serial0 = &uart0;
> };
>
> @@ -117,6 +118,13 @@
> status = "okay";
> };
>
> +&emac {
> + phy-handle = <&int_mii_phy>;
> + phy-mode = "mii";
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> +
> &ir {
> pinctrl-names = "default";
> pinctrl-0 = <&ir_pins_a>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> index 72ca01b93f1b..cbc499b04de4 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> @@ -47,6 +47,10 @@
> model = "Xunlong Orange Pi Plus / Plus 2";
> compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
>
> + aliases {
> + ethernet0 = &emac;
> + };
> +
> reg_gmac_3v3: gmac-3v3 {
> compatible = "regulator-fixed";
> regulator-name = "gmac-3v3";
> @@ -74,6 +78,24 @@
> status = "okay";
> };
>
> +&emac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&emac_rgmii_pins>;
> + phy-supply = <®_gmac_3v3>;
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii";
> +
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> +
> +&external_mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + };
> +};
> +
> &mmc2 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc2_8bit_pins>;
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
> b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
> index 97920b12a944..6dbf7b2e0c13 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
> @@ -61,3 +61,19 @@
> gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
> };
> };
> +
> +&emac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&emac_rgmii_pins>;
> + phy-supply = <®_gmac_3v3>;
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii";
> + status = "okay";
> +};
> +
> +&external_mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> +};
> --
> 2.13.6
>
>
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^ permalink raw reply
* [PATCH v4 4/4] drivers/fsi: sbefifo: Add in-kernel API
From: Eddie James @ 2017-11-17 19:34 UTC (permalink / raw)
To: linux-kernel
Cc: gregkh, devicetree, robh+dt, mark.rutland, bradleyb, cbostic,
joel, eajames, Edward A. James
In-Reply-To: <1510947274-7519-1-git-send-email-eajames@linux.vnet.ibm.com>
From: "Edward A. James" <eajames@us.ibm.com>
Refactor the user interface of the SBEFIFO driver to allow for an
in-kernel read/write API. Add exported functions for other drivers to
call, and add an include file with those functions. Also parse the
device tree for child nodes and create child platform devices
accordingly.
Signed-off-by: Edward A. James <eajames@us.ibm.com>
---
drivers/fsi/fsi-sbefifo.c | 137 +++++++++++++++++++++++++++++++++++++-------
include/linux/fsi-sbefifo.h | 30 ++++++++++
2 files changed, 146 insertions(+), 21 deletions(-)
create mode 100644 include/linux/fsi-sbefifo.h
diff --git a/drivers/fsi/fsi-sbefifo.c b/drivers/fsi/fsi-sbefifo.c
index 9970e2d..92947b0 100644
--- a/drivers/fsi/fsi-sbefifo.c
+++ b/drivers/fsi/fsi-sbefifo.c
@@ -15,12 +15,16 @@
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/fsi.h>
+#include <linux/fsi-sbefifo.h>
#include <linux/idr.h>
#include <linux/kernel.h>
#include <linux/kref.h>
#include <linux/list.h>
#include <linux/miscdevice.h>
#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
#include <linux/poll.h>
#include <linux/sched.h>
#include <linux/slab.h>
@@ -92,6 +96,7 @@ struct sbefifo_client {
struct list_head xfrs;
struct sbefifo *dev;
struct kref kref;
+ unsigned long f_flags;
};
static DEFINE_IDA(sbefifo_ida);
@@ -540,6 +545,7 @@ static int sbefifo_open(struct inode *inode, struct file *file)
return -ENOMEM;
file->private_data = client;
+ client->f_flags = file->f_flags;
return 0;
}
@@ -579,10 +585,9 @@ static bool sbefifo_read_ready(struct sbefifo *sbefifo,
(xfr && test_bit(SBEFIFO_XFR_COMPLETE, &xfr->flags));
}
-static ssize_t sbefifo_read(struct file *file, char __user *buf, size_t len,
- loff_t *offset)
+static ssize_t sbefifo_read_common(struct sbefifo_client *client,
+ char __user *ubuf, char *kbuf, size_t len)
{
- struct sbefifo_client *client = file->private_data;
struct sbefifo *sbefifo = client->dev;
struct sbefifo_xfr *xfr;
size_t n;
@@ -591,7 +596,7 @@ static ssize_t sbefifo_read(struct file *file, char __user *buf, size_t len,
if ((len >> 2) << 2 != len)
return -EINVAL;
- if ((file->f_flags & O_NONBLOCK) && !sbefifo_xfr_rsp_pending(client))
+ if ((client->f_flags & O_NONBLOCK) && !sbefifo_xfr_rsp_pending(client))
return -EAGAIN;
sbefifo_get_client(client);
@@ -609,9 +614,13 @@ static ssize_t sbefifo_read(struct file *file, char __user *buf, size_t len,
n = min_t(size_t, n, len);
- if (copy_to_user(buf, READ_ONCE(client->rbuf.rpos), n)) {
- ret = -EFAULT;
- goto out;
+ if (ubuf) {
+ if (copy_to_user(ubuf, READ_ONCE(client->rbuf.rpos), n)) {
+ ret = -EFAULT;
+ goto out;
+ }
+ } else {
+ memcpy(kbuf, READ_ONCE(client->rbuf.rpos), n);
}
if (sbefifo_buf_readnb(&client->rbuf, n)) {
@@ -643,6 +652,14 @@ static ssize_t sbefifo_read(struct file *file, char __user *buf, size_t len,
return ret;
}
+static ssize_t sbefifo_read(struct file *file, char __user *buf, size_t len,
+ loff_t *offset)
+{
+ struct sbefifo_client *client = file->private_data;
+
+ return sbefifo_read_common(client, buf, NULL, len);
+}
+
static bool sbefifo_write_ready(struct sbefifo *sbefifo,
struct sbefifo_xfr *xfr,
struct sbefifo_client *client, size_t *n)
@@ -655,10 +672,10 @@ static bool sbefifo_write_ready(struct sbefifo *sbefifo,
return READ_ONCE(sbefifo->rc) || (next == xfr && *n);
}
-static ssize_t sbefifo_write(struct file *file, const char __user *buf,
- size_t len, loff_t *offset)
+static ssize_t sbefifo_write_common(struct sbefifo_client *client,
+ const char __user *ubuf, const char *kbuf,
+ size_t len)
{
- struct sbefifo_client *client = file->private_data;
struct sbefifo *sbefifo = client->dev;
struct sbefifo_xfr *xfr;
ssize_t ret = 0;
@@ -676,7 +693,7 @@ static ssize_t sbefifo_write(struct file *file, const char __user *buf,
spin_lock_irq(&sbefifo->lock);
xfr = sbefifo_next_xfr(sbefifo); /* next xfr to be executed */
- if ((file->f_flags & O_NONBLOCK) && xfr && n < len) {
+ if ((client->f_flags & O_NONBLOCK) && xfr && n < len) {
spin_unlock_irq(&sbefifo->lock);
ret = -EAGAIN;
goto out;
@@ -717,16 +734,22 @@ static ssize_t sbefifo_write(struct file *file, const char __user *buf,
n = min_t(size_t, n, len);
- if (copy_from_user(READ_ONCE(client->wbuf.wpos), buf, n)) {
- set_bit(SBEFIFO_XFR_CANCEL, &xfr->flags);
- sbefifo_get(sbefifo);
- if (mod_timer(&sbefifo->poll_timer, jiffies))
- sbefifo_put(sbefifo);
- ret = -EFAULT;
- goto out;
- }
+ if (ubuf) {
+ if (copy_from_user(READ_ONCE(client->wbuf.wpos), ubuf,
+ n)) {
+ set_bit(SBEFIFO_XFR_CANCEL, &xfr->flags);
+ sbefifo_get(sbefifo);
+ if (mod_timer(&sbefifo->poll_timer, jiffies))
+ sbefifo_put(sbefifo);
+ ret = -EFAULT;
+ goto out;
+ }
- buf += n;
+ ubuf += n;
+ } else {
+ memcpy(READ_ONCE(client->wbuf.wpos), kbuf, n);
+ kbuf += n;
+ }
sbefifo_buf_wrotenb(&client->wbuf, n);
len -= n;
@@ -750,6 +773,14 @@ static ssize_t sbefifo_write(struct file *file, const char __user *buf,
return ret;
}
+static ssize_t sbefifo_write(struct file *file, const char __user *buf,
+ size_t len, loff_t *offset)
+{
+ struct sbefifo_client *client = file->private_data;
+
+ return sbefifo_write_common(client, buf, NULL, len);
+}
+
static int sbefifo_release(struct inode *inode, struct file *file)
{
struct sbefifo_client *client = file->private_data;
@@ -769,6 +800,56 @@ static int sbefifo_release(struct inode *inode, struct file *file)
.release = sbefifo_release,
};
+struct sbefifo_client *sbefifo_drv_open(struct device *dev,
+ unsigned long flags)
+{
+ struct sbefifo_client *client;
+ struct sbefifo *sbefifo = dev_get_drvdata(dev);
+
+ if (!sbefifo)
+ return NULL;
+
+ client = sbefifo_new_client(sbefifo);
+ if (client)
+ client->f_flags = flags;
+
+ return client;
+}
+EXPORT_SYMBOL_GPL(sbefifo_drv_open);
+
+int sbefifo_drv_read(struct sbefifo_client *client, char *buf, size_t len)
+{
+ return sbefifo_read_common(client, NULL, buf, len);
+}
+EXPORT_SYMBOL_GPL(sbefifo_drv_read);
+
+int sbefifo_drv_write(struct sbefifo_client *client, const char *buf,
+ size_t len)
+{
+ return sbefifo_write_common(client, NULL, buf, len);
+}
+EXPORT_SYMBOL_GPL(sbefifo_drv_write);
+
+void sbefifo_drv_release(struct sbefifo_client *client)
+{
+ if (!client)
+ return;
+
+ sbefifo_put_client(client);
+}
+EXPORT_SYMBOL_GPL(sbefifo_drv_release);
+
+static int sbefifo_unregister_child(struct device *dev, void *data)
+{
+ struct platform_device *child = to_platform_device(dev);
+
+ of_device_unregister(child);
+ if (dev->of_node)
+ of_node_clear_flag(dev->of_node, OF_POPULATED);
+
+ return 0;
+}
+
static int sbefifo_request_reset(struct sbefifo *sbefifo)
{
int ret;
@@ -803,8 +884,11 @@ static int sbefifo_probe(struct device *dev)
{
struct fsi_device *fsi_dev = to_fsi_dev(dev);
struct sbefifo *sbefifo;
+ struct device_node *np;
+ struct platform_device *child;
+ char child_name[32];
u32 up, down;
- int ret;
+ int ret, child_idx = 0;
dev_dbg(dev, "Found sbefifo device\n");
sbefifo = kzalloc(sizeof(*sbefifo), GFP_KERNEL);
@@ -855,6 +939,16 @@ static int sbefifo_probe(struct device *dev)
return ret;
}
+ /* create platform devs for dts child nodes (occ, etc) */
+ for_each_available_child_of_node(dev->of_node, np) {
+ snprintf(child_name, sizeof(child_name), "%s-dev%d",
+ sbefifo->name, child_idx++);
+ child = of_platform_device_create(np, child_name, dev);
+ if (!child)
+ dev_warn(dev, "failed to create child %s dev\n",
+ child_name);
+ }
+
dev_set_drvdata(dev, sbefifo);
return 0;
@@ -880,6 +974,7 @@ static int sbefifo_remove(struct device *dev)
wake_up_all(&sbefifo->wait);
misc_deregister(&sbefifo->mdev);
+ device_for_each_child(dev, NULL, sbefifo_unregister_child);
ida_simple_remove(&sbefifo_ida, sbefifo->idx);
diff --git a/include/linux/fsi-sbefifo.h b/include/linux/fsi-sbefifo.h
new file mode 100644
index 0000000..8e55891
--- /dev/null
+++ b/include/linux/fsi-sbefifo.h
@@ -0,0 +1,30 @@
+/*
+ * SBEFIFO FSI Client device driver
+ *
+ * Copyright (C) IBM Corporation 2017
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERGCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef LINUX_FSI_SBEFIFO_H
+#define LINUX_FSI_SBEFIFO_H
+
+struct device;
+struct sbefifo_client;
+
+extern struct sbefifo_client *sbefifo_drv_open(struct device *dev,
+ unsigned long flags);
+extern int sbefifo_drv_read(struct sbefifo_client *client, char *buf,
+ size_t len);
+extern int sbefifo_drv_write(struct sbefifo_client *client, const char *buf,
+ size_t len);
+extern void sbefifo_drv_release(struct sbefifo_client *client);
+
+#endif /* LINUX_FSI_SBEFIFO_H */
--
1.8.3.1
^ permalink raw reply related
* [PATCH v4 3/4] drivers/fsi: sbefifo: Add miscdevice
From: Eddie James @ 2017-11-17 19:34 UTC (permalink / raw)
To: linux-kernel
Cc: gregkh, devicetree, robh+dt, mark.rutland, bradleyb, cbostic,
joel, eajames, Edward A. James
In-Reply-To: <1510947274-7519-1-git-send-email-eajames@linux.vnet.ibm.com>
From: "Edward A. James" <eajames@us.ibm.com>
Add a miscdevice for the sbefifo to allow userspace access through
standard file operations.
Signed-off-by: Edward A. James <eajames@us.ibm.com>
---
drivers/fsi/fsi-sbefifo.c | 354 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 354 insertions(+)
diff --git a/drivers/fsi/fsi-sbefifo.c b/drivers/fsi/fsi-sbefifo.c
index 2439958..9970e2d 100644
--- a/drivers/fsi/fsi-sbefifo.c
+++ b/drivers/fsi/fsi-sbefifo.c
@@ -19,6 +19,7 @@
#include <linux/kernel.h>
#include <linux/kref.h>
#include <linux/list.h>
+#include <linux/miscdevice.h>
#include <linux/module.h>
#include <linux/poll.h>
#include <linux/sched.h>
@@ -54,6 +55,7 @@
struct sbefifo {
struct timer_list poll_timer;
struct fsi_device *fsi_dev;
+ struct miscdevice mdev;
wait_queue_head_t wait;
struct list_head xfrs;
struct kref kref;
@@ -256,6 +258,99 @@ static void sbefifo_put(struct sbefifo *sbefifo)
kref_put(&sbefifo->kref, sbefifo_free);
}
+static struct sbefifo_xfr *sbefifo_enq_xfr(struct sbefifo_client *client)
+{
+ struct sbefifo *sbefifo = client->dev;
+ struct sbefifo_xfr *xfr;
+
+ if (READ_ONCE(sbefifo->rc))
+ return ERR_PTR(sbefifo->rc);
+
+ xfr = kzalloc(sizeof(*xfr), GFP_KERNEL);
+ if (!xfr)
+ return ERR_PTR(-ENOMEM);
+
+ xfr->rbuf = &client->rbuf;
+ xfr->wbuf = &client->wbuf;
+ list_add_tail(&xfr->xfrs, &sbefifo->xfrs);
+ list_add_tail(&xfr->client, &client->xfrs);
+
+ return xfr;
+}
+
+static bool sbefifo_xfr_rsp_pending(struct sbefifo_client *client)
+{
+ struct sbefifo_xfr *xfr = list_first_entry_or_null(&client->xfrs,
+ struct sbefifo_xfr,
+ client);
+
+ if (xfr && test_bit(SBEFIFO_XFR_RESP_PENDING, &xfr->flags))
+ return true;
+
+ return false;
+}
+
+static struct sbefifo_client *sbefifo_new_client(struct sbefifo *sbefifo)
+{
+ struct sbefifo_client *client;
+
+ client = kzalloc(sizeof(*client), GFP_KERNEL);
+ if (!client)
+ return NULL;
+
+ kref_init(&client->kref);
+ client->dev = sbefifo;
+ sbefifo_buf_init(&client->rbuf);
+ sbefifo_buf_init(&client->wbuf);
+ INIT_LIST_HEAD(&client->xfrs);
+
+ sbefifo_get(sbefifo);
+
+ return client;
+}
+
+static void sbefifo_client_release(struct kref *kref)
+{
+ struct sbefifo *sbefifo;
+ struct sbefifo_client *client;
+ struct sbefifo_xfr *xfr, *tmp;
+
+ client = container_of(kref, struct sbefifo_client, kref);
+ sbefifo = client->dev;
+
+ if (!READ_ONCE(sbefifo->rc)) {
+ list_for_each_entry_safe(xfr, tmp, &client->xfrs, client) {
+ if (test_bit(SBEFIFO_XFR_COMPLETE, &xfr->flags)) {
+ list_del(&xfr->client);
+ kfree(xfr);
+ continue;
+ }
+
+ /*
+ * The client left with pending or running xfrs.
+ * Cancel them.
+ */
+ set_bit(SBEFIFO_XFR_CANCEL, &xfr->flags);
+ sbefifo_get(sbefifo);
+ if (mod_timer(&client->dev->poll_timer, jiffies))
+ sbefifo_put(sbefifo);
+ }
+ }
+
+ sbefifo_put(sbefifo);
+ kfree(client);
+}
+
+static void sbefifo_get_client(struct sbefifo_client *client)
+{
+ kref_get(&client->kref);
+}
+
+static void sbefifo_put_client(struct sbefifo_client *client)
+{
+ kref_put(&client->kref, sbefifo_client_release);
+}
+
static struct sbefifo_xfr *sbefifo_next_xfr(struct sbefifo *sbefifo)
{
struct sbefifo_xfr *xfr, *tmp;
@@ -429,6 +524,251 @@ static void sbefifo_poll_timer(unsigned long data)
spin_unlock(&sbefifo->lock);
}
+static int sbefifo_open(struct inode *inode, struct file *file)
+{
+ struct sbefifo *sbefifo = container_of(file->private_data,
+ struct sbefifo, mdev);
+ struct sbefifo_client *client;
+ int ret;
+
+ ret = READ_ONCE(sbefifo->rc);
+ if (ret)
+ return ret;
+
+ client = sbefifo_new_client(sbefifo);
+ if (!client)
+ return -ENOMEM;
+
+ file->private_data = client;
+
+ return 0;
+}
+
+static unsigned int sbefifo_poll(struct file *file, poll_table *wait)
+{
+ struct sbefifo_client *client = file->private_data;
+ struct sbefifo *sbefifo = client->dev;
+ unsigned int mask = 0;
+
+ poll_wait(file, &sbefifo->wait, wait);
+
+ if (READ_ONCE(sbefifo->rc))
+ mask |= POLLERR;
+
+ if (sbefifo_buf_nbreadable(&client->rbuf))
+ mask |= POLLIN;
+
+ if (sbefifo_buf_nbwriteable(&client->wbuf))
+ mask |= POLLOUT;
+
+ return mask;
+}
+
+static bool sbefifo_read_ready(struct sbefifo *sbefifo,
+ struct sbefifo_client *client, size_t *n,
+ size_t *ret)
+{
+ struct sbefifo_xfr *xfr = list_first_entry_or_null(&client->xfrs,
+ struct sbefifo_xfr,
+ client);
+
+ *n = sbefifo_buf_nbreadable(&client->rbuf);
+ *ret = READ_ONCE(sbefifo->rc);
+
+ return *ret || *n ||
+ (xfr && test_bit(SBEFIFO_XFR_COMPLETE, &xfr->flags));
+}
+
+static ssize_t sbefifo_read(struct file *file, char __user *buf, size_t len,
+ loff_t *offset)
+{
+ struct sbefifo_client *client = file->private_data;
+ struct sbefifo *sbefifo = client->dev;
+ struct sbefifo_xfr *xfr;
+ size_t n;
+ ssize_t ret = 0;
+
+ if ((len >> 2) << 2 != len)
+ return -EINVAL;
+
+ if ((file->f_flags & O_NONBLOCK) && !sbefifo_xfr_rsp_pending(client))
+ return -EAGAIN;
+
+ sbefifo_get_client(client);
+ if (wait_event_interruptible(sbefifo->wait,
+ sbefifo_read_ready(sbefifo, client, &n,
+ &ret))) {
+ ret = -ERESTARTSYS;
+ goto out;
+ }
+
+ if (ret) {
+ INIT_LIST_HEAD(&client->xfrs);
+ goto out;
+ }
+
+ n = min_t(size_t, n, len);
+
+ if (copy_to_user(buf, READ_ONCE(client->rbuf.rpos), n)) {
+ ret = -EFAULT;
+ goto out;
+ }
+
+ if (sbefifo_buf_readnb(&client->rbuf, n)) {
+ xfr = list_first_entry_or_null(&client->xfrs,
+ struct sbefifo_xfr, client);
+ if (!xfr) {
+ /* should be impossible to not have an xfr here */
+ WARN_ONCE(1, "no xfr in queue");
+ ret = -EPROTO;
+ goto out;
+ }
+
+ if (!test_bit(SBEFIFO_XFR_COMPLETE, &xfr->flags)) {
+ /* Fill the read buffer back up. */
+ sbefifo_get(sbefifo);
+ if (mod_timer(&client->dev->poll_timer, jiffies))
+ sbefifo_put(sbefifo);
+ } else {
+ list_del(&xfr->client);
+ kfree(xfr);
+ wake_up_interruptible(&sbefifo->wait);
+ }
+ }
+
+ ret = n;
+
+out:
+ sbefifo_put_client(client);
+ return ret;
+}
+
+static bool sbefifo_write_ready(struct sbefifo *sbefifo,
+ struct sbefifo_xfr *xfr,
+ struct sbefifo_client *client, size_t *n)
+{
+ struct sbefifo_xfr *next = list_first_entry_or_null(&client->xfrs,
+ struct sbefifo_xfr,
+ client);
+
+ *n = sbefifo_buf_nbwriteable(&client->wbuf);
+ return READ_ONCE(sbefifo->rc) || (next == xfr && *n);
+}
+
+static ssize_t sbefifo_write(struct file *file, const char __user *buf,
+ size_t len, loff_t *offset)
+{
+ struct sbefifo_client *client = file->private_data;
+ struct sbefifo *sbefifo = client->dev;
+ struct sbefifo_xfr *xfr;
+ ssize_t ret = 0;
+ size_t n;
+
+ if ((len >> 2) << 2 != len)
+ return -EINVAL;
+
+ if (!len)
+ return 0;
+
+ sbefifo_get_client(client);
+ n = sbefifo_buf_nbwriteable(&client->wbuf);
+
+ spin_lock_irq(&sbefifo->lock);
+ xfr = sbefifo_next_xfr(sbefifo); /* next xfr to be executed */
+
+ if ((file->f_flags & O_NONBLOCK) && xfr && n < len) {
+ spin_unlock_irq(&sbefifo->lock);
+ ret = -EAGAIN;
+ goto out;
+ }
+
+ xfr = sbefifo_enq_xfr(client); /* this xfr queued up */
+ if (IS_ERR(xfr)) {
+ spin_unlock_irq(&sbefifo->lock);
+ ret = PTR_ERR(xfr);
+ goto out;
+ }
+
+ spin_unlock_irq(&sbefifo->lock);
+
+ /*
+ * Partial writes are not really allowed in that EOT is sent exactly
+ * once per write.
+ */
+ while (len) {
+ if (wait_event_interruptible(sbefifo->wait,
+ sbefifo_write_ready(sbefifo, xfr,
+ client,
+ &n))) {
+ set_bit(SBEFIFO_XFR_CANCEL, &xfr->flags);
+ sbefifo_get(sbefifo);
+ if (mod_timer(&sbefifo->poll_timer, jiffies))
+ sbefifo_put(sbefifo);
+
+ ret = -ERESTARTSYS;
+ goto out;
+ }
+
+ if (sbefifo->rc) {
+ INIT_LIST_HEAD(&client->xfrs);
+ ret = sbefifo->rc;
+ goto out;
+ }
+
+ n = min_t(size_t, n, len);
+
+ if (copy_from_user(READ_ONCE(client->wbuf.wpos), buf, n)) {
+ set_bit(SBEFIFO_XFR_CANCEL, &xfr->flags);
+ sbefifo_get(sbefifo);
+ if (mod_timer(&sbefifo->poll_timer, jiffies))
+ sbefifo_put(sbefifo);
+ ret = -EFAULT;
+ goto out;
+ }
+
+ buf += n;
+
+ sbefifo_buf_wrotenb(&client->wbuf, n);
+ len -= n;
+ ret += n;
+
+ /*
+ * Set this before starting timer to avoid race condition on
+ * this flag with the timer function writer.
+ */
+ if (!len)
+ set_bit(SBEFIFO_XFR_WRITE_DONE, &xfr->flags);
+
+ /* Drain the write buffer. */
+ sbefifo_get(sbefifo);
+ if (mod_timer(&client->dev->poll_timer, jiffies))
+ sbefifo_put(sbefifo);
+ }
+
+out:
+ sbefifo_put_client(client);
+ return ret;
+}
+
+static int sbefifo_release(struct inode *inode, struct file *file)
+{
+ struct sbefifo_client *client = file->private_data;
+ struct sbefifo *sbefifo = client->dev;
+
+ sbefifo_put_client(client);
+
+ return READ_ONCE(sbefifo->rc);
+}
+
+static const struct file_operations sbefifo_fops = {
+ .owner = THIS_MODULE,
+ .open = sbefifo_open,
+ .read = sbefifo_read,
+ .write = sbefifo_write,
+ .poll = sbefifo_poll,
+ .release = sbefifo_release,
+};
+
static int sbefifo_request_reset(struct sbefifo *sbefifo)
{
int ret;
@@ -503,6 +843,18 @@ static int sbefifo_probe(struct device *dev)
setup_timer(&sbefifo->poll_timer, sbefifo_poll_timer,
(unsigned long)sbefifo);
+ sbefifo->mdev.minor = MISC_DYNAMIC_MINOR;
+ sbefifo->mdev.fops = &sbefifo_fops;
+ sbefifo->mdev.name = sbefifo->name;
+ sbefifo->mdev.parent = dev;
+ ret = misc_register(&sbefifo->mdev);
+ if (ret) {
+ dev_err(dev, "failed to register miscdevice: %d\n", ret);
+ ida_simple_remove(&sbefifo_ida, sbefifo->idx);
+ sbefifo_put(sbefifo);
+ return ret;
+ }
+
dev_set_drvdata(dev, sbefifo);
return 0;
@@ -527,6 +879,8 @@ static int sbefifo_remove(struct device *dev)
wake_up_all(&sbefifo->wait);
+ misc_deregister(&sbefifo->mdev);
+
ida_simple_remove(&sbefifo_ida, sbefifo->idx);
if (del_timer_sync(&sbefifo->poll_timer))
--
1.8.3.1
^ permalink raw reply related
* [PATCH v4 2/4] drivers/fsi: Add SBEFIFO FSI client device driver
From: Eddie James @ 2017-11-17 19:34 UTC (permalink / raw)
To: linux-kernel
Cc: gregkh, devicetree, robh+dt, mark.rutland, bradleyb, cbostic,
joel, eajames, Edward A. James
In-Reply-To: <1510947274-7519-1-git-send-email-eajames@linux.vnet.ibm.com>
From: "Edward A. James" <eajames@us.ibm.com>
IBM POWER9 processors contain some embedded hardware and software bits
collectively referred to as the self boot engine (SBE). One role of
the SBE is to act as a proxy that provides access to the registers of
the POWER chip from other (embedded) systems.
The POWER9 chip contains a hardware frontend for communicating with
the SBE from remote systems called the SBEFIFO. The SBEFIFO logic
is contained within an FSI CFAM and as such the driver implements an
FSI bus device.
The SBE expects to communicate using a defined wire protocol; however,
the driver knows nothing of the protocol and only provides raw access
to the fifo device to userspace applications wishing to communicate with
the SBE using the wire protocol.
The SBEFIFO consists of two hardware fifos. The upstream fifo is used
by the driver to transfer data to the SBE on the POWER chip, from the
system hosting the driver. The downstream fifo is used by the driver to
transfer data from the SBE on the power chip to the system hosting the
driver.
Contributions from Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Edward A. James <eajames@us.ibm.com>
---
drivers/fsi/Kconfig | 7 +
drivers/fsi/Makefile | 1 +
drivers/fsi/fsi-sbefifo.c | 575 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 583 insertions(+)
create mode 100644 drivers/fsi/fsi-sbefifo.c
diff --git a/drivers/fsi/Kconfig b/drivers/fsi/Kconfig
index 6821ed0..8c4d903 100644
--- a/drivers/fsi/Kconfig
+++ b/drivers/fsi/Kconfig
@@ -33,6 +33,13 @@ config FSI_SCOM
---help---
This option enables an FSI based SCOM device driver.
+config FSI_SBEFIFO
+ tristate "SBEFIFO FSI client device driver"
+ ---help---
+ This option enables an FSI based SBEFIFO device driver. The SBEFIFO is
+ a pipe-like FSI device for communicating with the self boot engine
+ (SBE) on POWER processors.
+
endif
endmenu
diff --git a/drivers/fsi/Makefile b/drivers/fsi/Makefile
index 65eb99d..851182e 100644
--- a/drivers/fsi/Makefile
+++ b/drivers/fsi/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_FSI) += fsi-core.o
obj-$(CONFIG_FSI_MASTER_HUB) += fsi-master-hub.o
obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o
obj-$(CONFIG_FSI_SCOM) += fsi-scom.o
+obj-$(CONFIG_FSI_SBEFIFO) += fsi-sbefifo.o
diff --git a/drivers/fsi/fsi-sbefifo.c b/drivers/fsi/fsi-sbefifo.c
new file mode 100644
index 0000000..2439958
--- /dev/null
+++ b/drivers/fsi/fsi-sbefifo.c
@@ -0,0 +1,575 @@
+/*
+ * Copyright (C) IBM Corporation 2017
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERGCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/fsi.h>
+#include <linux/idr.h>
+#include <linux/kernel.h>
+#include <linux/kref.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/poll.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/timer.h>
+#include <linux/uaccess.h>
+#include <linux/wait.h>
+
+/*
+ * The SBEFIFO is a pipe-like FSI device for communicating with
+ * the self boot engine on POWER processors.
+ */
+
+#define DEVICE_NAME "sbefifo"
+#define FSI_ENGID_SBE 0x22
+#define SBEFIFO_BUF_CNT 32
+
+#define SBEFIFO_UP 0x00 /* Up register offset */
+#define SBEFIFO_DWN 0x40 /* Down register offset */
+
+#define SBEFIFO_STS 0x04
+#define SBEFIFO_EMPTY BIT(20)
+#define SBEFIFO_STS_RESET_REQ BIT(25)
+#define SBEFIFO_EOT_RAISE 0x08
+#define SBEFIFO_EOT_MAGIC 0xffffffff
+#define SBEFIFO_REQ_RESET 0x0C
+#define SBEFIFO_EOT_ACK 0x14
+
+#define SBEFIFO_RESCHEDULE msecs_to_jiffies(500)
+#define SBEFIFO_MAX_RESCHDULE msecs_to_jiffies(5000)
+
+struct sbefifo {
+ struct timer_list poll_timer;
+ struct fsi_device *fsi_dev;
+ wait_queue_head_t wait;
+ struct list_head xfrs;
+ struct kref kref;
+ spinlock_t lock;
+ char name[32];
+ int idx;
+ int rc;
+};
+
+struct sbefifo_buf {
+ u32 buf[SBEFIFO_BUF_CNT];
+ unsigned long flags;
+#define SBEFIFO_BUF_FULL 1
+ u32 *rpos;
+ u32 *wpos;
+};
+
+struct sbefifo_xfr {
+ unsigned long wait_data_timeout;
+ struct sbefifo_buf *rbuf;
+ struct sbefifo_buf *wbuf;
+ struct list_head client;
+ struct list_head xfrs;
+ unsigned long flags;
+#define SBEFIFO_XFR_WRITE_DONE 1
+#define SBEFIFO_XFR_RESP_PENDING 2
+#define SBEFIFO_XFR_COMPLETE 3
+#define SBEFIFO_XFR_CANCEL 4
+};
+
+struct sbefifo_client {
+ struct sbefifo_buf rbuf;
+ struct sbefifo_buf wbuf;
+ struct list_head xfrs;
+ struct sbefifo *dev;
+ struct kref kref;
+};
+
+static DEFINE_IDA(sbefifo_ida);
+
+static int sbefifo_inw(struct sbefifo *sbefifo, int reg, u32 *word)
+{
+ int rc;
+ __be32 raw_word;
+
+ rc = fsi_device_read(sbefifo->fsi_dev, reg, &raw_word,
+ sizeof(raw_word));
+ if (rc)
+ return rc;
+
+ *word = be32_to_cpu(raw_word);
+
+ return 0;
+}
+
+static int sbefifo_outw(struct sbefifo *sbefifo, int reg, u32 word)
+{
+ __be32 raw_word = cpu_to_be32(word);
+
+ return fsi_device_write(sbefifo->fsi_dev, reg, &raw_word,
+ sizeof(raw_word));
+}
+
+/* Don't flip endianness of data to/from FIFO, just pass through. */
+static int sbefifo_readw(struct sbefifo *sbefifo, u32 *word)
+{
+ return fsi_device_read(sbefifo->fsi_dev, SBEFIFO_DWN, word,
+ sizeof(*word));
+}
+
+static int sbefifo_writew(struct sbefifo *sbefifo, u32 word)
+{
+ return fsi_device_write(sbefifo->fsi_dev, SBEFIFO_UP, &word,
+ sizeof(word));
+}
+
+static int sbefifo_ack_eot(struct sbefifo *sbefifo)
+{
+ u32 discard;
+ int ret;
+
+ /* Discard the EOT word. */
+ ret = sbefifo_readw(sbefifo, &discard);
+ if (ret)
+ return ret;
+
+ return sbefifo_outw(sbefifo, SBEFIFO_DWN | SBEFIFO_EOT_ACK,
+ SBEFIFO_EOT_MAGIC);
+}
+
+static size_t sbefifo_dev_nwreadable(u32 sts)
+{
+ static const u32 FIFO_NTRY_CNT_MSK = 0x000f0000;
+ static const unsigned int FIFO_NTRY_CNT_SHIFT = 16;
+
+ return (sts & FIFO_NTRY_CNT_MSK) >> FIFO_NTRY_CNT_SHIFT;
+}
+
+static size_t sbefifo_dev_nwwriteable(u32 sts)
+{
+ static const size_t FIFO_DEPTH = 8;
+
+ return FIFO_DEPTH - sbefifo_dev_nwreadable(sts);
+}
+
+static void sbefifo_buf_init(struct sbefifo_buf *buf)
+{
+ WRITE_ONCE(buf->flags, 0);
+ WRITE_ONCE(buf->rpos, buf->buf);
+ WRITE_ONCE(buf->wpos, buf->buf);
+}
+
+static size_t sbefifo_buf_nbreadable(struct sbefifo_buf *buf)
+{
+ size_t n;
+ u32 *rpos = READ_ONCE(buf->rpos);
+ u32 *wpos = READ_ONCE(buf->wpos);
+
+ if (test_bit(SBEFIFO_BUF_FULL, &buf->flags))
+ n = SBEFIFO_BUF_CNT;
+ else if (rpos <= wpos)
+ n = wpos - rpos;
+ else
+ n = (buf->buf + SBEFIFO_BUF_CNT) - rpos;
+
+ return n << 2;
+}
+
+static size_t sbefifo_buf_nbwriteable(struct sbefifo_buf *buf)
+{
+ size_t n;
+ u32 *rpos = READ_ONCE(buf->rpos);
+ u32 *wpos = READ_ONCE(buf->wpos);
+
+ if (test_bit(SBEFIFO_BUF_FULL, &buf->flags))
+ n = 0;
+ else if (wpos < rpos)
+ n = rpos - wpos;
+ else
+ n = (buf->buf + SBEFIFO_BUF_CNT) - wpos;
+
+ return n << 2;
+}
+
+/*
+ * Update pointers and flags after doing a buffer read. Return true if the
+ * buffer is now empty;
+ */
+static bool sbefifo_buf_readnb(struct sbefifo_buf *buf, size_t n)
+{
+ u32 *rpos = READ_ONCE(buf->rpos);
+ u32 *wpos = READ_ONCE(buf->wpos);
+
+ if (n)
+ clear_bit(SBEFIFO_BUF_FULL, &buf->flags);
+
+ rpos += (n >> 2);
+ if (rpos == buf->buf + SBEFIFO_BUF_CNT)
+ rpos = buf->buf;
+
+ WRITE_ONCE(buf->rpos, rpos);
+
+ return rpos == wpos;
+}
+
+/*
+ * Update pointers and flags after doing a buffer write. Return true if the
+ * buffer is now full.
+ */
+static bool sbefifo_buf_wrotenb(struct sbefifo_buf *buf, size_t n)
+{
+ u32 *rpos = READ_ONCE(buf->rpos);
+ u32 *wpos = READ_ONCE(buf->wpos);
+
+ wpos += (n >> 2);
+ if (wpos == buf->buf + SBEFIFO_BUF_CNT)
+ wpos = buf->buf;
+ if (wpos == rpos)
+ set_bit(SBEFIFO_BUF_FULL, &buf->flags);
+
+ WRITE_ONCE(buf->wpos, wpos);
+
+ return rpos == wpos;
+}
+
+static void sbefifo_free(struct kref *kref)
+{
+ struct sbefifo *sbefifo = container_of(kref, struct sbefifo, kref);
+
+ kfree(sbefifo);
+}
+
+static void sbefifo_get(struct sbefifo *sbefifo)
+{
+ kref_get(&sbefifo->kref);
+}
+
+static void sbefifo_put(struct sbefifo *sbefifo)
+{
+ kref_put(&sbefifo->kref, sbefifo_free);
+}
+
+static struct sbefifo_xfr *sbefifo_next_xfr(struct sbefifo *sbefifo)
+{
+ struct sbefifo_xfr *xfr, *tmp;
+
+ list_for_each_entry_safe(xfr, tmp, &sbefifo->xfrs, xfrs) {
+ if (unlikely(test_bit(SBEFIFO_XFR_CANCEL, &xfr->flags))) {
+ /* Discard cancelled transfers. */
+ list_del(&xfr->xfrs);
+ kfree(xfr);
+ continue;
+ }
+
+ return xfr;
+ }
+
+ return NULL;
+}
+
+static void sbefifo_poll_timer(unsigned long data)
+{
+ static const unsigned long EOT_MASK = 0x000000ff;
+ struct sbefifo *sbefifo = (void *)data;
+ struct sbefifo_buf *rbuf, *wbuf;
+ struct sbefifo_xfr *xfr, *tmp;
+ struct sbefifo_buf drain;
+ size_t devn, bufn;
+ int eot = 0;
+ int ret = 0;
+ u32 sts;
+ int i;
+
+ spin_lock(&sbefifo->lock);
+ xfr = list_first_entry_or_null(&sbefifo->xfrs, struct sbefifo_xfr,
+ xfrs);
+ if (!xfr)
+ goto out_unlock;
+
+ rbuf = xfr->rbuf;
+ wbuf = xfr->wbuf;
+
+ if (unlikely(test_bit(SBEFIFO_XFR_CANCEL, &xfr->flags))) {
+ /* The client left. */
+ rbuf = &drain;
+ wbuf = &drain;
+ sbefifo_buf_init(&drain);
+ if (!test_bit(SBEFIFO_XFR_RESP_PENDING, &xfr->flags))
+ set_bit(SBEFIFO_XFR_WRITE_DONE, &xfr->flags);
+ }
+
+ /* Drain the write buffer. */
+ while ((bufn = sbefifo_buf_nbreadable(wbuf))) {
+ ret = sbefifo_inw(sbefifo, SBEFIFO_UP | SBEFIFO_STS, &sts);
+ if (ret)
+ goto out;
+
+ devn = sbefifo_dev_nwwriteable(sts);
+ if (devn == 0) {
+ /* No open slot for write. Reschedule. */
+ sbefifo->poll_timer.expires = jiffies +
+ SBEFIFO_RESCHEDULE;
+ add_timer(&sbefifo->poll_timer);
+ goto out_unlock;
+ }
+
+ devn = min_t(size_t, devn, bufn >> 2);
+ for (i = 0; i < devn; i++) {
+ ret = sbefifo_writew(sbefifo, *wbuf->rpos);
+ if (ret)
+ goto out;
+
+ sbefifo_buf_readnb(wbuf, 1 << 2);
+ }
+ }
+
+ /* Send EOT if the writer is finished. */
+ if (test_and_clear_bit(SBEFIFO_XFR_WRITE_DONE, &xfr->flags)) {
+ ret = sbefifo_outw(sbefifo, SBEFIFO_UP | SBEFIFO_EOT_RAISE,
+ SBEFIFO_EOT_MAGIC);
+ if (ret)
+ goto out;
+
+ /* Inform reschedules that the writer is finished. */
+ set_bit(SBEFIFO_XFR_RESP_PENDING, &xfr->flags);
+ }
+
+ /* Nothing left to do if the writer is not finished. */
+ if (!test_bit(SBEFIFO_XFR_RESP_PENDING, &xfr->flags))
+ goto out;
+
+ /* Fill the read buffer. */
+ while ((bufn = sbefifo_buf_nbwriteable(rbuf))) {
+ ret = sbefifo_inw(sbefifo, SBEFIFO_DWN | SBEFIFO_STS, &sts);
+ if (ret)
+ goto out;
+
+ devn = sbefifo_dev_nwreadable(sts);
+ if (devn == 0) {
+ /*
+ * Limit the maximum waiting period for data in the
+ * FIFO. If the SBE isn't running, we will wait
+ * forever.
+ */
+ if (!xfr->wait_data_timeout) {
+ xfr->wait_data_timeout =
+ jiffies + SBEFIFO_MAX_RESCHDULE;
+ } else if (time_after(jiffies,
+ xfr->wait_data_timeout)) {
+ ret = -ETIME;
+ goto out;
+ }
+
+ /* No data yet. Reschedule. */
+ sbefifo->poll_timer.expires = jiffies +
+ SBEFIFO_RESCHEDULE;
+ add_timer(&sbefifo->poll_timer);
+ goto out_unlock;
+ } else {
+ xfr->wait_data_timeout = 0;
+ }
+
+ /* Fill. The EOT word is discarded. */
+ devn = min_t(size_t, devn, bufn >> 2);
+ eot = (sts & EOT_MASK) != 0;
+ if (eot)
+ devn--;
+
+ for (i = 0; i < devn; i++) {
+ ret = sbefifo_readw(sbefifo, rbuf->wpos);
+ if (ret)
+ goto out;
+
+ if (likely(!test_bit(SBEFIFO_XFR_CANCEL, &xfr->flags)))
+ sbefifo_buf_wrotenb(rbuf, 1 << 2);
+ }
+
+ if (eot) {
+ ret = sbefifo_ack_eot(sbefifo);
+ if (ret)
+ goto out;
+
+ set_bit(SBEFIFO_XFR_COMPLETE, &xfr->flags);
+ list_del(&xfr->xfrs);
+ if (unlikely(test_bit(SBEFIFO_XFR_CANCEL,
+ &xfr->flags)))
+ kfree(xfr);
+ break;
+ }
+ }
+
+out:
+ if (unlikely(ret)) {
+ sbefifo->rc = ret;
+ dev_err(&sbefifo->fsi_dev->dev,
+ "Fatal bus access failure: %d\n", ret);
+ list_for_each_entry_safe(xfr, tmp, &sbefifo->xfrs, xfrs) {
+ list_del(&xfr->xfrs);
+ kfree(xfr);
+ }
+ INIT_LIST_HEAD(&sbefifo->xfrs);
+
+ } else if (eot && sbefifo_next_xfr(sbefifo)) {
+ sbefifo_get(sbefifo);
+ sbefifo->poll_timer.expires = jiffies;
+ add_timer(&sbefifo->poll_timer);
+ }
+
+ sbefifo_put(sbefifo);
+ wake_up_interruptible(&sbefifo->wait);
+
+out_unlock:
+ spin_unlock(&sbefifo->lock);
+}
+
+static int sbefifo_request_reset(struct sbefifo *sbefifo)
+{
+ int ret;
+ u32 status;
+ unsigned long start;
+ const unsigned int wait_time = 5; /* jiffies */
+ const unsigned long timeout = msecs_to_jiffies(250);
+
+ ret = sbefifo_outw(sbefifo, SBEFIFO_UP | SBEFIFO_REQ_RESET, 1);
+ if (ret)
+ return ret;
+
+ start = jiffies;
+
+ do {
+ ret = sbefifo_inw(sbefifo, SBEFIFO_UP | SBEFIFO_STS, &status);
+ if (ret)
+ return ret;
+
+ if (!(status & SBEFIFO_STS_RESET_REQ))
+ return 0;
+
+ set_current_state(TASK_INTERRUPTIBLE);
+ if (schedule_timeout(wait_time) > 0)
+ return -EINTR;
+ } while (time_after(start + timeout, jiffies));
+
+ return -ETIME;
+}
+
+static int sbefifo_probe(struct device *dev)
+{
+ struct fsi_device *fsi_dev = to_fsi_dev(dev);
+ struct sbefifo *sbefifo;
+ u32 up, down;
+ int ret;
+
+ dev_dbg(dev, "Found sbefifo device\n");
+ sbefifo = kzalloc(sizeof(*sbefifo), GFP_KERNEL);
+ if (!sbefifo)
+ return -ENOMEM;
+
+ sbefifo->fsi_dev = fsi_dev;
+
+ ret = sbefifo_inw(sbefifo, SBEFIFO_UP | SBEFIFO_STS, &up);
+ if (ret)
+ return ret;
+
+ ret = sbefifo_inw(sbefifo, SBEFIFO_DWN | SBEFIFO_STS, &down);
+ if (ret)
+ return ret;
+
+ if (!(up & SBEFIFO_EMPTY) || !(down & SBEFIFO_EMPTY)) {
+ ret = sbefifo_request_reset(sbefifo);
+ if (ret) {
+ dev_err(dev,
+ "fifos weren't empty and failed the reset\n");
+ return ret;
+ }
+ }
+
+ spin_lock_init(&sbefifo->lock);
+ kref_init(&sbefifo->kref);
+ init_waitqueue_head(&sbefifo->wait);
+ INIT_LIST_HEAD(&sbefifo->xfrs);
+
+ sbefifo->idx = ida_simple_get(&sbefifo_ida, 1, INT_MAX, GFP_KERNEL);
+ snprintf(sbefifo->name, sizeof(sbefifo->name), "sbefifo%d",
+ sbefifo->idx);
+
+ /* This bit of silicon doesn't offer any interrupts... */
+ setup_timer(&sbefifo->poll_timer, sbefifo_poll_timer,
+ (unsigned long)sbefifo);
+
+ dev_set_drvdata(dev, sbefifo);
+
+ return 0;
+}
+
+static int sbefifo_remove(struct device *dev)
+{
+ struct sbefifo *sbefifo = dev_get_drvdata(dev);
+ struct sbefifo_xfr *xfr, *tmp;
+
+ spin_lock(&sbefifo->lock);
+
+ WRITE_ONCE(sbefifo->rc, -ENODEV);
+ list_for_each_entry_safe(xfr, tmp, &sbefifo->xfrs, xfrs) {
+ list_del(&xfr->xfrs);
+ kfree(xfr);
+ }
+
+ INIT_LIST_HEAD(&sbefifo->xfrs);
+
+ spin_unlock(&sbefifo->lock);
+
+ wake_up_all(&sbefifo->wait);
+
+ ida_simple_remove(&sbefifo_ida, sbefifo->idx);
+
+ if (del_timer_sync(&sbefifo->poll_timer))
+ sbefifo_put(sbefifo);
+
+ sbefifo_put(sbefifo);
+
+ return 0;
+}
+
+static struct fsi_device_id sbefifo_ids[] = {
+ {
+ .engine_type = FSI_ENGID_SBE,
+ .version = FSI_VERSION_ANY,
+ },
+ { 0 }
+};
+
+static struct fsi_driver sbefifo_drv = {
+ .id_table = sbefifo_ids,
+ .drv = {
+ .name = DEVICE_NAME,
+ .bus = &fsi_bus_type,
+ .probe = sbefifo_probe,
+ .remove = sbefifo_remove,
+ }
+};
+
+static int sbefifo_init(void)
+{
+ return fsi_driver_register(&sbefifo_drv);
+}
+
+static void sbefifo_exit(void)
+{
+ fsi_driver_unregister(&sbefifo_drv);
+
+ ida_destroy(&sbefifo_ida);
+}
+
+module_init(sbefifo_init);
+module_exit(sbefifo_exit);
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Brad Bishop <bradleyb@fuzziesquirrel.com>");
+MODULE_AUTHOR("Eddie James <eajames@linux.vnet.ibm.com>");
+MODULE_DESCRIPTION("Linux device interface to the POWER Self Boot Engine");
--
1.8.3.1
^ permalink raw reply related
* [PATCH v4 1/4] dt-bindings: fsi: Add SBEFIFO documentation
From: Eddie James @ 2017-11-17 19:34 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
bradleyb-r5pk2Da7Bxt8sGd51Jp2sdBPR1lH4CV8,
cbostic-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8,
joel-U3u1mxZcP9KHXe+LvDLADg,
eajames-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8, Edward A. James
In-Reply-To: <1510947274-7519-1-git-send-email-eajames-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org>
From: "Edward A. James" <eajames-r/Jw6+rmf7HQT0dZR+AlfA@public.gmane.org>
Document the bindings for the SBE CFAM device. SBE devices are
located on a CFAM off an FSI bus.
Signed-off-by: Edward A. James <eajames-r/Jw6+rmf7HQT0dZR+AlfA@public.gmane.org>
---
.../devicetree/bindings/fsi/ibm,p9-sbefifo.txt | 35 ++++++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.txt
diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.txt b/Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.txt
new file mode 100644
index 0000000..e69b0c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.txt
@@ -0,0 +1,35 @@
+Device-tree bindings for P9 SBEFIFO CFAM device
+-----------------------------------------------
+
+Required properties:
+ - compatible = "ibm,p9-sbefifo";
+ - reg = < address size >; : FSI CFAM address for the SBE engine
+ and address space size.
+ - #address-cells = <1>; : Number of address cells in child
+ nodes.
+ - #size-cells = <0>; : Number of size cells in child nodes.
+
+Optional properties:
+ - <child nodes> : Devices that are accessible through
+ the SBEFIFO. Child nodes are "opaque"
+ to the SBEFIFO; the SBEFIFO needs no
+ information about a child node other
+ than if it exists or not.
+
+Child node optional properties:
+ - compatible = "dts-name"
+ - reg = < address >; : Meaningful only for the child node
+
+Examples:
+
+ sbefifo@2400 {
+ compatible = "ibm,p9-sbefifo";
+ reg = < 0x2400 0x400 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ occ@1 {
+ compatible = "ibm,p9-occ";
+ reg = < 1 >;
+ };
+ };
--
1.8.3.1
--
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^ permalink raw reply related
* [PATCH v4 0/4] drivers/fsi: Add SBEFIFO client driver
From: Eddie James @ 2017-11-17 19:34 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
bradleyb-r5pk2Da7Bxt8sGd51Jp2sdBPR1lH4CV8,
cbostic-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8,
joel-U3u1mxZcP9KHXe+LvDLADg,
eajames-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8, Edward A. James
From: "Edward A. James" <eajames-r/Jw6+rmf7HQT0dZR+AlfA@public.gmane.org>
This series adds an FSI-based device driver for the SBEFIFO.
IBM POWER9 processors contain some embedded hardware and software bits
collectively referred to as the self boot engine (SBE). One role of
the SBE is to act as a proxy that provides access to the registers of
the POWER chip from other (embedded) systems.
The POWER9 chip contains a hardware frontend for communicating with
the SBE from remote systems called the SBEFIFO. The SBEFIFO logic
is contained within an FSI CFAM and as such the driver implements an
FSI bus device.
The SBE expects to communicate using a defined wire protocol; however,
the driver knows nothing of the protocol and only provides raw access
to the fifo device to userspace applications wishing to communicate with
the SBE using the wire protocol.
The SBEFIFO consists of two hardware fifos. The upstream fifo is used
by the driver to transfer data to the SBE on the POWER chip, from the
system hosting the driver. The downstream fifo is used by the driver to
transfer data from the SBE on the power chip to the system hosting the
driver.
Changes since v3:
- Add reset procedure and use it if there is data in the FIFO at probe time.
- Add timeout for waiting for data to appear in the FIFO; if the SBE isn't
running, then previously we would wait forever.
- Fix remove() order of operations.
- Fix xfr memory leak.
- Formatting fixes.
Edward A. James (4):
dt-bindings: fsi: Add SBEFIFO documentation
drivers/fsi: Add SBEFIFO FSI client device driver
drivers/fsi: sbefifo: Add miscdevice
drivers/fsi: sbefifo: Add in-kernel API
.../devicetree/bindings/fsi/ibm,p9-sbefifo.txt | 35 +
drivers/fsi/Kconfig | 7 +
drivers/fsi/Makefile | 1 +
drivers/fsi/fsi-sbefifo.c | 1024 ++++++++++++++++++++
include/linux/fsi-sbefifo.h | 30 +
5 files changed, 1097 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.txt
create mode 100644 drivers/fsi/fsi-sbefifo.c
create mode 100644 include/linux/fsi-sbefifo.h
--
1.8.3.1
--
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^ permalink raw reply
* Re: [PATCH v3 2/2] dt-binding: timer: document NPCM7xx timer DT bindings
From: Brendan Higgins @ 2017-11-17 19:31 UTC (permalink / raw)
To: Rob Herring
Cc: Tomer Maimon, Mark Rutland, Daniel Lezcano, Thomas Gleixner,
Avi Fishman, Rick Altherr, Joel Stanley, devicetree,
Linux Kernel Mailing List, OpenBMC Maillist
In-Reply-To: <20171106223950.ophliqmm7tz7aglu@rob-hp-laptop>
On Mon, Nov 6, 2017 at 2:39 PM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Mon, Nov 06, 2017 at 06:28:36PM +0200, Tomer Maimon wrote:
>> Added device tree binding documentation for Nuvoton NPCM7xx timer.
>>
>> Signed-off-by: Tomer Maimon <tmaimon77-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>> .../bindings/timer/nuvoton,npcm7xx-timer.txt | 25 ++++++++++++++++++++++
>> 1 file changed, 25 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.txt
>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Reviewed-by: Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply
* Re: [PATCH v3 1/2] clocksource: npcm: add NPCM7xx timer driver
From: Brendan Higgins @ 2017-11-17 19:29 UTC (permalink / raw)
To: Tomer Maimon
Cc: Rob Herring, Mark Rutland, Daniel Lezcano, Thomas Gleixner,
Avi Fishman, Rick Altherr, Joel Stanley, devicetree,
Linux Kernel Mailing List, OpenBMC Maillist
In-Reply-To: <1509985716-25759-2-git-send-email-tmaimon77-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Mon, Nov 6, 2017 at 8:28 AM, Tomer Maimon <tmaimon77-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Add Nuvoton BMC NPCM7xx timer driver.
>
> the clocksource Enable 24-bit TIMER0 and TIMER1 counters,
> while TIMER0 serves as clockevent and TIMER1 serves as clocksource.
>
> Signed-off-by: Tomer Maimon <tmaimon77-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> drivers/clocksource/Kconfig | 8 ++
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/npcm7xx-timer.c | 239 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 248 insertions(+)
> create mode 100644 drivers/clocksource/npcm7xx-timer.c
>
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index cc6062049170..46184af75d6c 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -140,6 +140,14 @@ config VT8500_TIMER
> help
> Enables support for the VT8500 driver.
>
> +config NPCM7XX_TIMER
> + bool "NPCM7xx timer driver" if COMPILE_TEST
> + depends on HAS_IOMEM
> + select CLKSRC_MMIO
> + help
> + Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx arcithcture,
> + While TIMER0 serves as clockevent and TIMER1 serves as clocksource.
> +
> config CADENCE_TTC_TIMER
> bool "Cadence TTC timer driver" if COMPILE_TEST
> depends on COMMON_CLK
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 72711f1491e3..ff2b30b75b5b 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -54,6 +54,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
> obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
> obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
> obj-$(CONFIG_OWL_TIMER) += owl-timer.o
> +obj-$(CONFIG_NPCM7XX_TIMER) += npcm7xx-timer.o
>
> obj-$(CONFIG_ARC_TIMERS) += arc_timer.o
> obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
> diff --git a/drivers/clocksource/npcm7xx-timer.c b/drivers/clocksource/npcm7xx-timer.c
> new file mode 100644
> index 000000000000..b9b468da4560
> --- /dev/null
> +++ b/drivers/clocksource/npcm7xx-timer.c
> @@ -0,0 +1,239 @@
> +
> +/*
> + * Copyright (c) 2017 Nuvoton Technology corporation.
> + * Copyright 2017 Google, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation;version 2 of the License.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/sched.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/err.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/clockchips.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +#include "timer-of.h"
> +
> +/* Timers registers */
> +#define NPCM7XX_REG_TCSR0 0x0 /* Timer 0 Control and Status Register */
> +#define NPCM7XX_REG_TICR0 0x8 /* Timer 0 Initial Count Register */
> +#define NPCM7XX_REG_TCSR1 0x4 /* Timer 1 Control and Status Register */
> +#define NPCM7XX_REG_TICR1 0xc /* Timer 1 Initial Count Register */
> +#define NPCM7XX_REG_TDR1 0x14 /* Timer 1 Data Register */
> +#define NPCM7XX_REG_TISR 0x18 /* Timer Interrupt Status Register */
> +
> +/* Timers control */
> +#define NPCM7XX_Tx_RESETINT 0x1f
> +#define NPCM7XX_Tx_PERIOD BIT(27)
> +#define NPCM7XX_Tx_INTEN BIT(29)
> +#define NPCM7XX_Tx_COUNTEN BIT(30)
> +#define NPCM7XX_Tx_ONESHOT 0x0
> +#define NPCM7XX_Tx_OPER GENMASK(3, 27)
> +#define NPCM7XX_Tx_MIN_PRESCALE 0x1
> +#define NPCM7XX_Tx_TDR_MASK_BITS 24
> +#define NPCM7XX_Tx_MAX_CNT 0xFFFFFF
> +#define NPCM7XX_T0_CLR_INT 0x1
> +#define NPCM7XX_Tx_CLR_CSR 0x0
> +
> +/* Timers operating mode */
> +#define NPCM7XX_START_PERIODIC_Tx (NPCM7XX_Tx_PERIOD | NPCM7XX_Tx_COUNTEN | \
> + NPCM7XX_Tx_INTEN | \
> + NPCM7XX_Tx_MIN_PRESCALE)
> +
> +#define NPCM7XX_START_ONESHOT_Tx (NPCM7XX_Tx_ONESHOT | NPCM7XX_Tx_COUNTEN | \
> + NPCM7XX_Tx_INTEN | \
> + NPCM7XX_Tx_MIN_PRESCALE)
> +
> +#define NPCM7XX_START_Tx (NPCM7XX_Tx_COUNTEN | NPCM7XX_Tx_PERIOD | \
> + NPCM7XX_Tx_MIN_PRESCALE)
> +
> +#define NPCM7XX_DEFAULT_CSR (NPCM7XX_Tx_CLR_CSR | NPCM7XX_Tx_MIN_PRESCALE)
> +
> +static int npcm7xx_timer_resume(struct clock_event_device *evt)
> +{
> + struct timer_of *to = to_timer_of(evt);
> + u32 val;
> +
> + val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
> + val |= NPCM7XX_Tx_COUNTEN;
> + writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
> +
> + return 0;
> +}
> +
> +static int npcm7xx_timer_shutdown(struct clock_event_device *evt)
> +{
> + struct timer_of *to = to_timer_of(evt);
> + u32 val;
> +
> + val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
> + val &= ~NPCM7XX_Tx_COUNTEN;
> + writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
> +
> + return 0;
> +}
> +
> +static int npcm7xx_timer_oneshot(struct clock_event_device *evt)
> +{
> + struct timer_of *to = to_timer_of(evt);
> + u32 val;
> +
> + val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
> + val &= ~NPCM7XX_Tx_OPER;
> +
> + val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
> + val |= NPCM7XX_START_ONESHOT_Tx;
> + writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
> +
> + return 0;
> +}
> +
> +static int npcm7xx_timer_periodic(struct clock_event_device *evt)
> +{
> + struct timer_of *to = to_timer_of(evt);
> + u32 val;
> +
> + val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
> + val &= ~NPCM7XX_Tx_OPER;
> +
> + writel((timer_of_rate(to) / HZ),
> + timer_of_base(to) + NPCM7XX_REG_TICR0);
> + val |= NPCM7XX_START_PERIODIC_Tx;
> +
> + writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
> +
> + return 0;
> +}
> +
> +static int npcm7xx_clockevent_setnextevent(unsigned long evt,
> + struct clock_event_device *clk)
> +{
> + struct timer_of *to = to_timer_of(clk);
> + u32 val;
> +
> + writel(evt, timer_of_base(to) + NPCM7XX_REG_TICR0);
> + val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
> + val |= NPCM7XX_START_Tx;
> + writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
> +
> + return 0;
> +}
> +
> +static irqreturn_t npcm7xx_timer0_interrupt(int irq, void *dev_id)
> +{
> + struct clock_event_device *evt = (struct clock_event_device *)dev_id;
> + struct timer_of *to = to_timer_of(evt);
> +
> + writel(NPCM7XX_T0_CLR_INT, timer_of_base(to) + NPCM7XX_REG_TISR);
> +
> + evt->event_handler(evt);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static struct timer_of to_npcm7xx = {
nit: the prefix should be npcm7xx_*
> + .flags = TIMER_OF_IRQ | TIMER_OF_BASE,
> +
> + .clkevt = {
> + .name = "npcm7xx-timer0",
> + .features = CLOCK_EVT_FEAT_PERIODIC |
> + CLOCK_EVT_FEAT_ONESHOT,
> + .set_next_event = npcm7xx_clockevent_setnextevent,
> + .set_state_shutdown = npcm7xx_timer_shutdown,
> + .set_state_periodic = npcm7xx_timer_periodic,
> + .set_state_oneshot = npcm7xx_timer_oneshot,
> + .tick_resume = npcm7xx_timer_resume,
> + .rating = 300,
> + },
> +
> + .of_irq = {
> + .handler = npcm7xx_timer0_interrupt,
> + .flags = IRQF_TIMER | IRQF_IRQPOLL,
> + },
> +};
> +
> +static void __init npcm7xx_clockevents_init(u32 rate)
> +{
> + writel(NPCM7XX_DEFAULT_CSR,
> + timer_of_base(&to_npcm7xx) + NPCM7XX_REG_TCSR0);
> +
> + writel(NPCM7XX_Tx_RESETINT,
> + timer_of_base(&to_npcm7xx) + NPCM7XX_REG_TISR);
> +
> + to_npcm7xx.clkevt.cpumask = cpumask_of(0);
> + clockevents_config_and_register(&to_npcm7xx.clkevt, rate,
> + 0x1, NPCM7XX_Tx_MAX_CNT);
> +}
> +
> +static void __init npcm7xx_clocksource_init(u32 rate)
> +{
> + u32 val;
> +
> + writel(NPCM7XX_DEFAULT_CSR,
> + timer_of_base(&to_npcm7xx) + NPCM7XX_REG_TCSR1);
> + writel(NPCM7XX_Tx_MAX_CNT,
> + timer_of_base(&to_npcm7xx) + NPCM7XX_REG_TICR1);
> +
> + val = readl(timer_of_base(&to_npcm7xx) + NPCM7XX_REG_TCSR1);
> + val |= NPCM7XX_START_Tx;
> + writel(val, timer_of_base(&to_npcm7xx) + NPCM7XX_REG_TCSR1);
> +
> + clocksource_mmio_init(timer_of_base(&to_npcm7xx) +
> + NPCM7XX_REG_TDR1,
> + "npcm7xx-timer1", rate,
> + 300, (unsigned int)NPCM7XX_Tx_TDR_MASK_BITS,
> + clocksource_mmio_readl_down);
> +}
> +
> +static int __init npcm7xx_timer_init(struct device_node *np)
> +{
> + struct clk *clk;
> + int ret;
> + u32 rate;
> +
> + clk = of_clk_get(np, 0);
> +
> + if (IS_ERR(clk)) {
> + ret = of_property_read_u32(np, "clock-frequency", &rate);
> + if (ret)
> + return ret;
> + } else {
> + clk_prepare_enable(clk);
> + rate = clk_get_rate(clk);
> + to_npcm7xx.of_clk.clk = clk;
> + }
> +
> + ret = timer_of_init(np, &to_npcm7xx);
> + if (ret)
> + goto err_timer_of_init;
> +
> + /* Clock input is divided by PRESCALE + 1 before it is fed */
> + /* to the counter */
> + rate = rate / (NPCM7XX_Tx_MIN_PRESCALE + 1);
> + to_npcm7xx.of_clk.rate = rate;
> +
> + npcm7xx_clocksource_init(rate);
> + npcm7xx_clockevents_init(rate);
> +
> + pr_info("Enabling NPCM7xx clocksource timer base: %p, IRQ: %d\n",
> + timer_of_base(&to_npcm7xx), timer_of_irq(&to_npcm7xx));
> +
> + return 0;
> +
> +err_timer_of_init:
> + if (!IS_ERR(clk)) {
> + clk_disable_unprepare(clk);
> + clk_put(clk);
> + }
> +
> + return ret;
> +}
> +
> +TIMER_OF_DECLARE(npcm7xx, "nuvoton,npcm750-timer", npcm7xx_timer_init);
> +
> --
> 2.14.1
>
Reviewed-by: Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
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^ permalink raw reply
* [PATCH v8 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM architecture
From: Brendan Higgins @ 2017-11-17 19:07 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
mark.rutland-5wv7dgnIgG8, tmaimon77-Re5JQEeQqe8AvxtiuMwx3w,
avifishman70-Re5JQEeQqe8AvxtiuMwx3w,
raltherr-hpIqsD4AKlfQT0dZR+AlfA,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w, julien.thierry-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Brendan Higgins
In-Reply-To: <20171117190747.21642-1-brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Add maintainers and reviewers for the Nuvoton NPCM architecture.
Signed-off-by: Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Reviewed-by: Tomer Maimon <tmaimon77-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Avi Fishman <avifishman70-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
MAINTAINERS | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 44cb004c765d..ec0d35384a16 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1598,6 +1598,19 @@ F: drivers/pinctrl/nomadik/
F: drivers/i2c/busses/i2c-nomadik.c
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
+ARM/NUVOTON NPCM ARCHITECTURE
+M: Avi Fishman <avifishman70-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+M: Tomer Maimon <tmaimon77-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+R: Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
+R: Rick Altherr <raltherr-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
+L: openbmc-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org (moderated for non-subscribers)
+S: Supported
+F: arch/arm/mach-npcm/
+F: arch/arm/boot/dts/nuvoton-npcm*
+F: include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
+F: drivers/*/*npcm*
+F: Documentation/*/*npcm*
+
ARM/NUVOTON W90X900 ARM ARCHITECTURE
M: Wan ZongShun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers)
--
2.15.0.448.gf294e3d99a-goog
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^ permalink raw reply related
* [PATCH v8 2/3] arm: dts: add Nuvoton NPCM750 device tree
From: Brendan Higgins @ 2017-11-17 19:07 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
mark.rutland-5wv7dgnIgG8, tmaimon77-Re5JQEeQqe8AvxtiuMwx3w,
avifishman70-Re5JQEeQqe8AvxtiuMwx3w,
raltherr-hpIqsD4AKlfQT0dZR+AlfA,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w, julien.thierry-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Brendan Higgins
In-Reply-To: <20171117190747.21642-1-brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Add a common device tree for all Nuvoton NPCM750 BMCs and a board
specific device tree for the NPCM750 (Poleg) evaluation board.
Signed-off-by: Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Reviewed-by: Tomer Maimon <tmaimon77-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Avi Fishman <avifishman70-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
Tested-by: Tomer Maimon <tmaimon77-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Avi Fishman <avifishman70-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
Changes since v7:
- Added arm,shared-override to l2 cache
- Cleaned up node names
- Cleaned up ranges properties
- Fixed address for nuvoton,npcm750-timer
- Dropped watchdog nodes for now since the properties in them are wrong
---
.../arm/cpu-enable-method/nuvoton,npcm7xx-smp | 42 +++++
.../devicetree/bindings/arm/npcm/npcm.txt | 6 +
arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 44 ++++++
arch/arm/boot/dts/nuvoton-npcm750.dtsi | 171 +++++++++++++++++++++
include/dt-bindings/clock/nuvoton,npcm7xx-clks.h | 39 +++++
5 files changed, 302 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp
create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt
create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts
create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi
create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp
new file mode 100644
index 000000000000..e81f85b400cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp
@@ -0,0 +1,42 @@
+=========================================================
+Secondary CPU enable-method "nuvoton,npcm7xx-smp" binding
+=========================================================
+
+To apply to all CPUs, a single "nuvoton,npcm7xx-smp" enable method should be
+defined in the "cpus" node.
+
+Enable method name: "nuvoton,npcm7xx-smp"
+Compatible machines: "nuvoton,npcm750"
+Compatible CPUs: "arm,cortex-a9"
+Related properties: (none)
+
+Note:
+This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
+"nuvoton,npcm750-gcr".
+
+Example:
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "nuvoton,npcm7xx-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
new file mode 100644
index 000000000000..2d87d9ecea85
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
@@ -0,0 +1,6 @@
+NPCM Platforms Device Tree Bindings
+-----------------------------------
+NPCM750 SoC
+Required root node properties:
+ - compatible = "nuvoton,npcm750";
+
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
new file mode 100644
index 000000000000..9c1122a2c21c
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
@@ -0,0 +1,44 @@
+/*
+ * DTS file for all NPCM750 SoCs
+ *
+ * Copyright 2012 Tomer Maimon <tomer.maimon-KrzQf0k3Iz9BDgjK7y7TUQ@public.gmane.org>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "nuvoton-npcm750.dtsi"
+
+/ {
+ model = "Nuvoton npcm750 Development Board (Device Tree)";
+ compatible = "nuvoton,npcm750";
+
+ chosen {
+ stdout-path = &serial3;
+ };
+
+ memory {
+ reg = <0 0x40000000>;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&serial3 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
new file mode 100644
index 000000000000..0dbea1195d7e
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -0,0 +1,171 @@
+/*
+ * DTSi file for the NPCM750 SoC
+ *
+ * Copyright 2012 Tomer Maimon <tomer.maimon-KrzQf0k3Iz9BDgjK7y7TUQ@public.gmane.org>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/nuvoton,npcm7xx-clks.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "nuvoton,npcm7xx-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <0>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <1>;
+ next-level-cache = <&l2>;
+ };
+ };
+
+/* external clock signal rg1refck, supplied by the phy */
+clk-rg1refck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+};
+
+/* external clock signal rg2refck, supplied by the phy */
+clk-rg2refck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+};
+
+clk-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+};
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0x0 0xf0000000 0x00900000>;
+
+ gcr: gcr@800000 {
+ compatible = "nuvoton,npcm750-gcr", "syscon",
+ "simple-mfd";
+ reg = <0x800000 0x1000>;
+ };
+
+ scu: scu@3fe000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x3fe000 0x1000>;
+ };
+
+ l2: cache-controller@3fc000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x3fc000 0x1000>;
+ interrupts = <0 21 4>;
+ cache-unified;
+ cache-level = <2>;
+ clocks = <&clk NPCM7XX_CLK_AXI>;
+ arm,shared-override;
+ };
+
+ gic: interrupt-controller@3ff000 {
+ compatible = "arm,cortex-a9-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x3ff000 0x1000>,
+ <0x3fe100 0x100>;
+ };
+
+ timer@3fe600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x3fe600 0x20>;
+ interrupts = <1 13 0x304>;
+ clocks = <&clk NPCM7XX_CLK_TIMER>;
+ };
+ };
+
+ ahb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ clk: clock-controller@f0801000 {
+ compatible = "nuvoton,npcm750-clk";
+ #clock-cells = <1>;
+ reg = <0xf0801000 0x1000>;
+ status = "okay";
+ };
+
+ apb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0x0 0xf0000000 0x00300000>;
+
+ timer0: timer@8000 {
+ compatible = "nuvoton,npcm750-timer";
+ interrupts = <0 32 4>;
+ reg = <0x8000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_TIMER>;
+ };
+
+ serial0: serial@1000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0x1000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_UART_CORE>;
+ interrupts = <0 2 4>;
+ status = "disabled";
+ };
+
+ serial1: serial@2000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0x2000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_UART_CORE>;
+ interrupts = <0 3 4>;
+ status = "disabled";
+ };
+
+ serial2: serial@3000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0x3000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_UART_CORE>;
+ interrupts = <0 4 4>;
+ status = "disabled";
+ };
+
+ serial3: serial@4000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0x4000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_UART_CORE>;
+ interrupts = <0 5 4>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
new file mode 100644
index 000000000000..c69d3bbf7e42
--- /dev/null
+++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2016 Nuvoton Technologies, tali.perry-KrzQf0k3Iz9BDgjK7y7TUQ@public.gmane.org
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ */
+
+#ifndef _DT_BINDINGS_CLK_NPCM7XX_H
+#define _DT_BINDINGS_CLK_NPCM7XX_H
+
+#define NPCM7XX_CLK_PLL0 0
+#define NPCM7XX_CLK_PLL1 1
+#define NPCM7XX_CLK_PLL2 2
+#define NPCM7XX_CLK_GFX 3
+#define NPCM7XX_CLK_APB1 4
+#define NPCM7XX_CLK_APB2 5
+#define NPCM7XX_CLK_APB3 6
+#define NPCM7XX_CLK_APB4 7
+#define NPCM7XX_CLK_APB5 8
+#define NPCM7XX_CLK_MC 9
+#define NPCM7XX_CLK_CPU 10
+#define NPCM7XX_CLK_SPI0 11
+#define NPCM7XX_CLK_SPI3 12
+#define NPCM7XX_CLK_SPIX 13
+#define NPCM7XX_CLK_UART_CORE 14
+#define NPCM7XX_CLK_TIMER 15
+#define NPCM7XX_CLK_HOST_UART 16
+#define NPCM7XX_CLK_MMC 17
+#define NPCM7XX_CLK_SDHC 18
+#define NPCM7XX_CLK_ADC 19
+#define NPCM7XX_CLK_GFX_MEM 20
+#define NPCM7XX_CLK_USB_BRIDGE 21
+#define NPCM7XX_CLK_AXI 22
+#define NPCM7XX_CLK_AHB 23
+#define NPCM7XX_CLK_EMC 24
+#define NPCM7XX_CLK_GMAC 25
+
+#endif
--
2.15.0.448.gf294e3d99a-goog
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* [PATCH v8 1/3] arm: npcm: add basic support for Nuvoton BMCs
From: Brendan Higgins @ 2017-11-17 19:07 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
mark.rutland-5wv7dgnIgG8, tmaimon77-Re5JQEeQqe8AvxtiuMwx3w,
avifishman70-Re5JQEeQqe8AvxtiuMwx3w,
raltherr-hpIqsD4AKlfQT0dZR+AlfA,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w, julien.thierry-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Brendan Higgins
In-Reply-To: <20171117190747.21642-1-brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Adds basic support for the Nuvoton NPCM750 BMC.
Signed-off-by: Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Reviewed-by: Tomer Maimon <tmaimon77-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Avi Fishman <avifishman70-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Tomer Maimon <tmaimon77-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Avi Fishman <avifishman70-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
Changes since v7:
- Fixed useless parameter in print statement
- Added/cleaned up some comments
- Fixed typo in DT_MACHINE_START
- Got rid of L2C aux value
- Dropped unnecessary memory barriers
- Renamed CPU_NPCM750 to ARCH_NPCM750
- Fixed some other minor issues
---
arch/arm/Kconfig | 2 ++
arch/arm/Makefile | 1 +
arch/arm/mach-npcm/Kconfig | 48 +++++++++++++++++++++++++
arch/arm/mach-npcm/Makefile | 3 ++
arch/arm/mach-npcm/headsmp.S | 21 +++++++++++
arch/arm/mach-npcm/npcm7xx.c | 25 +++++++++++++
arch/arm/mach-npcm/platsmp.c | 85 ++++++++++++++++++++++++++++++++++++++++++++
7 files changed, 185 insertions(+)
create mode 100644 arch/arm/mach-npcm/Kconfig
create mode 100644 arch/arm/mach-npcm/Makefile
create mode 100644 arch/arm/mach-npcm/headsmp.S
create mode 100644 arch/arm/mach-npcm/npcm7xx.c
create mode 100644 arch/arm/mach-npcm/platsmp.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 61a0cb15067e..05543f1cfbde 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -782,6 +782,8 @@ source "arch/arm/mach-netx/Kconfig"
source "arch/arm/mach-nomadik/Kconfig"
+source "arch/arm/mach-npcm/Kconfig"
+
source "arch/arm/mach-nspire/Kconfig"
source "arch/arm/plat-omap/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 47d3a1ab08d2..60ca50c7d762 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
machine-$(CONFIG_ARCH_MXS) += mxs
machine-$(CONFIG_ARCH_NETX) += netx
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
+machine-$(CONFIG_ARCH_NPCM) += npcm
machine-$(CONFIG_ARCH_NSPIRE) += nspire
machine-$(CONFIG_ARCH_OXNAS) += oxnas
machine-$(CONFIG_ARCH_OMAP1) += omap1
diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
new file mode 100644
index 000000000000..6ff9df2636be
--- /dev/null
+++ b/arch/arm/mach-npcm/Kconfig
@@ -0,0 +1,48 @@
+menuconfig ARCH_NPCM
+ bool "Nuvoton NPCM Architecture"
+ select ARCH_REQUIRE_GPIOLIB
+ select USE_OF
+ select PINCTRL
+ select PINCTRL_NPCM7XX
+
+if ARCH_NPCM
+
+comment "NPCM7XX CPU type"
+
+config ARCH_NPCM750
+ depends on ARCH_NPCM && ARCH_MULTI_V7
+ bool "Support for NPCM750 BMC CPU (Poleg)"
+ select CACHE_L2X0
+ select CPU_V7
+ select ARM_GIC
+ select HAVE_SMP
+ select SMP
+ select SMP_ON_UP
+ select HAVE_ARM_SCU
+ select HAVE_ARM_TWD if SMP
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_764369
+ select ARM_ERRATA_794072
+ select PL310_ERRATA_588369
+ select PL310_ERRATA_727915
+ select USB_EHCI_ROOT_HUB_TT
+ select USB_ARCH_HAS_HCD
+ select USB_ARCH_HAS_EHCI
+ select USB_EHCI_HCD
+ select USB_ARCH_HAS_OHCI
+ select USB_OHCI_HCD
+ select USB
+ select FIQ
+ select CPU_USE_DOMAINS
+ select GENERIC_CLOCKEVENTS
+ select CLKDEV_LOOKUP
+ select COMMON_CLK if OF
+ select NPCM750_TIMER
+ select MFD_SYSCON
+ help
+ Support for NPCM750 BMC CPU (Poleg).
+
+ Nuvoton NPCM750 BMC based on the Cortex A9.
+
+endif
diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile
new file mode 100644
index 000000000000..c7a1316d27c1
--- /dev/null
+++ b/arch/arm/mach-npcm/Makefile
@@ -0,0 +1,3 @@
+AFLAGS_headsmp.o += -march=armv7-a
+
+obj-$(CONFIG_ARCH_NPCM750) += npcm7xx.o platsmp.o headsmp.o
diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S
new file mode 100644
index 000000000000..2d0d8880634b
--- /dev/null
+++ b/arch/arm/mach-npcm/headsmp.S
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+
+/*
+ * The boot ROM does not start secondary CPUs in SVC mode, so we need to do that
+ * here.
+ */
+ENTRY(npcm7xx_secondary_startup)
+ safe_svcmode_maskall r0
+
+ b secondary_startup
+ENDPROC(npcm7xx_secondary_startup)
diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
new file mode 100644
index 000000000000..500bdd0a9ebb
--- /dev/null
+++ b/arch/arm/mach-npcm/npcm7xx.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2017 Nuvoton Technology corporation.
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
+static const char *const npcm7xx_dt_match[] = {
+ "nuvoton,npcm750",
+ NULL
+};
+
+DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
+ .atag_offset = 0x100,
+ .dt_compat = npcm7xx_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c
new file mode 100644
index 000000000000..959af7bd741f
--- /dev/null
+++ b/arch/arm/mach-npcm/platsmp.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "nuvoton,npcm7xx-smp: " fmt
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+#include <asm/smp.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+
+#define NPCM7XX_SCRPAD_REG 0x13c
+
+extern void npcm7xx_secondary_startup(void);
+
+static int npcm7xx_smp_boot_secondary(unsigned int cpu,
+ struct task_struct *idle)
+{
+ struct device_node *gcr_np;
+ void __iomem *gcr_base;
+ int ret = 0;
+
+ gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr");
+ if (!gcr_np) {
+ pr_err("no gcr device node\n");
+ ret = -ENODEV;
+ goto out;
+ }
+ gcr_base = of_iomap(gcr_np, 0);
+ if (!gcr_base) {
+ pr_err("could not iomap gcr");
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ /* give boot ROM kernel start address. */
+ iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +
+ NPCM7XX_SCRPAD_REG);
+ /* make sure the previous write is seen by all observers. */
+ dsb_sev();
+
+ iounmap(gcr_base);
+out:
+ return ret;
+}
+
+static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)
+{
+ struct device_node *scu_np;
+ void __iomem *scu_base;
+
+ scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+ if (!scu_np) {
+ pr_err("no scu device node\n");
+ return;
+ }
+ scu_base = of_iomap(scu_np, 0);
+ if (!scu_base) {
+ pr_err("could not iomap scu");
+ return;
+ }
+
+ scu_enable(scu_base);
+
+ iounmap(scu_base);
+}
+
+static struct smp_operations npcm7xx_smp_ops __initdata = {
+ .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,
+ .smp_boot_secondary = npcm7xx_smp_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm7xx-smp", &npcm7xx_smp_ops);
--
2.15.0.448.gf294e3d99a-goog
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^ permalink raw reply related
* [PATCH v8 0/3] arm: npcm: add basic support for Nuvoton BMCs
From: Brendan Higgins @ 2017-11-17 19:07 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
mark.rutland-5wv7dgnIgG8, tmaimon77-Re5JQEeQqe8AvxtiuMwx3w,
avifishman70-Re5JQEeQqe8AvxtiuMwx3w,
raltherr-hpIqsD4AKlfQT0dZR+AlfA,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w, julien.thierry-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ
Addressed comments from:
- Rick (offline comments)
- Julien: https://www.spinics.net/lists/arm-kernel/msg613222.html
- Russell: https://www.spinics.net/lists/arm-kernel/msg613212.html
- Tomer: https://www.spinics.net/lists/arm-kernel/msg614059.html
- Rob: https://www.spinics.net/lists/arm-kernel/msg613355.html
- Tomer
Summary of changes since previous update:
- Arch support:
- Cleaned up L2C aux values
- Cleaned up memory barries
- Renamed CPU_NPCM750 to ARCH_NPCM750
- Other mostly cosmetic changes
- DTS:
- Added property to L2 cache
- More clean up
- No changes to MAINTAINERS since v5
Changes have been tested on the NPCM750 evaluation board.
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^ permalink raw reply
* Re: [PATCH v2] dt-bindings: mtd: Add sst25vf016b to the list of supported chip names
From: Marek Vasut @ 2017-11-17 19:01 UTC (permalink / raw)
To: Cyrille Pitchen, Fabrizio Castro, David Woodhouse, Brian Norris,
Boris Brezillon, Richard Weinberger, Rob Herring, Mark Rutland
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Chris Paterson,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Biju Das,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <658ceb2b-5d2b-9349-f140-27858459e5a8-yU5RGvR974pGWvitb5QawA@public.gmane.org>
On 11/17/2017 06:36 PM, Cyrille Pitchen wrote:
> Hi Fabrizio,
>
> sorry but I won't apply this patch.
ACK on that, if it can be detected with READID or SFDP, use that and
don't add redundant stuff into the DT bindings.
btw which renesas board has this SPI NOR on it ?
> New values for the 'compatible' DT properties should only be added for
> memory parts not supporting the JEDEC READ ID (0x9F) command.
>
> SST25 memories do support this command hence should use the "jedec,spi-nor"
> value alone. For historical reasons, some DT nodes set their 'compatible'
> string to something like "<vendor>,<model>", "jedec,spi-nor".
> It should work as expected in most case however I discourage from doing so
> in new device trees because it may have some side effects especially when
> the m25p80.c driver is used between the spi-nor.c driver and the SPI
> controller driver.
>
> It's all about setting the 2nd parameter of spi_nor_scan(), the 'name'
> parameter, as NULL when possible. This parameter should be set to a non NULL
> value only for memories not supporting the JEDEC READ ID op code (0x9F).
>
> Best regards,
>
> Cyrille
>
> Le 24/10/2017 à 15:50, Fabrizio Castro a écrit :
>> There are a few DT files that make use of sst25vf016b in their
>> compatible strings, and the driver supports this chip already.
>> This patch improves the documentation and therefore the result
>> of ./scripts/checkpatch.pl.
>>
>> Signed-off-by: Fabrizio Castro <fabrizio.castro-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
>> Signed-off-by: Chris Paterson <Chris.Paterson2-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
>> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Acked-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
>> ---
>> Thank you Rob, thank you Geert, and sorry for the delay on this one.
>> Here is v2.
>>
>> Changes in v2:
>> * fixed subject prefix
>> * added changelog
>>
>> Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
>> index 4cab5d8..bf56d77 100644
>> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
>> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
>> @@ -31,6 +31,7 @@ Required properties:
>> s25sl12801
>> s25fl008k
>> s25fl064k
>> + sst25vf016b
>> sst25vf040b
>> sst25wf040b
>> m25p40
>>
>
--
Best regards,
Marek Vasut
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^ permalink raw reply
* Re: [PATCH] ARM: dts: bcm2835-rpi: Avoid conflicts on i2c0
From: Dave Stevenson @ 2017-11-17 18:30 UTC (permalink / raw)
To: Eric Anholt
Cc: Stefan Wahren, Mark Rutland, Scott Branden, devicetree,
Rob Herring, linux-rpi-kernel, linux-arm-kernel
In-Reply-To: <87a7zmq7wy.fsf@anholt.net>
On 16 November 2017 at 20:34, Eric Anholt <eric@anholt.net> wrote:
> Stefan Wahren <stefan.wahren@i2se.com> writes:
>
>> The GPU firmware of the Raspberry Pi 3 uses i2c0 to communicate to
>> the FXL6408 gpio expander. It's a bad idea to use the same interface
>> from the ARM side. Since this interface isn't used by the other
>> RPi boards, it's save to remove the complete node and avoid this
>> conflict.
>
> It's not used by other kernel drivers currently, but should we leave it
> in for the pi0/1/2 folks that might have userspace I2C stuff using it?
> That's a thing people do, right? I actually don't know.
The firmware hasn't used BSC0 for the GPIO expander since the end of
January. It now bit bashes it. Sorry if that information hadn't
filtered through.
I've got a patch I was about to send to rpi-linux for comment which
sets up the i2c-mux-pinctrl driver on BSC0 so that it can be used
either on GPIOs 0&1, or the GPIOs connected to the DSI and CSI
connectors (I want it to talk to the camera module, and I guess Eric
won't complain for talking to the DSI display). I'll aim to sort it on
Monday.
Dave
^ permalink raw reply
* Re: [PATCH] dt-bindings: qspi: Add r8a7743/5 to the compatible list
From: Mark Brown @ 2017-11-17 18:08 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Rob Herring, Mark Rutland, Simon Horman, Chris Paterson, Biju Das,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Russell King,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <TY1PR06MB08958546062D685532669977C02F0@TY1PR06MB0895.apcprd06.prod.outlook.com>
[-- Attachment #1: Type: text/plain, Size: 1199 bytes --]
On Fri, Nov 17, 2017 at 06:00:46PM +0000, Fabrizio Castro wrote:
> this patch has been around for some time now, it was reviewed-by Geert Uytterhoeven and acked-by Rob Herring, any news?
Please don't send content free pings and please allow a reasonable time
for review. People get busy, go on holiday, attend conferences and so
on so unless there is some reason for urgency (like critical bug fixes)
please allow at least a couple of weeks for review. If there have been
review comments then people may be waiting for those to be addressed.
Sending content free pings adds to the mail volume (if they are seen at
all) which is often the problem and since they can't be reviewed
directly if something has gone wrong you'll have to resend the patches
anyway, though there are some other maintainers who like them - if in
doubt look at how patches for the subsystem are normally handled.
Please submit patches using subject lines reflecting the style for the
subsystem. This makes it easier for people to identify relevant
patches. Look at what existing commits in the area you're changing are
doing and make sure your subject lines visually resemble what they're
doing.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
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