* Re: [PATCH 0/2] Microchip mcp2517fd can controller driver
From: Wolfgang Grandegger @ 2017-11-26 19:05 UTC (permalink / raw)
To: kernel
Cc: Oliver Hartkopp, Marc Kleine-Budde, Rob Herring, Mark Rutland,
linux-can, devicetree
In-Reply-To: <CEE8AB99-2B26-44C0-A8D1-DD339DC9FEF7@martin.sperl.org>
Am 26.11.2017 um 19:29 schrieb kernel@martin.sperl.org:
>
>> On 26.11.2017, at 17:18, Wolfgang Grandegger <wg@grandegger.com> wrote:
>>
>> Hello Martin,
>>
>> Am 25.11.2017 um 15:47 schrieb kernel@martin.sperl.org:
>>
>> ...snip...
>>> I see the following counters:
>>> 7: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 16 qdisc pfifo_fast state UNKNOWN mode DEFAULT group default qlen 10
>>> link/can promiscuity 0
>>> can <ONE-SHOT,BERR-REPORTING> state ERROR-ACTIVE (berr-counter tx 0 rx 0) restart-ms 0
>>
>> Why do you use "ONE_SHOT" in all your test cases?
> I did test oneshot and non-oneshot - I just did not document them
> here, I am just mentioning the issue of dropped frames when the driver
> is submitting them correctly.
>
> Also - for what it is worse - the RX case would not be impacted by one-shot
> enabled or not.
>
>
>> Did you also check for out-of-order issues, e.g. by using "canfdtest”?
>
> As for out of order: yes I have taken extreme care that we do not
> get out of order packets for all possible cases testing with cangen - there
> may be one error case where there could be an out of order case in the
> tx path (unless we want to drop that frame - it would be a MAB case)
>
> But until now I did not know about canfdtest, but for all practical
> purposes it can not test for out-of-order delivery on a 100% saturated
> bus the way it is working - latencies are too big for that!
>
> Still for completeness a quick test from beagleboneblack to a
> RPI CM3 with a mcp2517fd gives:
> root@beaglebone:~/can-utils# ./canfdtest -g -vvv can0 -l 32
> interface = can0, family = 29, type = 3, proto = 1
> 0078: [8] 01 02 03 04 05 06 07 08
> 0078: [8] 02 03 04 05 06 07 08 09
> 0078: [8] 03 04 05 06 07 08 09 0a
> 0078: [8] 04 05 06 07 08 09 0a 0b
> 0078: [8] 05 06 07 08 09 0a 0b 0c
> 0078: [8] 06 07 08 09 0a 0b 0c 0d
> 0078: [8] 07 08 09 0a 0b 0c 0d 0e
> 0078: [8] 08 09 0a 0b 0c 0d 0e 0f
> 0078: [8] 09 0a 0b 0c 0d 0e 0f 10
> 0078: [8] 0a 0b 0c 0d 0e 0f 10 11
> 0078: [8] 0b 0c 0d 0e 0f 10 11 12
> 0078: [8] 0c 0d 0e 0f 10 11 12 13
> 0078: [8] 0d 0e 0f 10 11 12 13 14
> 0078: [8] 0e 0f 10 11 12 13 14 15
> 0078: [8] 0f 10 11 12 13 14 15 16
> 0078: [8] 10 11 12 13 14 15 16 17
> 0078: [8] 11 12 13 14 15 16 17 18
> 0078: [8] 12 13 14 15 16 17 18 19
> 0078: [8] 13 14 15 16 17 18 19 1a
> 0078: [8] 14 15 16 17 18 19 1a 1b
> 0078: [8] 15 16 17 18 19 1a 1b 1c
> 0078: [8] 16 17 18 19 1a 1b 1c 1d
> 0078: [8] 17 18 19 1a 1b 1c 1d 1e
> 0078: [8] 18 19 1a 1b 1c 1d 1e 1f
> 0078: [8] 19 1a 1b 1c 1d 1e 1f 20
> 0078: [8] 1a 1b 1c 1d 1e 1f 20 21
> 0078: [8] 1b 1c 1d 1e 1f 20 21 22
> 0078: [8] 1c 1d 1e 1f 20 21 22 23
> 0078: [8] 1d 1e 1f 20 21 22 23 24
> 0078: [8] 1e 1f 20 21 22 23 24 25
> 0078: [8] 1f 20 21 22 23 24 25 26
> 0078: [8] 20 21 22 23 24 25 26 27
>
> Test messages sent and received: 32
>
> (I can not go to longer tests because I may hit a bug I am just
> now trying to fix in the current code level).
This test does not load the bus a lot but uses burst of message to
trigger out-of-order issues. Please run the test without "-v" and much
longer.
> If you are interested in any more specific tests that I should
> be running, then please list those and I can report them
> when submitting V2 of the patch set.
Other useful test are about bus error reporting and error state changes.
Can bus errors been disabled via interrupt? I do not see that
CAN_CTRLMODE_BERR_REPORTING is handled. This means that bus error
reporting is always on which may put heavy load on the system. e.g if no
cable is connected and a message sent (at 1MB/s).
Concerning the error state changes, have a look to [1].
> Just to put everything into perspective:
> The equipment available to me is:
> * beagle bone black with c_can
> * raspberry pi 3 with mcp2515
> * raspberry pi CM3 with mcp2517fd
> * raspberry pi 2 with mcp2517fd
> * saleae logic analyzer
[1] https://marc.info/?l=linux-can&m=151147114323582&w=2
The driver has more than 3000 lines... a review will take some time.
Thanks for your contribution.
Wolfgang.
>
> Thanks,
> Martin--
> To unsubscribe from this list: send the line "unsubscribe linux-can" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
^ permalink raw reply
* Re: [PATCH 1/3] ASoC: stm32: fix sync property description in SAI bindings
From: Rob Herring @ 2017-11-26 19:05 UTC (permalink / raw)
To: Olivier Moysan
Cc: lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, broonie-DgEjT+Ai2ygdnm+yROfE0A,
perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w,
alexandre.torgue-qxv4g6HH51o, alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-F5mvAk5X5gdBDgjK7y7TUQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, arnaud.pouliquen-qxv4g6HH51o,
benjamin.gaignard-qxv4g6HH51o
In-Reply-To: <1511362947-14747-2-git-send-email-olivier.moysan-qxv4g6HH51o@public.gmane.org>
On Wed, Nov 22, 2017 at 04:02:25PM +0100, Olivier Moysan wrote:
> SAI sync property must be described in SAI subnodes
> section, as it is a property of child node.
> This patch fixes commit 14f0e5f8d97e632695d92f41f2e91d10d8005d47
> "ASoC: stm32: Add synchronization to SAI bindings".
>
> Signed-off-by: Olivier Moysan <olivier.moysan-qxv4g6HH51o@public.gmane.org>
> ---
> Documentation/devicetree/bindings/sound/st,stm32-sai.txt | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
--
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^ permalink raw reply
* Re: [PATCH 1/5] drm/panel: Add support for the EDT ETM0700G0BDH6
From: Rob Herring @ 2017-11-26 19:10 UTC (permalink / raw)
To: Jan Tuerk
Cc: Mark Rutland, Thierry Reding, David Airlie, Russell King,
Shawn Guo, Sascha Hauer, Fabio Estevam, Andreas Färber,
Kevin Hilman, Maxime Ripard, Alexandre Belloni,
Greg Kroah-Hartman, SZ Lin, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20171123125600.41562-2-jan.tuerk-BU0Y/NROKIhBDgjK7y7TUQ@public.gmane.org>
On Thu, Nov 23, 2017 at 01:55:51PM +0100, Jan Tuerk wrote:
> The Emerging Display Technology ETM0700G0BDH6 is exactly
> the same display as the ETM0700G0DH6, exept the pixelclock
> polarity. Therefore re-use the ETM0700G0DH6 modes. It is
> used by default on emtrion Avari based development kits.
>
> Signed-off-by: Jan Tuerk <jan.tuerk-BU0Y/NROKIhBDgjK7y7TUQ@public.gmane.org>
> ---
> .../bindings/display/panel/edt,etm0700g0bdh6.txt | 9 +++++++++
> drivers/gpu/drm/panel/panel-simple.c | 15 +++++++++++++++
> 2 files changed, 24 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt
>
> diff --git a/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt
> new file mode 100644
> index 000000000000..099e30bfa17f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt
> @@ -0,0 +1,9 @@
> +Emerging Display Technology Corp. ETM0700G0BDH6 7.0" WVGA TFT LCD panel
> +
> +Required properties:
> + compatible: "edt,etm0700g0bdh6"
> +
> +This panel is exactly the same as ETM0700G0DH6 except the pixelclock polarity.
Perhaps document them together.
> +
> +This binding is compatible with the simple-panel binding, which is specified
> +in simple-panel.txt in this directory.
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^ permalink raw reply
* Re: [PATCH 2/5] dt-bindings: Add vendor prefix for emtrion GmbH
From: Rob Herring @ 2017-11-26 19:12 UTC (permalink / raw)
To: Jan Tuerk
Cc: Mark Rutland, devicetree, SZ Lin, David Airlie, Kevin Hilman,
Russell King, dri-devel, linux-kernel, Thierry Reding,
Alexandre Belloni, Sascha Hauer, Greg Kroah-Hartman,
Fabio Estevam, Maxime Ripard, Shawn Guo, Andreas Färber,
linux-arm-kernel
In-Reply-To: <20171123125600.41562-3-jan.tuerk@emtrion.com>
On Thu, Nov 23, 2017 at 01:55:52PM +0100, Jan Tuerk wrote:
> emtrion is a system integrator and manufacturer of embedded systems.
>
> Website: https://www.emtrion.de
>
> Signed-off-by: Jan Tuerk <jan.tuerk@emtrion.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH 4/5] ARM: dts: Add support for emtrion emCON-MX6 series
From: Rob Herring @ 2017-11-26 19:24 UTC (permalink / raw)
To: Jan Tuerk
Cc: Mark Rutland, Thierry Reding, David Airlie, Russell King,
Shawn Guo, Sascha Hauer, Fabio Estevam, Andreas Färber,
Kevin Hilman, Geert Uytterhoeven, Alexandre Belloni, SZ Lin,
Greg Kroah-Hartman, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20171123125600.41562-5-jan.tuerk-BU0Y/NROKIhBDgjK7y7TUQ@public.gmane.org>
On Thu, Nov 23, 2017 at 01:55:54PM +0100, Jan Tuerk wrote:
> This patch adds support for the emtrion GmbH emCON-MX6 modules.
> They are available with imx.6 Solo, Dual-Lite, Dual and Quad
> equipped with Memory from 512MB to 2GB (configured by U-Boot).
>
> Our default developer-Kit ships with the Avari baseboard and the
> EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari).
>
> The devicetree is split into the common part providing all module
> components and the basic support for all SoC versions
> (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant.
> Finally the support for the avari baseboard in the developer-kit
> configuration is provided by the emcon-avari dts files.
>
> Signed-off-by: Jan Tuerk <jan.tuerk-BU0Y/NROKIhBDgjK7y7TUQ@public.gmane.org>
> ---
> Documentation/devicetree/bindings/arm/emtrion.txt | 13 +
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/imx6dl-emcon-avari.dts | 233 ++++++
> arch/arm/boot/dts/imx6dl-emcon.dtsi | 37 +
> arch/arm/boot/dts/imx6q-emcon-avari.dts | 233 ++++++
> arch/arm/boot/dts/imx6q-emcon.dtsi | 37 +
> arch/arm/boot/dts/imx6qdl-emcon.dtsi | 849 ++++++++++++++++++++++
> 7 files changed, 1404 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt
> create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts
> create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi
> create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts
> create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi
> create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt
> new file mode 100644
> index 000000000000..3ff6c6c2034d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/emtrion.txt
> @@ -0,0 +1,13 @@
> +Emtrion Devicetree Bindings
> +===========================
> +
> +emCON Series:
> +-------------
> +
> +Required root node properties
> + - compatible:
> + - "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; : emCON-MX6 Generic SoM
> + - "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM
> + - "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base
> + - "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM
> + - "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index d0381e9caf21..5ce643ece228 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -373,6 +373,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
> imx6dl-colibri-eval-v3.dtb \
> imx6dl-cubox-i.dtb \
> imx6dl-dfi-fs700-m60.dtb \
> + imx6dl-emcon-avari.dtb \
> imx6dl-gw51xx.dtb \
> imx6dl-gw52xx.dtb \
> imx6dl-gw53xx.dtb \
> @@ -424,6 +425,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
> imx6q-dfi-fs700-m60.dtb \
> imx6q-display5-tianma-tm070-1280x768.dtb \
> imx6q-dmo-edmqmx6.dtb \
> + imx6q-emcon-avari.dtb \
> imx6q-evi.dtb \
> imx6q-gk802.dtb \
> imx6q-gw51xx.dtb \
> diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts
> new file mode 100644
> index 000000000000..f8ca63258eda
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts
> @@ -0,0 +1,233 @@
> +/*
> + * Copyright (C) 2017 emtrion GmbH
> + * Author: Jan Tuerk <jan.tuerk-BU0Y/NROKIhBDgjK7y7TUQ@public.gmane.org>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + *
> + */
> +
> +/dts-v1/;
> +#include "imx6dl.dtsi"
> +#include "imx6qdl-emcon.dtsi"
> +#include "imx6dl-emcon.dtsi" /*Include camera2 pinmux*/
> +
> +/ {
> + model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari";
> + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl";
> +
> + aliases {
> + mmc0 = &usdhc3;
> + mmc2 = &usdhc1;
> + mmc1 = &usdhc2;
> + mmc3 = &usdhc4;
> + };
> +
> + chosen {
> + stdout-path = <&uart1>;
> + };
> +
> + memory {
> + reg = <0x10000000 0x40000000>;
> + };
> +
> + supplies {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + wallplug5p0: supply@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "WALL-PLUG";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + base3p3: supply@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + vin-supply = <&wallplug5p0>;
> + regulator-name = "3V3-avari";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + base1p5: supply@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + vin-supply = <&base3p3>;
> + regulator-name = "1V5-avari";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + reg_usb_otg: otgvbus {
> + compatible = "regulator-fixed";
> + reg = <3>;
> + vin-supply = <&wallplug5p0>;
> + regulator-name = "OTG_VBUS";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
> + regulator-always-on;
> + };
> +
> + };
> +
> +
> + sndosc: 12MHZosc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12000000>;
> + };
> +
> + sound {
> + compatible = "fsl,imx-audio-sgtl5000";
> + model = "emCON-avari-sgtl5000";
> + ssi-controller = <&ssi2>;
> + audio-codec = <&sgtl5000>;
> + audio-routing =
> + "Headphone Jack", "HP_OUT";
> + mux-int-port = <2>;
> + mux-ext-port = <3>;
> + };
> +
> +};
> +
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + /*Unused emCON-MX6 outputs on AVARI*/
> + pinctrl-0 = <
> + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2
> + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5
> + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7
> + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a
> + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c
> + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash
> + &pinctrl_usdhc2
> + &pinctrl_spdif_out &pinctrl_spdif_in
> + &pinctrl_cpi1 &pinctrl_cpi2
> + >;
> +};
> +
> +&audmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_audmux>;
> + status = "okay";
> +};
> +
> +
> +
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + status = "okay";
> +
> + sgtl5000: sgtl5000@0a {
audio-codec@a
same errors repeat below.
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + clocks = <&sndosc>;
> + VDDA-supply = <&base3p3>;
> + VDDIO-supply = <&base3p3>;
> + };
> +
> + boardID: pca8754a@3A {
...@3a
> + compatible = "nxp,pca8574";
> + reg = <0x3A>;
0x3a
> + gpio-controller;
> + #gpio-cells = <1>;
> + };
> +
> + captouch: edt-ft5x06@38 {
touchscreen@38
> + reg = <0x38>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>;
> + interrupt-parent = <&gpio6>;
> + interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
> + compatible = "edt,edt-ft5406";
> + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
> + wakeup-source;
> + };
> +};
> +
> +&ssi2 {
> + status = "okay";
> +};
> +
> +&rgb_encoder {
> + status = "okay";
> +};
> +
> +&rgb_panel {
> + compatible = "edt,etm0700g0bdh6";
> + status = "okay";
> +};
> +
> +&i2c2 {
> + status = "okay";
> +};
> +
> +&hdmi {
> + ddc-i2c-bus = <&i2c2>;
> + status = "okay";
> +};
> +
> +&usbh1 {
> + status = "okay";
> +};
> +
> +&usbotg {
> + status = "okay";
> +};
> +
> +&pcie {
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + status = "okay";
> +};
> +
> +&can1 {
> + status = "okay";
> +};
> +
> +&can2 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> + uart-has-rtscts;
> +};
> +
> +&uart3 {
> + status = "okay";
> +};
> +
> +&uart4 {
> + status = "okay";
> +};
> +
> +&uart5 {
> + status = "okay";
> +};
> +
> +&ecspi2 {
> + status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/imx6dl-emcon.dtsi b/arch/arm/boot/dts/imx6dl-emcon.dtsi
> new file mode 100644
> index 000000000000..47f43bae5ac5
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-emcon.dtsi
> @@ -0,0 +1,37 @@
> +/*
> + * Copyright (C) 2017 emtrion GmbH
> + * Author: Jan Tuerk <jan.tuerk-BU0Y/NROKIhBDgjK7y7TUQ@public.gmane.org>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + *
> + */
> +
> +/ {
> + model = "emtrion SoM emCON-MX6 Solo/DualLite";
> + compatible = "emtrion,emcon-mx6","fsl,imx6dl";
> +};
> +
> +&iomuxc {
> + pinctrl_cpi2: csi1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x0b0b1
> + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b1
> + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b1
> + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b1
> + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b1
> + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b1
> + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b1
> + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b1
> + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b1
> + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b1
> + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b1
> + >;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts
> new file mode 100644
> index 000000000000..bccfd6344c18
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts
> @@ -0,0 +1,233 @@
> +/*
> + * Copyright (C) 2017 emtrion GmbH
> + * Author: Jan Tuerk <jan.tuerk-BU0Y/NROKIhBDgjK7y7TUQ@public.gmane.org>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + *
> + */
> +
> +/dts-v1/;
> +#include "imx6q.dtsi"
> +#include "imx6qdl-emcon.dtsi"
> +#include "imx6q-emcon.dtsi" /*Include camera2 pinmux*/
> +
> +/ {
> + model = "emtrion SoM emCON-MX6 Dual/Quad on Avari";
> + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q";
> +
> + aliases {
> + mmc0 = &usdhc3;
> + mmc2 = &usdhc1;
> + mmc1 = &usdhc2;
> + mmc3 = &usdhc4;
> + };
> +
> + chosen {
> + stdout-path = <&uart1>;
> + };
> +
> + memory {
> + reg = <0x10000000 0x40000000>;
> + };
> +
> + supplies {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + wallplug5p0: supply@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "WALL-PLUG";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + base3p3: supply@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + vin-supply = <&wallplug5p0>;
> + regulator-name = "3V3-avari";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + base1p5: supply@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + vin-supply = <&base3p3>;
> + regulator-name = "1V5-avari";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + reg_usb_otg: otgvbus {
> + compatible = "regulator-fixed";
> + reg = <3>;
> + vin-supply = <&wallplug5p0>;
> + regulator-name = "OTG_VBUS";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
> + regulator-always-on;
> + };
> +
> + };
> +
> +
> + sndosc: 12MHZosc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12000000>;
> + };
> +
> + sound {
> + compatible = "fsl,imx-audio-sgtl5000";
> + model = "emCON-avari-sgtl5000";
> + ssi-controller = <&ssi2>;
> + audio-codec = <&sgtl5000>;
> + audio-routing =
> + "Headphone Jack", "HP_OUT";
> + mux-int-port = <2>;
> + mux-ext-port = <3>;
> + };
> +
> +};
> +
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + /*Unused emCON-MX6 pingroups on AVARI baseboard, enable defaults*/
> + pinctrl-0 = <
> + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2
> + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5
> + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7
> + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a
> + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c
> + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash
> + &pinctrl_usdhc2
> + &pinctrl_spdif_out &pinctrl_spdif_in
> + &pinctrl_cpi1 &pinctrl_cpi2
> + >;
> +};
> +
> +&audmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_audmux>;
> + status = "okay";
> +};
> +
> +
> +
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + status = "okay";
> +
> + sgtl5000: sgtl5000@0a {
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + clocks = <&sndosc>;
> + VDDA-supply = <&base3p3>;
> + VDDIO-supply = <&base3p3>;
> + };
> +
> + boardID: pca8754a@3A {
> + compatible = "nxp,pca8574";
> + reg = <0x3A>;
> + gpio-controller;
> + #gpio-cells = <1>;
> + };
> +
> + captouch: edt-ft5x06@38 {
> + reg = <0x38>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>;
> + interrupt-parent = <&gpio6>;
> + interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
> + compatible = "edt,edt-ft5406";
> + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
> + wakeup-source;
> + };
> +};
> +
> +&ssi2 {
> + status = "okay";
> +};
> +
> +&rgb_encoder {
> + status = "okay";
> +};
> +
> +&rgb_panel {
> + compatible = "edt,etm0700g0bdh6";
> + status = "okay";
> +};
> +
> +&i2c2 {
> + status = "okay";
> +};
> +
> +&hdmi {
> + ddc-i2c-bus = <&i2c2>;
> + status = "okay";
> +};
> +
> +&usbh1 {
> + status = "okay";
> +};
> +
> +&usbotg {
> + status = "okay";
> +};
> +
> +&pcie {
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + status = "okay";
> +};
> +
> +&can1 {
> + status = "okay";
> +};
> +
> +&can2 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> + uart-has-rtscts;
> +};
> +
> +&uart3 {
> + status = "okay";
> +};
> +
> +&uart4 {
> + status = "okay";
> +};
> +
> +&uart5 {
> + status = "okay";
> +};
> +
> +&ecspi2 {
> + status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-emcon.dtsi
> new file mode 100644
> index 000000000000..64fc0cd74c05
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi
> @@ -0,0 +1,37 @@
> +/*
> + * Copyright (C) 2017 emtrion GmbH
> + * Author: Jan Tuerk <jan.tuerk-BU0Y/NROKIhBDgjK7y7TUQ@public.gmane.org>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + *
> + */
> +
> +/ {
> + model = "emtrion SoM emCON-MX6 Dual/Quad";
> + compatible = "emtrion,emcon-mx6","fsl,imx6q";
> +};
> +
> +&iomuxc {
> + pinctrl_cpi2: csi1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x0b0b1
> + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b1
> + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b1
> + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b1
> + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b1
> + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b1
> + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b1
> + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b1
> + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b1
> + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b1
> + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b1
> + >;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi
> new file mode 100644
> index 000000000000..22ad05880ea7
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi
> @@ -0,0 +1,849 @@
> +/*
> + * Copyright (C) 2017 emtrion GmbH
> + * Author: Jan Tuerk <jan.tuerk-BU0Y/NROKIhBDgjK7y7TUQ@public.gmane.org>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + *
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pwm/pwm.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> +
> + model = "emtrion SoM emCON-MX6";
> + compatible = "emtrion,emcon-mx6","fsl,imx6q", "fsl,imx6dl";
> +
> + aliases {
> + mmc0 = &usdhc3;
> + mmc2 = &usdhc1;
> + mmc1 = &usdhc2;
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg_parallel_disp: regulator@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rgb_bl_en>;
> + regulator-name = "LCD-Supply";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_lvds_disp: regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "LVDS-Supply";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> + };
> +
> + som_leds: leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_som_leds>;
> +
> + green {
> + label = "som:green";
> + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + default-state = "on";
> + };
> +
> + red {
> + label = "som:red";
> + gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
> + default-state = "keep";
> + };
> +
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_emcon_wake>;
> +
> + wake {
> + label = "Wake";
> + linux,code = <KEY_WAKEUP>;
> + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> + };
> + };
> +
> + pwm_fan: pwm-fan {
> + compatible = "pwm-fan";
> + cooling-min-state = <0>;
> + cooling-max-state = <4>;
> + #cooling-cells = <2>;
> + pwms = <&pwm4 0 50000>;
> + cooling-levels = <0 64 127 191 255>;
> + status = "disabled";
> + };
> +
> + rgb_encoder: lcd@di0 {
> + compatible = "fsl,imx-parallel-display";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rgb24_display>;
> + status = "disabled";
> +
> + port@0 {
> + reg = <0>;
> + rgb_encoder_in: endpoint {
> + remote-endpoint = <&ipu1_di0_disp0>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + rgb_encoder_out: endpoint {
> + remote-endpoint = <&rgb_panel_in>;
> + };
> + };
> + };
> +
> + rgb_panel: panel {
> + backlight = <&rgb_backlight>;
> + power-supply = <®_prallel_disp>;
> + port {
> + rgb_panel_in: endpoint {
> + remote-endpoint = <&rgb_encoder_out>;
> + };
> + };
> + };
> +
> + rgb_backlight: rgb_backlight {
rgb-backlight {
> + compatible = "pwm-backlight";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rgb_bl>;
> + enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
> + pwms = <&pwm3 0 5000000>;
> + brightness-levels = <250 176 160 144 128 112
> + 96 80 64 48 32 16 8 1
> + >;
> + default-brightness-level = <13>;
> + status = "okay";
> + };
> +
> + lvds_backlight: lvds_backlight {
lvds-backlight {
> + compatible = "pwm-backlight";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lvds_bl>;
> + enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
> + pwms = <&pwm1 0 50000>;
> + brightness-levels = <0 4 8 16 32 64 80 96 112
> + 128 144 160 176 250
> + >;
> + default-brightness-level = <13>;
> + status = "okay";
> + };
> +};
> +
> +
> +&iomuxc {
> +
> + pinctrl_secure: securegrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
> + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
> + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
> + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
> + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart5: uart5grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
> + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_emcon_gpio1: emcongpio1 {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1
> + >;
> + };
> +
> + pinctrl_emcon_gpio2: emcongpio2 {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1
> + >;
> + };
> +
> + pinctrl_emcon_gpio3: emcongpio3 {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1
> + >;
> + };
> +
> + pinctrl_emcon_gpio4: emcongpio4 {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1
> + >;
> + };
> +
> + pinctrl_emcon_gpio5: emcongpio5 {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1
> + >;
> + };
> +
> + pinctrl_emcon_gpio6: emcongpio6 {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1
> + >;
> + };
> +
> + pinctrl_emcon_gpio7: emcongpio7 {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1
> + >;
> + };
> +
> + pinctrl_emcon_gpio8: emcongpio8 {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1
> + >;
> + };
> +
> + pinctrl_emcon_irq_a: emconirqa {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1
> + >;
> + };
> +
> + pinctrl_emcon_irq_b: emconirqb {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1
> + >;
> + };
> +
> + pinctrl_emcon_irq_c: emconirqc {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1
> + >;
> + };
> +
> + pinctrl_emcon_wake: emconwake {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1
> + >;
> + };
> +
> + pinctrl_emcon_irq_pwr: emconirqpwr {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1
> + >;
> + };
> +
> + pinctrl_som_leds: somledgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1
> + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1
> + >;
> + };
> +
> + pinctrl_nor_flash: norflashgrp {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1
> + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
> + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
> + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
> + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
> + >;
> + };
> +
> + pinctrl_ecspi2: ecspi2grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
> + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
> + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1
> + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
> + >;
> + };
> +
> + pinctrl_pwm_fan: pwmfan {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1
> + >;
> + };
> +
> + pinctrl_can1: can1grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
> + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
> + >;
> + };
> +
> + pinctrl_can2: can2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1
> + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1
> + >;
> + };
> +
> + pinctrl_spdif_out: spdifout {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091
> + >;
> + };
> +
> + pinctrl_spdif_in: spdifin {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
> + >;
> + };
> +
> + pinctrl_cpi1: csi0grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
> + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1
> + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1
> + >;
> + };
> +
> + /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/
> +
> + pinctrl_pcie_ctrl: pciegrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1
> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1
> + >;
> + };
> +
> + pinctrl_audmux: audmux {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
> + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060
> + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0
> + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
> + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070
> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870
> + >;
> + };
> +
> + pinctrl_pmic: pmicgrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1
> + >;
> + };
> +
> + pinctrl_usb_host1: usbhgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058
> + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058
> + >;
> + };
> +
> + pinctrl_usb_otg: usbotggrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059
> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059
> + >;
> + };
> +
> + pinctrl_lvds_reg: lvdsreggrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1
> + >;
> + };
> +
> + pinctrl_lvds_bl: lvdsbacklightgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1
> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1
> + >;
> + };
> +
> + pinctrl_irq_touch1: irqtouch1 {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1
> + >;
> + };
> +
> + pinctrl_rgb_bl_en: rgbenable {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1
> + >;
> + };
> +
> + pinctrl_irq_touch2: irqtouch2 {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1
> + >;
> + };
> +
> + pinctrl_rgb_bl: rgbbacklightgrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1
> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1
> + >;
> + };
> +
> + pinctrl_rgb24_display: rgbgrp {
> + fsl,pins = <
> + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
> + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
> + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
> + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
> + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
> + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
> + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
> + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
> + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
> + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
> + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
> + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
> + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
> + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
> + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
> + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
> + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
> + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
> + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
> + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
> + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
> + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
> + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
> + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
> + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
> + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
> + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
> + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
> + >;
> + };
> +
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058
> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
> + >;
> + };
> +
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
> + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
> + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
> + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
> + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
> + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
> + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1
> + MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
> + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1
> + MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1
> + >;
> + };
> +
> +};
> +
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + rtc: rtc@68 {
> + compatible = "dallas,ds1307";
> + reg = <0x68>;
> + };
> +
> + da9063: da9063@58 {
pmic@38
> + compatible = "dlg,da9063";
> + reg = <0x58>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> + interrupt-parent = <&gpio2>;
> + interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-controller;
> +
> + onkey {
> + wakeup-source;
> + compatible = "dlg,da9063-onkey";
> + };
> +
> + wdt {
> + compatible = "dlg,da9063-watchdog";
> + timeout-sec = <0>;
> + };
> +
> + regulators {
> + vddcore_reg: bcore1 {
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1450000>;
> + regulator-ramp-delay = <20000>;
> + regulator-name = "DA9063_CORE";
> + regulator-always-on;
> + };
> +
> + vddsoc_reg: bcore2 {
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1450000>;
> + regulator-ramp-delay = <20000>;
> + regulator-name = "DA9063_SOC";
> + regulator-always-on;
> + };
> +
> + vdd_ddr3_reg: bpro {
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-ramp-delay = <20000>;
> + regulator-always-on;
> + };
> +
> + vdd_3v3_reg: bperi {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-ramp-delay = <20000>;
> + regulator-always-on;
> + };
> +
> + vdd_sata_reg: ldo3 {
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-always-on;
> + };
> + vdd_mipi_reg: ldo4 {
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-always-on;
> + };
> +
> + vdd_mx6_snvs_reg: ldo5 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vdd_hdmi_reg: ldo6 {
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_pcie_reg: ldo7 {
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-always-on;
> + };
> +
> + vdd_1V8_reg: ldo8 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + vdd_3V3_sdc_reg: ldo9 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vdd_1V2_reg: ldo10 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> +};
> +
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>;
> +};
> +
> +&uart5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart5>;
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-mode = "rgmii";
> + phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
> + phy-reset-duration = <50>;
> + phy-supply = <&vdd_1V8_reg>;
> + phy-handle = <&ksz9031>;
> + status = "okay";
> +
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ksz9031: phy {
phy@0
Building with W=2 or W=1 will tell you this.
> + reg = <0>;
> + compatible = "ethernet-phy-ieee802.3-c22";
> + interrupt-parent = <&gpio1>;
> + interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
> + rxdv-skew-ps = <480>;
> + txen-skew-ps = <480>;
> + rxd0-skew-ps = <480>;
> + rxd1-skew-ps = <480>;
> + rxd2-skew-ps = <480>;
> + rxd3-skew-ps = <480>;
> + txd0-skew-ps = <420>;
> + txd1-skew-ps = <420>;
> + txd2-skew-ps = <360>;
> + txd3-skew-ps = <360>;
> + txc-skew-ps = <1020>;
> + rxc-skew-ps = <960>;
> + };
> + };
> +};
> +
> +
> +&usdhc3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + non-removable;
> + bus-width = <8>;
> + status = "okay";
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie_ctrl>;
> + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
> + disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>;
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + fsl,wp-controller;
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + fsl,wp-controller;
> +};
> +
> +
> +&ipu1_di0_disp0 {
> + remote-endpoint = <&rgb_encoder_in>;
> +};
> +
> +&pwm1 {
> + status = "okay";
> +};
> +
> +&pwm3 {
> + status = "okay";
> +};
> +
> +&pwm4 {
> + status = "okay";
> +};
> +
> +&ecspi2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi2>;
> + cs-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>,
> + <&gpio2 26 GPIO_ACTIVE_HIGH>;
> +};
> +
> +&ecspi4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_nor_flash>;
> +};
> +
> +&can1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_can1>;
> +};
> +
> +&can2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_can2>;
> +};
> +
> +&usbh1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb_host1>;
> +};
> +
> +&usbotg {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb_otg>;
> + vbus-supply = <®_usb_otg>;
> + dr_mode = "peripheral";
> +};
> +
> +/******device power Management*********/
> +
> +&cpu0 {
> + voltage-tolerance = <2>;
> +};
> +
> +®_arm {
> + vin-supply = <&vddcore_reg>;
> +};
> +
> +®_soc {
> + vin-supply = <&vddsoc_reg>;
> +};
> +
> +®_pu {
> + vin-supply = <&vddsoc_reg>;
> +};
> +
> +
> +
> +/*******Disabled HW following***********/
> +
> +
> +&weim {
> + status = "disabled";
> +};
> +
> +&snvs_rtc {
> + status = "disabled";
> +};
> +
> --
> 2.11.0
>
>
> emtrion GmbH
> Kreativpark - Alter Schlachthof 45
> 76131 Karlsruhe
> GERMANY
> http://www.emtrion.de
> _______________________________________
>
> Amtsgericht Mannheim
> HRB 110 300
> Gesch?ftsf?hrer: Dieter Baur, Ramona Maurer
> _______________________________________
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^ permalink raw reply
* Re: [PATCH 2/5] dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe host controller
From: Rob Herring @ 2017-11-26 19:32 UTC (permalink / raw)
To: Cyrille Pitchen
Cc: bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, kishon-l0cyMroinI0,
lorenzo.pieralisi-5wv7dgnIgG8, linux-pci-u79uwXL29TY76Z2rM5mHXA,
adouglas-vna1KIf7WgpBDgjK7y7TUQ, stelford-vna1KIf7WgpBDgjK7y7TUQ,
dgary-vna1KIf7WgpBDgjK7y7TUQ, kgopi-vna1KIf7WgpBDgjK7y7TUQ,
eandrews-vna1KIf7WgpBDgjK7y7TUQ,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
sureshp-vna1KIf7WgpBDgjK7y7TUQ, nsekhar-l0cyMroinI0,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <895cbb8f862c712b78f780a53e05d5429d24cc35.1511439189.git.cyrille.pitchen-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Thu, Nov 23, 2017 at 04:01:47PM +0100, Cyrille Pitchen wrote:
> From: Scott Telford <stelford-vna1KIf7WgpBDgjK7y7TUQ@public.gmane.org>
>
> This patch adds documentation for the DT bindings of the Cadence PCIe
> controller when configured in host (Root Complex) mode.
>
> Signed-off-by: Scott Telford <stelford-vna1KIf7WgpBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Cyrille Pitchen <cyrille.pitchen-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>
> dt-bindings: PCI: cadence: host fixup
> ---
> .../bindings/pci/cdns,cdns-pcie-host.txt | 54 ++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
A few nits, otherwise:
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>
> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
> new file mode 100644
> index 000000000000..4b3df8ffd5e1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
> @@ -0,0 +1,54 @@
> +* Cadence PCIe host controller
> +
> +This PCIe controller inherits the base properties defined in
> +host-generic-pci.txt.
> +
> +Required properties:
> +- compatible: should contain "cdns,cdns-pcie-host" to identify the IP used.
> +- reg: Should contain the PCIe configuration window base address, controller
> + register base address, and AXI interface region base address respectively.
> +- reg-names: Must be "cfg", "reg" and "mem" respectively.
> +- #address-cells: set to <3>
> +- #size-cells: set to <2>
> +- device_type: set to "pci"
> +- ranges: ranges for the PCI memory and I/O regions
> +- #interrupt-cells: set to <1>
> +- interrupt-map-mask and interrupt-map: standard PCI
> + properties to define the mapping of the PCIe interface to interrupt
> + numbers.
> +
> +Example:
> +
> + pci@fb000000 {
pcie@...
Usually the first address is the unit-address, so either change the
order in reg or change this.
> + compatible = "cdns,cdns-pcie-host";
> + device_type = "pci";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x0 0xff>;
> + linux,pci-domain = <0>;
> +
> + // CPU_PHYSICAL(2) SIZE(2)
Drop the comment. If you know what 'reg' is then it is obvious. Also,
don't use C++ style comments.
> + reg = <0x0 0x41000000 0x0 0x00001000>, /* Config space */
> + <0x0 0xfb000000 0x0 0x01000000>, /* Base Address */
> + <0x0 0x40000000 0x0 0x04000000>; /* AXI region */
> + reg-names = "cfg", "reg", "mem";
> +
> + // BUS_ADDRESS(3) CPU_PHYSICAL(1) SIZE(2)
ditto
> + ranges =
> + <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
> + <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
> +
> +
> + #interrupt-cells = <0x1>;
> +
> + // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(5)
> + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1
> + 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1
> + 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1
> + 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>;
> +
> + // PCI_DEVICE(3) INT#(1)
> + interrupt-map-mask = <0x0000 0x0 0x0 0x7>;
> +
> + msi-parent = <&its_pci>;
> + };
> --
> 2.11.0
>
> --
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^ permalink raw reply
* Re: [PATCH 4/5] dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe endpoint controller
From: Rob Herring @ 2017-11-26 19:33 UTC (permalink / raw)
To: Cyrille Pitchen
Cc: bhelgaas, kishon, lorenzo.pieralisi, linux-pci, adouglas,
stelford, dgary, kgopi, eandrews, thomas.petazzoni, sureshp,
nsekhar, linux-kernel, devicetree
In-Reply-To: <0a11e9742db04fd5b4bc08568b3ab5a056a0ef9d.1511439189.git.cyrille.pitchen@free-electrons.com>
On Thu, Nov 23, 2017 at 04:01:49PM +0100, Cyrille Pitchen wrote:
> This patch documents the DT bindings for the Cadence PCIe controller
> when configured in endpoint mode.
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
> ---
> .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v8 2/2] ARM: dts: TS-4600: add basic device tree
From: Fabio Estevam @ 2017-11-26 19:39 UTC (permalink / raw)
To: Sebastien Bourdelin
Cc: linux-kernel, kernel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Fabio Estevam, Sascha Hauer, Shawn Guo,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Mark Rutland,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, Mark Featherston,
kris-L1vi/lXTdtvnC/t2CciAbw
In-Reply-To: <20171123210410.7107-2-sebastien.bourdelin-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org>
Hi Sebastien,
On Thu, Nov 23, 2017 at 7:04 PM, Sebastien Bourdelin
<sebastien.bourdelin-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org> wrote:
> + reg_vddio_sd0: regulator-vddio-sd0 {
> + compatible = "regulator-fixed";
> + regulator-name = "vddio-sd0";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
It seems this should be GPIO_ACTIVE_LOW instead, as you don't pass
'enable-active-high' here.
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^ permalink raw reply
* Re: [PATCH 0/2] Microchip mcp2517fd can controller driver
From: kernel @ 2017-11-26 19:53 UTC (permalink / raw)
To: Wolfgang Grandegger
Cc: Oliver Hartkopp, Marc Kleine-Budde, Rob Herring, Mark Rutland,
linux-can, devicetree
In-Reply-To: <3b1c4778-b155-7aaf-e5b4-14061e687161@grandegger.com>
Hi Wolfgang!
> On 26.11.2017, at 20:05, Wolfgang Grandegger <wg@grandegger.com> wrote:
>> Test messages sent and received: 32
>> (I can not go to longer tests because I may hit a bug I am just
>> now trying to fix in the current code level).
>
> This test does not load the bus a lot but uses burst of message to trigger out-of-order issues. Please run the test without "-v" and much longer.
I agree, but as mentioned: I am debugging something else, which makes the
system slightly unstable, so I refrained from running longer tests...
>> If you are interested in any more specific tests that I should
>> be running, then please list those and I can report them
>> when submitting V2 of the patch set.
>
> Other useful test are about bus error reporting and error state changes.
>
> Can bus errors been disabled via interrupt? I do not see that CAN_CTRLMODE_BERR_REPORTING is handled. This means that bus error reporting is always on which may put heavy load on the system. e.g if no cable is connected and a message sent (at 1MB/s).
>
> Concerning the error state changes, have a look to [1].
Yes - it comes with the 9 (32-bit) register read on every interrupt.
This is actually an optimization to avoid kernel latencies that would
occur when reading 3 sets of registers separately.
Also longer reads means a higher likleyhood that DMA will be used
by the spi-controller/driver.
>
>> Just to put everything into perspective:
>> The equipment available to me is:
>> * beagle bone black with c_can
>> * raspberry pi 3 with mcp2515
>> * raspberry pi CM3 with mcp2517fd
>> * raspberry pi 2 with mcp2517fd
>> * saleae logic analyzer
>
> [1] https://marc.info/?l=linux-can&m=151147114323582&w=2
>
I will try to run those and add them to the cover page for V2.
> The driver has more than 3000 lines... a review will take some time.
Please look mostly at the device-tree and the main comments about the
rationale and performance optimizations at first.
Feedback on these I could include with V2 of the patch that will
fix also the above mentioned errors and MAB avoidance code.
I should be able to post it later this week.
Thanks,
Martin
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: hwrng: Add Samsung Exynos 5250+ True RNG bindings
From: Rob Herring @ 2017-11-26 22:07 UTC (permalink / raw)
To: Łukasz Stelmach
Cc: Matt Mackall, Herbert Xu, Krzysztof Kozlowski, devicetree,
linux-crypto, linux-samsung-soc, linux-kernel, Marek Szyprowski,
Bartlomiej Zolnierkiewicz
In-Reply-To: <20171123150914.31462-2-l.stelmach@samsung.com>
On Thu, Nov 23, 2017 at 04:09:12PM +0100, Łukasz Stelmach wrote:
> Add binding documentation for the True Random Number Generator
> found on Samsung Exynos 5250+ SoCs.
>
> Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
> ---
> .../devicetree/bindings/rng/samsung,exynos5250-trng.txt | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 05/11] dt-bindings: Document the Rockchip ISP1 bindings
From: Rob Herring @ 2017-11-26 22:14 UTC (permalink / raw)
To: Jacob Chen
Cc: linux-rockchip, linux-kernel, linux-arm-kernel, mchehab,
linux-media, sakari.ailus, hans.verkuil, tfiga, zhengsq,
laurent.pinchart, zyc, eddie.cai.linux, jeffy.chen, allon.huang,
devicetree, heiko, Jacob Chen
In-Reply-To: <20171124023706.5702-6-jacob-chen@iotwrt.com>
On Fri, Nov 24, 2017 at 10:37:00AM +0800, Jacob Chen wrote:
> From: Jacob Chen <jacob2.chen@rock-chips.com>
>
> Add DT bindings documentation for Rockchip ISP1
>
> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
> ---
> .../devicetree/bindings/media/rockchip-isp1.txt | 61 ++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/rockchip-isp1.txt
>
> diff --git a/Documentation/devicetree/bindings/media/rockchip-isp1.txt b/Documentation/devicetree/bindings/media/rockchip-isp1.txt
> new file mode 100644
> index 000000000000..5e5b72edcf81
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/rockchip-isp1.txt
> @@ -0,0 +1,61 @@
> +Rockchip SoC Image Signal Processing unit v1
> +----------------------------------------------
> +
> +Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
> +which contains image processing, scaling, and compression funcitons.
> +
> +Currently device tree nodes for the Rockchip ISP1 driver includes:
Bindings describe the h/w, not drivers.
> +MIPI D-PHY, ISP.
> +
> +Required properties:
> + - compatible: value should be one of the following
> + "rockchip,rk3288-cif-isp";
> + "rockchip,rk3399-cif-isp";
> + - reg : offset and length of the register set for the device.
> + - interrupts: should contain ISP interrupt.
> + - clocks: phandle to the required clocks.
> + - clock-names: required clock name.
> + - iommus: required a iommu node.
> +
> +The device node should contain one 'port' child node with child 'endpoint'
> +nodes, according to the bindings defined in Documentation/devicetree/bindings/
> +media/video-interfaces.txt.
You need to enumerate the endpoints (mipi and parallel), too.
> +
> +Example:
> +SoC-specific DT entry:
> + isp0: isp0@ff910000 {
> + compatible = "rockchip,rk3399-cif-isp";
> + reg = <0x0 0xff910000 0x0 0x4000>;
> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru SCLK_ISP0>,
> + <&cru ACLK_ISP0>, <&cru ACLK_ISP0_WRAPPER>,
> + <&cru HCLK_ISP0>, <&cru HCLK_ISP0_WRAPPER>;
> + clock-names = "clk_isp",
> + "aclk_isp", "aclk_isp_wrap",
> + "hclk_isp", "hclk_isp_wrap";
> + power-domains = <&power RK3399_PD_ISP0>;
> + iommus = <&isp0_mmu>;
> + status = "disabled";
> + };
> +
> +Board-specific:
Just show the complete example. The SoC and board split is purely source
level convention.
> + isp0: isp0@ff910000 {
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* mipi */
> + isp0_mipi_in: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&dphy_rx0_out>;
> + };
> +
> + /* parallel */
> + isp0_parallel_in: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&ov5640_out>;
> + };
> + };
> + };
> +
> +The MIPI-DPHY device binding is defined in rockchip-mipi-dphy.txt.
> --
> 2.15.0
>
^ permalink raw reply
* Re: [PATCH v2 06/11] dt-bindings: Document the Rockchip MIPI RX D-PHY bindings
From: Rob Herring @ 2017-11-26 22:16 UTC (permalink / raw)
To: Jacob Chen
Cc: linux-rockchip, linux-kernel, linux-arm-kernel, mchehab,
linux-media, sakari.ailus, hans.verkuil, tfiga, zhengsq,
laurent.pinchart, zyc, eddie.cai.linux, jeffy.chen, allon.huang,
devicetree, heiko, Jacob Chen
In-Reply-To: <20171124023706.5702-7-jacob-chen@iotwrt.com>
On Fri, Nov 24, 2017 at 10:37:01AM +0800, Jacob Chen wrote:
> Add DT bindings documentation for Rockchip MIPI D-PHY RX
>
> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
> ---
> .../bindings/media/rockchip-mipi-dphy.txt | 77 ++++++++++++++++++++++
> 1 file changed, 77 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt
Same comments apply to this one.
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: clocksource: Add Spreadtrum SC9860 timer
From: Rob Herring @ 2017-11-26 22:17 UTC (permalink / raw)
To: Baolin Wang
Cc: daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
tglx-hfZtesqFncYOwBW4kG4KsQ, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
broonie-DgEjT+Ai2ygdnm+yROfE0A,
baolin.wang-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <2aaad500b5faf51c55fc6f0ad361d9078a521db8.1511501514.git.baolin.wang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
On Fri, Nov 24, 2017 at 01:37:47PM +0800, Baolin Wang wrote:
> This patch adds documentation of device tree bindings for the timers
> found on Spreadtrum SC9860 platform.
>
> Signed-off-by: Baolin Wang <baolin.wang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
> ---
> .../bindings/timer/spreadtrum,sprd-timer.txt | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v4 3/6] Documentation : can : flexcan : Add big-endian property to device tree
From: Rob Herring @ 2017-11-26 22:18 UTC (permalink / raw)
To: Pankaj Bansal
Cc: wg-5Yr1BZd7O62+XT7JhA+gdA, mkl-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-can-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA, V.Sethi-3arQi8VN3Tc,
poonam.aggrwal-3arQi8VN3Tc
In-Reply-To: <1511529733-27942-4-git-send-email-pankaj.bansal-3arQi8VN3Tc@public.gmane.org>
On Fri, Nov 24, 2017 at 06:52:10PM +0530, Pankaj Bansal wrote:
> The FlexCAN controller can be modelled as little or big endian depending
> on SOC design. This device tree property identifies the controller
> endianness and the driver reads/writes controller registers based on
> that.
>
> This is optional property. i.e. if this property is not present in
> device tree node then controller is assumed to be little endian. if this
> property is present then controller is assumed to be big endian.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal-3arQi8VN3Tc@public.gmane.org>
> Reviewed-by: Poonam Aggrwal <poonam.aggrwal-3arQi8VN3Tc@public.gmane.org>
> ---
> Changes in v4:
> - document the default behaviour in the bindings if the big-endian property
> is missing.
> - Merged device tree changes and driver changes in one series
> Changes in v3:
> - No change.
> Changes in v2:
> - No change.
> - Added one more patch in series.
>
> Documentation/devicetree/bindings/net/can/fsl-flexcan.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [RFC v1 5/8] Bluetooth: btrtl: add support for the RTL8723BS and RTL8723DS chips
From: Martin Blumenstingl @ 2017-11-26 22:23 UTC (permalink / raw)
To: Marcel Holtmann
Cc: Rob Herring, devicetree, open list:BLUETOOTH DRIVERS,
linux-serial-u79uwXL29TY76Z2rM5mHXA, Mark Rutland,
Gustavo F. Padovan, Johan Hedberg, Greg Kroah-Hartman, Jiri Slaby,
Johan Hovold, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Larry.Finger-tQ5ms3gMjBLk1uMJSBkQmQ
In-Reply-To: <4B23C5B4-DCB8-4B1C-B1BF-A99B1E5E10B0-kz+m5ild9QBg9hUCZPvPmw@public.gmane.org>
Hi Marcel,
On Sun, Nov 19, 2017 at 10:17 PM, Marcel Holtmann <marcel-kz+m5ild9QBg9hUCZPvPmw@public.gmane.org> wrote:
> Hi Martin,
>
>>>> The Realtek RTL8723BS and RTL8723DS chipsets are SDIO wifi chips. They
>>>> also contain a Bluetooth module which is connected via UART to the host.
>>>>
>>>> Realtek's userspace initialization tool (rtk_hciattach) differentiates
>>>> these two via the HCI version and revision returned by the
>>>> HCI_OP_READ_LOCAL_VERSION command.
>>>> Additionally we apply these checks only the for UART devices. Everything
>>>> else is assumed to be a "RTL8723B" which was originally supported by the
>>>> driver (communicating via USB).
>>>>
>>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>>>> ---
>>>> drivers/bluetooth/btrtl.c | 32 ++++++++++++++++++++++++++++++--
>>>> 1 file changed, 30 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c
>>>> index 45b872f5ad22..d896f9421250 100644
>>>> --- a/drivers/bluetooth/btrtl.c
>>>> +++ b/drivers/bluetooth/btrtl.c
>>>> @@ -418,9 +418,33 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev)
>>>> has_rom_version = false;
>>>> break;
>>>> case RTL_ROM_LMP_8723B:
>>>> - fw_name = "rtl_bt/rtl8723b_fw.bin";
>>>> - cfg_name = "rtl_bt/rtl8723b_config.bin";
>>>> + /* all variants support reading the ROM version */
>>>> has_rom_version = true;
>>>> +
>>>> + /*
>>>> + * RTL8723 devices exist in different variants:
>>>> + * - RTL8723BS (SDIO chip with UART Bluetooth)
>>>> + * - RTL8723DS (SDIO chip with UART Bluetooth)
>>>> + * - for backwards-compatibility everything else is assumed to
>>>> + * be an RTL8723B communicating over USB
>>>> + *
>>>> + * Only UART devices really need the config because that
>>>> + * contains the UART speed / flow control settings.
>>>> + */
>>>> + if (hdev->bus == HCI_UART && resp->hci_ver == 6 &&
>>>> + le16_to_cpu(resp->hci_rev) == 0xb) {
>>>> + fw_name = "rtl_bt/rtl8723bs_fw.bin";
>>>> + cfg_name = "rtl_bt/rtl8723bs_config.bin";
>>>> + cfg_needed = true;
>>>> + } else if (hdev->bus == HCI_UART && resp->hci_ver == 8 &&
>>>> + le16_to_cpu(resp->hci_rev) == 0xd) {
>>>> + fw_name = "rtl_bt/rtl8723ds_fw.bin";
>>>> + cfg_name = "rtl_bt/rtl872ds_config.bin";
>>>> + cfg_needed = true;
>>>> + } else {
>>>> + fw_name = "rtl_bt/rtl8723b_fw.bin";
>>>> + cfg_name = "rtl_bt/rtl8723b_config.bin";
>>>> + }
>>>
>>> so the main question is why is this a config file in the first place? So far all other drivers have expressed UART settings via DT (or even via ACPI). If we are just getting the baudrates, then better have this in DT. Since otherwise we end up with board specific filesystems again where different config files need to be installed. That is really not useful in the end.
>> this is an excellent question (and also the reason why it's an "RFC" patch)!
>> I'll try to figure out whether:
>> a) we can skip the config file completely
skipping the config blob causes it to time out at the end of the
firmware download (where the config seems to be applied internally)
>> b) we can generate the config file in-memory
I tried this as well with a very minimal version (where only the
"known" bits are used)
unfortunately this shows the same symptoms as skipping the config blob
I'll try experimenting with this to see if I can get it to work somehow
>> c) we have to stick with this config file
I'm afraid this would be our last option if I can't get b) working
a datasheet for these chips or some advice from someone who has access
to the datasheet/knowledge about the internals would be of great help
>>
>>> What is actually in these config files? Can we have some parsing and friendly display tool in bluez.git like we have for other manufactures.
>> to my knowledge this config file contains:
>> - the baudrate
>> - whether flow control is enabled or disabled
>
> these two are better done as part of the DT.
agreed, I'd also rather have this in DT than some blob
>> - (in some cases) the local-bd-address
>
> There is essentially DT support for that as well, but we also have Set Public Address mgmt command to handle this. Then again, first of all the hdev->set_bdaddr callback needs to be supported for that.
>
>> do you mean a tool that is similar to bluez.git tools/nokfw.c?
>
> Yes.
>
>> [0] https://github.com/NextThingCo/rtl8723ds_bt/blob/f56ef37217665070e574253d23a595ee1ca5ca23/rtk_hciattach/hciattach_rtk.c#L1781
>
> Please never ever make me look at code that defined struct sk_buff in userspace ;)
sorry for not putting a huge warning/disclaimer in front of that link!
as bad as it sounds: this is all I have as reference :(
Regards
Martin
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^ permalink raw reply
* Re: [PATCH 1/2] dt-binding: can: mcp2517fd: document device tree bindings
From: Rob Herring @ 2017-11-26 22:28 UTC (permalink / raw)
To: kernel-TqfNSX0MhmxHKSADF0wUEw
Cc: Wolfgang Grandegger, Marc Kleine-Budde, Mark Rutland,
linux-can-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171124183509.12810-2-kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
On Fri, Nov 24, 2017 at 06:35:08PM +0000, kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org wrote:
> From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
>
> Add device-tree bindings for Microcip CanFD Controller mcp2517fd
s/Microcip/Microchip/
>
> Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
> ---
> .../bindings/net/can/microchip,mcp2517fd.txt | 47 ++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/can/microchip,mcp2517fd.txt
>
> diff --git a/Documentation/devicetree/bindings/net/can/microchip,mcp2517fd.txt b/Documentation/devicetree/bindings/net/can/microchip,mcp2517fd.txt
> new file mode 100644
> index 000000000000..96cbf0c96895
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/can/microchip,mcp2517fd.txt
> @@ -0,0 +1,47 @@
> +* Microchip MCP2517 stand-alone CAN controller device tree bindings
> +
> +Required properties:
> + - compatible: Should be one of the following:
> + - "microchip,mcp2517fd" for MCP2517fd.
> + - reg: SPI chip select.
> + - clocks: The clock feeding the CAN controller.
> + - interrupt-parent: The parent interrupt controller.
> + - interrupts: Should contain IRQ line for the CAN controller.
> +
> +Optional properties:
> + - vdd-supply: Regulator that powers the CAN controller.
> + - xceiver-supply: Regulator that powers the CAN transceiver.
> + - microchip,clock_out_div = <0|1|2|4|10>: Clock output pin divider
s/_/-/
And on the rest. Don't use underscores...
> + 0 = Start of Frame output
> + default: 10
> + - microchip,clock_div = <1|2>: internal clock divider - default 1
> + - microchip,gpio_opendrain: gpio (int0,1) in open drain mode
> + instead of default push/pull
> + - microchip,int_opendrain: int pin in open drain mode
> + instead of default push/pull
IIRC, we have a standard property for this.
> + - microchip,txcan_opendrain: txcan pin in open drain mode
> + instead of default push/pull
> + - microchip,gpio0_mode : gpio mode functionality
> + 0 = input
> + 1 = TX interrupt output - default
> + 2 = output default low
> + 3 = output default high
> + 4 = (tx) transceiver standby
> + - microchip,gpio1_mode : gpio mode functionality
> + 0 = input - default
> + 1 = RX interrupt output - default
> + 2 = output default low
> + 3 = output default high
> +
> +Example:
> + can0: can@1 {
> + compatible = "microchip,mcp2515";
> + reg = <1>;
> + clocks = <&clk24m>;
> + interrupt-parent = <&gpio4>;
> + interrupts = <13 0x8>;
> + vdd-supply = <®5v0>;
> + xceiver-supply = <®5v0>;
> + microchip,gpio0_mode = <4>;
> + microchip,gpio0_mode = <1>;
> + };
> --
> 2.11.0
>
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^ permalink raw reply
* Re: [PATCH] arm64: renesas: document V3MSK board bindings
From: Rob Herring @ 2017-11-26 22:29 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Simon Horman,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Mark Rutland,
Magnus Damm, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20171124204748.920422106-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
On Fri, Nov 24, 2017 at 11:47:39PM +0300, Sergei Shtylyov wrote:
> Document the V3M Starter Kit device tree bindings, listing it as
> a supported board.
>
> This allows to use checkpatch.pl to validate .dts files referring to
> the V3MSK board.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
>
> ---
> Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH V2 2/9] of: Export of_pci_range_to_resource()
From: Rob Herring @ 2017-11-26 22:31 UTC (permalink / raw)
To: Manikanta Maddireddy
Cc: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, rjw-LthD3rsA81gm4RdzfppkhA,
tglx-hfZtesqFncYOwBW4kG4KsQ, vidyas-DDmLM1+adcrQT0dZR+AlfA,
kthota-DDmLM1+adcrQT0dZR+AlfA, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1511638333-22951-3-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Sun, Nov 26, 2017 at 01:02:06AM +0530, Manikanta Maddireddy wrote:
> Tegra PCIe host driver parses of_pci_range from device tree and converts
> to resource. Export of_pci_range_to_resource() to allow Tegra PCIe host
> driver to be compiled as loadable kernel module.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> V2:
> * commit message update
>
> drivers/of/address.c | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
^ permalink raw reply
* Re: [RFC v1 5/8] Bluetooth: btrtl: add support for the RTL8723BS and RTL8723DS chips
From: Emil Lenngren @ 2017-11-26 22:47 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: Marcel Holtmann, Rob Herring, devicetree,
open list:BLUETOOTH DRIVERS, linux-serial-u79uwXL29TY76Z2rM5mHXA,
Mark Rutland, Gustavo F. Padovan, Johan Hedberg,
Greg Kroah-Hartman, Jiri Slaby, Johan Hovold,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Larry.Finger-tQ5ms3gMjBLk1uMJSBkQmQ
In-Reply-To: <CAFBinCD+P6kBOXjp9YZf8DbsetvF+q6yfp3X+OTRfN_Pv8R88w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi,
2017-11-26 23:23 GMT+01:00 Martin Blumenstingl
<martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>:
>>> c) we have to stick with this config file
> I'm afraid this would be our last option if I can't get b) working
> a datasheet for these chips or some advice from someone who has access
> to the datasheet/knowledge about the internals would be of great help
>
FYI I happen to have the confidential 37 pages long datasheet for
rtl8723ds, but unfortunately it doesn't contain any info about the
format of the config file. I suggest you should reach out to the guys
at NextThing and ask if they have some documentation from Realtek.
/Emil
^ permalink raw reply
* Re: [PATCH] arm64: dts: Hi3660: Fix state id for 'CPU_NAP' state
From: Leo Yan @ 2017-11-27 2:01 UTC (permalink / raw)
To: Sudeep Holla
Cc: Wei Xu, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
devicetree-u79uwXL29TY76Z2rM5mHXA, Daniel Lezcano,
Vincent Guittot
In-Reply-To: <b62517be-1d4d-7b2e-7a6e-1c2abbb4ecee-5wv7dgnIgG8@public.gmane.org>
Hi Sudeep,
On Fri, Nov 24, 2017 at 02:39:47PM +0000, Sudeep Holla wrote:
[...]
> > Come back to recommended state id, I reviewed Juno board defintion and
> > I found it's not align with PSCI spec defintion, in ARM-TF Juno code
> > defines state as below [1]:
> >
>
> Yes Juno is almost 4 years old now, so it may not be too good a
> reference platform for latest and greatest platforms like hikey2 ;)
> As I said, Juno predates the recommendation in the PSCI spec.
>
> > #define ARM_LOCAL_STATE_RUN 0
> > #define ARM_LOCAL_STATE_RET 1
> > #define ARM_LOCAL_STATE_OFF 2
> >
> > In PSCI spec chapter "6.5 Recommended StateID Encoding" recommends power
> > state id as below:
> >
> > 0: Run
> > 1: Standby
> > 2: Retention
> > 3: Powerdown
> >
> > So could you confirm on Hikey960 we should follow PSCI definition for
> > state id definition?
> >
>
> Yes, I don't see any reason not to, as this may become reference to some
> other platform, it's good to keep it aligned so that copy paste happens
> in a good sense for future platforms. :)
Thanks for upper confirmation.
> >> Juno's implementation is legacy as these recommendations were added
> >> later in the specification while Juno is 3 year old platform now.
> >>
> >> Though strictly speaking it's not violation of the PSCI specification,
> >> but I would rather get this fixed not before it's too late and copied to
> >> the next generation of platforms. Since the firmware can be easily
> >> upgraded that shouldn't be that difficult.
> >
> > If completely compliant with PSCI recommended state id, we need change
> > both for ARM-TF and kernel for this. In ARM-TF, I have sent PR [2].
> >
>
> OK
>
> > For the kernel patch, we should change state id as below. Please let me
> > know if you have suggestion for this.
> >
>
> I would wait until ATF changes are merged before you patch DT in the kernel.
Agree, will sent new version patch after ATF patch merging ahead.
Thank you for suggestions.
Leo Yan
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^ permalink raw reply
* [PATCH] ARM: make ARCH_S3C24XX select USE_OF and clean-up boot/dts/Makefile
From: Masahiro Yamada @ 2017-11-27 2:19 UTC (permalink / raw)
To: arm, Olof Johansson, Arnd Bergmann
Cc: Mark Rutland, devicetree, linux-kernel, Russell King,
Masahiro Yamada, Rob Herring, linux-arm-kernel
ARCH_S3C24XX is a very exceptional platform that some DT files in
arch/arm/boot/dts/, but does not select USE_OF.
All the other platforms with DT files correctly select USE_OF
directly or indirectly (Most of them are either ARCH_MULTIPLATFORM
or ARM_SINGLE_ARMV7M).
With ARCH_S3C24XX fixed, "ifeq ($(CONFIG_OF),y)" in DT Makefile
can be deleted.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/Kconfig | 1 +
arch/arm/boot/dts/Makefile | 3 ---
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 51c8df5..5604497 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -595,6 +595,7 @@ config ARCH_S3C24XX
select MULTI_IRQ_HANDLER
select NEED_MACH_IO_H
select SAMSUNG_ATAGS
+ select USE_OF
help
Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0381e9..6f7f25d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,6 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-ifeq ($(CONFIG_OF),y)
-
dtb-$(CONFIG_ARCH_ALPINE) += \
alpine-db.dtb
dtb-$(CONFIG_MACH_ARTPEC6) += \
@@ -1104,4 +1102,3 @@ dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
aspeed-bmc-opp-romulus.dtb \
aspeed-ast2500-evb.dtb
-endif
--
2.7.4
^ permalink raw reply related
* RE: [RFC 1/2] of: reserved_mem: check return value of_dma_configure
From: Peng Fan @ 2017-11-27 4:15 UTC (permalink / raw)
To: hch-jcswGhMUV9g@public.gmane.org,
m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org,
robin.murphy-5wv7dgnIgG8@public.gmane.org,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Cc: van.freenix-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20171126131346.12532-1-peng.fan-3arQi8VN3Tc@public.gmane.org>
> -----Original Message-----
> From: Peng Fan
> Sent: Sunday, November 26, 2017 9:14 PM
> To: hch-jcswGhMUV9g@public.gmane.org; m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org; robin.murphy-5wv7dgnIgG8@public.gmane.org;
> gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org; robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
> Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org; linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org;
> devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; van.freenix-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; Peng Fan
> <peng.fan-3arQi8VN3Tc@public.gmane.org>
> Subject: [RFC 1/2] of: reserved_mem: check return value of_dma_configure
>
> In commit <7b07cbefb6>("iommu: of: Handle IOMMU lookup failure with
> deferred probing or error"), there is possibility that of_dma_configure may fail.
> So in of_reserved_mem_device_init_by_idx,
> also need to propagate the return value of_dma_configure to caller, when
> need to use reserved memory for a device which needs iommu.
Seems my understanding is wrong, with iommu enabled, reserved memory will not be used
for devices with memory-region. Please still help review RFC 2/2.
Thanks,
Peng.
>
> Signed-off-by: Peng Fan <peng.fan-3arQi8VN3Tc@public.gmane.org>
> ---
> drivers/of/of_reserved_mem.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/of/of_reserved_mem.c b/drivers/of/of_reserved_mem.c
> index 22b75c82e377..61523819b50e 100644
> --- a/drivers/of/of_reserved_mem.c
> +++ b/drivers/of/of_reserved_mem.c
> @@ -357,9 +357,12 @@ int of_reserved_mem_device_init_by_idx(struct
> device *dev,
> /* ensure that dma_ops is set for virtual devices
> * using reserved memory
> */
> - of_dma_configure(dev, np);
> -
> - dev_info(dev, "assigned reserved memory node %s\n", rmem-
> >name);
> + ret = of_dma_configure(dev, np);
> + if (ret)
> + of_reserved_mem_device_release(dev);
> + else
> + dev_info(dev, "assigned reserved memory node %s\n",
> + rmem->name);
> } else {
> kfree(rd);
> }
> --
> 2.14.1
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: clocksource: Add Spreadtrum SC9860 timer
From: Baolin Wang @ 2017-11-27 5:14 UTC (permalink / raw)
To: Rob Herring
Cc: Baolin Wang, Daniel Lezcano, Thomas Gleixner, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA, LKML, Mark Brown
In-Reply-To: <20171126221749.jjz4bstzvgzgt4ty@rob-hp-laptop>
Hi,
On 27 November 2017 at 06:17, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Fri, Nov 24, 2017 at 01:37:47PM +0800, Baolin Wang wrote:
>> This patch adds documentation of device tree bindings for the timers
>> found on Spreadtrum SC9860 platform.
>>
>> Signed-off-by: Baolin Wang <baolin.wang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
>> ---
>> .../bindings/timer/spreadtrum,sprd-timer.txt | 20 ++++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt
>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Thanks Rob.
--
Baolin Wang
Best Regards
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^ permalink raw reply
* Re: [PATCH 2/2] clocksource: sprd: Add timer driver for Spreadtrum SC9860 platform
From: Baolin Wang @ 2017-11-27 5:15 UTC (permalink / raw)
To: kbuild test robot
Cc: Baolin Wang, kbuild-all-JC7UmRfGjtg, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA, LKML, Mark Brown
In-Reply-To: <201711251226.MKE0Bxdd%fengguang.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
On 25 November 2017 at 13:00, kbuild test robot <lkp-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> wrote:
> Hi Baolin,
>
> Thank you for the patch! Perhaps something to improve:
>
> [auto build test WARNING on tip/timers/core]
> [also build test WARNING on v4.14 next-20171124]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>
> url: https://github.com/0day-ci/linux/commits/Baolin-Wang/dt-bindings-clocksource-Add-Spreadtrum-SC9860-timer/20171125-090749
> config: arm-allmodconfig (attached as .config)
> compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
> reproduce:
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=arm
>
> All warnings (new ones prefixed by >>):
>
> In file included from include/linux/swab.h:4:0,
> from include/uapi/linux/byteorder/big_endian.h:12,
> from include/linux/byteorder/big_endian.h:4,
> from arch/arm/include/uapi/asm/byteorder.h:19,
> from include/asm-generic/bitops/le.h:5,
> from arch/arm/include/asm/bitops.h:340,
> from include/linux/bitops.h:37,
> from include/linux/kernel.h:10,
> from include/linux/list.h:8,
> from include/linux/preempt.h:10,
> from include/linux/spinlock.h:50,
> from include/linux/seqlock.h:35,
> from include/linux/time.h:5,
> from include/uapi/linux/timex.h:56,
> from include/linux/timex.h:56,
> from include/linux/clocksource.h:12,
> from drivers/clocksource/sprd-timer.c:7:
> drivers/clocksource/sprd-timer.c: In function 'sprd_timer_update_counter':
> drivers/clocksource/sprd-timer.c:85:24: warning: right shift count >= width of type [-Wshift-count-overflow]
> writel_relaxed(cycles >> TIMER_VALUE_HI_SHIFT,
OK. I will fix this warning in next version. Thanks.
> ^
> include/uapi/linux/swab.h:113:54: note: in definition of macro '__swab32'
> #define __swab32(x) (__u32)__builtin_bswap32((__u32)(x))
> ^
> include/linux/byteorder/generic.h:87:21: note: in expansion of macro '__cpu_to_le32'
> #define cpu_to_le32 __cpu_to_le32
> ^~~~~~~~~~~~~
>>> drivers/clocksource/sprd-timer.c:85:2: note: in expansion of macro 'writel_relaxed'
> writel_relaxed(cycles >> TIMER_VALUE_HI_SHIFT,
> ^~~~~~~~~~~~~~
>
> vim +/writel_relaxed +85 drivers/clocksource/sprd-timer.c
>
> 79
> 80 static void sprd_timer_update_counter(struct sprd_timer_device *timer,
> 81 unsigned long cycles)
> 82 {
> 83 writel_relaxed(cycles & TIMER_VALUE_LO_MASK,
> 84 timer->base + TIMER_LOAD_LO);
> > 85 writel_relaxed(cycles >> TIMER_VALUE_HI_SHIFT,
> 86 timer->base + TIMER_LOAD_HI);
> 87 }
> 88
>
> ---
> 0-DAY kernel test infrastructure Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all Intel Corporation
--
Baolin.wang
Best Regards
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* Re: [PATCH v7 04/13] slimbus: core: Add slim controllers support
From: Vinod Koul @ 2017-11-27 5:52 UTC (permalink / raw)
To: Srinivas Kandagatla
Cc: Greg KH, broonie-DgEjT+Ai2ygdnm+yROfE0A,
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In-Reply-To: <64797182-9244-e6e7-8044-dbc404cdda7c-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Mon, Nov 20, 2017 at 06:47:58AM +0000, Srinivas Kandagatla wrote:
> >>>thanks for the comments.
> >>>
> >>>
> >>>On 16/11/17 16:42, Vinod Koul wrote:
> >>>>On Wed, Nov 15, 2017 at 02:10:34PM +0000,srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org wrote:
> >>>>
> >>>>>+static void slim_dev_release(struct device *dev)
> >>>>>+{
> >>>>>+ struct slim_device *sbdev = to_slim_device(dev);
> >>>>>+
> >>>>>+ put_device(sbdev->ctrl->dev);
> >>>>which device would that be?
> >>>This is controller device
> >>>
> >>>>>+static int slim_add_device(struct slim_controller *ctrl,
> >>>>>+ struct slim_device *sbdev,
> >>>>>+ struct device_node *node)
> >>>>>+{
> >>>>>+ sbdev->dev.bus = &slimbus_bus;
> >>>>>+ sbdev->dev.parent = ctrl->dev;
> >>>>>+ sbdev->dev.release = slim_dev_release;
> >>>>>+ sbdev->dev.driver = NULL;
> >>>>>+ sbdev->ctrl = ctrl;
> >>>>>+
> >>>>>+ dev_set_name(&sbdev->dev, "%x:%x:%x:%x",
> >>>>>+ sbdev->e_addr.manf_id,
> >>>>>+ sbdev->e_addr.prod_code,
> >>>>>+ sbdev->e_addr.dev_index,
> >>>>>+ sbdev->e_addr.instance);
> >>>>>+
> >>>>>+ get_device(ctrl->dev);
> >>>>is this controller device and you ensuring it doesnt go away while you have
> >>>>slaves on it?
> >>>Yes.
> >>I thought since you are marking ctrl->dev as parent, the device core should
> >>ensure that parent doesn't go off when you have child device?
> >>
> >>Greg, is that understanding correct, if so we may not need these calls.
> >That understanding should be correct, as the reference count is
> >incremented on the parent when a child is added.
> >
> >It would be trivial for this to be tested, and yes, I am pretty sure you
> >don't need this call.
>
> Thanks for suggestion, I will remove this in next version.
I think it might be helpful to test the assumption as Greg noted :)
--
~Vinod
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