* Re: [PATCH v2 22/35] nds32: Device tree support
From: Arnd Bergmann @ 2017-11-27 14:30 UTC (permalink / raw)
To: Greentime Hu
Cc: Greentime, Linux Kernel Mailing List, linux-arch, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Networking, Vincent Chen,
DTML, Al Viro, David Howells, Will Deacon, Daniel Lezcano,
linux-serial, Vincent Chen
In-Reply-To: <1055af0e8b98571b4461d6f899d043fe7f17408b.1511785528.git.green.hu@gmail.com>
On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu <green.hu@gmail.com> wrote:
> @@ -0,0 +1,55 @@
> +/dts-v1/;
> +/ {
> + compatible = "nds32 ae3xx";
The compatible string doesn't seem to match the binding, it should always have
vendor prefix.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&intc>;
> +
> + chosen {
> + bootargs = "earlycon console=ttyS0,38400n8 debug loglevel=7";
> + stdout-path = &serial0;
> + };
I would drop the bootargs here, this is something that should be set by the
bootloader and is up to the user.
Arnd
^ permalink raw reply
* Re: [PATCH v2 24/35] nds32: defconfig
From: Arnd Bergmann @ 2017-11-27 14:27 UTC (permalink / raw)
To: Greentime Hu
Cc: Greentime, Linux Kernel Mailing List, linux-arch, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Networking, Vincent Chen,
DTML, Al Viro, David Howells, Will Deacon, Daniel Lezcano,
linux-serial, Vincent Chen
In-Reply-To: <ba7df99550bdd5c06d01ef8f427d116280b8f52d.1511785528.git.green.hu@gmail.com>
On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu <green.hu@gmail.com> wrote:
> +CONFIG_EXPERT=y
You normally shouldn't need CONFIG_EXPERT in a defconfig file, by definition
this is needed for unusual configurations only.
> +CONFIG_NDS32_BUILTIN_DTB="ae3xx"
Having a built-in DTB also makes no sense for a defconfig, when the idea is that
it can run on as many machines as possible.
> +CONFIG_BLK_DEV_LOOP=y
> +CONFIG_BLK_DEV_RAM=y
> +CONFIG_BLK_DEV_RAM_SIZE=8192
Having ramdisk built-in is rather unusual, most users don't use ramdisks
any more since we don't need it for booting with the initramfs.
> +CONFIG_BRIDGE=y
> +CONFIG_TUN=y
These also look unusual. Would it make sense to have these as loadable
modules, or do you require having everything built-in for your workflow?
> +CONFIG_SOUND=y
> +CONFIG_SND=y
> +# CONFIG_SND_SUPPORT_OLD_API is not set
> +# CONFIG_SND_VERBOSE_PROCFS is not set
It seems the sound subsystem is enabled, but no drivers are selected,
so it won't actually do anything.
> +# CONFIG_USB_SUPPORT is not set
> +CONFIG_MMC=y
Same for MMC. If you are still trying to get the respective device drivers
merged, that doesn't need to stop you from enabling the configurations
here.
Arnd
^ permalink raw reply
* Re: [PATCH v2 25/35] nds32: Build infrastructure
From: Arnd Bergmann @ 2017-11-27 14:21 UTC (permalink / raw)
To: Greentime Hu
Cc: Greentime, Linux Kernel Mailing List, linux-arch, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Networking, Vincent Chen,
DTML, Al Viro, David Howells, Will Deacon, Daniel Lezcano,
linux-serial, Vincent Chen
In-Reply-To: <5e1be9ebc591c6de79b75f726a5a38b2564eaa92.1511785528.git.green.hu@gmail.com>
On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu <green.hu@gmail.com> wrote:
> diff --git a/arch/nds32/Kconfig.cpu b/arch/nds32/Kconfig.cpu
> new file mode 100644
> index 0000000..6b4013f
> --- /dev/null
> +++ b/arch/nds32/Kconfig.cpu
> @@ -0,0 +1,131 @@
> +comment "Processor Features"
> +
> +config CPU_BIG_ENDIAN
> + bool "Big endian"
> + def_bool n
> +
> +config CPU_LITTLE_ENDIAN
> + bool "Little endian"
> + def_bool y
These must be mutually exclusive, you surely get some build error if you try to
set both here.
You can either make it a 'choice' statement to pick between the two, or you
can make CPU_LITTLE_ENDIAN a silent option like
config CPU_BIG_ENDIAN
bool "Big endian"
config CPU_LITTLE_ENDIAN
def_bool !CPU_BIG_ENDIAN
> +config CPU_CACHE_NONALIASING
> + bool "Non-aliasing cache"
> + help
> + If this CPU is using VIPT data cache and its cache way size is larger
> + than page size, say N. If it is using PIPT data cache, say Y.
> +
> + If unsure, say Y.
Can you determine this from the CPU type?
> +choice
> + prompt "Memory split"
> + depends on MMU
> + default VMSPLIT_3G
> + help
> + Select the desired split between kernel and user memory.
> +
> + If you are not absolutely sure what you are doing, leave this
> + option alone!
> +
> + config VMSPLIT_3G
> + bool "3G/1G user/kernel split"
> + config VMSPLIT_3G_OPT
> + bool "3G/1G user/kernel split (for full 1G low memory)"
> + config VMSPLIT_2G
> + bool "2G/2G user/kernel split"
> + config VMSPLIT_1G
> + bool "1G/3G user/kernel split"
> +endchoice
I think you mentioned that the 1GB configuration is quite common, how
about making VMSPLIT_3G_OPT the default here?
Arnd
^ permalink raw reply
* Re: [PATCH v2 04/11] media: rkisp1: add Rockchip MIPI Synopsys DPHY driver
From: Jose Abreu @ 2017-11-27 14:15 UTC (permalink / raw)
To: Hans Verkuil, Jacob Chen, linux-rockchip
Cc: linux-kernel, linux-arm-kernel, mchehab, linux-media,
sakari.ailus, hans.verkuil, tfiga, zhengsq, laurent.pinchart, zyc,
eddie.cai.linux, jeffy.chen, allon.huang, devicetree, heiko,
robh+dt, Jacob Chen, Joao Pinto, Luis de Oliveira
In-Reply-To: <3481c46c-38c1-6754-043e-0338314ae0d0@xs4all.nl>
++ Joao, ++ Luis
Hi Hans,
We will take a look into this. Thanks for pointing this out!
Best Regards,
Jose Miguel Abreu
On 27-11-2017 12:01, Hans Verkuil wrote:
> I'm CC-ing Jose Abreu from Synopsys to this. Jose, can you or a colleague take
> a look at this as well?
>
> Jacob, I have some high-level questions first:
>
> 1) to what extend is this code rockchip-specific as opposed to be more synopsys-generic?
>
> 2) I don't quite see how this works when there are two sensors. Is only one active at a
> time? Or are they multiplexed somehow?
>
> 3) Same as for the previous patch: some more comments would be welcome.
>
> On 11/24/2017 03:36 AM, Jacob Chen wrote:
>> From: Jacob Chen <jacob2.chen@rock-chips.com>
>>
>> This commit adds a subdev driver for Rockchip MIPI Synopsys DPHY driver.
>>
>> The phy driver is kind of independent compare to the other parts, but i'd like
>> to keep it in rkisp1 driver, unless people want to generalize it
>>
>> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
>> Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
>> Signed-off-by: Tomasz Figa <tfiga@chromium.org>
>> ---
>> drivers/media/platform/rockchip/isp1/Makefile | 1 +
>> .../media/platform/rockchip/isp1/mipi_dphy_sy.c | 805 +++++++++++++++++++++
>> 2 files changed, 806 insertions(+)
>> create mode 100644 drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
>>
>> diff --git a/drivers/media/platform/rockchip/isp1/Makefile b/drivers/media/platform/rockchip/isp1/Makefile
>> index 8f52f959398e..18af64853734 100644
>> --- a/drivers/media/platform/rockchip/isp1/Makefile
>> +++ b/drivers/media/platform/rockchip/isp1/Makefile
>> @@ -4,4 +4,5 @@ video_rkisp1-objs += rkisp1.o \
>> regs.o \
>> isp_stats.o \
>> isp_params.o \
>> + mipi_dphy_sy.o \
>> capture.o
>> diff --git a/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
>> new file mode 100644
>> index 000000000000..56deff2be6fd
>> --- /dev/null
>> +++ b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
>> @@ -0,0 +1,805 @@
>> +/*
>> + * Rockchip MIPI Synopsys DPHY driver
>> + *
>> + * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
>> + *
>> + * This software is available to you under a choice of one of two
>> + * licenses. You may choose to be licensed under the terms of the GNU
>> + * General Public License (GPL) Version 2, available from the file
>> + * COPYING in the main directory of this source tree, or the
>> + * OpenIB.org BSD license below:
>> + *
>> + * Redistribution and use in source and binary forms, with or
>> + * without modification, are permitted provided that the following
>> + * conditions are met:
>> + *
>> + * - Redistributions of source code must retain the above
>> + * copyright notice, this list of conditions and the following
>> + * disclaimer.
>> + *
>> + * - Redistributions in binary form must reproduce the above
>> + * copyright notice, this list of conditions and the following
>> + * disclaimer in the documentation and/or other materials
>> + * provided with the distribution.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
>> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
>> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
>> + * SOFTWARE.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <media/media-entity.h>
>> +#include <media/v4l2-ctrls.h>
>> +#include <media/v4l2-fwnode.h>
>> +#include <media/v4l2-subdev.h>
>> +
>> +#define RK3288_GRF_SOC_CON6 0x025c
>> +#define RK3288_GRF_SOC_CON8 0x0264
>> +#define RK3288_GRF_SOC_CON9 0x0268
>> +#define RK3288_GRF_SOC_CON10 0x026c
>> +#define RK3288_GRF_SOC_CON14 0x027c
>> +#define RK3288_GRF_SOC_STATUS21 0x02d4
>> +#define RK3288_GRF_IO_VSEL 0x0380
>> +#define RK3288_GRF_SOC_CON15 0x03a4
>> +
>> +#define RK3399_GRF_SOC_CON9 0x6224
>> +#define RK3399_GRF_SOC_CON21 0x6254
>> +#define RK3399_GRF_SOC_CON22 0x6258
>> +#define RK3399_GRF_SOC_CON23 0x625c
>> +#define RK3399_GRF_SOC_CON24 0x6260
>> +#define RK3399_GRF_SOC_CON25 0x6264
>> +#define RK3399_GRF_SOC_STATUS1 0xe2a4
>> +
>> +#define CLOCK_LANE_HS_RX_CONTROL 0x34
>> +#define LANE0_HS_RX_CONTROL 0x44
>> +#define LANE1_HS_RX_CONTROL 0x54
>> +#define LANE2_HS_RX_CONTROL 0x84
>> +#define LANE3_HS_RX_CONTROL 0x94
>> +#define HS_RX_DATA_LANES_THS_SETTLE__CONTROL 0x75
>> +
>> +#define HIWORD_UPDATE(val, mask, shift) \
>> + ((val) << (shift) | (mask) << ((shift) + 16))
>> +
>> +enum mipi_dphy_sy_pads {
>> + MIPI_DPHY_SY_PAD_SINK = 0,
>> + MIPI_DPHY_SY_PAD_SOURCE,
>> + MIPI_DPHY_SY_PADS_NUM,
>> +};
>> +
>> +enum dphy_reg_id {
>> + GRF_DPHY_RX0_TURNDISABLE = 0,
>> + GRF_DPHY_RX0_FORCERXMODE,
>> + GRF_DPHY_RX0_FORCETXSTOPMODE,
>> + GRF_DPHY_RX0_ENABLE,
>> + GRF_DPHY_RX0_TESTCLR,
>> + GRF_DPHY_RX0_TESTCLK,
>> + GRF_DPHY_RX0_TESTEN,
>> + GRF_DPHY_RX0_TESTDIN,
>> + GRF_DPHY_RX0_TURNREQUEST,
>> + GRF_DPHY_RX0_TESTDOUT,
>> + GRF_DPHY_TX0_TURNDISABLE,
>> + GRF_DPHY_TX0_FORCERXMODE,
>> + GRF_DPHY_TX0_FORCETXSTOPMODE,
>> + GRF_DPHY_TX0_TURNREQUEST,
>> + GRF_DPHY_TX1RX1_TURNDISABLE,
>> + GRF_DPHY_TX1RX1_FORCERXMODE,
>> + GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
>> + GRF_DPHY_TX1RX1_ENABLE,
>> + GRF_DPHY_TX1RX1_MASTERSLAVEZ,
>> + GRF_DPHY_TX1RX1_BASEDIR,
>> + GRF_DPHY_TX1RX1_ENABLECLK,
>> + GRF_DPHY_TX1RX1_TURNREQUEST,
>> + GRF_DPHY_RX1_SRC_SEL,
>> + /* rk3288 only */
>> + GRF_CON_DISABLE_ISP,
>> + GRF_CON_ISP_DPHY_SEL,
>> + GRF_DSI_CSI_TESTBUS_SEL,
>> + GRF_DVP_V18SEL,
>> + /* below is for rk3399 only */
>> + GRF_DPHY_RX0_CLK_INV_SEL,
>> + GRF_DPHY_RX1_CLK_INV_SEL,
>> +};
>> +
>> +struct dphy_reg {
>> + u32 offset;
>> + u32 mask;
>> + u32 shift;
>> +};
>> +
>> +#define PHY_REG(_offset, _width, _shift) \
>> + { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
>> +
>> +static const struct dphy_reg rk3399_grf_dphy_regs[] = {
>> + [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
>> + [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),
>> + [GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11),
>> + [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
>> + [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4),
>> + [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8),
>> + [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12),
>> + [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0),
>> + [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4),
>> + [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 8),
>> + [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 12),
>> + [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0),
>> + [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 4),
>> + [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 8),
>> + [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 12),
>> + [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON24, 4, 0),
>> + [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4),
>> + [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5),
>> + [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 6),
>> + [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 7),
>> + [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0),
>> + [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8),
>> + [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9),
>> + [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10),
>> + [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0),
>> +};
>> +
>> +static const struct dphy_reg rk3288_grf_dphy_regs[] = {
>> + [GRF_CON_DISABLE_ISP] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 0),
>> + [GRF_CON_ISP_DPHY_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 1),
>> + [GRF_DSI_CSI_TESTBUS_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 14),
>> + [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 0),
>> + [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 4),
>> + [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 8),
>> + [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 0),
>> + [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 4),
>> + [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 8),
>> + [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 12),
>> + [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 0),
>> + [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 4),
>> + [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 8),
>> + [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 12),
>> + [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 0),
>> + [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 1),
>> + [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 2),
>> + [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3288_GRF_SOC_CON14, 8, 3),
>> + [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 12),
>> + [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 13),
>> + [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 14),
>> + [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 15),
>> + [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 0),
>> + [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 4),
>> + [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 3, 8),
>> + [GRF_DVP_V18SEL] = PHY_REG(RK3288_GRF_IO_VSEL, 1, 1),
>> + [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3288_GRF_SOC_STATUS21, 8, 0),
>> +};
>> +
>> +struct hsfreq_range {
>> + u32 range_h;
>> + u8 cfg_bit;
>> +};
>> +
>> +struct dphy_drv_data {
>> + const char * const *clks;
>> + int num_clks;
>> + const struct hsfreq_range *hsfreq_ranges;
>> + int num_hsfreq_ranges;
>> + const struct dphy_reg *regs;
>> +};
>> +
>> +struct sensor_async_subdev {
>> + struct v4l2_async_subdev asd;
>> + struct v4l2_mbus_config mbus;
>> + int lanes;
>> +};
>> +
>> +#define MAX_DPHY_CLK 8
>> +#define MAX_DPHY_SENSORS 2
>> +
>> +struct mipidphy_sensor {
>> + struct v4l2_subdev *sd;
>> + struct v4l2_mbus_config mbus;
>> + int lanes;
>> +};
>> +
>> +struct mipidphy_priv {
>> + struct device *dev;
>> + struct regmap *regmap_grf;
>> + const struct dphy_reg *grf_regs;
>> + struct clk *clks[MAX_DPHY_CLK];
>> + const struct dphy_drv_data *drv_data;
>> + u64 data_rate_mbps;
>> + struct v4l2_async_notifier notifier;
>> + struct v4l2_subdev sd;
>> + struct media_pad pads[MIPI_DPHY_SY_PADS_NUM];
>> + struct mipidphy_sensor sensors[MAX_DPHY_SENSORS];
>> + int num_sensors;
>> + bool is_streaming;
>> +};
>> +
>> +static inline struct mipidphy_priv *to_dphy_priv(struct v4l2_subdev *subdev)
>> +{
>> + return container_of(subdev, struct mipidphy_priv, sd);
>> +}
>> +
>> +static inline void write_reg(struct mipidphy_priv *priv, int index, u8 value)
>> +{
>> + const struct dphy_reg *reg = &priv->grf_regs[index];
>> + unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
>> +
>> + WARN_ON(!reg->offset);
>> + regmap_write(priv->regmap_grf, reg->offset, val);
>> +}
>> +
>> +static void mipidphy_wr_reg(struct mipidphy_priv *priv,
>> + u8 test_code, u8 test_data)
>> +{
>> + /*
>> + * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
>> + * is latched internally as the current test code. Test data is
>> + * programmed internally by rising edge on TESTCLK.
>> + */
>> + write_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
>> + write_reg(priv, GRF_DPHY_RX0_TESTDIN, test_code);
>> + write_reg(priv, GRF_DPHY_RX0_TESTEN, 1);
>> + write_reg(priv, GRF_DPHY_RX0_TESTCLK, 0);
>> + write_reg(priv, GRF_DPHY_RX0_TESTEN, 0);
>> + write_reg(priv, GRF_DPHY_RX0_TESTDIN, test_data);
>> + write_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
>> +}
>> +
>> +static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
>> +{
>> + struct media_pad *local, *remote;
>> + struct media_entity *sensor_me;
>> +
>> + local = &sd->entity.pads[MIPI_DPHY_SY_PAD_SINK];
>> + remote = media_entity_remote_pad(local);
>> + if (!remote) {
>> + v4l2_warn(sd, "No link between dphy and sensor\n");
>> + return NULL;
>> + }
>> +
>> + sensor_me = media_entity_remote_pad(local)->entity;
>> + return media_entity_to_v4l2_subdev(sensor_me);
>> +}
>> +
>> +static struct mipidphy_sensor *sd_to_sensor(struct mipidphy_priv *priv,
>> + struct v4l2_subdev *sd)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < priv->num_sensors; ++i)
>> + if (priv->sensors[i].sd == sd)
>> + return &priv->sensors[i];
>> +
>> + return NULL;
>> +}
>> +
>> +static int mipidphy_get_sensor_data_rate(struct v4l2_subdev *sd)
>> +{
>> + struct mipidphy_priv *priv = to_dphy_priv(sd);
>> + struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
>> + struct v4l2_ctrl *link_freq;
>> + struct v4l2_querymenu qm = { .id = V4L2_CID_LINK_FREQ, };
>> + int ret;
>> +
>> + link_freq = v4l2_ctrl_find(sensor_sd->ctrl_handler, V4L2_CID_LINK_FREQ);
>> + if (!link_freq) {
>> + v4l2_warn(sd, "No pixel rate control in subdev\n");
>> + return -EPIPE;
>> + }
>> +
>> + qm.index = v4l2_ctrl_g_ctrl(link_freq);
>> + ret = v4l2_querymenu(sensor_sd->ctrl_handler, &qm);
>> + if (ret < 0) {
>> + v4l2_err(sd, "Failed to get menu item\n");
>> + return ret;
>> + }
>> +
>> + if (!qm.value) {
>> + v4l2_err(sd, "Invalid link_freq\n");
>> + return -EINVAL;
>> + }
>> + priv->data_rate_mbps = qm.value * 2;
>> + do_div(priv->data_rate_mbps, 1000 * 1000);
>> +
>> + return 0;
>> +}
>> +
>> +static int mipidphy_s_stream_start(struct v4l2_subdev *sd)
>> +{
>> + struct mipidphy_priv *priv = to_dphy_priv(sd);
>> + const struct dphy_drv_data *drv_data = priv->drv_data;
>> + const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
>> + int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
>> + struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
>> + struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
>> + int i, ret, hsfreq = 0;
>> +
>> + if (priv->is_streaming)
>> + return 0;
>> +
>> + ret = mipidphy_get_sensor_data_rate(sd);
>> + if (ret < 0)
>> + return ret;
>> +
>> + for (i = 0; i < num_hsfreq_ranges; i++) {
>> + if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
>> + hsfreq = hsfreq_ranges[i].cfg_bit;
>> + break;
>> + }
>> + }
>> +
>> + write_reg(priv, GRF_DPHY_RX0_FORCERXMODE, 0);
>> + write_reg(priv, GRF_DPHY_RX0_FORCETXSTOPMODE, 0);
>> + /* Disable lan turn around, which is ignored in receive mode */
>> + write_reg(priv, GRF_DPHY_RX0_TURNREQUEST, 0);
>> + write_reg(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf);
>> +
>> + write_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(sensor->lanes - 1, 0));
>> +
>> + /* dphy start */
>> + write_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
>> + write_reg(priv, GRF_DPHY_RX0_TESTCLR, 1);
>> + usleep_range(100, 150);
>> + write_reg(priv, GRF_DPHY_RX0_TESTCLR, 0);
>> + usleep_range(100, 150);
>> +
>> + /* set clock lane */
>> + /* HS hsfreq_range & lane 0 settle bypass */
>> + mipidphy_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
>> + /* HS RX Control of lane0 */
>> + mipidphy_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq << 1);
>> + /* HS RX Control of lane1 */
>> + mipidphy_wr_reg(priv, LANE1_HS_RX_CONTROL, 0);
>> + /* HS RX Control of lane2 */
>> + mipidphy_wr_reg(priv, LANE2_HS_RX_CONTROL, 0);
>> + /* HS RX Control of lane3 */
>> + mipidphy_wr_reg(priv, LANE3_HS_RX_CONTROL, 0);
>> + /* HS RX Data Lanes Settle State Time Control */
>> + mipidphy_wr_reg(priv, HS_RX_DATA_LANES_THS_SETTLE__CONTROL, 0x04);
>> +
>> + /* Normal operation */
>> + mipidphy_wr_reg(priv, 0x0, 0);
>> +
>> + priv->is_streaming = true;
>> +
>> + return 0;
>> +}
>> +
>> +static int mipidphy_s_stream_stop(struct v4l2_subdev *sd)
>> +{
>> + struct mipidphy_priv *priv = to_dphy_priv(sd);
>> +
>> + if (!priv->is_streaming)
>> + return 0;
>> +
>> + priv->is_streaming = false;
>> +
>> + return 0;
>> +}
>> +
>> +static int mipidphy_s_stream(struct v4l2_subdev *sd, int on)
>> +{
>> + if (on)
>> + return mipidphy_s_stream_start(sd);
>> + else
>> + return mipidphy_s_stream_stop(sd);
>> +}
>> +
>> +static int mipidphy_g_mbus_config(struct v4l2_subdev *sd,
>> + struct v4l2_mbus_config *config)
>> +{
>> + struct mipidphy_priv *priv = to_dphy_priv(sd);
>> + struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
>> + struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
>> +
>> + *config = sensor->mbus;
>> +
>> + return 0;
>> +}
>> +
>> +static int mipidphy_s_power(struct v4l2_subdev *sd, int on)
>> +{
>> + struct mipidphy_priv *priv = to_dphy_priv(sd);
>> +
>> + if (on)
>> + return pm_runtime_get_sync(priv->dev);
>> + else
>> + return pm_runtime_put(priv->dev);
>> +}
>> +
>> +static int mipidphy_runtime_suspend(struct device *dev)
>> +{
>> + struct media_entity *me = dev_get_drvdata(dev);
>> + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
>> + struct mipidphy_priv *priv = to_dphy_priv(sd);
>> + int i, num_clks;
>> +
>> + num_clks = priv->drv_data->num_clks;
>> + for (i = num_clks - 1; i >= 0; i--)
>> + clk_disable_unprepare(priv->clks[i]);
>> +
>> + return 0;
>> +}
>> +
>> +static int mipidphy_runtime_resume(struct device *dev)
>> +{
>> + struct media_entity *me = dev_get_drvdata(dev);
>> + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
>> + struct mipidphy_priv *priv = to_dphy_priv(sd);
>> + int i, num_clks, ret;
>> +
>> + num_clks = priv->drv_data->num_clks;
>> + for (i = 0; i < num_clks; i++) {
>> + ret = clk_prepare_enable(priv->clks[i]);
>> + if (ret < 0)
>> + goto err;
>> + }
>> +
>> + return 0;
>> +err:
>> + while (--i >= 0)
>> + clk_disable_unprepare(priv->clks[i]);
>> + return ret;
>> +}
>> +
>> +/* dphy accepts all fmt/size from sensor */
>> +static int mipidphy_get_set_fmt(struct v4l2_subdev *sd,
>> + struct v4l2_subdev_pad_config *cfg,
>> + struct v4l2_subdev_format *fmt)
>> +{
>> + struct v4l2_subdev *sensor = get_remote_sensor(sd);
>> +
>> + /*
>> + * Do not allow format changes and just relay whatever
>> + * set currently in the sensor.
>> + */
>> + return v4l2_subdev_call(sensor, pad, get_fmt, NULL, fmt);
>> +}
>> +
>> +static const struct v4l2_subdev_pad_ops mipidphy_subdev_pad_ops = {
>> + .set_fmt = mipidphy_get_set_fmt,
>> + .get_fmt = mipidphy_get_set_fmt,
>> +};
>> +
>> +static const struct v4l2_subdev_core_ops mipidphy_core_ops = {
>> + .s_power = mipidphy_s_power,
>> +};
>> +
>> +static const struct v4l2_subdev_video_ops mipidphy_video_ops = {
>> + .g_mbus_config = mipidphy_g_mbus_config,
> Why do you need this?
>
>> + .s_stream = mipidphy_s_stream,
>> +};
>> +
>> +static const struct v4l2_subdev_ops mipidphy_subdev_ops = {
>> + .core = &mipidphy_core_ops,
>> + .video = &mipidphy_video_ops,
>> + .pad = &mipidphy_subdev_pad_ops,
>> +};
>> +
>> +/* These tables must be sorted by .range_h ascending. */
>> +static const struct hsfreq_range rk3288_mipidphy_hsfreq_ranges[] = {
>> + { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01},
>> + { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12},
>> + { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23},
>> + { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15},
>> + { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07},
>> + { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09},
>> + { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a},
>> + { 999, 0x1a}
>> +};
>> +
>> +static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = {
>> + { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01},
>> + { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12},
>> + { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23},
>> + { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15},
>> + { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07},
>> + { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09},
>> + { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a},
>> + { 999, 0x1a}, {1049, 0x2a}, {1099, 0x3a}, {1149, 0x0b},
>> + {1199, 0x1b}, {1249, 0x2b}, {1299, 0x3b}, {1349, 0x0c},
>> + {1399, 0x1c}, {1449, 0x2c}, {1500, 0x3c}
>> +};
>> +
>> +static const char * const rk3399_mipidphy_clks[] = {
>> + "dphy-ref",
>> + "dphy-cfg",
>> + "grf",
>> +};
>> +
>> +static const char * const rk3288_mipidphy_clks[] = {
>> + "dphy-ref",
>> + "pclk",
>> +};
>> +
>> +static const struct dphy_drv_data rk3288_mipidphy_drv_data = {
>> + .clks = rk3288_mipidphy_clks,
>> + .num_clks = ARRAY_SIZE(rk3288_mipidphy_clks),
>> + .hsfreq_ranges = rk3288_mipidphy_hsfreq_ranges,
>> + .num_hsfreq_ranges = ARRAY_SIZE(rk3288_mipidphy_hsfreq_ranges),
>> + .regs = rk3288_grf_dphy_regs,
>> +};
>> +
>> +static const struct dphy_drv_data rk3399_mipidphy_drv_data = {
>> + .clks = rk3399_mipidphy_clks,
>> + .num_clks = ARRAY_SIZE(rk3399_mipidphy_clks),
>> + .hsfreq_ranges = rk3399_mipidphy_hsfreq_ranges,
>> + .num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges),
>> + .regs = rk3399_grf_dphy_regs,
>> +};
>> +
>> +static const struct of_device_id rockchip_mipidphy_match_id[] = {
>> + {
>> + .compatible = "rockchip,rk3399-mipi-dphy",
>> + .data = &rk3399_mipidphy_drv_data,
>> + },
>> + {
>> + .compatible = "rockchip,rk3288-mipi-dphy",
>> + .data = &rk3288_mipidphy_drv_data,
>> + },
>> + {}
>> +};
>> +MODULE_DEVICE_TABLE(of, rockchip_mipidphy_match_id);
>> +
>> +/* The .bound() notifier callback when a match is found */
>> +static int
>> +rockchip_mipidphy_notifier_bound(struct v4l2_async_notifier *notifier,
>> + struct v4l2_subdev *sd,
>> + struct v4l2_async_subdev *asd)
>> +{
>> + struct mipidphy_priv *priv = container_of(notifier,
>> + struct mipidphy_priv,
>> + notifier);
>> + struct sensor_async_subdev *s_asd = container_of(asd,
>> + struct sensor_async_subdev, asd);
>> + struct mipidphy_sensor *sensor;
>> +
>> + if (priv->num_sensors == ARRAY_SIZE(priv->sensors))
>> + return -EBUSY;
>> +
>> + sensor = &priv->sensors[priv->num_sensors++];
>> + sensor->lanes = s_asd->lanes;
>> + sensor->mbus = s_asd->mbus;
>> + sensor->sd = sd;
>> +
>> + return 0;
>> +}
>> +
>> +/* The .unbind callback */
>> +static void
>> +rockchip_mipidphy_notifier_unbind(struct v4l2_async_notifier *notifier,
>> + struct v4l2_subdev *sd,
>> + struct v4l2_async_subdev *asd)
>> +{
>> + struct mipidphy_priv *priv = container_of(notifier,
>> + struct mipidphy_priv,
>> + notifier);
>> + struct mipidphy_sensor *sensor = sd_to_sensor(priv, sd);
>> +
>> + sensor->sd = NULL;
>> +}
>> +
>> +/* .complete() is called after all subdevices have been located */
>> +static int
>> +rockchip_mipidphy_notifier_complete(struct v4l2_async_notifier *notifier)
>> +{
>> + struct mipidphy_priv *priv = container_of(notifier,
>> + struct mipidphy_priv,
>> + notifier);
>> + unsigned int pad;
>> + int ret;
>> + int i;
>> +
>> + for (i = 0; i < priv->num_sensors; ++i) {
>> + struct mipidphy_sensor *sensor = &priv->sensors[i];
>> +
>> + for (pad = 0; pad < sensor->sd->entity.num_pads; pad++)
>> + if (sensor->sd->entity.pads[pad].flags
>> + & MEDIA_PAD_FL_SOURCE)
>> + break;
>> +
>> + if (pad == sensor->sd->entity.num_pads) {
>> + dev_err(priv->dev,
>> + "failed to find src pad for %s\n",
>> + sensor->sd->name);
>> +
>> + return -ENXIO;
>> + }
>> +
>> + ret = media_create_pad_link(
>> + &sensor->sd->entity, pad,
>> + &priv->sd.entity, MIPI_DPHY_SY_PAD_SINK,
>> + i ? 0 : MEDIA_LNK_FL_ENABLED);
>> + if (ret) {
>> + dev_err(priv->dev,
>> + "failed to create link for %s\n",
>> + sensor->sd->name);
>> + return ret;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static const
>> +struct v4l2_async_notifier_operationsrockchip_mipidphy_async_ops = {
>> + .bound = rockchip_mipidphy_notifier_bound,
>> + .unbind = rockchip_mipidphy_notifier_unbind,
>> + .complete = rockchip_mipidphy_notifier_complete,
>> +};
>> +
>> +static int rockchip_mipidphy_fwnode_parse(struct device *dev,
>> + struct v4l2_fwnode_endpoint *vep,
>> + struct v4l2_async_subdev *asd)
>> +{
>> + struct sensor_async_subdev *s_asd =
>> + container_of(asd, struct sensor_async_subdev, asd);
>> + struct v4l2_mbus_config *config = &s_asd->mbus;
>> +
>> + if (vep->bus_type != V4L2_MBUS_CSI2) {
>> + dev_err(dev, "Only CSI2 bus type is currently supported\n");
>> + return -EINVAL;
>> + }
>> +
>> + if (vep->base.port != 0) {
>> + dev_err(dev, "The PHY has only port 0\n");
>> + return -EINVAL;
>> + }
>> +
>> + config->type = V4L2_MBUS_CSI2;
>> + config->flags = vep->bus.mipi_csi2.flags;
>> + s_asd->lanes = vep->bus.mipi_csi2.num_data_lanes;
>> +
>> + switch (vep->bus.mipi_csi2.num_data_lanes) {
>> + case 1:
>> + config->flags |= V4L2_MBUS_CSI2_1_LANE;
>> + break;
>> + case 2:
>> + config->flags |= V4L2_MBUS_CSI2_2_LANE;
>> + break;
>> + case 3:
>> + config->flags |= V4L2_MBUS_CSI2_3_LANE;
>> + break;
>> + case 4:
>> + config->flags |= V4L2_MBUS_CSI2_4_LANE;
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_mipidphy_media_init(struct mipidphy_priv *priv)
>> +{
>> + int ret;
>> +
>> + priv->pads[MIPI_DPHY_SY_PAD_SOURCE].flags =
>> + MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
>> + priv->pads[MIPI_DPHY_SY_PAD_SINK].flags =
>> + MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
>> +
>> + ret = media_entity_pads_init(&priv->sd.entity,
>> + MIPI_DPHY_SY_PADS_NUM, priv->pads);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = v4l2_async_notifier_parse_fwnode_endpoints_by_port(
>> + priv->dev, &priv->notifier,
>> + sizeof(struct sensor_async_subdev), 0,
>> + rockchip_mipidphy_fwnode_parse);
>> + if (ret < 0)
>> + return ret;
>> +
>> + if (!priv->notifier.num_subdevs)
>> + return -ENODEV; /* no endpoint */
>> +
>> + priv->sd.subdev_notifier = &priv->notifier;
>> + priv->notifier.ops = &rockchip_mipidphy_async_ops;
>> + ret = v4l2_async_subdev_notifier_register(&priv->sd, &priv->notifier);
>> + if (ret) {
>> + dev_err(priv->dev,
>> + "failed to register async notifier : %d\n", ret);
>> + v4l2_async_notifier_cleanup(&priv->notifier);
>> + return ret;
>> + }
>> +
>> + return v4l2_async_register_subdev(&priv->sd);
>> +}
>> +
>> +static int rockchip_mipidphy_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct v4l2_subdev *sd;
>> + struct mipidphy_priv *priv;
>> + struct regmap *grf;
>> + const struct of_device_id *of_id;
>> + const struct dphy_drv_data *drv_data;
>> + int i, ret;
>> +
>> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>> + if (!priv)
>> + return -ENOMEM;
>> + priv->dev = dev;
>> +
>> + of_id = of_match_device(rockchip_mipidphy_match_id, dev);
>> + if (!of_id)
>> + return -EINVAL;
>> +
>> + grf = syscon_node_to_regmap(dev->parent->of_node);
>> + if (IS_ERR(grf)) {
>> + dev_err(dev, "Can't find GRF syscon\n");
>> + return -ENODEV;
>> + }
>> + priv->regmap_grf = grf;
>> +
>> + drv_data = of_id->data;
>> + for (i = 0; i < drv_data->num_clks; i++) {
>> + priv->clks[i] = devm_clk_get(dev, drv_data->clks[i]);
>> +
>> + if (IS_ERR(priv->clks[i])) {
>> + dev_err(dev, "Failed to get %s\n", drv_data->clks[i]);
>> + return PTR_ERR(priv->clks[i]);
>> + }
>> + }
>> +
>> + priv->grf_regs = drv_data->regs;
>> + priv->drv_data = drv_data;
>> +
>> + sd = &priv->sd;
>> + v4l2_subdev_init(sd, &mipidphy_subdev_ops);
>> + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
>> + snprintf(sd->name, sizeof(sd->name), "rockchip-sy-mipi-dphy");
>> + sd->dev = dev;
>> +
>> + platform_set_drvdata(pdev, &sd->entity);
>> +
>> + ret = rockchip_mipidphy_media_init(priv);
>> + if (ret < 0)
>> + return ret;
>> +
>> + pm_runtime_enable(&pdev->dev);
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_mipidphy_remove(struct platform_device *pdev)
>> +{
>> + struct media_entity *me = platform_get_drvdata(pdev);
>> + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
>> +
>> + media_entity_cleanup(&sd->entity);
>> +
>> + pm_runtime_disable(&pdev->dev);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct dev_pm_ops rockchip_mipidphy_pm_ops = {
>> + SET_RUNTIME_PM_OPS(mipidphy_runtime_suspend,
>> + mipidphy_runtime_resume, NULL)
>> +};
>> +
>> +static struct platform_driver rockchip_isp_mipidphy_driver = {
>> + .probe = rockchip_mipidphy_probe,
>> + .remove = rockchip_mipidphy_remove,
>> + .driver = {
>> + .name = "rockchip-sy-mipi-dphy",
>> + .pm = &rockchip_mipidphy_pm_ops,
>> + .of_match_table = rockchip_mipidphy_match_id,
>> + },
>> +};
>> +
>> +module_platform_driver(rockchip_isp_mipidphy_driver);
>> +MODULE_AUTHOR("Rockchip Camera/ISP team");
>> +MODULE_DESCRIPTION("Rockchip MIPI DPHY driver");
>> +MODULE_LICENSE("Dual BSD/GPL");
>>
> Regards,
>
> Hans
^ permalink raw reply
* Re: [PATCH v2 30/35] net: faraday add nds32 support.
From: Arnd Bergmann @ 2017-11-27 14:15 UTC (permalink / raw)
To: Greentime Hu
Cc: Greentime, Linux Kernel Mailing List, linux-arch, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Networking, Vincent Chen,
DTML, Al Viro, David Howells, Will Deacon, Daniel Lezcano,
linux-serial
In-Reply-To: <1aa759dbbb1032dd20e5fadbb0ce5aa4b8b22690.1511785528.git.green.hu@gmail.com>
On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu <green.hu@gmail.com> wrote:
> From: Greentime Hu <greentime@andestech.com>
>
> Signed-off-by: Greentime Hu <greentime@andestech.com>
This is missing a patch description.
> diff --git a/drivers/net/ethernet/faraday/Kconfig b/drivers/net/ethernet/faraday/Kconfig
> index 040c7f1..0ae6e9a 100644
> --- a/drivers/net/ethernet/faraday/Kconfig
> +++ b/drivers/net/ethernet/faraday/Kconfig
> @@ -5,7 +5,7 @@
> config NET_VENDOR_FARADAY
> bool "Faraday devices"
> default y
> - depends on ARM
> + depends on ARM || NDS32
> ---help---
> If you have a network (Ethernet) card belonging to this class, say Y.
>
We probably want to make all three here
depends on ARM || NDS32 || COMPILE_TEST
Arnd
^ permalink raw reply
* Re: [PATCH v2 32/35] asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU
From: Arnd Bergmann @ 2017-11-27 14:14 UTC (permalink / raw)
To: Greentime Hu
Cc: Greentime, Linux Kernel Mailing List, linux-arch, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Networking, Vincent Chen,
DTML, Al Viro, David Howells, Will Deacon, Daniel Lezcano,
linux-serial, Vincent Chen
In-Reply-To: <44e31de43dab9abecdc08f9a87244205f054cfa6.1511785528.git.green.hu@gmail.com>
On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu <green.hu@gmail.com> wrote:
> From: Greentime Hu <greentime@andestech.com>
>
> It allows some architectures to use this generic macro instead of
> defining theirs.
>
> Signed-off-by: Vincent Chen <vincentc@andestech.com>
> Signed-off-by: Greentime Hu <greentime@andestech.com>
> ---
> include/asm-generic/io.h | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
This looks good, but you probably want to do this earlier in the series, so you
can build on top of this change.
Please keep this patch as part of your series,
Acked-by: Arnd Bergmann <arnd@arndb.de>
^ permalink raw reply
* Re: [PATCH v2 34/35] clocksource/drivers/Kconfig: Support andestech atcpit100 timer
From: Arnd Bergmann @ 2017-11-27 14:11 UTC (permalink / raw)
To: Greentime Hu
Cc: Greentime, Linux Kernel Mailing List, linux-arch, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Networking, Vincent Chen,
DTML, Al Viro, David Howells, Will Deacon, Daniel Lezcano,
linux-serial, Rick Chen
In-Reply-To: <1a22db002413ff60851737736a86b40c38877220.1511785528.git.green.hu@gmail.com>
On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu <green.hu@gmail.com> wrote:
> From: Rick Chen <rickchen36@gmail.com>
>
> Add CLKSRC_ATCPIT100 for Andestech atcpit100 timer selection.
> It often be used in Andestech AE3XX platform.
>
> Signed-off-by: Rick Chen <rickchen36@gmail.com>
> Signed-off-by: Greentime Hu <green.hu@gmail.com>
No need to split out the Makefile patch from the actual driver, they
clearly belong together.
The binding change should be a separate patch, as you did.
It's probably best to separate the driver patches from the
architecture submission
in the future, they can simply get merged by the respective subsystem
maintainers,
with a smaller Cc list.
Arnd
^ permalink raw reply
* Re: [PATCH v4 0/6] Remodel FlexCAN register r/w APIs for big endian
From: Marc Kleine-Budde @ 2017-11-27 14:07 UTC (permalink / raw)
To: Pankaj Bansal, wg-5Yr1BZd7O62+XT7JhA+gdA,
linux-can-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: V.Sethi-3arQi8VN3Tc, poonam.aggrwal-3arQi8VN3Tc
In-Reply-To: <1511529733-27942-1-git-send-email-pankaj.bansal-3arQi8VN3Tc@public.gmane.org>
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On 11/24/2017 02:22 PM, Pankaj Bansal wrote:
> This patch series remodels the FlexCAN register r/w APIs for big endian.
> The endianness is checked based on optional big-endian property in
> device tree. if this property is not present in device tree node then
> controller is assumed to be little endian. if this property is present then
> controller is assumed to be big endian.
>
> An exception to this rule is powerpc P1010RDB, which is always
> big-endian, even if big-endian is not present in dts. This is
> checked using p1010-flexcan compatible in dts.
>
> Therefore, remove p1010-flexcan compatible from imx series dts,
> as their flexcan core is little endian.
>
> Finally this series adds support for NXP LS1021A SOC in flexcan,
> which is arm based SOC having big-endian FlexCAN controller.
>
> Pankaj Bansal (6):
> can: flexcan: Remodel FlexCAN register r/w APIs for big endian FlexCAN
> controllers.
> can: flexcan: adding platform specific details for LS1021A
> Documentation : can : flexcan : Add big-endian property to device tree
> powerpc: dts: P1010: Add endianness property to flexcan node
> arm: dts: Remove p1010-flexcan compatible from imx series dts
> arm/dts: Add nodes for flexcan devices present on LS1021A-Rev2 SoC
Applied to can-next.
Thanks,
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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^ permalink raw reply
* Re: [PATCH v4 1/6] can: flexcan: Remodel FlexCAN register r/w APIs for big endian FlexCAN controllers.
From: Marc Kleine-Budde @ 2017-11-27 14:06 UTC (permalink / raw)
To: Pankaj Bansal, wg@grandegger.com, linux-can@vger.kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
devicetree@vger.kernel.org
Cc: Varun Sethi, Poonam Aggrwal, Bhupesh Sharma, Sakar Arora
In-Reply-To: <AM0PR0402MB39405B9B5E5C04B2492221D6F1240@AM0PR0402MB3940.eurprd04.prod.outlook.com>
[-- Attachment #1.1: Type: text/plain, Size: 1574 bytes --]
On 11/26/2017 03:20 AM, Pankaj Bansal wrote:
>>> diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
>>> index a13a489..4c873fb 100644
>>> --- a/drivers/net/can/flexcan.c
>>> +++ b/drivers/net/can/flexcan.c
>>
>> [...]
>> I think this will select LE for non DT devices, right?
>>
>
> Yes. As per below code snippet:
>
> static struct property *__of_find_property(const struct device_node *np,
> const char *name, int *lenp)
> {
> struct property *pp;
>
> if (!np)
> return NULL;
> ....
> }
>
> If no device node is present null is returned.
> So we select le as default.
This is what I found out, too.
>>> + if (of_property_read_bool(pdev->dev.of_node, "big-endian")) {
>>> + priv->read = flexcan_read_be;
>>> + priv->write = flexcan_write_be;
>>> + } else {
>>> + if (of_device_is_compatible(pdev->dev.of_node,
>>> + "fsl,p1010-flexcan")) {
>>> + priv->read = flexcan_read_be;
>>> + priv->write = flexcan_write_be;
>>> + } else {
>>> + priv->read = flexcan_read_le;
>>> + priv->write = flexcan_write_le;
>>> + }
>>> + }
>>> +
>>> priv->can.clock.freq = clock_freq;
>>> priv->can.bittiming_const = &flexcan_bittiming_const;
>>> priv->can.do_set_mode = flexcan_set_mode;
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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^ permalink raw reply
* Re: [PATCH v2 10/35] nds32: Atomic operations
From: Mark Rutland @ 2017-11-27 13:57 UTC (permalink / raw)
To: Greentime Hu
Cc: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial, Vincent Chen
In-Reply-To: <56a24fae3cec68f80c41eebd98fcceb9b137ac64.1511785528.git.green.hu@gmail.com>
Hi,
On Mon, Nov 27, 2017 at 08:27:57PM +0800, Greentime Hu wrote:
> +static inline void arch_spin_unlock(arch_spinlock_t * lock)
> +{
> + asm volatile(
> + "xor $r15, $r15, $r15\n"
> + "swi $r15, [%0]\n"
> + :
> + :"r"(&lock->lock)
> + :"memory");
> +}
This looks suspicious. There's no clobber for $r15, so isn't this
corrupting a GPR behind the back of the compiler?
Shouldn't there be a tmp variable for the register allocation rather
than hard-coding $r15?
> +static inline void arch_write_unlock(arch_rwlock_t * rw)
> +{
> + asm volatile(
> + "xor $r15, $r15, $r15\n"
> + "swi $r15, [%0]\n"
> + :
> + :"r"(&rw->lock)
> + :"memory","$r15");
> +}
This time you have a clobber, but it's still not clear to me why you
don't use a tmp variable and leave the register allocation to the
compiler.
Thanks,
Mark.
^ permalink raw reply
* Re: [PATCH v2 06/35] nds32: MMU fault handling and page table management
From: Mark Rutland @ 2017-11-27 13:51 UTC (permalink / raw)
To: Greentime Hu
Cc: greentime-MUIXKm3Oiri1Z/+hSey0Gg,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
linux-arch-u79uwXL29TY76Z2rM5mHXA, tglx-hfZtesqFncYOwBW4kG4KsQ,
jason-NLaQJdtUoK4Be96aLqz0jA, marc.zyngier-5wv7dgnIgG8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, netdev-u79uwXL29TY76Z2rM5mHXA,
deanbo422-Re5JQEeQqe8AvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
viro-RmSDqhL/yNMiFSDQTTA3OLVCufUGDwFn,
dhowells-H+wXaHxf7aLQT0dZR+AlfA, will.deacon-5wv7dgnIgG8,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
linux-serial-u79uwXL29TY76Z2rM5mHXA, Vincent Chen
In-Reply-To: <ba92adae5d20d99c7c18e75146642a2ccbd5d047.1511785528.git.green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi,
On Mon, Nov 27, 2017 at 08:27:53PM +0800, Greentime Hu wrote:
> +void do_page_fault(unsigned long entry, unsigned long addr,
> + unsigned int error_code, struct pt_regs *regs)
> +{
> + /*
> + * As per x86, we may deadlock here. However, since the kernel only
> + * validly references user space from well defined areas of the code,
> + * we can bug out early if this is from code which shouldn't.
> + */
> + if (unlikely(!down_read_trylock(&mm->mmap_sem))) {
> + if (!user_mode(regs) &&
> + !search_exception_tables(instruction_pointer(regs)))
> + goto no_context;
> +retry:
> + down_read(&mm->mmap_sem);
> + } else {
> + /*
> + * The above down_read_trylock() might have succeeded in which
> + * case, we'll have missed the might_sleep() from down_read().
> + */
> + might_sleep();
> + if (IS_ENABLED(CONFIG_DEBUG_VM)) {
> + if (!user_mode(regs) &&
> + !search_exception_tables(instruction_pointer(regs)))
> + goto no_context;
> + }
> + }
> + fault = handle_mm_fault(vma, addr, flags);
> +
> + /*
> + * If we need to retry but a fatal signal is pending, handle the
> + * signal first. We do not need to release the mmap_sem because it
> + * would already be released in __lock_page_or_retry in mm/filemap.c.
> + */
> + if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
> + return;
I believe you can get stuck in a livelock here (with an unkillable
task), if a uaccess primitive tries to access a region protected by a
userfaultfd. Please see:
https://lkml.kernel.org/r/1499782590-31366-1-git-send-email-mark.rutland-5wv7dgnIgG8@public.gmane.org
... for details and a test case.
Thanks,
Mark.
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^ permalink raw reply
* Re: [PATCH v2 0/2] add clk controller driver for Meson-AXG SoC
From: Jerome Brunet @ 2017-11-27 13:48 UTC (permalink / raw)
To: Yixun Lan, Neil Armstrong, Kevin Hilman
Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Carlo Caione, Qiufang Dai, linux-amlogic, devicetree, linux-clk,
linux-arm-kernel, linux-kernel
In-Reply-To: <20171127094844.16742-1-yixun.lan@amlogic.com>
On Mon, 2017-11-27 at 17:48 +0800, Yixun Lan wrote:
> Add driver for the clk controller which found in Meson AXG SoC
>
> Note, we deliberately create a seperate source file for the Meson AXG
> series, instead of sharing code with previous GXBB/GXL - the file axg.c
> It would help us maintaining the code more easily.
But this will be the last meson SoC added this way. We need factor the code the
between meson8, gx and axg series since there is a lot of duplication there.
>
> Changes since v1 [1]:
> - rework register definion, use '(offset << 2)' to better match
As previously discussed, please drop these calculations and just write what the
offset actually are. Putting one comment at the top, explaining the translation,
would be nice though.
> the description from data sheet
> - drop "#include dt-bindings/clock/gxbb-aoclkc.h" from dts
> - rebase code to v4.15-rc1
>
> [1]
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005239.html
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005240.html
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005241.html
>
>
> Qiufang Dai (2):
First patch of the series should be adding the compatible documentation, which
is missing here (unless it has gone through another channel and I missed it)
> clk: meson-axg: add clock controller drivers
> arm64: dts: meson-axg: add clock DT info for Meson AXG SoC
>
> arch/arm64/Kconfig.platforms | 1 +
> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 15 +
> drivers/clk/meson/Kconfig | 8 +
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/axg.c | 948
> +++++++++++++++++++++++++++++
> drivers/clk/meson/axg.h | 126 ++++
> include/dt-bindings/clock/axg-clkc.h | 72 +++
> 7 files changed, 1171 insertions(+)
> create mode 100644 drivers/clk/meson/axg.c
> create mode 100644 drivers/clk/meson/axg.h
> create mode 100644 include/dt-bindings/clock/axg-clkc.h
>
^ permalink raw reply
* Re: [PATCH v2 29/35] dt-bindings: nds32 CPU Bindings
From: Mark Rutland @ 2017-11-27 13:42 UTC (permalink / raw)
To: Greentime Hu
Cc: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial, Vincent Chen,
Rick Chen, Zong Li
In-Reply-To: <20a04f4a5b08dcec221e0c511e42ff3df711ae66.1511785528.git.green.hu@gmail.com>
Him
On Mon, Nov 27, 2017 at 08:28:16PM +0800, Greentime Hu wrote:
> From: Greentime Hu <greentime@andestech.com>
>
> This patch adds nds32 CPU binding documents.
>
> Signed-off-by: Vincent Chen <vincentc@andestech.com>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Signed-off-by: Zong Li <zong@andestech.com>
> Signed-off-by: Greentime Hu <greentime@andestech.com>
> ---
> Documentation/devicetree/bindings/nds32/cpus.txt | 32 ++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt
>
> diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt b/Documentation/devicetree/bindings/nds32/cpus.txt
> new file mode 100644
> index 0000000..c302c89
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/nds32/cpus.txt
> @@ -0,0 +1,32 @@
> +* Andestech Processor Binding
> +
> +This binding specifies what properties must be available in the device tree
> +representation of a Andestech Processor Core, which is the root node in the
> +tree.
> +
> +Required properties:
> +
> + - compatible:
> + Usage: required
> + Value type: <string>
> + Definition: should be one of:
> + "andestech,n13"
> + "andestech,n15"
> + "andestech,d15"
> + "andestech,n10"
> + "andestech,d10"
> + "andestech,nds32v3"
Are these specific parts, or architecture versions?
I guess "andestech,nds32v3" is an architecture version, and the rest are
specific parts?
> + - device_type
> + Usage: required
> + Value type: <string>
> + Definition: must be "cpu"
> + - clock-frequency: Contains the clock frequency for CPU, in Hz.
> +
> +* Examples
> +
> +/ {
> + cpu {
> + device_type = "cpu";
> + compatible = "andestech,n13", "andestech,nds32v3";
> + };
This is missing the required clock-frequency property.
There should be a /cpus node, with each CPU listed under that, to align
with the devicetree spec. Even if you never support SMP, there's no
reason to be different from other architectures.
You should have something like:
/ {
cpus {
cpu {
device_type = "cpu";
compatible = "andestech,n13";
clock-frequency = <...>;
};
};
};
Thanks,
Mark.
^ permalink raw reply
* [PATCH v3] ARM: dts: imx6qdl-nitrogen6x: Add SPI NOR partitions
From: Otavio Salvador @ 2017-11-27 13:31 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Gary Bisson, Otavio Salvador, Fabio Estevam,
devicetree-u79uwXL29TY76Z2rM5mHXA, Sascha Hauer,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Mark Rutland,
Russell King, Shawn Guo
This adds the partitions definition for the SPI NOR to provide
backward compatibility with the documented[1] layout used with
Boundary Devices BSP.
1. https://boundarydevices.com/boot-flash-access-linux/
It exports to Linux:
mtd0: bootloader
mtd1: env
mtd2: splash
Signed-off-by: Otavio Salvador <otavio-fKevB0iiKLMBZ+LybsDmbA@public.gmane.org>
---
Changes in v3:
- use lock instead of read-only (Gary Bisson)
Changes in v2:
- rework labels (Fabio Estevam)
- add read-only flags (Fabio Estevam)
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 4bdf29169d2a..f855d802533e 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -276,6 +276,26 @@
compatible = "sst,sst25vf016b", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bootloader";
+ reg = <0x0 0xc0000>;
+ lock;
+ };
+
+ partition@c0000 {
+ label = "env";
+ reg = <0xc0000 0x2000>;
+ lock;
+ };
+
+ partition@c2000 {
+ label = "splash";
+ reg = <0xc2000 0x13e000>;
+ lock;
+ };
};
};
--
2.15.0
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* Re: [PATCH v2] ARM: dts: imx6qdl-nitrogen6x: Add SPI NOR partitions
From: Otavio Salvador @ 2017-11-27 13:28 UTC (permalink / raw)
To: Gary Bisson
Cc: Mark Rutland, devicetree@vger.kernel.org, Otavio Salvador,
Kernel development list, Russell King, Rob Herring, Sascha Hauer,
Fabio Estevam, Shawn Guo, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20171127101739.qs6ws3232hd5qwgv@t450s.lan>
On Mon, Nov 27, 2017 at 8:17 AM, Gary Bisson
<gary.bisson@boundarydevices.com> wrote:
> Hi Otavio,
>
> On Sat, Nov 25, 2017 at 07:55:53AM -0200, Otavio Salvador wrote:
>> On Fri, Nov 24, 2017 at 3:00 PM, Otavio Salvador
>> <otavio@ossystems.com.br> wrote:
>> > This adds the partitions definition for the SPI NOR to provide
>> > backward compatibility with the documented[1] layout used with
>> > Boundary Devices BSP.
>> >
>> > 1. https://boundarydevices.com/boot-flash-access-linux/
>> >
>> > It exports to Linux:
>> >
>> > mtd0: bootloader
>> > mtd1: env
>> > mtd2: splash
>> >
>> > Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
>>
>> After thinking a bit about Fabio's recommendation to use 'read-only'
>> to protect the partitions, I think it'd be better to use 'lock' so it
>> is still possible to write them on Linux but it requires a unlock
>> prior changing it.
>>
>> In my case, I am interested in being capable of upgrading the
>> bootloader from Linux.
>>
>> What people think?
>
> Agreed, I would rather have the lock option, especially for the splash
> and environment.
I will prepare a new patch using the lock option on the three
partitions so we allow the user to change them but knowing it may
break the system.
--
Otavio Salvador O.S. Systems
http://www.ossystems.com.br http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750
^ permalink raw reply
* [PATCH v3 3/6] dt-bindings: display: Add bindings for SGD GKTW70SDAE4SE Panel
From: Neil Armstrong @ 2017-11-27 12:28 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam
Cc: Neil Armstrong, linux-arm-kernel, linux-kernel, devicetree
In-Reply-To: <1511785716-23492-1-git-send-email-narmstrong@baylibre.com>
The GKTW70SDAE4SE is an LVDS display panel.
Their bindings are modelled on the the LVDS panel bindings.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../bindings/display/panel/sgd,gktw70sdae4se.txt | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt
diff --git a/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt b/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt
new file mode 100644
index 0000000..d06644b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt
@@ -0,0 +1,41 @@
+Solomon Goldentek Display GKTW70SDAE4SE LVDS Display Panel
+==========================================================
+
+The GKTW70SDAE4SE is a 7" WVGA TFT-LCD display panel.
+
+These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt
+with the following device-specific properties.
+
+Required properties:
+
+- compatible: Shall contain "sgd,gktw70sdae4se" and "panel-lvds", in that order.
+
+Example
+-------
+
+panel {
+ compatible = "sgd,gktw70sdae4se", "panel-lvds";
+
+ width-mm = <153>;
+ height-mm = <86>;
+
+ data-mapping = "jeida-18";
+
+ panel-timing {
+ clock-frequency = <32000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <39>;
+ hfront-porch = <39>;
+ vback-porch = <29>;
+ vfront-porch = <13>;
+ hsync-len = <47>;
+ vsync-len = <2>;
+ };
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds_encoder>;
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v3 2/6] dt-bindings: Add vendor prefix for Solomon Goldentek Display Corporation
From: Neil Armstrong @ 2017-11-27 12:28 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam
Cc: Neil Armstrong, linux-arm-kernel, linux-kernel, devicetree
In-Reply-To: <1511785716-23492-1-git-send-email-narmstrong@baylibre.com>
Solomon Goldentek Display Corporation is a Taiwanese LCD/LCM manufacturer.
Company Site: http://www.goldentek.com.tw
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 0994bdd..b0d3bef 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -305,6 +305,7 @@ seagate Seagate Technology PLC
semtech Semtech Corporation
sensirion Sensirion AG
sff Small Form Factor Committee
+sgd Solomon Goldentek Display Corporation
sgx SGX Sensortech
sharp Sharp Corporation
shimafuji Shimafuji Electric, Inc.
--
2.7.4
^ permalink raw reply related
* [PATCH v2 35/35] dt-bindings: timer: Add andestech atcpit100 timer binding doc
From: Greentime Hu @ 2017-11-27 12:28 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial
Cc: Rick Chen, green.hu
In-Reply-To: <cover.1511785528.git.green.hu@gmail.com>
From: Rick Chen <rickchen36@gmail.com>
Add a document to describe Andestech atcpit100 timer and
binding information.
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
---
.../bindings/timer/andestech,atcpit100-timer.txt | 33 ++++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
new file mode 100644
index 0000000..b97ff32
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
@@ -0,0 +1,33 @@
+Andestech ATCPIT100 timer
+------------------------------------------------------------------
+ATCPIT100 is a generic IP block from Andes Technology, embedded in
+Andestech AE3XX platforms and other designs.
+
+This timer is a set of compact multi-function timers, which can be
+used as pulse width modulators (PWM) as well as simple timers.
+
+It supports up to 4 PIT channels. Each PIT channel is a
+multi-function timer and provide the following usage scenarios:
+One 32-bit timer
+Two 16-bit timers
+Four 8-bit timers
+One 16-bit PWM
+One 16-bit timer and one 8-bit PWM
+Two 8-bit timer and one 8-bit PWM
+
+Required properties:
+- compatible : Should be "andestech,atcpit100"
+- reg : Address and length of the register set
+- interrupts : Reference to the timer interrupt
+- clocks : a clock to provide the tick rate for "andestech,atcpit100"
+- clock-names : should be "PCLK" for the external tick timer.
+
+Examples:
+
+timer0: timer@f0400000 {
+ compatible = "andestech,atcpit100";
+ reg = <0xf0400000 0x1000>;
+ interrupts = <2 4>;
+ clocks = <&clk_pll>;
+ clock-names = "PCLK";
+};
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 34/35] clocksource/drivers/Kconfig: Support andestech atcpit100 timer
From: Greentime Hu @ 2017-11-27 12:28 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial
Cc: Rick Chen, green.hu
In-Reply-To: <cover.1511785528.git.green.hu@gmail.com>
From: Rick Chen <rickchen36@gmail.com>
Add CLKSRC_ATCPIT100 for Andestech atcpit100 timer selection.
It often be used in Andestech AE3XX platform.
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
---
drivers/clocksource/Kconfig | 6 ++++++
drivers/clocksource/Makefile | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index cc60620..591362a 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -615,4 +615,10 @@ config CLKSRC_ST_LPC
Enable this option to use the Low Power controller timer
as clocksource.
+config CLKSRC_ATCPIT100
+ bool "Clocksource for AE3XX platform" if COMPILE_TEST
+ depends on GENERIC_CLOCKEVENTS && HAS_IOMEM
+ help
+ This option enables support for the Andestech AE3XX platform timers.
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 72711f1..7d072f5 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -75,3 +75,4 @@ obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o
obj-$(CONFIG_H8300_TPU) += h8300_tpu.o
obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
obj-$(CONFIG_X86_NUMACHIP) += numachip.o
+obj-$(CONFIG_CLKSRC_ATCPIT100) += timer-atcpit100.o
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 33/35] clocksource/drivers/atcpit100: Add andestech atcpit100 timer
From: Greentime Hu @ 2017-11-27 12:28 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial
Cc: Rick Chen, green.hu
In-Reply-To: <cover.1511785528.git.green.hu@gmail.com>
From: Rick Chen <rickchen36@gmail.com>
ATCPIT100 is often used on the Andes architecture,
This timer provide 4 PIT channels. Each PIT channel is a
multi-function timer, can be configured as 32,16,8 bit timers
or PWM as well.
For system timer it will set channel 1 32-bit timer0 as clock
source and count downwards until underflow and restart again.
It also set channel 0 32-bit timer0 as clock event and count
downwards until condition match. It will generate an interrupt
for handling periodically.
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
---
drivers/clocksource/timer-atcpit100.c | 247 +++++++++++++++++++++++++++++++++
1 file changed, 247 insertions(+)
create mode 100644 drivers/clocksource/timer-atcpit100.c
diff --git a/drivers/clocksource/timer-atcpit100.c b/drivers/clocksource/timer-atcpit100.c
new file mode 100644
index 0000000..76ddd2f
--- /dev/null
+++ b/drivers/clocksource/timer-atcpit100.c
@@ -0,0 +1,247 @@
+/*
+ * Andestech ATCPIT100 Timer Device Driver Implementation
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ */
+
+#include <linux/irq.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/sched.h>
+#include <linux/sched_clock.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include "timer-of.h"
+
+/*
+ * Definition of register offsets
+ */
+
+/* ID and Revision Register */
+#define ID_REV 0x0
+
+/* Configuration Register */
+#define CFG 0x10
+
+/* Interrupt Enable Register */
+#define INT_EN 0x14
+#define CH_INT_EN(c, i) ((1<<i)<<(4*c))
+#define CH0INT0EN 0x01
+
+/* Interrupt Status Register */
+#define INT_STA 0x18
+#define CH0INT0 0x01
+
+/* Channel Enable Register */
+#define CH_EN 0x1C
+#define CH0TMR0EN 0x1
+#define CH1TMR0EN 0x10
+
+/* Channel 0 , 1 Control Register */
+#define CH0_CTL (0x20)
+#define CH1_CTL (0x20 + 0x10)
+
+/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
+#define APB_CLK BIT(3)
+
+/* Channel mode , bit 0~2 */
+#define TMR_32 0x1
+#define TMR_16 0x2
+#define TMR_8 0x3
+
+/* Channel 0 , 1 Reload Register */
+#define CH0_REL (0x24)
+#define CH1_REL (0x24 + 0x10)
+
+/* Channel 0 , 1 Counter Register */
+#define CH0_CNT (0x28)
+#define CH1_CNT (0x28 + 0x10)
+
+#define TIMER_SYNC_TICKS 3
+
+static void atcpit100_ch1_tmr0_en(void __iomem *base)
+{
+ writel(~0, base + CH1_REL);
+ writel(APB_CLK|TMR_32, base + CH1_CTL);
+}
+
+static void atcpit100_ch0_tmr0_en(void __iomem *base)
+{
+ writel(APB_CLK|TMR_32, base + CH0_CTL);
+}
+
+static void atcpit100_clkevt_time_setup(void __iomem *base, unsigned long delay)
+{
+ writel(delay, base + CH0_CNT);
+ writel(delay, base + CH0_REL);
+}
+
+static void atcpit100_timer_clear_interrupt(void __iomem *base)
+{
+ u32 val;
+
+ val = readl(base + INT_STA);
+ writel(val | CH0INT0, base + INT_STA);
+}
+
+static void atcpit100_clocksource_start(void __iomem *base)
+{
+ u32 val;
+
+ val = readl(base + CH_EN);
+ writel(val | CH1TMR0EN, base + CH_EN);
+}
+
+static void atcpit100_clkevt_time_start(void __iomem *base)
+{
+ u32 val;
+
+ val = readl(base + CH_EN);
+ writel(val | CH0TMR0EN, base + CH_EN);
+}
+
+static void atcpit100_clkevt_time_stop(void __iomem *base)
+{
+ u32 val;
+
+ atcpit100_timer_clear_interrupt(base);
+ val = readl(base + CH_EN);
+ writel(val & ~CH0TMR0EN, base + CH_EN);
+}
+
+static int atcpit100_clkevt_next_event(unsigned long evt,
+ struct clock_event_device *clkevt)
+{
+ struct timer_of *to = to_timer_of(clkevt);
+
+ writel(evt, timer_of_base(to) + CH0_REL);
+
+ return 0;
+}
+
+static int atcpit100_clkevt_set_periodic(struct clock_event_device *evt)
+{
+ struct timer_of *to = to_timer_of(evt);
+
+ atcpit100_clkevt_time_setup(timer_of_base(to), timer_of_period(to));
+ atcpit100_clkevt_time_start(timer_of_base(to));
+
+ return 0;
+}
+static int atcpit100_clkevt_shutdown(struct clock_event_device *evt)
+{
+ struct timer_of *to = to_timer_of(evt);
+
+ atcpit100_clkevt_time_stop(timer_of_base(to));
+
+ return 0;
+}
+static int atcpit100_clkevt_set_oneshot(struct clock_event_device *evt)
+{
+ struct timer_of *to = to_timer_of(evt);
+ u32 val;
+
+ writel(~0x0, timer_of_base(to) + CH0_REL);
+ val = readl(timer_of_base(to) + CH_EN);
+ writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN);
+
+ return 0;
+}
+
+static irqreturn_t atcpit100_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+ struct timer_of *to = to_timer_of(evt);
+
+ atcpit100_timer_clear_interrupt(timer_of_base(to));
+
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static struct timer_of to = {
+ .flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,
+
+ .clkevt = {
+ .name = "atcpit100_tick",
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .set_state_shutdown = atcpit100_clkevt_shutdown,
+ .set_state_periodic = atcpit100_clkevt_set_periodic,
+ .set_state_oneshot = atcpit100_clkevt_set_oneshot,
+ .tick_resume = atcpit100_clkevt_shutdown,
+ .set_next_event = atcpit100_clkevt_next_event,
+ .cpumask = cpu_all_mask,
+ },
+
+ .of_irq = {
+ .handler = atcpit100_timer_interrupt,
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
+ },
+};
+
+static u64 notrace atcpit100_timer_sched_read(void)
+{
+ return ~readl(timer_of_base(&to) + CH1_CNT);
+}
+
+static int __init atcpit100_timer_init(struct device_node *node)
+{
+ int ret;
+ u32 val;
+ void __iomem *base;
+
+ ret = timer_of_init(node, &to);
+ if (ret)
+ return ret;
+
+ base = timer_of_base(&to);
+
+ sched_clock_register(atcpit100_timer_sched_read, 32,
+ timer_of_rate(&to));
+
+ ret = clocksource_mmio_init(base + CH1_CNT,
+ node->name, timer_of_rate(&to), 300, 32,
+ clocksource_mmio_readl_down);
+
+ if (ret) {
+ pr_err("Failed to register clocksource\n");
+ return ret;
+ }
+
+ /* clear channel 0 timer0 interrupt */
+ atcpit100_timer_clear_interrupt(base);
+
+ clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
+ TIMER_SYNC_TICKS, 0xffffffff);
+ atcpit100_ch0_tmr0_en(base);
+ atcpit100_ch1_tmr0_en(base);
+ atcpit100_clocksource_start(base);
+ atcpit100_clkevt_time_start(base);
+
+ /* Enable channel 0 timer0 interrupt */
+ val = readl(base + INT_EN);
+ writel(val | CH0INT0EN, base + INT_EN);
+
+ return ret;
+}
+
+TIMER_OF_DECLARE(atcpit100, "andestech,atcpit100", atcpit100_timer_init);
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 32/35] asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU
From: Greentime Hu @ 2017-11-27 12:28 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial
Cc: green.hu, Vincent Chen
In-Reply-To: <cover.1511785528.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
It allows some architectures to use this generic macro instead of
defining theirs.
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
include/asm-generic/io.h | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index b4531e3..7c6a39e 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -852,7 +852,16 @@ static inline void __iomem *__ioremap(phys_addr_t offset, size_t size,
}
#endif
+#ifndef iounmap
+#define iounmap iounmap
+
+static inline void iounmap(void __iomem *addr)
+{
+}
+#endif
+#endif /* CONFIG_MMU */
#ifndef ioremap_nocache
+void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
#define ioremap_nocache ioremap_nocache
static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size)
{
@@ -884,15 +893,6 @@ static inline void __iomem *ioremap_wt(phys_addr_t offset, size_t size)
}
#endif
-#ifndef iounmap
-#define iounmap iounmap
-
-static inline void iounmap(void __iomem *addr)
-{
-}
-#endif
-#endif /* CONFIG_MMU */
-
#ifdef CONFIG_HAS_IOPORT_MAP
#ifndef CONFIG_GENERIC_IOMAP
#ifndef ioport_map
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 31/35] earlycon: add reg-offset to physical address before mapping
From: Greentime Hu @ 2017-11-27 12:28 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial
Cc: green.hu
In-Reply-To: <cover.1511785528.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
It will get the wrong virtual address because port->mapbase is not added
the correct reg-offset yet. We have to update it before earlycon_map()
is called
---
drivers/tty/serial/earlycon.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
index 98928f0..17dba0a 100644
--- a/drivers/tty/serial/earlycon.c
+++ b/drivers/tty/serial/earlycon.c
@@ -253,11 +253,12 @@ int __init of_setup_earlycon(const struct earlycon_id *match,
}
port->mapbase = addr;
port->uartclk = BASE_BAUD * 16;
- port->membase = earlycon_map(port->mapbase, SZ_4K);
val = of_get_flat_dt_prop(node, "reg-offset", NULL);
if (val)
port->mapbase += be32_to_cpu(*val);
+ port->membase = earlycon_map(port->mapbase, SZ_4K);
+
val = of_get_flat_dt_prop(node, "reg-shift", NULL);
if (val)
port->regshift = be32_to_cpu(*val);
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 30/35] net: faraday add nds32 support.
From: Greentime Hu @ 2017-11-27 12:28 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial
Cc: green.hu
In-Reply-To: <cover.1511785528.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
drivers/net/ethernet/faraday/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/faraday/Kconfig b/drivers/net/ethernet/faraday/Kconfig
index 040c7f1..0ae6e9a 100644
--- a/drivers/net/ethernet/faraday/Kconfig
+++ b/drivers/net/ethernet/faraday/Kconfig
@@ -5,7 +5,7 @@
config NET_VENDOR_FARADAY
bool "Faraday devices"
default y
- depends on ARM
+ depends on ARM || NDS32
---help---
If you have a network (Ethernet) card belonging to this class, say Y.
@@ -18,7 +18,7 @@ if NET_VENDOR_FARADAY
config FTMAC100
tristate "Faraday FTMAC100 10/100 Ethernet support"
- depends on ARM
+ depends on ARM || NDS32
select MII
---help---
This driver supports the FTMAC100 10/100 Ethernet controller
@@ -27,7 +27,7 @@ config FTMAC100
config FTGMAC100
tristate "Faraday FTGMAC100 Gigabit Ethernet support"
- depends on ARM
+ depends on ARM || NDS32
select PHYLIB
---help---
This driver supports the FTGMAC100 Gigabit Ethernet controller
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 29/35] dt-bindings: nds32 CPU Bindings
From: Greentime Hu @ 2017-11-27 12:28 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial
Cc: green.hu, Vincent Chen, Rick Chen, Zong Li
In-Reply-To: <cover.1511785528.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
This patch adds nds32 CPU binding documents.
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
Documentation/devicetree/bindings/nds32/cpus.txt | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt
diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt b/Documentation/devicetree/bindings/nds32/cpus.txt
new file mode 100644
index 0000000..c302c89
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/cpus.txt
@@ -0,0 +1,32 @@
+* Andestech Processor Binding
+
+This binding specifies what properties must be available in the device tree
+representation of a Andestech Processor Core, which is the root node in the
+tree.
+
+Required properties:
+
+ - compatible:
+ Usage: required
+ Value type: <string>
+ Definition: should be one of:
+ "andestech,n13"
+ "andestech,n15"
+ "andestech,d15"
+ "andestech,n10"
+ "andestech,d10"
+ "andestech,nds32v3"
+ - device_type
+ Usage: required
+ Value type: <string>
+ Definition: must be "cpu"
+ - clock-frequency: Contains the clock frequency for CPU, in Hz.
+
+* Examples
+
+/ {
+ cpu {
+ device_type = "cpu";
+ compatible = "andestech,n13", "andestech,nds32v3";
+ };
+};
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 28/35] MAINTAINERS: Add nds32
From: Greentime Hu @ 2017-11-27 12:28 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial
Cc: green.hu
In-Reply-To: <cover.1511785528.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
MAINTAINERS | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2f4e462..20284c8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -857,6 +857,17 @@ X: drivers/iio/*/adjd*
F: drivers/staging/iio/*/ad*
F: drivers/staging/iio/trigger/iio-trig-bfin-timer.c
+ANDES ARCHITECTURE
+M: Greentime Hu <green.hu@gmail.com>
+M: Vincent Chen <deanbo422@gmail.com>
+T: git https://github.com/andestech/linux.git
+S: Supported
+F: arch/nds32
+F: Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
+F: Documentation/devicetree/bindings/nds32
+K: nds32
+N: nds32
+
ANDROID CONFIG FRAGMENTS
M: Rob Herring <robh@kernel.org>
S: Supported
--
1.7.9.5
^ permalink raw reply related
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