* Re: [PATCH] pinctrl: sunxi: add support for Allwinner H6 main pin controller
From: Maxime Ripard @ 2017-11-28 12:13 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Linus Walleij, Chen-Yu Tsai, linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20171128110614.9303-1-icenowy-h8G6r0blFSE@public.gmane.org>
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Hi,
On Tue, Nov 28, 2017 at 07:06:14PM +0800, Icenowy Zheng wrote:
> Allwinner H6 SoC has two pin controllers like other Allwinner SoCs with
> ARISC: one main pin controller (called CPUX-PORT in user manual) and one
> pin controller in the CPUs power domain (called CPUS-PORT in user
> manual).
>
> This commit adds support for the main pin controller in the H6 SoC.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
This looks mostly fine, but we've had issues in the past with pinctrl
drivers submitted without SoC support, and we'll have to support them
forever.
Please resend this as part your upcoming serie to enable the H6.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [linux-sunxi] Re: [PATCH] ARM: dts: sun8i: h3: Add dts file for Libre Computer Board ALL-H3-CC H3 ver.
From: Maxime Ripard @ 2017-11-28 12:11 UTC (permalink / raw)
To: Chen-Yu Tsai; +Cc: devicetree, linux-arm-kernel, linux-sunxi, Corentin Labbe
In-Reply-To: <CAGb2v67dg1dCw+n3aQ1aFqtZXU245v6jQ0E=4onPYjUOpUHjPw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
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Hi,
On Tue, Nov 28, 2017 at 05:26:37PM +0800, Chen-Yu Tsai wrote:
> On Tue, Nov 28, 2017 at 4:43 PM, Maxime Ripard
> <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> > Hi,
> >
> > On Tue, Nov 28, 2017 at 12:12:11PM +0800, Chen-Yu Tsai wrote:
> >> The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
> >> Pi B+ form factor single board computer based on the Allwinner H3 SoC.
> >> The board has 1GB DDR3 SDRAM, provided by 4 2Gb chips. The mounting holes
> >> and connectors are in the exact same position as on the Raspberry Pi B+.
> >>
> >> Raspberry Pi B+ like peripherals supported on this board include:
> >>
> >> - Power input through micro-USB connector (without USB OTG)
> >> - Native 100 Mbps ethernet using the internal PHY, as opposed to
> >> USB-based on the RPi
> >> - 4x USB 2.0 host ports, directly connected to the SoC, as opposed to
> >> being connected through a USB 2.0 hub on the RPi
> >> - TV and audio output on a 3.5mm TRRS jack
> >> - HDMI output
> >> - Micro-SD card slot
> >> - Standard RPi B+ GPIO header, with the standard peripherals routed to
> >> the same pins.
> >>
> >> * 5V, 3.3V power, and ground
> >> * I2C0 on the H3 is routed to I2C1 pins on the RPi header
> >> * I2C1 on the H3 is routed to I2C0 pins on the RPi header
> >> * UART1 on the H3 is routed to UART0 pins on the RPi header
> >> * SPI0 on the H3 is routed to SPI0 pins on the RPi header,
> >> with GPIO pin PA17 replacing the missing Chip Select 1
> >> * I2S1 on the H3 is routed to PCM pins on the RPi header
> >>
> >> - Additional peripherals from the H3 are available on different pins.
> >> These include I2S0, JTAG, PWM1, SPDIF, SPI1, and UART3
> >>
> >> In addition, there are a number of new features:
> >>
> >> - Console UART header
> >> - Consumer IR receiver
> >> - Camera interface (not compatible with RPi)
> >> - Onboard microphone
> >> - eMMC expansion module port
> >> - Heatsink mounting holes
> >>
> >> This patch adds a dts file for this board that enables all "onboard"
> >> peripherals currently supported. This means no display or camera
> >> support.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> >> ---
> >>
> >> There are two other variants [1] of this board, with different SoCs and
> >> DRAM configuration. But the board remains the same, thanks to the SoCs
> >> being pin compatible.
> >>
> >> Do we need different board compatible strings?
> >
> > Yes.
> >
> >> FWIW the soc compatible string already encodes the soc variant, and
> >> the DRAM stuff is handled by the bootloader. The filename also has
> >> the SoC family and chip name. The displayed board model also has
> >> the SoC variant included. The board itself is named "ALL-H3-CC".
> >
> > The point of a board compatible is to identify the way a board
> > behaves. If we ever need to make any quirks for one particular board,
> > we have to have a compatible that uniquely identifies it.
> >
> > However, we can have an intermediate compatible as well to catch all
> > those similar boards.
> >
> > Something like:
> > compatible = "libretech,h3-tritium", "libretech,tritium", "allwinner,sun8i-h3";
>
> compatible = "libretech,all-h3-cc-h3", "libretech,all-h3-cc",
> "allwinner,sun8i-h3";
>
> (See below about the names.) Does that look confusing?
A bit. So they're all going to be called all-h3-cc, even if they don't
sport an H3?
> >
> >> I'm asking as we have the same issue with the Bananapi M2+ [2], where
> >> they've released new variants with different SoCs and DRAM capacities
> >> using the same board. Not sure if they are commercially available though.
> >
> > You can have a look at the way we handled all the q8 tablets that were
> > pretty much in the same case. It's been working quite well.
>
> You mean the sun?i-reference-tablet-design.dtsi files? I'm thinking we
> might not have to go that far. The other variants could have:
>
> #include "sun8i-h3-libretech-all-h3-cc.dts"
> #include "sun8i-h5.dtsi"
>
> And then override the board compatible and model.
>
> Might not work. I'm not sure at this moment.
It's proven to work quite well with the Q8 stuff. One thing that you
really want to pay attention to is that you wouldn't want to "leak"
devices from the H3 into the H5. I have the feeling that with that
kind of construct we will eventually, and this is much harder to do
with the Q8 stuff.
> >> + gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
> >> + };
> >> + };
> >> +
> >> + gpio_keys {
> >> + compatible = "gpio-keys";
> >> +
> >> + recovery {
> >> + label = "recovery";
> >> + linux,code = <BTN_0>;
> >
> > How did you pick that keycode?
>
> It's the same as the Orange Pis. The board however does mark it as
> "Power Key". However the H3 (on mainline) does not have the ability
> to come back up once powered down, nor do we have the ability to
> power it off right now. (We could turn it off using "gpio-poweroff",
> though I'm sensing the GPIO usage would conflict with the regulator
> drivers.) I'll ask about the intended usage and behavior.
Ok, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH v5 2/2] media: i2c: Add the ov7740 image sensor driver
From: Sakari Ailus @ 2017-11-28 12:06 UTC (permalink / raw)
To: Wenyou Yang
Cc: Mauro Carvalho Chehab, Rob Herring, Mark Rutland, linux-kernel,
Nicolas Ferre, devicetree, Jonathan Corbet, Hans Verkuil,
linux-arm-kernel, Linux Media Mailing List, Songjun Wu
In-Reply-To: <20171128052259.4957-3-wenyou.yang@microchip.com>
Hi Wenyou,
Thanks for the patch. Some comments below.
On Tue, Nov 28, 2017 at 01:22:59PM +0800, Wenyou Yang wrote:
> The ov7740 (color) image sensor is a high performance VGA CMOS
> image snesor, which supports for output formats: RAW RGB and YUV
> and image sizes: VGA, and QVGA, CIF and any size smaller.
>
> Signed-off-by: Songjun Wu <songjun.wu@microchip.com>
> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
> ---
>
> Changes in v5:
> - Squash the driver and MAINTAINERS entry patches to one.
> - Precede the driver patch with the bindings patch.
>
> Changes in v4:
> - Assign 'val' a initial value to avoid warning: 'val' may be
> used uninitialized.
> - Rename REG_REG15 to avoid warning: "REG_REG15" redefined.
>
> Changes in v3:
> - Put the MAINTAINERS change to a separate patch.
>
> Changes in v2:
> - Split off the bindings into a separate patch.
> - Add a new entry to the MAINTAINERS file.
>
> MAINTAINERS | 8 +
> drivers/media/i2c/Kconfig | 8 +
> drivers/media/i2c/Makefile | 1 +
> drivers/media/i2c/ov7740.c | 1220 ++++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 1237 insertions(+)
> create mode 100644 drivers/media/i2c/ov7740.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index aa71ab52fd76..19086a073ae9 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -10053,6 +10053,14 @@ S: Maintained
> F: drivers/media/i2c/ov7670.c
> F: Documentation/devicetree/bindings/media/i2c/ov7670.txt
>
> +OMNIVISION OV7740 SENSOR DRIVER
> +M: Wenyou Yang <wenyou.yang@microchip.com>
> +L: linux-media@vger.kernel.org
> +T: git git://linuxtv.org/media_tree.git
> +S: Maintained
> +F: drivers/media/i2c/ov7740.c
> +F: Documentation/devicetree/bindings/media/i2c/ov7740.txt
> +
> ONENAND FLASH DRIVER
> M: Kyungmin Park <kyungmin.park@samsung.com>
> L: linux-mtd@lists.infradead.org
> diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
> index 3c6d6428f525..ac484bb82fae 100644
> --- a/drivers/media/i2c/Kconfig
> +++ b/drivers/media/i2c/Kconfig
> @@ -665,6 +665,14 @@ config VIDEO_OV7670
> OV7670 VGA camera. It currently only works with the M88ALP01
> controller.
>
> +config VIDEO_OV7740
> + tristate "OmniVision OV7740 sensor support"
> + depends on I2C && VIDEO_V4L2
> + depends on MEDIA_CAMERA_SUPPORT
> + ---help---
> + This is a Video4Linux2 sensor-level driver for the OmniVision
> + OV7740 VGA camera sensor.
> +
> config VIDEO_OV9650
> tristate "OmniVision OV9650/OV9652 sensor support"
> depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
> diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
> index 548a9efce966..9b19ec7fcaf4 100644
> --- a/drivers/media/i2c/Makefile
> +++ b/drivers/media/i2c/Makefile
> @@ -68,6 +68,7 @@ obj-$(CONFIG_VIDEO_OV5670) += ov5670.o
> obj-$(CONFIG_VIDEO_OV6650) += ov6650.o
> obj-$(CONFIG_VIDEO_OV7640) += ov7640.o
> obj-$(CONFIG_VIDEO_OV7670) += ov7670.o
> +obj-$(CONFIG_VIDEO_OV7740) += ov7740.o
> obj-$(CONFIG_VIDEO_OV9650) += ov9650.o
> obj-$(CONFIG_VIDEO_OV13858) += ov13858.o
> obj-$(CONFIG_VIDEO_MT9M032) += mt9m032.o
> diff --git a/drivers/media/i2c/ov7740.c b/drivers/media/i2c/ov7740.c
> new file mode 100644
> index 000000000000..b2ec015bf3f6
> --- /dev/null
> +++ b/drivers/media/i2c/ov7740.c
> @@ -0,0 +1,1220 @@
> +/*
> + * Copyright (c) 2017 Microchip Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License version
> + * 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/gpio.h>
> +#include <linux/i2c.h>
> +#include <linux/init.h>
Do you need init.h?
> +#include <linux/module.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <media/v4l2-ctrls.h>
> +#include <media/v4l2-event.h>
> +#include <media/v4l2-image-sizes.h>
> +#include <media/v4l2-subdev.h>
> +
> +#define REG_OUTSIZE_LSB 0x34
> +
> +/* OV7740 register tables */
> +#define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
> +#define REG_BGAIN 0x01 /* blue gain */
> +#define REG_RGAIN 0x02 /* red gain */
> +#define REG_GGAIN 0x03 /* green gain */
> +#define REG_REG04 0x04 /* analog setting, dont change*/
> +#define REG_BAVG 0x05 /* b channel average */
> +#define REG_GAVG 0x06 /* g channel average */
> +#define REG_RAVG 0x07 /* r channel average */
> +
> +#define REG_REG0C 0x0C /* filp enable */
> +#define REG0C_IMG_FLIP 0x80
> +#define REG0C_IMG_MIRROR 0x40
> +
> +#define REG_REG0E 0x0E /* blc line */
> +#define REG_HAEC 0x0F /* auto exposure cntrl */
> +#define REG_AEC 0x10 /* auto exposure cntrl */
> +
> +#define REG_CLK 0x11 /* Clock control */
> +#define REG_REG55 0x55 /* Clock PLL DIV/PreDiv */
> +
> +#define REG_REG12 0x12
> +
> +#define REG_REG13 0x13 /* auto/manual AGC, AEC, Write Balance*/
> +#define REG13_AEC_EN 0x01
> +#define REG13_AGC_EN 0x04
> +
> +#define REG_REG14 0x14
> +#define REG_CTRL15 0x15
> +#define REG15_GAIN_MSB 0x03
> +
> +#define REG_REG16 0x16
> +
> +#define REG_MIDH 0x1C /* manufacture id byte */
> +#define REG_MIDL 0x1D /* manufacture id byre */
> +#define REG_PIDH 0x0A /* Product ID MSB */
> +#define REG_PIDL 0x0B /* Product ID LSB */
> +
> +#define REG_84 0x84 /* lots of stuff */
> +#define REG_REG38 0x38 /* sub-addr */
> +
> +#define REG_AHSTART 0x17 /* Horiz start high bits */
> +#define REG_AHSIZE 0x18
> +#define REG_AVSTART 0x19 /* Vert start high bits */
> +#define REG_AVSIZE 0x1A
> +#define REG_PSHFT 0x1b /* Pixel delay after HREF */
> +
> +#define REG_HOUTSIZE 0x31
> +#define REG_VOUTSIZE 0x32
> +#define REG_HVSIZEOFF 0x33
> +#define REG_REG34 0x34 /* DSP output size H/V LSB*/
> +
> +#define REG_ISP_CTRL00 0x80
> +#define ISPCTRL00_AWB_EN 0x10
> +#define ISPCTRL00_AWB_GAIN_EN 0x04
> +
> +#define REG_YGAIN 0xE2 /* ygain for contrast control */
> +
> +#define REG_YBRIGHT 0xE3
> +#define REG_SGNSET 0xE4
> +#define SGNSET_YBRIGHT_MASK 0x08
> +
> +#define REG_USAT 0xDD
> +#define REG_VSAT 0xDE
> +
> +
> +struct ov7740 {
> + struct v4l2_subdev subdev;
> +#if defined(CONFIG_MEDIA_CONTROLLER)
> + struct media_pad pad;
> +#endif
> + struct v4l2_mbus_framefmt format;
> + struct ov7740_pixfmt *fmt; /* Current format */
> + struct ov7740_framesize *frmsize;
> + struct regmap *regmap;
> + struct clk *xvclk;
> + struct v4l2_ctrl_handler ctrl_handler;
> + struct {
> + /* gain cluster */
> + struct v4l2_ctrl *auto_gain;
> + struct v4l2_ctrl *gain;
> + };
> + struct {
> + struct v4l2_ctrl *auto_wb;
> + struct v4l2_ctrl *blue_balance;
> + struct v4l2_ctrl *red_balance;
> + };
> + struct {
> + struct v4l2_ctrl *hflip;
> + struct v4l2_ctrl *vflip;
> + };
> + struct {
> + /* exposure cluster */
> + struct v4l2_ctrl *auto_exposure;
> + struct v4l2_ctrl *exposure;
> + };
> + struct {
> + /* saturation/hue cluster */
> + struct v4l2_ctrl *saturation;
> + struct v4l2_ctrl *hue;
> + };
> + struct v4l2_ctrl *brightness;
> + struct v4l2_ctrl *contrast;
> +
> + struct mutex mutex; /* To serialize asynchronus callbacks */
> + bool streaming; /* Streaming on/off */
> +
> + struct gpio_desc *resetb_gpio;
> + struct gpio_desc *pwdn_gpio;
> +};
> +
> +struct ov7740_pixfmt {
> + u32 mbus_code;
> + enum v4l2_colorspace colorspace;
> + const struct reg_sequence *regs;
> + u32 reg_num;
> +};
> +
> +struct ov7740_framesize {
> + u16 width;
> + u16 height;
> + const struct reg_sequence *regs;
> + u32 reg_num;
> +};
> +
Are the register lists below for a particular external clock frequency?
> +static const struct reg_sequence ov7740_vga[] = {
> + {0x55, 0x40},
> + {0x11, 0x02},
> +
> + {0xd5, 0x10},
> + {0x0c, 0x12},
> + {0x0d, 0x34},
> + {0x17, 0x25},
> + {0x18, 0xa0},
> + {0x19, 0x03},
> + {0x1a, 0xf0},
> + {0x1b, 0x89},
> + {0x22, 0x03},
> + {0x29, 0x18},
> + {0x2b, 0xf8},
> + {0x2c, 0x01},
> + {REG_HOUTSIZE, 0xa0},
> + {REG_VOUTSIZE, 0xf0},
> + {0x33, 0xc4},
> + {REG_OUTSIZE_LSB, 0x0},
> + {0x35, 0x05},
> + //{0x36, 0x3f},
Why?
> + {0x04, 0x60},
> + {0x27, 0x80},
> + {0x3d, 0x0f},
> + {0x3e, 0x80},
> + {0x3f, 0x40},
> + {0x40, 0x7f},
> + {0x41, 0x6a},
> + {0x42, 0x29},
> + {0x44, 0x22},
> + {0x45, 0x41},
> + {0x47, 0x02},
> + {0x49, 0x64},
> + {0x4a, 0xa1},
> + {0x4b, 0x40},
> + {0x4c, 0x1a},
> + {0x4d, 0x50},
> + {0x4e, 0x13},
> + {0x64, 0x00},
> + {0x67, 0x88},
> + {0x68, 0x1a},
> +
> + {0x14, 0x28},
> + {0x24, 0x3c},
> + {0x25, 0x30},
> + {0x26, 0x72},
> + {0x50, 0x97},
> + {0x51, 0x1f},
> + {0x52, 0x00},
> + {0x53, 0x00},
> + {0x20, 0x00},
> + {0x21, 0xcf},
> + {0x50, 0x4b},
> + {0x38, 0x14},
> + {0xe9, 0x00},
> + {0x56, 0x55},
> + {0x57, 0xff},
> + {0x58, 0xff},
> + {0x59, 0xff},
> + {0x5f, 0x04},
> + {0xec, 0x00},
> + {0x13, 0xff},
> +
> + //{0x80,0x7f},
> + {0x81, 0x3f},
> + {0x82, 0x32},
> + //{0x83, 0x01},
Yes, but why?
> + {0x38, 0x11},
> + {0x84, 0x70},
> + {0x85, 0x00},
> + {0x86, 0x03},
> + {0x87, 0x01},
> + {0x88, 0x05},
> + {0x89, 0x30},
> + {0x8d, 0x30},
> + {0x8f, 0x85},
> + {0x93, 0x30},
> + {0x95, 0x85},
> + {0x99, 0x30},
> + {0x9b, 0x85},
> +
> + {0x9c, 0x08},
> + {0x9d, 0x12},
> + {0x9e, 0x23},
> + {0x9f, 0x45},
> + {0xa0, 0x55},
> + {0xa1, 0x64},
> + {0xa2, 0x72},
> + {0xa3, 0x7f},
> + {0xa4, 0x8b},
> + {0xa5, 0x95},
> + {0xa6, 0xa7},
> + {0xa7, 0xb5},
> + {0xa8, 0xcb},
> + {0xa9, 0xdd},
> + {0xaa, 0xec},
> + {0xab, 0x1a},
> +
> + {0xce, 0x78},
> + {0xcf, 0x6e},
> + {0xd0, 0x0a},
> + {0xd1, 0x0c},
> + {0xd2, 0x84},
> + {0xd3, 0x90},
> + {0xd4, 0x1e},
> +
> + {0x5a, 0x24},
> + {0x5b, 0x1f},
> + {0x5c, 0x88},
> + {0x5d, 0x60},
> +
> + {0xac, 0x6e},
> + {0xbe, 0xff},
> + {0xbf, 0x00},
> +
> + {0x0f, 0x1d},
> + {0x0f, 0x1f},
> +};
> +
> +static struct ov7740_framesize ov7740_framesizes[] = {
const?
Same for a number of structs below.
> + {
> + .width = VGA_WIDTH,
> + .height = VGA_HEIGHT,
> + .regs = ov7740_vga,
> + .reg_num = ARRAY_SIZE(ov7740_vga),
> + },
> +};
> +
> +#ifdef CONFIG_VIDEO_ADV_DEBUG
> +static int ov7740_get_register(struct v4l2_subdev *sd,
> + struct v4l2_dbg_register *reg)
> +{
> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
> + struct regmap *regmap = ov7740->regmap;
> + unsigned int val = 0;
> + int ret;
> +
> + ret = regmap_read(regmap, reg->reg & 0xff, &val);
> + reg->val = val;
> + reg->size = 1;
> +
> + return 0;
> +}
> +
> +static int ov7740_set_register(struct v4l2_subdev *sd,
> + const struct v4l2_dbg_register *reg)
> +{
> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
> + struct regmap *regmap = ov7740->regmap;
> +
> + regmap_write(regmap, reg->reg & 0xff, reg->val & 0xff);
> +
> + return 0;
> +}
> +#endif
> +
> +static int ov7740_set_power(struct v4l2_subdev *sd, int on)
> +{
> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
> +
> + if (ov7740->pwdn_gpio)
> + gpiod_direction_output(ov7740->pwdn_gpio, !on);
> + if (on && ov7740->resetb_gpio) {
> + gpiod_set_value(ov7740->resetb_gpio, 1);
> + usleep_range(500, 1000);
> + gpiod_set_value(ov7740->resetb_gpio, 0);
> + usleep_range(3000, 5000);
> + }
> +
> + return 0;
> +}
> +
> +static struct v4l2_subdev_core_ops ov7740_subdev_core_ops = {
> + .log_status = v4l2_ctrl_subdev_log_status,
> +#ifdef CONFIG_VIDEO_ADV_DEBUG
> + .g_register = ov7740_get_register,
> + .s_register = ov7740_set_register,
> +#endif
> + .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
> + .unsubscribe_event = v4l2_event_subdev_unsubscribe,
> +};
> +
> +static int ov7740_set_white_balance(struct ov7740 *ov7740, int awb)
> +{
> + struct regmap *regmap = ov7740->regmap;
> + unsigned int value;
> + int ret;
> +
> + ret = regmap_read(regmap, REG_ISP_CTRL00, &value);
> + if (!ret) {
> + if (awb)
> + value |= (ISPCTRL00_AWB_EN | ISPCTRL00_AWB_GAIN_EN);
> + else
> + value &= ~(ISPCTRL00_AWB_EN | ISPCTRL00_AWB_GAIN_EN);
> + ret = regmap_write(regmap, REG_ISP_CTRL00, value);
> + if (ret)
> + return ret;
> + }
> +
> + if (!awb) {
> + ret = regmap_write(regmap, REG_BGAIN,
> + ov7740->blue_balance->val);
> + if (ret)
> + return ret;
> +
> + ret = regmap_write(regmap, REG_RGAIN, ov7740->red_balance->val);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int ov7740_set_saturation(struct regmap *regmap, int value)
> +{
> + int ret;
> +
> + ret = regmap_write(regmap, REG_USAT, (unsigned char)value);
ret is not checked.
> + ret = regmap_write(regmap, REG_VSAT, (unsigned char)value);
> +
> + return ret;
> +}
> +
> +static int ov7740_set_gain(struct regmap *regmap, int value)
> +{
> + int ret;
> +
> + ret = regmap_write(regmap, REG_GAIN, value & 0xff);
> + if (ret)
> + return ret;
> +
> + ret = regmap_update_bits(regmap, REG_CTRL15,
> + REG15_GAIN_MSB, (value >> 8) & 0x3);
> + if (!ret)
> + ret = regmap_update_bits(regmap, REG_REG13, REG13_AGC_EN, 0);
> +
> + return ret;
> +}
> +
> +static int ov7740_set_autogain(struct regmap *regmap, int value)
> +{
> + unsigned int reg;
> + int ret;
> +
> + ret = regmap_read(regmap, REG_REG13, ®);
> + if (ret)
> + return ret;
> + if (value)
> + reg |= REG13_AGC_EN;
> + else
> + reg &= ~REG13_AGC_EN;
> + return regmap_write(regmap, REG_REG13, reg);
> +}
> +
> +static int ov7740_set_brightness(struct regmap *regmap, int value)
> +{
> + /* Turn off AEC/AGC */
> + regmap_update_bits(regmap, REG_REG13, REG13_AEC_EN, 0);
> + regmap_update_bits(regmap, REG_REG13, REG13_AGC_EN, 0);
> +
> + if (value >= 0) {
> + regmap_write(regmap, REG_YBRIGHT, (unsigned char)value);
> + regmap_update_bits(regmap, REG_SGNSET, SGNSET_YBRIGHT_MASK, 0);
> + } else{
> + regmap_write(regmap, REG_YBRIGHT, (unsigned char)(-value));
> + regmap_update_bits(regmap, REG_SGNSET, SGNSET_YBRIGHT_MASK, 1);
> + }
> +
> + return 0;
> +}
> +
> +static int ov7740_set_contrast(struct regmap *regmap, int value)
> +{
> + return regmap_write(regmap, REG_YGAIN, (unsigned char)value);
> +}
> +
> +static int ov7740_get_gain(struct ov7740 *ov7740, struct v4l2_ctrl *ctrl)
> +{
> + struct regmap *regmap = ov7740->regmap;
> + unsigned int value0, value1;
> + int ret;
> +
> + if (!ctrl->val)
> + return 0;
> +
> + ret = regmap_read(regmap, REG_GAIN, &value0);
> + if (ret)
> + return ret;
> + ret = regmap_read(regmap, REG_CTRL15, &value1);
> + if (ret)
> + return ret;
> +
> + ov7740->gain->val = (value1 << 8) | (value0 & 0xff);
> +
> + return 0;
> +}
> +
> +static int ov7740_set_exp(struct regmap *regmap, int value)
> +{
> + int ret;
> +
> + /* Turn off AEC/AGC */
> + ret = regmap_update_bits(regmap, REG_REG13,
> + REG13_AEC_EN | REG13_AGC_EN, 0);
> + if (ret)
> + return ret;
> +
> + ret = regmap_write(regmap, REG_AEC, (unsigned char)value);
> + if (ret)
> + return ret;
> +
> + return regmap_write(regmap, REG_HAEC, (unsigned char)(value >> 8));
> +}
> +
> +static int ov7740_set_autoexp(struct regmap *regmap,
> + enum v4l2_exposure_auto_type value)
> +{
> + unsigned int reg;
> + int ret;
> +
> + ret = regmap_read(regmap, REG_REG13, ®);
> + if (!ret) {
> + if (value == V4L2_EXPOSURE_AUTO)
> + reg |= (REG13_AEC_EN | REG13_AGC_EN);
> + else
> + reg &= ~(REG13_AEC_EN | REG13_AGC_EN);
> + ret = regmap_write(regmap, REG_REG13, reg);
> + }
> +
> + return ret;
> +}
> +
> +
> +static int ov7740_get_volatile_ctrl(struct v4l2_ctrl *ctrl)
> +{
> + struct ov7740 *ov7740 = container_of(ctrl->handler,
> + struct ov7740, ctrl_handler);
> + int ret;
> +
> + switch (ctrl->id) {
> + case V4L2_CID_AUTOGAIN:
> + ret = ov7740_get_gain(ov7740, ctrl);
> + break;
> + default:
> + ret = -EINVAL;
> + break;
> + }
> + return ret;
> +}
> +
> +static int ov7740_set_ctrl(struct v4l2_ctrl *ctrl)
> +{
> + struct ov7740 *ov7740 = container_of(ctrl->handler,
> + struct ov7740, ctrl_handler);
> + struct i2c_client *client = v4l2_get_subdevdata(&ov7740->subdev);
> + struct regmap *regmap = ov7740->regmap;
> + int ret;
> + u8 val = 0;
> +
> + if (pm_runtime_get_if_in_use(&client->dev) <= 0)
> + return 0;
> +
> + switch (ctrl->id) {
> + case V4L2_CID_AUTO_WHITE_BALANCE:
> + ret = ov7740_set_white_balance(ov7740, ctrl->val);
> + break;
> + case V4L2_CID_SATURATION:
> + ret = ov7740_set_saturation(regmap, ctrl->val);
> + break;
> + case V4L2_CID_BRIGHTNESS:
> + ret = ov7740_set_brightness(regmap, ctrl->val);
> + break;
> + case V4L2_CID_CONTRAST:
> + ret = ov7740_set_contrast(regmap, ctrl->val);
> + break;
> + case V4L2_CID_VFLIP:
> + ret = regmap_update_bits(regmap, REG_REG0C,
> + REG0C_IMG_FLIP, val);
> + break;
> + case V4L2_CID_HFLIP:
> + val = ctrl->val ? REG0C_IMG_MIRROR : 0x00;
> + ret = regmap_update_bits(regmap, REG_REG0C,
> + REG0C_IMG_MIRROR, val);
> + break;
> + case V4L2_CID_AUTOGAIN:
> + if (!ctrl->val)
> + return ov7740_set_gain(regmap, ov7740->gain->val);
> +
> + ret = ov7740_set_autogain(regmap, ctrl->val);
> + break;
> +
> + case V4L2_CID_EXPOSURE_AUTO:
> + if (ctrl->val == V4L2_EXPOSURE_MANUAL)
> + return ov7740_set_exp(regmap, ov7740->exposure->val);
> +
> + ret = ov7740_set_autoexp(regmap, ctrl->val);
> + break;
> + default:
> + ret = -EINVAL;
> + break;
> + }
> +
> + pm_runtime_put(&client->dev);
> +
> + return ret;
> +}
> +
> +static const struct v4l2_ctrl_ops ov7740_ctrl_ops = {
> + .g_volatile_ctrl = ov7740_get_volatile_ctrl,
> + .s_ctrl = ov7740_set_ctrl,
> +};
> +
> +static int ov7740_start_streaming(struct ov7740 *ov7740)
> +{
> + int ret;
> +
> + /* Apply customized values from user */
> + ret = __v4l2_ctrl_handler_setup(ov7740->subdev.ctrl_handler);
> + if (ret)
> + return ret;
return __v4l2_ctrl_handler_setup(...);
You could as well move this to where it's being called, there's a single
instance.
That would make it easier to see that the sensor is probably starting the
stream based on its power on or mode register list. Shouldn't you set the
controls before starting streaming?
> +
> + return 0;
> +}
> +static int ov7740_set_stream(struct v4l2_subdev *sd, int enable)
> +{
> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
> + struct i2c_client *client = v4l2_get_subdevdata(sd);
> + int ret = 0;
> +
> + mutex_lock(&ov7740->mutex);
> + if (ov7740->streaming == enable) {
> + mutex_unlock(&ov7740->mutex);
> + return 0;
> + }
> +
> + if (enable) {
> + ret = pm_runtime_get_sync(&client->dev);
> + if (ret < 0) {
> + pm_runtime_put_noidle(&client->dev);
> + goto err_unlock;
> + }
> +
> + ret = ov7740_start_streaming(ov7740);
> + if (ret)
> + goto err_rpm_put;
> + } else {
> + pm_runtime_put(&client->dev);
> + }
> +
> + ov7740->streaming = enable;
> +
> + mutex_unlock(&ov7740->mutex);
> + return ret;
> +
> +err_rpm_put:
> + pm_runtime_put(&client->dev);
> +err_unlock:
> + mutex_unlock(&ov7740->mutex);
> + return ret;
> +}
> +
> +static int ov7740_get_parm(struct v4l2_subdev *sd,
> + struct v4l2_streamparm *parms)
> +{
> + struct v4l2_captureparm *cp = &parms->parm.capture;
> + struct v4l2_fract *tpf = &cp->timeperframe;
> +
> + if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
> + return -EINVAL;
> +
> + memset(cp, 0, sizeof(struct v4l2_captureparm));
> + cp->capability = V4L2_CAP_TIMEPERFRAME;
> +
> + tpf->numerator = 1;
> + tpf->denominator = 60;
You implement also [gs]_frame_interval in pad ops. Do you have a need for
this?
It'd be better if sensor drivers just implemented one of these APIs to
select the frame interval ([gs]_frame_interval), not both.
> +
> + return 0;
> +}
> +
> +static int ov7740_set_parm(struct v4l2_subdev *sd,
> + struct v4l2_streamparm *parms)
> +{
> + struct v4l2_captureparm *cp = &parms->parm.capture;
> + struct v4l2_fract *tpf = &cp->timeperframe;
> +
> + if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
> + return -EINVAL;
> + if (cp->extendedmode != 0)
> + return -EINVAL;
> +
> + cp->capability = V4L2_CAP_TIMEPERFRAME;
> +
> + tpf->numerator = 1;
> + tpf->denominator = 60;
> +
> + return 0;
> +}
> +
> +static struct v4l2_subdev_video_ops ov7740_subdev_video_ops = {
const?
> + .s_stream = ov7740_set_stream,
> + .s_parm = ov7740_set_parm,
> + .g_parm = ov7740_get_parm,
> +};
> +
> +static const struct reg_sequence ov7740_format_yuyv[] = {
> + {0x12, 0x00},
> + {0x36, 0x3f},
> + {0x80, 0x7f},
> + {0x83, 0x01},
> +};
> +
> +static const struct reg_sequence ov7740_format_bggr8[] = {
> + {0x36, 0x2f},
> + {0x80, 0x01},
> + {0x83, 0x04},
> +};
> +
> +static struct ov7740_pixfmt ov7740_formats[] = {
> + {
> + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + .regs = ov7740_format_yuyv,
> + .reg_num = ARRAY_SIZE(ov7740_format_yuyv),
> + },
> + {
> + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + .regs = ov7740_format_bggr8,
> + .reg_num = ARRAY_SIZE(ov7740_format_bggr8),
> + }
> +};
> +#define N_OV7740_FMTS ARRAY_SIZE(ov7740_formats)
> +
> +static int ov7740_enum_mbus_code(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_mbus_code_enum *code)
> +{
> + if (code->pad || code->index >= N_OV7740_FMTS)
> + return -EINVAL;
> +
> + code->code = ov7740_formats[code->index].mbus_code;
> +
> + return 0;
> +}
> +
> +static int ov7740_enum_frame_interval(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_frame_interval_enum *fie)
> +{
> + if (fie->pad)
> + return -EINVAL;
> +
> + if (fie->index >= 1)
> + return -EINVAL;
> +
> + if ((fie->width != VGA_WIDTH) || (fie->height != VGA_HEIGHT))
> + return -EINVAL;
> +
> + fie->interval.numerator = 1;
> + fie->interval.denominator = 60;
> +
> + return 0;
> +}
> +
> +static int ov7740_enum_frame_size(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_frame_size_enum *fse)
> +{
> + if (fse->pad)
> + return -EINVAL;
> +
> + if (fse->index > 0)
> + return -EINVAL;
> +
> + fse->min_width = fse->max_width = VGA_WIDTH;
> + fse->min_height = fse->max_height = VGA_HEIGHT;
> +
> + return 0;
> +}
> +
> +static int ov7740_try_fmt_internal(struct v4l2_subdev *sd,
> + struct v4l2_mbus_framefmt *fmt,
> + struct ov7740_pixfmt **ret_fmt,
> + struct ov7740_framesize **ret_frmsize)
> +{
> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
> + struct ov7740_framesize *fsize = &ov7740_framesizes[0];
> + int index, i;
> +
> + for (index = 0; index < N_OV7740_FMTS; index++) {
> + if (ov7740_formats[index].mbus_code == fmt->code)
> + break;
> + }
> + if (index >= N_OV7740_FMTS) {
> + /* default to first format */
> + index = 0;
> + fmt->code = ov7740_formats[0].mbus_code;
> + }
> + if (ret_fmt != NULL)
> + *ret_fmt = ov7740_formats + index;
> +
> + for (i = 0; i < ARRAY_SIZE(ov7740_framesizes); i++) {
> + if ((fsize->width >= fmt->width) &&
> + (fsize->height >= fmt->height)) {
> + fmt->width = fsize->width;
> + fmt->height = fsize->height;
> + break;
> + }
> +
> + fsize++;
> + }
> +
> + if (ret_frmsize != NULL)
> + *ret_frmsize = fsize;
> +
> + fmt->field = V4L2_FIELD_NONE;
> + fmt->colorspace = ov7740_formats[index].colorspace;
> +
> + ov7740->format = *fmt;
> +
> + return 0;
> +}
> +
> +static int ov7740_set_fmt(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_format *format)
> +{
> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
> + struct ov7740_pixfmt *ovfmt;
> + struct ov7740_framesize *fsize;
> +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
> + struct v4l2_mbus_framefmt *mbus_fmt;
> +#endif
> + int ret;
> +
> + mutex_lock(&ov7740->mutex);
> + if (format->pad) {
> + ret = -EINVAL;
> + goto error;
> + }
> +
> + if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
> + ret = ov7740_try_fmt_internal(sd, &format->format, NULL, NULL);
> + if (ret)
> + goto error;
> +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
> + mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
> + *mbus_fmt = format->format;
> +
> + mutex_unlock(&ov7740->mutex);
> + return 0;
> +#else
> + ret = -ENOTTY;
> + goto error;
> +#endif
> + }
> +
> + ret = ov7740_try_fmt_internal(sd, &format->format, &ovfmt, &fsize);
> + if (ret)
> + goto error;
> +
> + if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
> + regmap_multi_reg_write(ov7740->regmap,
> + ovfmt->regs, ovfmt->reg_num);
What if streaming is started without calling set_fmt after the device is
powered on?
These should probably be written when streaming is started.
> +
> + regmap_multi_reg_write(ov7740->regmap,
> + fsize->regs, fsize->reg_num);
> + }
> +
> + ov7740->fmt = ovfmt;
> +
> + mutex_unlock(&ov7740->mutex);
> + return 0;
> +
> +error:
> + mutex_unlock(&ov7740->mutex);
> + return ret;
> +}
> +
> +static int ov7740_get_fmt(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_format *format)
> +{
> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
> +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
> + struct v4l2_mbus_framefmt *mbus_fmt;
> +#endif
> + int ret = 0;
> +
> + mutex_lock(&ov7740->mutex);
> + if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
> +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
> + mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, 0);
> + format->format = *mbus_fmt;
> + ret = 0;
> +#else
> + ret = -ENOTTY;
> +#endif
> + } else {
> + format->format = ov7740->format;
> + }
> + mutex_unlock(&ov7740->mutex);
> +
> + return ret;
> +}
> +
> +static const struct v4l2_subdev_pad_ops ov7740_subdev_pad_ops = {
> + .enum_frame_interval = ov7740_enum_frame_interval,
> + .enum_frame_size = ov7740_enum_frame_size,
> + .enum_mbus_code = ov7740_enum_mbus_code,
> + .get_fmt = ov7740_get_fmt,
> + .set_fmt = ov7740_set_fmt,
> +};
> +
> +static struct v4l2_subdev_ops ov7740_subdev_ops = {
> + .core = &ov7740_subdev_core_ops,
> + .video = &ov7740_subdev_video_ops,
> + .pad = &ov7740_subdev_pad_ops,
> +};
> +
> +static void ov7740_get_default_format(struct v4l2_subdev *sd,
> + struct v4l2_mbus_framefmt *format)
> +{
> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
> +
> + format->width = ov7740->frmsize->width;
> + format->height = ov7740->frmsize->height;
> + format->colorspace = ov7740->fmt->colorspace;
> + format->code = ov7740->fmt->mbus_code;
> + format->field = V4L2_FIELD_NONE;
> +}
> +
> +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
> +static int ov7740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
> +{
> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
> + struct v4l2_mbus_framefmt *format =
> + v4l2_subdev_get_try_format(sd, fh->pad, 0);
> +
> + mutex_lock(&ov7740->mutex);
> + ov7740_get_default_format(sd, format);
> + mutex_unlock(&ov7740->mutex);
> +
> + return 0;
> +}
> +
> +static const struct v4l2_subdev_internal_ops ov7740_subdev_internal_ops = {
> + .open = ov7740_open,
> +};
> +#endif
> +
> +static int ov7740_probe_dt(struct i2c_client *client,
> + struct ov7740 *ov7740)
> +{
> + ov7740->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
> + GPIOD_OUT_LOW);
> + if (IS_ERR(ov7740->resetb_gpio)) {
> + dev_info(&client->dev, "can't get %s GPIO\n", "reset");
> + return PTR_ERR(ov7740->resetb_gpio);
> + }
> +
> + ov7740->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
> + GPIOD_OUT_HIGH);
> + if (IS_ERR(ov7740->pwdn_gpio)) {
> + dev_info(&client->dev, "can't get %s GPIO\n", "powerdown");
> + return PTR_ERR(ov7740->pwdn_gpio);
> + }
> +
> + return 0;
> +}
> +
> +static int ov7740_detect(struct ov7740 *ov7740)
> +{
> + struct regmap *regmap = ov7740->regmap;
> + unsigned int midh, midl, pidh, pidl;
> + int ret;
> +
> + ret = regmap_read(regmap, REG_MIDH, &midh);
> + if (ret)
> + return ret;
> + if (midh != 0x7f)
> + return -ENODEV;
> +
> + ret = regmap_read(regmap, REG_MIDL, &midl);
> + if (ret)
> + return ret;
> + if (midl != 0xa2)
> + return -ENODEV;
> +
> + ret = regmap_read(regmap, REG_PIDH, &pidh);
> + if (ret)
> + return ret;
> + if (pidh != 0x77)
> + return -ENODEV;
> +
> + ret = regmap_read(regmap, REG_PIDL, &pidl);
> + if (ret)
> + return ret;
> + if ((pidl != 0x40) && (pidl != 0x41) && (pidl != 0x42))
> + return -ENODEV;
> +
> + return 0;
> +}
> +
> +static int ov7740_init_controls(struct ov7740 *ov7740)
> +{
> + struct i2c_client *client = v4l2_get_subdevdata(&ov7740->subdev);
> + struct v4l2_ctrl_handler *ctrl_hdlr = &ov7740->ctrl_handler;
> + int ret;
> +
> + ret = v4l2_ctrl_handler_init(ctrl_hdlr, 2);
> + if (ret < 0)
> + return ret;
> +
> + ctrl_hdlr->lock = &ov7740->mutex;
> + ov7740->auto_wb = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
> + V4L2_CID_AUTO_WHITE_BALANCE,
> + 0, 1, 1, 1);
> + ov7740->blue_balance = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
> + V4L2_CID_BLUE_BALANCE,
> + 0, 0xff, 1, 0x80);
> + ov7740->red_balance = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
> + V4L2_CID_RED_BALANCE,
> + 0, 0xff, 1, 0x80);
> +
> + ov7740->brightness = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
> + V4L2_CID_BRIGHTNESS,
> + -255, 255, 1, 0);
> + ov7740->contrast = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
> + V4L2_CID_CONTRAST,
> + 0, 127, 1, 0x20);
> + ov7740->saturation = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
> + V4L2_CID_SATURATION, 0, 256, 1, 0x80);
> + ov7740->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
> + V4L2_CID_HFLIP, 0, 1, 1, 0);
> + ov7740->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
> + V4L2_CID_VFLIP, 0, 1, 1, 0);
> + ov7740->gain = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
> + V4L2_CID_GAIN, 0, 1023, 1, 500);
> + ov7740->auto_gain = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
> + V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
> + ov7740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
> + V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
> + ov7740->auto_exposure = v4l2_ctrl_new_std_menu(ctrl_hdlr,
> + &ov7740_ctrl_ops,
> + V4L2_CID_EXPOSURE_AUTO,
> + V4L2_EXPOSURE_MANUAL, 0,
> + V4L2_EXPOSURE_AUTO);
> +
> + ov7740->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
> + ov7740->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
> +
> + v4l2_ctrl_auto_cluster(3, &ov7740->auto_wb, 0, false);
> + v4l2_ctrl_auto_cluster(2, &ov7740->auto_gain, 0, true);
> + v4l2_ctrl_auto_cluster(2, &ov7740->auto_exposure,
> + V4L2_EXPOSURE_MANUAL, false);
> + v4l2_ctrl_cluster(2, &ov7740->hflip);
> +
> + ret = v4l2_ctrl_handler_setup(ctrl_hdlr);
> + if (ret) {
> + dev_err(&client->dev, "%s control init failed (%d)\n",
> + __func__, ret);
> + goto error;
> + }
> +
> + ov7740->subdev.ctrl_handler = ctrl_hdlr;
> + return 0;
> +
> +error:
> + v4l2_ctrl_handler_free(ctrl_hdlr);
> + mutex_destroy(&ov7740->mutex);
> + return ret;
> +}
> +
> +static void ov7740_free_controls(struct ov7740 *ov7740)
> +{
> + v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler);
> + mutex_destroy(&ov7740->mutex);
> +}
> +
> +#define OV7740_MAX_REGISTER 0xff
> +static const struct regmap_config ov7740_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 8,
> + .max_register = OV7740_MAX_REGISTER,
> +};
> +
> +static int ov7740_probe(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + struct ov7740 *ov7740;
> + struct v4l2_subdev *sd;
> + int ret;
> +
> + if (!i2c_check_functionality(client->adapter,
> + I2C_FUNC_SMBUS_BYTE_DATA)) {
> + dev_err(&client->dev,
> + "OV7740: I2C-Adapter doesn't support SMBUS\n");
> + return -EIO;
> + }
> +
> + ov7740 = devm_kzalloc(&client->dev, sizeof(*ov7740), GFP_KERNEL);
> + if (!ov7740)
> + return -ENOMEM;
> +
> + ov7740->xvclk = devm_clk_get(&client->dev, "xvclk");
> + if (IS_ERR(ov7740->xvclk)) {
> + ret = PTR_ERR(ov7740->xvclk);
> + dev_err(&client->dev,
> + "OV7740: fail to get xvclk: %d\n", ret);
> + return ret;
> + }
> +
> + ret = ov7740_probe_dt(client, ov7740);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(ov7740->xvclk);
> + if (ret)
> + return ret;
> +
> + ov7740->regmap = devm_regmap_init_i2c(client, &ov7740_regmap_config);
> + if (IS_ERR(ov7740->regmap)) {
> + ret = PTR_ERR(ov7740->regmap);
> + dev_err(&client->dev, "Failed to allocate register map: %d\n",
> + ret);
> + goto error_regmap_init;
> + }
> +
> + sd = &ov7740->subdev;
> + client->flags |= I2C_CLIENT_SCCB;
> + v4l2_i2c_subdev_init(sd, client, &ov7740_subdev_ops);
> +
> +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
> + sd->internal_ops = &ov7740_subdev_internal_ops;
> + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
> +#endif
> +
> +#if defined(CONFIG_MEDIA_CONTROLLER)
> + ov7740->pad.flags = MEDIA_PAD_FL_SOURCE;
> + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
> + ret = media_entity_pads_init(&sd->entity, 1, &ov7740->pad);
> + if (ret)
> + goto error_regmap_init;
> +#endif
> +
> + ov7740_set_power(sd, 1);
> +
> + ret = ov7740_detect(ov7740);
> + if (ret)
> + goto error_detect;
> +
> + mutex_init(&ov7740->mutex);
> +
> + ret = ov7740_init_controls(ov7740);
> + if (ret)
> + goto error_init_controls;
> +
> + v4l_info(client, "chip found @ 0x%02x (%s)\n",
> + client->addr << 1, client->adapter->name);
> +
> + ov7740->fmt = &ov7740_formats[0];
> + ov7740->frmsize = &ov7740_framesizes[0];
> +
> + ov7740_get_default_format(sd, &ov7740->format);
> +
> + ret = v4l2_async_register_subdev(sd);
> + if (ret)
> + goto error_async_register;
> +
> + pm_runtime_get_noresume(&client->dev);
> + pm_runtime_set_active(&client->dev);
> + pm_runtime_enable(&client->dev);
> + pm_runtime_put(&client->dev);
You can use pm_runtime_idle() to replace get_noresume + put.
> +
> + return 0;
> +
> +error_async_register:
> + v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler);
> +error_init_controls:
> + ov7740_free_controls(ov7740);
> + ov7740_set_power(sd, 0);
> +error_detect:
ov7740_set_power(sd, 0) here?
> + media_entity_cleanup(&ov7740->subdev.entity);
> +error_regmap_init:
> + clk_disable_unprepare(ov7740->xvclk);
> +
> + return ret;
> +}
> +
> +static int ov7740_remove(struct i2c_client *client)
> +{
> + struct v4l2_subdev *sd = i2c_get_clientdata(client);
> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
> +
> + clk_disable_unprepare(ov7740->xvclk);
> + mutex_destroy(&ov7740->mutex);
> + v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler);
> +#if defined(CONFIG_MEDIA_CONTROLLER)
> + media_entity_cleanup(&ov7740->subdev.entity);
> +#endif
> + v4l2_async_unregister_subdev(sd);
> + ov7740_free_controls(ov7740);
> +
> + pm_runtime_get_sync(&client->dev);
> + pm_runtime_disable(&client->dev);
> + pm_runtime_set_suspended(&client->dev);
> + pm_runtime_put_noidle(&client->dev);
ov7740_set_power(sd, 0) if the device was suspended.
I'd think the smiapp driver does this generally right. Think about how this
works if runtime PM is disabled.
> +
> + return 0;
> +}
> +
> +static int __maybe_unused ov7740_runtime_suspend(struct device *dev)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> + struct v4l2_subdev *sd = i2c_get_clientdata(client);
> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
> +
> + clk_disable_unprepare(ov7740->xvclk);
> + ov7740_set_power(sd, 0);
How about moving clock control to ov7740_set_power()? Clock and the GPIOs
appear to be always controller together, aren't they?
> +
> + return 0;
> +}
> +
> +static int __maybe_unused ov7740_runtime_resume(struct device *dev)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> + struct v4l2_subdev *sd = i2c_get_clientdata(client);
> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
> +
> + ov7740_set_power(sd, 1);
> + return clk_prepare_enable(ov7740->xvclk);
> +}
> +
> +static const struct i2c_device_id ov7740_id[] = {
> + { "ov7740", 0 },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(i2c, ov7740_id);
> +
> +static const struct dev_pm_ops ov7740_pm_ops = {
> + SET_RUNTIME_PM_OPS(ov7740_runtime_suspend, ov7740_runtime_resume, NULL)
> +};
> +
> +static const struct of_device_id ov7740_of_match[] = {
> + {.compatible = "ovti,ov7740", },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, ov7740_of_match);
> +
Extra newline.
> +
> +static struct i2c_driver ov7740_i2c_driver = {
> + .driver = {
> + .name = "ov7740",
> + .pm = &ov7740_pm_ops,
> + .of_match_table = of_match_ptr(ov7740_of_match),
> + },
> + .probe = ov7740_probe,
> + .remove = ov7740_remove,
> + .id_table = ov7740_id,
> +};
> +module_i2c_driver(ov7740_i2c_driver);
> +
> +MODULE_DESCRIPTION("The V4L2 driver for Omnivision 7740 sensor");
> +MODULE_AUTHOR("Songjun Wu <songjun.wu@atmel.com>");
> +MODULE_LICENSE("GPL v2");
--
Regards,
Sakari Ailus
e-mail: sakari.ailus@iki.fi
^ permalink raw reply
* Re: [PATCH v2 10/10] arm64: dts: exynos: remove i80-if-timings nodes
From: Krzysztof Kozlowski @ 2017-11-28 11:56 UTC (permalink / raw)
To: Inki Dae
Cc: Andrzej Hajda, Bartlomiej Zolnierkiewicz, Marek Szyprowski,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Dave Airlie
In-Reply-To: <20170908164752.mrxqrhkszmfqbk6x@kozik-lap>
On Fri, Sep 8, 2017 at 6:47 PM, Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Thu, Aug 24, 2017 at 03:33:59PM +0200, Andrzej Hajda wrote:
>> Since i80/command mode is determined in runtime by propagating info
>> from panel this property can be removed.
>>
>> Signed-off-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> ---
>> arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 6 ------
>> 1 file changed, 6 deletions(-)
>>
>
> I understand this should go in after merging the driver changes to
> preserve bisectability?
Dear Inki Dae,
This was a DeviceTree patch and it should be kept separate from driver
changes. You should not apply it then. Especially without an ack from
arm-soc or Exynos maintainers... because the usual path is through
arm-soc.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=88a5e22a90efd12dfde642ed55d4c669ab658b0f
Best regards,
Krzysztof
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH] ARM: dts: sun8i: h3: Add dts file for Libre Computer Board ALL-H3-CC H3 ver.
From: Icenowy Zheng @ 2017-11-28 11:11 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Maxime Ripard, devicetree-u79uwXL29TY76Z2rM5mHXA, Corentin Labbe,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20171128041211.17375-1-wens-jdAy2FN1RRM@public.gmane.org>
在 2017-11-28 12:12，Chen-Yu Tsai 写道：
> The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
> Pi B+ form factor single board computer based on the Allwinner H3 SoC.
> The board has 1GB DDR3 SDRAM, provided by 4 2Gb chips. The mounting
> holes
> and connectors are in the exact same position as on the Raspberry Pi
> B+.
>
> Raspberry Pi B+ like peripherals supported on this board include:
>
> - Power input through micro-USB connector (without USB OTG)
> - Native 100 Mbps ethernet using the internal PHY, as opposed to
> USB-based on the RPi
> - 4x USB 2.0 host ports, directly connected to the SoC, as opposed to
> being connected through a USB 2.0 hub on the RPi
> - TV and audio output on a 3.5mm TRRS jack
> - HDMI output
> - Micro-SD card slot
> - Standard RPi B+ GPIO header, with the standard peripherals routed
> to
> the same pins.
>
> * 5V, 3.3V power, and ground
> * I2C0 on the H3 is routed to I2C1 pins on the RPi header
> * I2C1 on the H3 is routed to I2C0 pins on the RPi header
> * UART1 on the H3 is routed to UART0 pins on the RPi header
> * SPI0 on the H3 is routed to SPI0 pins on the RPi header,
> with GPIO pin PA17 replacing the missing Chip Select 1
> * I2S1 on the H3 is routed to PCM pins on the RPi header
>
> - Additional peripherals from the H3 are available on different pins.
> These include I2S0, JTAG, PWM1, SPDIF, SPI1, and UART3
>
> In addition, there are a number of new features:
>
> - Console UART header
> - Consumer IR receiver
> - Camera interface (not compatible with RPi)
> - Onboard microphone
> - eMMC expansion module port
> - Heatsink mounting holes
>
> This patch adds a dts file for this board that enables all "onboard"
> peripherals currently supported. This means no display or camera
> support.
>
> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> ---
>
> There are two other variants [1] of this board, with different SoCs and
> DRAM configuration. But the board remains the same, thanks to the SoCs
> being pin compatible.
>
> Do we need different board compatible strings? FWIW the soc compatible
> string already encodes the soc variant, and the DRAM stuff is handled
> by the bootloader. The filename also has the SoC family and chip name.
> The displayed board model also has the SoC variant included. The board
> itself is named "ALL-H3-CC".
>
> I'm asking as we have the same issue with the Bananapi M2+ [2], where
> they've released new variants with different SoCs and DRAM capacities
> using the same board. Not sure if they are commercially available
> though.
BPi M2+ H5 is not yet commercially available.
>
> Last, the LED polarity is wrong. This is due to the EMAC driver not
> following the DT binding and looking for the
> "allwinner,leds-active-low"
> under the PHY node, instead of the EMAC node. I've notified Corentin of
> this issue.
>
> [1]
> https://www.kickstarter.com/projects/librecomputer/libre-computer-board-tritium-sbc-linux-android-7-n
> [2] http://www.banana-pi.org/m2plus.html
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts | 196
> +++++++++++++++++++++
> 2 files changed, 197 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 3c139c63098f..aa68f719692f 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -953,6 +953,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-h2-plus-orangepi-zero.dtb \
> sun8i-h3-bananapi-m2-plus.dtb \
> sun8i-h3-beelink-x2.dtb \
> + sun8i-h3-libretech-all-h3-cc.dtb \
There's also a H5 variant of this board, so I think the
peripherals should be placed into a DTSI, and have the
board DTS include the SoC DTSI and peripheral DTSI.
> sun8i-h3-nanopi-m1.dtb \
> sun8i-h3-nanopi-m1-plus.dtb \
> sun8i-h3-nanopi-neo.dtb \
> diff --git a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
> b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
> new file mode 100644
> index 000000000000..6f544e007f71
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
> @@ -0,0 +1,196 @@
> +/*
> + * Copyright (C) 2017 Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> + *
> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + */
> +
> +/dts-v1/;
> +#include "sun8i-h3.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> + model = "Libre Computer Board ALL-H3-CC H3";
> + compatible = "libretech,all-h3-cc", "allwinner,sun8i-h3";
> +
> + aliases {
> + ethernet0 = &emac;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + pwr_led {
> + label = "librecomputer:pwr";
> + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
> + default-state = "on";
> + };
> +
> + status_led {
> + label = "librecomputer:status";
> + gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
> + };
> + };
> +
> + gpio_keys {
> + compatible = "gpio-keys";
> +
> + recovery {
> + label = "recovery";
> + linux,code = <BTN_0>;
> + gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
> + };
> + };
> +
> + reg_vcc1v2: vcc1v2 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc1v2";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_vcc5v0>;
> + gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
> + enable-active-high;
> + };
> +
> + reg_vcc3v3: vcc3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <®_vcc5v0>;
> + };
> +
> + /* This represents the board's 5V input */
> + reg_vcc5v0: vcc5v0 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + reg_vcc_dram: vcc-dram {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-dram";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_vcc5v0>;
> + gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
> + enable-active-high;
> + };
> +
> + reg_vcc_io: vcc-io {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-io";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_vcc3v3>;
> + gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
> + };
> +
> + reg_vdd_cpux: vdd-cpux {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd-cpux";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_vcc5v0>;
> + gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
> + enable-active-high;
> + };
> +};
> +
> +&codec {
> + allwinner,audio-routing =
> + "Line Out", "LINEOUT",
> + "MIC1", "Mic",
> + "Mic", "MBIAS";
> + status = "okay";
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&ehci2 {
> + status = "okay";
> +};
> +
> +&ehci3 {
> + status = "okay";
> +};
> +
> +&emac {
> + phy-handle = <&int_mii_phy>;
> + phy-mode = "mii";
> + allwinner,leds-active-low;
> + status = "okay";
> +};
> +
> +&ir {
> + pinctrl-names = "default";
> + pinctrl-0 = <&ir_pins_a>;
> + status = "okay";
> +};
> +
> +&mmc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins_a>;
> + vmmc-supply = <®_vcc_io>;
> + bus-width = <4>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> + cd-inverted;
> + status = "okay";
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&ohci2 {
> + status = "okay";
> +};
> +
> +&ohci3 {
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins_a>;
> + status = "okay";
> +};
> +
> +&usb_otg {
> + dr_mode = "host";
> + status = "okay";
> +};
> +
> +&usbphy {
> + /* VBUS on USB ports are always on */
> + usb0_vbus-supply = <®_vcc5v0>;
> + usb1_vbus-supply = <®_vcc5v0>;
> + usb2_vbus-supply = <®_vcc5v0>;
> + usb3_vbus-supply = <®_vcc5v0>;
> + status = "okay";
> +};
--
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^ permalink raw reply
* [PATCH] pinctrl: sunxi: add support for Allwinner H6 main pin controller
From: Icenowy Zheng @ 2017-11-28 11:06 UTC (permalink / raw)
To: Linus Walleij, Maxime Ripard, Chen-Yu Tsai
Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
Allwinner H6 SoC has two pin controllers like other Allwinner SoCs with
ARISC: one main pin controller (called CPUX-PORT in user manual) and one
pin controller in the CPUs power domain (called CPUS-PORT in user
manual).
This commit adds support for the main pin controller in the H6 SoC.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 525 +++++++++++++++++++++
4 files changed, 531 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 09789fdfa749..ed5eb547afc8 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -27,6 +27,7 @@ Required properties:
"allwinner,sun50i-a64-pinctrl"
"allwinner,sun50i-a64-r-pinctrl"
"allwinner,sun50i-h5-pinctrl"
+ "allwinner,sun50i-h6-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index bfce99d86dfc..5de1f63b07bb 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -77,4 +77,8 @@ config PINCTRL_SUN50I_H5
def_bool ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_H6
+ def_bool ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 12a752e836ef..3c4aec6611e9 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o
obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o
+obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
new file mode 100644
index 000000000000..468f77baa17c
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
@@ -0,0 +1,525 @@
+/*
+ * Allwinner H6 SoC pinctrl driver.
+ *
+ * Copyright (C) 2017 Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin h6_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* WE */
+ SUNXI_FUNCTION(0x4, "spi0")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* DS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
+ SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
+ SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RE */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
+ SUNXI_FUNCTION(0x4, "spi0")), /* CS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
+ SUNXI_FUNCTION(0x4, "spi0")), /* HOLD */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
+ SUNXI_FUNCTION(0x4, "spi0")), /* WP */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
+ SUNXI_FUNCTION(0x4, "csi"), /* PCLK */
+ SUNXI_FUNCTION(0x5, "emac")), /* ERXD3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
+ SUNXI_FUNCTION(0x4, "csi"), /* MCLK */
+ SUNXI_FUNCTION(0x5, "emac")), /* ERXD2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "csi"), /* HSYNC */
+ SUNXI_FUNCTION(0x5, "emac")), /* ERXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* DVLD */
+ SUNXI_FUNCTION(0x4, "csi"), /* VSYNC */
+ SUNXI_FUNCTION(0x5, "emac")), /* ERXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D0 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ERXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D1 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ERXCTL */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D2 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ENULL */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D3 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ETXD3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D4 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ETXD2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D5 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ETXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D6 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ETXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
+ SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
+ SUNXI_FUNCTION(0x4, "csi"), /* D7 */
+ SUNXI_FUNCTION(0x5, "emac")), /* ETXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
+ SUNXI_FUNCTION(0x3, "ts1"), /* CLK */
+ SUNXI_FUNCTION(0x4, "csi"), /* SCK */
+ SUNXI_FUNCTION(0x5, "emac")), /* ETXCTL */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
+ SUNXI_FUNCTION(0x3, "ts1"), /* ERR */
+ SUNXI_FUNCTION(0x4, "csi"), /* SDA */
+ SUNXI_FUNCTION(0x5, "emac")), /* ECLKIN */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
+ SUNXI_FUNCTION(0x3, "ts1"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
+ SUNXI_FUNCTION(0x5, "csi")), /* D8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
+ SUNXI_FUNCTION(0x3, "ts1"), /* DVLD */
+ SUNXI_FUNCTION(0x4, "dmic"), /* DATA0 */
+ SUNXI_FUNCTION(0x5, "csi")), /* D9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
+ SUNXI_FUNCTION(0x3, "ts1"), /* D0 */
+ SUNXI_FUNCTION(0x4, "dmic")), /* DATA1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
+ SUNXI_FUNCTION(0x3, "ts2"), /* CLK */
+ SUNXI_FUNCTION(0x4, "dmic")), /* DATA2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "ts2"), /* ERR */
+ SUNXI_FUNCTION(0x4, "dmic")), /* DATA3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
+ SUNXI_FUNCTION(0x3, "ts2"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "uart2"), /* TX */
+ SUNXI_FUNCTION(0x5, "emac")), /* EMDC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
+ SUNXI_FUNCTION(0x3, "ts2"), /* DVLD */
+ SUNXI_FUNCTION(0x4, "uart2"), /* RX */
+ SUNXI_FUNCTION(0x5, "emac")), /* EMDIO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "ts2"), /* D0 */
+ SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
+ SUNXI_FUNCTION(0x3, "ts3"), /* CLK */
+ SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
+ SUNXI_FUNCTION(0x3, "ts3"), /* ERR */
+ SUNXI_FUNCTION(0x4, "uart3"), /* TX */
+ SUNXI_FUNCTION(0x5, "jtag")), /* MS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
+ SUNXI_FUNCTION(0x3, "ts3"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "uart3"), /* RX */
+ SUNXI_FUNCTION(0x5, "jtag")), /* CK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
+ SUNXI_FUNCTION(0x3, "ts3"), /* DVLD */
+ SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
+ SUNXI_FUNCTION(0x5, "jtag")), /* DO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
+ SUNXI_FUNCTION(0x3, "ts3"), /* D0 */
+ SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
+ SUNXI_FUNCTION(0x5, "jtag")), /* DI */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PF_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PF_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PF_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PF_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart0"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PF_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PF_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PF_EINT6 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
+ SUNXI_FUNCTION(0x4, "sim0"), /* VPPEN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
+ SUNXI_FUNCTION(0x4, "sim0"), /* VPPPP */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* SYNC */
+ SUNXI_FUNCTION(0x3, "h_i2s2"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "sim0"), /* PWREN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* CLK */
+ SUNXI_FUNCTION(0x3, "h_i2s2"), /* CLK */
+ SUNXI_FUNCTION(0x4, "sim0"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* DOUT */
+ SUNXI_FUNCTION(0x3, "h_i2s2"), /* DOUT */
+ SUNXI_FUNCTION(0x4, "sim0"), /* DATA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* DIN */
+ SUNXI_FUNCTION(0x3, "h_i2s2"), /* DIN */
+ SUNXI_FUNCTION(0x4, "sim0"), /* RST */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s2"), /* MCLK */
+ SUNXI_FUNCTION(0x3, "h_i2s2"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "sim0"), /* DET */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), /* PG_EINT14 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0"), /* TX */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* SYNC */
+ SUNXI_FUNCTION(0x4, "h_i2s0"), /* SYNC */
+ SUNXI_FUNCTION(0x5, "sim1"), /* VPPEN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PH_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0"), /* RX */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* CLK */
+ SUNXI_FUNCTION(0x4, "h_i2s0"), /* CLK */
+ SUNXI_FUNCTION(0x5, "sim1"), /* VPPPP */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ir_tx"),
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */
+ SUNXI_FUNCTION(0x4, "h_i2s0"), /* DOUT */
+ SUNXI_FUNCTION(0x5, "sim1"), /* PWREN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PH_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CS */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */
+ SUNXI_FUNCTION(0x4, "h_i2s0"), /* DIN */
+ SUNXI_FUNCTION(0x5, "sim1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PH_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "h_i2s0"), /* MCLK */
+ SUNXI_FUNCTION(0x5, "sim1"), /* DATA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PH_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x3, "spdif"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */
+ SUNXI_FUNCTION(0x5, "sim1"), /* RST */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PH_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x3, "spdif"), /* IN */
+ SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */
+ SUNXI_FUNCTION(0x5, "sim1"), /* DET */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PH_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PH_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PH_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PH_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PH_EINT10 */
+};
+
+static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
+ .pins = h6_pins,
+ .npins = ARRAY_SIZE(h6_pins),
+ .irq_banks = 3,
+ .irq_bank_base = 5,
+ .irq_read_needs_mux = true
+};
+
+static int h6_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &h6_pinctrl_data);
+}
+
+static const struct of_device_id h6_pinctrl_match[] = {
+ { .compatible = "allwinner,sun50i-h6-pinctrl", },
+ {}
+};
+
+static struct platform_driver h6_pinctrl_driver = {
+ .probe = h6_pinctrl_probe,
+ .driver = {
+ .name = "sun50i-h6-pinctrl",
+ .of_match_table = h6_pinctrl_match,
+ },
+};
+builtin_platform_driver(h6_pinctrl_driver);
--
2.14.2
^ permalink raw reply related
* AW: [PATCH 4/5] ARM: dts: Add support for emtrion emCON-MX6 series
From: Türk, Jan @ 2017-11-28 10:52 UTC (permalink / raw)
To: 'Rob Herring'
Cc: Mark Rutland, Thierry Reding, David Airlie, Russell King,
Shawn Guo, Sascha Hauer, Fabio Estevam, Andreas Färber,
Kevin Hilman, Geert Uytterhoeven, Alexandre Belloni, SZ Lin,
Greg Kroah-Hartman, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
LinuxArmKernelMailingListe
In-Reply-To: <20171126192410.4eoujidx4nv3b2jf@rob-hp-laptop>
Hi Rob,
thanks for your feedback, the changes will be included in V2 of the patch-series.
Jan
> Von: Rob Herring
> Gesendet: Sonntag, 26. November 2017 20:24
> On Thu, Nov 23, 2017 at 01:55:54PM +0100, Jan Tuerk wrote:
> > This patch adds support for the emtrion GmbH emCON-MX6 modules.
> > They are available with imx.6 Solo, Dual-Lite, Dual and Quad
> > equipped with Memory from 512MB to 2GB (configured by U-Boot).
[...]
> > +&i2c3 {
> > + clock-frequency = <100000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_i2c3>;
> > + status = "okay";
> > +
> > + sgtl5000: sgtl5000@0a {
>
> audio-codec@a
>
> same errors repeat below.
changed for v2
>
> > + compatible = "fsl,sgtl5000";
> > + reg = <0x0a>;
> > + clocks = <&sndosc>;
> > + VDDA-supply = <&base3p3>;
> > + VDDIO-supply = <&base3p3>;
> > + };
> > +
> > + boardID: pca8754a@3A {
>
> ...@3a
changed in V2
>
> > + compatible = "nxp,pca8574";
> > + reg = <0x3A>;
>
> 0x3a
>
> > + gpio-controller;
> > + #gpio-cells = <1>;
> > + };
> > +
> > + captouch: edt-ft5x06@38 {
>
> touchscreen@38
>
> > + reg = <0x38>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>;
> > + interrupt-parent = <&gpio6>;
> > + interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
> > + compatible = "edt,edt-ft5406";
> > + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
> > + wakeup-source;
> > + };
> > +};
> > +
> > +&ssi2 {
> > + status = "okay";
> > +};
> > +
> > +&rgb_encoder {
> > + status = "okay";
> > +};
> > +
[...]
> > +
> > + rgb_panel: panel {
> > + backlight = <&rgb_backlight>;
> > + power-supply = <®_prallel_disp>;
> > + port {
> > + rgb_panel_in: endpoint {
> > + remote-endpoint = <&rgb_encoder_out>;
> > + };
> > + };
> > + };
> > +
> > + rgb_backlight: rgb_backlight {
>
> rgb-backlight {
[...]
> > +
> > + lvds_backlight: lvds_backlight {
>
> lvds-backlight {
Ok, I'll change that in V2
[...]
> > +
> > +&i2c1 {
> > + clock-frequency = <100000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_i2c1>;
> > + status = "okay";
> > +
> > + rtc: rtc@68 {
> > + compatible = "dallas,ds1307";
> > + reg = <0x68>;
> > + };
> > +
> > + da9063: da9063@58 {
>
> pmic@38
changed
>
> > + compatible = "dlg,da9063";
> > + reg = <0x58>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_pmic>;
> > + interrupt-parent = <&gpio2>;
> > +
[....]
> > +
> > + mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + ksz9031: phy {
>
> phy@0
>
> Building with W=2 or W=1 will tell you this.
thanks for the hint, it will be also included in v2
>
> > + reg = <0>;
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + interrupt-parent = <&gpio1>;
> > + interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
> > + rxdv-skew-ps = <480>;
> > + txen-skew-ps = <480>;
[...]
emtrion GmbH
Kreativpark - Alter Schlachthof 45
76131 Karlsruhe
GERMANY
http://www.emtrion.de
_______________________________________
Amtsgericht Mannheim
HRB 110 300
Geschäftsführer: Dieter Baur, Ramona Maurer
_______________________________________
^ permalink raw reply
* Re: [PATCH 03/13] ARM: dts: imx6qdl: SolidRun: move microsom includes into .dts
From: Russell King - ARM Linux @ 2017-11-28 10:45 UTC (permalink / raw)
To: Shawn Guo
Cc: Mark Rutland, devicetree, Jon Nettleton, Rob Herring,
Sascha Hauer, Fabio Estevam, linux-arm-kernel
In-Reply-To: <CALHpu36Kjy4SSn1m8ZOYwEr+9u67dobfNHiOX6s75UFGVm3atw@mail.gmail.com>
On Tue, Nov 28, 2017 at 05:46:07AM +0100, Jon Nettleton wrote:
> On Mon, Nov 27, 2017 at 5:52 PM, Russell King <rmk+kernel@armlinux.org.uk>
> wrote:
>
> > Move the microsom includes into the .dts files so different options can
> > be accomodated at the lowest level.
> >
> > Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
>
> Since we are going through and adding the som dtsi include to all the
> device-tree files, would it make sense to rename the microsom.dtsi at this
> point in time? Perhaps something like imx6qdl-sr-microsom.dtsi?
Shawn,
Having discussed with Jon this morning, we've decided that as
"imx6qdl-microsom.dtsi" is too generic, we'll to rename that file as
"imx6qdl-sr-som.dtsi" instead. New patch series on its way.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
* Re: [PATCH 01/10] genirq: Export irq_set_msi_desc()
From: Marc Zyngier @ 2017-11-28 10:00 UTC (permalink / raw)
To: Manikanta Maddireddy, Thomas Gleixner
Cc: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, rjw-LthD3rsA81gm4RdzfppkhA,
vidyas-DDmLM1+adcrQT0dZR+AlfA, kthota-DDmLM1+adcrQT0dZR+AlfA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <600a7b65-670e-b164-913c-99e18ae593d2-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 25/11/17 19:41, Manikanta Maddireddy wrote:
>
>
> On 25-Nov-17 5:25 AM, Thomas Gleixner wrote:
>> On Fri, 24 Nov 2017, Manikanta Maddireddy wrote:
>>
>> Please CC the proper mailing list for irq related changes.
>>
>>> PCI bus support MSI interrupts, allow PCI host driver to set MSI descriptor
>>> data for an irq.
>>
>> This is not really an explanation why this export is needed.
>>
>> Thanks,
>>
>> tglx
>>
> Updated the commit log with why Tegra PCIe driver is using this function in V2.
> Please review.
Well, to review it, I would like to be on Cc.
My current position on this is that if you need to export this function,
then you're using a deprecated API, and you should instead consider
moving to the generic MSI model, which doesn't need any of this.
I've done that a distant past, but never actually published the patch
(not tested it):
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/commit/?h=irq/kill-msi-controller&id=83b3602fcee7972b9d549ed729b56ec28de16081
But without seeing the patches, I may be barking up the wrong tree...
Thanks,
M.
--
Jazz is not dead. It just smells funny...
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v5 2/2] crypto: stm32 - Support for STM32 CRYP crypto module
From: Fabien DESSENNE @ 2017-11-28 9:47 UTC (permalink / raw)
To: Herbert Xu
Cc: Mark Rutland, devicetree@vger.kernel.org, Alexandre TORGUE,
linux-kernel@vger.kernel.org, Lionel DEBIEVE, Rob Herring,
Corentin Labbe, linux-crypto@vger.kernel.org, Maxime Coquelin,
Ludovic BARRE, David S . Miller,
linux-arm-kernel@lists.infradead.org, Benjamin GAIGNARD
In-Reply-To: <774a92f2-af70-0424-b066-0cc1db3f9ab0@st.com>
Just a gentle ping ... or have I missed out on a reply?
On 13/11/17 11:30, Fabien DESSENNE wrote:
> Hi Herbert,
>
> Can you check if this patchset (removed the AEAD part as you suggested +
> libkcapi test OK as suggested by Corentin) can be applied now?
>
> BR
>
> Fabien
>
>
> On 07/11/17 15:40, Fabien DESSENNE wrote:
>> On 22/10/17 09:26, Corentin Labbe wrote:
>>> On Thu, Oct 19, 2017 at 05:10:30PM +0200, Fabien Dessenne wrote:
>>>> This module registers block cipher algorithms that make use of the
>>>> STMicroelectronics STM32 crypto "CRYP1" hardware.
>>>> The following algorithms are supported:
>>>> - aes: ecb, cbc, ctr
>>>> - des: ecb, cbc
>>>> - tdes: ecb, cbc
>>>>
>>>> Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
>>>> ---
>>>> drivers/crypto/stm32/Kconfig | 9 +
>>>> drivers/crypto/stm32/Makefile | 3 +-
>>>> drivers/crypto/stm32/stm32-cryp.c | 1172 +++++++++++++++++++++++++++++++++++++
>>>> 3 files changed, 1183 insertions(+), 1 deletion(-)
>>>> create mode 100644 drivers/crypto/stm32/stm32-cryp.c
>>>>
>>>> diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
>>>> +static void stm32_cryp_irq_write_block(struct stm32_cryp *cryp)
>>>> +{
>>>> + unsigned int i, j;
>>>> + u32 *src;
>>>> + u8 d8[4];
>>>> +
>>>> + src = sg_virt(cryp->in_sg) + _walked_in;
>>>> +
>>>> + for (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++) {
>>>> + if (likely(cryp->total_in >= sizeof(u32))) {
>>>> + /* Write a full u32 */
>>>> + stm32_cryp_write(cryp, CRYP_DIN, *src);
>>> Hello
>>>
>>> Try also to test your driver with userspace via AF_ALG (libkcapi is a good start).
>>> It should probably crash here.
>>> I have do the same on my first sunxi-ss driver and you should use kmap().
>>>
>>> Regards
>> Hi Corentin,
>>
>> Thank you for suggesting to test from userspace through the AF_ALG
>> socket with libkcapi.
>> This increases my test coverage.
>>
>> I ran the miscellaneous tests (kcapi-enc-test(large).sh + test.sh) and
>> could not observe any crash.
>> Note that I had already fixed some 'memory crashes' while testing with
>> testmgr / tcrypt while testing from the kernel.
>>
>> So it looks like the proposed implementation is fine.
>>
>> BR
>>
>> Fabien
^ permalink raw reply
* Re: [PATCH v2 27/35] irqchip: Andestech Internal Vector Interrupt Controller driver
From: Marc Zyngier @ 2017-11-28 9:37 UTC (permalink / raw)
To: Greentime Hu, greentime-MUIXKm3Oiri1Z/+hSey0Gg,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
linux-arch-u79uwXL29TY76Z2rM5mHXA, tglx-hfZtesqFncYOwBW4kG4KsQ,
jason-NLaQJdtUoK4Be96aLqz0jA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
netdev-u79uwXL29TY76Z2rM5mHXA, deanbo422-Re5JQEeQqe8AvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
viro-RmSDqhL/yNMiFSDQTTA3OLVCufUGDwFn,
dhowells-H+wXaHxf7aLQT0dZR+AlfA, will.deacon-5wv7dgnIgG8,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
linux-serial-u79uwXL29TY76Z2rM5mHXA
Cc: Rick Chen
In-Reply-To: <e82831165cd9e45a7d03af9c870560a6384e1603.1511785528.git.green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 27/11/17 12:28, Greentime Hu wrote:
> From: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
>
> This patch adds the Andestech Internal Vector Interrupt Controller
> driver. You can find the spec here. Ch4.9 of AndeStar SPA V3 Manual.
> http://www.andestech.com/product.php?cls=9
>
> Signed-off-by: Rick Chen <rick-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
> Signed-off-by: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
> ---
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-ativic32.c | 119 ++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 120 insertions(+)
> create mode 100644 drivers/irqchip/irq-ativic32.c
>
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index b842dfd..201ca9f 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -80,3 +80,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
> obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
> obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
> obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
> +obj-$(CONFIG_NDS32) += irq-ativic32.o
> diff --git a/drivers/irqchip/irq-ativic32.c b/drivers/irqchip/irq-ativic32.c
> new file mode 100644
> index 0000000..c4d6f86
> --- /dev/null
> +++ b/drivers/irqchip/irq-ativic32.c
> @@ -0,0 +1,119 @@
> +/*
> + * Copyright (C) 2005-2017 Andes Technology Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/irq.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/interrupt.h>
> +#include <linux/irqdomain.h>
> +#include <linux/irqchip.h>
> +#include <nds32_intrinsic.h>
> +
> +static void ativic32_ack_irq(struct irq_data *data)
> +{
> + __nds32__mtsr_dsb(1 << data->hwirq, NDS32_SR_INT_PEND2);
Consider writing (1 << data->hwirq) as BIT(data->hwirq).
> +}
> +
> +static void ativic32_mask_irq(struct irq_data *data)
> +{
> + unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
> + __nds32__mtsr_dsb(int_mask2 & (~(1 << data->hwirq)), NDS32_SR_INT_MASK2);
Same here.
> +}
> +
> +static void ativic32_mask_ack_irq(struct irq_data *data)
> +{
> + unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
> + __nds32__mtsr_dsb(int_mask2 & (~(1 << data->hwirq)), NDS32_SR_INT_MASK2);
> + __nds32__mtsr_dsb((1 << data->hwirq), NDS32_SR_INT_PEND2);
This is effectively MASK+ACK, so you're better off just writing it as
such. And since there is no advantage in your implementation in having
MASK_ACK over MASK+ACK, I suggest you remove this function completely,
and rely on the core code which will call them in sequence.
> +
> +}
> +
> +static void ativic32_unmask_irq(struct irq_data *data)
> +{
> + unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
> + __nds32__mtsr_dsb(int_mask2 | (1 << data->hwirq), NDS32_SR_INT_MASK2);
Same BIT() here.
> +}
> +
> +static struct irq_chip ativic32_chip = {
> + .name = "ativic32",
> + .irq_ack = ativic32_ack_irq,
> + .irq_mask = ativic32_mask_irq,
> + .irq_mask_ack = ativic32_mask_ack_irq,
> + .irq_unmask = ativic32_unmask_irq,
> +};
> +
> +static unsigned int __initdata nivic_map[6] = { 6, 2, 10, 16, 24, 32 };
> +
> +static struct irq_domain *root_domain;
> +static int ativic32_irq_domain_map(struct irq_domain *id, unsigned int virq,
> + irq_hw_number_t hw)
> +{
> +
> + unsigned long int_trigger_type;
> + int_trigger_type = __nds32__mfsr(NDS32_SR_INT_TRIGGER);
> + if (int_trigger_type & (1 << hw))
And here.
> + irq_set_chip_and_handler(virq, &ativic32_chip, handle_edge_irq);
> + else
> + irq_set_chip_and_handler(virq, &ativic32_chip, handle_level_irq);
Since you do not express the trigger in DT, you need to tell the core
about it by calling irqd_set_trigger_type() with the right setting.
> +
> + return 0;
> +}
> +
> +static struct irq_domain_ops ativic32_ops = {
> + .map = ativic32_irq_domain_map,
> + .xlate = irq_domain_xlate_onecell
> +};
> +
> +static int get_intr_src(void)
I'm not sure "int" is the best return type here. I suspect something
unsigned would be preferable, or even the irq_hw_number_t type.
> +{
> + return ((__nds32__mfsr(NDS32_SR_ITYPE)&ITYPE_mskVECTOR) >> ITYPE_offVECTOR)
Spaces around '&'.
> + - NDS32_VECTOR_offINTERRUPT;
> +}
> +
> +asmlinkage void asm_do_IRQ(struct pt_regs *regs)
> +{
> + int hwirq = get_intr_src();
irq_hw_number_t.
> + handle_domain_irq(root_domain, hwirq, regs);
> +}
> +
> +int __init ativic32_init_irq(struct device_node *node, struct device_node *parent)
> +{
> + unsigned long int_vec_base, nivic;
> +
> + if (WARN(parent, "non-root ativic32 are not supported"))
> + return -EINVAL;
> +
> + int_vec_base = __nds32__mfsr(NDS32_SR_IVB);
> +
> + if (((int_vec_base & IVB_mskIVIC_VER) >> IVB_offIVIC_VER) == 0)
> + panic("Unable to use atcivic32 for this cpu.\n");
> +
> + nivic = (int_vec_base & IVB_mskNIVIC) >> IVB_offNIVIC;
> + if (nivic >= (sizeof nivic_map / sizeof nivic_map[0]))
This should be:
if (nivic >= ARRAY_SIZE(NIVIC_MAP))
> + panic("The number of input for ativic32 is not supported.\n");
> +
> + nivic = nivic_map[nivic];
I'd rather you use another variable (nr_ints?).
> +
> + root_domain = irq_domain_add_linear(node, nivic,
> + &ativic32_ops, NULL);
> +
> + if (!root_domain)
> + panic("%s: unable to create IRQ domain\n", node->full_name);
> +
> + return 0;
> +}
> +IRQCHIP_DECLARE(ativic32, "andestech,ativic32", ativic32_init_irq);
>
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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^ permalink raw reply
* Re: Re: [PATCH] ARM: dts: sun8i: h3: Add dts file for Libre Computer Board ALL-H3-CC H3 ver.
From: Chen-Yu Tsai @ 2017-11-28 9:26 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, devicetree, linux-arm-kernel, linux-sunxi,
Corentin Labbe
In-Reply-To: <20171128084359.rzplftb3z53cgukp-YififvaboMKzQB+pC5nmwQ@public.gmane.org>
On Tue, Nov 28, 2017 at 4:43 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Hi,
>
> On Tue, Nov 28, 2017 at 12:12:11PM +0800, Chen-Yu Tsai wrote:
>> The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
>> Pi B+ form factor single board computer based on the Allwinner H3 SoC.
>> The board has 1GB DDR3 SDRAM, provided by 4 2Gb chips. The mounting holes
>> and connectors are in the exact same position as on the Raspberry Pi B+.
>>
>> Raspberry Pi B+ like peripherals supported on this board include:
>>
>> - Power input through micro-USB connector (without USB OTG)
>> - Native 100 Mbps ethernet using the internal PHY, as opposed to
>> USB-based on the RPi
>> - 4x USB 2.0 host ports, directly connected to the SoC, as opposed to
>> being connected through a USB 2.0 hub on the RPi
>> - TV and audio output on a 3.5mm TRRS jack
>> - HDMI output
>> - Micro-SD card slot
>> - Standard RPi B+ GPIO header, with the standard peripherals routed to
>> the same pins.
>>
>> * 5V, 3.3V power, and ground
>> * I2C0 on the H3 is routed to I2C1 pins on the RPi header
>> * I2C1 on the H3 is routed to I2C0 pins on the RPi header
>> * UART1 on the H3 is routed to UART0 pins on the RPi header
>> * SPI0 on the H3 is routed to SPI0 pins on the RPi header,
>> with GPIO pin PA17 replacing the missing Chip Select 1
>> * I2S1 on the H3 is routed to PCM pins on the RPi header
>>
>> - Additional peripherals from the H3 are available on different pins.
>> These include I2S0, JTAG, PWM1, SPDIF, SPI1, and UART3
>>
>> In addition, there are a number of new features:
>>
>> - Console UART header
>> - Consumer IR receiver
>> - Camera interface (not compatible with RPi)
>> - Onboard microphone
>> - eMMC expansion module port
>> - Heatsink mounting holes
>>
>> This patch adds a dts file for this board that enables all "onboard"
>> peripherals currently supported. This means no display or camera
>> support.
>>
>> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
>> ---
>>
>> There are two other variants [1] of this board, with different SoCs and
>> DRAM configuration. But the board remains the same, thanks to the SoCs
>> being pin compatible.
>>
>> Do we need different board compatible strings?
>
> Yes.
>
>> FWIW the soc compatible string already encodes the soc variant, and
>> the DRAM stuff is handled by the bootloader. The filename also has
>> the SoC family and chip name. The displayed board model also has
>> the SoC variant included. The board itself is named "ALL-H3-CC".
>
> The point of a board compatible is to identify the way a board
> behaves. If we ever need to make any quirks for one particular board,
> we have to have a compatible that uniquely identifies it.
>
> However, we can have an intermediate compatible as well to catch all
> those similar boards.
>
> Something like:
> compatible = "libretech,h3-tritium", "libretech,tritium", "allwinner,sun8i-h3";
compatible = "libretech,all-h3-cc-h3", "libretech,all-h3-cc",
"allwinner,sun8i-h3";
(See below about the names.) Does that look confusing?
>
>> I'm asking as we have the same issue with the Bananapi M2+ [2], where
>> they've released new variants with different SoCs and DRAM capacities
>> using the same board. Not sure if they are commercially available though.
>
> You can have a look at the way we handled all the q8 tablets that were
> pretty much in the same case. It's been working quite well.
You mean the sun?i-reference-tablet-design.dtsi files? I'm thinking we
might not have to go that far. The other variants could have:
#include "sun8i-h3-libretech-all-h3-cc.dts"
#include "sun8i-h5.dtsi"
And then override the board compatible and model.
Might not work. I'm not sure at this moment.
>
>> Last, the LED polarity is wrong. This is due to the EMAC driver not
>> following the DT binding and looking for the "allwinner,leds-active-low"
>> under the PHY node, instead of the EMAC node. I've notified Corentin of
>> this issue.
>
> The DT should be correct, even if the code isn't. This seems to be a
> driver bug that should be fixed, but we don't want to change the DT.
So I'll leave it as is, as in the DT is correct.
>
>> [1] https://www.kickstarter.com/projects/librecomputer/libre-computer-board-tritium-sbc-linux-android-7-n
>> [2] http://www.banana-pi.org/m2plus.html
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts | 196 +++++++++++++++++++++
>> 2 files changed, 197 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 3c139c63098f..aa68f719692f 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -953,6 +953,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>> sun8i-h2-plus-orangepi-zero.dtb \
>> sun8i-h3-bananapi-m2-plus.dtb \
>> sun8i-h3-beelink-x2.dtb \
>> + sun8i-h3-libretech-all-h3-cc.dtb \
>
> Any reason to use the code name and not the "marketing" name?
I've asked and this is the preferred name. "Tritium" is more of an internal
codename.
>
>> sun8i-h3-nanopi-m1.dtb \
>> sun8i-h3-nanopi-m1-plus.dtb \
>> sun8i-h3-nanopi-neo.dtb \
>> diff --git a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
>> new file mode 100644
>> index 000000000000..6f544e007f71
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
>> @@ -0,0 +1,196 @@
>> +/*
>> + * Copyright (C) 2017 Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
>> + *
>> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> + */
>> +
>> +/dts-v1/;
>> +#include "sun8i-h3.dtsi"
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/input.h>
>> +
>> +/ {
>> + model = "Libre Computer Board ALL-H3-CC H3";
>> + compatible = "libretech,all-h3-cc", "allwinner,sun8i-h3";
>> +
>> + aliases {
>> + ethernet0 = &emac;
>> + serial0 = &uart0;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> +
>> + pwr_led {
>> + label = "librecomputer:pwr";
>
> You should have the color there too.
>
>> + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
>> + default-state = "on";
>> + };
>> +
>> + status_led {
>> + label = "librecomputer:status";
>
> Same thing here.
OK.
>
>> + gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
>> + };
>> + };
>> +
>> + gpio_keys {
>> + compatible = "gpio-keys";
>> +
>> + recovery {
>> + label = "recovery";
>> + linux,code = <BTN_0>;
>
> How did you pick that keycode?
It's the same as the Orange Pis. The board however does mark it as
"Power Key". However the H3 (on mainline) does not have the ability
to come back up once powered down, nor do we have the ability to
power it off right now. (We could turn it off using "gpio-poweroff",
though I'm sensing the GPIO usage would conflict with the regulator
drivers.) I'll ask about the intended usage and behavior.
ChenYu
>
> Looks good otherwise, thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
>
> --
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^ permalink raw reply
* Re: [PATCH v2 14/35] nds32: System calls handling
From: Arnd Bergmann @ 2017-11-28 9:23 UTC (permalink / raw)
To: Vincent Chen
Cc: Greentime Hu, Greentime, Linux Kernel Mailing List, linux-arch,
Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
Networking, DTML, Al Viro, David Howells, Will Deacon,
Daniel Lezcano, linux-serial, Vincent Chen
In-Reply-To: <CAJsyPhyep2xp1tANCUO=p9GwsAFZGcV=EdFnjdem8v3-o--O=Q@mail.gmail.com>
On Tue, Nov 28, 2017 at 3:18 AM, Vincent Chen <deanbo422@gmail.com> wrote:
> 2017-11-27 22:46 GMT+08:00 Arnd Bergmann <arnd@arndb.de>:
>> On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu <green.hu@gmail.com> wrote:
>>> diff --git a/arch/nds32/include/uapi/asm/unistd.h b/arch/nds32/include/uapi/asm/unistd.h
>>> new file mode 100644
>>> index 0000000..2bad1e7
>>> --- /dev/null
>>> +++ b/arch/nds32/include/uapi/asm/unistd.h
>>
>>> +
>>> +#define __ARCH_WANT_RENAMEAT
>>> +#define __ARCH_WANT_SYSCALL_OFF_T
>>
>> These two should not be here.
>>
>
> Thanks.
> But, I don't know I should move these two macro to which file.
> In asm-generic/unistd.h, these two are used to decide whether relative
> syscall number is defined or not.
> Therefore, I put these two macros here in order that these two
> definitions are available in user space.
What I meant is that they should not be available to user space.
The C libraries implement the user space interfaces based
on the replacement system calls, e.g. an application calling
the glibc stat() function will end up in the sys_stat64() system
call entry point, not the older sys_newstat().
Arnd
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: renesas: r8a7795: Move nodes which have no reg property out of bus
From: Geert Uytterhoeven @ 2017-11-28 9:04 UTC (permalink / raw)
To: Simon Horman
Cc: Linux-Renesas, linux-arm-kernel@lists.infradead.org, Magnus Damm,
Arnd Bergmann, Rob Herring, Geert Uytterhoeven,
devicetree@vger.kernel.org
In-Reply-To: <20171128085645.ofrk33bfqd736sip@verge.net.au>
Hi Simon,
On Tue, Nov 28, 2017 at 9:56 AM, Simon Horman <horms@verge.net.au> wrote:
> On Mon, Nov 27, 2017 at 12:15:39PM +0100, Geert Uytterhoeven wrote:
>> On Mon, Nov 27, 2017 at 12:04 PM, Simon Horman <horms@verge.net.au> wrote:
>> > I just noticed that with this patch applied I now see:
>> >
>> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a57
>> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a53
>> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a57
>> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a53arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (interrupts_property): Missing interrupt-parent for /timer
>> >
>> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (interrupts_property): Missing interrupt-parent for /timer
>>
>> Right, the "interrupt-parent = <&gic>;" inside the /soc node applies to child
>> nodes of the /soc node only.
>>
>> You can find this in two ways:
s/find/fix/
>>
>> 1. Add "interrupt-parent = <&gic>;" to the /pmu_a57 and /pmu_a53 nodes.
>> 2. Switch those nodes from "interrupt" to "interrupts-extended", e.g. turn
>>
>> interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
>>
>> into
>>
>> interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
>>
>> The latter is what e.g. arch/arm/boot/dts/armada-375.dtsi does.
>
> Thanks, I took option 1 as it seems consistent with the rest of the
> Renesas DT files. I also added it to the /timer node.
Actually we recently had a discussion about this on IRC, triggered by a
similar issue in board files (see e.g, Ethernet PHY interrupts).
Given the following comment:
drivers/of/irq.c: /* Try the new-style interrupts-extended first */
drivers/of/irq.c: res = of_parse_phandle_with_args(device,
"interrupts-extended",
I think it would be better to use interrupts-extended for individual/isolated
use outside the /soc node.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v3] arm64: dts: renesas: r8a7795: Move nodes which have no reg property out of bus
From: Simon Horman @ 2017-11-28 8:58 UTC (permalink / raw)
To: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Magnus Damm,
Arnd Bergmann, Rob Herring, Geert Uytterhoeven,
devicetree-u79uwXL29TY76Z2rM5mHXA, Simon Horman
Move pmu_a5[73], timer and thermal-zones nodes from soc node to root node.
The nodes that have been moved do not have any register properties and thus
shouldn't be placed on the bus.
This problem is flagged by the compiler as follows:
$ make
...
DTC arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
DTC arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
DTC arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
DTC arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb
arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
DTC arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb
arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
DTC arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
DTC arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
Signed-off-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
---
v3
* Add interrupt-parent property to /pmu_* and /timer nodes as
it is no longer inherited from the parent node
v2
* Preserve alphabetical order of nodes present in root node.
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 137 ++++++++++++++++---------------
1 file changed, 70 insertions(+), 67 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 6db4f10376a1..b8e5b7194aee 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -184,6 +184,32 @@
clock-frequency = <0>;
};
+ pmu_a57 {
+ compatible = "arm,cortex-a57-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a57_0>,
+ <&a57_1>,
+ <&a57_2>,
+ <&a57_3>;
+ };
+
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>,
+ <&a53_1>,
+ <&a53_2>,
+ <&a53_3>;
+ };
+
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@@ -338,42 +364,6 @@
resets = <&cpg 905>;
};
- pmu_a57 {
- compatible = "arm,cortex-a57-pmu";
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a57_0>,
- <&a57_1>,
- <&a57_2>,
- <&a57_3>;
- };
-
- pmu_a53 {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a53_0>,
- <&a53_1>,
- <&a53_2>,
- <&a53_3>;
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7795-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@@ -2331,47 +2321,60 @@
#thermal-sensor-cells = <1>;
status = "okay";
};
+ };
- thermal-zones {
- sensor_thermal1: sensor-thermal1 {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 0>;
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
- trips {
- sensor1_crit: sensor1-crit {
- temperature = <120000>;
- hysteresis = <2000>;
- type = "critical";
- };
+ thermal-zones {
+ sensor_thermal1: sensor-thermal1 {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsc 0>;
+
+ trips {
+ sensor1_crit: sensor1-crit {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "critical";
};
};
+ };
- sensor_thermal2: sensor-thermal2 {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 1>;
+ sensor_thermal2: sensor-thermal2 {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsc 1>;
- trips {
- sensor2_crit: sensor2-crit {
- temperature = <120000>;
- hysteresis = <2000>;
- type = "critical";
- };
+ trips {
+ sensor2_crit: sensor2-crit {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "critical";
};
};
+ };
- sensor_thermal3: sensor-thermal3 {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 2>;
+ sensor_thermal3: sensor-thermal3 {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsc 2>;
- trips {
- sensor3_crit: sensor3-crit {
- temperature = <120000>;
- hysteresis = <2000>;
- type = "critical";
- };
+ trips {
+ sensor3_crit: sensor3-crit {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "critical";
};
};
};
--
2.11.0
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^ permalink raw reply related
* [bbb-overlays] Fixing overlay configfs for v4.15-rc1
From: Geert Uytterhoeven @ 2017-11-28 8:57 UTC (permalink / raw)
To: Pantelis Antoniou
Cc: Frank Rowand, Rob Herring, devicetree@vger.kernel.org,
Linux-Renesas, linux-kernel@vger.kernel.org
Hi Pantelis,
Thanks to the rework of the overlay code in v4.15-rc1, the current overlay
configfs code no longer applies cleanly (that's what I call an understatement
;-).
I have rebased my topic/overlays and topic/renesas-overlays branches on top
of v4.15-rc1. Feel free to have a look, it seems to work.
The old versions (for v4.14) are still available in topic/overlays-v4.14
resp. topic/renesas-overlays-v4.14.
All topic branches mentioned above can be found in my repo at:
https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: renesas: r8a7795: Move nodes which have no reg property out of bus
From: Simon Horman @ 2017-11-28 8:56 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Linux-Renesas,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Magnus Damm, Arnd Bergmann, Rob Herring, Geert Uytterhoeven,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAMuHMdUm=PiGVWVg9pyNTR5z2WjLcoG1uecBNBeKsSxbAxBt8w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Mon, Nov 27, 2017 at 12:15:39PM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Mon, Nov 27, 2017 at 12:04 PM, Simon Horman <horms-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org> wrote:
> > On Fri, Nov 24, 2017 at 12:09:47PM +0100, Geert Uytterhoeven wrote:
> >> On Fri, Nov 24, 2017 at 11:52 AM, Simon Horman
> >> <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org> wrote:
> >> > Move pmu_a5[73], timer and thermal-zones nodes from soc node to root node.
> >> > The nodes that have been moved do not have any register properties and thus
> >> > shouldn't be placed on the bus.
> >> >
> >> > This problem is flagged by the compiler as follows:
> >> > $ make
> >> > ...
> >> > DTC arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb
> >> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> >> > DTC arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb
> >> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> >> > DTC arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb
> >> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> >> > DTC arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb
> >> > arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> >> > DTC arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb
> >> > arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> >> > DTC arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb
> >> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> >> > DTC arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb
> >> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> >> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> >> >
> >> > Signed-off-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
> >> > ---
> >> > v2
> >> > * Preserve alphabetical order of nodes present in root node.
> >>
> >> Thanks for the update!
> >>
> >> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
> >
> > I just noticed that with this patch applied I now see:
> >
> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a57
> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a53
> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a57
> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a53arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (interrupts_property): Missing interrupt-parent for /timer
> >
> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (interrupts_property): Missing interrupt-parent for /timer
>
> Right, the "interrupt-parent = <&gic>;" inside the /soc node applies to child
> nodes of the /soc node only.
>
> You can find this in two ways:
>
> 1. Add "interrupt-parent = <&gic>;" to the /pmu_a57 and /pmu_a53 nodes.
> 2. Switch those nodes from "interrupt" to "interrupts-extended", e.g. turn
>
> interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
>
> into
>
> interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
>
> The latter is what e.g. arch/arm/boot/dts/armada-375.dtsi does.
Thanks, I took option 1 as it seems consistent with the rest of the
Renesas DT files. I also added it to the /timer node.
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^ permalink raw reply
* Re: [PATCH] ARM: dts: sun8i: h3: Add dts file for Libre Computer Board ALL-H3-CC H3 ver.
From: Maxime Ripard @ 2017-11-28 8:43 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Corentin Labbe
In-Reply-To: <20171128041211.17375-1-wens-jdAy2FN1RRM@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 5987 bytes --]
Hi,
On Tue, Nov 28, 2017 at 12:12:11PM +0800, Chen-Yu Tsai wrote:
> The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
> Pi B+ form factor single board computer based on the Allwinner H3 SoC.
> The board has 1GB DDR3 SDRAM, provided by 4 2Gb chips. The mounting holes
> and connectors are in the exact same position as on the Raspberry Pi B+.
>
> Raspberry Pi B+ like peripherals supported on this board include:
>
> - Power input through micro-USB connector (without USB OTG)
> - Native 100 Mbps ethernet using the internal PHY, as opposed to
> USB-based on the RPi
> - 4x USB 2.0 host ports, directly connected to the SoC, as opposed to
> being connected through a USB 2.0 hub on the RPi
> - TV and audio output on a 3.5mm TRRS jack
> - HDMI output
> - Micro-SD card slot
> - Standard RPi B+ GPIO header, with the standard peripherals routed to
> the same pins.
>
> * 5V, 3.3V power, and ground
> * I2C0 on the H3 is routed to I2C1 pins on the RPi header
> * I2C1 on the H3 is routed to I2C0 pins on the RPi header
> * UART1 on the H3 is routed to UART0 pins on the RPi header
> * SPI0 on the H3 is routed to SPI0 pins on the RPi header,
> with GPIO pin PA17 replacing the missing Chip Select 1
> * I2S1 on the H3 is routed to PCM pins on the RPi header
>
> - Additional peripherals from the H3 are available on different pins.
> These include I2S0, JTAG, PWM1, SPDIF, SPI1, and UART3
>
> In addition, there are a number of new features:
>
> - Console UART header
> - Consumer IR receiver
> - Camera interface (not compatible with RPi)
> - Onboard microphone
> - eMMC expansion module port
> - Heatsink mounting holes
>
> This patch adds a dts file for this board that enables all "onboard"
> peripherals currently supported. This means no display or camera
> support.
>
> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> ---
>
> There are two other variants [1] of this board, with different SoCs and
> DRAM configuration. But the board remains the same, thanks to the SoCs
> being pin compatible.
>
> Do we need different board compatible strings?
Yes.
> FWIW the soc compatible string already encodes the soc variant, and
> the DRAM stuff is handled by the bootloader. The filename also has
> the SoC family and chip name. The displayed board model also has
> the SoC variant included. The board itself is named "ALL-H3-CC".
The point of a board compatible is to identify the way a board
behaves. If we ever need to make any quirks for one particular board,
we have to have a compatible that uniquely identifies it.
However, we can have an intermediate compatible as well to catch all
those similar boards.
Something like:
compatible = "libretech,h3-tritium", "libretech,tritium", "allwinner,sun8i-h3";
> I'm asking as we have the same issue with the Bananapi M2+ [2], where
> they've released new variants with different SoCs and DRAM capacities
> using the same board. Not sure if they are commercially available though.
You can have a look at the way we handled all the q8 tablets that were
pretty much in the same case. It's been working quite well.
> Last, the LED polarity is wrong. This is due to the EMAC driver not
> following the DT binding and looking for the "allwinner,leds-active-low"
> under the PHY node, instead of the EMAC node. I've notified Corentin of
> this issue.
The DT should be correct, even if the code isn't. This seems to be a
driver bug that should be fixed, but we don't want to change the DT.
> [1] https://www.kickstarter.com/projects/librecomputer/libre-computer-board-tritium-sbc-linux-android-7-n
> [2] http://www.banana-pi.org/m2plus.html
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts | 196 +++++++++++++++++++++
> 2 files changed, 197 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 3c139c63098f..aa68f719692f 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -953,6 +953,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-h2-plus-orangepi-zero.dtb \
> sun8i-h3-bananapi-m2-plus.dtb \
> sun8i-h3-beelink-x2.dtb \
> + sun8i-h3-libretech-all-h3-cc.dtb \
Any reason to use the code name and not the "marketing" name?
> sun8i-h3-nanopi-m1.dtb \
> sun8i-h3-nanopi-m1-plus.dtb \
> sun8i-h3-nanopi-neo.dtb \
> diff --git a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
> new file mode 100644
> index 000000000000..6f544e007f71
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
> @@ -0,0 +1,196 @@
> +/*
> + * Copyright (C) 2017 Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> + *
> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + */
> +
> +/dts-v1/;
> +#include "sun8i-h3.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> + model = "Libre Computer Board ALL-H3-CC H3";
> + compatible = "libretech,all-h3-cc", "allwinner,sun8i-h3";
> +
> + aliases {
> + ethernet0 = &emac;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + pwr_led {
> + label = "librecomputer:pwr";
You should have the color there too.
> + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
> + default-state = "on";
> + };
> +
> + status_led {
> + label = "librecomputer:status";
Same thing here.
> + gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
> + };
> + };
> +
> + gpio_keys {
> + compatible = "gpio-keys";
> +
> + recovery {
> + label = "recovery";
> + linux,code = <BTN_0>;
How did you pick that keycode?
Looks good otherwise, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH] of: overlay: Remove else after goto
From: Geert Uytterhoeven @ 2017-11-28 8:26 UTC (permalink / raw)
To: Rob Herring, Frank Rowand, Pantelis Antoniou
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Geert Uytterhoeven
If an "if" branch is terminated by a "goto", there's no need to have an
"else" statement and an indented block of code.
Remove the "else" statement to simplify the code flow for the casual
reviewer.
Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
drivers/of/overlay.c | 25 ++++++++++---------------
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
index 8676411bd3e6f29f..53bc9e3f0b985415 100644
--- a/drivers/of/overlay.c
+++ b/drivers/of/overlay.c
@@ -580,9 +580,9 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
of_node_put(fragment->overlay);
ret = -EINVAL;
goto err_free_fragments;
- } else {
- cnt++;
}
+
+ cnt++;
}
}
@@ -736,14 +736,12 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id)
devicetree_state_flags |= DTSF_APPLY_FAIL;
}
goto err_free_overlay_changeset;
- } else {
- ret = __of_changeset_apply_notify(&ovcs->cset);
- if (ret)
- pr_err("overlay changeset entry notify error %d\n",
- ret);
- /* fall through */
}
+ ret = __of_changeset_apply_notify(&ovcs->cset);
+ if (ret)
+ pr_err("overlay changeset entry notify error %d\n", ret);
+
list_add_tail(&ovcs->ovcs_list, &ovcs_list);
*ovcs_id = ovcs->id;
@@ -931,15 +929,12 @@ int of_overlay_remove(int *ovcs_id)
if (ret_apply)
devicetree_state_flags |= DTSF_REVERT_FAIL;
goto out_unlock;
- } else {
- ret = __of_changeset_revert_notify(&ovcs->cset);
- if (ret) {
- pr_err("overlay changeset entry notify error %d\n",
- ret);
- /* fall through - changeset was reverted */
- }
}
+ ret = __of_changeset_revert_notify(&ovcs->cset);
+ if (ret)
+ pr_err("overlay changeset entry notify error %d\n", ret);
+
*ovcs_id = 0;
ret_tmp = overlay_notify(ovcs, OF_OVERLAY_POST_REMOVE);
--
2.7.4
--
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^ permalink raw reply related
* [PATCH] of: Spelling s/changset/changeset/
From: Geert Uytterhoeven @ 2017-11-28 8:25 UTC (permalink / raw)
To: Rob Herring, Frank Rowand, Pantelis Antoniou
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Geert Uytterhoeven
Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
drivers/of/dynamic.c | 4 ++--
drivers/of/overlay.c | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/of/dynamic.c b/drivers/of/dynamic.c
index c454941b34ec8aa7..ab988d88704da0d2 100644
--- a/drivers/of/dynamic.c
+++ b/drivers/of/dynamic.c
@@ -695,7 +695,7 @@ int __of_changeset_apply_entries(struct of_changeset *ocs, int *ret_revert)
/*
* Returns 0 on success, a negative error value in case of an error.
*
- * If multiple changset entry notification errors occur then only the
+ * If multiple changeset entry notification errors occur then only the
* final notification error is reported.
*/
int __of_changeset_apply_notify(struct of_changeset *ocs)
@@ -795,7 +795,7 @@ int __of_changeset_revert_entries(struct of_changeset *ocs, int *ret_apply)
}
/*
- * If multiple changset entry notification errors occur then only the
+ * If multiple changeset entry notification errors occur then only the
* final notification error is reported.
*/
int __of_changeset_revert_notify(struct of_changeset *ocs)
diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
index 3b7a3980ff50d6bf..8676411bd3e6f29f 100644
--- a/drivers/of/overlay.c
+++ b/drivers/of/overlay.c
@@ -660,14 +660,14 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs)
* A non-zero return value will not have created the changeset if error is from:
* - parameter checks
* - building the changeset
- * - overlay changset pre-apply notifier
+ * - overlay changeset pre-apply notifier
*
* If an error is returned by an overlay changeset pre-apply notifier
* then no further overlay changeset pre-apply notifier will be called.
*
* A non-zero return value will have created the changeset if error is from:
* - overlay changeset entry notifier
- * - overlay changset post-apply notifier
+ * - overlay changeset post-apply notifier
*
* If an error is returned by an overlay changeset post-apply notifier
* then no further overlay changeset post-apply notifier will be called.
@@ -871,7 +871,7 @@ static int overlay_removal_is_ok(struct overlay_changeset *remove_ovcs)
*
* A non-zero return value will not revert the changeset if error is from:
* - parameter checks
- * - overlay changset pre-remove notifier
+ * - overlay changeset pre-remove notifier
* - overlay changeset entry revert
*
* If an error is returned by an overlay changeset pre-remove notifier
@@ -882,7 +882,7 @@ static int overlay_removal_is_ok(struct overlay_changeset *remove_ovcs)
*
* A non-zero return value will revert the changeset if error is from:
* - overlay changeset entry notifier
- * - overlay changset post-remove notifier
+ * - overlay changeset post-remove notifier
*
* If an error is returned by an overlay changeset post-remove notifier
* then no further overlay changeset post-remove notifier will be called.
--
2.7.4
--
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^ permalink raw reply related
* [PATCH] dt-bindings: pinctrl: uniphier: add UniPhier pinctrl binding
From: Masahiro Yamada @ 2017-11-28 7:49 UTC (permalink / raw)
To: linux-gpio
Cc: Mark Rutland, devicetree, Greg Kroah-Hartman, Linus Walleij,
Randy Dunlap, linux-kernel, Masahiro Yamada, Rob Herring,
Mauro Carvalho Chehab, David S. Miller, linux-arm-kernel
The driver has been in the tree for a while, but its binding document
is missing. Hence, here it is.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
.../pinctrl/socionext,uniphier-pinctrl.txt | 27 ++++++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt
new file mode 100644
index 0000000..8173b12
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt
@@ -0,0 +1,27 @@
+UniPhier SoCs pin controller
+
+Required properties:
+- compatible: should be one of the following:
+ "socionext,uniphier-ld4-pinctrl" - for LD4 SoC
+ "socionext,uniphier-pro4-pinctrl" - for Pro4 SoC
+ "socionext,uniphier-sld8-pinctrl" - for sLD8 SoC
+ "socionext,uniphier-pro5-pinctrl" - for Pro5 SoC
+ "socionext,uniphier-pxs2-pinctrl" - for PXs2 SoC
+ "socionext,uniphier-ld6b-pinctrl" - for LD6b SoC
+ "socionext,uniphier-ld11-pinctrl" - for LD11 SoC
+ "socionext,uniphier-ld20-pinctrl" - for LD20 SoC
+ "socionext,uniphier-pxs3-pinctrl" - for PXs3 SoC
+
+Note:
+The UniPhier pinctrl should be a subnode of a "syscon" compatible node.
+
+Example:
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-pro4-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-pro4-pinctrl";
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index aa71ab52f..38b0ddc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2042,6 +2042,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git
S: Maintained
F: Documentation/devicetree/bindings/gpio/gpio-uniphier.txt
+F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt
F: arch/arm/boot/dts/uniphier*
F: arch/arm/include/asm/hardware/cache-uniphier.h
F: arch/arm/mach-uniphier/
--
2.7.4
^ permalink raw reply related
* [PATCH] rtc: add mxc driver for i.MX53
From: linux-kernel-dev @ 2017-11-28 7:39 UTC (permalink / raw)
To: Alessandro Zummo, Alexandre Belloni
Cc: Mark Rutland, open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
Patrick Bruenn,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Russell King, Noel Vellemans, Rob Herring,
Sascha Hauer, Fabio Estevam, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
From: Patrick Bruenn <p.bruenn@beckhoff.com>
Neither rtc-imxdi nor rtc-mxc are compatible with i.MX53.
Add a modernized version of mxc_v2 from here:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/rtc/rtc-mxc_v2.c?h=imx_2.6.35_11.09.01
Changes to that version:
- updated to v4.15-rc1
- removed ioctl()
- removed proc()
- removed manual(redundant) enable_irq flag
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
---
Open issues:
- driver naming, should it be merged with rtc-mxc.c ?
- document DT binding "fsl,imx53-rtc" accordingly
- Should unused defines be removed or kept for someone else to be
useful?
- Is the use of __raw_readl/writel() correct? Should it be replaced with
readl/writel()?
- suspend/resume() seems different to existing rtc-mxc.c, should I apply
the pattern from rtc-mxc.c?
- On Shawns tree imx53.dtsi has been reverted already[1][2]. Should I split
the imx53.dtsi change into a separate patch based on his tree? Or can
we still stop the full revert and just remove the imx25-rtc compatible?
I am not in a hurry, so we could just wait until the revert landed in
Linus tree. Whatever you think is best.
[1] https://www.spinics.net/lists/arm-kernel/msg617113.html
[2] commit ee76f7729babd2700afd6f3874449d8084dd85ea
To: Alessandro Zummo <a.zummo@towertech.it>
To: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc@vger.kernel.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel@vger.kernel.org (open list)
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Juergen Borleis <jbe@pengutronix.de>
Cc: Noel Vellemans <Noel.Vellemans@visionbms.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Russell King <linux@armlinux.org.uk> (maintainer:ARM PORT)
Cc: linux-arm-kernel@lists.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
---
arch/arm/boot/dts/imx53.dtsi | 2 +-
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mxc_v2.c | 531 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 533 insertions(+), 1 deletion(-)
create mode 100644 drivers/rtc/rtc-mxc_v2.c
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 589a67c5f796..3d1a55e11ea8 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -434,7 +434,7 @@
};
srtc: srtc@53fa4000 {
- compatible = "fsl,imx53-rtc", "fsl,imx25-rtc";
+ compatible = "fsl,imx53-rtc";
reg = <0x53fa4000 0x4000>;
interrupts = <24>;
interrupt-parent = <&tzic>;
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index f2f50c11dc38..fb3dc458c185 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -106,6 +106,7 @@ obj-$(CONFIG_RTC_DRV_MT6397) += rtc-mt6397.o
obj-$(CONFIG_RTC_DRV_MT7622) += rtc-mt7622.o
obj-$(CONFIG_RTC_DRV_MV) += rtc-mv.o
obj-$(CONFIG_RTC_DRV_MXC) += rtc-mxc.o
+obj-$(CONFIG_RTC_DRV_MXC) += rtc-mxc_v2.o
obj-$(CONFIG_RTC_DRV_NUC900) += rtc-nuc900.o
obj-$(CONFIG_RTC_DRV_OMAP) += rtc-omap.o
obj-$(CONFIG_RTC_DRV_OPAL) += rtc-opal.o
diff --git a/drivers/rtc/rtc-mxc_v2.c b/drivers/rtc/rtc-mxc_v2.c
new file mode 100644
index 000000000000..5049b521b38e
--- /dev/null
+++ b/drivers/rtc/rtc-mxc_v2.c
@@ -0,0 +1,531 @@
+/*
+ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*
+ * Implementation based on rtc-ds1553.c
+ */
+
+/*!
+ * @defgroup RTC Real Time Clock (RTC) Driver for i.MX53
+ */
+/*!
+ * @file rtc-mxc_v2.c
+ * @brief Real Time Clock interface
+ *
+ * This file contains Real Time Clock interface for Linux.
+ *
+ * @ingroup RTC
+ */
+
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/rtc.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+//#include <linux/mxc_srtc.h>
+#define RTC_READ_TIME_47BIT _IOR('p', 0x20, unsigned long long)
+/* blocks until LPSCMR is set, returns difference */
+#define RTC_WAIT_TIME_SET _IOR('p', 0x21, int64_t)
+
+#define SRTC_LPSCLR_LLPSC_LSH 17 /* start bit for LSB time value */
+
+#define SRTC_LPPDR_INIT 0x41736166 /* init for glitch detect */
+
+#define SRTC_LPCR_SWR_LP (1 << 0) /* lp software reset */
+#define SRTC_LPCR_EN_LP (1 << 3) /* lp enable */
+#define SRTC_LPCR_WAE (1 << 4) /* lp wakeup alarm enable */
+#define SRTC_LPCR_SAE (1 << 5) /* lp security alarm enable */
+#define SRTC_LPCR_SI (1 << 6) /* lp security interrupt enable */
+#define SRTC_LPCR_ALP (1 << 7) /* lp alarm flag */
+#define SRTC_LPCR_LTC (1 << 8) /* lp lock time counter */
+#define SRTC_LPCR_LMC (1 << 9) /* lp lock monotonic counter */
+#define SRTC_LPCR_SV (1 << 10) /* lp security violation */
+#define SRTC_LPCR_NSA (1 << 11) /* lp non secure access */
+#define SRTC_LPCR_NVEIE (1 << 12) /* lp non valid state exit int en */
+#define SRTC_LPCR_IEIE (1 << 13) /* lp init state exit int enable */
+#define SRTC_LPCR_NVE (1 << 14) /* lp non valid state exit bit */
+#define SRTC_LPCR_IE (1 << 15) /* lp init state exit bit */
+
+#define SRTC_LPCR_ALL_INT_EN (SRTC_LPCR_WAE | SRTC_LPCR_SAE | \
+ SRTC_LPCR_SI | SRTC_LPCR_ALP | \
+ SRTC_LPCR_NVEIE | SRTC_LPCR_IEIE)
+
+#define SRTC_LPSR_TRI (1 << 0) /* lp time read invalidate */
+#define SRTC_LPSR_PGD (1 << 1) /* lp power supply glitc detected */
+#define SRTC_LPSR_CTD (1 << 2) /* lp clock tampering detected */
+#define SRTC_LPSR_ALP (1 << 3) /* lp alarm flag */
+#define SRTC_LPSR_MR (1 << 4) /* lp monotonic counter rollover */
+#define SRTC_LPSR_TR (1 << 5) /* lp time rollover */
+#define SRTC_LPSR_EAD (1 << 6) /* lp external alarm detected */
+#define SRTC_LPSR_IT0 (1 << 7) /* lp IIM throttle */
+#define SRTC_LPSR_IT1 (1 << 8)
+#define SRTC_LPSR_IT2 (1 << 9)
+#define SRTC_LPSR_SM0 (1 << 10) /* lp security mode */
+#define SRTC_LPSR_SM1 (1 << 11)
+#define SRTC_LPSR_STATE_LP0 (1 << 12) /* lp state */
+#define SRTC_LPSR_STATE_LP1 (1 << 13)
+#define SRTC_LPSR_NVES (1 << 14) /* lp non-valid state exit status */
+#define SRTC_LPSR_IES (1 << 15) /* lp init state exit status */
+
+#define MAX_PIE_NUM 15
+#define MAX_PIE_FREQ 32768
+#define MIN_PIE_FREQ 1
+
+#define SRTC_PI0 (1 << 0)
+#define SRTC_PI1 (1 << 1)
+#define SRTC_PI2 (1 << 2)
+#define SRTC_PI3 (1 << 3)
+#define SRTC_PI4 (1 << 4)
+#define SRTC_PI5 (1 << 5)
+#define SRTC_PI6 (1 << 6)
+#define SRTC_PI7 (1 << 7)
+#define SRTC_PI8 (1 << 8)
+#define SRTC_PI9 (1 << 9)
+#define SRTC_PI10 (1 << 10)
+#define SRTC_PI11 (1 << 11)
+#define SRTC_PI12 (1 << 12)
+#define SRTC_PI13 (1 << 13)
+#define SRTC_PI14 (1 << 14)
+#define SRTC_PI15 (1 << 15)
+
+#define PIT_ALL_ON (SRTC_PI1 | SRTC_PI2 | SRTC_PI3 | \
+ SRTC_PI4 | SRTC_PI5 | SRTC_PI6 | SRTC_PI7 | \
+ SRTC_PI8 | SRTC_PI9 | SRTC_PI10 | SRTC_PI11 | \
+ SRTC_PI12 | SRTC_PI13 | SRTC_PI14 | SRTC_PI15)
+
+#define SRTC_SWR_HP (1 << 0) /* hp software reset */
+#define SRTC_EN_HP (1 << 3) /* hp enable */
+#define SRTC_TS (1 << 4) /* time synchronize hp with lp */
+
+#define SRTC_IE_AHP (1 << 16) /* Alarm HP Interrupt Enable bit */
+#define SRTC_IE_WDHP (1 << 18) /* Write Done HP Interrupt Enable bit */
+#define SRTC_IE_WDLP (1 << 19) /* Write Done LP Interrupt Enable bit */
+
+#define SRTC_ISR_AHP (1 << 16) /* interrupt status: alarm hp */
+#define SRTC_ISR_WDHP (1 << 18) /* interrupt status: write done hp */
+#define SRTC_ISR_WDLP (1 << 19) /* interrupt status: write done lp */
+#define SRTC_ISR_WPHP (1 << 20) /* interrupt status: write pending hp */
+#define SRTC_ISR_WPLP (1 << 21) /* interrupt status: write pending lp */
+
+#define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
+#define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
+#define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
+#define SRTC_LPSMCR 0x0C /* LP Secure Monotonic Counter Reg */
+#define SRTC_LPCR 0x10 /* LP Control Reg */
+#define SRTC_LPSR 0x14 /* LP Status Reg */
+#define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
+#define SRTC_LPGR 0x1C /* LP General Purpose Reg */
+#define SRTC_HPCMR 0x20 /* HP Counter MSB Reg */
+#define SRTC_HPCLR 0x24 /* HP Counter LSB Reg */
+#define SRTC_HPAMR 0x28 /* HP Alarm MSB Reg */
+#define SRTC_HPALR 0x2C /* HP Alarm LSB Reg */
+#define SRTC_HPCR 0x30 /* HP Control Reg */
+#define SRTC_HPISR 0x34 /* HP Interrupt Status Reg */
+#define SRTC_HPIENR 0x38 /* HP Interrupt Enable Reg */
+
+#define SRTC_SECMODE_MASK 0x3 /* the mask of SRTC security mode */
+#define SRTC_SECMODE_LOW 0x0 /* Low Security */
+#define SRTC_SECMODE_MED 0x1 /* Medium Security */
+#define SRTC_SECMODE_HIGH 0x2 /* High Security */
+#define SRTC_SECMODE_RESERVED 0x3 /* Reserved */
+
+struct rtc_drv_data {
+ struct rtc_device *rtc;
+ void __iomem *ioaddr;
+ int irq;
+ struct clk *clk;
+};
+
+static DEFINE_SPINLOCK(rtc_lock);
+
+/*!
+ * This function does write synchronization for writes to the lp srtc block.
+ * To take care of the asynchronous CKIL clock, all writes from the IP domain
+ * will be synchronized to the CKIL domain.
+ */
+static inline void rtc_write_sync_lp(void __iomem *ioaddr)
+{
+ unsigned int i, count;
+ /* Wait for 3 CKIL cycles */
+ for (i = 0; i < 3; i++) {
+ count = readl(ioaddr + SRTC_LPSCLR);
+ while ((readl(ioaddr + SRTC_LPSCLR)) == count)
+ ;
+ }
+}
+
+/*!
+ * This function updates the RTC alarm registers and then clears all the
+ * interrupt status bits.
+ *
+ * @param alrm the new alarm value to be updated in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
+{
+ struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+ void __iomem *ioaddr = pdata->ioaddr;
+ struct rtc_time alarm_tm, now_tm;
+ unsigned long now, time;
+ int ret;
+
+ now = __raw_readl(ioaddr + SRTC_LPSCMR);
+ rtc_time_to_tm(now, &now_tm);
+
+ alarm_tm.tm_year = now_tm.tm_year;
+ alarm_tm.tm_mon = now_tm.tm_mon;
+ alarm_tm.tm_mday = now_tm.tm_mday;
+
+ alarm_tm.tm_hour = alrm->tm_hour;
+ alarm_tm.tm_min = alrm->tm_min;
+ alarm_tm.tm_sec = alrm->tm_sec;
+
+ rtc_tm_to_time(&now_tm, &now);
+ rtc_tm_to_time(&alarm_tm, &time);
+
+ if (time < now) {
+ time += 60 * 60 * 24;
+ rtc_time_to_tm(time, &alarm_tm);
+ }
+ ret = rtc_tm_to_time(&alarm_tm, &time);
+
+ __raw_writel(time, ioaddr + SRTC_LPSAR);
+
+ /* clear alarm interrupt status bit */
+ __raw_writel(SRTC_LPSR_ALP, ioaddr + SRTC_LPSR);
+
+ return ret;
+}
+
+/*!
+ * This function is the RTC interrupt service routine.
+ *
+ * @param irq RTC IRQ number
+ * @param dev_id device ID which is not used
+ *
+ * @return IRQ_HANDLED as defined in the include/linux/interrupt.h file.
+ */
+static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
+{
+ struct platform_device *pdev = dev_id;
+ struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+ void __iomem *ioaddr = pdata->ioaddr;
+ u32 lp_status, lp_cr;
+ u32 events = 0;
+
+ lp_status = __raw_readl(ioaddr + SRTC_LPSR);
+ lp_cr = __raw_readl(ioaddr + SRTC_LPCR);
+
+ /* update irq data & counter */
+ if (lp_status & SRTC_LPSR_ALP) {
+ if (lp_cr & SRTC_LPCR_ALP)
+ events |= (RTC_AF | RTC_IRQF);
+
+ /* disable further lp alarm interrupts */
+ lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+ }
+
+ /* Update interrupt enables */
+ __raw_writel(lp_cr, ioaddr + SRTC_LPCR);
+
+ /* clear interrupt status */
+ __raw_writel(lp_status, ioaddr + SRTC_LPSR);
+
+ rtc_write_sync_lp(ioaddr);
+ rtc_update_irq(pdata->rtc, 1, events);
+ return IRQ_HANDLED;
+}
+
+/*!
+ * This function reads the current RTC time into tm in Gregorian date.
+ *
+ * @param tm contains the RTC time value upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+ time_t now = readl(pdata->ioaddr + SRTC_LPSCMR);
+
+ rtc_time_to_tm(now, tm);
+ return rtc_valid_tm(tm);
+}
+
+/*!
+ * This function sets the internal RTC time based on tm in Gregorian date.
+ *
+ * @param tm the time value to be set in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+ time64_t time = rtc_tm_to_time64(tm);
+
+ if (time > UINT_MAX) {
+ dev_warn(dev, "time_t has overflow\n");
+ }
+
+ writel(time, pdata->ioaddr + SRTC_LPSCMR);
+ rtc_write_sync_lp(pdata->ioaddr);
+ return 0;
+}
+
+/*!
+ * This function reads the current alarm value into the passed in \b alrm
+ * argument. It updates the \b alrm's pending field value based on the whether
+ * an alarm interrupt occurs or not.
+ *
+ * @param alrm contains the RTC alarm value upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+ void __iomem *ioaddr = pdata->ioaddr;
+
+ rtc_time_to_tm(__raw_readl(ioaddr + SRTC_LPSAR), &alrm->time);
+ alrm->pending =
+ ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP) != 0) ? 1 : 0;
+
+ return 0;
+}
+
+static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
+{
+ struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+ unsigned long lock_flags = 0;
+ u32 lp_cr;
+
+ spin_lock_irqsave(&rtc_lock, lock_flags);
+ lp_cr = __raw_readl(pdata->ioaddr + SRTC_LPCR);
+
+ if (enable)
+ lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+ else
+ lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+
+ __raw_writel(lp_cr, pdata->ioaddr + SRTC_LPCR);
+ spin_unlock_irqrestore(&rtc_lock, lock_flags);
+ return 0;
+}
+
+/*!
+ * This function sets the RTC alarm based on passed in alrm.
+ *
+ * @param alrm the alarm value to be set in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+ void __iomem *ioaddr = pdata->ioaddr;
+ int ret;
+
+ ret = rtc_update_alarm(dev, &alrm->time);
+ if (!ret)
+ mxc_rtc_alarm_irq_enable(dev, alrm->enabled);
+
+ rtc_write_sync_lp(ioaddr);
+ return ret;
+}
+
+/*!
+ * The RTC driver structure
+ */
+static const struct rtc_class_ops mxc_rtc_ops = {
+ .read_time = mxc_rtc_read_time,
+ .set_time = mxc_rtc_set_time,
+ .read_alarm = mxc_rtc_read_alarm,
+ .set_alarm = mxc_rtc_set_alarm,
+ .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
+};
+
+/*! MXC RTC Power management control */
+static int mxc_rtc_probe(struct platform_device *pdev)
+{
+ struct timespec tv;
+ struct resource *res;
+ struct rtc_drv_data *pdata = NULL;
+ void __iomem *ioaddr;
+ int ret = 0;
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pdata->ioaddr))
+ return PTR_ERR(pdata->ioaddr);
+
+ ioaddr = pdata->ioaddr;
+
+ pdata->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pdata->clk)) {
+ dev_err(&pdev->dev, "unable to get rtc clock!\n");
+ return PTR_ERR(pdata->clk);
+ }
+ ret = clk_prepare_enable(pdata->clk);
+ if (ret)
+ return ret;
+
+ /* Configure and enable the RTC */
+ pdata->irq = platform_get_irq(pdev, 0);
+ if (pdata->irq >= 0
+ && devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
+ IRQF_SHARED, pdev->name, pdev) < 0) {
+ dev_warn(&pdev->dev, "interrupt not available.\n");
+ pdata->irq = -1;
+ }
+
+ if (pdata->irq >= 0)
+ device_init_wakeup(&pdev->dev, 1);
+
+ /* initialize glitch detect */
+ __raw_writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
+ udelay(100);
+
+ /* clear lp interrupt status */
+ __raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
+ udelay(100);
+
+ /* move out of init state */
+ __raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), ioaddr + SRTC_LPCR);
+
+ udelay(100);
+
+ while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_IES) == 0)
+ ;
+
+ /* move out of non-valid state */
+ __raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
+ SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
+
+ udelay(100);
+
+ while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_NVES) == 0)
+ ;
+
+ __raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
+ udelay(100);
+
+ platform_set_drvdata(pdev, pdata);
+ pdata->rtc =
+ devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
+ THIS_MODULE);
+ if (IS_ERR(pdata->rtc)) {
+ ret = PTR_ERR(pdata->rtc);
+ goto exit_put_clk;
+ }
+
+ tv.tv_nsec = 0;
+ tv.tv_sec = __raw_readl(ioaddr + SRTC_LPSCMR);
+
+ /* By default, devices should wakeup if they can */
+ /* So srtc is set as "should wakeup" as it can */
+ device_init_wakeup(&pdev->dev, 1);
+
+ return ret;
+
+exit_put_clk:
+ clk_disable_unprepare(pdata->clk);
+ return ret;
+}
+
+static int __exit mxc_rtc_remove(struct platform_device *pdev)
+{
+ struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(pdata->clk);
+ return 0;
+}
+
+/*!
+ * This function is called to save the system time delta relative to
+ * the MXC RTC when enterring a low power state. This time delta is
+ * then used on resume to adjust the system time to account for time
+ * loss while suspended.
+ *
+ * @param pdev not used
+ * @param state Power state to enter.
+ *
+ * @return The function always returns 0.
+ */
+static int mxc_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+
+ if (device_may_wakeup(&pdev->dev))
+ enable_irq_wake(pdata->irq);
+
+ return 0;
+}
+
+/*!
+ * This function is called to correct the system time based on the
+ * current MXC RTC time relative to the time delta saved during
+ * suspend.
+ *
+ * @param pdev not used
+ *
+ * @return The function always returns 0.
+ */
+static int mxc_rtc_resume(struct platform_device *pdev)
+{
+ struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+
+ if (device_may_wakeup(&pdev->dev))
+ disable_irq_wake(pdata->irq);
+
+ return 0;
+}
+
+static const struct of_device_id mxc_ids[] = {
+ {.compatible = "fsl,imx53-rtc",},
+ {}
+};
+
+/*!
+ * Contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxc_rtc_driver = {
+ .driver = {
+ .name = "mxc_rtc_v8",
+ .of_match_table = mxc_ids,
+ },
+ .probe = mxc_rtc_probe,
+ .remove = mxc_rtc_remove,
+ .suspend = mxc_rtc_suspend,
+ .resume = mxc_rtc_resume,
+};
+
+module_platform_driver(mxc_rtc_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Realtime Clock Driver (RTC)");
+MODULE_LICENSE("GPL");
--
2.11.0
^ permalink raw reply related
* [PATCH] dt-bindings: uniphier: add bindings for UniPhier SoC family
From: Masahiro Yamada @ 2017-11-28 7:29 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring
Cc: Andreas Färber, Masahiro Yamada, Mauro Carvalho Chehab,
Randy Dunlap, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
David S. Miller, Rob Herring, Greg Kroah-Hartman, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Signed-off-by: Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
---
Documentation/devicetree/bindings/arm/uniphier.txt | 40 ++++++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/uniphier.txt
diff --git a/Documentation/devicetree/bindings/arm/uniphier.txt b/Documentation/devicetree/bindings/arm/uniphier.txt
new file mode 100644
index 0000000..08d3cf3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/uniphier.txt
@@ -0,0 +1,40 @@
+Socionext UniPhier SoC family
+
+Required properties in the root node:
+ - compatible: should contain board and SoC compatible strings
+
+ SoC compatibles:
+ - "socionext,uniphier-ld4" - LD4 SoC
+ - "socionext,uniphier-pro4" - Pro4 SoC
+ - "socionext,uniphier-sld8" - sLD8 SoC
+ - "socionext,uniphier-pro5" - Pro5 SoC
+ - "socionext,uniphier-pxs2" - PXs2 SoC
+ - "socionext,uniphier-ld6b" - LD6b SoC
+ - "socionext,uniphier-ld11" - LD11 SoC
+ - "socionext,uniphier-ld20" - LD20 SoC
+ - "socionext,uniphier-pxs3" - PXs3 SoC
+
+ Board compatibles:
+ - "socionext,uniphier-ld4-ref" - LD4 Reference Board
+ - "socionext,uniphier-pro4-ref" - Pro4 Reference Board
+ - "socionext,uniphier-pro4-ace" - Pro4 Ace Board
+ - "socionext,uniphier-pro4-sanji" - Pro4 Sanji Board
+ - "socionext,uniphier-sld8-ref" - sLD8 Reference Board
+ - "socionext,uniphier-pxs2-gentil" - PXs2 Gentil Board
+ - "socionext,uniphier-pxs2-vodka" - PXs2 Vodka Board
+ - "socionext,uniphier-ld6b-ref" - LD6b Reference Board
+ - "socionext,uniphier-ld11-ref" - LD11 Reference Board
+ - "socionext,uniphier-ld11-global" - LD11 Global Board
+ - "socionext,uniphier-ld20-ref" - LD20 Reference Board
+ - "socionext,uniphier-ld20-global" - LD20 Global Board
+ - "socionext,uniphier-pxs3-ref" - PXs3 Reference Board
+
+Example:
+
+/dts-v1/;
+
+/ {
+ compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
+
+ ...
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index cbb89bb..1fcbd65 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2041,6 +2041,7 @@ M: Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers)
T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git
S: Maintained
+F: Documentation/devicetree/bindings/arm/uniphier.txt
F: Documentation/devicetree/bindings/gpio/gpio-uniphier.txt
F: arch/arm/boot/dts/uniphier*
F: arch/arm/include/asm/hardware/cache-uniphier.h
--
2.7.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v7 6/6] arm: dts: Add power controller device node of MT2712
From: Weiyi Lu @ 2017-11-28 7:28 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Mike Turquette, Rob Herring
Cc: James Liao, Fan Chen, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-clk, srv_heupstream, Weiyi Lu
In-Reply-To: <1511854102-23195-1-git-send-email-weiyi.lu@mediatek.com>
add power controller node for MT2712
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 5703793..61dd763 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt2712-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/mt2712-power.h>
/ {
compatible = "mediatek,mt2712";
@@ -172,6 +173,21 @@
#clock-cells = <1>;
};
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt2712-scpsys", "syscon";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_VENC_SEL>,
+ <&topckgen CLK_TOP_JPGDEC_SEL>,
+ <&topckgen CLK_TOP_A1SYS_HP_SEL>,
+ <&topckgen CLK_TOP_VDEC_SEL>;
+ clock-names = "mm", "mfg", "venc",
+ "jpgdec", "audio", "vdec";
+ infracfg = <&infracfg>;
+ };
+
uart5: serial@1000f000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
--
1.9.1
^ permalink raw reply related
* [PATCH v7 5/6] arm: dts: mt2712: Add clock controller device nodes
From: Weiyi Lu @ 2017-11-28 7:28 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Mike Turquette, Rob Herring
Cc: James Liao, Fan Chen, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-clk, srv_heupstream, Weiyi Lu
In-Reply-To: <1511854102-23195-1-git-send-email-weiyi.lu@mediatek.com>
Add clock controller nodes for MT2712, include topckgen, infracfg,
pericfg, mcucfg and apmixedsys. This patch also add six oscillators that
provide clocks for MT2712.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 115 ++++++++++++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 5d4e406..5703793 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -5,6 +5,7 @@
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
+#include <dt-bindings/clock/mt2712-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -98,6 +99,48 @@
#clock-cells = <0>;
};
+ clk26m: oscillator@0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator@1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "clk32k";
+ };
+
+ clkfpc: oscillator@2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "clkfpc";
+ };
+
+ clkaud_ext_i_0: oscillator@3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <6500000>;
+ clock-output-names = "clkaud_ext_i_0";
+ };
+
+ clkaud_ext_i_1: oscillator@4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <196608000>;
+ clock-output-names = "clkaud_ext_i_1";
+ };
+
+ clkaud_ext_i_2: oscillator@5 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <180633600>;
+ clock-output-names = "clkaud_ext_i_2";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
@@ -111,6 +154,24 @@
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
};
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt2712-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt2712-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt2712-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
uart5: serial@1000f000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
@@ -121,6 +182,18 @@
status = "disabled";
};
+ apmixedsys: syscon@10209000 {
+ compatible = "mediatek,mt2712-apmixedsys", "syscon";
+ reg = <0 0x10209000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mcucfg: syscon@10220000 {
+ compatible = "mediatek,mt2712-mcucfg", "syscon";
+ reg = <0 0x10220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
sysirq: interrupt-controller@10220a80 {
compatible = "mediatek,mt2712-sysirq",
"mediatek,mt6577-sysirq";
@@ -192,5 +265,47 @@
clock-names = "baud", "bus";
status = "disabled";
};
+
+ mfgcfg: syscon@13000000 {
+ compatible = "mediatek,mt2712-mfgcfg", "syscon";
+ reg = <0 0x13000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt2712-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: syscon@15000000 {
+ compatible = "mediatek,mt2712-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ bdpsys: syscon@15010000 {
+ compatible = "mediatek,mt2712-bdpsys", "syscon";
+ reg = <0 0x15010000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: syscon@16000000 {
+ compatible = "mediatek,mt2712-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: syscon@18000000 {
+ compatible = "mediatek,mt2712-vencsys", "syscon";
+ reg = <0 0x18000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ jpgdecsys: syscon@19000000 {
+ compatible = "mediatek,mt2712-jpgdecsys", "syscon";
+ reg = <0 0x19000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
--
1.9.1
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