* Re: [PATCH v2 0/4] ARM: dts: renesas: Convert to named i2c-gpio bindings
From: Simon Horman @ 2017-12-01 8:18 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Wolfram Sang, Linus Walleij,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512046646-15253-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
On Thu, Nov 30, 2017 at 01:57:22PM +0100, Geert Uytterhoeven wrote:
> Hi Simon, Magnus,
>
> Commits 7d29f509d2cfd807 ("dt-bindings: i2c: i2c-gpio: Add support for
> named gpios") and 05c74778858d7d99 ("i2c: gpio: Add support for named
> gpios in DT") introduced named i2c-gpio DT bindings, and deprecated the
> more error-prone unnamed variant.
>
> This patch series switches all Renesas boards to the new bindings, and
> adds the missing GPIO_OPEN_DRAIN I/O flags, which were implicitly
> assumed before. The latter gets rid of messages like:
>
> gpio-208 (?): enforced open drain please flag it properly in DT/ACPI DSDT/board file
> gpio-91 (?): enforced open drain please flag it properly in DT/ACPI DSDT/board file
>
> Patch 1 was extracted from series "[PATCH/RFC 0/3] i2c: gpio: Add
> support for named gpios in DT", hence the v2. All other patches are
> new.
>
> Note that after this series is applied, the i2c-gpio buses are no longer
> detected when booting new DTBs on old (v4.14 and older) kernels, which
> should not be an issue. Booting old DTBs on new kernels is not
> affected.
>
> Thanks for applying!
Thanks, applied.
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* Re: [PATCH v3 4/5] pinctrl: mcp23s08: configure irq polarity using irq data
From: Linus Walleij @ 2017-12-01 8:38 UTC (permalink / raw)
To: Marc Zyngier
Cc: Sebastian Reichel, Phil Reid, Rob Herring, Mark Rutland,
linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <1ba1c850-dd22-fa98-66ea-fcb8527ec5ad@arm.com>
On Thu, Nov 30, 2017 at 4:50 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> I'm clearly inclined to prefer the first solution. But maybe it is time
> to invent a "generic inverter" driver that could be reusable, just like
> we have a generic irqchip?
I'm leaning towards that we should create
compatible = "irqline-inverter"; irqchip and just slap that into
drivers/of/irq.c for everyone. *Maybe* with a Kconfig
for it if people worry about the extra bytes.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH RFC 2/2] arm64: allwinner: a64: Add Brava Keller initial support
From: Philippe Ombredanne @ 2017-12-01 8:41 UTC (permalink / raw)
To: Jagan Teki
Cc: Chen-Yu Tsai, Icenowy Zheng, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Michael Trimarchi,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML,
Mark Janoff, Stuart Westerman, linux-sunxi, Jagan Teki,
Maxime Ripard
In-Reply-To: <20171201075421.33pgum4jjcvjxuju@flea.lan>
Dear Jagan,
On Fri, Dec 1, 2017 at 8:54 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Fri, Dec 01, 2017 at 12:12:14AM +0530, Jagan Teki wrote:
[]
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-brava-keller.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-brava-keller.dts
>> new file mode 100644
>> index 0000000..f5303a3
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-brava-keller.dts
>> @@ -0,0 +1,244 @@
>> +/*
>> + * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
Have you considered replacing this fine licensing boilerplate by the
new concise and cleaner SPDX ids?
Could it make sense, especially for new files, to avoid adding
boilerplate that will need to be cleaned up later?
You could get rid of these 37 lines and use this shorthand instead,
using the new conventions started by greg-kh and documented by tglx?
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +// Copyright (c) 2017 Jagan Teki <jagan@amarulasolutions.com>
Thomas has sent a first doc patch [1] set and is working on an updated
version. Jonathan also wrote a nice background article on the topic
at LWN [2].
And as a bonus, this device tree addition of yours minus this
boilerplate could save a few real trees if someone ever prints --god
forbid-- this file, so you would be making a good thing for the
planet! And consider too the energy savings from not having these
extra bytes transferred million of times and not retrieved from disks
spindles.
[1] https://marc.info/?l=linux-kernel&m=151051532322831&w=2
[2] https://lwn.net/SubscriberLink/739183/262749cbe307ddc7/
--
Cordially
Philippe Ombredanne
^ permalink raw reply
* Re: [PATCH V2 8/9] PCI: tegra: Broadcast PME_turn_Off message before link goes to L2
From: Mikko Perttunen @ 2017-12-01 8:51 UTC (permalink / raw)
To: Manikanta Maddireddy, thierry.reding, jonathanh, robh+dt,
frowand.list, bhelgaas, rjw, tglx
Cc: vidyas, kthota, linux-tegra, devicetree, linux-pci, linux-pm
In-Reply-To: <dd3cb6a5-76ec-98c2-4132-54678c2d74ce@kapsi.fi>
On 29.11.2017 14:18, Mikko Perttunen wrote:
> On 25.11.2017 21:32, Manikanta Maddireddy wrote:
>> Per PCIe r3.0, sec 5.3.3.2.1, PCIe root port shoould broadcast
>> PME_turn_Off
>> message before PCIe link goes to L2. PME_turn_Off broadcast mechanism is
>> implemented in AFI module. Each Tegra PCIe root port has its own
>> PME_turn_Off and PME_TO_Ack bitmap in AFI_PME register, program this
>> register to broadcast PME_turn_Off message.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> V2:
>> * no change in this patch
>>
>> drivers/pci/host/pci-tegra.c | 76
>> ++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 76 insertions(+)
>>
>> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
>> index bbc2807bcd4a..b380958a3deb 100644
>> --- a/drivers/pci/host/pci-tegra.c
>> +++ b/drivers/pci/host/pci-tegra.c
>> @@ -155,6 +155,8 @@
>> #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
>> #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
>>
>> +#define AFI_PCIE_PME 0xf0
>> +
>> #define AFI_PCIE_CONFIG 0x0f8
>> #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
>> #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
>> @@ -315,6 +317,7 @@
>> #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
>>
>> #define LINK_RETRAIN_TIMEOUT 100000
>> +#define PME_ACK_TIMEOUT 10000
>>
>> struct tegra_msi {
>> struct msi_controller chip;
>> @@ -1503,6 +1506,76 @@ static int tegra_pcie_put_resources(struct
>> tegra_pcie *pcie)
>> return 0;
>> }
>>
>> +static inline u32 get_pme_turnoff_bitmap(struct tegra_pcie_port *port)
>> +{
>> + struct device *dev = port->pcie->dev;
>> + struct device_node *np = dev->of_node;
>> + int ret = 0;
>> +
>> + switch (port->index) {
>> + case 0:
>> + ret = 0;
>> + case 1:
>> + ret = 8;
>> + case 2:
>> + if (of_device_is_compatible(np, "nvidia,tegra30-pcie"))
>> + ret = 16;
>> + else
>> + ret = 12;
>> + }
>> + return ret;
>> +}
>> +
>> +static inline u32 get_pme_ack_bitmap(struct tegra_pcie_port *port)
>> +{
>> + struct device *dev = port->pcie->dev;
>> + struct device_node *np = dev->of_node;
>> + int ret = 0;
>> +
>> + switch (port->index) {
>> + case 0:
>> + ret = 5;
>> + case 1:
>> + ret = 10;
>> + case 2:
>> + if (of_device_is_compatible(np, "nvidia,tegra30-pcie"))
>> + ret = 18;
>> + else
>> + ret = 14;
>> + }
>> + return ret;
>> +}
>
> From what I can tell, the port 2 bit is 12/14 on everything after
> Tegra30 as well, so I don't think this actually works?
Looks like I misread this and it is correct, sorry :)
Still the below applies.
Thanks,
Mikko
>
> I think simpler would be to add a SoC data fields 'u8
> pme_turnoff_bit[3]' and 'u8 pme_ack_bit[3]' and then set that
> to '.pme_turnoff_bit = { 0, 8, 16 }' and so on.
>
>> +
>> +static void tegra_pcie_pme_turnoff(struct tegra_pcie_port *port)
>> +{
>> + struct tegra_pcie *pcie = port->pcie;
>> + ktime_t deadline;
>> + unsigned int data;
>> +
>> + data = afi_readl(pcie, AFI_PCIE_PME);
>> + data |= (0x1 << get_pme_turnoff_bitmap(port));
>> + afi_writel(pcie, data, AFI_PCIE_PME);
>> +
>> + deadline = ktime_add_us(ktime_get(), PME_ACK_TIMEOUT);
>> + do {
>> + data = afi_readl(pcie, AFI_PCIE_PME);
>> + data &= (0x1 << get_pme_ack_bitmap(port));
>> + udelay(1);
>> + if (ktime_after(ktime_get(), deadline))
>> + break;
>> + } while (!data);
>
> Since this is a normal MMIO read, we could replace the whole loop with a
> call to readl_poll_timeout (or readl_relaxed_poll_timeout, or if we
> really must delay and not sleep, readl_poll_timeout_atomic etc.) from
> iopoll.h
>
> int err;
> u32 val;
>
> err = readl_poll_timeout(pcie->afi + AFI_PCIE_PME, val,
> val & (0x1 << pcie->soc->pme_ack_bit[port]),
> 1, PME_ACK_TIMEOUT);
> if (err)
> ...
>
>> +
>> + if (data)
>> + dev_err(pcie->dev, "PME Ack is not receieved on port: %d\n",
>> + port->index);
>> +
>
> Typo here, s/receieved/received/
>
> Cheers,
> Mikko
>
>> + usleep_range(10000, 11000);
>> +
>> + data = afi_readl(pcie, AFI_PCIE_PME);
>> + data &= ~(0x1 << get_pme_turnoff_bitmap(port));
>> + afi_writel(pcie, data, AFI_PCIE_PME);
>> +}
>> +
>> static int tegra_msi_alloc(struct tegra_msi *chip)
>> {
>> int msi;
>> @@ -2828,6 +2901,7 @@ static int tegra_pcie_remove(struct
>> platform_device *pdev)
>> {
>> struct tegra_pcie *pcie = platform_get_drvdata(pdev);
>> struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
>> + struct tegra_pcie_port *port, *tmp;
>>
>> if (IS_ENABLED(CONFIG_DEBUG_FS))
>> tegra_pcie_debugfs_exit(pcie);
>> @@ -2835,6 +2909,8 @@ static int tegra_pcie_remove(struct
>> platform_device *pdev)
>> pci_remove_root_bus(host->bus);
>> if (IS_ENABLED(CONFIG_PCI_MSI))
>> tegra_pcie_disable_msi(pcie);
>> + list_for_each_entry_safe(port, tmp, &pcie->ports, list)
>> + tegra_pcie_pme_turnoff(port);
>> tegra_pcie_disable_ports(pcie);
>> tegra_pcie_free_resources(pcie);
>> tegra_pcie_disable_controller(pcie);
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo@vger.kernel.org
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* [PATCH 1/2] dt-bindings: regulator: Add Spreadtrum SC27xx regulator documentation
From: Erick Chen @ 2017-12-01 8:58 UTC (permalink / raw)
To: broonie-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, lgirdwood-Re5JQEeQqe8AvxtiuMwx3w
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
baolin.wang-QSEj5FYQhm4dnm+yROfE0A,
baolin.wang-lxIno14LUO0EEoCn2XhGlw,
erick.chen-lxIno14LUO0EEoCn2XhGlw
This patch adds support for the Spreadtrum SC2731
voltage regulator device.
Signed-off-by: Erick Chen <erick.chen-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
---
.../bindings/regulator/sprd,sc2731-regulator.txt | 45 ++++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.txt
diff --git a/Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.txt b/Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.txt
new file mode 100644
index 0000000..619385e
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.txt
@@ -0,0 +1,45 @@
+Spreadtrum SC2731 Voltage regulators
+
+The SC2731 integrates low-voltage and low quiescent current DCDC/LDO.
+14 LDO and 3 DCDCs are designed for external use. All DCDCs/LDOs have
+their own bypass (power-down) control signals. External tantalum or MLCC
+ceramic capacitors are recommended to use with these LDOs.
+
+Required properties:
+ - compatible: should be "sprd,sc2731-regulator".
+ - reg: address offset of regulator registers.
+ - regulators: List of regulators provided by this controller. It is named
+ according to its regulator type, BUCK_<name> and LDO_<name>. The definition
+ for each of these nodes is defined using the standard binding for regulators
+ at Documentation/devicetree/bindings/regulator/regulator.txt.
+
+The valid names for regulators are::
+BUCK:
+ BUCK_CPU0, BUCK_CPU1, BUCK_RF
+LDO:
+ LDO_CAMA0, LDO_CAMA1, LDO_CAMMOT, LDO_VLDO, LDO_EMMCCORE, LDO_SDCORE, LDO_SDIO,
+ LDO_WIFIPA, LDO_USB33, LDO_CAMD0, LDO_CAMD1, LDO_CON, LDO_CAMIO, LDO_SRAM
+
+Example:
+ power-controller@810 {
+ compatible = "sprd,sc2731-regulator";
+ reg = <0x810>;
+
+ regulators {
+ vddarm0: BUCK_CPU0 {
+ regulator-name = "vddarm0";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1996875>;
+ regulator-ramp-delay = <25000>;
+ regulator-always-on;
+ };
+
+ vddcama0: LDO_CAMA0 {
+ regulator-name = "vddcama0";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3750000>;
+ regulator-enable-ramp-delay = <100>;
+ };
+ ...
+ };
+ };
--
1.7.9.5
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* [PATCH 2/2] regulator: sc2731: Add regulator driver to support Spreadtrum SC2731 PMIC
From: Erick Chen @ 2017-12-01 8:58 UTC (permalink / raw)
To: broonie, robh+dt, mark.rutland, lgirdwood
Cc: linux-kernel, devicetree, baolin.wang, baolin.wang, erick.chen
In-Reply-To: <f6d8ff765f4864e5b6ace1f022202d8793a7becf.1512118703.git.erick.chen@spreadtrum.com>
Add regulator driver for Spreadtrum SC2731 device.
It has 17 general purpose LDOs, BUCKs generator and
digital output to control regulators.
Signed-off-by: Erick Chen <erick.chen@spreadtrum.com>
Reviewed-by: Baolin Wang <baolin.wang@spreadtrum.com>
---
drivers/regulator/Kconfig | 7 +
drivers/regulator/Makefile | 1 +
drivers/regulator/sc2731-regulator.c | 276 ++++++++++++++++++++++++++++++++++
3 files changed, 284 insertions(+)
create mode 100644 drivers/regulator/sc2731-regulator.c
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 96cd55f..b27417c 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -744,6 +744,13 @@ config REGULATOR_S5M8767
via I2C bus. S5M8767A have 9 Bucks and 28 LDOs output and
supports DVS mode with 8bits of output voltage control.
+config REGULATOR_SC2731
+ tristate "Spreadtrum SC2731 power regulator driver"
+ depends on MFD_SC27XX_PMIC || COMPILE_TEST
+ help
+ This driver provides support for the voltage regulators on the
+ SC2731 PMIC.
+
config REGULATOR_SKY81452
tristate "Skyworks Solutions SKY81452 voltage regulator"
depends on MFD_SKY81452
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 80ffc57..19fea09 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_REGULATOR_RT5033) += rt5033-regulator.o
obj-$(CONFIG_REGULATOR_S2MPA01) += s2mpa01.o
obj-$(CONFIG_REGULATOR_S2MPS11) += s2mps11.o
obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
+obj-$(CONFIG_REGULATOR_SC2731) += sc2731-regulator.o
obj-$(CONFIG_REGULATOR_SKY81452) += sky81452-regulator.o
obj-$(CONFIG_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o
obj-$(CONFIG_REGULATOR_STW481X_VMMC) += stw481x-vmmc.o
diff --git a/drivers/regulator/sc2731-regulator.c b/drivers/regulator/sc2731-regulator.c
new file mode 100644
index 0000000..e56448a
--- /dev/null
+++ b/drivers/regulator/sc2731-regulator.c
@@ -0,0 +1,276 @@
+/*
+ * Copyright (C) 2017 Spreadtrum Communications Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/of_regulator.h>
+
+/*
+ * SC2731 regulator lock register
+ */
+#define SC2731_PWR_WR_PROT_VALUE 0xf0c
+#define SC2731_WR_UNLOCK 0x6e7f
+
+/*
+ * SC2731 enable register
+ */
+#define SC2731_POWER_PD_SW 0xc28
+#define SC2731_LDO_CAMA0_PD 0xcfc
+#define SC2731_LDO_CAMA1_PD 0xd04
+#define SC2731_LDO_CAMMOT_PD 0xd0c
+#define SC2731_LDO_VLDO_PD 0xd6c
+#define SC2731_LDO_EMMCCORE_PD 0xd2c
+#define SC2731_LDO_SDCORE_PD 0xd74
+#define SC2731_LDO_SDIO_PD 0xd70
+#define SC2731_LDO_WIFIPA_PD 0xd4c
+#define SC2731_LDO_USB33_PD 0xd5c
+#define SC2731_LDO_CAMD0_PD 0xd7c
+#define SC2731_LDO_CAMD1_PD 0xd84
+#define SC2731_LDO_CON_PD 0xd8c
+#define SC2731_LDO_CAMIO_PD 0xd94
+#define SC2731_LDO_SRAM_PD 0xd78
+
+/*
+ * SC2731 enable mask
+ */
+#define SC2731_DCDC_CPU0_PD_MASK BIT(4)
+#define SC2731_DCDC_CPU1_PD_MASK BIT(3)
+#define SC2731_DCDC_RF_PD_MASK BIT(11)
+#define SC2731_LDO_CAMA0_PD_MASK BIT(0)
+#define SC2731_LDO_CAMA1_PD_MASK BIT(0)
+#define SC2731_LDO_CAMMOT_PD_MASK BIT(0)
+#define SC2731_LDO_VLDO_PD_MASK BIT(0)
+#define SC2731_LDO_EMMCCORE_PD_MASK BIT(0)
+#define SC2731_LDO_SDCORE_PD_MASK BIT(0)
+#define SC2731_LDO_SDIO_PD_MASK BIT(0)
+#define SC2731_LDO_WIFIPA_PD_MASK BIT(0)
+#define SC2731_LDO_USB33_PD_MASK BIT(0)
+#define SC2731_LDO_CAMD0_PD_MASK BIT(0)
+#define SC2731_LDO_CAMD1_PD_MASK BIT(0)
+#define SC2731_LDO_CON_PD_MASK BIT(0)
+#define SC2731_LDO_CAMIO_PD_MASK BIT(0)
+#define SC2731_LDO_SRAM_PD_MASK BIT(0)
+
+/*
+ * SC2731 vsel register
+ */
+#define SC2731_DCDC_CPU0_VOL 0xc54
+#define SC2731_DCDC_CPU1_VOL 0xc64
+#define SC2731_DCDC_RF_VOL 0xcb8
+#define SC2731_LDO_CAMA0_VOL 0xd00
+#define SC2731_LDO_CAMA1_VOL 0xd08
+#define SC2731_LDO_CAMMOT_VOL 0xd10
+#define SC2731_LDO_VLDO_VOL 0xd28
+#define SC2731_LDO_EMMCCORE_VOL 0xd30
+#define SC2731_LDO_SDCORE_VOL 0xd38
+#define SC2731_LDO_SDIO_VOL 0xd40
+#define SC2731_LDO_WIFIPA_VOL 0xd50
+#define SC2731_LDO_USB33_VOL 0xd60
+#define SC2731_LDO_CAMD0_VOL 0xd80
+#define SC2731_LDO_CAMD1_VOL 0xd88
+#define SC2731_LDO_CON_VOL 0xd90
+#define SC2731_LDO_CAMIO_VOL 0xd98
+#define SC2731_LDO_SRAM_VOL 0xdB0
+
+/*
+ * SC2731 vsel register mask
+ */
+#define SC2731_DCDC_CPU0_VOL_MASK GENMASK(8, 0)
+#define SC2731_DCDC_CPU1_VOL_MASK GENMASK(8, 0)
+#define SC2731_DCDC_RF_VOL_MASK GENMASK(8, 0)
+#define SC2731_LDO_CAMA0_VOL_MASK GENMASK(7, 0)
+#define SC2731_LDO_CAMA1_VOL_MASK GENMASK(7, 0)
+#define SC2731_LDO_CAMMOT_VOL_MASK GENMASK(7, 0)
+#define SC2731_LDO_VLDO_VOL_MASK GENMASK(7, 0)
+#define SC2731_LDO_EMMCCORE_VOL_MASK GENMASK(7, 0)
+#define SC2731_LDO_SDCORE_VOL_MASK GENMASK(7, 0)
+#define SC2731_LDO_SDIO_VOL_MASK GENMASK(7, 0)
+#define SC2731_LDO_WIFIPA_VOL_MASK GENMASK(7, 0)
+#define SC2731_LDO_USB33_VOL_MASK GENMASK(7, 0)
+#define SC2731_LDO_CAMD0_VOL_MASK GENMASK(6, 0)
+#define SC2731_LDO_CAMD1_VOL_MASK GENMASK(6, 0)
+#define SC2731_LDO_CON_VOL_MASK GENMASK(6, 0)
+#define SC2731_LDO_CAMIO_VOL_MASK GENMASK(6, 0)
+#define SC2731_LDO_SRAM_VOL_MASK GENMASK(6, 0)
+
+enum sc2731_regulator_id {
+ SC2731_BUCK_CPU0,
+ SC2731_BUCK_CPU1,
+ SC2731_BUCK_RF,
+ SC2731_LDO_CAMA0,
+ SC2731_LDO_CAMA1,
+ SC2731_LDO_CAMMOT,
+ SC2731_LDO_VLDO,
+ SC2731_LDO_EMMCCORE,
+ SC2731_LDO_SDCORE,
+ SC2731_LDO_SDIO,
+ SC2731_LDO_WIFIPA,
+ SC2731_LDO_USB33,
+ SC2731_LDO_CAMD0,
+ SC2731_LDO_CAMD1,
+ SC2731_LDO_CON,
+ SC2731_LDO_CAMIO,
+ SC2731_LDO_SRAM,
+};
+
+static const struct regulator_ops sc2731_regu_linear_ops = {
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .list_voltage = regulator_list_voltage_linear,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+};
+
+#define SC2731_REGU_LINEAR(_id, en_reg, en_mask, vreg, vmask, \
+ vstep, vmin, vmax) { \
+ .name = #_id, \
+ .of_match = of_match_ptr(#_id), \
+ .ops = &sc2731_regu_linear_ops, \
+ .regulators_node = of_match_ptr("regulators"), \
+ .type = REGULATOR_VOLTAGE, \
+ .id = SC2731_##_id, \
+ .owner = THIS_MODULE, \
+ .min_uV = vmin, \
+ .n_voltages = ((vmax) - (vmin)) / (vstep) + 1, \
+ .uV_step = vstep, \
+ .enable_is_inverted = true, \
+ .enable_val = 0, \
+ .enable_reg = en_reg, \
+ .enable_mask = en_mask, \
+ .vsel_reg = vreg, \
+ .vsel_mask = vmask, \
+}
+
+static struct regulator_desc regulators[] = {
+ SC2731_REGU_LINEAR(BUCK_CPU0, SC2731_POWER_PD_SW,
+ SC2731_DCDC_CPU0_PD_MASK, SC2731_DCDC_CPU0_VOL,
+ SC2731_DCDC_CPU0_VOL_MASK, 3125, 400000, 1996875),
+ SC2731_REGU_LINEAR(BUCK_CPU1, SC2731_POWER_PD_SW,
+ SC2731_DCDC_CPU1_PD_MASK, SC2731_DCDC_CPU1_VOL,
+ SC2731_DCDC_CPU1_VOL_MASK, 3125, 400000, 1996875),
+ SC2731_REGU_LINEAR(BUCK_RF, SC2731_POWER_PD_SW, SC2731_DCDC_RF_PD_MASK,
+ SC2731_DCDC_RF_VOL, SC2731_DCDC_RF_VOL_MASK,
+ 3125, 600000, 2196875),
+ SC2731_REGU_LINEAR(LDO_CAMA0, SC2731_LDO_CAMA0_PD,
+ SC2731_LDO_CAMA0_PD_MASK, SC2731_LDO_CAMA0_VOL,
+ SC2731_LDO_CAMA0_VOL_MASK, 10000, 1200000, 3750000),
+ SC2731_REGU_LINEAR(LDO_CAMA1, SC2731_LDO_CAMA1_PD,
+ SC2731_LDO_CAMA1_PD_MASK, SC2731_LDO_CAMA1_VOL,
+ SC2731_LDO_CAMA1_VOL_MASK, 10000, 1200000, 3750000),
+ SC2731_REGU_LINEAR(LDO_CAMMOT, SC2731_LDO_CAMMOT_PD,
+ SC2731_LDO_CAMMOT_PD_MASK, SC2731_LDO_CAMMOT_VOL,
+ SC2731_LDO_CAMMOT_VOL_MASK, 10000, 1200000, 3750000),
+ SC2731_REGU_LINEAR(LDO_VLDO, SC2731_LDO_VLDO_PD,
+ SC2731_LDO_VLDO_PD_MASK, SC2731_LDO_VLDO_VOL,
+ SC2731_LDO_VLDO_VOL_MASK, 10000, 1200000, 3750000),
+ SC2731_REGU_LINEAR(LDO_EMMCCORE, SC2731_LDO_EMMCCORE_PD,
+ SC2731_LDO_EMMCCORE_PD_MASK, SC2731_LDO_EMMCCORE_VOL,
+ SC2731_LDO_EMMCCORE_VOL_MASK, 10000, 1200000,
+ 3750000),
+ SC2731_REGU_LINEAR(LDO_SDCORE, SC2731_LDO_SDCORE_PD,
+ SC2731_LDO_SDCORE_PD_MASK, SC2731_LDO_SDCORE_VOL,
+ SC2731_LDO_SDCORE_VOL_MASK, 10000, 1200000, 3750000),
+ SC2731_REGU_LINEAR(LDO_SDIO, SC2731_LDO_SDIO_PD,
+ SC2731_LDO_SDIO_PD_MASK, SC2731_LDO_SDIO_VOL,
+ SC2731_LDO_SDIO_VOL_MASK, 10000, 1200000, 3750000),
+ SC2731_REGU_LINEAR(LDO_WIFIPA, SC2731_LDO_WIFIPA_PD,
+ SC2731_LDO_WIFIPA_PD_MASK, SC2731_LDO_WIFIPA_VOL,
+ SC2731_LDO_WIFIPA_VOL_MASK, 10000, 1200000, 3750000),
+ SC2731_REGU_LINEAR(LDO_USB33, SC2731_LDO_USB33_PD,
+ SC2731_LDO_USB33_PD_MASK, SC2731_LDO_USB33_VOL,
+ SC2731_LDO_USB33_VOL_MASK, 10000, 1200000, 3750000),
+ SC2731_REGU_LINEAR(LDO_CAMD0, SC2731_LDO_CAMD0_PD,
+ SC2731_LDO_CAMD0_PD_MASK, SC2731_LDO_CAMD0_VOL,
+ SC2731_LDO_CAMD0_VOL_MASK, 6250, 1000000, 1793750),
+ SC2731_REGU_LINEAR(LDO_CAMD1, SC2731_LDO_CAMD1_PD,
+ SC2731_LDO_CAMD1_PD_MASK, SC2731_LDO_CAMD1_VOL,
+ SC2731_LDO_CAMD1_VOL_MASK, 6250, 1000000, 1793750),
+ SC2731_REGU_LINEAR(LDO_CON, SC2731_LDO_CON_PD,
+ SC2731_LDO_CON_PD_MASK, SC2731_LDO_CON_VOL,
+ SC2731_LDO_CON_VOL_MASK, 6250, 1000000, 1793750),
+ SC2731_REGU_LINEAR(LDO_CAMIO, SC2731_LDO_CAMIO_PD,
+ SC2731_LDO_CAMIO_PD_MASK, SC2731_LDO_CAMIO_VOL,
+ SC2731_LDO_CAMIO_VOL_MASK, 6250, 1000000, 1793750),
+ SC2731_REGU_LINEAR(LDO_SRAM, SC2731_LDO_SRAM_PD,
+ SC2731_LDO_SRAM_PD_MASK, SC2731_LDO_SRAM_VOL,
+ SC2731_LDO_SRAM_VOL_MASK, 6250, 1000000, 1793750),
+};
+
+static int sc2731_regulator_unlock(struct regmap *regmap)
+{
+ return regmap_write(regmap, SC2731_PWR_WR_PROT_VALUE,
+ SC2731_WR_UNLOCK);
+}
+
+static int sc2731_regulator_probe(struct platform_device *pdev)
+{
+ int i, ret;
+ struct regmap *regmap;
+ struct regulator_config config = { };
+ struct regulator_dev *rdev;
+
+ regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!regmap) {
+ dev_err(&pdev->dev, "failed to get regmap.\n");
+ return -ENODEV;
+ }
+
+ ret = sc2731_regulator_unlock(regmap);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to release regulator lock\n");
+ return ret;
+ }
+
+ config.dev = &pdev->dev;
+ config.regmap = regmap;
+
+ for (i = 0; i < ARRAY_SIZE(regulators); i++) {
+ rdev = devm_regulator_register(&pdev->dev, ®ulators[i],
+ &config);
+ if (IS_ERR(rdev)) {
+ dev_err(&pdev->dev, "failed to register regulator %s\n",
+ regulators[i].name);
+ return PTR_ERR(rdev);
+ }
+ }
+
+ return 0;
+}
+
+static const struct of_device_id sc2731_regulator_of_match[] = {
+ {.compatible = "sprd,sc2731-regulator",},
+ {}
+};
+MODULE_DEVICE_TABLE(of, sc2731_regulator_of_match);
+
+static struct platform_driver sc2731_regulator_driver = {
+ .driver = {
+ .name = "sc2731-regulator",
+ .of_match_table = sc2731_regulator_of_match,
+ },
+ .probe = sc2731_regulator_probe,
+};
+
+static int __init sc2731_regulator_init(void)
+{
+ return platform_driver_register(&sc2731_regulator_driver);
+}
+
+static void __exit sc2731_regulator_exit(void)
+{
+ platform_driver_unregister(&sc2731_regulator_driver);
+}
+
+subsys_initcall(sc2731_regulator_init);
+module_exit(sc2731_regulator_exit);
+
+MODULE_AUTHOR("Chen Junhui <erick.chen@spreadtrum.com>");
+MODULE_DESCRIPTION("Spreadtrum SC2731 regulator driver");
+MODULE_LICENSE("GPL v2");
--
1.7.9.5
^ permalink raw reply related
* [PATCH v5 2/6] dt-bindings: Add vendor prefix for Solomon Goldentek Display Corporation
From: Neil Armstrong @ 2017-12-01 9:03 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam
Cc: devicetree, linux-kernel, linux-arm-kernel, Neil Armstrong
In-Reply-To: <1512119024-521-1-git-send-email-narmstrong@baylibre.com>
Solomon Goldentek Display Corporation is a Taiwanese LCD/LCM manufacturer.
Company Site: http://www.goldentek.com.tw
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 0994bdd..b0d3bef 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -305,6 +305,7 @@ seagate Seagate Technology PLC
semtech Semtech Corporation
sensirion Sensirion AG
sff Small Form Factor Committee
+sgd Solomon Goldentek Display Corporation
sgx SGX Sensortech
sharp Sharp Corporation
shimafuji Shimafuji Electric, Inc.
--
2.7.4
^ permalink raw reply related
* [PATCH v5 3/6] dt-bindings: display: Add bindings for SGD GKTW70SDAE4SE Panel
From: Neil Armstrong @ 2017-12-01 9:03 UTC (permalink / raw)
To: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
fabio.estevam-3arQi8VN3Tc
Cc: Neil Armstrong, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512119024-521-1-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
The GKTW70SDAE4SE is an LVDS display panel.
Their bindings are modelled on the the LVDS panel bindings.
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
.../bindings/display/panel/sgd,gktw70sdae4se.txt | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt
diff --git a/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt b/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt
new file mode 100644
index 0000000..d06644b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt
@@ -0,0 +1,41 @@
+Solomon Goldentek Display GKTW70SDAE4SE LVDS Display Panel
+==========================================================
+
+The GKTW70SDAE4SE is a 7" WVGA TFT-LCD display panel.
+
+These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt
+with the following device-specific properties.
+
+Required properties:
+
+- compatible: Shall contain "sgd,gktw70sdae4se" and "panel-lvds", in that order.
+
+Example
+-------
+
+panel {
+ compatible = "sgd,gktw70sdae4se", "panel-lvds";
+
+ width-mm = <153>;
+ height-mm = <86>;
+
+ data-mapping = "jeida-18";
+
+ panel-timing {
+ clock-frequency = <32000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <39>;
+ hfront-porch = <39>;
+ vback-porch = <29>;
+ vfront-porch = <13>;
+ hsync-len = <47>;
+ vsync-len = <2>;
+ };
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds_encoder>;
+ };
+ };
+};
--
2.7.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 1/2] arm64: dts: a64-olinuxino: Enable RTL8723BS WiFi
From: Jagan Teki @ 2017-12-01 9:06 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Icenowy Zheng, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Michael Trimarchi,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Jagan Teki
Enable RTL8723BS WiFi chip on a64-olinuxino board:
- WiFi SDIO interface is connected to MMC1
- WiFi REG_ON pin connected to gpio PL2: attach to mmc-pwrseq
- WiFi HOST_WAKE pin connected to gpio PL3
To make rtl8723bs chip to work build it as module to and run
CONFIG_RTL8723BS=m
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
.../boot/dts/allwinner/sun50i-a64-olinuxino.dts | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
index 338e7861..8807664 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
@@ -57,6 +57,11 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+ };
};
&mmc0 {
@@ -70,6 +75,24 @@
status = "okay";
};
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <®_aldo2>;
+ vqmmc-supply = <®_dldo4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8723bs: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
+ interrupt-names = "host-wake";
+ };
+};
+
&r_rsb {
status = "okay";
--
2.7.4
^ permalink raw reply related
* [PATCH 2/2] arm64: allwinner: a64-sopine: Use dcdc1 regulator instead of vcc3v3
From: Jagan Teki @ 2017-12-01 9:06 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Icenowy Zheng, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Michael Trimarchi,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Jagan Teki
In-Reply-To: <1512119165-15290-1-git-send-email-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Since current tree support AXP803 regulators,
replace fixed regulator vcc3v3 with AXP803 dcdc1 regulator.
Tested mmc0 on sopine baseboard.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 2 +-
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi | 11 +----------
2 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
index a053a6a..abe179d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -96,7 +96,7 @@
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
- vmmc-supply = <®_vcc3v3>;
+ vmmc-supply = <®_dcdc1>;
vqmmc-supply = <®_vcc1v8>;
bus-width = <8>;
non-removable;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
index a5da18a..43418bd 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
@@ -45,19 +45,10 @@
#include "sun50i-a64.dtsi"
-/ {
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
- vmmc-supply = <®_vcc3v3>;
+ vmmc-supply = <®_dcdc1>;
non-removable;
disable-wp;
bus-width = <4>;
--
2.7.4
^ permalink raw reply related
* Re: [PATCH 1/3] dt-bindings: net: Add DT bindings for Socionext Netsec
From: Ard Biesheuvel @ 2017-12-01 9:12 UTC (permalink / raw)
To: Jassi Brar
Cc: <netdev@vger.kernel.org>, devicetree@vger.kernel.org,
David S. Miller, Arnd Bergmann, Rob Herring, Mark Rutland,
Jassi Brar
In-Reply-To: <1512058351-15851-1-git-send-email-jassisinghbrar@gmail.com>
Hi Jassi,
On 30 November 2017 at 16:12, <jassisinghbrar@gmail.com> wrote:
> From: Jassi Brar <jassisinghbrar@gmail.com>
>
> This patch adds documentation for Device-Tree bindings for the
> Socionext NetSec Controller driver.
>
> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
No need to keep my signoff here: if you are posting the patch, your
signoff should come last. (Authorship is no factor here, only the path
taken by the patch from the author/copyright holder to the sender of
the email)
> ---
> .../devicetree/bindings/net/socionext-netsec.txt | 43 ++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/socionext-netsec.txt
>
> diff --git a/Documentation/devicetree/bindings/net/socionext-netsec.txt b/Documentation/devicetree/bindings/net/socionext-netsec.txt
> new file mode 100644
> index 0000000..4695969
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/socionext-netsec.txt
> @@ -0,0 +1,43 @@
> +* Socionext NetSec Ethernet Controller IP
> +
> +Required properties:
> +- compatible: Should be "socionext,synquacer-netsec"
> +- reg: Address and length of the control register area, followed by the
> + address and length of the EEPROM holding the MAC address and
> + microengine firmware
> +- interrupts: Should contain ethernet controller interrupt
> +- clocks: phandle to the PHY reference clock, and any other clocks to be
> + switched by runtime_pm
> +- clock-names: Required only if more than a single clock is listed in 'clocks'.
> + The PHY reference clock must be named 'phy_refclk'
> +- phy-mode: See ethernet.txt file in the same directory
> +- phy-handle: phandle to select child phy
> +
We should add the following property here:
- dma-coherent: Boolean property, must only be present if memory
accesses performed by the device are cache coherent
(I only added support for this in our platform earlier this week)
> +Optional properties: (See ethernet.txt file in the same directory)
> +- local-mac-address
> +- mac-address
> +- max-speed
> +- max-frame-size
> +
> +Required properties for the child phy:
> +- reg: phy address
> +
> +Example:
> + eth0: netsec@522D0000 {
> + compatible = "socionext,synquacer-netsec";
> + reg = <0 0x522D0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>;
> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_netsec>;
> + phy-mode = "rgmii";
> + max-speed = <1000>;
> + max-frame-size = <9000>;
> + phy-handle = <ðphy0>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> + };
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH 2/2] regulator: sc2731: Add regulator driver to support Spreadtrum SC2731 PMIC
From: Philippe Ombredanne @ 2017-12-01 9:13 UTC (permalink / raw)
To: Erick Chen
Cc: Mark, Rob Herring, Mark Rutland, lgirdwood, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
baolin.wang, baolin.wang
In-Reply-To: <75a6a48f603a25d744ef46287e036975b0203608.1512118703.git.erick.chen@spreadtrum.com>
Erik,
On Fri, Dec 1, 2017 at 9:58 AM, Erick Chen <erick.chen@spreadtrum.com> wrote:
> Add regulator driver for Spreadtrum SC2731 device.
> It has 17 general purpose LDOs, BUCKs generator and
> digital output to control regulators.
>
> Signed-off-by: Erick Chen <erick.chen@spreadtrum.com>
> Reviewed-by: Baolin Wang <baolin.wang@spreadtrum.com>
> ---
> drivers/regulator/Kconfig | 7 +
> drivers/regulator/Makefile | 1 +
> drivers/regulator/sc2731-regulator.c | 276 ++++++++++++++++++++++++++++++++++
> 3 files changed, 284 insertions(+)
> create mode 100644 drivers/regulator/sc2731-regulator.c
>
> diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
> index 96cd55f..b27417c 100644
> --- a/drivers/regulator/Kconfig
> +++ b/drivers/regulator/Kconfig
> @@ -744,6 +744,13 @@ config REGULATOR_S5M8767
> via I2C bus. S5M8767A have 9 Bucks and 28 LDOs output and
> supports DVS mode with 8bits of output voltage control.
>
> +config REGULATOR_SC2731
> + tristate "Spreadtrum SC2731 power regulator driver"
> + depends on MFD_SC27XX_PMIC || COMPILE_TEST
> + help
> + This driver provides support for the voltage regulators on the
> + SC2731 PMIC.
> +
> config REGULATOR_SKY81452
> tristate "Skyworks Solutions SKY81452 voltage regulator"
> depends on MFD_SKY81452
> diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
> index 80ffc57..19fea09 100644
> --- a/drivers/regulator/Makefile
> +++ b/drivers/regulator/Makefile
> @@ -95,6 +95,7 @@ obj-$(CONFIG_REGULATOR_RT5033) += rt5033-regulator.o
> obj-$(CONFIG_REGULATOR_S2MPA01) += s2mpa01.o
> obj-$(CONFIG_REGULATOR_S2MPS11) += s2mps11.o
> obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
> +obj-$(CONFIG_REGULATOR_SC2731) += sc2731-regulator.o
> obj-$(CONFIG_REGULATOR_SKY81452) += sky81452-regulator.o
> obj-$(CONFIG_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o
> obj-$(CONFIG_REGULATOR_STW481X_VMMC) += stw481x-vmmc.o
> diff --git a/drivers/regulator/sc2731-regulator.c b/drivers/regulator/sc2731-regulator.c
> new file mode 100644
> index 0000000..e56448a
> --- /dev/null
> +++ b/drivers/regulator/sc2731-regulator.c
> @@ -0,0 +1,276 @@
> +/*
> + * Copyright (C) 2017 Spreadtrum Communications Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
I think that per Linus, and Thomas doc patches for SPDX ids this
should be instead either:
> +// SPDX-License-Identifier: GPL-2.0
> + // Copyright (c) 2017 Spreadtrum Communications Inc.
or at least this with the id on the first and the // comment style
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 Spreadtrum Communications Inc.
> + *
> + */
--
Cordially
Philippe Ombredanne
^ permalink raw reply
* Re: [PATCH 3/3] MAINTAINERS: Add entry for Socionext ethernet driver
From: Ard Biesheuvel @ 2017-12-01 9:14 UTC (permalink / raw)
To: Jassi Brar
Cc: <netdev@vger.kernel.org>, devicetree@vger.kernel.org,
David S. Miller, Arnd Bergmann, Rob Herring, Mark Rutland,
Jassi Brar
In-Reply-To: <1512058416-15968-1-git-send-email-jassisinghbrar@gmail.com>
On 30 November 2017 at 16:13, <jassisinghbrar@gmail.com> wrote:
> From: Jassi Brar <jaswinder.singh@linaro.org>
>
> Add entry for the Socionext Netsec controller driver and DT bindings.
>
> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
(with Joe's comment addressed)
> ---
> MAINTAINERS | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index aa71ab52f..aed9d32 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -12617,6 +12617,14 @@ F: drivers/md/raid*
> F: include/linux/raid/
> F: include/uapi/linux/raid/
>
> +SOCIONEXT (SNI) NETSEC NETWORK DRIVER
> +M: Jassi Brar <jaswinder.singh@linaro.org>
> +L: netdev@vger.kernel.org
> +S: Supported
> +S: Maintained
> +F: drivers/net/ethernet/socionext/netsec.c
> +F: Documentation/devicetree/bindings/net/socionext-netsec.txt
> +
> SONIC NETWORK DRIVER
> M: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> L: netdev@vger.kernel.org
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH V3 0/7] Add loadable kernel module and power management support
From: Manikanta Maddireddy @ 2017-12-01 9:20 UTC (permalink / raw)
To: cyndis-/1wQRMveznE, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, lorenzo.pieralisi-5wv7dgnIgG8
Cc: jonathanh-DDmLM1+adcrQT0dZR+AlfA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, rjw-LthD3rsA81gm4RdzfppkhA,
tglx-hfZtesqFncYOwBW4kG4KsQ, vidyas-DDmLM1+adcrQT0dZR+AlfA,
kthota-DDmLM1+adcrQT0dZR+AlfA, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA,
Manikanta Maddireddy
This series of patches add loadable kernel module and power management
support to Tegra PCIe host controller driver.
These patches are tested on Jetson TK1, TX1 and TX2 platforms, following
are the verification details.
- Multiple module insert & remove
- PCIe device functionality after module insert
- Free clock, resets, regulators, powergate, iomem and interrupt
resources after module remove
- PCIe device functionality after resume from RAM
Tegra PCIe host controller driver is using ioremap_page_range() which is
not exported. This is switched with devm_ioremap() in the series
'https://patchwork.ozlabs.org/project/linux-tegra/list/?series=9907'.
V2: PM QoS fix is dropped in V2 from this series because the fix is
incorporated in latest 'commit 0759e80b84e3 ("PM / QoS: Fix device resume
latency framework")'. Update commit message of few patches in V2.
V3: Patches to export irq_set_msi_desc() and tegra_cpuidle_pcie_irqs_in_use()
are dropped based on review comments. These symbols will be addressed in
next series. Remove PCI_REASSIGN_ALL_BUS flag for Tegra PCIe and took care
of few other review comments.
Manikanta Maddireddy (7):
of: Export of_pci_range_to_resource()
PCI: Export pci_find_host_bridge()
PCI: tegra: Remove PCI_REASSIGN_ALL_BUS flag for Tegra PCIe
PCI: tegra: Free resources on probe failure
PCI: tegra: Add loadable kernel module support
PCI: tegra: Broadcast PME_Turn_Off message before link goes to L2
PCI: tegra: Add power management support
drivers/of/address.c | 1 +
drivers/pci/host-bridge.c | 1 +
drivers/pci/host/Kconfig | 2 +-
drivers/pci/host/pci-tegra.c | 331 +++++++++++++++++++++++++++++++++----------
4 files changed, 257 insertions(+), 78 deletions(-)
--
2.1.4
^ permalink raw reply
* [PATCH V3 1/7] of: Export of_pci_range_to_resource()
From: Manikanta Maddireddy @ 2017-12-01 9:20 UTC (permalink / raw)
To: cyndis, thierry.reding, bhelgaas, lorenzo.pieralisi
Cc: jonathanh, robh+dt, frowand.list, rjw, tglx, vidyas, kthota,
linux-tegra, devicetree, linux-pci, linux-pm,
Manikanta Maddireddy
In-Reply-To: <1512120007-28088-1-git-send-email-mmaddireddy@nvidia.com>
Tegra PCIe host driver parses of_pci_range from device tree and converts
to resource. Export of_pci_range_to_resource() to allow Tegra PCIe host
driver to be compiled as loadable kernel module.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
---
V2:
* commit message update
V3:
* no change in this patch
drivers/of/address.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index fa6cabfc3cb9..8d9b93f8701a 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -361,6 +361,7 @@ int of_pci_range_to_resource(struct of_pci_range *range,
res->end = (resource_size_t)OF_BAD_ADDR;
return err;
}
+EXPORT_SYMBOL(of_pci_range_to_resource);
#endif /* CONFIG_PCI */
/*
--
2.1.4
^ permalink raw reply related
* [PATCH V3 2/7] PCI: Export pci_find_host_bridge()
From: Manikanta Maddireddy @ 2017-12-01 9:20 UTC (permalink / raw)
To: cyndis-/1wQRMveznE, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, lorenzo.pieralisi-5wv7dgnIgG8
Cc: jonathanh-DDmLM1+adcrQT0dZR+AlfA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, rjw-LthD3rsA81gm4RdzfppkhA,
tglx-hfZtesqFncYOwBW4kG4KsQ, vidyas-DDmLM1+adcrQT0dZR+AlfA,
kthota-DDmLM1+adcrQT0dZR+AlfA, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA,
Manikanta Maddireddy
In-Reply-To: <1512120007-28088-1-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
PCI subsystem pass pci_bus pointer to pci_ops callback functions, Tegra
host driver use pci_find_host_bridge() to get pci_host_bridge from pci_bus.
Export pci_find_host_bridge() to allow Tegra PCIe driver to be compiled as
loadable kernel module.
Signed-off-by: Manikanta Maddireddy <mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* commit message update
V3:
* EXPORT_SYMBOL is changed to EXPORT_SYMBOL_GPL
drivers/pci/host-bridge.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c
index add66236215c..b8c0fcde9bd7 100644
--- a/drivers/pci/host-bridge.c
+++ b/drivers/pci/host-bridge.c
@@ -22,6 +22,7 @@ struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus)
return to_pci_host_bridge(root_bus->bridge);
}
+EXPORT_SYMBOL_GPL(pci_find_host_bridge);
struct device *pci_get_host_bridge_device(struct pci_dev *dev)
{
--
2.1.4
^ permalink raw reply related
* [PATCH V3 3/7] PCI: tegra: Remove PCI_REASSIGN_ALL_BUS flag for Tegra PCIe
From: Manikanta Maddireddy @ 2017-12-01 9:20 UTC (permalink / raw)
To: cyndis, thierry.reding, bhelgaas, lorenzo.pieralisi
Cc: jonathanh, robh+dt, frowand.list, rjw, tglx, vidyas, kthota,
linux-tegra, devicetree, linux-pci, linux-pm,
Manikanta Maddireddy
In-Reply-To: <1512120007-28088-1-git-send-email-mmaddireddy@nvidia.com>
Primary, secondary and subordinate default bus numbers are 0 in Tegra and
it is expecting SW to program these numbers in configration space.
pci_scan_bridge_extend() function programs these numbers in configuration
space if secondary & subordinate bus numbers are 0 or PCI_REASSIGN_ALL_BUS
flag is set. Since secondary & subordinate default bus numbers are 0,
PCI_REASSIGN_ALL_BUS flag can be removed for Tegra PCIe.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
V3:
* new patch in V3
drivers/pci/host/pci-tegra.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 72a316940723..2a108c798846 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -2706,7 +2706,6 @@ static int tegra_pcie_probe(struct platform_device *pdev)
tegra_pcie_enable_ports(pcie);
- pci_add_flags(PCI_REASSIGN_ALL_BUS);
host->busnr = pcie->busn.start;
host->dev.parent = &pdev->dev;
host->ops = &tegra_pcie_ops;
--
2.1.4
^ permalink raw reply related
* [PATCH V3 4/7] PCI: tegra: Free resources on probe failure
From: Manikanta Maddireddy @ 2017-12-01 9:20 UTC (permalink / raw)
To: cyndis-/1wQRMveznE, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, lorenzo.pieralisi-5wv7dgnIgG8
Cc: jonathanh-DDmLM1+adcrQT0dZR+AlfA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, rjw-LthD3rsA81gm4RdzfppkhA,
tglx-hfZtesqFncYOwBW4kG4KsQ, vidyas-DDmLM1+adcrQT0dZR+AlfA,
kthota-DDmLM1+adcrQT0dZR+AlfA, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA,
Manikanta Maddireddy
In-Reply-To: <1512120007-28088-1-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
tegra_pcie_probe() can fail in multiple instances, this patch takes care
of freeing the resources which are allocated before probe fail.
Signed-off-by: Manikanta Maddireddy <mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* no change in this patch
V3:
* change 'if check' to 'legacy_phy is true' for tegra_pcie_phys_put_legacy()
* commit log correction
drivers/pci/host/pci-tegra.c | 100 ++++++++++++++++++++++++++++++++++++-------
1 file changed, 84 insertions(+), 16 deletions(-)
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 2a108c798846..36795b34d996 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -701,14 +701,25 @@ static int tegra_pcie_request_resources(struct tegra_pcie *pcie)
pci_add_resource(windows, &pcie->busn);
err = devm_request_pci_bus_resources(dev, windows);
- if (err < 0)
+ if (err < 0) {
+ pci_free_resource_list(windows);
return err;
+ }
pci_remap_iospace(&pcie->pio, pcie->io.start);
return 0;
}
+static void tegra_pcie_free_resources(struct tegra_pcie *pcie)
+{
+ struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
+ struct list_head *windows = &host->windows;
+
+ pci_unmap_iospace(&pcie->pio);
+ pci_free_resource_list(windows);
+}
+
static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
{
struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus);
@@ -1109,29 +1120,40 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
return 0;
}
-static void tegra_pcie_power_off(struct tegra_pcie *pcie)
+static void tegra_pcie_disable_controller(struct tegra_pcie *pcie)
{
struct device *dev = pcie->dev;
const struct tegra_pcie_soc *soc = pcie->soc;
int err;
- /* TODO: disable and unprepare clocks? */
-
if (soc->program_uphy) {
err = tegra_pcie_phy_power_off(pcie);
if (err < 0)
dev_err(dev, "failed to power off PHY(s): %d\n", err);
}
+}
+
+static void tegra_pcie_power_off(struct tegra_pcie *pcie)
+{
+ struct device *dev = pcie->dev;
+ const struct tegra_pcie_soc *soc = pcie->soc;
+ int err;
reset_control_assert(pcie->afi_rst);
reset_control_assert(pcie->pex_rst);
- if (!dev->pm_domain)
- tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
+ clk_disable_unprepare(pcie->pll_e);
+ if (soc->has_cml_clk)
+ clk_disable_unprepare(pcie->cml_clk);
+ clk_disable_unprepare(pcie->afi_clk);
+ clk_disable_unprepare(pcie->pex_clk);
err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
if (err < 0)
dev_warn(dev, "failed to disable regulators: %d\n", err);
+
+ if (!dev->pm_domain)
+ tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
}
static int tegra_pcie_power_on(struct tegra_pcie *pcie)
@@ -1262,6 +1284,15 @@ static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie)
return 0;
}
+static void tegra_pcie_phys_put_legacy(struct tegra_pcie *pcie)
+{
+ int err;
+
+ err = phy_exit(pcie->phy);
+ if (err < 0)
+ dev_err(pcie->dev, "failed to teardown PHY: %d\n", err);
+}
+
static struct phy *devm_of_phy_optional_get_index(struct device *dev,
struct device_node *np,
const char *consumer,
@@ -1315,6 +1346,19 @@ static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port)
return 0;
}
+static void tegra_pcie_port_put_phys(struct tegra_pcie_port *port)
+{
+ struct device *dev = port->pcie->dev;
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < port->lanes; i++) {
+ err = phy_exit(port->phys[i]);
+ if (err < 0)
+ dev_err(dev, "failed to teardown PHY#%u: %d\n", i, err);
+ }
+}
+
static int tegra_pcie_phys_get(struct tegra_pcie *pcie)
{
const struct tegra_pcie_soc *soc = pcie->soc;
@@ -1334,6 +1378,17 @@ static int tegra_pcie_phys_get(struct tegra_pcie *pcie)
return 0;
}
+static void tegra_pcie_phys_put(struct tegra_pcie *pcie)
+{
+ struct tegra_pcie_port *port;
+
+ if (pcie->legacy_phy)
+ tegra_pcie_phys_put_legacy(pcie);
+
+ list_for_each_entry(port, &pcie->ports, list)
+ tegra_pcie_port_put_phys(port);
+}
+
static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
{
struct device *dev = pcie->dev;
@@ -1366,7 +1421,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
err = tegra_pcie_power_on(pcie);
if (err) {
dev_err(dev, "failed to power up: %d\n", err);
- return err;
+ goto phys_put;
}
pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
@@ -1424,25 +1479,23 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
poweroff:
tegra_pcie_power_off(pcie);
+phys_put:
+ if (soc->program_uphy)
+ tegra_pcie_phys_put(pcie);
return err;
}
static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
{
- struct device *dev = pcie->dev;
const struct tegra_pcie_soc *soc = pcie->soc;
- int err;
if (pcie->irq > 0)
free_irq(pcie->irq, pcie);
tegra_pcie_power_off(pcie);
- if (soc->program_uphy) {
- err = phy_exit(pcie->phy);
- if (err < 0)
- dev_err(dev, "failed to teardown PHY: %d\n", err);
- }
+ if (soc->program_uphy)
+ tegra_pcie_phys_put(pcie);
return 0;
}
@@ -2371,6 +2424,16 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
}
}
+static void tegra_pcie_disable_ports(struct tegra_pcie *pcie)
+{
+ struct tegra_pcie_port *port, *tmp;
+
+ reset_control_assert(pcie->pcie_xrst);
+
+ list_for_each_entry_safe(port, tmp, &pcie->ports, list)
+ tegra_pcie_port_disable(port);
+}
+
static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie,
struct pci_dev *pci_dev)
{
@@ -2691,7 +2754,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
err = tegra_pcie_request_resources(pcie);
if (err)
- goto put_resources;
+ goto disable_controller;
/* setup the AFI address translations */
tegra_pcie_setup_translations(pcie);
@@ -2700,7 +2763,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
err = tegra_pcie_enable_msi(pcie);
if (err < 0) {
dev_err(dev, "failed to enable MSI support: %d\n", err);
- goto put_resources;
+ goto free_resources;
}
}
@@ -2740,6 +2803,11 @@ static int tegra_pcie_probe(struct platform_device *pdev)
disable_msi:
if (IS_ENABLED(CONFIG_PCI_MSI))
tegra_pcie_disable_msi(pcie);
+ tegra_pcie_disable_ports(pcie);
+free_resources:
+ tegra_pcie_free_resources(pcie);
+disable_controller:
+ tegra_pcie_disable_controller(pcie);
put_resources:
tegra_pcie_put_resources(pcie);
return err;
--
2.1.4
^ permalink raw reply related
* [PATCH V3 5/7] PCI: tegra: Add loadable kernel module support
From: Manikanta Maddireddy @ 2017-12-01 9:20 UTC (permalink / raw)
To: cyndis-/1wQRMveznE, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, lorenzo.pieralisi-5wv7dgnIgG8
Cc: jonathanh-DDmLM1+adcrQT0dZR+AlfA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, rjw-LthD3rsA81gm4RdzfppkhA,
tglx-hfZtesqFncYOwBW4kG4KsQ, vidyas-DDmLM1+adcrQT0dZR+AlfA,
kthota-DDmLM1+adcrQT0dZR+AlfA, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA,
Manikanta Maddireddy
In-Reply-To: <1512120007-28088-1-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Implement remove callback function for Tegra PCIe driver to add
loadable kernel module support. Change PCI_TEGRA config to tristate to
allow pci-tegra driver to be build as a module.
Signed-off-by: Manikanta Maddireddy <mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* no change in this patch
V3:
* use tegra_pcie_debugfs_exit() helper function in tegra_pcie_debugfs_init()
drivers/pci/host/Kconfig | 2 +-
drivers/pci/host/pci-tegra.c | 34 +++++++++++++++++++++++++++++++---
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 38d12980db0f..6fd2a5937804 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -34,7 +34,7 @@ config PCI_FTPCI100
default ARCH_GEMINI
config PCI_TEGRA
- bool "NVIDIA Tegra PCIe controller"
+ tristate "NVIDIA Tegra PCIe controller"
depends on ARCH_TEGRA
help
Say Y here if you want support for the PCIe host controller found
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 36795b34d996..2c13f43e8450 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -35,6 +35,7 @@
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/module.h>
#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
@@ -2697,6 +2698,12 @@ static const struct file_operations tegra_pcie_ports_ops = {
.release = seq_release,
};
+static void tegra_pcie_debugfs_exit(struct tegra_pcie *pcie)
+{
+ debugfs_remove_recursive(pcie->debugfs);
+ pcie->debugfs = NULL;
+}
+
static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie)
{
struct dentry *file;
@@ -2713,8 +2720,7 @@ static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie)
return 0;
remove:
- debugfs_remove_recursive(pcie->debugfs);
- pcie->debugfs = NULL;
+ tegra_pcie_debugfs_exit(pcie);
return -ENOMEM;
}
@@ -2732,6 +2738,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
return -ENOMEM;
pcie = pci_host_bridge_priv(host);
+ platform_set_drvdata(pdev, pcie);
pcie->soc = of_device_get_match_data(dev);
INIT_LIST_HEAD(&pcie->buses);
@@ -2813,6 +2820,25 @@ static int tegra_pcie_probe(struct platform_device *pdev)
return err;
}
+static int tegra_pcie_remove(struct platform_device *pdev)
+{
+ struct tegra_pcie *pcie = platform_get_drvdata(pdev);
+ struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
+
+ if (IS_ENABLED(CONFIG_DEBUG_FS))
+ tegra_pcie_debugfs_exit(pcie);
+ pci_stop_root_bus(host->bus);
+ pci_remove_root_bus(host->bus);
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ tegra_pcie_disable_msi(pcie);
+ tegra_pcie_disable_ports(pcie);
+ tegra_pcie_free_resources(pcie);
+ tegra_pcie_disable_controller(pcie);
+ tegra_pcie_put_resources(pcie);
+
+ return 0;
+}
+
static struct platform_driver tegra_pcie_driver = {
.driver = {
.name = "tegra-pcie",
@@ -2820,5 +2846,7 @@ static struct platform_driver tegra_pcie_driver = {
.suppress_bind_attrs = true,
},
.probe = tegra_pcie_probe,
+ .remove = tegra_pcie_remove,
};
-builtin_platform_driver(tegra_pcie_driver);
+module_platform_driver(tegra_pcie_driver);
+MODULE_LICENSE("GPL");
--
2.1.4
^ permalink raw reply related
* [PATCH V3 6/7] PCI: tegra: Broadcast PME_Turn_Off message before link goes to L2
From: Manikanta Maddireddy @ 2017-12-01 9:20 UTC (permalink / raw)
To: cyndis, thierry.reding, bhelgaas, lorenzo.pieralisi
Cc: jonathanh, robh+dt, frowand.list, rjw, tglx, vidyas, kthota,
linux-tegra, devicetree, linux-pci, linux-pm,
Manikanta Maddireddy
In-Reply-To: <1512120007-28088-1-git-send-email-mmaddireddy@nvidia.com>
Per PCIe r3.0, sec 5.3.3.2.1, PCIe root port shoould broadcast PME_Turn_Off
message before PCIe link goes to L2. PME_Turn_Off broadcast mechanism is
implemented in AFI module. Each Tegra PCIe root port has its own
PME_Turn_Off and PME_TO_Ack bitmap in AFI_PME register, program this
register to broadcast PME_Turn_Off message.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
V2:
* no change in this patch
V3:
* add PME bitmap in soc data instead of using compatible string
* replace while loop with readl_poll_timeout() for polling
* commit log correction
drivers/pci/host/pci-tegra.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 2c13f43e8450..bc532c0fd04f 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -31,6 +31,7 @@
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/interrupt.h>
+#include <linux/iopoll.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
@@ -155,6 +156,8 @@
#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
#define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
+#define AFI_PCIE_PME 0xf0
+
#define AFI_PCIE_CONFIG 0x0f8
#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
@@ -315,6 +318,7 @@
#define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
#define LINK_RETRAIN_TIMEOUT 100000
+#define PME_ACK_TIMEOUT 10000
struct tegra_msi {
struct msi_controller chip;
@@ -342,6 +346,8 @@ struct tegra_pcie_soc {
u32 rp_ectl_4_r2;
u32 rp_ectl_5_r2;
u32 rp_ectl_6_r2;
+ u8 pme_turnoff_bit[3];
+ u8 pme_ack_bit[3];
bool has_pex_clkreq_en;
bool has_pex_bias_ctrl;
bool has_intr_prsnt_sense;
@@ -1501,6 +1507,31 @@ static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
return 0;
}
+static void tegra_pcie_pme_turnoff(struct tegra_pcie_port *port)
+{
+ struct tegra_pcie *pcie = port->pcie;
+ const struct tegra_pcie_soc *soc = pcie->soc;
+ int err;
+ u32 val;
+
+ val = afi_readl(pcie, AFI_PCIE_PME);
+ val |= (0x1 << soc->pme_turnoff_bit[port->index]);
+ afi_writel(pcie, val, AFI_PCIE_PME);
+
+ err = readl_poll_timeout(pcie->afi + AFI_PCIE_PME, val,
+ val & (0x1 << soc->pme_ack_bit[port->index]),
+ 1, PME_ACK_TIMEOUT);
+ if (err)
+ dev_err(pcie->dev, "PME Ack is not received on port: %d\n",
+ port->index);
+
+ usleep_range(10000, 11000);
+
+ val = afi_readl(pcie, AFI_PCIE_PME);
+ val &= ~(0x1 << soc->pme_turnoff_bit[port->index]);
+ afi_writel(pcie, val, AFI_PCIE_PME);
+}
+
static int tegra_msi_alloc(struct tegra_msi *chip)
{
int msi;
@@ -2477,6 +2508,8 @@ static const struct tegra_pcie_soc tegra20_pcie = {
.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
.pads_refclk_cfg0 = 0xfa5cfa5c,
+ .pme_turnoff_bit = {0, 8},
+ .pme_ack_bit = {5, 10},
.has_pex_clkreq_en = false,
.has_pex_bias_ctrl = false,
.has_intr_prsnt_sense = false,
@@ -2502,6 +2535,8 @@ static const struct tegra_pcie_soc tegra30_pcie = {
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
.pads_refclk_cfg0 = 0xfa5cfa5c,
.pads_refclk_cfg1 = 0xfa5cfa5c,
+ .pme_turnoff_bit = {0, 8, 16},
+ .pme_ack_bit = {5, 10, 18},
.has_pex_clkreq_en = true,
.has_pex_bias_ctrl = true,
.has_intr_prsnt_sense = true,
@@ -2526,6 +2561,8 @@ static const struct tegra_pcie_soc tegra124_pcie = {
.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
.pads_refclk_cfg0 = 0x44ac44ac,
+ .pme_turnoff_bit = {0, 8},
+ .pme_ack_bit = {5, 10},
.has_pex_clkreq_en = true,
.has_pex_bias_ctrl = true,
.has_intr_prsnt_sense = true,
@@ -2550,6 +2587,8 @@ static const struct tegra_pcie_soc tegra210_pcie = {
.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
.pads_refclk_cfg0 = 0x90b890b8,
+ .pme_turnoff_bit = {0, 8},
+ .pme_ack_bit = {5, 10},
.rp_ectl_2_r1 = 0x0000000f,
.rp_ectl_4_r1 = 0x00000067,
.rp_ectl_5_r1 = 0x55010000,
@@ -2583,6 +2622,8 @@ static const struct tegra_pcie_soc tegra186_pcie = {
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
.pads_refclk_cfg0 = 0x80b880b8,
.pads_refclk_cfg1 = 0x000480b8,
+ .pme_turnoff_bit = {0, 8, 12},
+ .pme_ack_bit = {5, 10, 14},
.has_pex_clkreq_en = true,
.has_pex_bias_ctrl = true,
.has_intr_prsnt_sense = true,
@@ -2824,6 +2865,7 @@ static int tegra_pcie_remove(struct platform_device *pdev)
{
struct tegra_pcie *pcie = platform_get_drvdata(pdev);
struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
+ struct tegra_pcie_port *port, *tmp;
if (IS_ENABLED(CONFIG_DEBUG_FS))
tegra_pcie_debugfs_exit(pcie);
@@ -2831,6 +2873,8 @@ static int tegra_pcie_remove(struct platform_device *pdev)
pci_remove_root_bus(host->bus);
if (IS_ENABLED(CONFIG_PCI_MSI))
tegra_pcie_disable_msi(pcie);
+ list_for_each_entry_safe(port, tmp, &pcie->ports, list)
+ tegra_pcie_pme_turnoff(port);
tegra_pcie_disable_ports(pcie);
tegra_pcie_free_resources(pcie);
tegra_pcie_disable_controller(pcie);
--
2.1.4
^ permalink raw reply related
* [PATCH V3 7/7] PCI: tegra: Add power management support
From: Manikanta Maddireddy @ 2017-12-01 9:20 UTC (permalink / raw)
To: cyndis-/1wQRMveznE, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, lorenzo.pieralisi-5wv7dgnIgG8
Cc: jonathanh-DDmLM1+adcrQT0dZR+AlfA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, rjw-LthD3rsA81gm4RdzfppkhA,
tglx-hfZtesqFncYOwBW4kG4KsQ, vidyas-DDmLM1+adcrQT0dZR+AlfA,
kthota-DDmLM1+adcrQT0dZR+AlfA, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA,
Manikanta Maddireddy
In-Reply-To: <1512120007-28088-1-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Tegra186 powergate driver is implemented as power domain driver, power
partition ungate/gate are registered as power_on/power_off callback
functions. There are no direct functions to power gate/ungate host
controller in Tegra186. Host controller driver should add "power-domains"
property in device tree and implement runtime suspend and resume
callback functons. Power gate and ungate is taken care by power domain
driver when host controller driver calls pm_runtime_put_sync and
pm_runtime_get_sync respectively.
Register suspend_noirq & resume_noirq callback functions to allow PCIe to
come up after resume from RAM. Both runtime and noirq pm ops share same
callback functions.
Signed-off-by: Manikanta Maddireddy <mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* no change in this patch
V3:
* no change in this patch
drivers/pci/host/pci-tegra.c | 174 ++++++++++++++++++++++++++-----------------
1 file changed, 106 insertions(+), 68 deletions(-)
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index bc532c0fd04f..30af1bf5620e 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -1425,31 +1425,25 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
}
}
- err = tegra_pcie_power_on(pcie);
- if (err) {
- dev_err(dev, "failed to power up: %d\n", err);
- goto phys_put;
- }
-
pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
pcie->pads = devm_ioremap_resource(dev, pads);
if (IS_ERR(pcie->pads)) {
err = PTR_ERR(pcie->pads);
- goto poweroff;
+ goto phys_put;
}
afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
pcie->afi = devm_ioremap_resource(dev, afi);
if (IS_ERR(pcie->afi)) {
err = PTR_ERR(pcie->afi);
- goto poweroff;
+ goto phys_put;
}
/* request configuration space, but remap later, on demand */
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs");
if (!res) {
err = -EADDRNOTAVAIL;
- goto poweroff;
+ goto phys_put;
}
axi_addr = pcie->soc->use_4k_conf_space ?
@@ -1457,21 +1451,21 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
pcie->cs = devm_request_mem_region(dev, axi_addr, SZ_4K, res->name);
if (!pcie->cs) {
err = -EADDRNOTAVAIL;
- goto poweroff;
+ goto phys_put;
}
pcie->cfg_va_base = devm_ioremap(dev, pcie->cs->start, SZ_4K);
if (!pcie->cfg_va_base) {
dev_err(pcie->dev, "failed to ioremap config space\n");
err = -EADDRNOTAVAIL;
- goto poweroff;
+ goto phys_put;
}
/* request interrupt */
err = platform_get_irq_byname(pdev, "intr");
if (err < 0) {
dev_err(dev, "failed to get IRQ: %d\n", err);
- goto poweroff;
+ goto phys_put;
}
pcie->irq = err;
@@ -1479,13 +1473,11 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
if (err) {
dev_err(dev, "failed to register IRQ: %d\n", err);
- goto poweroff;
+ goto phys_put;
}
return 0;
-poweroff:
- tegra_pcie_power_off(pcie);
phys_put:
if (soc->program_uphy)
tegra_pcie_phys_put(pcie);
@@ -1499,8 +1491,6 @@ static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
if (pcie->irq > 0)
free_irq(pcie->irq, pcie);
- tegra_pcie_power_off(pcie);
-
if (soc->program_uphy)
tegra_pcie_phys_put(pcie);
@@ -1678,37 +1668,41 @@ static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
int err;
u32 reg;
- mutex_init(&msi->lock);
+ if (!msi->phys) {
+ mutex_init(&msi->lock);
- msi->chip.dev = dev;
- msi->chip.setup_irq = tegra_msi_setup_irq;
- msi->chip.teardown_irq = tegra_msi_teardown_irq;
+ msi->chip.dev = dev;
+ msi->chip.setup_irq = tegra_msi_setup_irq;
+ msi->chip.teardown_irq = tegra_msi_teardown_irq;
- msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR,
- &msi_domain_ops, &msi->chip);
- if (!msi->domain) {
- dev_err(dev, "failed to create IRQ domain\n");
- return -ENOMEM;
- }
+ msi->domain = irq_domain_add_linear(dev->of_node,
+ INT_PCI_MSI_NR,
+ &msi_domain_ops,
+ &msi->chip);
+ if (!msi->domain) {
+ dev_err(dev, "failed to create IRQ domain\n");
+ return -ENOMEM;
+ }
- err = platform_get_irq_byname(pdev, "msi");
- if (err < 0) {
- dev_err(dev, "failed to get IRQ: %d\n", err);
- goto err;
- }
+ err = platform_get_irq_byname(pdev, "msi");
+ if (err < 0) {
+ dev_err(dev, "failed to get IRQ: %d\n", err);
+ goto err;
+ }
- msi->irq = err;
+ msi->irq = err;
- err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD,
- tegra_msi_irq_chip.name, pcie);
- if (err < 0) {
- dev_err(dev, "failed to request IRQ: %d\n", err);
- goto err;
- }
+ err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD,
+ tegra_msi_irq_chip.name, pcie);
+ if (err < 0) {
+ dev_err(dev, "failed to request IRQ: %d\n", err);
+ goto err;
+ }
- /* setup AFI/FPCI range */
- msi->pages = __get_free_pages(GFP_KERNEL, 0);
- msi->phys = virt_to_phys((void *)msi->pages);
+ /* setup AFI/FPCI range */
+ msi->pages = __get_free_pages(GFP_KERNEL, 0);
+ msi->phys = virt_to_phys((void *)msi->pages);
+ }
afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST);
@@ -2796,26 +2790,16 @@ static int tegra_pcie_probe(struct platform_device *pdev)
return err;
}
- err = tegra_pcie_enable_controller(pcie);
- if (err)
+ pm_runtime_enable(pcie->dev);
+ err = pm_runtime_get_sync(pcie->dev);
+ if (err) {
+ dev_err(dev, "fail to enable pcie controller: %d\n", err);
goto put_resources;
+ }
err = tegra_pcie_request_resources(pcie);
if (err)
- goto disable_controller;
-
- /* setup the AFI address translations */
- tegra_pcie_setup_translations(pcie);
-
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- err = tegra_pcie_enable_msi(pcie);
- if (err < 0) {
- dev_err(dev, "failed to enable MSI support: %d\n", err);
- goto free_resources;
- }
- }
-
- tegra_pcie_enable_ports(pcie);
+ goto pm_runtime_put;
host->busnr = pcie->busn.start;
host->dev.parent = &pdev->dev;
@@ -2826,7 +2810,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
err = pci_scan_root_bus_bridge(host);
if (err < 0) {
dev_err(dev, "failed to register host: %d\n", err);
- goto disable_msi;
+ goto free_resources;
}
pci_bus_size_bridges(host->bus);
@@ -2848,14 +2832,13 @@ static int tegra_pcie_probe(struct platform_device *pdev)
return 0;
-disable_msi:
- if (IS_ENABLED(CONFIG_PCI_MSI))
- tegra_pcie_disable_msi(pcie);
- tegra_pcie_disable_ports(pcie);
free_resources:
tegra_pcie_free_resources(pcie);
-disable_controller:
- tegra_pcie_disable_controller(pcie);
+pm_runtime_put:
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ tegra_pcie_disable_msi(pcie);
+ pm_runtime_put_sync(pcie->dev);
+ pm_runtime_disable(pcie->dev);
put_resources:
tegra_pcie_put_resources(pcie);
return err;
@@ -2865,7 +2848,6 @@ static int tegra_pcie_remove(struct platform_device *pdev)
{
struct tegra_pcie *pcie = platform_get_drvdata(pdev);
struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
- struct tegra_pcie_port *port, *tmp;
if (IS_ENABLED(CONFIG_DEBUG_FS))
tegra_pcie_debugfs_exit(pcie);
@@ -2873,21 +2855,77 @@ static int tegra_pcie_remove(struct platform_device *pdev)
pci_remove_root_bus(host->bus);
if (IS_ENABLED(CONFIG_PCI_MSI))
tegra_pcie_disable_msi(pcie);
+ tegra_pcie_free_resources(pcie);
+ pm_runtime_put_sync(pcie->dev);
+ pm_runtime_disable(pcie->dev);
+ tegra_pcie_put_resources(pcie);
+
+ return 0;
+}
+
+static int tegra_pcie_pm_suspend(struct device *dev)
+{
+ struct tegra_pcie *pcie = dev_get_drvdata(dev);
+ struct tegra_pcie_port *port, *tmp;
+
list_for_each_entry_safe(port, tmp, &pcie->ports, list)
tegra_pcie_pme_turnoff(port);
tegra_pcie_disable_ports(pcie);
- tegra_pcie_free_resources(pcie);
tegra_pcie_disable_controller(pcie);
- tegra_pcie_put_resources(pcie);
+ tegra_pcie_power_off(pcie);
return 0;
}
+static int tegra_pcie_pm_resume(struct device *dev)
+{
+ struct tegra_pcie *pcie = dev_get_drvdata(dev);
+ int err;
+
+ err = tegra_pcie_power_on(pcie);
+ if (err) {
+ dev_err(dev, "tegra pcie power on fail: %d\n", err);
+ return err;
+ }
+ err = tegra_pcie_enable_controller(pcie);
+ if (err) {
+ dev_err(dev, "tegra pcie controller enable fail: %d\n", err);
+ goto poweroff;
+ }
+ tegra_pcie_setup_translations(pcie);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ err = tegra_pcie_enable_msi(pcie);
+ if (err < 0) {
+ dev_err(dev, "failed to enable MSI support: %d\n", err);
+ goto disable_controller;
+ }
+ }
+
+ tegra_pcie_enable_ports(pcie);
+
+ return 0;
+
+disable_controller:
+ tegra_pcie_disable_controller(pcie);
+poweroff:
+ tegra_pcie_power_off(pcie);
+
+ return err;
+}
+
+static const struct dev_pm_ops tegra_pcie_pm_ops = {
+ SET_RUNTIME_PM_OPS(tegra_pcie_pm_suspend, tegra_pcie_pm_resume, NULL)
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_pcie_pm_suspend,
+ tegra_pcie_pm_resume)
+};
+
static struct platform_driver tegra_pcie_driver = {
.driver = {
.name = "tegra-pcie",
.of_match_table = tegra_pcie_of_match,
.suppress_bind_attrs = true,
+ .pm = &tegra_pcie_pm_ops,
},
.probe = tegra_pcie_probe,
.remove = tegra_pcie_remove,
--
2.1.4
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^ permalink raw reply related
* Re: [PATCH] ARM64: dts: meson-axg: enable IR controller
From: Jerome Brunet @ 2017-12-01 9:25 UTC (permalink / raw)
To: Yixun Lan, Kevin Hilman, Rob Herring, devicetree
Cc: Neil Armstrong, Mark Rutland, Carlo Caione, linux-amlogic,
linux-arm-kernel, linux-kernel
In-Reply-To: <20171201013612.13927-1-yixun.lan@amlogic.com>
On Fri, 2017-12-01 at 09:36 +0800, Yixun Lan wrote:
> Enable IR remote controller which find in Amlogic's Meson-AXG SoC.
>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 6 ++++++
> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 14 ++++++++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> index 0864d1ff2d9b..ca676cafdbb3 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> @@ -34,3 +34,9 @@
> pinctrl-0 = <&i2c1_z_pins>;
> pinctrl-names = "default";
> };
> +
> +&ir {
> + status = "okay";
> + pinctrl-0 = <&remote_input_ao_pins>;
> + pinctrl-names = "default";
> +};
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index 9bb85893c1b7..80d5b8c13fac 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -616,6 +616,13 @@
> #gpio-cells = <2>;
> gpio-ranges = <&pinctrl_aobus 0 0
> 15>;
> };
> +
> + remote_input_ao_pins: remote_input_ao {
> + mux {
> + groups = "remote_input_ao";
> + function = "remote_input_ao";
> + };
> + };
> };
>
> i2c_AO: i2c@5000 {
> @@ -664,6 +671,13 @@
> clock-names = "xtal", "pclk", "baud";
> status = "disabled";
> };
> +
> + ir: ir@8000 {
> + compatible = "amlogic,meson-gx-
> ir","amlogic,meson-gxbb-ir";
The order is bad here (Yes the same mistake is present a *LOT* in the gx family
- I'm preparing a patch for that). In addition, "amlogic,meson-gx-ir" is
unmatched, undocumented and unlikely to be ever used since every compatible SoC
will use the gxbb compatible string. You may as well drop it and just keep the
gxbb one
> + reg = <0x0 0x8000 0x0 0x20>;
> + interrupts = <GIC_SPI 196
> IRQ_TYPE_EDGE_RISING>;
> + status = "disabled";
> + };
> };
> };
> };
^ permalink raw reply
* Re: [RFC PATCH 1/3] dt-bindings: pinctrl: sunxi: document new generic binding
From: Linus Walleij @ 2017-12-01 9:38 UTC (permalink / raw)
To: Andre Przywara
Cc: Thierry Reding, Maxime Ripard, Chen-Yu Tsai,
linux-gpio-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, Arnd Bergmann, Icenowy Zheng,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
In-Reply-To: <0c8051e6-5d8c-32d6-97e4-11c2283da5b4-5wv7dgnIgG8@public.gmane.org>
On Fri, Nov 24, 2017 at 6:19 PM, Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org> wrote:
> On 24/11/17 13:31, Thierry Reding wrote:
>> Register values don't belong in a device tree.
>
> I don't think that's true in a general way. This "pinmux" is already an
> accepted property and used for exactly that purpose in other pinctrl
> drivers:
> $ git grep -l '[^,]pinmux = ' arch/arm{,64}/boot/dts
> Plus the fsl,pinmux-ids property, which seems to serve the same purpose.
There are several examples of register values (and register
numbers even!) being encoded in the kernel.
What we need to ask is whether that is good in the general case
or bad. I don't even think that has a clear answer, it's a grey area.
So we need to avoid "arguments from consistency" which reads
something like "you allowed this thing A so now you must allow
this thing B which is similar". It is not a helpful approach to the
problem.
Some drivers encode a bunch of data into the device tree,
pinctrl-single is the most extreme. This conflict between in-DT
and in-driver data storage has been there since pinctrl was created
and was the result of a compromise between OMAPs needs
and everyone else, especially Tegra.
The opinions on this - and it is really opinions, not facts - differ
between people and over time.
Resolving the conflicts is more about classical diplomacy than
science unfortunately. I used to think the christian trinity was
amusing and inconsistent, but nowadays I understand exactly how
the people who came up with the Nicean creed were reasoning.
What is paramount for me as subsystem maintainer is the fact
that this driver has an active maintainer. And maintainers
is what makes things manageable for me. It would be much easier
for you to have your way if you were submitting an entirely
new driver. Like this pinmux property, it was submitted by the
mediatek people because it fits their usecase/hardware especially
well.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3 4/4] DTS: Pandora: fix panel compatibility string
From: H. Nikolaus Schaller @ 2017-12-01 9:48 UTC (permalink / raw)
To: Tomi Valkeinen
Cc: Mark Rutland, DTML, Julia Lawall,
Discussions about the Letux Kernel, Bartlomiej Zolnierkiewicz,
Tony Lindgren, Linux Kernel Mailing List, dri-devel,
Sebastian Reichel, Rob Herring, Russell King, David Airlie,
linux-fbdev, Thierry Reding, Sean Paul, Laurent Pinchart,
Benoît Cousson, kernel, linux-omap, Linux ARM
In-Reply-To: <6ca5f2ea-e725-9a9e-ac02-e16beca4a1a0@ti.com>
Hi Tomi,
> Am 01.12.2017 um 09:13 schrieb Tomi Valkeinen <tomi.valkeinen@ti.com>:
>
> On 01/12/17 00:06, Sebastian Reichel wrote:
>
>>>>> How about let's call it a "typo fix" then? :)
>>>>
>>>> Well, it is not really a typo.
>>>
>>> Well what if the stable people pick it into earlier stable series
>>> based on the word fix in the subject? That has happened before.
>>>
>>> I suggest you update the dts patches to use wording like
>>> "update compatible to use new naming" or something similar.
>>
>> Patch 4/4 is a Fix and should be applied to stable trees. "omapdss,"
>> prefix was never supposed to be in the DTS files, is not supposed to
>> be in there now and will break some time in the future.
>>
>> Explanation: The early init of omapdss adds the prefix at runtime,
>> so that the binding can use generic properties and the kernel can
>> use omapdss specific drivers until the generic ones can be used
>
> This is true, but the extra "omapdss" does not cause any issues at the
> moment, and the time when it causes issues is still many kernel versions
> in the future.
>
> But, yes, thinking about this, I agree, it's better to pick this one
> separately as a fix (after rebasing it on top of current maineline so
> that it doesn't depend on the toppoly name change), and leaving the
> toppoly->tpo change as a cleanup.
Just a note: there is no toppoly->tpo change for *this* panel and
Pandora board. Just omapdss removal.
The GTA04 needs a toppoly->tpo change but no omapdss, removal.
So they solve different problems and are independent of each other.
GTA04: change vendor string
Pandora: remove omapdss, prefix
BR and thanks,
Nikolaus
^ permalink raw reply
* Re: [PATCH v8 07/13] slimbus: Add support for 'clock-pause' feature
From: Greg Kroah-Hartman @ 2017-12-01 9:51 UTC (permalink / raw)
To: Philippe Ombredanne
Cc: Srini Kandagatla, Mark, ALSA, Sagar Dharia, bp, poeschel, treding,
andreas.noever, alan, mathieu.poirier, daniel, jkosina,
sharon.dvir1, Joe Perches, David S. Miller, james.hogan,
michael.opdenacker, Rob Herring, pawel.moll, Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML,
linux-arm-msm, Vinod Koul
In-Reply-To: <CAOFm3uE+ehT+WGHO2tYz4W8h35wBgge+BO5fS=yuxemq28TERg@mail.gmail.com>
On Thu, Nov 30, 2017 at 08:25:26PM +0100, Philippe Ombredanne wrote:
> On Thu, Nov 30, 2017 at 6:41 PM, <srinivas.kandagatla@linaro.org> wrote:
> []
> > diff --git a/drivers/slimbus/sched.c b/drivers/slimbus/sched.c
> > new file mode 100644
> > index 000000000000..74300f1a6898
> > --- /dev/null
> > +++ b/drivers/slimbus/sched.c
> > @@ -0,0 +1,128 @@
> > +/* Copyright (c) 2011-2016, The Linux Foundation. All rights reserved.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 and
> > + * only version 2 as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
>
> Could it make sense to use the new SPDX ids here? e.g.
>
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright (c) 2011-2016, The Linux Foundation
>
> This neat and cleaner, is it?
> See tglx doc posted as patches and Linus comments for a rationale on
> the comment styles.
Yes please, otherwise I'll just have to write add-on patches to do just
this :)
thanks,
greg k-h
^ permalink raw reply
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