* [PATCH v6 00/13] Add STM32 DFSDM support
From: Arnaud Pouliquen @ 2017-12-01 17:40 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree, alsa-devel, Alexandre Torgue, linux-iio,
arnaud.pouliquen, Maxime Coquelin, linux-arm-kernel
Hello,
Here is a new version to fix kbuild test warnings
Main deltas V6 vs V5:
- Fix warning reported by kbuild test in :
include/linux/iio/consumer.h
sound/soc/stm/stm32_adfsdm.c
Main deltas V5 vs V4:
- Integrate ASOC DAI as a subnode of the DFSDM.
- Add in kernel consumer interface to allow to manipulate attribute.
Context reminder:
-----------------
DFSDM peripheral is a peripheral that allows to connect some sigma delta ADCs
or PDM microphones via a SPI or Manchester bus.
DFSDM integrates digital filters to offer up to 24 bits final resolution.
In term of SW architecture. 2 use-cases have to be supported:
1) Sigma delta ADC conversion through IIO framework.
Sigma delta ADC is handled by generic sigma delta modulator driver.
DFSDM peripheral is binded to a SD modulator ADC using the IIO HW consumer interface.
Please notice that IIO HW consumer interface has be proposed by Lars, but is
part of this patchset with Lars's agreement.
User interface is IIO one.
Notice that this patch-set propose only a raw conversion, to simplify review.
Buffer and trigger management will be added in next patch-sets.
2) PDM microphone record through ALSA framework.
PDM microphone is handled by ASOC Generic DMIC codec driver.
ADFSDM ASOC DAI driver is binded to IIO driver using the IIO consumer interface
ADFSDM ASOC DAI driver is binded to a PDM microphone ASOC component using ASOC Of_graph.
User interface is ALSA one.
As IIO DMA management is not adapted to an audio realtime stream. A specific DMA
management has been implemented in IIO driver for audio purposes.
Regards,
Arnaud
Arnaud Pouliquen (12):
docs: driver-api: add iio hw consumer section
IIO: hw_consumer: add devm_iio_hw_consumer_alloc
IIO: inkern: API for manipulating channel attributes
IIO: Add DT bindings for sigma delta adc modulator
IIO: ADC: add sigma delta modulator support
IIO: add DT bindings for stm32 DFSDM filter
IIO: ADC: add stm32 DFSDM core support
IIO: ADC: add STM32 DFSDM sigma delta ADC support
IIO: ADC: add stm32 DFSDM support for PDM microphone
IIO: consumer: allow to set buffer sizes
ASoC: add bindings for stm32 DFSDM filter
ASoC: stm32: add DFSDM DAI support
Lars-Peter Clausen (1):
iio: Add hardware consumer buffer support
.../ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32 | 16 +
.../bindings/iio/adc/sigma-delta-modulator.txt | 13 +
.../bindings/iio/adc/st,stm32-dfsdm-adc.txt | 127 ++
.../devicetree/bindings/sound/st,stm32-adfsdm.txt | 62 +
Documentation/driver-api/iio/hw-consumer.rst | 51 +
Documentation/driver-api/iio/index.rst | 1 +
drivers/iio/adc/Kconfig | 37 +
drivers/iio/adc/Makefile | 3 +
drivers/iio/adc/sd_adc_modulator.c | 81 ++
drivers/iio/adc/stm32-dfsdm-adc.c | 1232 ++++++++++++++++++++
drivers/iio/adc/stm32-dfsdm-core.c | 318 +++++
drivers/iio/adc/stm32-dfsdm.h | 319 +++++
drivers/iio/buffer/Kconfig | 10 +
drivers/iio/buffer/Makefile | 1 +
drivers/iio/buffer/industrialio-buffer-cb.c | 11 +
drivers/iio/buffer/industrialio-hw-consumer.c | 248 ++++
drivers/iio/inkern.c | 18 +-
include/linux/iio/adc/stm32-dfsdm-adc.h | 28 +
include/linux/iio/consumer.h | 39 +-
include/linux/iio/hw-consumer.h | 22 +
sound/soc/stm/Kconfig | 11 +
sound/soc/stm/Makefile | 3 +
sound/soc/stm/stm32_adfsdm.c | 386 ++++++
23 files changed, 3031 insertions(+), 6 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32
create mode 100644 Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt
create mode 100644 Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt
create mode 100644 Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt
create mode 100644 Documentation/driver-api/iio/hw-consumer.rst
create mode 100644 drivers/iio/adc/sd_adc_modulator.c
create mode 100644 drivers/iio/adc/stm32-dfsdm-adc.c
create mode 100644 drivers/iio/adc/stm32-dfsdm-core.c
create mode 100644 drivers/iio/adc/stm32-dfsdm.h
create mode 100644 drivers/iio/buffer/industrialio-hw-consumer.c
create mode 100644 include/linux/iio/adc/stm32-dfsdm-adc.h
create mode 100644 include/linux/iio/hw-consumer.h
create mode 100644 sound/soc/stm/stm32_adfsdm.c
--
2.7.4
^ permalink raw reply
* Re: [PATCH v3 0/4] Fixes for omapdrm on OpenPandora and GTA04
From: Bartlomiej Zolnierkiewicz @ 2017-12-01 17:22 UTC (permalink / raw)
To: Tomi Valkeinen
Cc: Mark Rutland, devicetree, linux-fbdev, letux-kernel, Julia Lawall,
David Airlie, H. Nikolaus Schaller, dri-devel, Russell King,
Rob Herring, linux-kernel, Tony Lindgren, Thierry Reding,
Laurent Pinchart, Benoît Cousson, kernel, linux-omap,
linux-arm-kernel
In-Reply-To: <27b12bc8-2c3a-6caa-c800-158b75f80d3f@ti.com>
On Thursday, November 30, 2017 12:54:07 PM Tomi Valkeinen wrote:
> On 28/11/17 17:48, H. Nikolaus Schaller wrote:
> > Changes V3:
> > * stay compatible with old DTB files which still use "toppoly" (suggested by Tomi Valkeinen)
> > * replaced MODULE_ALIAS entries by MODULE_DEVICE_TABLE (suggested by Andrew F. Davis)
> > * removed DSI VDDS patch as it has already been accepted
> >
> > 2017-11-16 09:50:22: Changes V2:
> > * replaced patch to fix DSI VDDS for OMAP3 by equivalent patch from Laurent Pinchart
> > * keep previous compatibility option in panel driver to handle older device tree binaries
> >
> > 2017-11-08 22:09:36:
> > This patch set fixes vendor names of the panels
> > and fixes a problem on omapdrm with enabling
> > VDD_DSI for OMAP3 which is needed for displaying
> > the Red and Green channel on OMAP3530 (Pandora).
> >
> > H. Nikolaus Schaller (4):
> > omapdrm: panel: fix compatible vendor string for td028ttec1
> > omapdrm: panel: td028ttec1: replace MODULE_ALIAS by
> > MODULE_DEVICE_TABLE
> > DTS: GTA04: fix panel compatibility string
> > DTS: Pandora: fix panel compatibility string
> >
> > .../panel/{toppoly,td028ttec1.txt => tpo,td028ttec1.txt} | 4 ++--
> > arch/arm/boot/dts/omap3-gta04.dtsi | 2 +-
> > arch/arm/boot/dts/omap3-pandora-common.dtsi | 2 +-
> > drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c | 13 ++++++++++++-
> > .../fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c | 12 +++++++++++-
> > 5 files changed, 27 insertions(+), 6 deletions(-)
> > rename Documentation/devicetree/bindings/display/panel/{toppoly,td028ttec1.txt => tpo,td028ttec1.txt} (84%)
> >
>
> Thanks. I have picked up patches 1 and 2.
Thanks for taking care of them (they both look fine to me).
> 3 can be applied when 1 & 2 are in. The change in 4 could be applied
> independently, but it conflicts with 3.
>
> Tony, how do you want to handle 3 and 4? I will push 1 and 2 to v4.16. I
> don't think they are real issues, so I don't see a reason to push them
> as fixes to v4.15. I think they are mostly just cleanups, and we might
> as well wait until v4.17, but that's quite far away...
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* [PATCH v10 6/6] clk: qcom: Add APCS clock controller support
From: Georgi Djakov @ 2017-12-01 17:02 UTC (permalink / raw)
To: sboyd, jassisinghbrar, bjorn.andersson, robh
Cc: mturquette, linux-clk, linux-kernel, linux-arm-msm, devicetree,
georgi.djakov
In-Reply-To: <20171201170224.25053-1-georgi.djakov@linaro.org>
Add a driver for the APCS clock controller. It is part of the APCS
hardware block, which among other things implements also a combined
mux and half integer divider functionality. It can choose between a
fixed-rate clock or the dedicated APCS (A53) PLL. The source and the
divider can be set both at the same time.
This is required for enabling CPU frequency scaling on MSM8916-based
platforms.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
drivers/clk/qcom/Kconfig | 11 +++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apcs-msm8916.c | 149 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 161 insertions(+)
create mode 100644 drivers/clk/qcom/apcs-msm8916.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 81ac7b9378fe..255023b439c9 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -22,6 +22,17 @@ config QCOM_A53PLL
Say Y if you want to support higher CPU frequencies on MSM8916
devices.
+config QCOM_CLK_APCS_MSM8916
+ bool "MSM8916 APCS Clock Controller"
+ depends on COMMON_CLK_QCOM
+ depends on QCOM_APCS_IPC
+ default ARCH_QCOM
+ help
+ Support for the APCS Clock Controller on msm8916 devices. The
+ APCS is managing the mux and divider which feeds the CPUs.
+ Say Y if you want to support CPU frequency scaling on devices
+ such as msm8916.
+
config QCOM_CLK_RPM
tristate "RPM based Clock Controller"
depends on COMMON_CLK_QCOM && MFD_QCOM_RPM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 7c51d877f967..0408cebf38d4 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -34,5 +34,6 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
+obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c
new file mode 100644
index 000000000000..f71039ff2347
--- /dev/null
+++ b/drivers/clk/qcom/apcs-msm8916.c
@@ -0,0 +1,149 @@
+/*
+ * Qualcomm APCS clock controller driver
+ *
+ * Copyright (c) 2017, Linaro Limited
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/mailbox_controller.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include "clk-regmap.h"
+#include "clk-regmap-mux-div.h"
+
+enum {
+ P_GPLL0,
+ P_A53PLL,
+};
+
+static const struct parent_map gpll0_a53cc_map[] = {
+ { P_GPLL0, 4 },
+ { P_A53PLL, 5 },
+};
+
+static const char * const gpll0_a53cc[] = {
+ "gpll0_vote",
+ "a53pll",
+};
+
+/*
+ * We use the notifier function for switching to a temporary safe configuration
+ * (mux and divider), while the A53 PLL is reconfigured.
+ */
+static int a53cc_notifier_cb(struct notifier_block *nb, unsigned long event,
+ void *data)
+{
+ int ret = 0;
+ struct clk_regmap_mux_div *md = container_of(nb,
+ struct clk_regmap_mux_div,
+ clk_nb);
+ if (event == PRE_RATE_CHANGE)
+ /* set the mux and divider to safe frequency (400mhz) */
+ ret = __mux_div_set_src_div(md, 4, 3);
+
+ return notifier_from_errno(ret);
+}
+
+static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
+{
+ struct device *dev = pdev->dev.parent;
+ struct device_node *np = dev->of_node;
+ struct clk_regmap_mux_div *a53cc;
+ struct regmap *regmap;
+ struct clk_init_data init = { };
+ int ret;
+
+ regmap = dev_get_regmap(dev, NULL);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+ dev_err(dev, "failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL);
+ if (!a53cc)
+ return -ENOMEM;
+
+ init.name = "a53mux";
+ init.parent_names = gpll0_a53cc;
+ init.num_parents = ARRAY_SIZE(gpll0_a53cc);
+ init.ops = &clk_regmap_mux_div_ops;
+ init.flags = CLK_SET_RATE_PARENT;
+
+ a53cc->clkr.hw.init = &init;
+ a53cc->clkr.regmap = regmap;
+ a53cc->reg_offset = 0x50;
+ a53cc->hid_width = 5;
+ a53cc->hid_shift = 0;
+ a53cc->src_width = 3;
+ a53cc->src_shift = 8;
+ a53cc->parent_map = gpll0_a53cc_map;
+
+ a53cc->pclk = devm_clk_get(dev, NULL);
+ if (IS_ERR(a53cc->pclk)) {
+ ret = PTR_ERR(a53cc->pclk);
+ dev_err(dev, "failed to get clk: %d\n", ret);
+ return ret;
+ }
+
+ a53cc->clk_nb.notifier_call = a53cc_notifier_cb;
+ ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb);
+ if (ret) {
+ dev_err(dev, "failed to register clock notifier: %d\n", ret);
+ return ret;
+ }
+
+ ret = devm_clk_register_regmap(dev, &a53cc->clkr);
+ if (ret) {
+ dev_err(dev, "failed to register regmap clock: %d\n", ret);
+ goto err;
+ }
+
+ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get,
+ &a53cc->clkr.hw);
+ if (ret) {
+ dev_err(dev, "failed to add clock provider: %d\n", ret);
+ goto err;
+ }
+
+ platform_set_drvdata(pdev, a53cc);
+
+ return 0;
+
+err:
+ clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
+ return ret;
+}
+
+static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev)
+{
+ struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev);
+
+ clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
+ of_clk_del_provider(pdev->dev.of_node);
+
+ return 0;
+}
+
+static struct platform_driver qcom_apcs_msm8916_clk_driver = {
+ .probe = qcom_apcs_msm8916_clk_probe,
+ .remove = qcom_apcs_msm8916_clk_remove,
+ .driver = {
+ .name = "qcom-apcs-msm8916-clk",
+ },
+};
+module_platform_driver(qcom_apcs_msm8916_clk_driver);
+
+MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Qualcomm MSM8916 APCS clock driver");
^ permalink raw reply related
* [PATCH v10 5/6] dt-bindings: mailbox: qcom: Document the APCS clock binding
From: Georgi Djakov @ 2017-12-01 17:02 UTC (permalink / raw)
To: sboyd, jassisinghbrar, bjorn.andersson, robh
Cc: mturquette, linux-clk, linux-kernel, linux-arm-msm, devicetree,
georgi.djakov
In-Reply-To: <20171201170224.25053-1-georgi.djakov@linaro.org>
Update the binding documentation for APCS to mention that the APCS
hardware block also expose a clock controller functionality.
The APCS clock controller is a mux and half-integer divider. It has the
main CPU PLL as an input and provides the clock for the application CPU.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
index fb961c310f44..16964f0c1773 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
@@ -15,12 +15,21 @@ platforms.
Usage: required
Value type: <prop-encoded-array>
Definition: must specify the base address and size of the global block
+- clocks:
+ Usage: required if #clocks-cells property is present
+ Value type: <phandle>
+ Definition: phandle to the input PLL, which feeds the APCS mux/divider
- #mbox-cells:
Usage: required
Value type: <u32>
Definition: as described in mailbox.txt, must be 1
+- #clock-cells:
+ Usage: optional
+ Value type: <u32>
+ Definition: as described in clock.txt, must be 0
+
= EXAMPLE
The following example describes the APCS HMSS found in MSM8996 and part of the
@@ -44,3 +53,12 @@ GLINK RPM referencing the "rpm_hlos" doorbell therein.
mbox-names = "rpm_hlos";
};
+Below is another example of the APCS binding on MSM8916 platforms:
+
+ apcs: mailbox@b011000 {
+ compatible = "qcom,msm8916-apcs-kpss-global";
+ reg = <0xb011000 0x1000>;
+ #mbox-cells = <1>;
+ clocks = <&a53pll>;
+ #clock-cells = <0>;
+ };
^ permalink raw reply related
* [PATCH v10 4/6] clk: qcom: Add regmap mux-div clocks support
From: Georgi Djakov @ 2017-12-01 17:02 UTC (permalink / raw)
To: sboyd, jassisinghbrar, bjorn.andersson, robh
Cc: mturquette, linux-clk, linux-kernel, linux-arm-msm, devicetree,
georgi.djakov
In-Reply-To: <20171201170224.25053-1-georgi.djakov@linaro.org>
Add support for hardware that can switch both parent clock and divider
at the same time. This avoids generating intermediate frequencies from
either the old parent clock and new divider or new parent clock and
old divider combinations.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-regmap-mux-div.c | 230 ++++++++++++++++++++++++++++++++++
drivers/clk/qcom/clk-regmap-mux-div.h | 47 +++++++
3 files changed, 278 insertions(+)
create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.c
create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.h
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index e767c60c24ec..7c51d877f967 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -10,6 +10,7 @@ clk-qcom-y += clk-rcg2.o
clk-qcom-y += clk-branch.o
clk-qcom-y += clk-regmap-divider.o
clk-qcom-y += clk-regmap-mux.o
+clk-qcom-y += clk-regmap-mux-div.o
clk-qcom-y += reset.o
clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
diff --git a/drivers/clk/qcom/clk-regmap-mux-div.c b/drivers/clk/qcom/clk-regmap-mux-div.c
new file mode 100644
index 000000000000..9885b8bc0890
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap-mux-div.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2017, Linaro Limited
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/regmap.h>
+
+#include "clk-regmap-mux-div.h"
+
+#define CMD_RCGR 0x0
+#define CMD_RCGR_UPDATE BIT(0)
+#define CMD_RCGR_DIRTY_CFG BIT(4)
+#define CMD_RCGR_ROOT_OFF BIT(31)
+#define CFG_RCGR 0x4
+
+#define to_clk_regmap_mux_div(_hw) \
+ container_of(to_clk_regmap(_hw), struct clk_regmap_mux_div, clkr)
+
+int __mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div)
+{
+ int ret, count;
+ u32 val, mask;
+ const char *name = clk_hw_get_name(&md->clkr.hw);
+
+ val = (div << md->hid_shift) | (src << md->src_shift);
+ mask = ((BIT(md->hid_width) - 1) << md->hid_shift) |
+ ((BIT(md->src_width) - 1) << md->src_shift);
+
+ ret = regmap_update_bits(md->clkr.regmap, CFG_RCGR + md->reg_offset,
+ mask, val);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(md->clkr.regmap, CMD_RCGR + md->reg_offset,
+ CMD_RCGR_UPDATE, CMD_RCGR_UPDATE);
+ if (ret)
+ return ret;
+
+ /* Wait for update to take effect */
+ for (count = 500; count > 0; count--) {
+ ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset,
+ &val);
+ if (ret)
+ return ret;
+ if (!(val & CMD_RCGR_UPDATE))
+ return 0;
+ udelay(1);
+ }
+
+ pr_err("%s: RCG did not update its configuration", name);
+ return -EBUSY;
+}
+
+static void __mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src,
+ u32 *div)
+{
+ u32 val, d, s;
+ const char *name = clk_hw_get_name(&md->clkr.hw);
+
+ regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val);
+
+ if (val & CMD_RCGR_DIRTY_CFG) {
+ pr_err("%s: RCG configuration is pending\n", name);
+ return;
+ }
+
+ regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val);
+ s = (val >> md->src_shift);
+ s &= BIT(md->src_width) - 1;
+ *src = s;
+
+ d = (val >> md->hid_shift);
+ d &= BIT(md->hid_width) - 1;
+ *div = d;
+}
+
+static inline bool is_better_rate(unsigned long req, unsigned long best,
+ unsigned long new)
+{
+ return (req <= new && new < best) || (best < req && best < new);
+}
+
+static int mux_div_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+ unsigned int i, div, max_div;
+ unsigned long actual_rate, best_rate = 0;
+ unsigned long req_rate = req->rate;
+
+ for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
+ struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
+ unsigned long parent_rate = clk_hw_get_rate(parent);
+
+ max_div = BIT(md->hid_width) - 1;
+ for (div = 1; div < max_div; div++) {
+ parent_rate = mult_frac(req_rate, div, 2);
+ parent_rate = clk_hw_round_rate(parent, parent_rate);
+ actual_rate = mult_frac(parent_rate, 2, div);
+
+ if (is_better_rate(req_rate, best_rate, actual_rate)) {
+ best_rate = actual_rate;
+ req->rate = best_rate;
+ req->best_parent_rate = parent_rate;
+ req->best_parent_hw = parent;
+ }
+
+ if (actual_rate < req_rate || best_rate <= req_rate)
+ break;
+ }
+ }
+
+ if (!best_rate)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate, u32 src)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+ int ret;
+ u32 div, max_div, best_src = 0, best_div = 0;
+ unsigned int i;
+ unsigned long actual_rate, best_rate = 0;
+
+ for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
+ struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
+ unsigned long parent_rate = clk_hw_get_rate(parent);
+
+ max_div = BIT(md->hid_width) - 1;
+ for (div = 1; div < max_div; div++) {
+ parent_rate = mult_frac(rate, div, 2);
+ parent_rate = clk_hw_round_rate(parent, parent_rate);
+ actual_rate = mult_frac(parent_rate, 2, div);
+
+ if (is_better_rate(rate, best_rate, actual_rate)) {
+ best_rate = actual_rate;
+ best_src = md->parent_map[i].cfg;
+ best_div = div - 1;
+ }
+
+ if (actual_rate < rate || best_rate <= rate)
+ break;
+ }
+ }
+
+ ret = __mux_div_set_src_div(md, best_src, best_div);
+ if (!ret) {
+ md->div = best_div;
+ md->src = best_src;
+ }
+
+ return ret;
+}
+
+static u8 mux_div_get_parent(struct clk_hw *hw)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+ const char *name = clk_hw_get_name(hw);
+ u32 i, div, src = 0;
+
+ __mux_div_get_src_div(md, &src, &div);
+
+ for (i = 0; i < clk_hw_get_num_parents(hw); i++)
+ if (src == md->parent_map[i].cfg)
+ return i;
+
+ pr_err("%s: Can't find parent with src %d\n", name, src);
+ return 0;
+}
+
+static int mux_div_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+
+ return __mux_div_set_src_div(md, md->parent_map[index].cfg, md->div);
+}
+
+static int mux_div_set_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long prate)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+
+ return __mux_div_set_rate_and_parent(hw, rate, prate, md->src);
+}
+
+static int mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate, u8 index)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+
+ return __mux_div_set_rate_and_parent(hw, rate, prate,
+ md->parent_map[index].cfg);
+}
+
+static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
+{
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
+ u32 div, src;
+ int i, num_parents = clk_hw_get_num_parents(hw);
+ const char *name = clk_hw_get_name(hw);
+
+ __mux_div_get_src_div(md, &src, &div);
+ for (i = 0; i < num_parents; i++)
+ if (src == md->parent_map[i].cfg) {
+ struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
+ unsigned long parent_rate = clk_hw_get_rate(p);
+
+ return mult_frac(parent_rate, 2, div + 1);
+ }
+
+ pr_err("%s: Can't find parent %d\n", name, src);
+ return 0;
+}
+
+const struct clk_ops clk_regmap_mux_div_ops = {
+ .get_parent = mux_div_get_parent,
+ .set_parent = mux_div_set_parent,
+ .set_rate = mux_div_set_rate,
+ .set_rate_and_parent = mux_div_set_rate_and_parent,
+ .determine_rate = mux_div_determine_rate,
+ .recalc_rate = mux_div_recalc_rate,
+};
diff --git a/drivers/clk/qcom/clk-regmap-mux-div.h b/drivers/clk/qcom/clk-regmap-mux-div.h
new file mode 100644
index 000000000000..6088f8f23f45
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap-mux-div.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2017, Linaro Limited
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QCOM_CLK_REGMAP_MUX_DIV_H__
+#define __QCOM_CLK_REGMAP_MUX_DIV_H__
+
+#include <linux/clk-provider.h>
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+
+/**
+ * struct mux_div_clk - combined mux/divider clock
+ * @reg_offset: offset of the mux/divider register
+ * @hid_width: number of bits in half integer divider
+ * @hid_shift: lowest bit of hid value field
+ * @src_width: number of bits in source select
+ * @src_shift: lowest bit of source select field
+ * @div: the divider raw configuration value
+ * @src: the mux index which will be used if the clock is enabled
+ * @parent_map: pointer to parent_map struct
+ * @clkr: handle between common and hardware-specific interfaces
+ * @pclk: the input PLL clock
+ * @clk_nb: clock notifier for rate changes of the input PLL
+ */
+
+struct clk_regmap_mux_div {
+ u32 reg_offset;
+ u32 hid_width;
+ u32 hid_shift;
+ u32 src_width;
+ u32 src_shift;
+ u32 div;
+ u32 src;
+ const struct parent_map *parent_map;
+ struct clk_regmap clkr;
+ struct clk *pclk;
+ struct notifier_block clk_nb;
+};
+
+extern const struct clk_ops clk_regmap_mux_div_ops;
+int __mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div);
+
+#endif
^ permalink raw reply related
* [PATCH v10 3/6] clk: qcom: Add A53 PLL support
From: Georgi Djakov @ 2017-12-01 17:02 UTC (permalink / raw)
To: sboyd, jassisinghbrar, bjorn.andersson, robh
Cc: mturquette, linux-clk, linux-kernel, linux-arm-msm, devicetree,
georgi.djakov
In-Reply-To: <20171201170224.25053-1-georgi.djakov@linaro.org>
The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs,
a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources
are connected to a mux and half-integer divider, which is feeding the
CPU cores.
This patch adds support for the primary CPU PLL which generates the
higher range of frequencies above 1GHz.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/clock/qcom,a53pll.txt | 22 +++++
drivers/clk/qcom/Kconfig | 10 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/a53-pll.c | 109 +++++++++++++++++++++
4 files changed, 142 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53pll.txt
create mode 100644 drivers/clk/qcom/a53-pll.c
diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.txt b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt
new file mode 100644
index 000000000000..e3fa8118eaee
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt
@@ -0,0 +1,22 @@
+Qualcomm MSM8916 A53 PLL Binding
+--------------------------------
+The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies
+above 1GHz.
+
+Required properties :
+- compatible : Shall contain only one of the following:
+
+ "qcom,msm8916-a53pll"
+
+- reg : shall contain base register location and length
+
+- #clock-cells : must be set to <0>
+
+Example:
+
+ a53pll: clock@b016000 {
+ compatible = "qcom,msm8916-a53pll";
+ reg = <0xb016000 0x40>;
+ #clock-cells = <0>;
+ };
+
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9f6c278deead..81ac7b9378fe 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -12,6 +12,16 @@ config COMMON_CLK_QCOM
select REGMAP_MMIO
select RESET_CONTROLLER
+config QCOM_A53PLL
+ bool "MSM8916 A53 PLL"
+ depends on COMMON_CLK_QCOM
+ default ARCH_QCOM
+ help
+ Support for the A53 PLL on MSM8916 devices. It provides
+ the CPU with frequencies above 1GHz.
+ Say Y if you want to support higher CPU frequencies on MSM8916
+ devices.
+
config QCOM_CLK_RPM
tristate "RPM based Clock Controller"
depends on COMMON_CLK_QCOM && MFD_QCOM_RPM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 26410d31446b..e767c60c24ec 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -32,5 +32,6 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
+obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c
new file mode 100644
index 000000000000..b2bb8e9437f1
--- /dev/null
+++ b/drivers/clk/qcom/a53-pll.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2017, Linaro Limited
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "clk-pll.h"
+#include "clk-regmap.h"
+
+static const struct pll_freq_tbl a53pll_freq[] = {
+ { 998400000, 52, 0x0, 0x1, 0 },
+ { 1094400000, 57, 0x0, 0x1, 0 },
+ { 1152000000, 62, 0x0, 0x1, 0 },
+ { 1209600000, 63, 0x0, 0x1, 0 },
+ { 1248000000, 65, 0x0, 0x1, 0 },
+ { 1363200000, 71, 0x0, 0x1, 0 },
+ { 1401600000, 73, 0x0, 0x1, 0 },
+};
+
+static const struct regmap_config a53pll_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x40,
+ .fast_io = true,
+};
+
+static int qcom_a53pll_remove(struct platform_device *pdev)
+{
+ of_clk_del_provider(pdev->dev.of_node);
+ return 0;
+}
+
+static int qcom_a53pll_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct regmap *regmap;
+ struct resource *res;
+ struct clk_pll *pll;
+ void __iomem *base;
+ struct clk_init_data init = { };
+ int ret;
+
+ pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ pll->l_reg = 0x04;
+ pll->m_reg = 0x08;
+ pll->n_reg = 0x0c;
+ pll->config_reg = 0x14;
+ pll->mode_reg = 0x00;
+ pll->status_reg = 0x1c;
+ pll->status_bit = 16;
+ pll->freq_tbl = a53pll_freq;
+
+ init.name = "a53pll";
+ init.parent_names = (const char *[]){ "xo" };
+ init.num_parents = 1;
+ init.ops = &clk_pll_sr2_ops;
+ init.flags = CLK_IS_CRITICAL;
+ pll->clkr.hw.init = &init;
+
+ ret = devm_clk_register_regmap(dev, &pll->clkr);
+ if (ret) {
+ dev_err(dev, "failed to register regmap clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
+ &pll->clkr.hw);
+ if (ret) {
+ dev_err(dev, "failed to add clock provider: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id qcom_a53pll_match_table[] = {
+ { .compatible = "qcom,msm8916-a53pll" },
+ { }
+};
+
+static struct platform_driver qcom_a53pll_driver = {
+ .probe = qcom_a53pll_probe,
+ .remove = qcom_a53pll_remove,
+ .driver = {
+ .name = "qcom-a53pll",
+ .of_match_table = qcom_a53pll_match_table,
+ },
+};
+
+builtin_platform_driver(qcom_a53pll_driver);
^ permalink raw reply related
* [PATCH v10 2/6] mailbox: qcom: Create APCS child device for clock controller
From: Georgi Djakov @ 2017-12-01 17:02 UTC (permalink / raw)
To: sboyd, jassisinghbrar, bjorn.andersson, robh
Cc: mturquette, linux-clk, linux-kernel, linux-arm-msm, devicetree,
georgi.djakov
In-Reply-To: <20171201170224.25053-1-georgi.djakov@linaro.org>
There is a clock controller functionality provided by the APCS hardware
block of msm8916 devices. The device-tree would represent an APCS node
with both mailbox and clock provider properties.
Create a platform child device for the clock controller functionality so
the driver can probe and use APCS as parent.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index ab344bc6fa63..57bde0dfd12f 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -29,6 +29,7 @@ struct qcom_apcs_ipc {
struct regmap *regmap;
unsigned long offset;
+ struct platform_device *clk;
};
static const struct regmap_config apcs_regmap_config = {
@@ -96,6 +97,14 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
return ret;
}
+ if (of_device_is_compatible(np, "qcom,msm8916-apcs-kpss-global")) {
+ apcs->clk = platform_device_register_data(&pdev->dev,
+ "qcom-apcs-msm8916-clk",
+ -1, NULL, 0);
+ if (IS_ERR(apcs->clk))
+ dev_err(&pdev->dev, "failed to register APCS clk\n");
+ }
+
platform_set_drvdata(pdev, apcs);
return 0;
@@ -104,8 +113,10 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
static int qcom_apcs_ipc_remove(struct platform_device *pdev)
{
struct qcom_apcs_ipc *apcs = platform_get_drvdata(pdev);
+ struct platform_device *clk = apcs->clk;
mbox_controller_unregister(&apcs->mbox);
+ platform_device_unregister(clk);
return 0;
}
^ permalink raw reply related
* [PATCH v10 1/6] mailbox: qcom: Convert APCS IPC driver to use regmap
From: Georgi Djakov @ 2017-12-01 17:02 UTC (permalink / raw)
To: sboyd, jassisinghbrar, bjorn.andersson, robh
Cc: mturquette, linux-clk, linux-kernel, linux-arm-msm, devicetree,
georgi.djakov
In-Reply-To: <20171201170224.25053-1-georgi.djakov@linaro.org>
This hardware block provides more functionalities that just IPC. Convert
it to regmap to allow other child platform devices to use the same regmap.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 24 +++++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 9924c6d7f05d..ab344bc6fa63 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -18,6 +18,7 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/mailbox_controller.h>
#define QCOM_APCS_IPC_BITS 32
@@ -26,19 +27,25 @@ struct qcom_apcs_ipc {
struct mbox_controller mbox;
struct mbox_chan mbox_chans[QCOM_APCS_IPC_BITS];
- void __iomem *reg;
+ struct regmap *regmap;
unsigned long offset;
};
+static const struct regmap_config apcs_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1000,
+ .fast_io = true,
+};
+
static int qcom_apcs_ipc_send_data(struct mbox_chan *chan, void *data)
{
struct qcom_apcs_ipc *apcs = container_of(chan->mbox,
struct qcom_apcs_ipc, mbox);
unsigned long idx = (unsigned long)chan->con_priv;
- writel(BIT(idx), apcs->reg);
-
- return 0;
+ return regmap_write(apcs->regmap, apcs->offset, BIT(idx));
}
static const struct mbox_chan_ops qcom_apcs_ipc_ops = {
@@ -47,7 +54,9 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = {
static int qcom_apcs_ipc_probe(struct platform_device *pdev)
{
+ struct device_node *np = pdev->dev.of_node;
struct qcom_apcs_ipc *apcs;
+ struct regmap *regmap;
struct resource *res;
unsigned long offset;
void __iomem *base;
@@ -63,9 +72,14 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
+ regmap = devm_regmap_init_mmio(&pdev->dev, base, &apcs_regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
offset = (unsigned long)of_device_get_match_data(&pdev->dev);
- apcs->reg = base + offset;
+ apcs->regmap = regmap;
+ apcs->offset = offset;
/* Initialize channel identifiers */
for (i = 0; i < ARRAY_SIZE(apcs->mbox_chans); i++)
^ permalink raw reply related
* [PATCH v10 0/6] Add support for Qualcomm A53 CPU clock
From: Georgi Djakov @ 2017-12-01 17:02 UTC (permalink / raw)
To: sboyd, jassisinghbrar, bjorn.andersson, robh
Cc: mturquette, linux-clk, linux-kernel, linux-arm-msm, devicetree,
georgi.djakov
This patchset adds support for the A53 CPU clock on MSM8916 platforms
and allows scaling of the CPU frequency on msm8916 based platforms.
Changes since v9 (https://lkml.org/lkml/2017/9/21/511)
* Added the clock properties to the APCS DT node, instead of adding a subnode
and also replaced patch "mailbox: qcom: Populate APCS child platform devices"
with "mailbox: qcom: Create APCS child device for clock controller".
* Dropped patch "mailbox: qcom: Move the apcs struct into a separate header",
and use dev_get_regmap(dev->parent) in the child driver.
* Addressed Bjorn's comments on a53-pll and apcs-clk drivers.
* Added SPDX copyright identifiers.
Changes since v8 (https://lkml.org/lkml/2017/6/23/476)
* Converted APCS mailbox driver to use regmap and to populate child
platform devices that will handle the rest of the functionality
provided by APCS block.
* Picked Rob's Ack for the PLL binding.
* Changed the APCS binding and put it into a separate patch.
* Addressed review comments.
* Minor changes.
Changes since v7 (https://lkml.org/lkml/2016/10/31/296)
* Add the APCS clock controller to the APCS driver to expose both the
mailbox and clock controller functionality as discussed earlier:
https://lkml.org/lkml/2016/11/14/860
* Changed the a53pll compatible string as suggested by Rob.
Changes since v6 (https://lkml.org/lkml/2016/9/7/347)
* Addressed various comments from Stephen Boyd
Changes since v5 (https://lkml.org/lkml/2016/2/1/407)
* Rebase to clk-next and update according to the recent API changes.
Changes since v4 (https://lkml.org/lkml/2015/12/14/367)
* Convert to builtin drivers as now __clk_lookup() is used
Changes since v3 (https://lkml.org/lkml/2015/8/12/585)
* Split driver into two parts - and separate A53 PLL and
A53 clock controller drivers.
* Drop the safe switch hook patch. Add a clock notifier in
the clock provider to handle switching via safe mux and
divider configuration.
Changes since v2 (https://lkml.org/lkml/2015/7/24/526)
* Drop gpll0_vote patch.
* Switch to the new clk_hw_* APIs.
* Rebase to the current clk-next.
Changes since v1 (https://lkml.org/lkml/2015/6/12/193)
* Drop SR2 PLL patch, as it is already applied.
* Add gpll0_vote rate propagation patch.
* Update/rebase patches to the current clk-next.
Georgi Djakov (6):
mailbox: qcom: Convert APCS IPC driver to use regmap
mailbox: qcom: Create APCS child device for clock controller
clk: qcom: Add A53 PLL support
clk: qcom: Add regmap mux-div clocks support
dt-bindings: mailbox: qcom: Document the APCS clock binding
clk: qcom: Add APCS clock controller support
.../devicetree/bindings/clock/qcom,a53pll.txt | 22 ++
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 18 ++
drivers/clk/qcom/Kconfig | 21 ++
drivers/clk/qcom/Makefile | 3 +
drivers/clk/qcom/a53-pll.c | 109 ++++++++++
drivers/clk/qcom/apcs-msm8916.c | 149 +++++++++++++
drivers/clk/qcom/clk-regmap-mux-div.c | 230 +++++++++++++++++++++
drivers/clk/qcom/clk-regmap-mux-div.h | 47 +++++
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 35 +++-
9 files changed, 629 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53pll.txt
create mode 100644 drivers/clk/qcom/a53-pll.c
create mode 100644 drivers/clk/qcom/apcs-msm8916.c
create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.c
create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.h
^ permalink raw reply
* Re: [PATCH v3 3/3] arm64: dts: meson-axg: add clock DT info for Meson AXG SoC
From: Jerome Brunet @ 2017-12-01 16:59 UTC (permalink / raw)
To: Stephen Boyd, Yixun Lan
Cc: Neil Armstrong, Kevin Hilman, Rob Herring, Mark Rutland,
Michael Turquette, Carlo Caione, Qiufang Dai, linux-amlogic,
devicetree, linux-clk, linux-arm-kernel, linux-kernel
In-Reply-To: <20171201163437.GE19419@codeaurora.org>
On Fri, 2017-12-01 at 08:34 -0800, Stephen Boyd wrote:
> On 11/30, Yixun Lan wrote:
> > Hi Stephen
> >
> > On 11/30/17 03:35, Stephen Boyd wrote:
> > > On 11/28, Yixun Lan wrote:
> > > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> > > > b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> > > > index b932a784b02a..36a2e98338a8 100644
> > > > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> > > > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> > > > @@ -7,6 +7,7 @@
> > > > #include <dt-bindings/gpio/gpio.h>
> > > > #include <dt-bindings/interrupt-controller/irq.h>
> > > > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > +#include <dt-bindings/clock/axg-clkc.h>
> > > >
> > > > / {
> > > > compatible = "amlogic,meson-axg";
> > > > @@ -148,6 +149,20 @@
> > > > #address-cells = <0>;
> > > > };
> > > >
> > > > + hiubus: hiubus@ff63c000 {
> > >
> > > Maybe just call the node "bus@ff63c000"?
> > >
> >
> > isn't this just a name? what's the benefits to change?
> > personally, I tend to keep it this way, because it's better map to the
> > data sheet
> >
> > we also has 'aobus', 'cbus' scattered there..
>
> Per the ePAPR node names are supposed to be generic, like disk,
> cpu, display-controller, gpu, etc. I've never heard of a hiubus,
> so probably it's some vendor specific thing? We have the phandle
> anyway so it's not like we're losing much information here.
Stephen, there is a lot of busses on platform. We can't just call them all
'bus'.
I don't get the problem with this name.
We are re-using the name from the datasheet here, no fancy invention. It seems
to be quite common.
>
^ permalink raw reply
* Re: [PATCH v3 2/3] clk: meson-axg: add clock controller drivers
From: Stephen Boyd @ 2017-12-01 16:39 UTC (permalink / raw)
To: Yixun Lan
Cc: Neil Armstrong, Jerome Brunet, Kevin Hilman, Rob Herring,
Mark Rutland, Michael Turquette, Carlo Caione, Qiufang Dai,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <d2b58c06-93dc-4368-501e-4b8bdc9a4c34-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
On 11/30, Yixun Lan wrote:
> Hi Stephen
>
> On 11/30/17 03:34, Stephen Boyd wrote:
> > On 11/28, Yixun Lan wrote:
> >> diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
> >> new file mode 100644
> >> index 000000000000..51c5b4062715
> >> --- /dev/null
> >> +++ b/drivers/clk/meson/axg.c
> >> @@ -0,0 +1,948 @@
> >> +/*
> >> + * AmLogic Meson-AXG Clock Controller Driver
> >> + *
> >> + * Copyright (c) 2016 Baylibre SAS.
> >> + * Author: Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> >> + *
> >> + * Copyright (c) 2017 Amlogic, inc.
> >> + * Author: Qiufang Dai <qiufang.dai-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
> >> + *
> >> + * SPDX-License-Identifier: GPL-2.0+
> >> + */
> >> +
> >> +#include <linux/clk.h>
> >> +#include <linux/clk-provider.h>
> >> +#include <linux/of_address.h>
> >> +#include <linux/of_device.h>
> >> +#include <linux/platform_device.h>
> >> +#include <linux/init.h>
> >> +
> >> +#include "clkc.h"
> >> +#include "axg.h"
> >> +
> >> +static DEFINE_SPINLOCK(clk_lock);
> >
> > meson_axg_clk_lock?
> >
> em... I'd leave it unchanged
>
> because the spinlock will be used at macro MESON_GATE() [1] which
> defined at drivers/clk/meson/clkc.h, and it assume using the generic
> name 'clk_lock', change name will break the code..
>
> and besides it's already defined as static, so I see no problem here
The problem is lockdep debugging and ctags/grep on the source
code. clk_lock is very generic when it should be more specific so
we can find this lock later on from a lockdep report with a
simple search of the code.
Maybe make another patch to rename it to meson_clk_lock so the
macro doesn't have to change too much, and we get it slightly
more unique. Looks like v4l2 also has a clk_lock.
>
> >> +};
> >> +
> >> +static int axg_clkc_probe(struct platform_device *pdev)
> >> +{
> >> + const struct clkc_data *clkc_data;
> >> + void __iomem *clk_base;
> >> + int ret, clkid, i;
> >> + struct device *dev = &pdev->dev;
> >> +
> >> + clkc_data = of_device_get_match_data(&pdev->dev);
> >> + if (!clkc_data)
> >> + return -EINVAL;
> >> +
> >> + /* Generic clocks and PLLs */
> >> + clk_base = of_iomap(dev->of_node, 0);
> >
> > Use platform device APIs for ioremapping?
> >
> I assume you are referring to 'platform_get_resource +
> devm_ioremap_resource' ?
>
> the idea sounds good to me.
Yes.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply
* [PATCH 2/2] serial: stm32: fix name conflict with 8250
From: Ludovic Barre @ 2017-12-01 16:36 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring
Cc: Maxime Coquelin, Alexandre Torgue, linux-serial, linux-kernel,
linux-arm-kernel, devicetree, Ludovic Barre
In-Reply-To: <1512146211-29086-1-git-send-email-ludovic.Barre@st.com>
From: Ludovic Barre <ludovic.barre@st.com>
This patch replaces stm32 tty name ttyS by ttySTM
to avoid a name conflict when Serial: 8250/16550 driver
is activated.
sysfs: cannot create duplicate filename '/class/tty/ttyS3'
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.14.0-12903-gb392521-dirty #1
[<c03118dc>] (unwind_backtrace) from [<c030c950>] (show_stack+0x10/0x14)
[<c030c950>] (show_stack) from [<c0d31e18>] (dump_stack+0x90/0xa4)
[<c0d31e18>] (dump_stack) from [<c03430a0>] (__warn+0xf8/0x110)
[<c03430a0>] (__warn) from [<c03430f0>] (warn_slowpath_fmt+0x38/0x48)
[<c03430f0>] (warn_slowpath_fmt) from [<c04ce574>] (sysfs_warn_dup+0x68/0x78)
[<c04ce574>] (sysfs_warn_dup) from [<c04ce824>] (sysfs_do_create_link_sd+0xb4/0xc4)
[<c04ce824>] (sysfs_do_create_link_sd) from [<c08c60ec>] (device_add+0x204/0x574)
[<c08c60ec>] (device_add) from [<c07a7ddc>] (tty_register_device_attr+0xc8/0x1bc)
[<c07a7ddc>] (tty_register_device_attr) from [<c07c6530>] (uart_add_one_port+0x22c/0x4f4)
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
drivers/tty/serial/stm32-usart.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index 8a5ff54..2294d0f 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -236,7 +236,7 @@ struct stm32_usart_info stm32h7_info = {
#define USART_ICR_CMCF BIT(17) /* F7 */
#define USART_ICR_WUCF BIT(20) /* H7 */
-#define STM32_SERIAL_NAME "ttyS"
+#define STM32_SERIAL_NAME "ttySTM"
#define STM32_MAX_PORTS 8
#define RX_BUF_L 200 /* dma rx buffer length */
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] serial: stm32: add default console
From: Ludovic Barre @ 2017-12-01 16:36 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring
Cc: devicetree, Alexandre Torgue, linux-kernel, Ludovic Barre,
Maxime Coquelin, linux-serial, linux-arm-kernel
In-Reply-To: <1512146211-29086-1-git-send-email-ludovic.Barre@st.com>
From: Ludovic Barre <ludovic.barre@st.com>
This patch adds by default the console support
on stm32.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
drivers/tty/serial/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index b788fee..969e598 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1664,6 +1664,7 @@ config SERIAL_STM32_CONSOLE
bool "Support for console on STM32"
depends on SERIAL_STM32=y
select SERIAL_CORE_CONSOLE
+ default y
config SERIAL_MVEBU_UART
bool "Marvell EBU serial port support"
--
2.7.4
^ permalink raw reply related
* [PATCH 0/2] serial: stm32: fix name conflict
From: Ludovic Barre @ 2017-12-01 16:36 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring
Cc: Maxime Coquelin, Alexandre Torgue, linux-serial, linux-kernel,
linux-arm-kernel, devicetree, Ludovic Barre
From: Ludovic Barre <ludovic.barre@st.com>
This patch series:
-fix name conflict, when both driver 8250/stm32-usart
are activated. Replace stm32 tty name "ttyS" by "ttySTM".
-by default add stm32 console when SERIAL_STM32 is selected.
Ludovic Barre (2):
serial: stm32: add default console
serial: stm32: fix name conflict with 8250
drivers/tty/serial/Kconfig | 1 +
drivers/tty/serial/stm32-usart.h | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
--
2.7.4
^ permalink raw reply
* Re: [PATCH v3 3/3] arm64: dts: meson-axg: add clock DT info for Meson AXG SoC
From: Stephen Boyd @ 2017-12-01 16:34 UTC (permalink / raw)
To: Yixun Lan
Cc: Neil Armstrong, Jerome Brunet, Kevin Hilman, Rob Herring,
Mark Rutland, Michael Turquette, Carlo Caione, Qiufang Dai,
linux-amlogic, devicetree, linux-clk, linux-arm-kernel,
linux-kernel
In-Reply-To: <8353c264-3253-0268-91fc-8d42fbe82611@amlogic.com>
On 11/30, Yixun Lan wrote:
> Hi Stephen
>
> On 11/30/17 03:35, Stephen Boyd wrote:
> > On 11/28, Yixun Lan wrote:
> >> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> >> index b932a784b02a..36a2e98338a8 100644
> >> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> >> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> >> @@ -7,6 +7,7 @@
> >> #include <dt-bindings/gpio/gpio.h>
> >> #include <dt-bindings/interrupt-controller/irq.h>
> >> #include <dt-bindings/interrupt-controller/arm-gic.h>
> >> +#include <dt-bindings/clock/axg-clkc.h>
> >>
> >> / {
> >> compatible = "amlogic,meson-axg";
> >> @@ -148,6 +149,20 @@
> >> #address-cells = <0>;
> >> };
> >>
> >> + hiubus: hiubus@ff63c000 {
> >
> > Maybe just call the node "bus@ff63c000"?
> >
> isn't this just a name? what's the benefits to change?
> personally, I tend to keep it this way, because it's better map to the
> data sheet
>
> we also has 'aobus', 'cbus' scattered there..
Per the ePAPR node names are supposed to be generic, like disk,
cpu, display-controller, gpu, etc. I've never heard of a hiubus,
so probably it's some vendor specific thing? We have the phandle
anyway so it's not like we're losing much information here.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] arm64: dts: allwinner: a64: bananapi-m64: Add LED device node
From: Chen-Yu Tsai @ 2017-12-01 16:27 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
The Bananapi-M64 has 3 LEDS in red, green, and blue. These are toggled
via GPIO lines, which drive transistors that control current across the
LEDS. The red LED is by default on, via an additional pull-up on the
control line. We consider this means that it is a power indicator.
So we set the "default-on" property for it.
The pingroups the GPIO lines belong to require external regulators be
enabled to be able to drive the GPIO high. These regulators also have
other purposes. However the pin controller does not have bindings for
regulators. Here we just set them to always-on.
Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 36 ++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index 4a8d3f83a36e..a6975670cd1c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -60,6 +60,26 @@
stdout-path = "serial0:115200n8";
};
+ leds {
+ compatible = "gpio-leds";
+
+ pwr-led {
+ label = "bananapi-m64:red:pwr";
+ gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ default-state = "on";
+ };
+
+ green {
+ label = "bananapi-m64:green:user";
+ gpios = <&pio 4 14 GPIO_ACTIVE_HIGH>; /* PE14 */
+ };
+
+ blue {
+ label = "bananapi-m64:blue:user";
+ gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */
+ };
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
@@ -153,6 +173,17 @@
#include "axp803.dtsi"
+®_aldo1 {
+ /*
+ * This regulator also drives the PE pingroup GPIOs,
+ * which also controls two LEDs.
+ */
+ regulator-always-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "afvcc-csi";
+};
+
®_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
@@ -168,6 +199,11 @@
};
®_dc1sw {
+ /*
+ * This regulator also indirectly drives the PD pingroup GPIOs,
+ * which also controls the power LED.
+ */
+ regulator-always-on;
regulator-name = "vcc-phy";
};
--
2.15.0
^ permalink raw reply related
* Re: [PATCH 3/5] PCI: cadence: Add host driver for Cadence PCIe controller
From: Lorenzo Pieralisi @ 2017-12-01 16:20 UTC (permalink / raw)
To: Cyrille Pitchen
Cc: Bjorn Helgaas, bhelgaas-hpIqsD4AKlfQT0dZR+AlfA,
kishon-l0cyMroinI0, linux-pci-u79uwXL29TY76Z2rM5mHXA,
adouglas-vna1KIf7WgpBDgjK7y7TUQ, stelford-vna1KIf7WgpBDgjK7y7TUQ,
dgary-vna1KIf7WgpBDgjK7y7TUQ, kgopi-vna1KIf7WgpBDgjK7y7TUQ,
eandrews-vna1KIf7WgpBDgjK7y7TUQ,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
sureshp-vna1KIf7WgpBDgjK7y7TUQ, nsekhar-l0cyMroinI0,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <c6a0d70d-d584-2db8-f862-0c3ddbf6939d-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Fri, Dec 01, 2017 at 11:37:49AM +0100, Cyrille Pitchen wrote:
> Hi Bjorn,
>
> Le 28/11/2017 à 21:41, Bjorn Helgaas a écrit :
> > On Thu, Nov 23, 2017 at 04:01:48PM +0100, Cyrille Pitchen wrote:
> >> This patch adds support to the Cadence PCIe controller in host mode.
> >>
> >> Signed-off-by: Cyrille Pitchen <cyrille.pitchen-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> >> ---
> >> drivers/Makefile | 1 +
> >> drivers/pci/Kconfig | 1 +
> >> drivers/pci/cadence/Kconfig | 24 ++
> >> drivers/pci/cadence/Makefile | 2 +
> >> drivers/pci/cadence/pcie-cadence-host.c | 425 ++++++++++++++++++++++++++++++++
> >> drivers/pci/cadence/pcie-cadence.c | 110 +++++++++
> >> drivers/pci/cadence/pcie-cadence.h | 325 ++++++++++++++++++++++++
> >> 7 files changed, 888 insertions(+)
> >> create mode 100644 drivers/pci/cadence/Kconfig
> >> create mode 100644 drivers/pci/cadence/Makefile
> >> create mode 100644 drivers/pci/cadence/pcie-cadence-host.c
> >> create mode 100644 drivers/pci/cadence/pcie-cadence.c
> >> create mode 100644 drivers/pci/cadence/pcie-cadence.h
> >
> > I prefer a single file per driver. I assume you're anticipating
> > something like dwc, where the DesignWare core is incorporated into
> > several devices in slightly different ways. But it doesn't look like
> > that's here yet, and personally, I'd rather split out the required
> > things when they actually become required, not ahead of time.
> >
>
> The source code in pcie-cadence.c is shared between pcie-cadence-host.c
> (Root Complex mode) and pcie-cadence-ep.c (Endpoint mode), the second
> driver of this series.
>
> Taking other comments into accounts, I will move endpoint only related
> stuff in the pcie-cadence.{c,h} files from this patch to the endpoint
> patch.
>
> Otherwise your right, I expect this Cadence PCIe core to be embedded inside
> several vendor SoCs but I thought I could handle this as much as possible
> using mainly DT properties and/or the 'struct cdns_pcie_*_data' associated
> to the DT 'compatible' strings. We will have to wait for those SoCs to be
> released to know whether these two solutions are enough or if we will need
> dedicated files anyway.
>
> >> diff --git a/drivers/Makefile b/drivers/Makefile
> >> index 1d034b680431..27bdd98784d9 100644
> >> --- a/drivers/Makefile
> >> +++ b/drivers/Makefile
> >> @@ -18,6 +18,7 @@ obj-y += pwm/
> >>
> >> obj-$(CONFIG_PCI) += pci/
> >> obj-$(CONFIG_PCI_ENDPOINT) += pci/endpoint/
> >> +obj-$(CONFIG_PCI_CADENCE) += pci/cadence/
> >
> > I can't remember why we added CONFIG_PCI_ENDPOINT here instead of in
> > drivers/pci/Makefile. Is there any way to move both CONFIG_PCI_ENDPOINT
> > and CONFIG_PCI_CADENCE into drivers/pci/Makefile so this is better
> > encapsulated?
> >
>
> I will work on the solution I have proposed in another reply since it seems
> to be OK for you :)
>
> >> # PCI dwc controller drivers
> >> obj-y += pci/dwc/
> >> ...
> >
> >> + * struct cdns_pcie_rc_data - hardware specific data
> >
> > "cdns" is a weird abbreviation for "Cadence", since "Cadence" doesn't
> > contain an "s".
> >
> >> ...
> >> +static int cdns_pcie_parse_request_of_pci_ranges(struct device *dev,
> >> + struct list_head *resources,
> >> + struct resource **bus_range)
> >> +{
> >> + int err, res_valid = 0;
> >> + struct device_node *np = dev->of_node;
> >> + resource_size_t iobase;
> >> + struct resource_entry *win, *tmp;
> >> +
> >> + err = of_pci_get_host_bridge_resources(np, 0, 0xff, resources, &iobase);
> >> + if (err)
> >> + return err;
> >> +
> >> + err = devm_request_pci_bus_resources(dev, resources);
> >> + if (err)
> >> + return err;
> >> +
> >> + resource_list_for_each_entry_safe(win, tmp, resources) {
> >> + struct resource *res = win->res;
> >> +
> >> + switch (resource_type(res)) {
> >> + case IORESOURCE_IO:
> >> + err = pci_remap_iospace(res, iobase);
> >> + if (err) {
> >> + dev_warn(dev, "error %d: failed to map resource %pR\n",
> >> + err, res);
> >> + resource_list_destroy_entry(win);
> >> + }
> >> + break;
> >> + case IORESOURCE_MEM:
> >> + res_valid |= !(res->flags & IORESOURCE_PREFETCH);
> >> + break;
> >> + case IORESOURCE_BUS:
> >> + *bus_range = res;
> >> + break;
> >> + }
> >> + }
> >> +
> >> + if (res_valid)
> >> + return 0;
> >> +
> >> + dev_err(dev, "non-prefetchable memory resource required\n");
> >> + return -EINVAL;
> >> +}
> >
> > The code above is starting to look awfully familiar. I wonder if it's
> > time to think about some PCI-internal interface that can encapsulate
> > this. In this case, there's really nothing Cadence-specific here.
> > There are other callers where there *is* vendor-specific code, but
> > possibly that could be handled by returning pointers to bus number,
> > I/O port, and MMIO resources so the caller could do the
> > vendor-specific stuff?
> >
> > Bjorn
> >
>
> I am listing:
> - gen_pci_parse_request_of_pci_ranges() [1]
> - cdns_pcie_parse_request_of_pci_ranges() - same as [1]
> - advk_pcie_parse_request_of_pci_ranges()
> - altera_pcie_parse_request_of_pci_ranges()
> - versatile_pci_parse_request_of_pci_ranges()
> - rcar_pcie_parse_request_of_pci_ranges()
>
> Then what about doing something like that:
>
> ---8<--------------------------------------------------------------------------
> diff --git a/drivers/pci/host/pci-host-common.c b/drivers/pci/host/pci-host-common.c
> index 44a47d4f0b8f..2413c5d83cbd 100644
> --- a/drivers/pci/host/pci-host-common.c
> +++ b/drivers/pci/host/pci-host-common.c
> @@ -24,10 +24,19 @@
> #include <linux/pci-ecam.h>
> #include <linux/platform_device.h>
>
> -static int gen_pci_parse_request_of_pci_ranges(struct device *dev,
> - struct list_head *resources, struct resource **bus_range)
> +struct pci_host_resource_parser {
> + int (*get_resource)(void *userdata, struct resource_entry *win,
> + resource_size_t iobase);
> + int (*finalize)(void *userdata);
> + void (*abort)(void *userdata);
> +};
> +
> +int pci_host_parse_request_of_pci_ranges(struct device *dev,
> + struct list_head *resources,
> + const struct pci_host_resource_parser *parser,
> + void *userdata)
> {
> - int err, res_valid = 0;
> + int err;
> struct device_node *np = dev->of_node;
> resource_size_t iobase;
> struct resource_entry *win, *tmp;
> @@ -40,34 +49,94 @@ static int gen_pci_parse_request_of_pci_ranges(struct device *dev,
> if (err)
> return err;
>
> - resource_list_for_each_entry_safe(win, tmp, resources) {
> - struct resource *res = win->res;
> -
> - switch (resource_type(res)) {
> - case IORESOURCE_IO:
> - err = pci_remap_iospace(res, iobase);
> - if (err) {
> - dev_warn(dev, "error %d: failed to map resource %pR\n",
> - err, res);
> - resource_list_destroy_entry(win);
> - }
> - break;
> - case IORESOURCE_MEM:
> - res_valid |= !(res->flags & IORESOURCE_PREFETCH);
> - break;
> - case IORESOURCE_BUS:
> - *bus_range = res;
> - break;
> + if (parser && parser->get_resource) {
> + resource_list_for_each_entry_safe(win, tmp, resources) {
> + err = parser->get_resource(userdata, win, iobase);
> + if (err)
> + goto do_abort;
> + }
> + }
> +
> + if (parser && parser->finalize)
> + return parser->finalize(userdata);
> +
> + return 0;
> +
> + do_abort:
> + if (parser && parser->abort)
> + parser->abort(userdata);
> +
> + return err;
> +}
> +EXPORT_SYMBOL_GPL(pci_host_parse_request_of_pci_ranges);
> +
> +
> +struct gen_pci_parser_context {
> + struct device *dev;
> + struct resource **bus_range;
> + int res_valid;
> +};
> +
> +static int gen_pci_resource_parser_get_resource(void *userdata,
> + struct resource_entry *win,
> + resource_size_t iobase)
> +{
> + struct gen_pci_parser_context *ctx = userdata;
> + struct device *dev = ctx->dev;
> + struct resource *res = win->res;
> + int err;
> +
> + switch (resource_type(res)) {
> + case IORESOURCE_IO:
> + err = pci_remap_iospace(res, iobase);
> + if (err) {
> + dev_warn(dev, "error %d: failed to map resource %pR\n",
> + err, res);
> + resource_list_destroy_entry(win);
> }
> + break;
> + case IORESOURCE_MEM:
> + ctx->res_valid |= !(res->flags & IORESOURCE_PREFETCH);
> + break;
> + case IORESOURCE_BUS:
> + *ctx->bus_range = res;
> + break;
> }
>
> - if (res_valid)
> + return 0;
> +}
> +
> +static int gen_pci_resource_parser_finalize(void *userdata)
> +{
> + struct gen_pci_parser_context *ctx = userdata;
> + struct device *dev = ctx->dev;
> +
> + if (ctx->res_valid)
> return 0;
>
> dev_err(dev, "non-prefetchable memory resource required\n");
> return -EINVAL;
> }
>
> +static const struct pci_host_resource_parser gen_pci_resource_parser = {
> + .get_resource = gen_pci_resource_parser_get_resource,
> + .finalize = gen_pci_resource_parser_finalize,
> +};
> +
> +static int gen_pci_parse_request_of_pci_ranges(struct device *dev,
> + struct list_head *resources, struct resource **bus_range)
> +{
> + struct gen_pci_parser_context ctx;
> +
> + ctx.dev = dev;
> + ctx.bus_range = bus_range;
> + ctx.res_valid = 0;
> +
> + return pci_host_parse_request_of_pci_ranges(dev, resources,
> + &gen_pci_resource_parser,
> + &ctx);
> +}
I think that what you are doing is something along the lines:
acpi_dev_get_resources()
and the struct res_proc_context but maybe we can do something
simpler to start with.
We can go through the resource list twice in every driver, once through
the generic function that we are creating - that embeds code common
across bridges - to be clear something like:
static int of_pci_parse_request_pci_resources(struct device *dev,
struct list_head *res)
{
int err, res_valid;
resource_size_t iobase;
struct device_node *np = dev->of_node;
struct resource_entry *win, *tmp;
err = of_pci_get_host_bridge_resources(np, 0, 0xff, res, &iobase);
if (err)
return err;
err = devm_request_pci_bus_resources(dev, res);
if (err)
goto out_release_res;
resource_list_for_each_entry_safe(win, tmp, res) {
struct resource *res = win->res;
switch (resource_type(res)) {
case IORESOURCE_IO:
err = pci_remap_iospace(res, iobase);
if (err) {
dev_warn(dev, "error %d: failed to map resource %pR\n",
err, res);
resource_list_destroy_entry(win);
}
break;
case IORESOURCE_MEM:
res_valid |= !(res->flags & IORESOURCE_PREFETCH);
break;
}
}
if (res_valid)
return 0;
dev_err(dev, "non-prefetchable memory resource required\n");
err = -EINVAL;
out_release_res:
pci_free_resource_list(res);
return err;
}
and then in a PCI host bridge specific loop that just carries
out the host bridge specific actions for every resource returned
in the res list.
Lorenzo
> +
> static void gen_pci_unmap_cfg(void *ptr)
> {
> pci_ecam_free((struct pci_config_window *)ptr);
> ---8<--------------------------------------------------------------------------
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* [PATCH 1/3] drm/panel: Add DT bindings for Ilitek ILI9322
From: Linus Walleij @ 2017-12-01 16:16 UTC (permalink / raw)
To: Thierry Reding, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Linus Walleij, David Lechner, Stefano Babic, Ben Dooks,
devicetree-u79uwXL29TY76Z2rM5mHXA
This adds device tree bindings for the Ilitek ILI9322
320x240 TFT panel driver.
Cc: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
Cc: Stefano Babic <sbabic-ynQEQJNshbs@public.gmane.org>
Cc: Ben Dooks <ben.dooks-4yDnlxn2s6sWdaTGBSpHTA@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
ChangeLog v1->v2:
- Add explicit requirement to specify the system type so the
driver can look up the display configuration from the
compatible string.
- Dropped all display-specific configuration data I could
in favor of open coding it all in a per-system config struct
in the driver.
- Now only regulators and GPIO lines remain as DT resources.
---
.../bindings/display/panel/ilitek,ili9322.txt | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/ilitek,ili9322.txt
diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9322.txt b/Documentation/devicetree/bindings/display/panel/ilitek,ili9322.txt
new file mode 100644
index 000000000000..3d5ce6ad6ec7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9322.txt
@@ -0,0 +1,49 @@
+Ilitek ILI9322 TFT panel driver with SPI control bus
+
+This is a driver for 320x240 TFT panels, accepting a variety of input
+streams that get adapted and scaled to the panel. The panel output has
+960 TFT source driver pins and 240 TFT gate driver pins, VCOM, VCOML and
+VCOMH outputs.
+
+Required properties:
+ - compatible: "dlink,dir-685-panel", "ilitek,ili9322"
+ (full system-specific compatible is always required to look up configuration)
+ - reg: address of the panel on the SPI bus
+
+Optional properties:
+ - vcc-supply: core voltage supply, see regulator/regulator.txt
+ - iovcc-supply: voltage supply for the interface input/output signals,
+ see regulator/regulator.txt
+ - vci-supply: voltage supply for analog parts, see regulator/regulator.txt
+ - reset-gpios: a GPIO spec for the reset pin, see gpio/gpio.txt
+
+ The following optional properties only apply to RGB and YUV input modes and
+ can be omitted for BT.656 input modes:
+
+ - pixelclk-active: see display/panel/display-timing.txt
+ - de-active: see display/panel/display-timing.txt
+ - hsync-active: see display/panel/display-timing.txt
+ - vsync-active: see display/panel/display-timing.txt
+
+The panel must obey the rules for a SPI slave device as specified in
+spi/spi-bus.txt
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
+
+Example:
+
+panel: display@0 {
+ compatible = "dlink,dir-685-panel", "ilitek,ili9322";
+ reg = <0>;
+ vcc-supply = <&vdisp>;
+ iovcc-supply = <&vdisp>;
+ vci-supply = <&vdisp>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+};
--
2.14.3
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^ permalink raw reply related
* Re: [PATCH 2/2] arm64: allwinner: a64-sopine: Use dcdc1 regulator instead of vcc3v3
From: Maxime Ripard @ 2017-12-01 16:03 UTC (permalink / raw)
To: Jagan Teki
Cc: Chen-Yu Tsai, Icenowy Zheng, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Michael Trimarchi,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Jagan Teki
In-Reply-To: <1512119165-15290-2-git-send-email-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 436 bytes --]
Hi
On Fri, Dec 01, 2017 at 02:36:05PM +0530, Jagan Teki wrote:
> Since current tree support AXP803 regulators,
> replace fixed regulator vcc3v3 with AXP803 dcdc1 regulator.
>
> Tested mmc0 on sopine baseboard.
>
> Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Is it supposed to be a fix?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: a64-olinuxino: Enable RTL8723BS WiFi
From: Maxime Ripard @ 2017-12-01 16:02 UTC (permalink / raw)
To: Jagan Teki
Cc: Chen-Yu Tsai, Icenowy Zheng, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Michael Trimarchi,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Jagan Teki
In-Reply-To: <1512119165-15290-1-git-send-email-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 671 bytes --]
On Fri, Dec 01, 2017 at 02:36:04PM +0530, Jagan Teki wrote:
> Enable RTL8723BS WiFi chip on a64-olinuxino board:
> - WiFi SDIO interface is connected to MMC1
> - WiFi REG_ON pin connected to gpio PL2: attach to mmc-pwrseq
> - WiFi HOST_WAKE pin connected to gpio PL3
>
> To make rtl8723bs chip to work build it as module to and run
> CONFIG_RTL8723BS=m
You can definitely use that driver without building it as a module.
Once that part of the commit log has been removed,
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH v4 10/10] ARM: dtsi: axp81x: set pinmux for GPIO0/1 when used as LDOs
From: Maxime Ripard @ 2017-12-01 15:58 UTC (permalink / raw)
To: Quentin Schulz
Cc: linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
wens-jdAy2FN1RRM, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <afc22693e34c11231fc85a0dc6af3ffb340ba9b2.1512135804.git-series.quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
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On Fri, Dec 01, 2017 at 02:44:51PM +0100, Quentin Schulz wrote:
> On AXP813/818, GPIO0 and GPIO1 can be used as LDO as (respectively)
> ldo_io0 and ldo_io1.
>
> Let's add the pinctrl properties to the said regulators.
>
> Signed-off-by: Quentin Schulz <quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH v4 06/10] pinctrl: axp209: add programmable ADC muxing value
From: Maxime Ripard @ 2017-12-01 15:57 UTC (permalink / raw)
To: Quentin Schulz
Cc: linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
wens-jdAy2FN1RRM, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <a4f348914450705f1f784a2148559e19caf9e9fd.1512135804.git-series.quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
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On Fri, Dec 01, 2017 at 02:44:47PM +0100, Quentin Schulz wrote:
> To prepare for patches that will add support for a new PMIC that has a
> different GPIO adc muxing value, add an adc_mux within axp20x_pctl
> structure and use it.
>
> Signed-off-by: Quentin Schulz <quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH v2 16/19] ASoC: tlv320aic31xx: Add short circuit detection support
From: Mark Brown @ 2017-12-01 15:57 UTC (permalink / raw)
To: Andrew F. Davis
Cc: Mark Rutland, devicetree, alsa-devel, Tony Lindgren,
Liam Girdwood, linux-kernel, Rob Herring, Benoît Cousson
In-Reply-To: <4d956cbc-829c-0d81-2980-aa2a79f36660@ti.com>
[-- Attachment #1.1: Type: text/plain, Size: 556 bytes --]
On Fri, Dec 01, 2017 at 09:32:12AM -0600, Andrew F. Davis wrote:
> On 12/01/2017 07:39 AM, Mark Brown wrote:
> > Is the interrupt only available on GPIO1?
> Some devices can route this to GPIO2 IIRC.
> I'm not sure how that would be supported, I think we would need to add
> interrupt names to DT so users could specify which gpio they wired their
> IRQ lines to.
> interrupt = <&host 23>;
> interrupt-name = "gpio2";
> or similar?
You could also use pinctrl an require the user to mux the interrupt in
whatever fashion makes sense for their device.
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^ permalink raw reply
* Re: [PATCH v4 02/10] pinctrl: axp209: add pinctrl features
From: Maxime Ripard @ 2017-12-01 15:57 UTC (permalink / raw)
To: Quentin Schulz
Cc: linus.walleij, robh+dt, mark.rutland, wens, linux, lee.jones,
linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
thomas.petazzoni, linux-sunxi
In-Reply-To: <71c9da94df2a5938cb8c092e40f8e36eec0b01c3.1512135804.git-series.quentin.schulz@free-electrons.com>
[-- Attachment #1: Type: text/plain, Size: 1544 bytes --]
On Fri, Dec 01, 2017 at 02:44:43PM +0100, Quentin Schulz wrote:
> +static void axp20x_gpio_set(struct gpio_chip *chip, unsigned offset,
> + int value)
> +{
checkpatch output:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
> +static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
> + unsigned int function, unsigned int group)
> +{
> + struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev);
> + unsigned int mask;
> +
> + /* Every pin supports GPIO_OUT and GPIO_IN functions */
> + if (function <= AXP20X_FUNC_GPIO_IN)
> + return axp20x_pmx_set(pctldev, group,
> + gpio->funcs[function].muxval);
> +
> + if (function == AXP20X_FUNC_LDO)
> + mask = gpio->desc->ldo_mask;
> + else
> + mask = gpio->desc->adc_mask;
What is the point of this test...
> + if (!(BIT(group) & mask))
> + return -EINVAL;
> +
> + /*
> + * We let the regulator framework handle the LDO muxing as muxing bits
> + * are basically also regulators on/off bits. It's better not to enforce
> + * any state of the regulator when selecting LDO mux so that we don't
> + * interfere with the regulator driver.
> + */
> + if (function == AXP20X_FUNC_LDO)
> + return 0;
... if you know that you're not going to do anything with one of the
outcomes. It would be better to just move that part above, instead of
doing the same test twice.
It looks good otherwise, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH v2 15/19] ASoC: tlv320aic31xx: Reset registers during power up
From: Mark Brown @ 2017-12-01 15:55 UTC (permalink / raw)
To: Andrew F. Davis
Cc: Liam Girdwood, Rob Herring, Mark Rutland, Benoît Cousson,
Tony Lindgren, alsa-devel, devicetree, linux-kernel
In-Reply-To: <f8b03c59-c7c5-da32-c0fb-de366e931bc9@ti.com>
[-- Attachment #1: Type: text/plain, Size: 446 bytes --]
On Fri, Dec 01, 2017 at 09:04:41AM -0600, Andrew F. Davis wrote:
> On 12/01/2017 07:37 AM, Mark Brown wrote:
> > On Wed, Nov 29, 2017 at 03:32:56PM -0600, Andrew F. Davis wrote:
> >> + } else {
> >> + ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1);
> >> + if (ret < 0)
> >> + dev_err(aic31xx->dev, "Could not reset device\n");
> > Print the error to help people doing debug.
> Do you mean by adding the ret code to the print?
Yes.
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