* Re: [PATCH 1/2] arm64: dts: orange-pi-zero-plus2: fix sdcard detect
From: Sergey Matyukevich @ 2017-12-03 20:13 UTC (permalink / raw)
To: Maxime Ripard
Cc: Jagan Teki, Chen-Yu Tsai, Rob Herring, Mark Rutland, devicetree,
linux-arm-kernel
In-Reply-To: <CAMty3ZDQqaiZ0RxtngWdX9PCW2+tzXLVB64heHLjRBeVF2-FCQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hello Maxime,
> >> > Do you plan to accept this patch as well ? Or you would prefer to wait
> >> > for the confirmation from Jagan as well ?
> >>
> >> I'm happy with the patch, but I was under the impression that the
> >> discussion had not settled yet. If it did, then yeah I'll merge it :)
> >
> > Both schematics and my tests on v1.0 board confirm that this fix is ok.
> > However we haven't yet got the ACK from Jagan, the original submitter
> > of this dts file. FWIW discussion was mostly about the problems with
> > his setup and not about the fix itself.
> >
> > Jagan,
> > did you have a chance to resolve the issues with your setup and verify
> > that boot from sd-card is fixed by this patch ?
>
> Acked-by: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
It looks like discussion has finally settled: here is ACK from Jagan.
Could you please take this patch.
Regards,
Sergey
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^ permalink raw reply
* Re: [PATCH] fsi: Add Self Boot Engine FIFO FSI client
From: kbuild test robot @ 2017-12-03 20:25 UTC (permalink / raw)
Cc: kbuild-all-JC7UmRfGjtg, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Andrew Jeffery, gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
bradleyb-r5pk2Da7Bxt8sGd51Jp2sdBPR1lH4CV8,
cbostic-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8,
joel-U3u1mxZcP9KHXe+LvDLADg,
eajames-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8, Edward A. James
In-Reply-To: <20171201130744.17659-1-andrew-zrmu5oMJ5Fs@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 21628 bytes --]
Hi Andrew,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v4.15-rc2 next-20171201]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Andrew-Jeffery/fsi-Add-Self-Boot-Engine-FIFO-FSI-client/20171204-031454
config: blackfin-allmodconfig (attached as .config)
compiler: bfin-uclinux-gcc (GCC) 6.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=blackfin
All error/warnings (new ones prefixed by >>):
>> drivers/fsi//clients/fsi-sbefifo.c:325:0: warning: "TEST_SET" redefined
#define TEST_SET(s) ((s) & BIT(7))
In file included from arch/blackfin/mach-bf533/include/mach/blackfin.h:15:0,
from arch/blackfin/include/asm/irqflags.h:11,
from include/linux/irqflags.h:16,
from arch/blackfin/include/asm/bitops.h:33,
from include/linux/bitops.h:38,
from drivers/fsi//clients/fsi-sbefifo.c:5:
arch/blackfin/include/asm/def_LPBlackfin.h:687:0: note: this is the location of the previous definition
#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
In file included from include/linux/printk.h:329:0,
from include/linux/kernel.h:14,
from include/linux/list.h:9,
from include/linux/kobject.h:20,
from include/linux/device.h:17,
from include/linux/fsi.h:18,
from drivers/fsi//clients/fsi-sbefifo.c:6:
drivers/fsi//clients/fsi-sbefifo.c: In function 'sbefifo_drain':
>> drivers/fsi//clients/fsi-sbefifo.c:359:21: warning: format '%d' expects argument of type 'int', but argument 7 has type 'ssize_t {aka long int}' [-Wformat=]
dev_dbg(fifo->dev, "%s: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
>> drivers/fsi//clients/fsi-sbefifo.c:359:2: note: in expansion of macro 'dev_dbg'
dev_dbg(fifo->dev, "%s: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^~~~~~~
drivers/fsi//clients/fsi-sbefifo.c:359:21: warning: format '%d' expects argument of type 'int', but argument 9 has type 'ssize_t {aka long int}' [-Wformat=]
dev_dbg(fifo->dev, "%s: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
>> drivers/fsi//clients/fsi-sbefifo.c:359:2: note: in expansion of macro 'dev_dbg'
dev_dbg(fifo->dev, "%s: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^~~~~~~
drivers/fsi//clients/fsi-sbefifo.c:378:21: warning: format '%d' expects argument of type 'int', but argument 7 has type 'ssize_t {aka long int}' [-Wformat=]
dev_dbg(fifo->dev, "%s: Data phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
drivers/fsi//clients/fsi-sbefifo.c:378:2: note: in expansion of macro 'dev_dbg'
dev_dbg(fifo->dev, "%s: Data phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^~~~~~~
drivers/fsi//clients/fsi-sbefifo.c:378:21: warning: format '%d' expects argument of type 'int', but argument 9 has type 'ssize_t {aka long int}' [-Wformat=]
dev_dbg(fifo->dev, "%s: Data phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
drivers/fsi//clients/fsi-sbefifo.c:378:2: note: in expansion of macro 'dev_dbg'
dev_dbg(fifo->dev, "%s: Data phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^~~~~~~
drivers/fsi//clients/fsi-sbefifo.c:403:21: warning: format '%d' expects argument of type 'int', but argument 7 has type 'ssize_t {aka long int}' [-Wformat=]
dev_dbg(fifo->dev, "%s: EOT phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d\n, nr_xfer: %d, rem: %d\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
drivers/fsi//clients/fsi-sbefifo.c:403:2: note: in expansion of macro 'dev_dbg'
dev_dbg(fifo->dev, "%s: EOT phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d\n, nr_xfer: %d, rem: %d\n",
^~~~~~~
drivers/fsi//clients/fsi-sbefifo.c:403:21: warning: format '%d' expects argument of type 'int', but argument 9 has type 'ssize_t {aka long int}' [-Wformat=]
dev_dbg(fifo->dev, "%s: EOT phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d\n, nr_xfer: %d, rem: %d\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
drivers/fsi//clients/fsi-sbefifo.c:403:2: note: in expansion of macro 'dev_dbg'
dev_dbg(fifo->dev, "%s: EOT phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d\n, nr_xfer: %d, rem: %d\n",
^~~~~~~
drivers/fsi//clients/fsi-sbefifo.c:417:21: warning: format '%d' expects argument of type 'int', but argument 7 has type 'ssize_t {aka long int}' [-Wformat=]
dev_dbg(fifo->dev, "%s: Drain phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
drivers/fsi//clients/fsi-sbefifo.c:417:2: note: in expansion of macro 'dev_dbg'
dev_dbg(fifo->dev, "%s: Drain phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^~~~~~~
drivers/fsi//clients/fsi-sbefifo.c:417:21: warning: format '%d' expects argument of type 'int', but argument 9 has type 'ssize_t {aka long int}' [-Wformat=]
dev_dbg(fifo->dev, "%s: Drain phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
drivers/fsi//clients/fsi-sbefifo.c:417:2: note: in expansion of macro 'dev_dbg'
dev_dbg(fifo->dev, "%s: Drain phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^~~~~~~
In file included from include/linux/list.h:9:0,
from include/linux/kobject.h:20,
from include/linux/device.h:17,
from include/linux/fsi.h:18,
from drivers/fsi//clients/fsi-sbefifo.c:6:
drivers/fsi//clients/fsi-sbefifo.c: In function 'sbefifo_down_read':
include/linux/kernel.h:792:16: warning: comparison of distinct pointer types lacks a cast
(void) (&min1 == &min2); \
^
include/linux/kernel.h:801:2: note: in expansion of macro '__min'
__min(typeof(x), typeof(y), \
^~~~~
>> drivers/fsi//clients/fsi-sbefifo.c:453:34: note: in expansion of macro 'min'
} while (rem && read && read == min((rem + read), SBEFIFO_FIFO_DEPTH));
^~~
drivers/fsi//clients/fsi-sbefifo.c: In function 'sbefifo_write':
drivers/fsi//clients/fsi-sbefifo.c:557:43: warning: format '%d' expects argument of type 'int', but argument 3 has type 'ssize_t {aka long int}' [-Wformat=]
dev_err(fifo->dev, "FIFO write failed: %d\n", rv);
^
In file included from arch/blackfin/include/asm/bug.h:71:0,
from include/linux/bug.h:5,
from include/linux/thread_info.h:12,
from include/asm-generic/current.h:5,
from ./arch/blackfin/include/generated/asm/current.h:1,
from include/linux/mutex.h:14,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:21,
from include/linux/device.h:17,
from include/linux/fsi.h:18,
from drivers/fsi//clients/fsi-sbefifo.c:6:
drivers/fsi//clients/fsi-sbefifo.c:572:17: warning: format '%d' expects argument of type 'int', but argument 4 has type 'ssize_t {aka long int}' [-Wformat=]
WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
^
include/asm-generic/bug.h:91:69: note: in definition of macro '__WARN_printf'
#define __WARN_printf(arg...) warn_slowpath_fmt(__FILE__, __LINE__, arg)
^~~
>> drivers/fsi//clients/fsi-sbefifo.c:572:2: note: in expansion of macro 'WARN'
WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
^~~~
drivers/fsi//clients/fsi-sbefifo.c:572:17: warning: format '%d' expects argument of type 'int', but argument 5 has type 'ssize_t {aka long int}' [-Wformat=]
WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
^
include/asm-generic/bug.h:91:69: note: in definition of macro '__WARN_printf'
#define __WARN_printf(arg...) warn_slowpath_fmt(__FILE__, __LINE__, arg)
^~~
>> drivers/fsi//clients/fsi-sbefifo.c:572:2: note: in expansion of macro 'WARN'
WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
^~~~
drivers/fsi//clients/fsi-sbefifo.c: In function 'sbefifo_read':
drivers/fsi//clients/fsi-sbefifo.c:650:42: warning: format '%d' expects argument of type 'int', but argument 3 has type 'ssize_t {aka long int}' [-Wformat=]
dev_err(fifo->dev, "FIFO read failed: %d\n", rv);
^
drivers/fsi//clients/fsi-sbefifo.c: In function 'sbefifo_probe':
>> drivers/fsi//clients/fsi-sbefifo.c:769:2: error: implicit declaration of function 'setup_timer' [-Werror=implicit-function-declaration]
setup_timer(&fifo->poll.timer, sbefifo_poll_device,
^~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/setup_timer +769 drivers/fsi//clients/fsi-sbefifo.c
498
499 /**
500 * sbefifo_write()
501 *
502 * @client The client context for the SBEFIFO
503 * @buf The buffer of data to write, at least @len elements
504 * @len The number elements in @buffer
505 *
506 * The buffer must represent a complete chip-op: EOT is signalled after the
507 * last element is written to the upstream FIFO.
508 *
509 * Returns the number of elements written on success and negative values on
510 * failure. If the call is successful a subsequent call to sbefifo_read() MUST
511 * be made.
512 */
513 ssize_t sbefifo_write(struct sbefifo_client *client, const u32 *buf,
514 ssize_t len)
515 {
516 struct sbefifo *fifo = client->fifo;
517 unsigned long flags;
518 ssize_t rv;
519
520 spin_lock_irqsave(&fifo->wait.lock, flags);
521
522 if (client->state == sbefifo_client_active) {
523 dev_warn(fifo->dev, "Transfer already in progress\n");
524 spin_unlock_irqrestore(&fifo->wait.lock, flags);
525 return -EBUSY;
526 }
527
528 rv = wait_event_interruptible_locked_irq(fifo->wait,
529 fifo->state == sbefifo_ready ||
530 fifo->state == sbefifo_dead);
531 if (rv < 0) {
532 spin_unlock_irqrestore(&fifo->wait.lock, flags);
533 return rv;
534 }
535
536 if (fifo->state == sbefifo_dead) {
537 client->state = sbefifo_client_closed;
538 wake_up(&client->wait);
539 spin_unlock_irqrestore(&fifo->wait.lock, flags);
540 return -ENODEV;
541 }
542
543 WARN_ON(fifo->state != sbefifo_ready);
544
545 fifo->curr = client;
546 fifo->state = sbefifo_tx;
547
548 /* Move a threaded read() onto waiting for FIFO read readiness */
549 client->state = sbefifo_client_active;
550 wake_up(&client->wait);
551
552 spin_unlock_irqrestore(&fifo->wait.lock, flags);
553
554 /* FIFO Tx, reset the FIFO on error */
555 rv = sbefifo_up_write(fifo, buf, len);
556 if (rv < len) {
557 dev_err(fifo->dev, "FIFO write failed: %d\n", rv);
558 rv = sbefifo_reset(fifo);
559 if (rv < 0)
560 return rv;
561
562 spin_lock_irqsave(&fifo->wait.lock, flags);
563 fifo->state = sbefifo_ready;
564 client->state = sbefifo_client_idle;
565 wake_up(&client->wait);
566 wake_up_locked(&fifo->wait);
567 spin_unlock_irqrestore(&fifo->wait.lock, flags);
568
569 return -EIO;
570 }
571
> 572 WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
573
574 /* Write completed successfully */
575 spin_lock_irqsave(&fifo->wait.lock, flags);
576 fifo->state = sbefifo_interval;
577 wake_up(&client->wait);
578 spin_unlock_irqrestore(&fifo->wait.lock, flags);
579
580 return rv;
581 }
582 EXPORT_SYMBOL_GPL(sbefifo_write);
583
584 /**
585 * sbefifo_read()
586 *
587 * @client The client context for the SBEFIFO
588 * @data The buffer of data to write, at least @len elements
589 * @len The number elements in @buffer
590 *
591 * Returns the number of elements read on success and negative values on
592 * failure. A return value of 0 indicates EOT.
593 */
594 ssize_t sbefifo_read(struct sbefifo_client *client, u32 *buf, ssize_t len)
595 {
596 struct sbefifo *fifo = client->fifo;
597 unsigned long flags;
598 ssize_t rv;
599
600 rv = wait_event_interruptible(client->wait,
601 (client->state == sbefifo_client_active ||
602 client->state == sbefifo_client_closed));
603 if (rv < 0)
604 return rv;
605
606 spin_lock_irqsave(&fifo->wait.lock, flags);
607 if (client->state == sbefifo_client_closed) {
608 spin_unlock_irqrestore(&fifo->wait.lock, flags);
609 return -EBADFD;
610 }
611
612 if (client->state == sbefifo_client_idle) {
613 spin_unlock_irqrestore(&fifo->wait.lock, flags);
614 return -EIO;
615 }
616
617 rv = wait_event_interruptible_locked_irq(fifo->wait,
618 fifo->state == sbefifo_interval ||
619 fifo->state == sbefifo_rx ||
620 fifo->state == sbefifo_ready ||
621 fifo->state == sbefifo_dead);
622 if (rv < 0) {
623 spin_unlock_irqrestore(&fifo->wait.lock, flags);
624 return rv;
625 }
626
627 if (fifo->state == sbefifo_ready) {
628 /* We've reset FIFO, whatever we were waiting for has gone */
629 client->state = sbefifo_client_idle;
630 /* We're done, wake another task up as the FIFO is ready */
631 wake_up_locked(&fifo->wait);
632 spin_unlock_irqrestore(&fifo->wait.lock, flags);
633 return -EIO;
634 }
635
636 if (fifo->state == sbefifo_dead) {
637 spin_unlock_irqrestore(&fifo->wait.lock, flags);
638 return -ENODEV;
639 }
640
641 fifo->state = sbefifo_rx;
642 spin_unlock_irqrestore(&fifo->wait.lock, flags);
643
644 rv = sbefifo_down_read(fifo, buf, len);
645 if (rv > 0)
646 return rv;
647
648 /* Reset the FIFO on error */
649 if (rv < 0) {
650 dev_err(fifo->dev, "FIFO read failed: %d\n", rv);
651 rv = sbefifo_reset(fifo);
652 if (rv < 0)
653 return rv;
654
655 rv = -EIO;
656 }
657
658 /* Read is complete one way or the other (0 length read or error) */
659 spin_lock_irqsave(&fifo->wait.lock, flags);
660 client->state = sbefifo_client_idle;
661
662 /* Queue next FIFO transfer */
663 fifo->curr = NULL;
664 fifo->state = sbefifo_ready;
665 wake_up_locked(&fifo->wait);
666
667 spin_unlock_irqrestore(&fifo->wait.lock, flags);
668
669 return rv;
670 }
671 EXPORT_SYMBOL_GPL(sbefifo_read);
672
673 /**
674 * sbefifo_release()
675 *
676 * @client The client context for the SBEFIFO
677 *
678 */
679 int sbefifo_release(struct sbefifo_client *client)
680 {
681 struct sbefifo *fifo = client->fifo;
682 enum sbefifo_client_state old;
683 unsigned long flags;
684 int rv;
685
686 /* Determine if we need to clean up */
687 spin_lock_irqsave(&client->fifo->wait.lock, flags);
688 old = client->state;
689 client->state = sbefifo_client_closed;
690
691 if (old == sbefifo_client_closed) {
692 spin_unlock_irqrestore(&fifo->wait.lock, flags);
693 return -EBADFD;
694 }
695
696 if (old == sbefifo_client_idle) {
697 spin_unlock_irqrestore(&fifo->wait.lock, flags);
698 return 0;
699 }
700
701 /* We need to clean up, get noisy about inconsistencies */
702 dev_warn(fifo->dev, "Releasing client with transfer in progress!\n");
703 WARN_ON(old != sbefifo_client_active);
704 WARN_ON(fifo->state == sbefifo_ready);
705
706 /* Mark ourselves as broken for cleanup */
707 fifo->state = sbefifo_broken;
708 fifo->curr = NULL;
709
710 wake_up(&client->wait);
711 spin_unlock_irqrestore(&client->fifo->wait.lock, flags);
712
713 /* Clean up poll waiter */
714 spin_lock_irqsave(&fifo->poll.wait.lock, flags);
715 del_timer_sync(&fifo->poll.timer);
716 fifo->poll.rv = -EBADFD;
717 wake_up_all_locked(&fifo->poll.wait);
718 spin_unlock_irqrestore(&fifo->poll.wait.lock, flags);
719
720 /* Reset the FIFO */
721 rv = sbefifo_reset(fifo);
722 if (rv < 0)
723 return rv;
724
725 /* Mark the FIFO as ready and wake pending transfer */
726 spin_lock_irqsave(&client->fifo->wait.lock, flags);
727 fifo->state = sbefifo_ready;
728 wake_up_locked(&fifo->wait);
729 spin_unlock_irqrestore(&client->fifo->wait.lock, flags);
730
731 return 0;
732 }
733 EXPORT_SYMBOL_GPL(sbefifo_release);
734
735 static int sbefifo_unregister_child(struct device *dev, void *data)
736 {
737 struct platform_device *pdev = to_platform_device(dev);
738
739 of_device_unregister(pdev);
740 if (dev->of_node)
741 of_node_clear_flag(dev->of_node, OF_POPULATED);
742
743 return 0;
744 }
745
746 static int sbefifo_probe(struct device *dev)
747 {
748 struct device_node *np;
749 struct sbefifo *fifo;
750 int child_idx;
751 u32 up, down;
752 int rv;
753
754 fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
755 if (!fifo)
756 return -ENOMEM;
757
758 fifo->dev = dev;
759 fifo->state = sbefifo_ready;
760 fifo->fsi = to_fsi_dev(dev);
761
762 fifo->id = ida_simple_get(&sbefifo_ida, 0, 0, GFP_KERNEL);
763 if (fifo->id < 0)
764 return fifo->id;
765
766 init_waitqueue_head(&fifo->wait);
767
768 /* No interrupts, need to poll the controller */
> 769 setup_timer(&fifo->poll.timer, sbefifo_poll_device,
770 (unsigned long)fifo);
771 init_waitqueue_head(&fifo->poll.wait);
772
773 rv = sbefifo_up_sts(fifo, &up);
774 if (rv < 0)
775 return rv;
776
777 rv = sbefifo_down_sts(fifo, &down);
778 if (rv < 0)
779 return rv;
780
781 if (!(sbefifo_empty(up) && sbefifo_empty(down))) {
782 dev_warn(fifo->dev, "FIFOs were not empty, requesting reset from SBE\n");
783 /* Request the SBE reset the FIFOs */
784 rv = sbefifo_reset(fifo);
785 if (rv == -ETIMEDOUT) {
786 dev_warn(fifo->dev, "SBE unresponsive, probing FIFO clients may fail. Performing hard FIFO reset\n");
787 rv = sbefifo_do_reset(fifo);
788 if (rv < 0)
789 return rv;
790 } else if (rv < 0) {
791 return rv;
792 }
793 }
794
795 dev_set_drvdata(dev, fifo);
796 list_add(&fifo->entry, &sbefifos);
797
798 child_idx = 0;
799 for_each_available_child_of_node(dev->of_node, np) {
800 struct platform_device *child;
801 char name[32];
802
803 snprintf(name, sizeof(name), "sbefifo%d-dev%d", fifo->id,
804 child_idx++);
805 child = of_platform_device_create(np, name, dev);
806 if (!child)
807 dev_warn(dev, "Failed to create platform device %s\n",
808 name);
809 }
810
811 return 0;
812 }
813
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 46944 bytes --]
^ permalink raw reply
* Re: [PATCH 3/5] PCI: cadence: Add host driver for Cadence PCIe controller
From: Cyrille Pitchen @ 2017-12-03 20:44 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: bhelgaas, kishon, linux-pci, adouglas, stelford, dgary, kgopi,
eandrews, thomas.petazzoni, sureshp, nsekhar, linux-kernel, robh,
devicetree
In-Reply-To: <20171129173426.GB31205@red-moon>
Hi Lorenzo,
Le 29/11/2017 à 18:34, Lorenzo Pieralisi a écrit :
> On Thu, Nov 23, 2017 at 04:01:48PM +0100, Cyrille Pitchen wrote:
>> This patch adds support to the Cadence PCIe controller in host mode.
>
> Bjorn already commented on this, it would be good to add some
> of the cover letter details in this log.
>
>> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
>> ---
>> drivers/Makefile | 1 +
>> drivers/pci/Kconfig | 1 +
>> drivers/pci/cadence/Kconfig | 24 ++
>> drivers/pci/cadence/Makefile | 2 +
>> drivers/pci/cadence/pcie-cadence-host.c | 425 ++++++++++++++++++++++++++++++++
>
> You should also update the MAINTAINERS file.
I will ask Cadence who will be the maintainer.
>
>> drivers/pci/cadence/pcie-cadence.c | 110 +++++++++
>> drivers/pci/cadence/pcie-cadence.h | 325 ++++++++++++++++++++++++
>> 7 files changed, 888 insertions(+)
>> create mode 100644 drivers/pci/cadence/Kconfig
>> create mode 100644 drivers/pci/cadence/Makefile
>> create mode 100644 drivers/pci/cadence/pcie-cadence-host.c
>> create mode 100644 drivers/pci/cadence/pcie-cadence.c
>> create mode 100644 drivers/pci/cadence/pcie-cadence.h
>>
>> diff --git a/drivers/Makefile b/drivers/Makefile
>> index 1d034b680431..27bdd98784d9 100644
>> --- a/drivers/Makefile
>> +++ b/drivers/Makefile
>> @@ -18,6 +18,7 @@ obj-y += pwm/
>>
>> obj-$(CONFIG_PCI) += pci/
>> obj-$(CONFIG_PCI_ENDPOINT) += pci/endpoint/
>> +obj-$(CONFIG_PCI_CADENCE) += pci/cadence/
>
> Already commented on the cover letter.
>
>> # PCI dwc controller drivers
>> obj-y += pci/dwc/
>>
>> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
>> index 90944667ccea..2471b2e36b8b 100644
>> --- a/drivers/pci/Kconfig
>> +++ b/drivers/pci/Kconfig
>> @@ -144,6 +144,7 @@ config PCI_HYPERV
>> PCI devices from a PCI backend to support PCI driver domains.
>>
>> source "drivers/pci/hotplug/Kconfig"
>> +source "drivers/pci/cadence/Kconfig"
>> source "drivers/pci/dwc/Kconfig"
>> source "drivers/pci/host/Kconfig"
>> source "drivers/pci/endpoint/Kconfig"
>> diff --git a/drivers/pci/cadence/Kconfig b/drivers/pci/cadence/Kconfig
>> new file mode 100644
>> index 000000000000..120306cae2aa
>> --- /dev/null
>> +++ b/drivers/pci/cadence/Kconfig
>> @@ -0,0 +1,24 @@
>> +menuconfig PCI_CADENCE
>> + bool "Cadence PCI controllers support"
>> + depends on PCI && HAS_IOMEM
>> + help
>> + Say Y here if you want to support some Cadence PCI controller.
>> +
>> + When in doubt, say N.
>> +
>> +if PCI_CADENCE
>> +
>> +config PCIE_CADENCE
>> + bool
>> +
>> +config PCIE_CADENCE_HOST
>> + bool "Cadence PCIe host controller"
>> + depends on OF
>> + depends on PCI_MSI_IRQ_DOMAIN
>
> I do not see the reason for this dependency in the code.
>
I will remove it if it's not needed.
>> + select PCIE_CADENCE
>> + help
>> + Say Y here if you want to support the Cadence PCIe controller in host
>> + mode. This PCIe controller may be embedded into many different vendors
>> + SoCs.
>> +
>> +endif # PCI_CADENCE
>> diff --git a/drivers/pci/cadence/Makefile b/drivers/pci/cadence/Makefile
>> new file mode 100644
>> index 000000000000..d57d192d2595
>> --- /dev/null
>> +++ b/drivers/pci/cadence/Makefile
>> @@ -0,0 +1,2 @@
>> +obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o
>> +obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o
>> diff --git a/drivers/pci/cadence/pcie-cadence-host.c b/drivers/pci/cadence/pcie-cadence-host.c
>> new file mode 100644
>> index 000000000000..252471e72a93
>> --- /dev/null
>> +++ b/drivers/pci/cadence/pcie-cadence-host.c
>> @@ -0,0 +1,425 @@
>> +/*
>> + * Cadence PCIe host controller driver.
>> + *
>> + * Copyright (c) 2017 Cadence
>> + *
>> + * Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +#include <linux/kernel.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_pci.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pm_runtime.h>
>> +
>> +#include "pcie-cadence.h"
>> +
>> +/**
>> + * struct cdns_pcie_rc_data - hardware specific data
>> + * @max_regions: maximum number of regions supported by the hardware
>> + * @vendor_id: PCI vendor ID
>> + * @device_id: PCI device ID
>> + * @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address
>> + * translation (nbits sets into the "no BAR match" register).
>> + */
>> +struct cdns_pcie_rc_data {
>> + size_t max_regions;
>
> Reason for it to be size_t ?
>
No special reason, I can use another integer type.
>> + u16 vendor_id;
>> + u16 device_id;
>> + u8 no_bar_nbits;
>> +};
>
> I think that this data should come from DT (?) more below.
>
I can update the DT bindings documentation and the driver source code as needed.
>> +
>> +/**
>> + * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
>> + * @pcie: Cadence PCIe controller
>> + * @dev: pointer to PCIe device
>> + * @cfg_res: start/end offsets in the physical system memory to map PCI
>> + * configuration space accesses
>> + * @bus_range: first/last buses behind the PCIe host controller
>> + * @cfg_base: IO mapped window to access the PCI configuration space of a
>> + * single function at a time
>> + * @data: pointer to a 'struct cdns_pcie_rc_data'
>> + */
>> +struct cdns_pcie_rc {
>> + struct cdns_pcie pcie;
>> + struct device *dev;
>> + struct resource *cfg_res;
>> + struct resource *bus_range;
>> + void __iomem *cfg_base;
>> + const struct cdns_pcie_rc_data *data;
>> +};
>> +
>> +static void __iomem *
>
> Please do not split lines like this, storage class and return type
> should be in the same line as the name, move parameter(s) to a new
> line.
>
> static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
> int where)
>
ok :)
>> +cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
>> +{
>> + struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
>> + struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
>> + struct cdns_pcie *pcie = &rc->pcie;
>> + unsigned int busn = bus->number;
>> + u32 addr0, desc0;
>> +
>> + if (busn < rc->bus_range->start || busn > rc->bus_range->end)
>> + return NULL;
>
> It does not hurt but I wonder whether you really need this check.
>
I can remove it.
>> + if (busn == rc->bus_range->start) {
>> + if (devfn)
>
> I suspect I know why you need this check but I ask you to explain it
> anyway if you do not mind please.
>
If I have understood correctly, Cadence team told me that only the root
port is available on the first bus through device 0, function 0.
No other device/function should connected on this bus, all other devices
are behind at least one PCI bridge.
I can add a comment here to explain that.
>> + return NULL;
>> +
>> + return pcie->reg_base + (where & 0xfff);
>> + }
>> +
>> + /* Update Output registers for AXI region 0. */
>> + addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
>
> Ok, so for every config access you reprogram addr0 to reflect the
> correct bus|devfn ID in the PCI bus TLP corresponding to an ECAM address
> in CPU physical address space, is my understanding correct ?
>
The idea is to able to use only a 4KB memory area at a fixed address in the
space allocated for the PCIe controller in the AXI bus. I guess the plan is
to leave more space on the AXI bus to map all other PCIe devices.
This is just my guess. Anyway one purpose of this driver was actually to
perform all PCI configuration space accesses through this single 4KB memory
area in the AXI bus, changing the mapping dynamically to reach the relevant
PCI device.
>> + CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) |
>> + CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(busn);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0);
>> +
>> + /* Configuration Type 0 or Type 1 access. */
>> + desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
>> + CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
>> + /*
>> + * The bus number was already set once for all in desc1 by
>> + * cdns_pcie_host_init_address_translation().
>> + */
>> + if (busn == rc->bus_range->start + 1)
>> + desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0;
>> + else
>> + desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1;
>
> I would like to ask you why you have to do it here and the root port
> does not figure it out by itself, I do not have the datasheet so I am
> just asking for my own information.
PCI configuration space registers of the root port can only be read through
the APB bus at offset 0:
->reg_base + (where & 0xfff)
They are internal registers of the PCIe controller so no TLP on the PCIe bus.
However to access the PCI configuration space registers of any other device,
the PCIe controller builds then sends a TLP on the PCIe bus using the offset
in the 4KB AXI area as the offset of the register in the PCI configuration
space:
->cfg_base + (where & 0xfff)
>
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0);
>> +
>> + return rc->cfg_base + (where & 0xfff);
>> +}
>> +
>> +static struct pci_ops cdns_pcie_host_ops = {
>> + .map_bus = cdns_pci_map_bus,
>> + .read = pci_generic_config_read,
>> + .write = pci_generic_config_write,
>> +};
>> +
>> +static const struct cdns_pcie_rc_data cdns_pcie_rc_data = {
>> + .max_regions = 32,
>> + .vendor_id = PCI_VENDOR_ID_CDNS,
>> + .device_id = 0x0200,
>> + .no_bar_nbits = 32,
>> +};
>
> Should (some of) these parameters be retrieved through a DT binding ?
>
Indeed, maybe we get max_regions and no_bar_nbits from the DT.
About the vendor and device IDs, I don't know which would be the best
choice between some dedicated DT properties or associating a custom
structure as above to the 'compatible' string.
Honestly, I don't have any strong preference, please just tell me what
you would prefer :)
>> +static const struct of_device_id cdns_pcie_host_of_match[] = {
>> + { .compatible = "cdns,cdns-pcie-host",
>> + .data = &cdns_pcie_rc_data },
>> +
>> + { },
>> +};
>> +
>> +static int cdns_pcie_parse_request_of_pci_ranges(struct device *dev,
>> + struct list_head *resources,
>> + struct resource **bus_range)
>> +{
>> + int err, res_valid = 0;
>> + struct device_node *np = dev->of_node;
>> + resource_size_t iobase;
>> + struct resource_entry *win, *tmp;
>> +
>> + err = of_pci_get_host_bridge_resources(np, 0, 0xff, resources, &iobase);
>> + if (err)
>> + return err;
>> +
>> + err = devm_request_pci_bus_resources(dev, resources);
>> + if (err)
>> + return err;
>> +
>> + resource_list_for_each_entry_safe(win, tmp, resources) {
>> + struct resource *res = win->res;
>> +
>> + switch (resource_type(res)) {
>> + case IORESOURCE_IO:
>> + err = pci_remap_iospace(res, iobase);
>> + if (err) {
>> + dev_warn(dev, "error %d: failed to map resource %pR\n",
>> + err, res);
>> + resource_list_destroy_entry(win);
>> + }
>> + break;
>> + case IORESOURCE_MEM:
>> + res_valid |= !(res->flags & IORESOURCE_PREFETCH);
>> + break;
>> + case IORESOURCE_BUS:
>> + *bus_range = res;
>> + break;
>> + }
>> + }
>> +
>> + if (res_valid)
>> + return 0;
>> +
>> + dev_err(dev, "non-prefetchable memory resource required\n");
>> + return -EINVAL;
>
> Nit, I prefer you swap these two as it is done in pci-aardvark.c:
>
> if (!res_valid) {
> dev_err(dev, "non-prefetchable memory resource required\n");
> return -EINVAL;
> }
>
> return 0;
>
> but as per previous replies this function can be factorized in
> core PCI code - I would not bother unless you are willing to write
> the patch series that does the refactoring yourself :)
>
>> +}
>> +
>> +static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
>> +{
>> + const struct cdns_pcie_rc_data *data = rc->data;
>> + struct cdns_pcie *pcie = &rc->pcie;
>> + u8 pbn, sbn, subn;
>> + u32 value, ctrl;
>> +
>> + /*
>> + * Set the root complex BAR configuration register:
>> + * - disable both BAR0 and BAR1.
>> + * - enable Prefetchable Memory Base and Limit registers in type 1
>> + * config space (64 bits).
>> + * - enable IO Base and Limit registers in type 1 config
>> + * space (32 bits).
>> + */
>> + ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
>> + value = CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) |
>> + CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) |
>> + CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE |
>> + CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS |
>> + CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE |
>> + CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS;
>> + cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value);
>> +
>> + /* Set root port configuration space */
>> + if (data->vendor_id != 0xffff)
>> + cdns_pcie_rp_writew(pcie, PCI_VENDOR_ID, data->vendor_id);
>> + if (data->device_id != 0xffff)
>> + cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, data->device_id);
>> +
>> + cdns_pcie_rp_writeb(pcie, PCI_CLASS_REVISION, 0);
>> + cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);
>> + cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
>> +
>> + pbn = rc->bus_range->start;
>> + sbn = pbn + 1; /* Single root port. */
>> + subn = rc->bus_range->end;
>> + cdns_pcie_rp_writeb(pcie, PCI_PRIMARY_BUS, pbn);
>> + cdns_pcie_rp_writeb(pcie, PCI_SECONDARY_BUS, sbn);
>> + cdns_pcie_rp_writeb(pcie, PCI_SUBORDINATE_BUS, subn);
>
> Again - I do not have the datasheet for this device therefore I would
> kindly ask you how this works; it seems to me that what you are doing
> here is done through normal configuration cycles in an ECAM compliant
> system to program the RP PRIMARY/SECONDARY/SUBORDINATE bus - I would
> like to understand why this code is needed.
>
I will test without those lines to test whether I can remove them.
At first, the PCIe controller was tested by Cadence team: there was code
in their bootloader to initialize the hardware (building the AXI <-> PCIe
mappings, ...): the bootloader used to set the primary, secondary and
subordinate bus numbers in the root port PCI config space.
Also there was a hardware trick to redirect accesses of the lowest
addresses in the AXI bus to the APB bus so the PCI configuration space of
the root port could have been accessed from the AXI bus too.
The AXI <-> PCIe mapping being done by the bootloader and the root port
config space being accessible from the AXI bus, it was possible to use
the pci-host-generic driver.
However, the hardware trick won't be included in the final design since
Cadence now wants to perform all PCI configuration space accesses through
a small 4KB window at a fixed address on the AXI bus.
Also, we now want all initialisations to be done by the linux driver
instead of the bootloader.
I simply moved all those initialisations from the bootloader to the linux
driver but actually there is a chance that I can remove the 3 writes to
the PCI_*_BUS registers.
>> + return 0;
>> +}
>> +
>> +static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
>> +{
>> + struct cdns_pcie *pcie = &rc->pcie;
>> + struct resource *cfg_res = rc->cfg_res;
>> + struct resource *mem_res = pcie->mem_res;
>> + struct resource *bus_range = rc->bus_range;
>> + struct device *dev = rc->dev;
>> + struct device_node *np = dev->of_node;
>> + struct of_pci_range_parser parser;
>> + struct of_pci_range range;
>> + u32 addr0, addr1, desc1;
>> + u64 cpu_addr;
>> + int r, err;
>> +
>> + /*
>> + * Reserve region 0 for PCI configure space accesses:
>> + * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by
>> + * cdns_pci_map_bus(), other region registers are set here once for all.
>> + */
>> + addr1 = 0; /* Should be programmed to zero. */
>> + desc1 = CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus_range->start);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);
>> +
>> + cpu_addr = cfg_res->start - mem_res->start;
>> + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) |
>> + (lower_32_bits(cpu_addr) & GENMASK(31, 8));
>> + addr1 = upper_32_bits(cpu_addr);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(0), addr0);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(0), addr1);
>> +
>> + err = of_pci_range_parser_init(&parser, np);
>> + if (err)
>> + return err;
>> +
>> + r = 1;
>> + for_each_of_pci_range(&parser, &range) {
>> + bool is_io;
>> +
>> + if (r >= rc->data->max_regions)
>> + break;
>> +
>> + if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
>> + is_io = false;
>> + else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
>> + is_io = true;
>> + else
>> + continue;
>> +
>> + cdns_pcie_set_outbound_region(pcie, r, is_io,
>> + range.cpu_addr,
>> + range.pci_addr,
>> + range.size);
>> + r++;
>> + }
>> +
>> + /*
>> + * Set Root Port no BAR match Inbound Translation registers:
>> + * needed for MSI.
>
> And DMA :) if I understand what this is doing correctly, ie setting
> the root complex decoding for incoming memory traffic.
>
Yes, indeed :)
>> + * Root Port BAR0 and BAR1 are disabled, hence no need to set their
>> + * inbound translation registers.
>> + */
>> + addr0 = CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(rc->data->no_bar_nbits);
>> + addr1 = 0;
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(RP_NO_BAR), addr0);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(RP_NO_BAR), addr1);
>> +
>> + return 0;
>> +}
>> +
>> +static int cdns_pcie_host_init(struct device *dev,
>> + struct list_head *resources,
>> + struct cdns_pcie_rc *rc)
>> +{
>> + struct resource *bus_range = NULL;
>> + int err;
>> +
>> + /* Parse our PCI ranges and request their resources */
>> + err = cdns_pcie_parse_request_of_pci_ranges(dev, resources, &bus_range);
>> + if (err)
>> + goto err_out;
>
> I think that the err_out path should be part of:
>
> cdns_pcie_parse_request_of_pci_ranges()
>
> implementation and here you would just return.
>
>> +
>> + if (bus_range->start > bus_range->end) {
>> + err = -EINVAL;
>> + goto err_out;
>> + }
>
> Add a space here; this check seems useless to me anyway.
>
I can remove this too.
>> + rc->bus_range = bus_range;
>> + rc->pcie.bus = bus_range->start;
>> +
>> + err = cdns_pcie_host_init_root_port(rc);
>> + if (err)
>> + goto err_out;
>> +
>> + err = cdns_pcie_host_init_address_translation(rc);
>> + if (err)
>> + goto err_out;
>> +
>> + return 0;
>> +
>> + err_out:
>> + pci_free_resource_list(resources);
>
> See above.
>
>> + return err;
>> +}
>> +
>> +static int cdns_pcie_host_probe(struct platform_device *pdev)
>> +{
>> + const struct of_device_id *of_id;
>> + const char *type;
>> + struct device *dev = &pdev->dev;
>> + struct device_node *np = dev->of_node;
>> + struct pci_bus *bus, *child;
>> + struct pci_host_bridge *bridge;
>> + struct list_head resources;
>> + struct cdns_pcie_rc *rc;
>> + struct cdns_pcie *pcie;
>> + struct resource *res;
>> + int ret;
>> +
>> + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
>> + if (!bridge)
>> + return -ENOMEM;
>> +
>> + rc = pci_host_bridge_priv(bridge);
>> + rc->dev = dev;
>> + platform_set_drvdata(pdev, rc);
>
> I do not think it is needed.
>
>> + pcie = &rc->pcie;
>> + pcie->is_rc = true;
>> +
>> + of_id = of_match_node(cdns_pcie_host_of_match, np);
>> + rc->data = (const struct cdns_pcie_rc_data *)of_id->data;
>> +
>> + type = of_get_property(np, "device_type", NULL);
>> + if (!type || strcmp(type, "pci")) {
>> + dev_err(dev, "invalid \"device_type\" %s\n", type);
>> + return -EINVAL;
>> + }
>> +
>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
>> + pcie->reg_base = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(pcie->reg_base)) {
>> + dev_err(dev, "missing \"reg\"\n");
>> + return PTR_ERR(pcie->reg_base);
>> + }
>> +
>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
>> + rc->cfg_base = devm_ioremap_resource(dev, res);
>
> devm_pci_remap_cfg_resource() please.
>
I will change that.
>> + if (IS_ERR(rc->cfg_base)) {
>> + dev_err(dev, "missing \"cfg\"\n");
>> + return PTR_ERR(rc->cfg_base);
>> + }
>> + rc->cfg_res = res;
>> +
>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
>> + if (!res) {
>> + dev_err(dev, "missing \"mem\"\n");
>> + return -EINVAL;
>> + }
>> + pcie->mem_res = res;
>> +
>> + pm_runtime_enable(dev);
>> + ret = pm_runtime_get_sync(dev);
>> + if (ret < 0) {
>> + dev_err(dev, "pm_runtime_get_sync() failed\n");
>> + goto err_get_sync;
>> + }
>> +
>> + INIT_LIST_HEAD(&resources);
>> + ret = cdns_pcie_host_init(dev, &resources, rc);
>> + if (ret)
>> + goto err_init;
>> +
>> + list_splice_init(&resources, &bridge->windows);
>> + bridge->dev.parent = dev;
>> + bridge->busnr = pcie->bus;
>> + bridge->ops = &cdns_pcie_host_ops;
>> + bridge->map_irq = of_irq_parse_and_map_pci;
>> + bridge->swizzle_irq = pci_common_swizzle;
>> +
>> + ret = pci_scan_root_bus_bridge(bridge);
>> + if (ret < 0) {
>> + dev_err(dev, "Scanning root bridge failed");
>> + goto err_init;
>> + }
>> +
>> + bus = bridge->bus;
>> + pci_bus_size_bridges(bus);
>> + pci_bus_assign_resources(bus);
>> +
>> + list_for_each_entry(child, &bus->children, node)
>> + pcie_bus_configure_settings(child);
>> +
>> + pci_bus_add_devices(bus);
>> +
>> + return 0;
>> +
>> + err_init:
>> + pm_runtime_put_sync(dev);
>> +
>> + err_get_sync:
>> + pm_runtime_disable(dev);
>> +
>> + return ret;
>> +}
>> +
>> +static struct platform_driver cdns_pcie_host_driver = {
>> + .driver = {
>> + .name = "cdns-pcie-host",
>> + .of_match_table = cdns_pcie_host_of_match,
>> + },
>> + .probe = cdns_pcie_host_probe,
>> +};
>> +builtin_platform_driver(cdns_pcie_host_driver);
>> diff --git a/drivers/pci/cadence/pcie-cadence.c b/drivers/pci/cadence/pcie-cadence.c
>> new file mode 100644
>> index 000000000000..5c10879d5e96
>> --- /dev/null
>> +++ b/drivers/pci/cadence/pcie-cadence.c
>> @@ -0,0 +1,110 @@
>> +/*
>> + * Cadence PCIe controller driver.
>> + *
>> + * Copyright (c) 2017 Cadence
>> + *
>> + * Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +
>> +#include "pcie-cadence.h"
>> +
>> +void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u32 r, bool is_io,
>> + u64 cpu_addr, u64 pci_addr, size_t size)
>> +{
>> + /*
>> + * roundup_pow_of_two() returns an unsigned long, which is not suited
>> + * for 64bit values.
>> + */
>> + u64 sz = 1ULL << fls64(size - 1);
>> + int nbits = ilog2(sz);
>> + u32 addr0, addr1, desc0, desc1;
>> +
>> + if (nbits < 8)
>> + nbits = 8;
>> +
>> + /* Set the PCI address */
>> + addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) |
>> + (lower_32_bits(pci_addr) & GENMASK(31, 8));
>> + addr1 = upper_32_bits(pci_addr);
>> +
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1);
>> +
>> + /* Set the PCIe header descriptor */
>> + if (is_io)
>> + desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO;
>> + else
>> + desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM;
>> + desc1 = 0;
>> +
>> + if (pcie->is_rc) {
>> + desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
>> + CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
>> + desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(pcie->bus);
>> + }
>> +
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
>> +
>> + /* Set the CPU address */
>> + cpu_addr -= pcie->mem_res->start;
>> + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
>> + (lower_32_bits(cpu_addr) & GENMASK(31, 8));
>> + addr1 = upper_32_bits(cpu_addr);
>> +
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
>> +}
>> +
>> +void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u32 r,
>> + u64 cpu_addr)
>
> Not used in this patch, you should split it out.
>
>> +{
>> + u32 addr0, addr1, desc0, desc1;
>> +
>> + desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG;
>> + desc1 = 0;
>> + if (pcie->is_rc) {
>> + desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
>> + CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
>> + desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(pcie->bus);
>> + }
>> +
>> + /* Set the CPU address */
>> + cpu_addr -= pcie->mem_res->start;
>> + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) |
>> + (lower_32_bits(cpu_addr) & GENMASK(31, 8));
>> + addr1 = upper_32_bits(cpu_addr);
>> +
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), 0);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), 0);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
>> +}
>> +
>> +void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r)
>> +{
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), 0);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), 0);
>> +
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), 0);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), 0);
>> +
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), 0);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), 0);
>> +}
>> diff --git a/drivers/pci/cadence/pcie-cadence.h b/drivers/pci/cadence/pcie-cadence.h
>> new file mode 100644
>> index 000000000000..195e23b7d4fe
>> --- /dev/null
>> +++ b/drivers/pci/cadence/pcie-cadence.h
>> @@ -0,0 +1,325 @@
>> +/*
>> + * Cadence PCIe controller driver.
>> + *
>> + * Copyright (c) 2017 Cadence
>> + *
>> + * Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#ifndef _PCIE_CADENCE_H
>> +#define _PCIE_CADENCE_H
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/pci.h>
>> +
>> +/*
>> + * Local Management Registers
>> + */
>> +#define CDNS_PCIE_LM_BASE 0x00100000
>> +
>> +/* Vendor ID Register */
>> +#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044)
>> +#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0)
>> +#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0
>> +#define CDNS_PCIE_LM_ID_VENDOR(vid) \
>> + (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK)
>> +#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16)
>> +#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16
>> +#define CDNS_PCIE_LM_ID_SUBSYS(sub) \
>> + (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
>> +
>> +/* Root Port Requestor ID Register */
>> +#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)
>> +#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
>> +#define CDNS_PCIE_LM_RP_RID_SHIFT 0
>> +#define CDNS_PCIE_LM_RP_RID_(rid) \
>> + (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK)
>> +
>> +/* Endpoint Bus and Device Number Register */
>> +#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c)
>> +#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0)
>> +#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0
>> +#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8)
>> +#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8
>> +
>> +/* Endpoint Function f BAR b Configuration Registers */
>> +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \
>> + (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008)
>> +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \
>> + (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008)
>> +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \
>> + (GENMASK(4, 0) << ((b) * 8))
>> +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
>> + (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))
>> +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \
>> + (GENMASK(7, 5) << ((b) * 8))
>> +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
>> + (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
>> +
>> +/* Endpoint Function Configuration Register */
>> +#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0)
>
> All endpoint defines should be moved to the patch that needs them.
>
Will move those definitions into the endpoint patch.
Thanks for the review!
Best regards,
Cyrille
>> +
>> +/* Root Complex BAR Configuration Register */
>> +#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300)
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
>> + (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK)
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \
>> + (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9)
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
>> + (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK)
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14)
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \
>> + (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK)
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17)
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18)
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19)
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20)
>> +#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31)
>> +
>> +/* BAR control values applicable to both Endpoint Function and Root Complex */
>> +#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0
>> +#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1
>> +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4
>> +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5
>> +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6
>> +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7
>> +
>> +
>> +/*
>> + * Endpoint Function Registers (PCI configuration space for endpoint functions)
>> + */
>> +#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))
>> +
>> +#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90
>> +
>> +/*
>> + * Root Port Registers (PCI configuration space for the root port function)
>> + */
>> +#define CDNS_PCIE_RP_BASE 0x00200000
>> +
>> +
>> +/*
>> + * Address Translation Registers
>> + */
>> +#define CDNS_PCIE_AT_BASE 0x00400000
>> +
>> +/* Region r Outbound AXI to PCIe Address Translation Register 0 */
>> +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
>> + (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)
>> +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
>> +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
>> + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
>> +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)
>> +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
>> + (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)
>> +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)
>> +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
>> + (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
>> +
>> +/* Region r Outbound AXI to PCIe Address Translation Register 1 */
>> +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
>> + (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)
>> +
>> +/* Region r Outbound PCIe Descriptor Register 0 */
>> +#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \
>> + (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)
>> +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0)
>> +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2
>> +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6
>> +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa
>> +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb
>> +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc
>> +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd
>> +/* Bit 23 MUST be set in RC mode. */
>> +#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23)
>> +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)
>> +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
>> + (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
>> +
>> +/* Region r Outbound PCIe Descriptor Register 1 */
>> +#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \
>> + (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020)
>> +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0)
>> +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \
>> + ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
>> +
>> +/* Region r AXI Region Base Address Register 0 */
>> +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
>> + (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)
>> +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
>> +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
>> + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
>> +
>> +/* Region r AXI Region Base Address Register 1 */
>> +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
>> + (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020)
>> +
>> +/* Root Port BAR Inbound PCIe to AXI Address Translation Register */
>> +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \
>> + (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
>> +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
>> +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
>> + (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
>> +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
>> + (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
>> +
>> +enum cdns_pcie_rp_bar {
>> + RP_BAR0,
>> + RP_BAR1,
>> + RP_NO_BAR
>> +};
>> +
>> +/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
>> +#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
>> + (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
>> +#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
>> + (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
>> +
>> +/* Normal/Vendor specific message access: offset inside some outbound region */
>> +#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5)
>> +#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \
>> + (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)
>> +#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8)
>> +#define CDNS_PCIE_NORMAL_MSG_CODE(code) \
>> + (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK)
>> +#define CDNS_PCIE_MSG_NO_DATA BIT(16)
>> +
>> +enum cdns_pcie_msg_code {
>> + MSG_CODE_ASSERT_INTA = 0x20,
>> + MSG_CODE_ASSERT_INTB = 0x21,
>> + MSG_CODE_ASSERT_INTC = 0x22,
>> + MSG_CODE_ASSERT_INTD = 0x23,
>> + MSG_CODE_DEASSERT_INTA = 0x24,
>> + MSG_CODE_DEASSERT_INTB = 0x25,
>> + MSG_CODE_DEASSERT_INTC = 0x26,
>> + MSG_CODE_DEASSERT_INTD = 0x27,
>> +};
>> +
>> +enum cdns_pcie_msg_routing {
>> + /* Route to Root Complex */
>> + MSG_ROUTING_TO_RC,
>> +
>> + /* Use Address Routing */
>> + MSG_ROUTING_BY_ADDR,
>> +
>> + /* Use ID Routing */
>> + MSG_ROUTING_BY_ID,
>> +
>> + /* Route as Broadcast Message from Root Complex */
>> + MSG_ROUTING_BCAST,
>> +
>> + /* Local message; terminate at receiver (INTx messages) */
>> + MSG_ROUTING_LOCAL,
>> +
>> + /* Gather & route to Root Complex (PME_TO_Ack message) */
>> + MSG_ROUTING_GATHER,
>> +};
>> +
>> +/**
>> + * struct cdns_pcie - private data for Cadence PCIe controller drivers
>> + * @reg_base: IO mapped register base
>> + * @mem_res: start/end offsets in the physical system memory to map PCI accesses
>> + * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
>> + * @bus: In Root Complex mode, the bus number
>> + */
>> +struct cdns_pcie {
>> + void __iomem *reg_base;
>> + struct resource *mem_res;
>> + bool is_rc;
>> + u8 bus;
>> +};
>> +
>> +/* Register access */
>> +static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value)
>> +{
>> + writeb(value, pcie->reg_base + reg);
>> +}
>> +
>> +static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value)
>> +{
>> + writew(value, pcie->reg_base + reg);
>> +}
>> +
>> +static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value)
>> +{
>> + writel(value, pcie->reg_base + reg);
>> +}
>> +
>> +static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)
>> +{
>> + return readl(pcie->reg_base + reg);
>> +}
>> +
>> +/* Root Port register access */
>> +static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie,
>> + u32 reg, u8 value)
>> +{
>> + writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
>> +}
>> +
>> +static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie,
>> + u32 reg, u16 value)
>> +{
>> + writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
>> +}
>> +
>> +/* Endpoint Function register access */
>> +static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
>> + u32 reg, u8 value)
>> +{
>> + writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
>> +}
>> +
>> +static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn,
>> + u32 reg, u16 value)
>> +{
>> + writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
>> +}
>> +
>> +static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
>> + u32 reg, u16 value)
>> +{
>> + writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
>> +}
>> +
>> +static inline u8 cdns_pcie_ep_fn_readb(struct cdns_pcie *pcie, u8 fn, u32 reg)
>> +{
>> + return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
>> +}
>> +
>> +static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg)
>> +{
>> + return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
>> +}
>> +
>> +static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)
>> +{
>> + return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
>> +}
>
> Same comments for all endpoint related functions and defines above.
>
> Thanks,
> Lorenzo
>
>> +void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u32 r, bool is_io,
>> + u64 cpu_addr, u64 pci_addr, size_t size);
>> +
>> +void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u32 r,
>> + u64 cpu_addr);
>> +
>> +void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
>> +
>> +#endif /* _PCIE_CADENCE_H */
>> --
>> 2.11.0
>>
> IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
>
--
Cyrille Pitchen, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: trivial: add tfa9879 device
From: Peter Rosin @ 2017-12-03 20:53 UTC (permalink / raw)
To: Fabio Estevam
Cc: Mark Rutland, devicetree@vger.kernel.org,
alsa-devel@alsa-project.org, Takashi Iwai, linux-kernel,
Rob Herring, Liam Girdwood, Mark Brown, Alexandre Belloni,
Russell King, linux-arm-kernel@lists.infradead.org, Nicolas Ferre
In-Reply-To: <CAOMZO5AE++an6MnagrWoL4qwkDJaqtg_qJ5UKX3PB7sw1cTeiA@mail.gmail.com>
On 2017-12-03 12:12, Fabio Estevam wrote:
> Hi Peter,
>
> On Sun, Dec 3, 2017 at 4:59 AM, Peter Rosin <peda@axentia.se> wrote:
>
>> Right. However, the patch adding that should have been sent to me, the
>> maintainer of the driver. That is carefully recorded in MAINTAINERS. So,
>> forgive me for assuming that nothing had changed in the driver behind my
>> back.
>>
>> Had that patch been sent my way as it should have been, I would have
>> insisted that maintenance of the bindings had been kept together with
>> the maintenance of the driver.
>
> When I sent this patch ./scripts/get_maintainer.pl did lot list your
> name, so that's why I did not put you on Cc, sorry.
>
> 4.15-rc1 still does not list you, but linux-next does.
That's funny, because I get the below on both 4.14 and 4.15-rc1. And I
expect the same ever since the driver was added some 3 years ago.
$ scripts/get_maintainer.pl your-patch-from[1].diff | grep Peter
Peter Rosin <peda@axentia.se> (maintainer:NXP TFA9879 DRIVER)
[1] https://patchwork.ozlabs.org/patch/815930/
By the way, scripts/checkpatch.pl on that patch reports
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
> Would you like me to send the following patch so that new binding
> updates go to you?
Naahh, I'll claim it myself, that way I can clean up some nits in the
actual file while at it...
Cheers,
Peter
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -9808,6 +9808,7 @@ NXP TFA9879 DRIVER
> M: Peter Rosin <peda@axentia.se>
> L: alsa-devel@alsa-project.org (moderated for non-subscribers)
> S: Maintained
> +F: Documentation/devicetree/bindings/sound/tfa9879.txt
> F: sound/soc/codecs/tfa9879*
>
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: trivial: add tfa9879 device
From: Fabio Estevam @ 2017-12-03 21:01 UTC (permalink / raw)
To: Peter Rosin
Cc: linux-kernel, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org, Liam Girdwood,
Mark Brown, Takashi Iwai, Nicolas Ferre, Russell King,
Rob Herring, Alexandre Belloni,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <5ec7ae30-eeac-3cf8-15ad-f6c3a110c5d7-koto5C5qi+TLoDKTGw+V6w@public.gmane.org>
On Sun, Dec 3, 2017 at 6:53 PM, Peter Rosin <peda-koto5C5qi+TLoDKTGw+V6w@public.gmane.org> wrote:
> That's funny, because I get the below on both 4.14 and 4.15-rc1. And I
> expect the same ever since the driver was added some 3 years ago.
>
> $ scripts/get_maintainer.pl your-patch-from[1].diff | grep Peter
> Peter Rosin <peda-koto5C5qi+TLoDKTGw+V6w@public.gmane.org> (maintainer:NXP TFA9879 DRIVER)
You are right.
I tried ./scripts/get_maintainer.pl
Documentation/devicetree/bindings/sound/tfa9879.txt
in 4.15-rc1.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH] dt-bindings: mtd: fsl-quadspi: Pass the qspi clock names
From: Fabio Estevam @ 2017-12-03 22:36 UTC (permalink / raw)
To: boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8
Cc: cyrille.pitchen-yU5RGvR974pGWvitb5QawA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
Fabio Estevam
From: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
In order to improve the bindings documentation, explicitly pass the name
of the clocks: "qspi_en" and "qspi", which are mandatory.
Signed-off-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
---
Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index c34aa6f..cc3f579 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -12,7 +12,7 @@ Required properties:
- reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
- interrupts : Should contain the interrupt for the device
- clocks : The clocks needed by the QuadSPI controller
- - clock-names : the name of the clocks
+ - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi".
Optional properties:
- fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B.
--
2.7.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH 08/12] ARM: dts: imx6qdl-apalis: Remove unneeded reg property
From: Marcel Ziswiler @ 2017-12-03 22:48 UTC (permalink / raw)
To: festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
fabio.estevam-3arQi8VN3Tc@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1512156285-18451-8-git-send-email-festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Thanks Fabio for catching that one!
On Fri, 2017-12-01 at 17:24 -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@nxp.com>
>
> As described in
> Documentation/devicetree/bindings/input/touchscreen/stmpe.txt
> there is no 'reg' property under stmpe_touchscreen, so remove it
> to fix the following build warning with W=1:
>
> arch/arm/boot/dts/imx6q-apalis-eval.dtb: Warning
> (unit_address_vs_reg): Node /soc/aips-bus@2100000/i2c@21a4000/stmpe81
> 1@41/stmpe_touchscreen has a reg or ranges property, but no unit name
>
> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
> arch/arm/boot/dts/imx6qdl-apalis.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> index e80fdca..4e776e0 100644
> --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> @@ -338,7 +338,6 @@
>
> stmpe_touchscreen {
> compatible = "st,stmpe-ts";
> - reg = <0>;
> /* 3.25 MHz ADC clock speed */
> st,adc-freq = <1>;
> /* 8 sample average control */
^ permalink raw reply
* Re: [PATCH v4 07/12] [media] cxd2880: Add top level of the driver
From: Sean Young @ 2017-12-03 22:59 UTC (permalink / raw)
To: Yasunari.Takiguchi-7U/KSKJipcs
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-media-u79uwXL29TY76Z2rM5mHXA,
tbird20d-Re5JQEeQqe8AvxtiuMwx3w,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, Masayuki Yamamoto,
Hideki Nozawa, Kota Yonezawa, Toshihiko Matsumoto,
Satoshi Watanabe
In-Reply-To: <20171013060934.21612-1-Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
Hello,
Many thanks for the driver.
The ./scripts/checkpatch.pl with --strict has many warnings, some of which might
be nice to have cleaned up.
There are some very minor comments below. Similar constructs are in other files too.
After reading and understanding through all the code, I think the driver looks
very good, and is ready for merging except for the minor things listed.
Thank you for your submission.
Regards,
Sean
On Fri, Oct 13, 2017 at 03:09:34PM +0900, Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org wrote:
> From: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
>
> This provides the main dvb frontend operation functions
> for the Sony CXD2880 DVB-T2/T tuner + demodulator driver.
>
> Signed-off-by: Yasunari Takiguchi <Yasunari.Takiguchi-7U/KSKJipcs@public.gmane.org>
> Signed-off-by: Masayuki Yamamoto <Masayuki.Yamamoto-7U/KSKJipcs@public.gmane.org>
> Signed-off-by: Hideki Nozawa <Hideki.Nozawa-7U/KSKJipcs@public.gmane.org>
> Signed-off-by: Kota Yonezawa <Kota.Yonezawa-7U/KSKJipcs@public.gmane.org>
> Signed-off-by: Toshihiko Matsumoto <Toshihiko.Matsumoto-7U/KSKJipcs@public.gmane.org>
> Signed-off-by: Satoshi Watanabe <Satoshi.C.Watanabe-7U/KSKJipcs@public.gmane.org>
> ---
>
> [Change list]
> Changes in V4
> drivers/media/dvb-frontends/cxd2880/cxd2880_top.c
> -modified typo "inavlid" to "invalid" at pr_err
> -removed unnecessary initialization at variable declaration
> -removed unnecessary brace {}
> -changed to use cxd2880_dvbt_tune and cxd2880_dvbt2_tune
> instead of cxd2880_integ_dvbt_tune and cxd2880_integ_dvbt2_tune
> (because we changed it so that demodulator does not
> wait for locking the signal.)
>
> Changes in V3
> drivers/media/dvb-frontends/cxd2880/cxd2880_top.c
> -adjusted indent spaces
> -modified debugging code
> -removed unnecessary cast
> -modified return code
> -modified coding style of if()
> -modified about measurement period of PER/BER.
> -changed hexadecimal code to lower case.
>
> drivers/media/dvb-frontends/cxd2880/cxd2880_top.c | 2019 +++++++++++++++++++++
> 1 file changed, 2019 insertions(+)
> create mode 100644 drivers/media/dvb-frontends/cxd2880/cxd2880_top.c
>
> diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c b/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c
> new file mode 100644
> index 000000000000..c82aaf0c1597
> --- /dev/null
> +++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c
> @@ -0,0 +1,2019 @@
> +/*
> + * cxd2880_top.c
> + * Sony CXD2880 DVB-T2/T tuner + demodulator driver
> + *
> + * Copyright (C) 2016, 2017 Sony Semiconductor Solutions Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; version 2 of the License.
> + *
> + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
> + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
> + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
> + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
> + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
> + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
> + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__
> +
> +#include <linux/spi/spi.h>
> +
> +#include "dvb_frontend.h"
> +#include "dvb_math.h"
> +
> +#include "cxd2880.h"
> +#include "cxd2880_tnrdmd_mon.h"
> +#include "cxd2880_tnrdmd_dvbt2_mon.h"
> +#include "cxd2880_tnrdmd_dvbt_mon.h"
> +#include "cxd2880_integ.h"
> +#include "cxd2880_tnrdmd_dvbt2.h"
> +#include "cxd2880_tnrdmd_dvbt.h"
> +#include "cxd2880_devio_spi.h"
> +#include "cxd2880_spi_device.h"
> +#include "cxd2880_tnrdmd_driver_version.h"
> +
> +struct cxd2880_priv {
> + struct cxd2880_tnrdmd tnrdmd;
> + struct spi_device *spi;
> + struct cxd2880_io regio;
> + struct cxd2880_spi_device spi_device;
> + struct cxd2880_spi cxd2880_spi;
> + struct cxd2880_dvbt_tune_param dvbt_tune_param;
> + struct cxd2880_dvbt2_tune_param dvbt2_tune_param;
> + struct mutex *spi_mutex; /* For SPI access exclusive control */
> + unsigned long pre_ber_update;
> + unsigned long pre_ber_interval;
> + unsigned long post_ber_update;
> + unsigned long post_ber_interval;
> + unsigned long ucblock_update;
> + unsigned long ucblock_interval;
> + enum fe_status s;
> +};
> +
> +static int cxd2880_pre_bit_err_t(
> + struct cxd2880_tnrdmd *tnrdmd, u32 *pre_bit_err,
> + u32 *pre_bit_count)
> +{
> + u8 rdata[2];
> + int ret;
> +
> + if ((!tnrdmd) || (!pre_bit_err) || (!pre_bit_count))
> + return -EINVAL;
> +
> + if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
> + return -EINVAL;
divermode: this should say drivermode, correct?
> +
> + if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
> + return -EPERM;
> +
> + if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
> + return -EPERM;
> +
> + ret = slvt_freeze_reg(tnrdmd);
> + if (ret)
> + return ret;
> +
> + ret = tnrdmd->io->write_reg(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x00, 0x10);
> + if (ret) {
> + slvt_unfreeze_reg(tnrdmd);
> + return ret;
> + }
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x39, rdata, 1);
> + if (ret) {
> + slvt_unfreeze_reg(tnrdmd);
> + return ret;
> + }
> +
> + if ((rdata[0] & 0x01) == 0) {
> + slvt_unfreeze_reg(tnrdmd);
> + return -EBUSY;
> + }
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x22, rdata, 2);
> + if (ret) {
> + slvt_unfreeze_reg(tnrdmd);
> + return ret;
> + }
> +
> + *pre_bit_err = (rdata[0] << 8) | rdata[1];
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x6f, rdata, 1);
> + if (ret) {
> + slvt_unfreeze_reg(tnrdmd);
> + return ret;
> + }
> +
> + slvt_unfreeze_reg(tnrdmd);
> +
> + *pre_bit_count = ((rdata[0] & 0x07) == 0) ?
> + 256 : (0x1000 << (rdata[0] & 0x07));
> +
> + return 0;
> +}
> +
> +static int cxd2880_pre_bit_err_t2(struct cxd2880_tnrdmd *tnrdmd,
> + u32 *pre_bit_err,
> + u32 *pre_bit_count)
> +{
> + u32 period_exp = 0;
> + u32 n_ldpc = 0;
> + u8 data[5];
> + int ret;
> +
> + if ((!tnrdmd) || (!pre_bit_err) || (!pre_bit_count))
> + return -EINVAL;
> +
> + if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
> + return -EINVAL;
> +
> + if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
> + return -EPERM;
> +
> + if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
> + return -EPERM;
> +
> + ret = slvt_freeze_reg(tnrdmd);
> + if (ret)
> + return ret;
> +
> + ret = tnrdmd->io->write_reg(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x00, 0x0b);
> + if (ret) {
> + slvt_unfreeze_reg(tnrdmd);
> + return ret;
> + }
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x3c, data, sizeof(data));
> + if (ret) {
> + slvt_unfreeze_reg(tnrdmd);
> + return ret;
> + }
> +
> + if (!(data[0] & 0x01)) {
> + slvt_unfreeze_reg(tnrdmd);
> + return -EBUSY;
> + }
> + *pre_bit_err =
> + ((data[1] & 0x0f) << 24) | (data[2] << 16) | (data[3] << 8) | data[4];
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0xa0, data, 1);
> + if (ret) {
> + slvt_unfreeze_reg(tnrdmd);
> + return ret;
> + }
> +
> + if (((enum cxd2880_dvbt2_plp_fec)(data[0] & 0x03)) ==
> + CXD2880_DVBT2_FEC_LDPC_16K)
> + n_ldpc = 16200;
> + else
> + n_ldpc = 64800;
> + slvt_unfreeze_reg(tnrdmd);
> +
> + ret = tnrdmd->io->write_reg(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x00, 0x20);
> + if (ret)
> + return ret;
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x6f, data, 1);
> + if (ret)
> + return ret;
> +
> + period_exp = data[0] & 0x0f;
> +
> + *pre_bit_count = (1U << period_exp) * n_ldpc;
> +
> + return 0;
> +}
> +
> +static int cxd2880_post_bit_err_t(struct cxd2880_tnrdmd *tnrdmd,
> + u32 *post_bit_err,
> + u32 *post_bit_count)
> +{
> + u8 rdata[3];
> + u32 bit_error = 0;
> + u32 period_exp = 0;
> + int ret;
> +
> + if ((!tnrdmd) || (!post_bit_err) || (!post_bit_count))
> + return -EINVAL;
> +
> + if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
> + return -EINVAL;
> +
> + if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
> + return -EPERM;
> +
> + if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
> + return -EPERM;
> +
> + ret = tnrdmd->io->write_reg(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x00, 0x0d);
> + if (ret)
> + return ret;
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x15, rdata, 3);
> + if (ret)
> + return ret;
> +
> + if ((rdata[0] & 0x40) == 0)
> + return -EBUSY;
> +
> + *post_bit_err = ((rdata[0] & 0x3f) << 16) | (rdata[1] << 8) | rdata[2];
> +
> + ret = tnrdmd->io->write_reg(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x00, 0x10);
> + if (ret)
> + return ret;
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x60, rdata, 1);
> + if (ret)
> + return ret;
> +
> + period_exp = (rdata[0] & 0x1f);
> +
> + if ((period_exp <= 11) && (bit_error > (1U << period_exp) * 204 * 8))
> + return -EBUSY;
> +
> + if (period_exp == 11)
> + *post_bit_count = 3342336;
> + else
> + *post_bit_count = (1U << period_exp) * 204 * 81;
> +
> + return 0;
> +}
> +
> +static int cxd2880_post_bit_err_t2(struct cxd2880_tnrdmd *tnrdmd,
> + u32 *post_bit_err,
> + u32 *post_bit_count)
> +{
> + u32 period_exp = 0;
> + u32 n_bch = 0;
> + u8 data[3];
> + enum cxd2880_dvbt2_plp_fec plp_fec_type =
> + CXD2880_DVBT2_FEC_LDPC_16K;
> + enum cxd2880_dvbt2_plp_code_rate plp_code_rate =
> + CXD2880_DVBT2_R1_2;
> + int ret;
> + static const u16 n_bch_bits_lookup[2][8] = {
> + {7200, 9720, 10800, 11880, 12600, 13320, 5400, 6480},
> + {32400, 38880, 43200, 48600, 51840, 54000, 21600, 25920}
> + };
> +
> + if ((!tnrdmd) || (!post_bit_err) || (!post_bit_count))
> + return -EINVAL;
> +
> + if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
> + return -EINVAL;
> +
> + if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
> + return -EPERM;
> +
> + if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
> + return -EPERM;
> +
> + ret = slvt_freeze_reg(tnrdmd);
> + if (ret)
> + return ret;
> +
> + ret = tnrdmd->io->write_reg(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x00, 0x0b);
> + if (ret) {
> + slvt_unfreeze_reg(tnrdmd);
> + return ret;
> + }
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x15, data, 3);
> + if (ret) {
> + slvt_unfreeze_reg(tnrdmd);
> + return ret;
> + }
> +
> + if (!(data[0] & 0x40)) {
> + slvt_unfreeze_reg(tnrdmd);
> + return -EBUSY;
> + }
> +
> + *post_bit_err =
> + ((data[0] & 0x3f) << 16) | (data[1] << 8) | data[2];
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x9d, data, 1);
> + if (ret) {
> + slvt_unfreeze_reg(tnrdmd);
> + return ret;
> + }
> +
> + plp_code_rate =
> + (enum cxd2880_dvbt2_plp_code_rate)(data[0] & 0x07);
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0xa0, data, 1);
> + if (ret) {
> + slvt_unfreeze_reg(tnrdmd);
> + return ret;
> + }
> +
> + plp_fec_type = (enum cxd2880_dvbt2_plp_fec)(data[0] & 0x03);
> +
> + slvt_unfreeze_reg(tnrdmd);
> +
> + ret = tnrdmd->io->write_reg(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x00, 0x20);
> + if (ret)
> + return ret;
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x72, data, 1);
> + if (ret)
> + return ret;
> +
> + period_exp = data[0] & 0x0f;
> +
> + if ((plp_fec_type > CXD2880_DVBT2_FEC_LDPC_64K) ||
> + (plp_code_rate > CXD2880_DVBT2_R2_5))
> + return -EBUSY;
> +
> + n_bch = n_bch_bits_lookup[plp_fec_type][plp_code_rate];
> +
> + if (*post_bit_err > ((1U << period_exp) * n_bch))
> + return -EBUSY;
> +
> + *post_bit_count = (1U << period_exp) * n_bch;
> +
> + return 0;
> +}
> +
> +static int cxd2880_read_block_err_t(struct cxd2880_tnrdmd *tnrdmd,
> + u32 *block_err,
> + u32 *block_count)
> +{
> + u8 rdata[3];
> + int ret;
> +
> + if ((!tnrdmd) || (!block_err) || (!block_count))
> + return -EINVAL;
> +
> + if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
> + return -EINVAL;
> +
> + if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
> + return -EPERM;
> +
> + if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
> + return -EPERM;
> +
> + ret = tnrdmd->io->write_reg(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x00, 0x0d);
> + if (ret)
> + return ret;
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x18, rdata, 3);
> + if (ret)
> + return ret;
> +
> + if ((rdata[0] & 0x01) == 0)
> + return -EBUSY;
> +
> + *block_err = (rdata[1] << 8) | rdata[2];
> +
> + ret = tnrdmd->io->write_reg(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x00, 0x10);
> + if (ret)
> + return ret;
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x5c, rdata, 1);
> + if (ret)
> + return ret;
> +
> + *block_count = 1U << (rdata[0] & 0x0f);
> +
> + if ((*block_count == 0) || (*block_err > *block_count))
> + return -EBUSY;
> +
> + return 0;
> +}
> +
> +static int cxd2880_read_block_err_t2(struct cxd2880_tnrdmd *tnrdmd,
> + u32 *block_err,
> + u32 *block_count)
> +{
> + u8 rdata[3];
> + int ret;
> +
> + if ((!tnrdmd) || (!block_err) || (!block_count))
> + return -EINVAL;
> +
> + if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
> + return -EINVAL;
> +
> + if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
> + return -EPERM;
> + if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
> + return -EPERM;
> +
> + ret = tnrdmd->io->write_reg(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x00, 0x0b);
> + if (ret)
> + return ret;
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x18, rdata, 3);
> + if (ret)
> + return ret;
> +
> + if ((rdata[0] & 0x01) == 0)
> + return -EBUSY;
> +
> + *block_err = (rdata[1] << 8) | rdata[2];
> +
> + ret = tnrdmd->io->write_reg(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x00, 0x24);
> + if (ret)
> + return ret;
> +
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0xdc, rdata, 1);
> + if (ret)
> + return ret;
> +
> + *block_count = 1U << (rdata[0] & 0x0f);
> +
> + if ((*block_count == 0) || (*block_err > *block_count))
> + return -EBUSY;
> +
> + return 0;
> +}
> +
> +static void cxd2880_release(struct dvb_frontend *fe)
> +{
> + struct cxd2880_priv *priv = NULL;
> +
> + if (!fe) {
> + pr_err("invalid arg.\n");
> + return;
> + }
> + priv = fe->demodulator_priv;
> + kfree(priv);
> +}
> +
> +static int cxd2880_init(struct dvb_frontend *fe)
> +{
> + int ret;
> + struct cxd2880_priv *priv = NULL;
> + struct cxd2880_tnrdmd_create_param create_param;
> +
> + if (!fe) {
> + pr_err("invalid arg.\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> +
> + create_param.ts_output_if = CXD2880_TNRDMD_TSOUT_IF_SPI;
> + create_param.xtal_share_type = CXD2880_TNRDMD_XTAL_SHARE_NONE;
> + create_param.en_internal_ldo = 1;
> + create_param.xosc_cap = 18;
> + create_param.xosc_i = 8;
> + create_param.stationary_use = 1;
> +
> + mutex_lock(priv->spi_mutex);
> + if (priv->tnrdmd.io != &priv->regio) {
> + ret = cxd2880_tnrdmd_create(&priv->tnrdmd,
> + &priv->regio, &create_param);
> + if (ret) {
> + mutex_unlock(priv->spi_mutex);
> + pr_info("cxd2880 tnrdmd create failed %d\n", ret);
> + return ret;
> + }
> + }
> + ret = cxd2880_integ_init(&priv->tnrdmd);
> + if (ret) {
> + mutex_unlock(priv->spi_mutex);
> + pr_err("cxd2880 integ init failed %d\n", ret);
> + return ret;
> + }
> + mutex_unlock(priv->spi_mutex);
> +
> + pr_debug("OK.\n");
> +
> + return ret;
> +}
> +
> +static int cxd2880_sleep(struct dvb_frontend *fe)
> +{
> + int ret;
> + struct cxd2880_priv *priv = NULL;
> +
> + if (!fe) {
> + pr_err("invalid arg\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> +
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_tnrdmd_sleep(&priv->tnrdmd);
> + mutex_unlock(priv->spi_mutex);
> +
> + pr_debug("tnrdmd_sleep ret %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int cxd2880_read_signal_strength(struct dvb_frontend *fe,
> + u16 *strength)
> +{
> + int ret;
> + struct cxd2880_priv *priv = NULL;
> + struct dtv_frontend_properties *c = NULL;
> + int level = 0;
> +
> + if ((!fe) || (!strength)) {
> + pr_err("invalid arg\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> + c = &fe->dtv_property_cache;
> +
> + mutex_lock(priv->spi_mutex);
> + if ((c->delivery_system == SYS_DVBT) ||
> + (c->delivery_system == SYS_DVBT2)) {
> + ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &level);
> + } else {
> + pr_debug("invalid system\n");
> + mutex_unlock(priv->spi_mutex);
> + return -EINVAL;
> + }
> + mutex_unlock(priv->spi_mutex);
> +
> + level /= 125;
> + /*
> + * level should be between -105dBm and -30dBm.
> + * E.g. they should be between:
> + * -105000/125 = -840 and -30000/125 = -240
> + */
> + level = clamp(level, -840, -240);
> + /* scale value to 0x0000-0xffff */
> + *strength = (u16)(((level + 840) * 0xffff) / (-240 + 840));
The cast is not necessary, the implicit cast will do fine.
> +
> + if (ret)
> + pr_debug("ret = %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int cxd2880_read_snr(struct dvb_frontend *fe, u16 *snr)
> +{
> + int ret;
> + int snrvalue = 0;
> + struct cxd2880_priv *priv = NULL;
> + struct dtv_frontend_properties *c = NULL;
> +
> + if ((!fe) || (!snr)) {
> + pr_err("invalid arg\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> + c = &fe->dtv_property_cache;
> +
> + mutex_lock(priv->spi_mutex);
> + if (c->delivery_system == SYS_DVBT) {
> + ret = cxd2880_tnrdmd_dvbt_mon_snr(&priv->tnrdmd,
> + &snrvalue);
> + } else if (c->delivery_system == SYS_DVBT2) {
> + ret = cxd2880_tnrdmd_dvbt2_mon_snr(&priv->tnrdmd,
> + &snrvalue);
> + } else {
> + pr_err("invalid system\n");
> + mutex_unlock(priv->spi_mutex);
> + return -EINVAL;
> + }
> + mutex_unlock(priv->spi_mutex);
> +
> + if (snrvalue < 0)
> + snrvalue = 0;
> + *snr = (u16)snrvalue;
Again cast not necessary.
> +
> + if (ret)
> + pr_debug("ret = %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int cxd2880_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
> +{
> + int ret;
> + struct cxd2880_priv *priv = NULL;
> + struct dtv_frontend_properties *c = NULL;
> +
> + if ((!fe) || (!ucblocks)) {
> + pr_err("invalid arg\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> + c = &fe->dtv_property_cache;
> +
> + mutex_lock(priv->spi_mutex);
> + if (c->delivery_system == SYS_DVBT) {
> + ret = cxd2880_tnrdmd_dvbt_mon_packet_error_number(
> + &priv->tnrdmd,
> + ucblocks);
> + } else if (c->delivery_system == SYS_DVBT2) {
> + ret = cxd2880_tnrdmd_dvbt2_mon_packet_error_number(
> + &priv->tnrdmd,
> + ucblocks);
> + } else {
> + pr_err("invalid system\n");
> + mutex_unlock(priv->spi_mutex);
> + return -EINVAL;
> + }
> + mutex_unlock(priv->spi_mutex);
> +
> + if (ret)
> + pr_debug("ret = %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int cxd2880_read_ber(struct dvb_frontend *fe, u32 *ber)
> +{
> + int ret;
> + struct cxd2880_priv *priv = NULL;
> + struct dtv_frontend_properties *c = NULL;
> +
> + if ((!fe) || (!ber)) {
> + pr_err("invalid arg\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> + c = &fe->dtv_property_cache;
> +
> + mutex_lock(priv->spi_mutex);
> + if (c->delivery_system == SYS_DVBT) {
> + ret = cxd2880_tnrdmd_dvbt_mon_pre_rsber(&priv->tnrdmd,
> + ber);
> + /* x100 to change unit.(10^7 -> 10^9) */
> + *ber *= 100;
> + } else if (c->delivery_system == SYS_DVBT2) {
> + ret = cxd2880_tnrdmd_dvbt2_mon_pre_bchber(&priv->tnrdmd,
> + ber);
> + } else {
> + pr_err("invalid system\n");
> + mutex_unlock(priv->spi_mutex);
> + return -EINVAL;
> + }
> + mutex_unlock(priv->spi_mutex);
> +
> + if (ret)
> + pr_debug("ret = %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int cxd2880_set_ber_per_period_t(struct dvb_frontend *fe)
> +{
> + int ret;
> + struct dtv_frontend_properties *c;
> + struct cxd2880_priv *priv;
> + struct cxd2880_dvbt_tpsinfo info;
> + enum cxd2880_dtv_bandwidth bw = CXD2880_DTV_BW_1_7_MHZ;
> + u32 pre_ber_rate = 0;
> + u32 post_ber_rate = 0;
> + u32 ucblock_rate = 0;
> + u32 mes_exp = 0;
> + static const int cr_table[5] = {31500, 42000, 47250, 52500, 55125};
> + static const int denominator_tbl[4] = {125664, 129472, 137088, 152320};
> +
> + if (!fe) {
> + pr_err("invalid arg\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> + c = &fe->dtv_property_cache;
> + bw = priv->dvbt_tune_param.bandwidth;
> +
> + ret = cxd2880_tnrdmd_dvbt_mon_tps_info(&priv->tnrdmd,
> + &info);
> + if (ret) {
> + pr_err("tps monitor error ret = %d\n", ret);
> + info.hierarchy = CXD2880_DVBT_HIERARCHY_NON;
> + info.constellation = CXD2880_DVBT_CONSTELLATION_QPSK;
> + info.guard = CXD2880_DVBT_GUARD_1_4;
> + info.rate_hp = CXD2880_DVBT_CODERATE_1_2;
> + info.rate_lp = CXD2880_DVBT_CODERATE_1_2;
> + }
> +
> + if (info.hierarchy == CXD2880_DVBT_HIERARCHY_NON) {
> + pre_ber_rate = 63000000 * bw * (info.constellation * 2 + 2) /
> + denominator_tbl[info.guard];
> +
> + post_ber_rate = 1000 * cr_table[info.rate_hp] * bw *
> + (info.constellation * 2 + 2) /
> + denominator_tbl[info.guard];
> +
> + ucblock_rate = 875 * cr_table[info.rate_hp] * bw *
> + (info.constellation * 2 + 2) /
> + denominator_tbl[info.guard];
> + } else {
> + u8 data = 0;
> + struct cxd2880_tnrdmd *tnrdmd = &priv->tnrdmd;
> +
> + ret = tnrdmd->io->write_reg(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x00, 0x10);
> + if (!ret) {
> + ret = tnrdmd->io->read_regs(tnrdmd->io,
> + CXD2880_IO_TGT_DMD,
> + 0x67, &data, 1);
> + if (ret)
> + data = 0x00;
> + } else {
> + data = 0x00;
> + }
> +
> + if (data & 0x01) { /* Low priority */
> + pre_ber_rate =
> + 63000000 * bw * (info.constellation * 2 + 2) /
> + denominator_tbl[info.guard];
> +
> + post_ber_rate = 1000 * cr_table[info.rate_lp] * bw *
> + (info.constellation * 2 + 2) /
> + denominator_tbl[info.guard];
> +
> + ucblock_rate = (1000 * 7 / 8) * cr_table[info.rate_lp] *
> + bw * (info.constellation * 2 + 2) /
> + denominator_tbl[info.guard];
> + } else { /* High priority */
> + pre_ber_rate =
> + 63000000 * bw * 2 / denominator_tbl[info.guard];
> +
> + post_ber_rate = 1000 * cr_table[info.rate_hp] * bw * 2 /
> + denominator_tbl[info.guard];
> +
> + ucblock_rate = (1000 * 7 / 8) * cr_table[info.rate_hp] *
> + bw * 2 / denominator_tbl[info.guard];
> + }
> + }
> +
> + mes_exp = pre_ber_rate < 8192 ? 8 : intlog2(pre_ber_rate) >> 24;
> + priv->pre_ber_interval =
> + ((1U << mes_exp) * 1000 + (pre_ber_rate / 2)) /
> + pre_ber_rate;
> + cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
> + CXD2880_TNRDMD_CFG_DVBT_VBER_PERIOD,
> + mes_exp == 8 ? 0 : mes_exp - 12);
> +
> + mes_exp = intlog2(post_ber_rate) >> 24;
> + priv->post_ber_interval =
> + ((1U << mes_exp) * 1000 + (post_ber_rate / 2)) /
> + post_ber_rate;
> + cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
> + CXD2880_TNRDMD_CFG_DVBT_BERN_PERIOD,
> + mes_exp);
> +
> + mes_exp = intlog2(ucblock_rate) >> 24;
> + priv->ucblock_interval =
> + ((1U << mes_exp) * 1000 + (ucblock_rate / 2)) /
> + ucblock_rate;
> + cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
> + CXD2880_TNRDMD_CFG_DVBT_PER_MES,
> + mes_exp);
> +
> + return 0;
> +}
> +
> +static int cxd2880_set_ber_per_period_t2(struct dvb_frontend *fe)
> +{
> + int ret;
> + struct dtv_frontend_properties *c;
> + struct cxd2880_priv *priv;
> + struct cxd2880_dvbt2_l1pre l1pre;
> + struct cxd2880_dvbt2_l1post l1post;
> + struct cxd2880_dvbt2_plp plp;
> + struct cxd2880_dvbt2_bbheader bbheader;
> + enum cxd2880_dtv_bandwidth bw = CXD2880_DTV_BW_1_7_MHZ;
> + u32 pre_ber_rate = 0;
> + u32 post_ber_rate = 0;
> + u32 ucblock_rate = 0;
> + u32 mes_exp = 0;
> + u32 term_a = 0;
> + u32 term_b = 0;
> + u32 denominator = 0;
> + static const u32 gi_tbl[7] = {32, 64, 128, 256, 8, 152, 76};
> + static const u8 n_tbl[6] = {8, 2, 4, 16, 1, 1};
> + static const u8 mode_tbl[6] = {2, 8, 4, 1, 16, 32};
> + static const u32 kbch_tbl[2][8] = {
> + {6952, 9472, 10552, 11632, 12352, 13072, 5152, 6232},
> + {32128, 38608, 42960, 48328, 51568, 53760, 0, 0}
> + };
> +
> + if (!fe) {
> + pr_err("invalid arg\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> + c = &fe->dtv_property_cache;
> + bw = priv->dvbt2_tune_param.bandwidth;
> +
> + ret = cxd2880_tnrdmd_dvbt2_mon_l1_pre(&priv->tnrdmd, &l1pre);
> + if (ret) {
> + pr_info("l1 pre error\n");
> + goto error_ber_setting;
> + }
> +
> + ret = cxd2880_tnrdmd_dvbt2_mon_active_plp(&priv->tnrdmd,
> + CXD2880_DVBT2_PLP_DATA, &plp);
> + if (ret) {
> + pr_info("plp info error\n");
> + goto error_ber_setting;
> + }
> +
> + ret = cxd2880_tnrdmd_dvbt2_mon_l1_post(&priv->tnrdmd, &l1post);
> + if (ret) {
> + pr_info("l1 post error\n");
> + goto error_ber_setting;
> + }
> +
> + term_a =
> + (mode_tbl[l1pre.fft_mode] * (1024 + gi_tbl[l1pre.gi])) *
> + (l1pre.num_symbols + n_tbl[l1pre.fft_mode]) + 2048;
> +
> + if (l1pre.mixed && l1post.fef_intvl) {
> + term_b = (l1post.fef_length + (l1post.fef_intvl / 2)) /
> + l1post.fef_intvl;
> + } else {
> + term_b = 0;
> + }
> +
> + switch (bw) {
> + case CXD2880_DTV_BW_1_7_MHZ:
> + denominator = ((term_a + term_b) * 71 + (131 / 2)) / 131;
> + break;
> + case CXD2880_DTV_BW_5_MHZ:
> + denominator = ((term_a + term_b) * 7 + 20) / 40;
> + break;
> + case CXD2880_DTV_BW_6_MHZ:
> + denominator = ((term_a + term_b) * 7 + 24) / 48;
> + break;
> + case CXD2880_DTV_BW_7_MHZ:
> + denominator = ((term_a + term_b) + 4) / 8;
> + break;
> + case CXD2880_DTV_BW_8_MHZ:
> + default:
> + denominator = ((term_a + term_b) * 7 + 32) / 64;
> + break;
> + }
> +
> + if (plp.til_type && plp.til_len) {
> + pre_ber_rate =
> + (plp.num_blocks_max * 1000000 + (denominator / 2)) /
> + denominator;
> + pre_ber_rate = (pre_ber_rate + (plp.til_len / 2)) /
> + plp.til_len;
> + } else {
> + pre_ber_rate =
> + (plp.num_blocks_max * 1000000 + (denominator / 2)) /
> + denominator;
> + }
> +
> + post_ber_rate = pre_ber_rate;
> +
> + mes_exp = intlog2(pre_ber_rate) >> 24;
> + priv->pre_ber_interval =
> + ((1U << mes_exp) * 1000 + (pre_ber_rate / 2)) /
> + pre_ber_rate;
> + cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
> + CXD2880_TNRDMD_CFG_DVBT2_LBER_MES,
> + mes_exp);
> +
> + mes_exp = intlog2(post_ber_rate) >> 24;
> + priv->post_ber_interval =
> + ((1U << mes_exp) * 1000 + (post_ber_rate / 2)) /
> + post_ber_rate;
> + cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
> + CXD2880_TNRDMD_CFG_DVBT2_BBER_MES,
> + mes_exp);
> +
> + ret = cxd2880_tnrdmd_dvbt2_mon_bbheader(&priv->tnrdmd,
> + CXD2880_DVBT2_PLP_DATA,
> + &bbheader);
> + if (ret) {
> + pr_info("bb header error\n");
> + goto error_ucblock_setting;
> + }
> +
> + if (bbheader.plp_mode == CXD2880_DVBT2_PLP_MODE_NM) {
> + if (!bbheader.issy_indicator) {
> + ucblock_rate =
> + (pre_ber_rate * kbch_tbl[plp.fec][plp.plp_cr] +
> + 752) / 1504;
> + } else {
> + ucblock_rate =
> + (pre_ber_rate * kbch_tbl[plp.fec][plp.plp_cr] +
> + 764) / 1528;
> + }
> + } else if (bbheader.plp_mode == CXD2880_DVBT2_PLP_MODE_HEM) {
> + ucblock_rate =
> + (pre_ber_rate * kbch_tbl[plp.fec][plp.plp_cr] + 748) /
> + 1496;
> + } else {
> + pr_info("plp mode is not Normal or HEM\n");
> + goto error_ucblock_setting;
> + }
> +
> + mes_exp = intlog2(ucblock_rate) >> 24;
> + priv->ucblock_interval =
> + ((1U << mes_exp) * 1000 + (ucblock_rate / 2)) /
> + ucblock_rate;
> + cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
> + CXD2880_TNRDMD_CFG_DVBT2_PER_MES,
> + mes_exp);
> +
> + return 0;
> +
> +error_ber_setting:
> + priv->pre_ber_interval = 1000;
> + cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
> + CXD2880_TNRDMD_CFG_DVBT2_LBER_MES, 0);
> +
> + priv->post_ber_interval = 1000;
> + cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
> + CXD2880_TNRDMD_CFG_DVBT2_BBER_MES, 0);
> +
> +error_ucblock_setting:
> + priv->ucblock_interval = 1000;
> + cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
> + CXD2880_TNRDMD_CFG_DVBT2_PER_MES, 8);
> +
> + return 0;
> +}
> +
> +static int cxd2880_dvbt_tune(struct cxd2880_tnrdmd *tnr_dmd,
> + struct cxd2880_dvbt_tune_param
> + *tune_param)
> +{
> + int ret;
> +
> + if ((!tnr_dmd) || (!tune_param))
> + return -EINVAL;
> +
> + if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
> + return -EINVAL;
> +
> + if ((tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP) &&
> + (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE))
> + return -EPERM;
> +
> + atomic_set(&tnr_dmd->cancel, 0);
> +
> + if ((tune_param->bandwidth != CXD2880_DTV_BW_5_MHZ) &&
> + (tune_param->bandwidth != CXD2880_DTV_BW_6_MHZ) &&
> + (tune_param->bandwidth != CXD2880_DTV_BW_7_MHZ) &&
> + (tune_param->bandwidth != CXD2880_DTV_BW_8_MHZ)) {
> + return -EOPNOTSUPP;
> + }
> +
> + ret = cxd2880_tnrdmd_dvbt_tune1(tnr_dmd, tune_param);
> + if (ret)
> + return ret;
> +
> + usleep_range(CXD2880_TNRDMD_WAIT_AGC_STABLE * 10000,
> + CXD2880_TNRDMD_WAIT_AGC_STABLE * 10000 + 1000);
> +
> + ret = cxd2880_tnrdmd_dvbt_tune2(tnr_dmd, tune_param);
> + if (ret)
> + return ret;
> +
> + return 0;
These last four lines can be shortened to:
return cxd2880_tnrdmd_dvbt_tune2(tnr_dmd, tune_param);
This construct is repeated many times in cxd2880_tnrdmd_dvbt2.c and
cxd2880_tnrdmd_dvbt.c
> +}
> +
> +static int cxd2880_dvbt2_tune(struct cxd2880_tnrdmd *tnr_dmd,
> + struct cxd2880_dvbt2_tune_param
> + *tune_param)
> +{
> + int ret;
> +
> + if ((!tnr_dmd) || (!tune_param))
> + return -EINVAL;
> +
> + if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
> + return -EINVAL;
> +
> + if ((tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP) &&
> + (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE))
> + return -EPERM;
> +
> + atomic_set(&tnr_dmd->cancel, 0);
> +
> + if ((tune_param->bandwidth != CXD2880_DTV_BW_1_7_MHZ) &&
> + (tune_param->bandwidth != CXD2880_DTV_BW_5_MHZ) &&
> + (tune_param->bandwidth != CXD2880_DTV_BW_6_MHZ) &&
> + (tune_param->bandwidth != CXD2880_DTV_BW_7_MHZ) &&
> + (tune_param->bandwidth != CXD2880_DTV_BW_8_MHZ)) {
> + return -EOPNOTSUPP;
> + }
> +
> + if ((tune_param->profile != CXD2880_DVBT2_PROFILE_BASE) &&
> + (tune_param->profile != CXD2880_DVBT2_PROFILE_LITE))
> + return -EINVAL;
> +
> + ret = cxd2880_tnrdmd_dvbt2_tune1(tnr_dmd, tune_param);
> + if (ret)
> + return ret;
> +
> + usleep_range(CXD2880_TNRDMD_WAIT_AGC_STABLE * 10000,
> + CXD2880_TNRDMD_WAIT_AGC_STABLE * 10000 + 1000);
> +
> + ret = cxd2880_tnrdmd_dvbt2_tune2(tnr_dmd, tune_param);
> + if (ret)
> + return ret;
> +
> + return ret;
> +}
> +
> +static int cxd2880_set_frontend(struct dvb_frontend *fe)
> +{
> + int ret;
> + struct dtv_frontend_properties *c;
> + struct cxd2880_priv *priv;
> + enum cxd2880_dtv_bandwidth bw = CXD2880_DTV_BW_1_7_MHZ;
> +
> + if (!fe) {
> + pr_err("invalid arg\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> + c = &fe->dtv_property_cache;
> +
> + c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + c->pre_bit_error.stat[0].uvalue = 0;
> + c->pre_bit_error.len = 1;
> + c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + c->pre_bit_count.stat[0].uvalue = 0;
> + c->pre_bit_count.len = 1;
> + c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + c->post_bit_error.stat[0].uvalue = 0;
> + c->post_bit_error.len = 1;
> + c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + c->post_bit_count.stat[0].uvalue = 0;
> + c->post_bit_count.len = 1;
> + c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + c->block_error.stat[0].uvalue = 0;
> + c->block_error.len = 1;
> + c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + c->block_count.stat[0].uvalue = 0;
> + c->block_count.len = 1;
> +
> + switch (c->bandwidth_hz) {
> + case 1712000:
> + bw = CXD2880_DTV_BW_1_7_MHZ;
> + break;
> + case 5000000:
> + bw = CXD2880_DTV_BW_5_MHZ;
> + break;
> + case 6000000:
> + bw = CXD2880_DTV_BW_6_MHZ;
> + break;
> + case 7000000:
> + bw = CXD2880_DTV_BW_7_MHZ;
> + break;
> + case 8000000:
> + bw = CXD2880_DTV_BW_8_MHZ;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + priv->s = 0;
> +
> + pr_info("sys:%d freq:%d bw:%d\n",
> + c->delivery_system, c->frequency, bw);
> + mutex_lock(priv->spi_mutex);
> + if (c->delivery_system == SYS_DVBT) {
> + priv->tnrdmd.sys = CXD2880_DTV_SYS_DVBT;
> + priv->dvbt_tune_param.center_freq_khz = c->frequency / 1000;
> + priv->dvbt_tune_param.bandwidth = bw;
> + priv->dvbt_tune_param.profile = CXD2880_DVBT_PROFILE_HP;
> + ret = cxd2880_dvbt_tune(&priv->tnrdmd,
> + &priv->dvbt_tune_param);
> + } else if (c->delivery_system == SYS_DVBT2) {
> + priv->tnrdmd.sys = CXD2880_DTV_SYS_DVBT2;
> + priv->dvbt2_tune_param.center_freq_khz = c->frequency / 1000;
> + priv->dvbt2_tune_param.bandwidth = bw;
> + priv->dvbt2_tune_param.data_plp_id = (u16)c->stream_id;
> + priv->dvbt2_tune_param.profile = CXD2880_DVBT2_PROFILE_BASE;
> + ret = cxd2880_dvbt2_tune(&priv->tnrdmd,
> + &priv->dvbt2_tune_param);
> + } else {
> + pr_err("invalid system\n");
> + mutex_unlock(priv->spi_mutex);
> + return -EINVAL;
> + }
> + mutex_unlock(priv->spi_mutex);
> +
> + pr_info("tune result %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int cxd2880_get_stats(struct dvb_frontend *fe,
> + enum fe_status status)
> +{
> + struct cxd2880_priv *priv = NULL;
> + struct dtv_frontend_properties *c = NULL;
> + u32 pre_bit_err = 0, pre_bit_count = 0;
> + u32 post_bit_err = 0, post_bit_count = 0;
> + u32 block_err = 0, block_count = 0;
> + int ret;
> +
> + if (!fe) {
> + pr_err("invalid arg\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> + c = &fe->dtv_property_cache;
> +
> + if (!(status & FE_HAS_LOCK)) {
> + c->pre_bit_error.len = 1;
> + c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + c->pre_bit_count.len = 1;
> + c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + c->post_bit_error.len = 1;
> + c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + c->post_bit_count.len = 1;
> + c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + c->block_error.len = 1;
> + c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + c->block_count.len = 1;
> + c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> +
> + return 0;
> + }
> +
> + if (time_after(jiffies, priv->pre_ber_update)) {
> + priv->pre_ber_update =
> + jiffies + msecs_to_jiffies(priv->pre_ber_interval);
> + if (c->delivery_system == SYS_DVBT) {
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_pre_bit_err_t(&priv->tnrdmd,
> + &pre_bit_err,
> + &pre_bit_count);
> + mutex_unlock(priv->spi_mutex);
> + } else if (c->delivery_system == SYS_DVBT2) {
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_pre_bit_err_t2(&priv->tnrdmd,
> + &pre_bit_err,
> + &pre_bit_count);
> + mutex_unlock(priv->spi_mutex);
> + } else {
> + return -EINVAL;
> + }
> +
> + if (!ret) {
> + c->pre_bit_error.len = 1;
> + c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
> + c->pre_bit_error.stat[0].uvalue += pre_bit_err;
> + c->pre_bit_count.len = 1;
> + c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
> + c->pre_bit_count.stat[0].uvalue += pre_bit_count;
> + } else {
> + c->pre_bit_error.len = 1;
> + c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + c->pre_bit_count.len = 1;
> + c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + pr_debug("pre_bit_error_t failed %d\n", ret);
> + }
> + }
> +
> + if (time_after(jiffies, priv->post_ber_update)) {
> + priv->post_ber_update =
> + jiffies + msecs_to_jiffies(priv->post_ber_interval);
> + if (c->delivery_system == SYS_DVBT) {
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_post_bit_err_t(&priv->tnrdmd,
> + &post_bit_err,
> + &post_bit_count);
> + mutex_unlock(priv->spi_mutex);
> + } else if (c->delivery_system == SYS_DVBT2) {
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_post_bit_err_t2(&priv->tnrdmd,
> + &post_bit_err,
> + &post_bit_count);
> + mutex_unlock(priv->spi_mutex);
> + } else {
> + return -EINVAL;
> + }
> +
> + if (!ret) {
> + c->post_bit_error.len = 1;
> + c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
> + c->post_bit_error.stat[0].uvalue += post_bit_err;
> + c->post_bit_count.len = 1;
> + c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
> + c->post_bit_count.stat[0].uvalue += post_bit_count;
> + } else {
> + c->post_bit_error.len = 1;
> + c->post_bit_error.stat[0].scale =
> + FE_SCALE_NOT_AVAILABLE;
> + c->post_bit_count.len = 1;
> + c->post_bit_count.stat[0].scale =
> + FE_SCALE_NOT_AVAILABLE;
> + pr_debug("post_bit_err_t %d\n", ret);
> + }
> + }
> +
> + if (time_after(jiffies, priv->ucblock_update)) {
> + priv->ucblock_update =
> + jiffies + msecs_to_jiffies(priv->ucblock_interval);
> + if (c->delivery_system == SYS_DVBT) {
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_read_block_err_t(&priv->tnrdmd,
> + &block_err,
> + &block_count);
> + mutex_unlock(priv->spi_mutex);
> + } else if (c->delivery_system == SYS_DVBT2) {
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_read_block_err_t2(&priv->tnrdmd,
> + &block_err,
> + &block_count);
> + mutex_unlock(priv->spi_mutex);
> + } else {
> + return -EINVAL;
> + }
> + if (!ret) {
> + c->block_error.len = 1;
> + c->block_error.stat[0].scale = FE_SCALE_COUNTER;
> + c->block_error.stat[0].uvalue += block_err;
> + c->block_count.len = 1;
> + c->block_count.stat[0].scale = FE_SCALE_COUNTER;
> + c->block_count.stat[0].uvalue += block_count;
> + } else {
> + c->block_error.len = 1;
> + c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + c->block_count.len = 1;
> + c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + pr_debug("read_block_err_t %d\n", ret);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int cxd2880_check_l1post_plp(struct dvb_frontend *fe)
> +{
> + u8 valid = 0;
> + u8 plp_not_found;
> + int ret;
> + struct cxd2880_priv *priv = NULL;
> +
> + if (!fe) {
> + pr_err("invalid arg\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> +
> + ret = cxd2880_tnrdmd_dvbt2_check_l1post_valid(&priv->tnrdmd,
> + &valid);
> + if (ret)
> + return ret;
> +
> + if (!valid)
> + return -EAGAIN;
> +
> + ret = cxd2880_tnrdmd_dvbt2_mon_data_plp_error(&priv->tnrdmd,
> + &plp_not_found);
> + if (ret)
> + return ret;
> +
> + if (plp_not_found) {
> + priv->dvbt2_tune_param.tune_info =
> + CXD2880_TNRDMD_DVBT2_TUNE_INFO_INVALID_PLP_ID;
> + } else {
> + priv->dvbt2_tune_param.tune_info =
> + CXD2880_TNRDMD_DVBT2_TUNE_INFO_OK;
> + }
> +
> + return 0;
> +}
> +
> +static int cxd2880_read_status(struct dvb_frontend *fe,
> + enum fe_status *status)
> +{
> + int ret;
> + u8 sync = 0;
> + u8 lock = 0;
> + u8 unlock = 0;
> + struct cxd2880_priv *priv = NULL;
> + struct dtv_frontend_properties *c = NULL;
> +
> + if ((!fe) || (!status)) {
> + pr_err("invalid arg\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> + c = &fe->dtv_property_cache;
> + *status = 0;
> +
> + if (priv->tnrdmd.state == CXD2880_TNRDMD_STATE_ACTIVE) {
> + mutex_lock(priv->spi_mutex);
> + if (c->delivery_system == SYS_DVBT) {
> + ret = cxd2880_tnrdmd_dvbt_mon_sync_stat(
> + &priv->tnrdmd,
> + &sync,
> + &lock,
> + &unlock);
> + } else if (c->delivery_system == SYS_DVBT2) {
> + ret = cxd2880_tnrdmd_dvbt2_mon_sync_stat(
> + &priv->tnrdmd,
> + &sync,
> + &lock,
> + &unlock);
> + } else {
> + pr_err("invalid system");
> + mutex_unlock(priv->spi_mutex);
> + return -EINVAL;
> + }
> +
> + mutex_unlock(priv->spi_mutex);
> + if (ret) {
> + pr_err("failed. sys = %d\n", priv->tnrdmd.sys);
> + return ret;
> + }
> +
> + if (sync == 6) {
> + *status = FE_HAS_SIGNAL |
> + FE_HAS_CARRIER;
> + }
> + if (lock)
> + *status |= FE_HAS_VITERBI |
> + FE_HAS_SYNC |
> + FE_HAS_LOCK;
> + }
> +
> + pr_debug("status %d\n", *status);
> +
> + if (priv->s == 0 && (*status & FE_HAS_LOCK)) {
> + mutex_lock(priv->spi_mutex);
> + if (c->delivery_system == SYS_DVBT) {
> + ret = cxd2880_set_ber_per_period_t(fe);
> + priv->s = *status;
> + } else if (c->delivery_system == SYS_DVBT2) {
> + ret = cxd2880_check_l1post_plp(fe);
> + if (!ret) {
> + ret = cxd2880_set_ber_per_period_t2(fe);
> + priv->s = *status;
> + }
> + } else {
> + pr_err("invalid system\n");
> + mutex_unlock(priv->spi_mutex);
> + return -EINVAL;
> + }
> + mutex_unlock(priv->spi_mutex);
> + }
> +
> + cxd2880_get_stats(fe, *status);
> + return 0;
> +}
> +
> +static int cxd2880_tune(struct dvb_frontend *fe,
> + bool retune,
> + unsigned int mode_flags,
> + unsigned int *delay,
> + enum fe_status *status)
> +{
> + int ret;
> +
> + if ((!fe) || (!delay) || (!status)) {
> + pr_err("invalid arg.");
> + return -EINVAL;
> + }
> +
> + if (retune) {
> + ret = cxd2880_set_frontend(fe);
> + if (ret) {
> + pr_err("cxd2880_set_frontend failed %d\n", ret);
> + return ret;
> + }
> + }
> +
> + *delay = HZ / 5;
> +
> + return cxd2880_read_status(fe, status);
> +}
> +
> +static int cxd2880_get_frontend_t(struct dvb_frontend *fe,
> + struct dtv_frontend_properties *c)
> +{
> + int ret;
> + struct cxd2880_priv *priv = NULL;
> + enum cxd2880_dvbt_mode mode = CXD2880_DVBT_MODE_2K;
> + enum cxd2880_dvbt_guard guard = CXD2880_DVBT_GUARD_1_32;
> + struct cxd2880_dvbt_tpsinfo tps;
> + enum cxd2880_tnrdmd_spectrum_sense sense;
> + u16 snr = 0;
> + int strength = 0;
> +
> + if ((!fe) || (!c)) {
> + pr_err("invalid arg\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> +
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_tnrdmd_dvbt_mon_mode_guard(&priv->tnrdmd,
> + &mode, &guard);
> + mutex_unlock(priv->spi_mutex);
> + if (!ret) {
> + switch (mode) {
> + case CXD2880_DVBT_MODE_2K:
> + c->transmission_mode = TRANSMISSION_MODE_2K;
> + break;
> + case CXD2880_DVBT_MODE_8K:
> + c->transmission_mode = TRANSMISSION_MODE_8K;
> + break;
> + default:
> + c->transmission_mode = TRANSMISSION_MODE_2K;
> + pr_debug("transmission mode is invalid %d\n", mode);
> + break;
> + }
> + switch (guard) {
> + case CXD2880_DVBT_GUARD_1_32:
> + c->guard_interval = GUARD_INTERVAL_1_32;
> + break;
> + case CXD2880_DVBT_GUARD_1_16:
> + c->guard_interval = GUARD_INTERVAL_1_16;
> + break;
> + case CXD2880_DVBT_GUARD_1_8:
> + c->guard_interval = GUARD_INTERVAL_1_8;
> + break;
> + case CXD2880_DVBT_GUARD_1_4:
> + c->guard_interval = GUARD_INTERVAL_1_4;
> + break;
> + default:
> + c->guard_interval = GUARD_INTERVAL_1_32;
> + pr_debug("guard interval is invalid %d\n",
> + guard);
> + break;
> + }
> + } else {
> + c->transmission_mode = TRANSMISSION_MODE_2K;
> + c->guard_interval = GUARD_INTERVAL_1_32;
> + pr_debug("ModeGuard err %d\n", ret);
> + }
> +
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_tnrdmd_dvbt_mon_tps_info(&priv->tnrdmd, &tps);
> + mutex_unlock(priv->spi_mutex);
> + if (!ret) {
> + switch (tps.hierarchy) {
> + case CXD2880_DVBT_HIERARCHY_NON:
> + c->hierarchy = HIERARCHY_NONE;
> + break;
> + case CXD2880_DVBT_HIERARCHY_1:
> + c->hierarchy = HIERARCHY_1;
> + break;
> + case CXD2880_DVBT_HIERARCHY_2:
> + c->hierarchy = HIERARCHY_2;
> + break;
> + case CXD2880_DVBT_HIERARCHY_4:
> + c->hierarchy = HIERARCHY_4;
> + break;
> + default:
> + c->hierarchy = HIERARCHY_NONE;
> + pr_debug("TPSInfo hierarchy is invalid %d\n",
> + tps.hierarchy);
> + break;
> + }
> +
> + switch (tps.rate_hp) {
> + case CXD2880_DVBT_CODERATE_1_2:
> + c->code_rate_HP = FEC_1_2;
> + break;
> + case CXD2880_DVBT_CODERATE_2_3:
> + c->code_rate_HP = FEC_2_3;
> + break;
> + case CXD2880_DVBT_CODERATE_3_4:
> + c->code_rate_HP = FEC_3_4;
> + break;
> + case CXD2880_DVBT_CODERATE_5_6:
> + c->code_rate_HP = FEC_5_6;
> + break;
> + case CXD2880_DVBT_CODERATE_7_8:
> + c->code_rate_HP = FEC_7_8;
> + break;
> + default:
> + c->code_rate_HP = FEC_NONE;
> + pr_debug("TPSInfo rateHP is invalid %d\n",
> + tps.rate_hp);
> + break;
> + }
> + switch (tps.rate_lp) {
> + case CXD2880_DVBT_CODERATE_1_2:
> + c->code_rate_LP = FEC_1_2;
> + break;
> + case CXD2880_DVBT_CODERATE_2_3:
> + c->code_rate_LP = FEC_2_3;
> + break;
> + case CXD2880_DVBT_CODERATE_3_4:
> + c->code_rate_LP = FEC_3_4;
> + break;
> + case CXD2880_DVBT_CODERATE_5_6:
> + c->code_rate_LP = FEC_5_6;
> + break;
> + case CXD2880_DVBT_CODERATE_7_8:
> + c->code_rate_LP = FEC_7_8;
> + break;
> + default:
> + c->code_rate_LP = FEC_NONE;
> + pr_debug("TPSInfo rateLP is invalid %d\n",
> + tps.rate_lp);
> + break;
> + }
> + switch (tps.constellation) {
> + case CXD2880_DVBT_CONSTELLATION_QPSK:
> + c->modulation = QPSK;
> + break;
> + case CXD2880_DVBT_CONSTELLATION_16QAM:
> + c->modulation = QAM_16;
> + break;
> + case CXD2880_DVBT_CONSTELLATION_64QAM:
> + c->modulation = QAM_64;
> + break;
> + default:
> + c->modulation = QPSK;
> + pr_debug("TPSInfo constellation is invalid %d\n",
> + tps.constellation);
> + break;
> + }
> + } else {
> + c->hierarchy = HIERARCHY_NONE;
> + c->code_rate_HP = FEC_NONE;
> + c->code_rate_LP = FEC_NONE;
> + c->modulation = QPSK;
> + pr_debug("TPS info err %d\n", ret);
> + }
> +
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_tnrdmd_dvbt_mon_spectrum_sense(&priv->tnrdmd, &sense);
> + mutex_unlock(priv->spi_mutex);
> + if (!ret) {
> + switch (sense) {
> + case CXD2880_TNRDMD_SPECTRUM_NORMAL:
> + c->inversion = INVERSION_OFF;
> + break;
> + case CXD2880_TNRDMD_SPECTRUM_INV:
> + c->inversion = INVERSION_ON;
> + break;
> + default:
> + c->inversion = INVERSION_OFF;
> + pr_debug("spectrum sense is invalid %d\n", sense);
> + break;
> + }
> + } else {
> + c->inversion = INVERSION_OFF;
> + pr_debug("spectrum_sense %d\n", ret);
> + }
> +
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);
> + mutex_unlock(priv->spi_mutex);
> + if (!ret) {
> + c->strength.len = 1;
> + c->strength.stat[0].scale = FE_SCALE_DECIBEL;
> + c->strength.stat[0].svalue = strength;
> + } else {
> + c->strength.len = 1;
> + c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + pr_debug("mon_rf_lvl %d\n", ret);
> + }
> +
> + ret = cxd2880_read_snr(fe, &snr);
> + if (!ret) {
> + c->cnr.len = 1;
> + c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
> + c->cnr.stat[0].svalue = snr;
> + } else {
> + c->cnr.len = 1;
> + c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + pr_debug("read_snr %d\n", ret);
> + }
> +
> + return 0;
> +}
> +
> +static int cxd2880_get_frontend_t2(struct dvb_frontend *fe,
> + struct dtv_frontend_properties *c)
> +{
> + int ret;
> + struct cxd2880_priv *priv = NULL;
> + struct cxd2880_dvbt2_l1pre l1pre;
> + enum cxd2880_dvbt2_plp_code_rate coderate;
> + enum cxd2880_dvbt2_plp_constell qam;
> + enum cxd2880_tnrdmd_spectrum_sense sense;
> + u16 snr = 0;
> + int strength = 0;
> +
> + if ((!fe) || (!c)) {
> + pr_err("invalid arg.\n");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> +
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_tnrdmd_dvbt2_mon_l1_pre(&priv->tnrdmd, &l1pre);
> + mutex_unlock(priv->spi_mutex);
> + if (!ret) {
> + switch (l1pre.fft_mode) {
> + case CXD2880_DVBT2_M2K:
> + c->transmission_mode = TRANSMISSION_MODE_2K;
> + break;
> + case CXD2880_DVBT2_M8K:
> + c->transmission_mode = TRANSMISSION_MODE_8K;
> + break;
> + case CXD2880_DVBT2_M4K:
> + c->transmission_mode = TRANSMISSION_MODE_4K;
> + break;
> + case CXD2880_DVBT2_M1K:
> + c->transmission_mode = TRANSMISSION_MODE_1K;
> + break;
> + case CXD2880_DVBT2_M16K:
> + c->transmission_mode = TRANSMISSION_MODE_16K;
> + break;
> + case CXD2880_DVBT2_M32K:
> + c->transmission_mode = TRANSMISSION_MODE_32K;
> + break;
> + default:
> + c->transmission_mode = TRANSMISSION_MODE_2K;
> + pr_debug("L1Pre fft_mode is invalid %d\n",
> + l1pre.fft_mode);
> + break;
> + }
> + switch (l1pre.gi) {
> + case CXD2880_DVBT2_G1_32:
> + c->guard_interval = GUARD_INTERVAL_1_32;
> + break;
> + case CXD2880_DVBT2_G1_16:
> + c->guard_interval = GUARD_INTERVAL_1_16;
> + break;
> + case CXD2880_DVBT2_G1_8:
> + c->guard_interval = GUARD_INTERVAL_1_8;
> + break;
> + case CXD2880_DVBT2_G1_4:
> + c->guard_interval = GUARD_INTERVAL_1_4;
> + break;
> + case CXD2880_DVBT2_G1_128:
> + c->guard_interval = GUARD_INTERVAL_1_128;
> + break;
> + case CXD2880_DVBT2_G19_128:
> + c->guard_interval = GUARD_INTERVAL_19_128;
> + break;
> + case CXD2880_DVBT2_G19_256:
> + c->guard_interval = GUARD_INTERVAL_19_256;
> + break;
> + default:
> + c->guard_interval = GUARD_INTERVAL_1_32;
> + pr_debug("L1Pre guard interval is invalid %d\n",
> + l1pre.gi);
> + break;
> + }
> + } else {
> + c->transmission_mode = TRANSMISSION_MODE_2K;
> + c->guard_interval = GUARD_INTERVAL_1_32;
> + pr_debug("L1Pre err %d\n", ret);
> + }
> +
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_tnrdmd_dvbt2_mon_code_rate(&priv->tnrdmd,
> + CXD2880_DVBT2_PLP_DATA,
> + &coderate);
> + mutex_unlock(priv->spi_mutex);
> + if (!ret) {
> + switch (coderate) {
> + case CXD2880_DVBT2_R1_2:
> + c->fec_inner = FEC_1_2;
> + break;
> + case CXD2880_DVBT2_R3_5:
> + c->fec_inner = FEC_3_5;
> + break;
> + case CXD2880_DVBT2_R2_3:
> + c->fec_inner = FEC_2_3;
> + break;
> + case CXD2880_DVBT2_R3_4:
> + c->fec_inner = FEC_3_4;
> + break;
> + case CXD2880_DVBT2_R4_5:
> + c->fec_inner = FEC_4_5;
> + break;
> + case CXD2880_DVBT2_R5_6:
> + c->fec_inner = FEC_5_6;
> + break;
> + default:
> + c->fec_inner = FEC_NONE;
> + pr_debug("CodeRate is invalid %d\n", coderate);
> + break;
> + }
> + } else {
> + c->fec_inner = FEC_NONE;
> + pr_debug("CodeRate %d\n", ret);
> + }
> +
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_tnrdmd_dvbt2_mon_qam(&priv->tnrdmd,
> + CXD2880_DVBT2_PLP_DATA,
> + &qam);
> + mutex_unlock(priv->spi_mutex);
> + if (!ret) {
> + switch (qam) {
> + case CXD2880_DVBT2_QPSK:
> + c->modulation = QPSK;
> + break;
> + case CXD2880_DVBT2_QAM16:
> + c->modulation = QAM_16;
> + break;
> + case CXD2880_DVBT2_QAM64:
> + c->modulation = QAM_64;
> + break;
> + case CXD2880_DVBT2_QAM256:
> + c->modulation = QAM_256;
> + break;
> + default:
> + c->modulation = QPSK;
> + pr_debug("QAM is invalid %d\n", qam);
> + break;
> + }
> + } else {
> + c->modulation = QPSK;
> + pr_debug("QAM %d\n", ret);
> + }
> +
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_tnrdmd_dvbt2_mon_spectrum_sense(&priv->tnrdmd, &sense);
> + mutex_unlock(priv->spi_mutex);
> + if (!ret) {
> + switch (sense) {
> + case CXD2880_TNRDMD_SPECTRUM_NORMAL:
> + c->inversion = INVERSION_OFF;
> + break;
> + case CXD2880_TNRDMD_SPECTRUM_INV:
> + c->inversion = INVERSION_ON;
> + break;
> + default:
> + c->inversion = INVERSION_OFF;
> + pr_debug("spectrum sense is invalid %d\n", sense);
> + break;
> + }
> + } else {
> + c->inversion = INVERSION_OFF;
> + pr_debug("SpectrumSense %d\n", ret);
> + }
> +
> + mutex_lock(priv->spi_mutex);
> + ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);
> + mutex_unlock(priv->spi_mutex);
> + if (!ret) {
> + c->strength.len = 1;
> + c->strength.stat[0].scale = FE_SCALE_DECIBEL;
> + c->strength.stat[0].svalue = strength;
> + } else {
> + c->strength.len = 1;
> + c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + pr_debug("mon_rf_lvl %d\n", ret);
> + }
> +
> + ret = cxd2880_read_snr(fe, &snr);
> + if (!ret) {
> + c->cnr.len = 1;
> + c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
> + c->cnr.stat[0].svalue = snr;
> + } else {
> + c->cnr.len = 1;
> + c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
> + pr_debug("read_snr %d\n", ret);
> + }
> +
> + return 0;
> +}
> +
> +static int cxd2880_get_frontend(struct dvb_frontend *fe,
> + struct dtv_frontend_properties *props)
> +{
> + struct cxd2880_priv *priv = NULL;
> + int ret;
> +
> + if ((!fe) || (!props)) {
> + pr_err("invalid arg.");
> + return -EINVAL;
> + }
> +
> + priv = fe->demodulator_priv;
> +
> + pr_debug("system=%d\n", fe->dtv_property_cache.delivery_system);
> + switch (fe->dtv_property_cache.delivery_system) {
> + case SYS_DVBT:
> + ret = cxd2880_get_frontend_t(fe, props);
> + break;
> + case SYS_DVBT2:
> + ret = cxd2880_get_frontend_t2(fe, props);
> + break;
> + default:
> + ret = -EINVAL;
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static enum dvbfe_algo cxd2880_get_frontend_algo(struct dvb_frontend *fe)
> +{
> + return DVBFE_ALGO_HW;
> +}
> +
> +static struct dvb_frontend_ops cxd2880_dvbt_t2_ops;
> +
> +struct dvb_frontend *cxd2880_attach(struct dvb_frontend *fe,
> + struct cxd2880_config *cfg)
> +{
> + int ret;
> + enum cxd2880_tnrdmd_chip_id chipid =
> + CXD2880_TNRDMD_CHIP_ID_UNKNOWN;
> + static struct cxd2880_priv *priv;
> + u8 data = 0;
> +
> + if (!fe) {
> + pr_err("invalid arg.\n");
> + return NULL;
> + }
> +
> + priv = kzalloc(sizeof(struct cxd2880_priv), GFP_KERNEL);
> + if (!priv)
> + return NULL;
> +
> + priv->spi = cfg->spi;
> + priv->spi_mutex = cfg->spi_mutex;
> + priv->spi_device.spi = cfg->spi;
> +
> + memcpy(&fe->ops, &cxd2880_dvbt_t2_ops,
> + sizeof(struct dvb_frontend_ops));
Since this is struct, will struct assignment not do?
> +
> + ret = cxd2880_spi_device_initialize(&priv->spi_device,
> + CXD2880_SPI_MODE_0,
> + 55000000);
> + if (ret) {
> + pr_err("spi_device_initialize failed. %d\n", ret);
> + kfree(priv);
> + return NULL;
> + }
> +
> + ret = cxd2880_spi_device_create_spi(&priv->cxd2880_spi,
> + &priv->spi_device);
> + if (ret) {
> + pr_err("spi_device_create_spi failed. %d\n", ret);
> + kfree(priv);
> + return NULL;
> + }
> +
> + ret = cxd2880_io_spi_create(&priv->regio, &priv->cxd2880_spi, 0);
> + if (ret) {
> + pr_err("io_spi_create failed. %d\n", ret);
> + kfree(priv);
> + return NULL;
> + }
> + ret = priv->regio.write_reg(&priv->regio,
> + CXD2880_IO_TGT_SYS, 0x00, 0x00);
> + if (ret) {
> + pr_err("set bank to 0x00 failed.\n");
> + kfree(priv);
> + return NULL;
> + }
> + ret = priv->regio.read_regs(&priv->regio,
> + CXD2880_IO_TGT_SYS, 0xfd, &data, 1);
> + if (ret) {
> + pr_err("read chip id failed.\n");
> + kfree(priv);
> + return NULL;
> + }
> +
> + chipid = (enum cxd2880_tnrdmd_chip_id)data;
> + if ((chipid != CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X) &&
> + (chipid != CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11)) {
> + pr_err("chip id invalid.\n");
> + kfree(priv);
> + return NULL;
> + }
> +
> + fe->demodulator_priv = priv;
> + pr_info("CXD2880 driver version: Ver %s\n",
> + CXD2880_TNRDMD_DRIVER_VERSION);
> +
> + return fe;
> +}
> +EXPORT_SYMBOL(cxd2880_attach);
> +
> +static struct dvb_frontend_ops cxd2880_dvbt_t2_ops = {
> + .info = {
> + .name = "Sony CXD2880",
> + .frequency_min = 174000000,
> + .frequency_max = 862000000,
> + .frequency_stepsize = 1000,
> + .caps = FE_CAN_INVERSION_AUTO |
> + FE_CAN_FEC_1_2 |
> + FE_CAN_FEC_2_3 |
> + FE_CAN_FEC_3_4 |
> + FE_CAN_FEC_4_5 |
> + FE_CAN_FEC_5_6 |
> + FE_CAN_FEC_7_8 |
> + FE_CAN_FEC_AUTO |
> + FE_CAN_QPSK |
> + FE_CAN_QAM_16 |
> + FE_CAN_QAM_32 |
> + FE_CAN_QAM_64 |
> + FE_CAN_QAM_128 |
> + FE_CAN_QAM_256 |
> + FE_CAN_QAM_AUTO |
> + FE_CAN_TRANSMISSION_MODE_AUTO |
> + FE_CAN_GUARD_INTERVAL_AUTO |
> + FE_CAN_2G_MODULATION |
> + FE_CAN_RECOVER |
> + FE_CAN_MUTE_TS,
> + },
> + .delsys = { SYS_DVBT, SYS_DVBT2 },
> +
> + .release = cxd2880_release,
> + .init = cxd2880_init,
> + .sleep = cxd2880_sleep,
> + .tune = cxd2880_tune,
> + .set_frontend = cxd2880_set_frontend,
> + .get_frontend = cxd2880_get_frontend,
> + .read_status = cxd2880_read_status,
> + .read_ber = cxd2880_read_ber,
> + .read_signal_strength = cxd2880_read_signal_strength,
> + .read_snr = cxd2880_read_snr,
> + .read_ucblocks = cxd2880_read_ucblocks,
> + .get_frontend_algo = cxd2880_get_frontend_algo,
> +};
> +
> +MODULE_DESCRIPTION(
> +"Sony CXD2880 DVB-T2/T tuner + demodulator drvier");
drvier => driver
> +MODULE_AUTHOR("Sony Semiconductor Solutions Corporation");
> +MODULE_LICENSE("GPL v2");
> --
> 2.13.0
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* Re: [PATCH 09/12] ARM: dts: imx6qdl-colibri: Remove unneeded reg property
From: Marcel Ziswiler @ 2017-12-03 23:02 UTC (permalink / raw)
To: festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
fabio.estevam-3arQi8VN3Tc@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
maitysanchayan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
In-Reply-To: <1512156285-18451-9-git-send-email-festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 1349 bytes --]
On Fri, 2017-12-01 at 17:24 -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@nxp.com>
>
> As described in
> Documentation/devicetree/bindings/input/touchscreen/stmpe.txt
> there is no 'reg' property under stmpe_touchscreen, so remove it
> to fix the following build warning with W=1:
>
> arch/arm/boot/dts/imx6dl-colibri-eval-v3.dtb: Warning
> (unit_address_vs_reg): Node /soc/aips-bus@2100000/i2c@21a4000/stmpe81
> 1@41/stmpe_touchscreen has a reg or ranges property, but no unit name
>
> Cc: Sanchayan Maity <maitysanchayan@gmail.com>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
> arch/arm/boot/dts/imx6qdl-colibri.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> index fc66bbf..e4eb300 100644
> --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> @@ -274,7 +274,6 @@
>
> stmpe_touchscreen {
> compatible = "st,stmpe-ts";
> - reg = <0>;
> /* 3.25 MHz ADC clock speed */
> st,adc-freq = <1>;
> /* 8 sample average control */N‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·zøœzÚÞz)í…æèw*\x1fjg¬±¨\x1e¶‰šŽŠÝ¢j.ïÛ°\½½MŽúgjÌæa×\x02››–' ™©Þ¢¸\f¢·¦j:+v‰¨ŠwèjØm¶Ÿÿ¾\a«‘êçzZ+ƒùšŽŠÝ¢j"ú!¶i
^ permalink raw reply
* Re: [PATCH 1/4] arm: dts: imx28: Use phandles instead of unit addresses
From: kbuild test robot @ 2017-12-03 23:13 UTC (permalink / raw)
Cc: kbuild-all-JC7UmRfGjtg, shawnguo-DgEjT+Ai2ygdnm+yROfE0A,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
fabio.estevam-3arQi8VN3Tc,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
karthik-fINqtvHxh+hg9hUCZPvPmw,
shrikant.maurya-fINqtvHxh+hg9hUCZPvPmw, Ravi Eluri, Suniel Mahesh
In-Reply-To: <1512110311-15788-2-git-send-email-venkataravi.e-fINqtvHxh+hg9hUCZPvPmw@public.gmane.org>
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Hi Ravi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on shawnguo/for-next]
[also build test ERROR on v4.15-rc2 next-20171201]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/venkataravi-e-techveda-org/arm-dts-imx28-Use-phandles-instead-of-unit-addresses/20171204-023409
base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
config: arm-at91_dt_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
Note: the linux-review/venkataravi-e-techveda-org/arm-dts-imx28-Use-phandles-instead-of-unit-addresses/20171204-023409 HEAD c17ed56cb053430c58e4b6748774a1f195df2627 builds fine.
It only hurts bisectibility.
All errors (new ones prefixed by >>):
>> Error: arch/arm/boot/dts/imx28-evk.dts:25.4-9 syntax error
>> FATAL ERROR: Unable to parse input tree
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 23569 bytes --]
^ permalink raw reply
* Re: [PATCH] fsi: Add Self Boot Engine FIFO FSI client
From: Andrew Jeffery @ 2017-12-04 0:05 UTC (permalink / raw)
To: kbuild test robot
Cc: kbuild-all-JC7UmRfGjtg, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
bradleyb-r5pk2Da7Bxt8sGd51Jp2sdBPR1lH4CV8,
cbostic-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8,
joel-U3u1mxZcP9KHXe+LvDLADg,
eajames-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8, Edward A. James
In-Reply-To: <201712040455.1tZmVDmK%fengguang.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
If there's enthusiasm for what I've proposed over Eddy and Brad's patch,
I'll clean up the kbuild issues and resend. It was more meant to trigger
discussion than sent as ready for submission.
Cheers,
Andrew
On Mon, 4 Dec 2017, at 06:55, kbuild test robot wrote:
> Hi Andrew,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on linus/master]
> [also build test ERROR on v4.15-rc2 next-20171201]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve the system]
>
> url:
> https://github.com/0day-ci/linux/commits/Andrew-Jeffery/fsi-Add-Self-Boot-Engine-FIFO-FSI-client/20171204-031454
> config: blackfin-allmodconfig (attached as .config)
> compiler: bfin-uclinux-gcc (GCC) 6.2.0
> reproduce:
> wget
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross
> -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=blackfin
>
> All error/warnings (new ones prefixed by >>):
>
> >> drivers/fsi//clients/fsi-sbefifo.c:325:0: warning: "TEST_SET" redefined
> #define TEST_SET(s) ((s) & BIT(7))
>
> In file included from
> arch/blackfin/mach-bf533/include/mach/blackfin.h:15:0,
> from arch/blackfin/include/asm/irqflags.h:11,
> from include/linux/irqflags.h:16,
> from arch/blackfin/include/asm/bitops.h:33,
> from include/linux/bitops.h:38,
> from drivers/fsi//clients/fsi-sbefifo.c:5:
> arch/blackfin/include/asm/def_LPBlackfin.h:687:0: note: this is the
> location of the previous definition
> #define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
>
> In file included from include/linux/printk.h:329:0,
> from include/linux/kernel.h:14,
> from include/linux/list.h:9,
> from include/linux/kobject.h:20,
> from include/linux/device.h:17,
> from include/linux/fsi.h:18,
> from drivers/fsi//clients/fsi-sbefifo.c:6:
> drivers/fsi//clients/fsi-sbefifo.c: In function 'sbefifo_drain':
> >> drivers/fsi//clients/fsi-sbefifo.c:359:21: warning: format '%d' expects argument of type 'int', but argument 7 has type 'ssize_t {aka long int}' [-Wformat=]
> dev_dbg(fifo->dev, "%s: valid_set: 0x%x, eot_set: 0x%x, nr_valid:
> %d, nr_xfer: %d, rem: %d\n",
> ^
> include/linux/dynamic_debug.h:135:39: note: in definition of macro
> 'dynamic_dev_dbg'
> __dynamic_dev_dbg(&descriptor, dev, fmt, \
> ^~~
> >> drivers/fsi//clients/fsi-sbefifo.c:359:2: note: in expansion of macro 'dev_dbg'
> dev_dbg(fifo->dev, "%s: valid_set: 0x%x, eot_set: 0x%x, nr_valid:
> %d, nr_xfer: %d, rem: %d\n",
> ^~~~~~~
> drivers/fsi//clients/fsi-sbefifo.c:359:21: warning: format '%d'
> expects argument of type 'int', but argument 9 has type 'ssize_t {aka
> long int}' [-Wformat=]
> dev_dbg(fifo->dev, "%s: valid_set: 0x%x, eot_set: 0x%x, nr_valid:
> %d, nr_xfer: %d, rem: %d\n",
> ^
> include/linux/dynamic_debug.h:135:39: note: in definition of macro
> 'dynamic_dev_dbg'
> __dynamic_dev_dbg(&descriptor, dev, fmt, \
> ^~~
> >> drivers/fsi//clients/fsi-sbefifo.c:359:2: note: in expansion of macro 'dev_dbg'
> dev_dbg(fifo->dev, "%s: valid_set: 0x%x, eot_set: 0x%x, nr_valid:
> %d, nr_xfer: %d, rem: %d\n",
> ^~~~~~~
> drivers/fsi//clients/fsi-sbefifo.c:378:21: warning: format '%d'
> expects argument of type 'int', but argument 7 has type 'ssize_t {aka
> long int}' [-Wformat=]
> dev_dbg(fifo->dev, "%s: Data phase complete: valid_set: 0x%x,
> eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
> ^
> include/linux/dynamic_debug.h:135:39: note: in definition of macro
> 'dynamic_dev_dbg'
> __dynamic_dev_dbg(&descriptor, dev, fmt, \
> ^~~
> drivers/fsi//clients/fsi-sbefifo.c:378:2: note: in expansion of macro
> 'dev_dbg'
> dev_dbg(fifo->dev, "%s: Data phase complete: valid_set: 0x%x,
> eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
> ^~~~~~~
> drivers/fsi//clients/fsi-sbefifo.c:378:21: warning: format '%d'
> expects argument of type 'int', but argument 9 has type 'ssize_t {aka
> long int}' [-Wformat=]
> dev_dbg(fifo->dev, "%s: Data phase complete: valid_set: 0x%x,
> eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
> ^
> include/linux/dynamic_debug.h:135:39: note: in definition of macro
> 'dynamic_dev_dbg'
> __dynamic_dev_dbg(&descriptor, dev, fmt, \
> ^~~
> drivers/fsi//clients/fsi-sbefifo.c:378:2: note: in expansion of macro
> 'dev_dbg'
> dev_dbg(fifo->dev, "%s: Data phase complete: valid_set: 0x%x,
> eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
> ^~~~~~~
> drivers/fsi//clients/fsi-sbefifo.c:403:21: warning: format '%d'
> expects argument of type 'int', but argument 7 has type 'ssize_t {aka
> long int}' [-Wformat=]
> dev_dbg(fifo->dev, "%s: EOT phase complete: valid_set: 0x%x,
> eot_set: 0x%x, nr_valid: %d\n, nr_xfer: %d, rem: %d\n",
> ^
> include/linux/dynamic_debug.h:135:39: note: in definition of macro
> 'dynamic_dev_dbg'
> __dynamic_dev_dbg(&descriptor, dev, fmt, \
> ^~~
> drivers/fsi//clients/fsi-sbefifo.c:403:2: note: in expansion of macro
> 'dev_dbg'
> dev_dbg(fifo->dev, "%s: EOT phase complete: valid_set: 0x%x,
> eot_set: 0x%x, nr_valid: %d\n, nr_xfer: %d, rem: %d\n",
> ^~~~~~~
> drivers/fsi//clients/fsi-sbefifo.c:403:21: warning: format '%d'
> expects argument of type 'int', but argument 9 has type 'ssize_t {aka
> long int}' [-Wformat=]
> dev_dbg(fifo->dev, "%s: EOT phase complete: valid_set: 0x%x,
> eot_set: 0x%x, nr_valid: %d\n, nr_xfer: %d, rem: %d\n",
> ^
> include/linux/dynamic_debug.h:135:39: note: in definition of macro
> 'dynamic_dev_dbg'
> __dynamic_dev_dbg(&descriptor, dev, fmt, \
> ^~~
> drivers/fsi//clients/fsi-sbefifo.c:403:2: note: in expansion of macro
> 'dev_dbg'
> dev_dbg(fifo->dev, "%s: EOT phase complete: valid_set: 0x%x,
> eot_set: 0x%x, nr_valid: %d\n, nr_xfer: %d, rem: %d\n",
> ^~~~~~~
> drivers/fsi//clients/fsi-sbefifo.c:417:21: warning: format '%d'
> expects argument of type 'int', but argument 7 has type 'ssize_t {aka
> long int}' [-Wformat=]
> dev_dbg(fifo->dev, "%s: Drain phase complete: valid_set: 0x%x,
> eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
> ^
> include/linux/dynamic_debug.h:135:39: note: in definition of macro
> 'dynamic_dev_dbg'
> __dynamic_dev_dbg(&descriptor, dev, fmt, \
> ^~~
> drivers/fsi//clients/fsi-sbefifo.c:417:2: note: in expansion of macro
> 'dev_dbg'
> dev_dbg(fifo->dev, "%s: Drain phase complete: valid_set: 0x%x,
> eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
> ^~~~~~~
> drivers/fsi//clients/fsi-sbefifo.c:417:21: warning: format '%d'
> expects argument of type 'int', but argument 9 has type 'ssize_t {aka
> long int}' [-Wformat=]
> dev_dbg(fifo->dev, "%s: Drain phase complete: valid_set: 0x%x,
> eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
> ^
> include/linux/dynamic_debug.h:135:39: note: in definition of macro
> 'dynamic_dev_dbg'
> __dynamic_dev_dbg(&descriptor, dev, fmt, \
> ^~~
> drivers/fsi//clients/fsi-sbefifo.c:417:2: note: in expansion of macro
> 'dev_dbg'
> dev_dbg(fifo->dev, "%s: Drain phase complete: valid_set: 0x%x,
> eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
> ^~~~~~~
> In file included from include/linux/list.h:9:0,
> from include/linux/kobject.h:20,
> from include/linux/device.h:17,
> from include/linux/fsi.h:18,
> from drivers/fsi//clients/fsi-sbefifo.c:6:
> drivers/fsi//clients/fsi-sbefifo.c: In function 'sbefifo_down_read':
> include/linux/kernel.h:792:16: warning: comparison of distinct pointer
> types lacks a cast
> (void) (&min1 == &min2); \
> ^
> include/linux/kernel.h:801:2: note: in expansion of macro '__min'
> __min(typeof(x), typeof(y), \
> ^~~~~
> >> drivers/fsi//clients/fsi-sbefifo.c:453:34: note: in expansion of macro 'min'
> } while (rem && read && read == min((rem + read),
> SBEFIFO_FIFO_DEPTH));
> ^~~
> drivers/fsi//clients/fsi-sbefifo.c: In function 'sbefifo_write':
> drivers/fsi//clients/fsi-sbefifo.c:557:43: warning: format '%d'
> expects argument of type 'int', but argument 3 has type 'ssize_t {aka
> long int}' [-Wformat=]
> dev_err(fifo->dev, "FIFO write failed: %d\n", rv);
> ^
> In file included from arch/blackfin/include/asm/bug.h:71:0,
> from include/linux/bug.h:5,
> from include/linux/thread_info.h:12,
> from include/asm-generic/current.h:5,
> from
> ./arch/blackfin/include/generated/asm/current.h:1,
> from include/linux/mutex.h:14,
> from include/linux/kernfs.h:13,
> from include/linux/sysfs.h:16,
> from include/linux/kobject.h:21,
> from include/linux/device.h:17,
> from include/linux/fsi.h:18,
> from drivers/fsi//clients/fsi-sbefifo.c:6:
> drivers/fsi//clients/fsi-sbefifo.c:572:17: warning: format '%d'
> expects argument of type 'int', but argument 4 has type 'ssize_t {aka
> long int}' [-Wformat=]
> WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
> ^
> include/asm-generic/bug.h:91:69: note: in definition of macro
> '__WARN_printf'
> #define __WARN_printf(arg...) warn_slowpath_fmt(__FILE__, __LINE__,
> arg)
> ^~~
> >> drivers/fsi//clients/fsi-sbefifo.c:572:2: note: in expansion of macro 'WARN'
> WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
> ^~~~
> drivers/fsi//clients/fsi-sbefifo.c:572:17: warning: format '%d'
> expects argument of type 'int', but argument 5 has type 'ssize_t {aka
> long int}' [-Wformat=]
> WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
> ^
> include/asm-generic/bug.h:91:69: note: in definition of macro
> '__WARN_printf'
> #define __WARN_printf(arg...) warn_slowpath_fmt(__FILE__, __LINE__,
> arg)
> ^~~
> >> drivers/fsi//clients/fsi-sbefifo.c:572:2: note: in expansion of macro 'WARN'
> WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
> ^~~~
> drivers/fsi//clients/fsi-sbefifo.c: In function 'sbefifo_read':
> drivers/fsi//clients/fsi-sbefifo.c:650:42: warning: format '%d'
> expects argument of type 'int', but argument 3 has type 'ssize_t {aka
> long int}' [-Wformat=]
> dev_err(fifo->dev, "FIFO read failed: %d\n", rv);
> ^
> drivers/fsi//clients/fsi-sbefifo.c: In function 'sbefifo_probe':
> >> drivers/fsi//clients/fsi-sbefifo.c:769:2: error: implicit declaration of function 'setup_timer' [-Werror=implicit-function-declaration]
> setup_timer(&fifo->poll.timer, sbefifo_poll_device,
> ^~~~~~~~~~~
> cc1: some warnings being treated as errors
>
> vim +/setup_timer +769 drivers/fsi//clients/fsi-sbefifo.c
>
> 498
> 499 /**
> 500 * sbefifo_write()
> 501 *
> 502 * @client The client context for the SBEFIFO
> 503 * @buf The buffer of data to write, at least @len
> elements
> 504 * @len The number elements in @buffer
> 505 *
> 506 * The buffer must represent a complete chip-op: EOT is
> signalled after the
> 507 * last element is written to the upstream FIFO.
> 508 *
> 509 * Returns the number of elements written on success and
> negative values on
> 510 * failure. If the call is successful a subsequent call to
> sbefifo_read() MUST
> 511 * be made.
> 512 */
> 513 ssize_t sbefifo_write(struct sbefifo_client *client, const u32
> *buf,
> 514 ssize_t len)
> 515 {
> 516 struct sbefifo *fifo = client->fifo;
> 517 unsigned long flags;
> 518 ssize_t rv;
> 519
> 520 spin_lock_irqsave(&fifo->wait.lock, flags);
> 521
> 522 if (client->state == sbefifo_client_active) {
> 523 dev_warn(fifo->dev, "Transfer already in
> progress\n");
> 524 spin_unlock_irqrestore(&fifo->wait.lock,
> flags);
> 525 return -EBUSY;
> 526 }
> 527
> 528 rv = wait_event_interruptible_locked_irq(fifo->wait,
> 529 fifo->state ==
> sbefifo_ready ||
> 530 fifo->state ==
> sbefifo_dead);
> 531 if (rv < 0) {
> 532 spin_unlock_irqrestore(&fifo->wait.lock,
> flags);
> 533 return rv;
> 534 }
> 535
> 536 if (fifo->state == sbefifo_dead) {
> 537 client->state = sbefifo_client_closed;
> 538 wake_up(&client->wait);
> 539 spin_unlock_irqrestore(&fifo->wait.lock,
> flags);
> 540 return -ENODEV;
> 541 }
> 542
> 543 WARN_ON(fifo->state != sbefifo_ready);
> 544
> 545 fifo->curr = client;
> 546 fifo->state = sbefifo_tx;
> 547
> 548 /* Move a threaded read() onto waiting for FIFO read
> readiness */
> 549 client->state = sbefifo_client_active;
> 550 wake_up(&client->wait);
> 551
> 552 spin_unlock_irqrestore(&fifo->wait.lock, flags);
> 553
> 554 /* FIFO Tx, reset the FIFO on error */
> 555 rv = sbefifo_up_write(fifo, buf, len);
> 556 if (rv < len) {
> 557 dev_err(fifo->dev, "FIFO write failed: %d\n",
> rv);
> 558 rv = sbefifo_reset(fifo);
> 559 if (rv < 0)
> 560 return rv;
> 561
> 562 spin_lock_irqsave(&fifo->wait.lock, flags);
> 563 fifo->state = sbefifo_ready;
> 564 client->state = sbefifo_client_idle;
> 565 wake_up(&client->wait);
> 566 wake_up_locked(&fifo->wait);
> 567 spin_unlock_irqrestore(&fifo->wait.lock,
> flags);
> 568
> 569 return -EIO;
> 570 }
> 571
> > 572 WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
> 573
> 574 /* Write completed successfully */
> 575 spin_lock_irqsave(&fifo->wait.lock, flags);
> 576 fifo->state = sbefifo_interval;
> 577 wake_up(&client->wait);
> 578 spin_unlock_irqrestore(&fifo->wait.lock, flags);
> 579
> 580 return rv;
> 581 }
> 582 EXPORT_SYMBOL_GPL(sbefifo_write);
> 583
> 584 /**
> 585 * sbefifo_read()
> 586 *
> 587 * @client The client context for the SBEFIFO
> 588 * @data The buffer of data to write, at least @len
> elements
> 589 * @len The number elements in @buffer
> 590 *
> 591 * Returns the number of elements read on success and negative
> values on
> 592 * failure. A return value of 0 indicates EOT.
> 593 */
> 594 ssize_t sbefifo_read(struct sbefifo_client *client, u32 *buf,
> ssize_t len)
> 595 {
> 596 struct sbefifo *fifo = client->fifo;
> 597 unsigned long flags;
> 598 ssize_t rv;
> 599
> 600 rv = wait_event_interruptible(client->wait,
> 601 (client->state ==
> sbefifo_client_active ||
> 602 client->state ==
> sbefifo_client_closed));
> 603 if (rv < 0)
> 604 return rv;
> 605
> 606 spin_lock_irqsave(&fifo->wait.lock, flags);
> 607 if (client->state == sbefifo_client_closed) {
> 608 spin_unlock_irqrestore(&fifo->wait.lock,
> flags);
> 609 return -EBADFD;
> 610 }
> 611
> 612 if (client->state == sbefifo_client_idle) {
> 613 spin_unlock_irqrestore(&fifo->wait.lock,
> flags);
> 614 return -EIO;
> 615 }
> 616
> 617 rv = wait_event_interruptible_locked_irq(fifo->wait,
> 618 fifo->state ==
> sbefifo_interval ||
> 619 fifo->state ==
> sbefifo_rx ||
> 620 fifo->state ==
> sbefifo_ready ||
> 621 fifo->state ==
> sbefifo_dead);
> 622 if (rv < 0) {
> 623 spin_unlock_irqrestore(&fifo->wait.lock,
> flags);
> 624 return rv;
> 625 }
> 626
> 627 if (fifo->state == sbefifo_ready) {
> 628 /* We've reset FIFO, whatever we were waiting
> for has gone */
> 629 client->state = sbefifo_client_idle;
> 630 /* We're done, wake another task up as the
> FIFO is ready */
> 631 wake_up_locked(&fifo->wait);
> 632 spin_unlock_irqrestore(&fifo->wait.lock,
> flags);
> 633 return -EIO;
> 634 }
> 635
> 636 if (fifo->state == sbefifo_dead) {
> 637 spin_unlock_irqrestore(&fifo->wait.lock,
> flags);
> 638 return -ENODEV;
> 639 }
> 640
> 641 fifo->state = sbefifo_rx;
> 642 spin_unlock_irqrestore(&fifo->wait.lock, flags);
> 643
> 644 rv = sbefifo_down_read(fifo, buf, len);
> 645 if (rv > 0)
> 646 return rv;
> 647
> 648 /* Reset the FIFO on error */
> 649 if (rv < 0) {
> 650 dev_err(fifo->dev, "FIFO read failed: %d\n",
> rv);
> 651 rv = sbefifo_reset(fifo);
> 652 if (rv < 0)
> 653 return rv;
> 654
> 655 rv = -EIO;
> 656 }
> 657
> 658 /* Read is complete one way or the other (0 length
> read or error) */
> 659 spin_lock_irqsave(&fifo->wait.lock, flags);
> 660 client->state = sbefifo_client_idle;
> 661
> 662 /* Queue next FIFO transfer */
> 663 fifo->curr = NULL;
> 664 fifo->state = sbefifo_ready;
> 665 wake_up_locked(&fifo->wait);
> 666
> 667 spin_unlock_irqrestore(&fifo->wait.lock, flags);
> 668
> 669 return rv;
> 670 }
> 671 EXPORT_SYMBOL_GPL(sbefifo_read);
> 672
> 673 /**
> 674 * sbefifo_release()
> 675 *
> 676 * @client The client context for the SBEFIFO
> 677 *
> 678 */
> 679 int sbefifo_release(struct sbefifo_client *client)
> 680 {
> 681 struct sbefifo *fifo = client->fifo;
> 682 enum sbefifo_client_state old;
> 683 unsigned long flags;
> 684 int rv;
> 685
> 686 /* Determine if we need to clean up */
> 687 spin_lock_irqsave(&client->fifo->wait.lock, flags);
> 688 old = client->state;
> 689 client->state = sbefifo_client_closed;
> 690
> 691 if (old == sbefifo_client_closed) {
> 692 spin_unlock_irqrestore(&fifo->wait.lock,
> flags);
> 693 return -EBADFD;
> 694 }
> 695
> 696 if (old == sbefifo_client_idle) {
> 697 spin_unlock_irqrestore(&fifo->wait.lock,
> flags);
> 698 return 0;
> 699 }
> 700
> 701 /* We need to clean up, get noisy about
> inconsistencies */
> 702 dev_warn(fifo->dev, "Releasing client with transfer in
> progress!\n");
> 703 WARN_ON(old != sbefifo_client_active);
> 704 WARN_ON(fifo->state == sbefifo_ready);
> 705
> 706 /* Mark ourselves as broken for cleanup */
> 707 fifo->state = sbefifo_broken;
> 708 fifo->curr = NULL;
> 709
> 710 wake_up(&client->wait);
> 711 spin_unlock_irqrestore(&client->fifo->wait.lock,
> flags);
> 712
> 713 /* Clean up poll waiter */
> 714 spin_lock_irqsave(&fifo->poll.wait.lock, flags);
> 715 del_timer_sync(&fifo->poll.timer);
> 716 fifo->poll.rv = -EBADFD;
> 717 wake_up_all_locked(&fifo->poll.wait);
> 718 spin_unlock_irqrestore(&fifo->poll.wait.lock, flags);
> 719
> 720 /* Reset the FIFO */
> 721 rv = sbefifo_reset(fifo);
> 722 if (rv < 0)
> 723 return rv;
> 724
> 725 /* Mark the FIFO as ready and wake pending transfer */
> 726 spin_lock_irqsave(&client->fifo->wait.lock, flags);
> 727 fifo->state = sbefifo_ready;
> 728 wake_up_locked(&fifo->wait);
> 729 spin_unlock_irqrestore(&client->fifo->wait.lock,
> flags);
> 730
> 731 return 0;
> 732 }
> 733 EXPORT_SYMBOL_GPL(sbefifo_release);
> 734
> 735 static int sbefifo_unregister_child(struct device *dev, void
> *data)
> 736 {
> 737 struct platform_device *pdev =
> to_platform_device(dev);
> 738
> 739 of_device_unregister(pdev);
> 740 if (dev->of_node)
> 741 of_node_clear_flag(dev->of_node,
> OF_POPULATED);
> 742
> 743 return 0;
> 744 }
> 745
> 746 static int sbefifo_probe(struct device *dev)
> 747 {
> 748 struct device_node *np;
> 749 struct sbefifo *fifo;
> 750 int child_idx;
> 751 u32 up, down;
> 752 int rv;
> 753
> 754 fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
> 755 if (!fifo)
> 756 return -ENOMEM;
> 757
> 758 fifo->dev = dev;
> 759 fifo->state = sbefifo_ready;
> 760 fifo->fsi = to_fsi_dev(dev);
> 761
> 762 fifo->id = ida_simple_get(&sbefifo_ida, 0, 0,
> GFP_KERNEL);
> 763 if (fifo->id < 0)
> 764 return fifo->id;
> 765
> 766 init_waitqueue_head(&fifo->wait);
> 767
> 768 /* No interrupts, need to poll the controller */
> > 769 setup_timer(&fifo->poll.timer, sbefifo_poll_device,
> 770 (unsigned long)fifo);
> 771 init_waitqueue_head(&fifo->poll.wait);
> 772
> 773 rv = sbefifo_up_sts(fifo, &up);
> 774 if (rv < 0)
> 775 return rv;
> 776
> 777 rv = sbefifo_down_sts(fifo, &down);
> 778 if (rv < 0)
> 779 return rv;
> 780
> 781 if (!(sbefifo_empty(up) && sbefifo_empty(down))) {
> 782 dev_warn(fifo->dev, "FIFOs were not empty,
> requesting reset from SBE\n");
> 783 /* Request the SBE reset the FIFOs */
> 784 rv = sbefifo_reset(fifo);
> 785 if (rv == -ETIMEDOUT) {
> 786 dev_warn(fifo->dev, "SBE unresponsive,
> probing FIFO clients may fail. Performing hard FIFO reset\n");
> 787 rv = sbefifo_do_reset(fifo);
> 788 if (rv < 0)
> 789 return rv;
> 790 } else if (rv < 0) {
> 791 return rv;
> 792 }
> 793 }
> 794
> 795 dev_set_drvdata(dev, fifo);
> 796 list_add(&fifo->entry, &sbefifos);
> 797
> 798 child_idx = 0;
> 799 for_each_available_child_of_node(dev->of_node, np) {
> 800 struct platform_device *child;
> 801 char name[32];
> 802
> 803 snprintf(name, sizeof(name),
> "sbefifo%d-dev%d", fifo->id,
> 804 child_idx++);
> 805 child = of_platform_device_create(np, name,
> dev);
> 806 if (!child)
> 807 dev_warn(dev, "Failed to create
> platform device %s\n",
> 808 name);
> 809 }
> 810
> 811 return 0;
> 812 }
> 813
>
> ---
> 0-DAY kernel test infrastructure Open Source Technology
> Center
> https://lists.01.org/pipermail/kbuild-all Intel
> Corporation
> Email had 1 attachment:
> + .config.gz
> 64k (application/gzip)
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^ permalink raw reply
* Re: [PATCH v5.1 1/2] ARM64: dts: meson-gx: use stable UART bindings with correct gate clock
From: Andreas Färber @ 2017-12-04 0:16 UTC (permalink / raw)
To: Neil Armstrong, khilman-rdvid1DuHRBWk0Htik3J/w, Helmut Klein
Cc: Martin Blumenstingl, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <4e0d1db1-6382-a4b7-d112-3e45e0c1af2d-l3A5Bk7waGM@public.gmane.org>
Am 03.12.2017 um 15:15 schrieb Andreas Färber:
> Hi,
>
> Am 21.06.2017 um 16:42 schrieb Neil Armstrong:
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
>> index 17d3efd..ea53cc2 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
>> @@ -682,6 +682,31 @@
>> clocks = <&clkc CLKID_SPI>;
>> };
>>
>> +&uart_A {
>> + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
>> + clock-names = "xtal", "pclk", "baud";
>> +};
>> +
>> +&uart_AO {
>> + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
>> + clock-names = "xtal", "pclk", "baud";
>> +};
>> +
>> +&uart_AO_B {
>> + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
>> + clock-names = "xtal", "pclk", "baud";
>> +};
>> +
>> +&uart_B {
>> + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
>> + clock-names = "xtal", "core", "baud";
>
> Looking at the meson_uart driver, it only looks for a "pclk" clock,
> never for "core", and the only unnamed clock used should be the first.
>
> There is no bindings documentation for "core", so I assume this was an
> oversight and should be "pclk" everywhere?
>
>> +};
>> +
>> +&uart_C {
>> + clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
>> + clock-names = "xtal", "core", "baud";
>> +};
>
> The issue I'm facing is that uart_C on NanoPi K2 is not working in
> 4.14.1. To my surprise it appears to be probing okay though.
In 4.14 the serial driver checks for the legacy compatible and if
present (even alongside the new compatible) always takes the legacy code
path, using only the first clock, thus not tripping over "core" and not
enabling the "pclk" if supplied.
This was changed for v4.15-rc1, so we should start seeing errors for
missing "pclk" clocks.
> Sadly just overwriting the clock-names property via overlay does not fix
> my issue. Any ideas?
For reference here's my latest overlay, overriding compatible, too:
https://github.com/afaerber/dt-overlays/blob/master/meson-gxbb-nanopi-k2%2Barpi600%2Bnucleo-lrwan1.dts
Regards,
Andreas
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GF: Felix Imendörffer, Jane Smithard, Graham Norton
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^ permalink raw reply
* Re: [PATCH v2 35/35] dt-bindings: timer: Add andestech atcpit100 timer binding doc
From: 陳建志 @ 2017-12-04 1:07 UTC (permalink / raw)
To: Linus Walleij
Cc: Greentime Hu, greentime, linux-kernel@vger.kernel.org,
Arnd Bergmann, linux-arch, Thomas Gleixner, Jason Cooper,
Marc Zyngier, Rob Herring, netdev, deanbo422,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Al Viro, David Howells, Will Deacon, Daniel Lezcano, linux-serial
In-Reply-To: <CACRpkdYuo88qeEznKxVojYofV4YTGu6AOgan-2GPYS9qZCVxZA@mail.gmail.com>
2017-12-01 20:19 GMT+08:00 Linus Walleij <linus.walleij@linaro.org>:
> On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu <green.hu@gmail.com> wrote:
>
>> From: Rick Chen <rickchen36@gmail.com>
>>
>> Add a document to describe Andestech atcpit100 timer and
>> binding information.
>>
>> Signed-off-by: Rick Chen <rickchen36@gmail.com>
>> Acked-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Greentime Hu <green.hu@gmail.com>
>
> Thanks for submitting this interesting architecture!
>
> (...)
>
>> +Required properties:
>> +- compatible : Should be "andestech,atcpit100"
>> +- reg : Address and length of the register set
>> +- interrupts : Reference to the timer interrupt
>> +- clocks : a clock to provide the tick rate for "andestech,atcpit100"
>> +- clock-names : should be "PCLK" for the external tick timer.
>
> This text seem wrong. PCLK is the internal timer, right? "PCLK" is
> "peripheral clock" (I hope) and that comes from the bus.
>
> Consider also adding an optional "EXTCLK" already now, since it is
> evident from the driver that this is also supported.
>
Thank you for reviewing !
I will modify it in the next patch.
Rick
> Yours,
> Linus Walleij
^ permalink raw reply
* Re: [PATCH 0/4] Move DP phy switch to PHY driver
From: Chris Zhong @ 2017-12-04 2:47 UTC (permalink / raw)
To: Heiko Stuebner, Doug Anderson
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
Kishon Vijay Abraham I, Rob Herring,
open list:ARM/Rockchip SoC..., LKML, Guenter Roeck, Sean Paul,
William wu, Rob Herring, David Airlie, Shawn Lin, Catalin Marinas,
Elaine Zhang, David Wu, Kever Yang, Brian Norris, Tomasz Figa,
Will Deacon, devicetree-u79uwXL29TY76Z2rM5mHXA, Linux ARM
In-Reply-To: <1941891.vosvJnn3h1@phil>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=gb18030; format=flowed, Size: 3236 bytes --]
Hi Heiko
On 2017Äê12ÔÂ02ÈÕ 05:58, Heiko Stuebner wrote:
> Am Freitag, 1. Dezember 2017, 13:42:46 CET schrieb Doug Anderson:
>> Hi,
>>
>> On Wed, Nov 29, 2017 at 6:27 PM, Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
>>> Hi Doug
>>>
>>> Thank you for mentioning this patch.
>>>
>>> I think the focus of the discussion is: can we put the grf control bit to
>>> dts.
>>>
>>> The RK3399 has 2 Type-C phy, but only one DP controller, this "uphy_dp_sel"
>>>
>>> can help to switch these 2 phy. So I think this bit can be considered as a
>>> part of
>>>
>>> Type-C phy, these 2 phy have different bits, just similar to other bits
>>> (such as "pipe-status").
>>>
>>> Put them to DTS file might be a accepted practice.
>> I guess the first step would be finding the person to make a decision.
>> Is that Heiko? Olof? Kishon? Rob?. As I see it there are a few
>> options:
>>
>> 1. Land this series as-is. This makes the new bit work just like all
>> the other ones next to it. If anyone happens to try to use an old
>> device tree on a new kernel they'll break. Seems rather unlikely
>> given that the whole type C PHY is not really fully functional
>> upstream, but technically this is a no-no from a device tree
>> perspective.
>>
>> 2. Change the series to make this property optional. If it's not
>> there then the code behaves like it always did. This would address
>> the "compatibility" problem but likely wouldn't actually help any real
>> people, and it would be extra work.
>>
>> 3. Redo the driver to deprecate all the old offsets / bits and just
>> put the table in the driver, keyed off the compatible string and base
>> address if the IO memory.
>>
>>
>> I can't make this decision. It's up to those folks who would be
>> landing the patch and I'd be happy with any of them. What I'm less
>> happy with, however, is the indecision preventing forward progress.
>> We should pick one of the above things and land it. My own personal
>> bias is #1: just land the series. No real people will be hurt and
>> it's just adding another property that matches the ones next to it.
> I'd second that #1 . That whole type-c phy thingy never fully worked in
> the past (some for the never used dp output), so personally I don't have
> issues with going that route.
>
>
>> From a long term perspective (AKA how I'd write the next driver like
>> this) I personally lean towards to "tables in the driver, not in the
>> device tree" but quite honestly I'm happy to take whatever direction
>> the maintainers give.
> It looks like we're in agreement here :-) . GRF stuff should not leak into
> the devicetree, as it causes endless headaches later. But I guess we'll
> need to live with the ones that happened so far.
>
So, the first step is: move all the private property of tcphy to
drivers/phy/rockchip/phy-rockchip-typec.c.
Second step: new a member: uphy-dp-sel.
In my mind, we should have discussed these properties before, and then I
moved them all into DTS.
>
>
>
>
--
Chris Zhong
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* [PATCH 0/3] bluetooth: hci_ll: Get MAC address from NVMEM
From: David Lechner @ 2017-12-04 3:21 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA
Cc: David Lechner, Rob Herring, Mark Rutland, Marcel Holtmann,
Gustavo Padovan, Johan Hedberg, netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
This series adds supporting getting the MAC address from a NVMEM provider
for "LL" HCI controllers (Texas Instruments).
The second patch is just cleaning things up before I add another similar
vendor-specific HCI command constant in the final patch.
David Lechner (3):
dt-bindings: Add optional nvmem MAC address bindings to ti,wlink-st
bluetooth: hci_ll: add constant for vendor-specific command
bluetooth: hci_ll: Add optional nvmem MAC address source
.../devicetree/bindings/net/ti,wilink-st.txt | 4 ++
drivers/bluetooth/hci_ll.c | 43 +++++++++++++++++++++-
2 files changed, 45 insertions(+), 2 deletions(-)
--
2.7.4
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* [PATCH 1/3] dt-bindings: Add optional nvmem MAC address bindings to ti,wlink-st
From: David Lechner @ 2017-12-04 3:21 UTC (permalink / raw)
To: devicetree, linux-bluetooth
Cc: David Lechner, Rob Herring, Mark Rutland, Marcel Holtmann,
Gustavo Padovan, Johan Hedberg, netdev, linux-kernel
In-Reply-To: <1512357682-8911-1-git-send-email-david@lechnology.com>
This adds optional nvmem consumer properties to the ti,wlink-st device tree
bindings to allow specifying the Bluetooth MAC address.
Signed-off-by: David Lechner <david@lechnology.com>
---
Documentation/devicetree/bindings/net/ti,wilink-st.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ti,wilink-st.txt b/Documentation/devicetree/bindings/net/ti,wilink-st.txt
index 1649c1f..24eb897 100644
--- a/Documentation/devicetree/bindings/net/ti,wilink-st.txt
+++ b/Documentation/devicetree/bindings/net/ti,wilink-st.txt
@@ -32,6 +32,8 @@ Optional properties:
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entry:
"ext_clock" (External clock provided to the TI combo chip).
+ - nvmem-cells: phandle to nvmem data cell that contains a MAC address
+ - nvmem-cell-names: "mac-address" (required when nvmem-cells is specified)
Example:
@@ -43,5 +45,7 @@ Example:
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
clocks = <&clk32k_wl18xx>;
clock-names = "ext_clock";
+ nvmem-cells: <&mac_address>
+ nvmem-cell-names "mac-address"
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/3] bluetooth: hci_ll: add constant for vendor-specific command
From: David Lechner @ 2017-12-04 3:21 UTC (permalink / raw)
To: devicetree, linux-bluetooth
Cc: David Lechner, Rob Herring, Mark Rutland, Marcel Holtmann,
Gustavo Padovan, Johan Hedberg, netdev, linux-kernel
In-Reply-To: <1512357682-8911-1-git-send-email-david@lechnology.com>
This adds a #define for the vendor-specific HCI command to set the
baudrate instead of using the bare 0xff36 multiple times.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/bluetooth/hci_ll.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/bluetooth/hci_ll.c b/drivers/bluetooth/hci_ll.c
index 447abea..974a788 100644
--- a/drivers/bluetooth/hci_ll.c
+++ b/drivers/bluetooth/hci_ll.c
@@ -56,6 +56,9 @@
#include "hci_uart.h"
+/* Vendor-specific HCI commands */
+#define HCI_VS_UPDATE_UART_HCI_BAUDRATE 0xff36
+
/* HCILL commands */
#define HCILL_GO_TO_SLEEP_IND 0x30
#define HCILL_GO_TO_SLEEP_ACK 0x31
@@ -620,7 +623,7 @@ static int download_firmware(struct ll_device *lldev)
case ACTION_SEND_COMMAND: /* action send */
bt_dev_dbg(lldev->hu.hdev, "S");
cmd = (struct hci_command *)action_ptr;
- if (cmd->opcode == 0xff36) {
+ if (cmd->opcode == HCI_VS_UPDATE_UART_HCI_BAUDRATE) {
/* ignore remote change
* baud rate HCI VS command
*/
@@ -704,7 +707,10 @@ static int ll_setup(struct hci_uart *hu)
speed = 0;
if (speed) {
- struct sk_buff *skb = __hci_cmd_sync(hu->hdev, 0xff36, sizeof(speed), &speed, HCI_INIT_TIMEOUT);
+ struct sk_buff *skb;
+
+ skb = __hci_cmd_sync(hu->hdev, HCI_VS_UPDATE_UART_HCI_BAUDRATE,
+ sizeof(speed), &speed, HCI_INIT_TIMEOUT);
if (!IS_ERR(skb)) {
kfree_skb(skb);
serdev_device_set_baudrate(serdev, speed);
--
2.7.4
^ permalink raw reply related
* [PATCH 3/3] bluetooth: hci_ll: Add optional nvmem MAC address source
From: David Lechner @ 2017-12-04 3:21 UTC (permalink / raw)
To: devicetree, linux-bluetooth
Cc: David Lechner, Rob Herring, Mark Rutland, Marcel Holtmann,
Gustavo Padovan, Johan Hedberg, netdev, linux-kernel
In-Reply-To: <1512357682-8911-1-git-send-email-david@lechnology.com>
This adds an optional nvmem consumer to get a MAC address from an external
source. The MAC address is then set in the Bluetooth chip after the
firmware has been loaded.
This has been tested working with a TI CC2560A chip (in a LEGO MINDSTORMS
EV3).
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/bluetooth/hci_ll.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/bluetooth/hci_ll.c b/drivers/bluetooth/hci_ll.c
index 974a788..dd3b5c2 100644
--- a/drivers/bluetooth/hci_ll.c
+++ b/drivers/bluetooth/hci_ll.c
@@ -53,10 +53,12 @@
#include <net/bluetooth/bluetooth.h>
#include <net/bluetooth/hci_core.h>
#include <linux/gpio/consumer.h>
+#include <linux/nvmem-consumer.h>
#include "hci_uart.h"
/* Vendor-specific HCI commands */
+#define HCI_VS_WRITE_BD_ADDR 0xfc06
#define HCI_VS_UPDATE_UART_HCI_BAUDRATE 0xff36
/* HCILL commands */
@@ -89,6 +91,7 @@ struct ll_device {
struct serdev_device *serdev;
struct gpio_desc *enable_gpio;
struct clk *ext_clk;
+ u8 *bdaddr;
};
struct ll_struct {
@@ -698,6 +701,19 @@ static int ll_setup(struct hci_uart *hu)
if (err)
return err;
+ /* Set MAC address, if any */
+ if (lldev->bdaddr) {
+ struct sk_buff *skb;
+
+ skb = __hci_cmd_sync(hu->hdev, HCI_VS_WRITE_BD_ADDR, 6,
+ lldev->bdaddr, HCI_INIT_TIMEOUT);
+ if (IS_ERR(skb))
+ bt_dev_err(hu->hdev, "Failed to set MAC address (%ld)",
+ PTR_ERR(skb));
+ else
+ kfree_skb(skb);
+ }
+
/* Operational speed if any */
if (hu->oper_speed)
speed = hu->oper_speed;
@@ -726,6 +742,7 @@ static int hci_ti_probe(struct serdev_device *serdev)
{
struct hci_uart *hu;
struct ll_device *lldev;
+ struct nvmem_cell *bdaddr_cell;
u32 max_speed = 3000000;
lldev = devm_kzalloc(&serdev->dev, sizeof(struct ll_device), GFP_KERNEL);
@@ -747,6 +764,22 @@ static int hci_ti_probe(struct serdev_device *serdev)
of_property_read_u32(serdev->dev.of_node, "max-speed", &max_speed);
hci_uart_set_speeds(hu, 115200, max_speed);
+ /* optional MAC address from nvram */
+ bdaddr_cell = nvmem_cell_get(&serdev->dev, "mac-address");
+ if (IS_ERR(bdaddr_cell)) {
+ int err = PTR_ERR(bdaddr_cell);
+
+ if (err != -ENOENT) {
+ if (err != -EPROBE_DEFER)
+ dev_err(&serdev->dev,
+ "Failed to get \"mac-address\" nvmem cell\n");
+ return err;
+ }
+ } else {
+ lldev->bdaddr = nvmem_cell_read(bdaddr_cell, NULL);
+ nvmem_cell_put(bdaddr_cell);
+ }
+
return hci_uart_register_device(hu, &llp);
}
--
2.7.4
^ permalink raw reply related
* Re: [PATCH] fsi: Add Self Boot Engine FIFO FSI client
From: kbuild test robot @ 2017-12-04 4:50 UTC (permalink / raw)
Cc: kbuild-all-JC7UmRfGjtg, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Andrew Jeffery, gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
bradleyb-r5pk2Da7Bxt8sGd51Jp2sdBPR1lH4CV8,
cbostic-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8,
joel-U3u1mxZcP9KHXe+LvDLADg,
eajames-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8, Edward A. James
In-Reply-To: <20171201130744.17659-1-andrew-zrmu5oMJ5Fs@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 18489 bytes --]
Hi Andrew,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v4.15-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Andrew-Jeffery/fsi-Add-Self-Boot-Engine-FIFO-FSI-client/20171204-031454
config: sparc64-allyesconfig (attached as .config)
compiler: sparc64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=sparc64
All errors (new ones prefixed by >>):
drivers/fsi/clients/fsi-sbefifo.c:378:21: warning: format '%d' expects argument of type 'int', but argument 9 has type 'ssize_t {aka long int}' [-Wformat=]
dev_dbg(fifo->dev, "%s: Data phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
drivers/fsi/clients/fsi-sbefifo.c:378:2: note: in expansion of macro 'dev_dbg'
dev_dbg(fifo->dev, "%s: Data phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^~~~~~~
drivers/fsi/clients/fsi-sbefifo.c:403:21: warning: format '%d' expects argument of type 'int', but argument 7 has type 'ssize_t {aka long int}' [-Wformat=]
dev_dbg(fifo->dev, "%s: EOT phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d\n, nr_xfer: %d, rem: %d\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
drivers/fsi/clients/fsi-sbefifo.c:403:2: note: in expansion of macro 'dev_dbg'
dev_dbg(fifo->dev, "%s: EOT phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d\n, nr_xfer: %d, rem: %d\n",
^~~~~~~
drivers/fsi/clients/fsi-sbefifo.c:403:21: warning: format '%d' expects argument of type 'int', but argument 9 has type 'ssize_t {aka long int}' [-Wformat=]
dev_dbg(fifo->dev, "%s: EOT phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d\n, nr_xfer: %d, rem: %d\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
drivers/fsi/clients/fsi-sbefifo.c:403:2: note: in expansion of macro 'dev_dbg'
dev_dbg(fifo->dev, "%s: EOT phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d\n, nr_xfer: %d, rem: %d\n",
^~~~~~~
drivers/fsi/clients/fsi-sbefifo.c:417:21: warning: format '%d' expects argument of type 'int', but argument 7 has type 'ssize_t {aka long int}' [-Wformat=]
dev_dbg(fifo->dev, "%s: Drain phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
drivers/fsi/clients/fsi-sbefifo.c:417:2: note: in expansion of macro 'dev_dbg'
dev_dbg(fifo->dev, "%s: Drain phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^~~~~~~
drivers/fsi/clients/fsi-sbefifo.c:417:21: warning: format '%d' expects argument of type 'int', but argument 9 has type 'ssize_t {aka long int}' [-Wformat=]
dev_dbg(fifo->dev, "%s: Drain phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
drivers/fsi/clients/fsi-sbefifo.c:417:2: note: in expansion of macro 'dev_dbg'
dev_dbg(fifo->dev, "%s: Drain phase complete: valid_set: 0x%x, eot_set: 0x%x, nr_valid: %d, nr_xfer: %d, rem: %d\n",
^~~~~~~
In file included from include/linux/list.h:9:0,
from include/linux/kobject.h:20,
from include/linux/device.h:17,
from include/linux/fsi.h:18,
from drivers/fsi/clients/fsi-sbefifo.c:6:
drivers/fsi/clients/fsi-sbefifo.c: In function 'sbefifo_down_read':
include/linux/kernel.h:792:16: warning: comparison of distinct pointer types lacks a cast
(void) (&min1 == &min2); \
^
include/linux/kernel.h:801:2: note: in expansion of macro '__min'
__min(typeof(x), typeof(y), \
^~~~~
drivers/fsi/clients/fsi-sbefifo.c:453:34: note: in expansion of macro 'min'
} while (rem && read && read == min((rem + read), SBEFIFO_FIFO_DEPTH));
^~~
drivers/fsi/clients/fsi-sbefifo.c: In function 'sbefifo_write':
drivers/fsi/clients/fsi-sbefifo.c:557:43: warning: format '%d' expects argument of type 'int', but argument 3 has type 'ssize_t {aka long int}' [-Wformat=]
dev_err(fifo->dev, "FIFO write failed: %d\n", rv);
~^
%ld
In file included from arch/sparc/include/asm/bug.h:21:0,
from include/linux/bug.h:5,
from include/linux/thread_info.h:12,
from arch/sparc/include/asm/current.h:15,
from include/linux/mutex.h:14,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:21,
from include/linux/device.h:17,
from include/linux/fsi.h:18,
from drivers/fsi/clients/fsi-sbefifo.c:6:
drivers/fsi/clients/fsi-sbefifo.c:572:17: warning: format '%d' expects argument of type 'int', but argument 4 has type 'ssize_t {aka long int}' [-Wformat=]
WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
^
include/asm-generic/bug.h:91:69: note: in definition of macro '__WARN_printf'
#define __WARN_printf(arg...) warn_slowpath_fmt(__FILE__, __LINE__, arg)
^~~
drivers/fsi/clients/fsi-sbefifo.c:572:2: note: in expansion of macro 'WARN'
WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
^~~~
drivers/fsi/clients/fsi-sbefifo.c:572:17: warning: format '%d' expects argument of type 'int', but argument 5 has type 'ssize_t {aka long int}' [-Wformat=]
WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
^
include/asm-generic/bug.h:91:69: note: in definition of macro '__WARN_printf'
#define __WARN_printf(arg...) warn_slowpath_fmt(__FILE__, __LINE__, arg)
^~~
drivers/fsi/clients/fsi-sbefifo.c:572:2: note: in expansion of macro 'WARN'
WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
^~~~
drivers/fsi/clients/fsi-sbefifo.c: In function 'sbefifo_read':
drivers/fsi/clients/fsi-sbefifo.c:650:42: warning: format '%d' expects argument of type 'int', but argument 3 has type 'ssize_t {aka long int}' [-Wformat=]
dev_err(fifo->dev, "FIFO read failed: %d\n", rv);
~^
%ld
drivers/fsi/clients/fsi-sbefifo.c: In function 'sbefifo_probe':
>> drivers/fsi/clients/fsi-sbefifo.c:769:2: error: implicit declaration of function 'setup_timer'; did you mean 'setup_tba'? [-Werror=implicit-function-declaration]
setup_timer(&fifo->poll.timer, sbefifo_poll_device,
^~~~~~~~~~~
setup_tba
cc1: some warnings being treated as errors
vim +769 drivers/fsi/clients/fsi-sbefifo.c
498
499 /**
500 * sbefifo_write()
501 *
502 * @client The client context for the SBEFIFO
503 * @buf The buffer of data to write, at least @len elements
504 * @len The number elements in @buffer
505 *
506 * The buffer must represent a complete chip-op: EOT is signalled after the
507 * last element is written to the upstream FIFO.
508 *
509 * Returns the number of elements written on success and negative values on
510 * failure. If the call is successful a subsequent call to sbefifo_read() MUST
511 * be made.
512 */
513 ssize_t sbefifo_write(struct sbefifo_client *client, const u32 *buf,
514 ssize_t len)
515 {
516 struct sbefifo *fifo = client->fifo;
517 unsigned long flags;
518 ssize_t rv;
519
520 spin_lock_irqsave(&fifo->wait.lock, flags);
521
522 if (client->state == sbefifo_client_active) {
523 dev_warn(fifo->dev, "Transfer already in progress\n");
524 spin_unlock_irqrestore(&fifo->wait.lock, flags);
525 return -EBUSY;
526 }
527
528 rv = wait_event_interruptible_locked_irq(fifo->wait,
529 fifo->state == sbefifo_ready ||
530 fifo->state == sbefifo_dead);
531 if (rv < 0) {
532 spin_unlock_irqrestore(&fifo->wait.lock, flags);
533 return rv;
534 }
535
536 if (fifo->state == sbefifo_dead) {
537 client->state = sbefifo_client_closed;
538 wake_up(&client->wait);
539 spin_unlock_irqrestore(&fifo->wait.lock, flags);
540 return -ENODEV;
541 }
542
543 WARN_ON(fifo->state != sbefifo_ready);
544
545 fifo->curr = client;
546 fifo->state = sbefifo_tx;
547
548 /* Move a threaded read() onto waiting for FIFO read readiness */
549 client->state = sbefifo_client_active;
550 wake_up(&client->wait);
551
552 spin_unlock_irqrestore(&fifo->wait.lock, flags);
553
554 /* FIFO Tx, reset the FIFO on error */
555 rv = sbefifo_up_write(fifo, buf, len);
556 if (rv < len) {
557 dev_err(fifo->dev, "FIFO write failed: %d\n", rv);
558 rv = sbefifo_reset(fifo);
559 if (rv < 0)
560 return rv;
561
562 spin_lock_irqsave(&fifo->wait.lock, flags);
563 fifo->state = sbefifo_ready;
564 client->state = sbefifo_client_idle;
565 wake_up(&client->wait);
566 wake_up_locked(&fifo->wait);
567 spin_unlock_irqrestore(&fifo->wait.lock, flags);
568
569 return -EIO;
570 }
571
> 572 WARN(rv > len, "Unreachable state: len: %d, rv: %d\n", len, rv);
573
574 /* Write completed successfully */
575 spin_lock_irqsave(&fifo->wait.lock, flags);
576 fifo->state = sbefifo_interval;
577 wake_up(&client->wait);
578 spin_unlock_irqrestore(&fifo->wait.lock, flags);
579
580 return rv;
581 }
582 EXPORT_SYMBOL_GPL(sbefifo_write);
583
584 /**
585 * sbefifo_read()
586 *
587 * @client The client context for the SBEFIFO
588 * @data The buffer of data to write, at least @len elements
589 * @len The number elements in @buffer
590 *
591 * Returns the number of elements read on success and negative values on
592 * failure. A return value of 0 indicates EOT.
593 */
594 ssize_t sbefifo_read(struct sbefifo_client *client, u32 *buf, ssize_t len)
595 {
596 struct sbefifo *fifo = client->fifo;
597 unsigned long flags;
598 ssize_t rv;
599
600 rv = wait_event_interruptible(client->wait,
601 (client->state == sbefifo_client_active ||
602 client->state == sbefifo_client_closed));
603 if (rv < 0)
604 return rv;
605
606 spin_lock_irqsave(&fifo->wait.lock, flags);
607 if (client->state == sbefifo_client_closed) {
608 spin_unlock_irqrestore(&fifo->wait.lock, flags);
609 return -EBADFD;
610 }
611
612 if (client->state == sbefifo_client_idle) {
613 spin_unlock_irqrestore(&fifo->wait.lock, flags);
614 return -EIO;
615 }
616
617 rv = wait_event_interruptible_locked_irq(fifo->wait,
618 fifo->state == sbefifo_interval ||
619 fifo->state == sbefifo_rx ||
620 fifo->state == sbefifo_ready ||
621 fifo->state == sbefifo_dead);
622 if (rv < 0) {
623 spin_unlock_irqrestore(&fifo->wait.lock, flags);
624 return rv;
625 }
626
627 if (fifo->state == sbefifo_ready) {
628 /* We've reset FIFO, whatever we were waiting for has gone */
629 client->state = sbefifo_client_idle;
630 /* We're done, wake another task up as the FIFO is ready */
631 wake_up_locked(&fifo->wait);
632 spin_unlock_irqrestore(&fifo->wait.lock, flags);
633 return -EIO;
634 }
635
636 if (fifo->state == sbefifo_dead) {
637 spin_unlock_irqrestore(&fifo->wait.lock, flags);
638 return -ENODEV;
639 }
640
641 fifo->state = sbefifo_rx;
642 spin_unlock_irqrestore(&fifo->wait.lock, flags);
643
644 rv = sbefifo_down_read(fifo, buf, len);
645 if (rv > 0)
646 return rv;
647
648 /* Reset the FIFO on error */
649 if (rv < 0) {
650 dev_err(fifo->dev, "FIFO read failed: %d\n", rv);
651 rv = sbefifo_reset(fifo);
652 if (rv < 0)
653 return rv;
654
655 rv = -EIO;
656 }
657
658 /* Read is complete one way or the other (0 length read or error) */
659 spin_lock_irqsave(&fifo->wait.lock, flags);
660 client->state = sbefifo_client_idle;
661
662 /* Queue next FIFO transfer */
663 fifo->curr = NULL;
664 fifo->state = sbefifo_ready;
665 wake_up_locked(&fifo->wait);
666
667 spin_unlock_irqrestore(&fifo->wait.lock, flags);
668
669 return rv;
670 }
671 EXPORT_SYMBOL_GPL(sbefifo_read);
672
673 /**
674 * sbefifo_release()
675 *
676 * @client The client context for the SBEFIFO
677 *
678 */
679 int sbefifo_release(struct sbefifo_client *client)
680 {
681 struct sbefifo *fifo = client->fifo;
682 enum sbefifo_client_state old;
683 unsigned long flags;
684 int rv;
685
686 /* Determine if we need to clean up */
687 spin_lock_irqsave(&client->fifo->wait.lock, flags);
688 old = client->state;
689 client->state = sbefifo_client_closed;
690
691 if (old == sbefifo_client_closed) {
692 spin_unlock_irqrestore(&fifo->wait.lock, flags);
693 return -EBADFD;
694 }
695
696 if (old == sbefifo_client_idle) {
697 spin_unlock_irqrestore(&fifo->wait.lock, flags);
698 return 0;
699 }
700
701 /* We need to clean up, get noisy about inconsistencies */
702 dev_warn(fifo->dev, "Releasing client with transfer in progress!\n");
703 WARN_ON(old != sbefifo_client_active);
704 WARN_ON(fifo->state == sbefifo_ready);
705
706 /* Mark ourselves as broken for cleanup */
707 fifo->state = sbefifo_broken;
708 fifo->curr = NULL;
709
710 wake_up(&client->wait);
711 spin_unlock_irqrestore(&client->fifo->wait.lock, flags);
712
713 /* Clean up poll waiter */
714 spin_lock_irqsave(&fifo->poll.wait.lock, flags);
715 del_timer_sync(&fifo->poll.timer);
716 fifo->poll.rv = -EBADFD;
717 wake_up_all_locked(&fifo->poll.wait);
718 spin_unlock_irqrestore(&fifo->poll.wait.lock, flags);
719
720 /* Reset the FIFO */
721 rv = sbefifo_reset(fifo);
722 if (rv < 0)
723 return rv;
724
725 /* Mark the FIFO as ready and wake pending transfer */
726 spin_lock_irqsave(&client->fifo->wait.lock, flags);
727 fifo->state = sbefifo_ready;
728 wake_up_locked(&fifo->wait);
729 spin_unlock_irqrestore(&client->fifo->wait.lock, flags);
730
731 return 0;
732 }
733 EXPORT_SYMBOL_GPL(sbefifo_release);
734
735 static int sbefifo_unregister_child(struct device *dev, void *data)
736 {
737 struct platform_device *pdev = to_platform_device(dev);
738
739 of_device_unregister(pdev);
740 if (dev->of_node)
741 of_node_clear_flag(dev->of_node, OF_POPULATED);
742
743 return 0;
744 }
745
746 static int sbefifo_probe(struct device *dev)
747 {
748 struct device_node *np;
749 struct sbefifo *fifo;
750 int child_idx;
751 u32 up, down;
752 int rv;
753
754 fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
755 if (!fifo)
756 return -ENOMEM;
757
758 fifo->dev = dev;
759 fifo->state = sbefifo_ready;
760 fifo->fsi = to_fsi_dev(dev);
761
762 fifo->id = ida_simple_get(&sbefifo_ida, 0, 0, GFP_KERNEL);
763 if (fifo->id < 0)
764 return fifo->id;
765
766 init_waitqueue_head(&fifo->wait);
767
768 /* No interrupts, need to poll the controller */
> 769 setup_timer(&fifo->poll.timer, sbefifo_poll_device,
770 (unsigned long)fifo);
771 init_waitqueue_head(&fifo->poll.wait);
772
773 rv = sbefifo_up_sts(fifo, &up);
774 if (rv < 0)
775 return rv;
776
777 rv = sbefifo_down_sts(fifo, &down);
778 if (rv < 0)
779 return rv;
780
781 if (!(sbefifo_empty(up) && sbefifo_empty(down))) {
782 dev_warn(fifo->dev, "FIFOs were not empty, requesting reset from SBE\n");
783 /* Request the SBE reset the FIFOs */
784 rv = sbefifo_reset(fifo);
785 if (rv == -ETIMEDOUT) {
786 dev_warn(fifo->dev, "SBE unresponsive, probing FIFO clients may fail. Performing hard FIFO reset\n");
787 rv = sbefifo_do_reset(fifo);
788 if (rv < 0)
789 return rv;
790 } else if (rv < 0) {
791 return rv;
792 }
793 }
794
795 dev_set_drvdata(dev, fifo);
796 list_add(&fifo->entry, &sbefifos);
797
798 child_idx = 0;
799 for_each_available_child_of_node(dev->of_node, np) {
800 struct platform_device *child;
801 char name[32];
802
803 snprintf(name, sizeof(name), "sbefifo%d-dev%d", fifo->id,
804 child_idx++);
805 child = of_platform_device_create(np, name, dev);
806 if (!child)
807 dev_warn(dev, "Failed to create platform device %s\n",
808 name);
809 }
810
811 return 0;
812 }
813
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 53052 bytes --]
^ permalink raw reply
* [PATCH v2 1/2] arm64: dts: a64-olinuxino: Enable RTL8723BS WiFi
From: Jagan Teki @ 2017-12-04 4:53 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Icenowy Zheng, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Michael Trimarchi,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Jagan Teki
Enable RTL8723BS WiFi chip on a64-olinuxino board:
- WiFi SDIO interface is connected to MMC1
- WiFi REG_ON pin connected to gpio PL2: attach to mmc-pwrseq
- WiFi HOST_WAKE pin connected to gpio PL3
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
Changes for v2:
- Remove wrong commit message
.../boot/dts/allwinner/sun50i-a64-olinuxino.dts | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
index 338e7861..8807664 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
@@ -57,6 +57,11 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+ };
};
&mmc0 {
@@ -70,6 +75,24 @@
status = "okay";
};
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <®_aldo2>;
+ vqmmc-supply = <®_dldo4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8723bs: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
+ interrupt-names = "host-wake";
+ };
+};
+
&r_rsb {
status = "okay";
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/2] arm64: allwinner: a64-sopine: Fix to use dcdc1 regulator instead of vcc3v3
From: Jagan Teki @ 2017-12-04 4:53 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Icenowy Zheng, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Michael Trimarchi,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Jagan Teki
In-Reply-To: <1512363187-8353-1-git-send-email-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Since current tree support AXP803 regulators,
replace fixed regulator vcc3v3 with AXP803 dcdc1 regulator where ever
it need to replace.
Tested mmc0 on sopine baseboard.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
Changes for v2:
- Commit message edited as fix since it has issue with sdcard detect.
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 2 +-
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi | 11 +----------
2 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
index a053a6a..abe179d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -96,7 +96,7 @@
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
- vmmc-supply = <®_vcc3v3>;
+ vmmc-supply = <®_dcdc1>;
vqmmc-supply = <®_vcc1v8>;
bus-width = <8>;
non-removable;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
index a5da18a..43418bd 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
@@ -45,19 +45,10 @@
#include "sun50i-a64.dtsi"
-/ {
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
- vmmc-supply = <®_vcc3v3>;
+ vmmc-supply = <®_dcdc1>;
non-removable;
disable-wp;
bus-width = <4>;
--
2.7.4
^ permalink raw reply related
* [PATCH v2] ARM64: dts: meson-axg: enable IR controller
From: Yixun Lan @ 2017-12-04 5:38 UTC (permalink / raw)
To: Kevin Hilman, Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Neil Armstrong, Jerome Brunet, Mark Rutland, Carlo Caione,
Yixun Lan, linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Enable IR remote controller which find in Amlogic's Meson-AXG SoC.
Signed-off-by: Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
---
Changes since v1 at [1]:
- drop the compatbile 'amlogic,meson-gx-ir'
[1]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005527.html
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 6 ++++++
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 14 ++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 0864d1ff2d9b..ca676cafdbb3 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -34,3 +34,9 @@
pinctrl-0 = <&i2c1_z_pins>;
pinctrl-names = "default";
};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 9bb85893c1b7..f68f709762dd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -616,6 +616,13 @@
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_aobus 0 0 15>;
};
+
+ remote_input_ao_pins: remote_input_ao {
+ mux {
+ groups = "remote_input_ao";
+ function = "remote_input_ao";
+ };
+ };
};
i2c_AO: i2c@5000 {
@@ -664,6 +671,13 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ ir: ir@8000 {
+ compatible = "amlogic,meson-gxbb-ir";
+ reg = <0x0 0x8000 0x0 0x20>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
};
};
};
--
2.15.0
--
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* [PATCH 0/3] pwm: meson-axg: add pwm controller driver
From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw)
To: Thierry Reding, Kevin Hilman, linux-pwm, linux-amlogic
Cc: Rob Herring, devicetree, Neil Armstrong, Jerome Brunet,
Mark Rutland, Carlo Caione, Jian Hu, Yixun Lan, linux-arm-kernel,
linux-kernel
This patch series try to add PWM controller driver for the
Amlogic's Meson-AXG SoC. Update the Clock sources, pin DT.
Jian Hu (3):
dt-bindings: pwm: update bindings for the Meson-AXG
pwm: meson: add clock source configuratin for Meson-AXG
ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC
.../devicetree/bindings/pwm/pwm-meson.txt | 2 +
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 +++++++++++++++++++++
drivers/pwm/pwm-meson.c | 26 +++++
3 files changed, 148 insertions(+)
--
2.15.0
^ permalink raw reply
* [PATCH 1/3] dt-bindings: pwm: update bindings for the Meson-AXG
From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw)
To: Thierry Reding, Kevin Hilman, linux-pwm, linux-amlogic
Cc: Mark Rutland, devicetree, Neil Armstrong, Yixun Lan, linux-kernel,
Rob Herring, Jian Hu, Carlo Caione, linux-arm-kernel,
Jerome Brunet
In-Reply-To: <20171204060018.8856-1-yixun.lan@amlogic.com>
From: Jian Hu <jian.hu@amlogic.com>
Update the doc to explicitly support Meson-AXG
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
Documentation/devicetree/bindings/pwm/pwm-meson.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-meson.txt b/Documentation/devicetree/bindings/pwm/pwm-meson.txt
index 1ee81321c35e..1fa3f7182133 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-meson.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-meson.txt
@@ -5,6 +5,8 @@ Required properties:
- compatible: Shall contain "amlogic,meson8b-pwm"
or "amlogic,meson-gxbb-pwm"
or "amlogic,meson-gxbb-ao-pwm"
+ or "amlogic,meson-axg-ee-pwm"
+ or "amlogic,meson-axg-ao-pwm"
- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
the cells format.
--
2.15.0
^ permalink raw reply related
* [PATCH 2/3] pwm: meson: add clock source configuratin for Meson-AXG
From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw)
To: Thierry Reding, Kevin Hilman, linux-pwm, linux-amlogic
Cc: Rob Herring, devicetree, Neil Armstrong, Jerome Brunet,
Mark Rutland, Carlo Caione, Jian Hu, Yixun Lan, linux-arm-kernel,
linux-kernel
In-Reply-To: <20171204060018.8856-1-yixun.lan@amlogic.com>
From: Jian Hu <jian.hu@amlogic.com>
For PWM controller in the Meson-AXG SoC, the EE domain and
AO domain have different clock source. This patch try to describe
them in the DT compatible data.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
drivers/pwm/pwm-meson.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 1f44b288af57..dcacc5c6ac1e 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -421,6 +421,24 @@ static const struct meson_pwm_data pwm_gxbb_ao_data = {
.num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
};
+static const char * const pwm_axg_ee_parent_names[] = {
+ "xtal", "fclk_div5", "fclk_div4", "fclk_div3"
+};
+
+static const struct meson_pwm_data pwm_axg_ee_data = {
+ .parent_names = pwm_axg_ee_parent_names,
+ .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
+};
+
+static const char * const pwm_axg_ao_parent_names[] = {
+ "aoclk81", "xtal", "fclk_div4", "fclk_div5"
+};
+
+static const struct meson_pwm_data pwm_axg_ao_data = {
+ .parent_names = pwm_axg_ao_parent_names,
+ .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
+};
+
static const struct of_device_id meson_pwm_matches[] = {
{
.compatible = "amlogic,meson8b-pwm",
@@ -434,6 +452,14 @@ static const struct of_device_id meson_pwm_matches[] = {
.compatible = "amlogic,meson-gxbb-ao-pwm",
.data = &pwm_gxbb_ao_data
},
+ {
+ .compatible = "amlogic,meson-axg-ee-pwm",
+ .data = &pwm_axg_ee_data
+ },
+ {
+ .compatible = "amlogic,meson-axg-ao-pwm",
+ .data = &pwm_axg_ao_data
+ },
{},
};
MODULE_DEVICE_TABLE(of, meson_pwm_matches);
--
2.15.0
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