* Re: [PATCH v6 net-next,mips 0/7] Cavium OCTEON-III network driver.
From: Philippe Ombredanne @ 2017-12-08 8:11 UTC (permalink / raw)
To: David Daney
Cc: linux-mips, ralf, James Hogan, netdev, David S. Miller,
Rob Herring, Mark Rutland, LKML, Steven J. Hill,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrew Lunn, Florian Fainelli
In-Reply-To: <20171208000934.6554-1-david.daney@cavium.com>
David,
On Fri, Dec 8, 2017 at 1:09 AM, David Daney <david.daney@cavium.com> wrote:
[]
> Changes in v5:
[]
> o Removed redundant licensing text boilerplate.
Thank you very much!
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
--
Cordially
Philippe Ombredanne, the licensing scruffy
^ permalink raw reply
* Re: [PATCH V6 4/7] OF: properties: Implement get_match_data() callback
From: Lothar Waßmann @ 2017-12-08 8:09 UTC (permalink / raw)
To: Sinan Kaya
Cc: devicetree, linux-arm-msm, timur, open list, linux-acpi,
Rob Herring, dmaengine, Frank Rowand, linux-arm-kernel
In-Reply-To: <661cbe4d-ea33-3e84-b5f2-ab6517cbb135@codeaurora.org>
Hi,
On Thu, 7 Dec 2017 12:50:50 -0500 Sinan Kaya wrote:
> On 12/7/2017 10:20 AM, Lothar Waßmann wrote:
> > Hi,
> >
> > On Thu, 7 Dec 2017 09:45:31 -0500 Sinan Kaya wrote:
> >> On 12/7/2017 8:10 AM, Lothar Waßmann wrote:
> >>>> +void *of_fwnode_get_match_data(const struct fwnode_handle *fwnode,
> >>>> + struct device *dev)
> >>> Shouldn't this be 'const void *of_fwnode_get_match_data
> >>
> >> OF keeps the driver data as a (const void*) internally. ACPI keeps the
> >> driver data as kernel_ulong_t in struct acpi_device_id.
> >>
> >> I tried to find the middle ground here by converting output to void*
> >> but not keeping const.
> >>
> > It should be no problem to cast a (const void *) to an unsigned long
> > data type (without const qualifier).
> >
>
> It is the other way around. If I change this API to return a a (const void*),
> the device_get_match_data() function need to return a (const void *).
>
> While implementing the ACPI piece, I have to convert an unsigned long to
> (const void *) in ACPI code so that the APIs are compatible.
>
That's true, but I don't see any problem with that. Your
device_get_match_data() is merely a wrapper around of_device_get_match_data()
which returns a const pointer. I see no reason to change this to a
non-const pointer by the wrapper function.
Lothar Waßmann
^ permalink raw reply
* Re: [PATCH v2 2/3] dt-bindings: Add optional nvmem BD address bindings to ti,wlink-st
From: Marcel Holtmann @ 2017-12-08 8:08 UTC (permalink / raw)
To: David Lechner, Rob Herring
Cc: devicetree, open list:BLUETOOTH DRIVERS, Mark Rutland,
Gustavo F. Padovan, Johan Hedberg, Network Development,
Linux Kernel Mailing List
In-Reply-To: <1512701860-8321-3-git-send-email-david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
Hi David,
> This adds optional nvmem consumer properties to the ti,wlink-st device tree
> bindings to allow specifying the BD address.
>
> Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
> ---
>
> v2 changes:
> * Renamed "mac-address" to "bd-address"
> * Fixed typos in example
> * Specify byte order of "bd-address"
>
> Documentation/devicetree/bindings/net/ti,wilink-st.txt | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/ti,wilink-st.txt b/Documentation/devicetree/bindings/net/ti,wilink-st.txt
> index 1649c1f..a45a508 100644
> --- a/Documentation/devicetree/bindings/net/ti,wilink-st.txt
> +++ b/Documentation/devicetree/bindings/net/ti,wilink-st.txt
> @@ -32,6 +32,9 @@ Optional properties:
> See ../clocks/clock-bindings.txt for details.
> - clock-names : Must include the following entry:
> "ext_clock" (External clock provided to the TI combo chip).
> + - nvmem-cells: phandle to nvmem data cell that contains a 6 byte BD address
> + with the most significant byte first (big-endian).
> + - nvmem-cell-names: "bd-address" (required when nvmem-cells is specified)
>
> Example:
>
> @@ -43,5 +46,7 @@ Example:
> enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
> clocks = <&clk32k_wl18xx>;
> clock-names = "ext_clock";
> + nvmem-cells = <&bd_address>;
> + nvmem-cell-names = "bd-address”;
For me this looks good, but I like to get an extra ACK from Rob on this.
Regards
Marcel
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^ permalink raw reply
* Re: [PATCH v2 1/3] Bluetooth: hci_ll: add support for setting public address
From: Marcel Holtmann @ 2017-12-08 8:07 UTC (permalink / raw)
To: David Lechner
Cc: devicetree, open list:BLUETOOTH DRIVERS, Rob Herring,
Mark Rutland, Gustavo F. Padovan, Johan Hedberg,
netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512701860-8321-2-git-send-email-david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
Hi David,
> This adds support for setting the public address on Texas Instruments
> Bluetooth chips using a vendor-specific command.
>
> This has been tested on a CC2560A. The TI wiki also indicates that this
> command should work on TI WL17xx/WL18xx Bluetooth chips.
>
> Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
> ---
>
> v2 changes:
> * This is a new patch in v2
>
> drivers/bluetooth/hci_ll.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/bluetooth/hci_ll.c b/drivers/bluetooth/hci_ll.c
> index 974a788..b732004 100644
> --- a/drivers/bluetooth/hci_ll.c
> +++ b/drivers/bluetooth/hci_ll.c
> @@ -57,6 +57,7 @@
> #include "hci_uart.h"
>
> /* Vendor-specific HCI commands */
> +#define HCI_VS_WRITE_BD_ADDR 0xfc06
> #define HCI_VS_UPDATE_UART_HCI_BAUDRATE 0xff36
>
> /* HCILL commands */
> @@ -662,6 +663,20 @@ static int download_firmware(struct ll_device *lldev)
> return err;
> }
>
> +static int ll_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr)
> +{
> + bdaddr_t bdaddr_swapped;
> + struct sk_buff *skb;
> +
> + baswap(&bdaddr_swapped, bdaddr);
> + skb = __hci_cmd_sync(hdev, HCI_VS_WRITE_BD_ADDR, sizeof(bdaddr_t),
> + &bdaddr_swapped, HCI_INIT_TIMEOUT);
> + if (!IS_ERR(skb))
> + kfree_skb(skb);
> +
You have a trailing whitespace here.
Does the HCI command really expect the BD_ADDR in the swapped order. The caller of hdev->set_bdaddr while provide it in the same order as the HCI Read BD Address command and everything in HCI. So it seems odd that you have to swap it for the vendor command.
So have you actually tested this with btmgmt public-add <xx:xx..> and checked that the address comes out correctly. I think ll_set_bdaddr should function correctly for the mgmt interface. And if needed any other caller outside of mgmt has to do the swapping.
Regards
Marcel
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^ permalink raw reply
* Re: [PATCH] arm64: allwinner: a64: orangepi-zero-plus2: add usb otg
From: Maxime Ripard @ 2017-12-08 7:57 UTC (permalink / raw)
To: Jagan Teki
Cc: Chen-Yu Tsai, Icenowy Zheng, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Michael Trimarchi,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi, Jagan Teki
In-Reply-To: <CAD6G_RQkBWth6iygyGfBX_rROEM7XUh3BmvoXfsxm8=po+kksQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1654 bytes --]
On Thu, Dec 07, 2017 at 10:23:18PM +0530, Jagan Teki wrote:
> On Thu, Dec 7, 2017 at 7:04 PM, Maxime Ripard
> <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> > Hi,
> >
> > On Thu, Dec 07, 2017 at 04:35:48PM +0530, Jagan Teki wrote:
> >> Add usb otg support for orangepi-zero-plus2 board:
> >> - Add usb_otg node with dr_mode as 'otg'
> >> - USB0-IDDET connected to PA21
> >> - VBUS connected through DCIN which always on
> >>
> >> Tested mass storage function.
> >>
> >> Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
> >
> > Did you test the OTG or peripheral modes?
>
> dr_mode with otg and I've tested mas storage gadget with mmc disk
> emulation.
So, peripheral, not OTG.
> >
> >> Note: Anyone please check vbus connection [1]
> >> Since it is connected through DCIN of vcc-5v, I've added vcc-5v0
> >> regulator for the same and attached to usb0_vbus-supply but it is
> >> disabling during kernel boot.
> >> [ 1.887854] vcc5v0: disabling
> >
> > VBUS is the power line that is provided on the USB connector. In
> > peripheral, that power is provided by the host, therefore it needs to
> > be shutdown on the peripheral end. This is the expected behaviour.
>
> So, in my test with 'otg' host drive the vbus so-it is disabling at
> target end is it?
You're not testing OTG, you're testing in peripheral mode. OTG is
switching between host and peripheral at runtime. And I'm pretty sure
this board cannot implement OTG at all, since its only source of power
seems to be USB.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH v8 4/6] clocksource: stm32: only use 32 bits timers
From: Daniel Lezcano @ 2017-12-08 7:52 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: Rob Herring, Mark Rutland, Russell King - ARM Linux,
Maxime Coquelin, Alexandre Torgue, Thomas Gleixner, Ludovic Barre,
Julien Thierry, Sudeep Holla, Arnd Bergmann,
devicetree-u79uwXL29TY76Z2rM5mHXA, Linux ARM,
Linux Kernel Mailing List
In-Reply-To: <CA+M3ks4KLy0VkJOSGR7tmefOT1rw9nrMsRQvwwK-YZQ7Gm7hQA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 07/12/2017 21:36, Benjamin Gaignard wrote:
> 2017-12-07 17:49 GMT+01:00 Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>:
>> On 07/12/2017 17:33, Benjamin Gaignard wrote:
>>> 2017-12-07 16:27 GMT+01:00 Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>:
>>>> On 14/11/2017 09:52, Benjamin Gaignard wrote:
>>>>> The clock driving counters is at 90MHz so the maximum period
>>>>> for 16 bis counters is around 750 ms which is a short period
>>>>> for a clocksource.
>>>>
>>>> Isn't it 728us ?
>>>
>>> yes it is: 2^16 / 90.000.000 => 728us
>>
>> Ok, now I can do the connection with the previous patch.
>>
>> So, the real issue of all this is the 16bits clocksource is wrapping up
>> every 728us, hence the clockevent periodically expires every ~728us to
>> keep the timekeeping consistent. Unfortunately, the kernel has a too
>> high overhead for this as the system is consistently processing this
>> timer leading to a CPU time resource starvation.
>>
>> Is that correct ?
>
> Yes that is correct
Oh man. That was unclear since the beginning, we are not talking about
inaccurate clocksource or whatever but just these 16bits timers can't
work on Linux.
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
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^ permalink raw reply
* [PATCH 2/2] ARM: dts: sun8i: a83t: Enable Ethernet on two boards
From: Chen-Yu Tsai @ 2017-12-08 7:31 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Corentin Labbe, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20171208073157.14599-1-wens-jdAy2FN1RRM@public.gmane.org>
The Cubietruck Plus has a Realtek RTL8211E RGMII PHY tied to the EMAC.
The AXP818 PMIC's regulators provide main power and secondary signaling
voltages to the PHY. The latter is always on, as it also supplies the
pingroup on the SoC, which has other uses.
The Bananapi M3 has a Realtek RTL8211E RGMII PHY tied to the EMAC.
The AXP818 PMIC's SW regulators provides power to the PHY.
This patch enables Ethernet with the EMAC on both these boards by
enabling the emac node and setting all the required properties.
A proper ethernet alias is added as well.
Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 19 +++++++++++++++++++
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 17 +++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index c606af3dbfed..6550bf0e594b 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -52,6 +52,7 @@
compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -88,6 +89,24 @@
/* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_sw>;
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii";
+ allwinner,rx-delay-ps = <700>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+&mdio {
+ rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index 7f0a3f6d0cf2..6da08cd0e107 100644
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -52,6 +52,7 @@
compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -154,6 +155,22 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_dldo4>;
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&mdio {
+ rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
--
2.15.0
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: sun8i: a83t: add dwmac-sun8i device node
From: Chen-Yu Tsai @ 2017-12-08 7:31 UTC (permalink / raw)
To: Maxime Ripard
Cc: Corentin LABBE, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Chen-Yu Tsai
In-Reply-To: <20171208073157.14599-1-wens-jdAy2FN1RRM@public.gmane.org>
From: Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 speed.
This patch add support for it on the Allwinner a83t SoC Device-tree.
This patch add the emac device node and the related RGMII pins node.
Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 19acae1b4089..a384b766f3dc 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -336,6 +336,18 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ emac_rgmii_pins: emac-rgmii-pins {
+ pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+ "PD11", "PD12", "PD13", "PD14", "PD18",
+ "PD19", "PD21", "PD22", "PD23";
+ function = "gmac";
+ /*
+ * data lines in RGMII mode use DDR mode
+ * and need a higher signal drive strength
+ */
+ drive-strength = <40>;
+ };
+
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
@@ -440,6 +452,27 @@
status = "disabled";
};
+ emac: ethernet@1c30000 {
+ compatible = "allwinner,sun8i-a83t-emac";
+ syscon = <&syscon>;
+ reg = <0x01c30000 0x104>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu 13>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu 27>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
--
2.15.0
^ permalink raw reply related
* [PATCH 0/2] ARM: sun8i: a83t: Enable EMAC Ethernet
From: Chen-Yu Tsai @ 2017-12-08 7:31 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Corentin Labbe, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Hi,
This is my spin on enabling Ethernet on the A83T. It consists of
Corentin's dtsi patch plus my board level patch. There's nothing
really special about them.
ChenYu
Chen-Yu Tsai (1):
ARM: dts: sun8i: a83t: Enable Ethernet on two boards
Corentin LABBE (1):
ARM: dts: sun8i: a83t: add dwmac-sun8i device node
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 19 ++++++++++++++
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 17 ++++++++++++
arch/arm/boot/dts/sun8i-a83t.dtsi | 33 ++++++++++++++++++++++++
3 files changed, 69 insertions(+)
--
2.15.0
^ permalink raw reply
* Re: [PATCH v3 2/2] clocksource: sprd: Add timer driver for Spreadtrum SC9860 platform
From: Daniel Lezcano @ 2017-12-08 6:58 UTC (permalink / raw)
To: Baolin Wang, tglx-hfZtesqFncYOwBW4kG4KsQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
broonie-DgEjT+Ai2ygdnm+yROfE0A,
baolin.wang-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <c85f55a434efada592c50f46c0d0532fdb5340b0.1512708743.git.baolin.wang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
On 08/12/2017 06:03, Baolin Wang wrote:
> The Spreadtrum SC9860 platform will use the architected timers as local
> clock events, but we also need a broadcast timer device to wakeup the
> cpus when the cpus are in sleep mode.
>
> The Spreadtrum timer can support 32bit or 64bit counter, as well as
> supporting period mode or one-shot mode.
>
> Signed-off-by: Baolin Wang <baolin.wang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
> ---
> Changes since v2:
> - Add more timer description in changelog.
> - Rename the driver file.
> - Remove GENERIC_CLOCKEVENTS and ARCH_SPRD dependency.
> - Remove some redundant headfiles.
> - Use timer-of APIs.
> - Change the license format according to Linus[1][2][3],
> Thomas[4] and Greg[5] comments on the topic.
> [1] https://lkml.org/lkml/2017/11/2/715
> [2] https://lkml.org/lkml/2017/11/25/125
> [3] https://lkml.org/lkml/2017/11/25/133
> [4] https://lkml.org/lkml/2017/11/2/805
> [5] https://lkml.org/lkml/2017/10/19/165
>
> Changes since v1:
> - Change to 32bit counter to avoid build warning.
> ---
> drivers/clocksource/Kconfig | 7 ++
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/timer-sprd.c | 168 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 176 insertions(+)
> create mode 100644 drivers/clocksource/timer-sprd.c
>
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index c729a88..9a6b087 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -441,6 +441,13 @@ config MTK_TIMER
> help
> Support for Mediatek timer driver.
>
> +config SPRD_TIMER
> + bool "Spreadtrum timer driver" if COMPILE_TEST
> + depends on HAS_IOMEM
> + select TIMER_OF
> + help
> + Enables the support for the Spreadtrum timer driver.
> +
> config SYS_SUPPORTS_SH_MTU2
> bool
>
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 72711f1..d6dec44 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -54,6 +54,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
> obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
> obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
> obj-$(CONFIG_OWL_TIMER) += owl-timer.o
> +obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
>
> obj-$(CONFIG_ARC_TIMERS) += arc_timer.o
> obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
> diff --git a/drivers/clocksource/timer-sprd.c b/drivers/clocksource/timer-sprd.c
> new file mode 100644
> index 0000000..81a5f0c
> --- /dev/null
> +++ b/drivers/clocksource/timer-sprd.c
> @@ -0,0 +1,168 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 Spreadtrum Communications Inc.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +
> +#include "timer-of.h"
> +
> +#define TIMER_NAME "sprd_timer"
> +
> +#define TIMER_LOAD_LO 0x0
> +#define TIMER_LOAD_HI 0x4
> +#define TIMER_VALUE_LO 0x8
> +#define TIMER_VALUE_HI 0xc
> +
> +#define TIMER_CTL 0x10
> +#define TIMER_CTL_PERIOD_MODE BIT(0)
> +#define TIMER_CTL_ENABLE BIT(1)
> +#define TIMER_CTL_64BIT_WIDTH BIT(16)
> +
> +#define TIMER_INT 0x14
> +#define TIMER_INT_EN BIT(0)
> +#define TIMER_INT_RAW_STS BIT(1)
> +#define TIMER_INT_MASK_STS BIT(2)
> +#define TIMER_INT_CLR BIT(3)
> +
> +#define TIMER_VALUE_SHDW_LO 0x18
> +#define TIMER_VALUE_SHDW_HI 0x1c
> +
> +#define TIMER_VALUE_LO_MASK GENMASK(31, 0)
> +
> +static void sprd_timer_enable(void __iomem *base, u32 flag)
> +{
> + u32 val = readl_relaxed(base + TIMER_CTL);
> +
> + val |= TIMER_CTL_ENABLE;
> + if (flag & TIMER_CTL_64BIT_WIDTH)
> + val |= TIMER_CTL_64BIT_WIDTH;
> + else
> + val &= ~TIMER_CTL_64BIT_WIDTH;
> +
> + if (flag & TIMER_CTL_PERIOD_MODE)
> + val |= TIMER_CTL_PERIOD_MODE;
> + else
> + val &= ~TIMER_CTL_PERIOD_MODE;
> +
> + writel_relaxed(val, base + TIMER_CTL);
> +}
> +
> +static void sprd_timer_disable(void __iomem *base)
> +{
> + u32 val = readl_relaxed(base + TIMER_CTL);
> +
> + val &= ~TIMER_CTL_ENABLE;
> + writel_relaxed(val, base + TIMER_CTL);
> +}
> +
> +static void sprd_timer_update_counter(void __iomem *base, unsigned long cycles)
> +{
> + writel_relaxed(cycles & TIMER_VALUE_LO_MASK, base + TIMER_LOAD_LO);
> + writel_relaxed(0, base + TIMER_LOAD_HI);
> +}
> +
> +static void sprd_timer_enable_interrupt(void __iomem *base)
> +{
> + writel_relaxed(TIMER_INT_EN, base + TIMER_INT);
> +}
> +
> +static void sprd_timer_clear_interrupt(void __iomem *base)
> +{
> + u32 val = readl_relaxed(base + TIMER_INT);
> +
> + val |= TIMER_INT_CLR;
> + writel_relaxed(val, base + TIMER_INT);
> +}
> +
> +static int sprd_timer_set_next_event(unsigned long cycles,
> + struct clock_event_device *ce)
> +{
> + struct timer_of *to = to_timer_of(ce);
> +
> + sprd_timer_disable(timer_of_base(to));
> + sprd_timer_update_counter(timer_of_base(to), cycles);
> + sprd_timer_enable(timer_of_base(to), 0);
> +
> + return 0;
> +}
> +
> +static int sprd_timer_set_periodic(struct clock_event_device *ce)
> +{
> + struct timer_of *to = to_timer_of(ce);
> +
> + sprd_timer_disable(timer_of_base(to));
> + sprd_timer_update_counter(timer_of_base(to), timer_of_period(to));
> + sprd_timer_enable(timer_of_base(to), TIMER_CTL_PERIOD_MODE);
> +
> + return 0;
> +}
> +
> +static int sprd_timer_shutdown(struct clock_event_device *ce)
> +{
> + struct timer_of *to = to_timer_of(ce);
> +
> + sprd_timer_disable(timer_of_base(to));
> + return 0;
> +}
> +
> +static irqreturn_t sprd_timer_interrupt(int irq, void *dev_id)
> +{
> + struct clock_event_device *ce = (struct clock_event_device *)dev_id;
> + struct timer_of *to = to_timer_of(ce);
> +
> + sprd_timer_clear_interrupt(timer_of_base(to));
> +
> + if (clockevent_state_oneshot(ce))
> + sprd_timer_disable(timer_of_base(to));
> +
> + ce->event_handler(ce);
> + return IRQ_HANDLED;
> +}
> +
> +static struct timer_of to = {
> + .flags = TIMER_OF_IRQ | TIMER_OF_BASE,
Why not the TIMER_OF_CLOCK ?
> +
> + .clkevt = {
> + .name = TIMER_NAME,
> + .rating = 300,
> + .features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_PERIODIC |
> + CLOCK_EVT_FEAT_ONESHOT,
> + .set_state_shutdown = sprd_timer_shutdown,
> + .set_state_periodic = sprd_timer_set_periodic,
> + .set_next_event = sprd_timer_set_next_event,
> + .cpumask = cpu_possible_mask,
> + },
> +
> + .of_irq = {
> + .handler = sprd_timer_interrupt,
> + .flags = IRQF_TIMER | IRQF_IRQPOLL,
> + },
> +};
> +
> +static int __init sprd_timer_init(struct device_node *np)
> +{
> + int ret;
> + u32 freq;
> +
> + ret = timer_of_init(np, &to);
> + if (ret)
> + return ret;
> +
> + ret = of_property_read_u32(np, "clock-frequency", &freq);
> + if (ret) {
> + pr_err("failed to get clock frequency\n");
> + timer_of_cleanup(&to);
> + return ret;
> + }
> +
> + to.of_clk.period = DIV_ROUND_UP(freq, HZ);
> +
> + sprd_timer_enable_interrupt(timer_of_base(&to));
> + clockevents_config_and_register(&to.clkevt, freq, 1, UINT_MAX);
> +
> + return 0;
> +}
> +
> +TIMER_OF_DECLARE(sc9860_timer, "sprd,sc9860-timer", sprd_timer_init);
>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
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^ permalink raw reply
* Re: [PATCH 00/20] ARM: dts: add omap clkctrl support
From: Tero Kristo @ 2017-12-08 6:58 UTC (permalink / raw)
To: Tony Lindgren
Cc: bcousson-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171207211620.GD28152-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
On 07/12/17 23:16, Tony Lindgren wrote:
> * Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org> [171207 00:49]:
>> Hi,
>>
>> This series adds the clkctrl support for omap2 family SoCs for am33xx,
>> am43xx, omap4, omap5, dra7 and dm81xx. This series depends on the
>> previously posted drivers/clk [1] + mach-omap2 [2] series for the same.
>
> Looks good to me except the comments I made on patch 14/20 that applies
> to many of these patches.
Ok, let me update my script to use the human readable values for these,
I'll repost once done.
-Tero
--
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^ permalink raw reply
* [PATCH v1 4/4] arm64: dts: mediatek: add mt2712 cpufreq related device nodes
From: Andrew-sh Cheng @ 2017-12-08 6:07 UTC (permalink / raw)
To: rjw, viresh.kumar, matthias.bgg, mark.rutland
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
srv_heupstream, robh+dt, devicetree, Andrew-sh Cheng
In-Reply-To: <1512713278-17807-1-git-send-email-andrew-sh.cheng@mediatek.com>
Add opp v2 information,
and also add clocks, regulators and opp information into cpu nodes
Signed-off-by: Andrew-sh Cheng <andrew-sh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 27 ++++++++++++++
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 57 +++++++++++++++++++++++++++++
2 files changed, 84 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
index 14163b9..d47f3c7 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -26,6 +26,33 @@
linux,initrd-start = <0x45000000>;
linux,initrd-end = <0x4a000000>;
};
+
+ cpus_fixed_vproc0: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vproc_buck0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ cpus_fixed_vproc1: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vproc_buck1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+};
+
+&cpu0 {
+ proc-supply = <&cpus_fixed_vproc0>;
+};
+
+&cpu1 {
+ proc-supply = <&cpus_fixed_vproc0>;
+};
+
+&cpu2 {
+ proc-supply = <&cpus_fixed_vproc1>;
};
&uart0 {
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 61dd763..fdf66f4 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -16,6 +16,48 @@
#address-cells = <2>;
#size-cells = <2>;
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00 {
+ opp-hz = /bits/ 64 <598000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <702000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <1000000>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00 {
+ opp-hz = /bits/ 64 <598000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <702000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <897000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1001000000>;
+ opp-microvolt = <1000000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -41,6 +83,11 @@
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x000>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_F_MP0_PLL1>;
+ clock-names = "cpu", "intermediate";
+ proc-supply = <&cpus_fixed_vproc0>;
+ operating-points-v2 = <&cluster0_opp>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
@@ -49,6 +96,11 @@
compatible = "arm,cortex-a35";
reg = <0x001>;
enable-method = "psci";
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_F_MP0_PLL1>;
+ clock-names = "cpu", "intermediate";
+ proc-supply = <&cpus_fixed_vproc0>;
+ operating-points-v2 = <&cluster0_opp>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
@@ -57,6 +109,11 @@
compatible = "arm,cortex-a72";
reg = <0x200>;
enable-method = "psci";
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_F_BIG_PLL1>;
+ clock-names = "cpu", "intermediate";
+ proc-supply = <&cpus_fixed_vproc1>;
+ operating-points-v2 = <&cluster1_opp>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
--
2.6.4
^ permalink raw reply related
* [PATCH v1 3/4] arm64: dts: mediatek: add mt8173 cpufreq related device nodes
From: Andrew-sh Cheng @ 2017-12-08 6:07 UTC (permalink / raw)
To: rjw, viresh.kumar, matthias.bgg, mark.rutland
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
srv_heupstream, robh+dt, devicetree, Andrew-sh Cheng
In-Reply-To: <1512713278-17807-1-git-send-email-andrew-sh.cheng@mediatek.com>
Add opp v2 information,
and also add clocks, regulators and opp information into cpu nodes
Signed-off-by: Andrew-sh Cheng <andrew-sh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 ++++++
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 90 +++++++++++++++++++++++++++++
2 files changed, 108 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 1c3634f..369dfcd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -74,6 +74,24 @@
status = "okay";
};
+&cpu0 {
+ proc-supply = <&mt6397_vpca15_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6397_vpca15_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+};
+
&dpi0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 26396ef..31bc593 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -51,6 +51,80 @@
mdp_wrot1 = &mdp_wrot1;
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-507000000 {
+ opp-hz = /bits/ 64 <507000000>;
+ opp-microvolt = <859000>;
+ };
+ opp-702000000 {
+ opp-hz = /bits/ 64 <702000000>;
+ opp-microvolt = <908000>;
+ };
+ opp-1001000000 {
+ opp-hz = /bits/ 64 <1001000000>;
+ opp-microvolt = <983000>;
+ };
+ opp-1105000000 {
+ opp-hz = /bits/ 64 <1105000000>;
+ opp-microvolt = <1009000>;
+ };
+ opp-1209000000 {
+ opp-hz = /bits/ 64 <1209000000>;
+ opp-microvolt = <1034000>;
+ };
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <1057000>;
+ };
+ opp-1508000000 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <1109000>;
+ };
+ opp-1703000000 {
+ opp-hz = /bits/ 64 <1703000000>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-507000000 {
+ opp-hz = /bits/ 64 <507000000>;
+ opp-microvolt = <828000>;
+ };
+ opp-702000000 {
+ opp-hz = /bits/ 64 <702000000>;
+ opp-microvolt = <867000>;
+ };
+ opp-1001000000 {
+ opp-hz = /bits/ 64 <1001000000>;
+ opp-microvolt = <927000>;
+ };
+ opp-1209000000 {
+ opp-hz = /bits/ 64 <1209000000>;
+ opp-microvolt = <968000>;
+ };
+ opp-1404000000 {
+ opp-hz = /bits/ 64 <1404000000>;
+ opp-microvolt = <1007000>;
+ };
+ opp-1612000000 {
+ opp-hz = /bits/ 64 <1612000000>;
+ opp-microvolt = <1049000>;
+ };
+ opp-1807000000 {
+ opp-hz = /bits/ 64 <1807000000>;
+ opp-microvolt = <1089000>;
+ };
+ opp-2106000000 {
+ opp-hz = /bits/ 64 <2106000000>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -81,6 +155,10 @@
reg = <0x000>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
@@ -89,6 +167,10 @@
reg = <0x001>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@100 {
@@ -97,6 +179,10 @@
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
};
cpu3: cpu@101 {
@@ -105,6 +191,10 @@
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
};
idle-states {
--
2.6.4
^ permalink raw reply related
* [PATCH v1 2/4] cpufreq: mediatek: Add mediatek related projects into blacklist
From: Andrew-sh Cheng @ 2017-12-08 6:07 UTC (permalink / raw)
To: rjw, viresh.kumar, matthias.bgg, mark.rutland
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
srv_heupstream, robh+dt, devicetree, Andrew-sh Cheng
In-Reply-To: <1512713278-17807-1-git-send-email-andrew-sh.cheng@mediatek.com>
mediatek projects will use mediate-cpufreq.c as cpufreq driver,
instead of using cpufreq_dt.c
Add mediatek related projects into cpufreq-dt blacklist
Signed-off-by: Andrew-sh Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index ecc56e2..3b585e4 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -108,6 +108,14 @@ static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "marvell,armadaxp", },
+ { .compatible = "mediatek,mt2701", },
+ { .compatible = "mediatek,mt2712", },
+ { .compatible = "mediatek,mt7622", },
+ { .compatible = "mediatek,mt7623", },
+ { .compatible = "mediatek,mt817x", },
+ { .compatible = "mediatek,mt8173", },
+ { .compatible = "mediatek,mt8176", },
+
{ .compatible = "nvidia,tegra124", },
{ .compatible = "st,stih407", },
--
2.6.4
^ permalink raw reply related
* [PATCH v1 1/4] cpufreq: mediatek: add mt2712 into compatible list
From: Andrew-sh Cheng @ 2017-12-08 6:07 UTC (permalink / raw)
To: rjw, viresh.kumar, matthias.bgg, mark.rutland
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
srv_heupstream, robh+dt, devicetree, Andrew-sh Cheng
In-Reply-To: <1512713278-17807-1-git-send-email-andrew-sh.cheng@mediatek.com>
Support mt2712 in mediatek-cpufreq.c
Signed-off-by: Andrew-sh Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 18c4bd9..62aec5c 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -574,6 +574,7 @@ static struct platform_driver mtk_cpufreq_platdrv = {
/* List of machines supported by this driver */
static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
{ .compatible = "mediatek,mt2701", },
+ { .compatible = "mediatek,mt2712", },
{ .compatible = "mediatek,mt7622", },
{ .compatible = "mediatek,mt7623", },
{ .compatible = "mediatek,mt817x", },
--
2.6.4
^ permalink raw reply related
* [PATCH v1 0/4] add support of cpufreq to mt8173 and mt2712
From: Andrew-sh Cheng @ 2017-12-08 6:07 UTC (permalink / raw)
To: rjw-LthD3rsA81gm4RdzfppkhA, viresh.kumar-QSEj5FYQhm4dnm+yROfE0A,
matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w, mark.rutland-5wv7dgnIgG8
Cc: linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
Andrew-sh Cheng
This series is based on v4.15-rc1 and [1].
Mediatek projects will use mediate-cpufreq.c as cpufreq driver,
so add mediatek related projects into black list of cpufreq_dt.c
mt8173 and mt2712 both support 2 clusters, and the main difference
is that mt2712 currently only support fixed voltage.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2017-November/544072.html
Andrew-sh Cheng (4):
cpufreq: mediatek: add mt2712 into compatible list
cpufreq: mediatek: Add mediatek related projects into blacklist
arm64: dts: mediatek: add mt8173 cpufreq related device nodes
arm64: dts: mediatek: add mt2712 cpufreq related device nodes
arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 27 +++++++++
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 57 ++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 ++++++
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 90 +++++++++++++++++++++++++++++
drivers/cpufreq/cpufreq-dt-platdev.c | 8 +++
drivers/cpufreq/mediatek-cpufreq.c | 1 +
6 files changed, 201 insertions(+)
--
2.6.4
--
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^ permalink raw reply
* Re: [PATCH v2 2/3] arm64: allwinner: axp803: Add drivevbus regulator
From: Jagan Teki @ 2017-12-08 5:32 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Maxime Ripard, Icenowy Zheng, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Michael Trimarchi, linux-arm-kernel,
devicetree, linux-kernel, linux-sunxi, Jagan Teki
In-Reply-To: <CAGb2v671Gra_Fq3Oa96zsQVeABxu0VKRyzVsiba93s5j+WqboA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Fri, Dec 8, 2017 at 8:22 AM, Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
> On Fri, Dec 8, 2017 at 3:04 AM, Jagan Teki <jagannadh.teki-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> Add reg_drivevbus regualtor for boards which are using
>> external regulator to drive the OTG VBus through N_VBUSEN
>> PMIC pin.
>>
>> Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
>> ---
>> Changes for v2:
>> - New patch
>>
>> arch/arm64/boot/dts/allwinner/axp803.dtsi | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi
>> index ff8af52..e5eae8b 100644
>> --- a/arch/arm64/boot/dts/allwinner/axp803.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi
>> @@ -146,5 +146,10 @@
>> regulator-max-microvolt = <3000000>;
>> regulator-name = "rtc-ldo";
>> };
>> +
>> + reg_drivevbus: drivevbus {
>
> Could you keep the nodes in alphabetical order please?
thought the same, but this seems to be different regulator from above
AXP_DESC regulators and even binding documentation follow this order.
thanks!
--
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
^ permalink raw reply
* Re: [PATCH v2 08/35] nds32: Process management
From: Greentime Hu @ 2017-12-08 5:27 UTC (permalink / raw)
To: Al Viro
Cc: Greentime, Linux Kernel Mailing List, Arnd Bergmann, linux-arch,
Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring, netdev,
Vincent Chen, DTML, David Howells, Will Deacon, Daniel Lezcano,
linux-serial, Vincent Chen
In-Reply-To: <20171207164506.GE21978@ZenIV.linux.org.uk>
2017-12-08 0:45 GMT+08:00 Al Viro <viro@zeniv.linux.org.uk>:
> On Mon, Nov 27, 2017 at 08:27:55PM +0800, Greentime Hu wrote:
>
>> +#define start_thread(regs,pc,stack) \
>> +({ \
>> + set_fs(USER_DS); \
>
> Not the job of start_thread() - its users (->load_binary() methods of
> assorted binfmt) must (and do) call flush_old_exec() first. And
> that will switch to USER_DS just fine.
Thanks. I will remove this setting in the next version patch.
^ permalink raw reply
* Re: [PATCH v2 06/35] nds32: MMU fault handling and page table management
From: Greentime Hu @ 2017-12-08 5:26 UTC (permalink / raw)
To: Al Viro
Cc: Greentime, Linux Kernel Mailing List, Arnd Bergmann, linux-arch,
Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring, netdev,
Vincent Chen, DTML, David Howells, Will Deacon, Daniel Lezcano,
linux-serial-u79uwXL29TY76Z2rM5mHXA, Vincent Chen
In-Reply-To: <20171207164040.GD21978-3bDd1+5oDREiFSDQTTA3OLVCufUGDwFn@public.gmane.org>
2017-12-08 0:40 GMT+08:00 Al Viro <viro-RmSDqhL/yNMiFSDQTTA3OLVCufUGDwFn@public.gmane.org>:
> On Mon, Nov 27, 2017 at 08:27:53PM +0800, Greentime Hu wrote:
>> +void do_page_fault(unsigned long entry, unsigned long addr,
>> + unsigned int error_code, struct pt_regs *regs)
> [snip]
>> + /*
>> + * If we're in an interrupt or have no user
>> + * context, we must not take the fault..
>> + */
>> + if (unlikely(in_atomic() || !mm))
>
> Broken. in_atomic() is wrong here - it should be faulthandler_disabled().
Thanks.
I will include <linux/uaccess.h> and replace in_atomic() with
faulthandler_disabled()
I will fix it in the next version patch.
--
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^ permalink raw reply
* [PATCH v3 2/2] clocksource: sprd: Add timer driver for Spreadtrum SC9860 platform
From: Baolin Wang @ 2017-12-08 5:03 UTC (permalink / raw)
To: daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
tglx-hfZtesqFncYOwBW4kG4KsQ, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
broonie-DgEjT+Ai2ygdnm+yROfE0A,
baolin.wang-QSEj5FYQhm4dnm+yROfE0A,
baolin.wang-lxIno14LUO0EEoCn2XhGlw
In-Reply-To: <1b80566bd849d68b0fc8de54ecbbc7b4efbb1077.1512708743.git.baolin.wang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
The Spreadtrum SC9860 platform will use the architected timers as local
clock events, but we also need a broadcast timer device to wakeup the
cpus when the cpus are in sleep mode.
The Spreadtrum timer can support 32bit or 64bit counter, as well as
supporting period mode or one-shot mode.
Signed-off-by: Baolin Wang <baolin.wang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
---
Changes since v2:
- Add more timer description in changelog.
- Rename the driver file.
- Remove GENERIC_CLOCKEVENTS and ARCH_SPRD dependency.
- Remove some redundant headfiles.
- Use timer-of APIs.
- Change the license format according to Linus[1][2][3],
Thomas[4] and Greg[5] comments on the topic.
[1] https://lkml.org/lkml/2017/11/2/715
[2] https://lkml.org/lkml/2017/11/25/125
[3] https://lkml.org/lkml/2017/11/25/133
[4] https://lkml.org/lkml/2017/11/2/805
[5] https://lkml.org/lkml/2017/10/19/165
Changes since v1:
- Change to 32bit counter to avoid build warning.
---
drivers/clocksource/Kconfig | 7 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-sprd.c | 168 ++++++++++++++++++++++++++++++++++++++
3 files changed, 176 insertions(+)
create mode 100644 drivers/clocksource/timer-sprd.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index c729a88..9a6b087 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -441,6 +441,13 @@ config MTK_TIMER
help
Support for Mediatek timer driver.
+config SPRD_TIMER
+ bool "Spreadtrum timer driver" if COMPILE_TEST
+ depends on HAS_IOMEM
+ select TIMER_OF
+ help
+ Enables the support for the Spreadtrum timer driver.
+
config SYS_SUPPORTS_SH_MTU2
bool
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 72711f1..d6dec44 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
obj-$(CONFIG_OWL_TIMER) += owl-timer.o
+obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
obj-$(CONFIG_ARC_TIMERS) += arc_timer.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
diff --git a/drivers/clocksource/timer-sprd.c b/drivers/clocksource/timer-sprd.c
new file mode 100644
index 0000000..81a5f0c
--- /dev/null
+++ b/drivers/clocksource/timer-sprd.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Spreadtrum Communications Inc.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+
+#include "timer-of.h"
+
+#define TIMER_NAME "sprd_timer"
+
+#define TIMER_LOAD_LO 0x0
+#define TIMER_LOAD_HI 0x4
+#define TIMER_VALUE_LO 0x8
+#define TIMER_VALUE_HI 0xc
+
+#define TIMER_CTL 0x10
+#define TIMER_CTL_PERIOD_MODE BIT(0)
+#define TIMER_CTL_ENABLE BIT(1)
+#define TIMER_CTL_64BIT_WIDTH BIT(16)
+
+#define TIMER_INT 0x14
+#define TIMER_INT_EN BIT(0)
+#define TIMER_INT_RAW_STS BIT(1)
+#define TIMER_INT_MASK_STS BIT(2)
+#define TIMER_INT_CLR BIT(3)
+
+#define TIMER_VALUE_SHDW_LO 0x18
+#define TIMER_VALUE_SHDW_HI 0x1c
+
+#define TIMER_VALUE_LO_MASK GENMASK(31, 0)
+
+static void sprd_timer_enable(void __iomem *base, u32 flag)
+{
+ u32 val = readl_relaxed(base + TIMER_CTL);
+
+ val |= TIMER_CTL_ENABLE;
+ if (flag & TIMER_CTL_64BIT_WIDTH)
+ val |= TIMER_CTL_64BIT_WIDTH;
+ else
+ val &= ~TIMER_CTL_64BIT_WIDTH;
+
+ if (flag & TIMER_CTL_PERIOD_MODE)
+ val |= TIMER_CTL_PERIOD_MODE;
+ else
+ val &= ~TIMER_CTL_PERIOD_MODE;
+
+ writel_relaxed(val, base + TIMER_CTL);
+}
+
+static void sprd_timer_disable(void __iomem *base)
+{
+ u32 val = readl_relaxed(base + TIMER_CTL);
+
+ val &= ~TIMER_CTL_ENABLE;
+ writel_relaxed(val, base + TIMER_CTL);
+}
+
+static void sprd_timer_update_counter(void __iomem *base, unsigned long cycles)
+{
+ writel_relaxed(cycles & TIMER_VALUE_LO_MASK, base + TIMER_LOAD_LO);
+ writel_relaxed(0, base + TIMER_LOAD_HI);
+}
+
+static void sprd_timer_enable_interrupt(void __iomem *base)
+{
+ writel_relaxed(TIMER_INT_EN, base + TIMER_INT);
+}
+
+static void sprd_timer_clear_interrupt(void __iomem *base)
+{
+ u32 val = readl_relaxed(base + TIMER_INT);
+
+ val |= TIMER_INT_CLR;
+ writel_relaxed(val, base + TIMER_INT);
+}
+
+static int sprd_timer_set_next_event(unsigned long cycles,
+ struct clock_event_device *ce)
+{
+ struct timer_of *to = to_timer_of(ce);
+
+ sprd_timer_disable(timer_of_base(to));
+ sprd_timer_update_counter(timer_of_base(to), cycles);
+ sprd_timer_enable(timer_of_base(to), 0);
+
+ return 0;
+}
+
+static int sprd_timer_set_periodic(struct clock_event_device *ce)
+{
+ struct timer_of *to = to_timer_of(ce);
+
+ sprd_timer_disable(timer_of_base(to));
+ sprd_timer_update_counter(timer_of_base(to), timer_of_period(to));
+ sprd_timer_enable(timer_of_base(to), TIMER_CTL_PERIOD_MODE);
+
+ return 0;
+}
+
+static int sprd_timer_shutdown(struct clock_event_device *ce)
+{
+ struct timer_of *to = to_timer_of(ce);
+
+ sprd_timer_disable(timer_of_base(to));
+ return 0;
+}
+
+static irqreturn_t sprd_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *ce = (struct clock_event_device *)dev_id;
+ struct timer_of *to = to_timer_of(ce);
+
+ sprd_timer_clear_interrupt(timer_of_base(to));
+
+ if (clockevent_state_oneshot(ce))
+ sprd_timer_disable(timer_of_base(to));
+
+ ce->event_handler(ce);
+ return IRQ_HANDLED;
+}
+
+static struct timer_of to = {
+ .flags = TIMER_OF_IRQ | TIMER_OF_BASE,
+
+ .clkevt = {
+ .name = TIMER_NAME,
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_FEAT_ONESHOT,
+ .set_state_shutdown = sprd_timer_shutdown,
+ .set_state_periodic = sprd_timer_set_periodic,
+ .set_next_event = sprd_timer_set_next_event,
+ .cpumask = cpu_possible_mask,
+ },
+
+ .of_irq = {
+ .handler = sprd_timer_interrupt,
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
+ },
+};
+
+static int __init sprd_timer_init(struct device_node *np)
+{
+ int ret;
+ u32 freq;
+
+ ret = timer_of_init(np, &to);
+ if (ret)
+ return ret;
+
+ ret = of_property_read_u32(np, "clock-frequency", &freq);
+ if (ret) {
+ pr_err("failed to get clock frequency\n");
+ timer_of_cleanup(&to);
+ return ret;
+ }
+
+ to.of_clk.period = DIV_ROUND_UP(freq, HZ);
+
+ sprd_timer_enable_interrupt(timer_of_base(&to));
+ clockevents_config_and_register(&to.clkevt, freq, 1, UINT_MAX);
+
+ return 0;
+}
+
+TIMER_OF_DECLARE(sc9860_timer, "sprd,sc9860-timer", sprd_timer_init);
--
1.7.9.5
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^ permalink raw reply related
* [PATCH v3 1/2] dt-bindings: clocksource: Add Spreadtrum SC9860 timer
From: Baolin Wang @ 2017-12-08 5:03 UTC (permalink / raw)
To: daniel.lezcano, tglx, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, broonie, baolin.wang, baolin.wang
This patch adds documentation of device tree bindings for the timers
found on Spreadtrum SC9860 platform.
Signed-off-by: Baolin Wang <baolin.wang@spreadtrum.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes since v2:
- No updates.
Changes since v1:
- Add acked tag from Rob.
---
.../bindings/timer/spreadtrum,sprd-timer.txt | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt b/Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt
new file mode 100644
index 0000000..f9d5eb9
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt
@@ -0,0 +1,20 @@
+Spreadtrum timers
+
+The Spreadtrum SC9860 platform provides 3 general-purpose timers.
+These timers can support 32bit or 64bit counter, as well as supporting
+period mode or one-shot mode, and they are can be wakeup source
+during deep sleep.
+
+Required properties:
+- compatible: should be "sprd,sc9860-timer" for SC9860 platform.
+- reg: The register address of the timer device.
+- interrupts: Should contain the interrupt for the timer device.
+- clock-frequency: The frequency of the clock that drives the counter, in Hz.
+
+Example:
+ timer@40050000 {
+ compatible = "sprd,sc9860-timer";
+ reg = <0 0x40050000 0 0x20>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <32768>;
+ };
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 3/3] Bluetooth: hci_ll: Add optional nvmem BD address source
From: David Lechner @ 2017-12-08 2:57 UTC (permalink / raw)
To: devicetree, linux-bluetooth
Cc: David Lechner, Rob Herring, Mark Rutland, Marcel Holtmann,
Gustavo Padovan, Johan Hedberg, netdev, linux-kernel
In-Reply-To: <1512701860-8321-1-git-send-email-david@lechnology.com>
This adds an optional nvmem consumer to get a BD address from an external
source. The BD address is then set in the Bluetooth chip after the
firmware has been loaded.
This has been tested working with a TI CC2560A chip (in a LEGO MINDSTORMS
EV3).
Signed-off-by: David Lechner <david@lechnology.com>
---
v2 changes:
* Add support for HCI_QUIRK_INVALID_BDADDR when there is an error getting the
BD address from nvmem
* Rework error handling
* rename "mac-address" to "bd-address"
* use bdaddr_t, bacmp and other bluetooth helper functions
* use ll_set_bdaddr() from new, separate patch
drivers/bluetooth/hci_ll.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/drivers/bluetooth/hci_ll.c b/drivers/bluetooth/hci_ll.c
index b732004..f5fef2d 100644
--- a/drivers/bluetooth/hci_ll.c
+++ b/drivers/bluetooth/hci_ll.c
@@ -53,6 +53,7 @@
#include <net/bluetooth/bluetooth.h>
#include <net/bluetooth/hci_core.h>
#include <linux/gpio/consumer.h>
+#include <linux/nvmem-consumer.h>
#include "hci_uart.h"
@@ -90,6 +91,7 @@ struct ll_device {
struct serdev_device *serdev;
struct gpio_desc *enable_gpio;
struct clk *ext_clk;
+ bdaddr_t bdaddr;
};
struct ll_struct {
@@ -715,6 +717,19 @@ static int ll_setup(struct hci_uart *hu)
if (err)
return err;
+ /* Set BD address if one was specified at probe */
+ if (!bacmp(&lldev->bdaddr, BDADDR_NONE)) {
+ /*
+ * This means that there was an error getting the BD address
+ * during probe, so mark the device as having a bad address.
+ */
+ set_bit(HCI_QUIRK_INVALID_BDADDR, &hu->hdev->quirks);
+ } else if (bacmp(&lldev->bdaddr, BDADDR_ANY)) {
+ err = ll_set_bdaddr(hu->hdev, &lldev->bdaddr);
+ if (err)
+ set_bit(HCI_QUIRK_INVALID_BDADDR, &hu->hdev->quirks);
+ }
+
/* Operational speed if any */
if (hu->oper_speed)
speed = hu->oper_speed;
@@ -743,6 +758,7 @@ static int hci_ti_probe(struct serdev_device *serdev)
{
struct hci_uart *hu;
struct ll_device *lldev;
+ struct nvmem_cell *bdaddr_cell;
u32 max_speed = 3000000;
lldev = devm_kzalloc(&serdev->dev, sizeof(struct ll_device), GFP_KERNEL);
@@ -764,6 +780,45 @@ static int hci_ti_probe(struct serdev_device *serdev)
of_property_read_u32(serdev->dev.of_node, "max-speed", &max_speed);
hci_uart_set_speeds(hu, 115200, max_speed);
+ /* optional BD address from nvram */
+ bdaddr_cell = nvmem_cell_get(&serdev->dev, "bd-address");
+ if (IS_ERR(bdaddr_cell)) {
+ int err = PTR_ERR(bdaddr_cell);
+
+ if (err == -EPROBE_DEFER)
+ return err;
+
+ /*
+ * ENOENT means there is no matching nvmem cell and ENOSYS
+ * means that nvmem is not enabled in the kernel configuration.
+ */
+ if (err != -ENOENT && err != -ENOSYS) {
+ /*
+ * If there was some other error, give userspace a
+ * chance to fix the problem instead of failing to load
+ * the driver. Using BDADDR_NONE as a flag that is
+ * tested later in the setup function.
+ */
+ dev_warn(&serdev->dev,
+ "Failed to get \"bd-address\" nvmem cell (%d)\n",
+ err);
+ bacpy(&lldev->bdaddr, BDADDR_NONE);
+ }
+ } else {
+ bdaddr_t *bdaddr;
+ int len;
+
+ bdaddr = nvmem_cell_read(bdaddr_cell, &len);
+ if (len != sizeof(bdaddr_t)) {
+ dev_err(&serdev->dev, "Invalid nvmem bd-address length\n");
+ nvmem_cell_put(bdaddr_cell);
+ return -EINVAL;
+ }
+
+ baswap(&lldev->bdaddr, bdaddr);
+ nvmem_cell_put(bdaddr_cell);
+ }
+
return hci_uart_register_device(hu, &llp);
}
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/3] dt-bindings: Add optional nvmem BD address bindings to ti,wlink-st
From: David Lechner @ 2017-12-08 2:57 UTC (permalink / raw)
To: devicetree, linux-bluetooth
Cc: David Lechner, Rob Herring, Mark Rutland, Marcel Holtmann,
Gustavo Padovan, Johan Hedberg, netdev, linux-kernel
In-Reply-To: <1512701860-8321-1-git-send-email-david@lechnology.com>
This adds optional nvmem consumer properties to the ti,wlink-st device tree
bindings to allow specifying the BD address.
Signed-off-by: David Lechner <david@lechnology.com>
---
v2 changes:
* Renamed "mac-address" to "bd-address"
* Fixed typos in example
* Specify byte order of "bd-address"
Documentation/devicetree/bindings/net/ti,wilink-st.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ti,wilink-st.txt b/Documentation/devicetree/bindings/net/ti,wilink-st.txt
index 1649c1f..a45a508 100644
--- a/Documentation/devicetree/bindings/net/ti,wilink-st.txt
+++ b/Documentation/devicetree/bindings/net/ti,wilink-st.txt
@@ -32,6 +32,9 @@ Optional properties:
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entry:
"ext_clock" (External clock provided to the TI combo chip).
+ - nvmem-cells: phandle to nvmem data cell that contains a 6 byte BD address
+ with the most significant byte first (big-endian).
+ - nvmem-cell-names: "bd-address" (required when nvmem-cells is specified)
Example:
@@ -43,5 +46,7 @@ Example:
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
clocks = <&clk32k_wl18xx>;
clock-names = "ext_clock";
+ nvmem-cells = <&bd_address>;
+ nvmem-cell-names = "bd-address";
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 1/3] Bluetooth: hci_ll: add support for setting public address
From: David Lechner @ 2017-12-08 2:57 UTC (permalink / raw)
To: devicetree, linux-bluetooth
Cc: David Lechner, Rob Herring, Mark Rutland, Marcel Holtmann,
Gustavo Padovan, Johan Hedberg, netdev, linux-kernel
In-Reply-To: <1512701860-8321-1-git-send-email-david@lechnology.com>
This adds support for setting the public address on Texas Instruments
Bluetooth chips using a vendor-specific command.
This has been tested on a CC2560A. The TI wiki also indicates that this
command should work on TI WL17xx/WL18xx Bluetooth chips.
Signed-off-by: David Lechner <david@lechnology.com>
---
v2 changes:
* This is a new patch in v2
drivers/bluetooth/hci_ll.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/bluetooth/hci_ll.c b/drivers/bluetooth/hci_ll.c
index 974a788..b732004 100644
--- a/drivers/bluetooth/hci_ll.c
+++ b/drivers/bluetooth/hci_ll.c
@@ -57,6 +57,7 @@
#include "hci_uart.h"
/* Vendor-specific HCI commands */
+#define HCI_VS_WRITE_BD_ADDR 0xfc06
#define HCI_VS_UPDATE_UART_HCI_BAUDRATE 0xff36
/* HCILL commands */
@@ -662,6 +663,20 @@ static int download_firmware(struct ll_device *lldev)
return err;
}
+static int ll_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr)
+{
+ bdaddr_t bdaddr_swapped;
+ struct sk_buff *skb;
+
+ baswap(&bdaddr_swapped, bdaddr);
+ skb = __hci_cmd_sync(hdev, HCI_VS_WRITE_BD_ADDR, sizeof(bdaddr_t),
+ &bdaddr_swapped, HCI_INIT_TIMEOUT);
+ if (!IS_ERR(skb))
+ kfree_skb(skb);
+
+ return PTR_ERR_OR_ZERO(skb);
+}
+
static int ll_setup(struct hci_uart *hu)
{
int err, retry = 3;
@@ -674,6 +689,8 @@ static int ll_setup(struct hci_uart *hu)
lldev = serdev_device_get_drvdata(serdev);
+ hu->hdev->set_bdaddr = ll_set_bdaddr;
+
serdev_device_set_flow_control(serdev, true);
do {
--
2.7.4
^ permalink raw reply related
* [PATCH v2 0/3] Bluetooth: hci_ll: Get BD address from NVMEM (was "bluetooth: hci_ll: Get MAC address from NVMEM")
From: David Lechner @ 2017-12-08 2:57 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA
Cc: David Lechner, Rob Herring, Mark Rutland, Marcel Holtmann,
Gustavo Padovan, Johan Hedberg, netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
This series adds supporting getting the BD address from a NVMEM provider
for "LL" HCI controllers (Texas Instruments).
v2 changes:
* Fixed typos in dt-bindings
* Use "bd-address" instead of "mac-address"
* Updated dt-bindings to specify the byte order of "bd-address"
* New patch "Bluetooth: hci_ll: add support for setting public address"
* Dropped patch "Bluetooth: hci_ll: add constant for vendor-specific command"
that is already in bluetooth-next
* Rework error handling
* Use bdaddr_t, bacmp and other bluetooth utils
David Lechner (3):
Bluetooth: hci_ll: add support for setting public address
dt-bindings: Add optional nvmem BD address bindings to ti,wlink-st
Bluetooth: hci_ll: Add optional nvmem BD address source
.../devicetree/bindings/net/ti,wilink-st.txt | 5 ++
drivers/bluetooth/hci_ll.c | 71 ++++++++++++++++++++++
2 files changed, 76 insertions(+)
--
2.7.4
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