* [PATCH RESEND v6 2/2] dt-bindings: add eeprom "no-read-rollover" property
From: Sven Van Asbroeck @ 2017-12-08 15:37 UTC (permalink / raw)
To: svendev-fuHqz3Nb1YI, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, wsa-z923LK4zBo2bacvFa/9K2g,
brgl-ARrdPY/1zhM, nsekhar-l0cyMroinI0,
sakari.ailus-VuQAYsv1563Yd54FQh9/CA, david-nq/r/kbU++upp/zk7JDF2g,
javier-0uQlZySMnqxg9hUCZPvPmw,
divagar.mohandass-ral2JQCrhuEAvxtiuMwx3w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512747445-5817-1-git-send-email-svendev-fuHqz3Nb1YI@public.gmane.org>
Adds an optional property for at24 eeproms.
This parameterless property indicates that the multi-address eeprom
does not automatically roll over reads to the next slave address.
Signed-off-by: Sven Van Asbroeck <svendev-fuHqz3Nb1YI@public.gmane.org>
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/eeprom/eeprom.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/eeprom/eeprom.txt b/Documentation/devicetree/bindings/eeprom/eeprom.txt
index 27f2bc1..5bfc0ac 100644
--- a/Documentation/devicetree/bindings/eeprom/eeprom.txt
+++ b/Documentation/devicetree/bindings/eeprom/eeprom.txt
@@ -38,6 +38,11 @@ Optional properties:
- size: total eeprom size in bytes
+ - no-read-rollover:
+ This parameterless property indicates that the multi-address
+ eeprom does not automatically roll over reads to the next
+ slave address. Please consult the manual of your device.
+
Example:
eeprom@52 {
--
1.9.1
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^ permalink raw reply related
* [PATCH RESEND v6 1/2] at24: support eeproms that do not auto-rollover reads.
From: Sven Van Asbroeck @ 2017-12-08 15:37 UTC (permalink / raw)
To: svendev-fuHqz3Nb1YI, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, wsa-z923LK4zBo2bacvFa/9K2g,
brgl-ARrdPY/1zhM, nsekhar-l0cyMroinI0,
sakari.ailus-VuQAYsv1563Yd54FQh9/CA, david-nq/r/kbU++upp/zk7JDF2g,
javier-0uQlZySMnqxg9hUCZPvPmw,
divagar.mohandass-ral2JQCrhuEAvxtiuMwx3w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512747445-5817-1-git-send-email-svendev-fuHqz3Nb1YI@public.gmane.org>
Some multi-address eeproms in the at24 family may not automatically
roll-over reads to the next slave address. On those eeproms, reads
that straddle slave boundaries will not work correctly.
Solution:
Mark such eeproms with a flag that prevents reads straddling
slave boundaries. Add the AT24_FLAG_NO_RDROL flag to the eeprom
entry in the device_id table, or add 'no-read-rollover' to the
eeprom devicetree entry.
Note that I have not personally enountered an at24 chip that
does not support read rollovers. They may or may not exist.
However, my hardware requires this functionality because of
a quirk.
It's up to the Linux community to decide if this patch is useful/
general enough to warrant merging.
Signed-off-by: Sven Van Asbroeck <svendev-fuHqz3Nb1YI@public.gmane.org>
---
drivers/misc/eeprom/at24.c | 39 ++++++++++++++++++++++++++------------
include/linux/platform_data/at24.h | 2 ++
2 files changed, 29 insertions(+), 12 deletions(-)
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index 625b001..06ffa11 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -251,15 +251,6 @@ struct at24_data {
* Slave address and byte offset derive from the offset. Always
* set the byte address; on a multi-master board, another master
* may have changed the chip's "current" address pointer.
- *
- * REVISIT some multi-address chips don't rollover page reads to
- * the next slave address, so we may need to truncate the count.
- * Those chips might need another quirk flag.
- *
- * If the real hardware used four adjacent 24c02 chips and that
- * were misconfigured as one 24c08, that would be a similar effect:
- * one "eeprom" file not four, but larger reads would fail when
- * they crossed certain pages.
*/
static struct at24_client *at24_translate_offset(struct at24_data *at24,
unsigned int *offset)
@@ -277,6 +268,30 @@ static struct at24_client *at24_translate_offset(struct at24_data *at24,
return &at24->client[i];
}
+static size_t at24_adjust_read_count(struct at24_data *at24,
+ unsigned int offset, size_t count)
+{
+ unsigned int bits;
+ size_t remainder;
+
+ /*
+ * In case of multi-address chips that don't rollover reads to
+ * the next slave address: truncate the count to the slave boundary,
+ * so that the read never straddles slaves.
+ */
+ if (at24->chip.flags & AT24_FLAG_NO_RDROL) {
+ bits = (at24->chip.flags & AT24_FLAG_ADDR16) ? 16 : 8;
+ remainder = BIT(bits) - offset;
+ if (count > remainder)
+ count = remainder;
+ }
+
+ if (count > io_limit)
+ count = io_limit;
+
+ return count;
+}
+
static ssize_t at24_regmap_read(struct at24_data *at24, char *buf,
unsigned int offset, size_t count)
{
@@ -289,9 +304,7 @@ static ssize_t at24_regmap_read(struct at24_data *at24, char *buf,
at24_client = at24_translate_offset(at24, &offset);
regmap = at24_client->regmap;
client = at24_client->client;
-
- if (count > io_limit)
- count = io_limit;
+ count = at24_adjust_read_count(at24, offset, count);
/* adjust offset for mac and serial read ops */
offset += at24->offset_adj;
@@ -457,6 +470,8 @@ static void at24_get_pdata(struct device *dev, struct at24_platform_data *chip)
if (device_property_present(dev, "read-only"))
chip->flags |= AT24_FLAG_READONLY;
+ if (device_property_present(dev, "no-read-rollover"))
+ chip->flags |= AT24_FLAG_NO_RDROL;
err = device_property_read_u32(dev, "size", &val);
if (!err)
diff --git a/include/linux/platform_data/at24.h b/include/linux/platform_data/at24.h
index 271a4e2..841bb28 100644
--- a/include/linux/platform_data/at24.h
+++ b/include/linux/platform_data/at24.h
@@ -50,6 +50,8 @@ struct at24_platform_data {
#define AT24_FLAG_TAKE8ADDR BIT(4) /* take always 8 addresses (24c00) */
#define AT24_FLAG_SERIAL BIT(3) /* factory-programmed serial number */
#define AT24_FLAG_MAC BIT(2) /* factory-programmed mac address */
+#define AT24_FLAG_NO_RDROL BIT(1) /* does not auto-rollover reads to */
+ /* the next slave address */
void (*setup)(struct nvmem_device *nvmem, void *context);
void *context;
--
1.9.1
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^ permalink raw reply related
* [PATCH RESEND v6 0/2] at24: support eeproms that do not auto-rollover reads.
From: Sven Van Asbroeck @ 2017-12-08 15:37 UTC (permalink / raw)
To: svendev, robh+dt, mark.rutland, wsa, brgl, nsekhar, sakari.ailus,
david, javier, divagar.mohandass
Cc: devicetree, linux-kernel, linux-i2c
v6 resend:
added Reviewed-by: Rob Herring <robh@kernel.org>
v6:
added newlines, asked by Bartosz
no need for braces around ternary operator's condition:
bits = (at24->chip.flags & AT24_FLAG_ADDR16) ? 16 : 8;
but keep the braces anyway, as asked by Uwe Klein-Koenig
v5:
at Rob Herring's request, renamed devicetree property:
at24,no-read-rollover -> no-read-rollover
v4:
renamed devicetree property:
no-read-rollover -> at24,no-read-rollover
dt-bindings update now a separate patch
v3:
rebased against at24 maintainer's devel staging branch:
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git at24/devel
clarified some of the comments and wording
v2:
kbuild test robot feedback: correct
"warning: comparison of distinct pointer types lacks a cast"
build warning on some compilers / architectures.
v1:
original patch
Sven Van Asbroeck (2):
at24: support eeproms that do not auto-rollover reads.
dt-bindings: add eeprom "at24,no-read-rollover" property
.../devicetree/bindings/eeprom/eeprom.txt | 5 +++
drivers/misc/eeprom/at24.c | 37 +++++++++++++++-------
include/linux/platform_data/at24.h | 2 ++
3 files changed, 32 insertions(+), 12 deletions(-)
--
1.9.1
^ permalink raw reply
* Re: [PATCH v1 1/2] eeprom: at24: convert magic numbers to structs.
From: Bartosz Golaszewski @ 2017-12-08 15:32 UTC (permalink / raw)
To: Sven Van Asbroeck
Cc: Sven Van Asbroeck, Wolfram Sang, nsekhar-l0cyMroinI0,
Sakari Ailus, Javier Martinez Canillas, Divagar Mohandass,
devicetree-u79uwXL29TY76Z2rM5mHXA, Linux Kernel Mailing List,
linux-i2c
In-Reply-To: <CAGngYiWmnBgjufeEUW5LYA8Ci7Rwt2m=FLCDX3RjrdWrxY97aw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-12-08 16:25 GMT+01:00 Sven Van Asbroeck <thesven73-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>:
> Bartosz wrote:
>>
>> Just make it accept two parameters: the string and the data object
>> name. For example:
>>
>>
> AT24_OF_DEVICE_ID("atmel,24c01", 24c01);
>>
>
> I don't want to do too much bikeshedding,
> but one last comment.
>
> Is it a good idea to have duplicated information?
> Do you think the risk of a typo mismatch is acceptable? E.g.
> AT24_OF_DEVICE_ID("atmel,24c01", 24c0
> 2
> );
> At least the original syntax is not susceptible to this problem,
> but of course as you say, it hides the of_ compatible string:
> AT24_OF_DEVICE_ID(atmel, 24c01);
> /* hides 'atmel,24c01' */
>
> Pros and cons. Pick one.
Nah, there aren't like two thousand compatible chips so that a mistake
would go unnoticed.
Bartosz
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^ permalink raw reply
* Re: [PATCH v1 1/2] eeprom: at24: convert magic numbers to structs.
From: Sven Van Asbroeck @ 2017-12-08 15:28 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Sven Van Asbroeck, Wolfram Sang, nsekhar, Sakari Ailus,
Javier Martinez Canillas, Divagar Mohandass, devicetree,
Linux Kernel Mailing List, linux-i2c
In-Reply-To: <CAMRc=Mf6e=O_M40Vaq4jygBwPHB8-X6wyDVG8Ee7qw+PjLTXUA@mail.gmail.com>
Bartosz wrote:
> Just make it accept two parameters: the string and the data object
> name. For example:
>
> AT24_OF_DEVICE_ID("atmel,24c01", 24c01);
>
I don't want to do too much bikeshedding,
but one last comment.
Is it a good idea to have duplicated information?
Do you think the risk of a typo mismatch is acceptable? E.g.
AT24_OF_DEVICE_ID("atmel,24c01", 24c02);
At least the original syntax is not susceptible to this problem,
but of course as you say, it hides the of_ compatible string:
AT24_OF_DEVICE_ID(atmel, 24c01);
/* hides 'atmel,24c01' */
Pros and cons. Pick one.
^ permalink raw reply
* Re: [PATCH 0/2] of: overlay: Crash fix and improvement
From: Geert Uytterhoeven @ 2017-12-08 15:24 UTC (permalink / raw)
To: Rob Herring
Cc: Geert Uytterhoeven, Pantelis Antoniou, Frank Rowand,
devicetree@vger.kernel.org, Linux-Renesas,
linux-kernel@vger.kernel.org
In-Reply-To: <20171208151114.ly7sqymznmeme4w4@rob-hp-laptop>
Hi Rob,
On Fri, Dec 8, 2017 at 4:11 PM, Rob Herring <robh@kernel.org> wrote:
> On Fri, Dec 08, 2017 at 02:13:01PM +0100, Geert Uytterhoeven wrote:
>> This patch series fixes memory corruption when applying overlays.
>>
>> I first noticed this when using OF configfs. After lots of failed
>> debugging attempts, I bisected it to "of: overlay: add per overlay sysfs
>> attributes", which is not upstream. But that was a red herring: that
>> commit enlarged struct fragment to exactly 64-bytes, which just made it
>> more likely to cause random corruption when writing beyond the end of an
>> array of fragment structures. With the smaller structure size before,
>> such writes usually ended up in the unused holes between allocated
>> blocks, causing no harm.
>>
>> The first patch is the real fix, and applies to both v4.15-rc2 and Rob's
>> for-next branch.
>> The second patch is a small improvement, and applies to Rob's for-next
>> branch only.
>>
>> I've updated my topic/overlays and topic/renesas-overlays branches at
>> git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
>> accordingly.
>>
>> Thanks!
>>
>> Geert Uytterhoeven (2):
>> of: overlay: Fix out-of-bounds write in init_overlay_changeset()
>> of: overlay: Make node skipping in init_overlay_changeset() clearer
>
> I've applied both and am updating my pull req to Linus. I hope that's
> the end of it. If further fixes can't be reproduced with mainline, I'm
> not going to be inclined to take them for 4.15.
Tahnks!
BTW, seems I accidentally used "--" instead of "---" as a separator, so the
commit message
https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git/commit/?h=dt/linus&id=efb72067c287cd6aba8eb434bd5bdc1ae0af6ed7
contains a few more lines than intended.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCHv2 18/20] ARM: dts: am43xx: add clkctrl nodes
From: Tero Kristo @ 2017-12-08 15:17 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512746251-20123-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add clkctrl nodes for AM43xx SoC. These are going to be acting as
replacement for part of the existing clock data and the existing
clkctrl hooks under hwmod data.
This patch also removes any obsolete clock nodes, and reroutes all users
for these to use the new clkctrl clocks instead.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am4372.dtsi | 7 +-
arch/arm/boot/dts/am43x-epos-evm.dts | 2 +-
arch/arm/boot/dts/am43xx-clocks.dtsi | 230 +++++++++++------------------------
3 files changed, 75 insertions(+), 164 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index bf4e58e..39a5bd7 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/am4.h>
/ {
compatible = "ti,am4372", "ti,am43";
@@ -998,7 +999,7 @@
reg = <0x483a8000 0x8000>;
syscon-phy-power = <&scm_conf 0x620>;
clocks = <&usb_phy0_always_on_clk32k>,
- <&usb_otg_ss0_refclk960m>;
+ <&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
@@ -1017,7 +1018,7 @@
reg = <0x483e8000 0x8000>;
syscon-phy-power = <&scm_conf 0x628>;
clocks = <&usb_phy1_always_on_clk32k>,
- <&usb_otg_ss1_refclk960m>;
+ <&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
@@ -1180,4 +1181,4 @@
};
};
-/include/ "am43xx-clocks.dtsi"
+#include "am43xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index a04d79e..d3363fb 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -985,7 +985,7 @@
rx-num-evt = <32>;
};
-&synctimer_32kclk {
+&mux_synctimer32k_ck {
assigned-clocks = <&mux_synctimer32k_ck>;
assigned-clock-parents = <&clkdiv32k_ick>;
};
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 430be58..a7037a4 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -524,54 +524,6 @@
reg = <0x4240>;
};
- gpio0_dbclk: gpio0_dbclk@2b68 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&gpio0_dbclk_mux_ck>;
- ti,bit-shift = <8>;
- reg = <0x2b68>;
- };
-
- gpio1_dbclk: gpio1_dbclk@8c78 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <8>;
- reg = <0x8c78>;
- };
-
- gpio2_dbclk: gpio2_dbclk@8c80 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <8>;
- reg = <0x8c80>;
- };
-
- gpio3_dbclk: gpio3_dbclk@8c88 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <8>;
- reg = <0x8c88>;
- };
-
- gpio4_dbclk: gpio4_dbclk@8c90 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <8>;
- reg = <0x8c90>;
- };
-
- gpio5_dbclk: gpio5_dbclk@8c98 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <8>;
- reg = <0x8c98>;
- };
-
mmc_clk: mmc_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -629,14 +581,6 @@
reg = <0x4230>;
};
- synctimer_32kclk: synctimer_32kclk@2a30 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&mux_synctimer32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x2a30>;
- };
-
timer8_fck: timer8_fck@421c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -763,110 +707,76 @@
ti,bit-shift = <8>;
reg = <0x2a48>;
};
+};
- usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_per_clkdcoldo>;
- ti,bit-shift = <8>;
- reg = <0x8a60>;
- };
-
- usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_per_clkdcoldo>;
- ti,bit-shift = <8>;
- reg = <0x8a68>;
- };
-
- clkout1_osc_div_ck: clkout1_osc_div_ck {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&sys_clkin_ck>;
- ti,bit-shift = <20>;
- ti,max-div = <4>;
- reg = <0x4100>;
- };
-
- clkout1_src2_mux_ck: clkout1_src2_mux_ck {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
- <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
- <&dpll_mpu_m2_ck>;
- reg = <0x4100>;
- };
-
- clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&clkout1_src2_mux_ck>;
- ti,bit-shift = <4>;
- ti,max-div = <8>;
- reg = <0x4100>;
- };
-
- clkout1_src2_post_div_ck: clkout1_src2_post_div_ck {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&clkout1_src2_pre_div_ck>;
- ti,bit-shift = <8>;
- ti,max-div = <32>;
- ti,index-power-of-two;
- reg = <0x4100>;
- };
-
- clkout1_mux_ck: clkout1_mux_ck {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
- <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
- ti,bit-shift = <16>;
- reg = <0x4100>;
- };
-
- clkout1_ck: clkout1_ck {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkout1_mux_ck>;
- ti,bit-shift = <23>;
- reg = <0x4100>;
- };
-
- clkout2_src_mux_ck: clkout2_src_mux_ck {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
- <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
- <&dpll_mpu_m2_ck>, <&dpll_extdev_ck>;
- reg = <0x4108>;
- };
-
- clkout2_pre_div_ck: clkout2_pre_div_ck {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&clkout2_src_mux_ck>;
- ti,bit-shift = <4>;
- ti,max-div = <8>;
- reg = <0x4108>;
- };
-
- clkout2_post_div_ck: clkout2_post_div_ck {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&clkout2_pre_div_ck>;
- ti,bit-shift = <8>;
- ti,max-div = <32>;
- ti,index-power-of-two;
- reg = <0x4108>;
- };
-
- clkout2_ck: clkout2_ck {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkout2_post_div_ck>;
- ti,bit-shift = <16>;
- reg = <0x4108>;
+&prcm {
+ l4_wkup_cm: l4_wkup_cm@2800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x2800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2800 0x400>;
+
+ l4_wkup_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x34c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ mpu_cm: mpu_cm@8300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x8300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x8300 0x100>;
+
+ mpu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ gfx_l3_cm: gfx_l3_cm@8400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x8400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x8400 0x100>;
+
+ gfx_l3_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_rtc_cm: l4_rtc_cm@8500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x8500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x8500 0x100>;
+
+ l4_rtc_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_per_cm: l4_per_cm@8800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x8800 0xc00>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x8800 0xc00>;
+
+ l4_per_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xb04>;
+ #clock-cells = <2>;
+ };
};
};
--
1.9.1
--
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* [PATCHv2 17/20] ARM: dts: am33xx: add clkctrl nodes
From: Tero Kristo @ 2017-12-08 15:17 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512746251-20123-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add clkctrl nodes for AM33xx SoC. These are going to be acting as
replacement for part of the existing clock data and the existing
clkctrl hooks under hwmod data.
This patch also removes any obsolete clock nodes, and reroutes all users
for these to use the new clkctrl clocks instead.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am335x-bone-common.dtsi | 2 +-
arch/arm/boot/dts/am335x-boneblue.dts | 2 +-
arch/arm/boot/dts/am335x-evm.dts | 2 +-
arch/arm/boot/dts/am335x-evmsk.dts | 2 +-
arch/arm/boot/dts/am33xx-clocks.dtsi | 205 ++++++++++++++----------------
arch/arm/boot/dts/am33xx.dtsi | 5 +-
6 files changed, 99 insertions(+), 119 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 48a15fc..e67b4d6 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -409,6 +409,6 @@
};
&rtc {
- clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts
index cdc1b2b..d5be9fc 100644
--- a/arch/arm/boot/dts/am335x-boneblue.dts
+++ b/arch/arm/boot/dts/am335x-boneblue.dts
@@ -446,7 +446,7 @@
&rtc {
system-power-controller;
- clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index ddd8975..fee6b3e 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -790,6 +790,6 @@
};
&rtc {
- clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 9ba4b18..fa608cd 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -722,6 +722,6 @@
};
&rtc {
- clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 8d83195..95d5c9d 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -292,14 +292,6 @@
clock-div = <4>;
};
- cefuse_fck: cefuse_fck@a20 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_clkin_ck>;
- ti,bit-shift = <1>;
- reg = <0x0a20>;
- };
-
clk_24mhz: clk_24mhz {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -316,14 +308,6 @@
clock-div = <732>;
};
- clkdiv32k_ick: clkdiv32k_ick@14c {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ck>;
- ti,bit-shift = <1>;
- reg = <0x014c>;
- };
-
l3_gclk: l3_gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -350,49 +334,49 @@
timer1_fck: timer1_fck@528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+ clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
timer2_fck: timer2_fck@508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0508>;
};
timer3_fck: timer3_fck@50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x050c>;
};
timer4_fck: timer4_fck@510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0510>;
};
timer5_fck: timer5_fck@518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0518>;
};
timer6_fck: timer6_fck@51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x051c>;
};
timer7_fck: timer7_fck@504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0504>;
};
@@ -423,7 +407,7 @@
wdt1_fck: wdt1_fck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+ clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0538>;
};
@@ -493,42 +477,10 @@
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x053c>;
};
- gpio0_dbclk: gpio0_dbclk@408 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&gpio0_dbclk_mux_ck>;
- ti,bit-shift = <18>;
- reg = <0x0408>;
- };
-
- gpio1_dbclk: gpio1_dbclk@ac {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <18>;
- reg = <0x00ac>;
- };
-
- gpio2_dbclk: gpio2_dbclk@b0 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <18>;
- reg = <0x00b0>;
- };
-
- gpio3_dbclk: gpio3_dbclk@b4 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <18>;
- reg = <0x00b4>;
- };
-
lcd_gclk: lcd_gclk@534 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -577,58 +529,6 @@
reg = <0x0700>;
};
- dbg_sysclk_ck: dbg_sysclk_ck@414 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_clkin_ck>;
- ti,bit-shift = <19>;
- reg = <0x0414>;
- };
-
- dbg_clka_ck: dbg_clka_ck@414 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_core_m4_ck>;
- ti,bit-shift = <30>;
- reg = <0x0414>;
- };
-
- stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@414 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
- ti,bit-shift = <22>;
- reg = <0x0414>;
- };
-
- trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@414 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
- ti,bit-shift = <20>;
- reg = <0x0414>;
- };
-
- stm_clk_div_ck: stm_clk_div_ck@414 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&stm_pmd_clock_mux_ck>;
- ti,bit-shift = <27>;
- ti,max-div = <64>;
- reg = <0x0414>;
- ti,index-power-of-two;
- };
-
- trace_clk_div_ck: trace_clk_div_ck@414 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&trace_pmd_clk_mux_ck>;
- ti,bit-shift = <24>;
- ti,max-div = <64>;
- reg = <0x0414>;
- ti,index-power-of-two;
- };
-
clkout2_ck: clkout2_ck@700 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -638,9 +538,88 @@
};
};
-&prcm_clockdomains {
- clk_24mhz_clkdm: clk_24mhz_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&clkdiv32k_ick>;
+&prcm {
+ l4_per_cm: l4_per_cm@0 {
+ compatible = "ti,omap4-cm";
+ reg = <0x0 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x200>;
+
+ l4_per_clkctrl: clk@14 {
+ compatible = "ti,clkctrl";
+ reg = <0x14 0x13c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_wkup_cm: l4_wkup_cm@400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x400 0x100>;
+
+ l4_wkup_clkctrl: clk@4 {
+ compatible = "ti,clkctrl";
+ reg = <0x4 0xd4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ mpu_cm: mpu_cm@600 {
+ compatible = "ti,omap4-cm";
+ reg = <0x600 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x600 0x100>;
+
+ mpu_clkctrl: clk@4 {
+ compatible = "ti,clkctrl";
+ reg = <0x4 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_rtc_cm: l4_rtc_cm@800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x800 0x100>;
+
+ l4_rtc_clkctrl: clk@0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ gfx_l3_cm: gfx_l3_cm@900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x900 0x100>;
+
+ gfx_l3_clkctrl: clk@4 {
+ compatible = "ti,clkctrl";
+ reg = <0x4 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_cefuse_cm: l4_cefuse_cm@a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xa00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa00 0x100>;
+
+ l4_cefuse_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
};
};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bd10ba7..d1690bc 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
+#include <dt-bindings/clock/am3.h>
/ {
compatible = "ti,am33xx";
@@ -578,7 +579,7 @@
interrupts = <75
76>;
ti,hwmods = "rtc";
- clocks = <&clkdiv32k_ick>;
+ clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "int-clk";
};
@@ -1019,4 +1020,4 @@
};
};
-/include/ "am33xx-clocks.dtsi"
+#include "am33xx-clocks.dtsi"
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related
* [PATCHv2 16/20] ARM: dts: dra7: add clkctrl nodes
From: Tero Kristo @ 2017-12-08 15:17 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512746251-20123-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add clkctrl nodes for DRA7 SoC. These are going to be acting as
replacement for part of the existing clock data and the existing
clkctrl hooks under hwmod data.
This patch also removes any obsolete clock nodes, and reroutes all users
for these to use the new clkctrl clocks instead.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 2 +-
arch/arm/boot/dts/dra7-evm-common.dtsi | 4 +-
arch/arm/boot/dts/dra7.dtsi | 68 +-
arch/arm/boot/dts/dra72-evm-common.dtsi | 4 +-
arch/arm/boot/dts/dra72x.dtsi | 4 +-
arch/arm/boot/dts/dra74x.dtsi | 6 +-
arch/arm/boot/dts/dra7xx-clocks.dtsi | 909 ++++++------------------
7 files changed, 261 insertions(+), 736 deletions(-)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index 49aeecd..74d1d0d 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -554,7 +554,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
- assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&sys_clkin2>;
status = "okay";
diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi
index e088bb9..05a7b1a 100644
--- a/arch/arm/boot/dts/dra7-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra7-evm-common.dtsi
@@ -204,7 +204,7 @@
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
- <&atl_gfclk_mux>,
+ <&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
@@ -222,7 +222,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
- assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5e24cea..a1d7178 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/dra.h>
+#include <dt-bindings/clock/dra7.h>
#define MAX_SOURCES 400
@@ -887,7 +888,7 @@
ti,hwmods = "timer1";
ti,timer-alwon;
clock-names = "fck";
- clocks = <&timer1_gfclk_mux>;
+ clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
};
timer2: timer@48032000 {
@@ -1370,7 +1371,7 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
- clocks = <&qspi_gfclk_div>;
+ clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>;
clock-names = "fck";
num-cs = <4>;
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
@@ -1392,7 +1393,8 @@
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
syscon-phy-power = <&scm_conf 0x374>;
- clocks = <&sys_clkin1>, <&sata_ref_clk>;
+ clocks = <&sys_clkin1>,
+ <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
clock-names = "sysclk", "refclk";
syscon-pllreset = <&scm_conf 0x3fc>;
#phy-cells = <0>;
@@ -1407,9 +1409,9 @@
syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
- <&optfclk_pciephy1_32khz>,
- <&optfclk_pciephy1_clk>,
- <&optfclk_pciephy1_div_clk>,
+ <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>,
+ <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>,
+ <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>,
<&optfclk_pciephy_div>,
<&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
@@ -1427,9 +1429,9 @@
syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
- <&optfclk_pciephy2_32khz>,
- <&optfclk_pciephy2_clk>,
- <&optfclk_pciephy2_div_clk>,
+ <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>,
+ <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>,
+ <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>,
<&optfclk_pciephy_div>,
<&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
@@ -1446,7 +1448,7 @@
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>;
phy-names = "sata-phy";
- clocks = <&sata_ref_clk>;
+ clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
ti,hwmods = "sata";
ports-implemented = <0x1>;
};
@@ -1474,7 +1476,7 @@
reg = <0x4a084000 0x400>;
syscon-phy-power = <&scm_conf 0x300>;
clocks = <&usb_phy1_always_on_clk32k>,
- <&usb_otg_ss1_refclk960m>;
+ <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk",
"refclk";
#phy-cells = <0>;
@@ -1486,7 +1488,7 @@
reg = <0x4a085000 0x400>;
syscon-phy-power = <&scm_conf 0xe74>;
clocks = <&usb_phy2_always_on_clk32k>,
- <&usb_otg_ss2_refclk960m>;
+ <&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>;
clock-names = "wkupclk",
"refclk";
#phy-cells = <0>;
@@ -1501,7 +1503,7 @@
syscon-phy-power = <&scm_conf 0x370>;
clocks = <&usb_phy3_always_on_clk32k>,
<&sys_clkin1>,
- <&usb_otg_ss1_refclk960m>;
+ <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk",
"sysclk",
"refclk";
@@ -1648,7 +1650,7 @@
ti,hwmods = "atl";
ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
- clocks = <&atl_gfclk_mux>;
+ clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
clock-names = "fck";
status = "disabled";
};
@@ -1664,8 +1666,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
- <&mcasp1_ahclkr_mux>;
+ clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>,
+ <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled";
};
@@ -1681,8 +1683,9 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
- <&mcasp2_ahclkr_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>,
+ <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled";
};
@@ -1698,7 +1701,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@@ -1714,7 +1718,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@@ -1730,7 +1735,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@@ -1746,7 +1752,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@@ -1762,7 +1769,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@@ -1778,7 +1786,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@@ -1800,7 +1809,7 @@
mac: ethernet@48484000 {
compatible = "ti,dra7-cpsw","ti,cpsw";
ti,hwmods = "gmac";
- clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
+ clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
@@ -1870,7 +1879,7 @@
reg = <0x4ae3c000 0x2000>;
syscon-raminit = <&scm_conf 0x558 0>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dcan1_sys_clk_mux>;
+ clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>;
status = "disabled";
};
@@ -1901,7 +1910,7 @@
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
- clocks = <&dss_dss_clk>;
+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
/* CTRL_CORE_SMA_SW_1 */
syscon-pol = <&scm_conf 0x534>;
@@ -1917,7 +1926,8 @@
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_hdmi";
- clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
};
@@ -2101,4 +2111,4 @@
temperature = <120000>; /* milli Celsius */
};
-/include/ "dra7xx-clocks.dtsi"
+#include "dra7xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 2e485a1..e85f560 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -514,7 +514,7 @@
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
- <&atl_gfclk_mux>,
+ <&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
@@ -532,7 +532,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
- assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index 6710760..a06d399 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -25,8 +25,8 @@
<0x58004300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1";
- clocks = <&dss_dss_clk>,
- <&dss_video1_clk>;
+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>;
clock-names = "fck", "video1_clk";
};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 24e6746..24ff17b 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -93,9 +93,9 @@
reg-names = "dss", "pll1_clkctrl", "pll1",
"pll2_clkctrl", "pll2";
- clocks = <&dss_dss_clk>,
- <&dss_video1_clk>,
- <&dss_video2_clk>;
+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>,
+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 13>;
clock-names = "fck", "video1_clk", "video2_clk";
};
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e62b628..69562cd 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -11,25 +11,25 @@
atl_clkin0_ck: atl_clkin0_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
- clocks = <&atl_gfclk_mux>;
+ clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
};
atl_clkin1_ck: atl_clkin1_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
- clocks = <&atl_gfclk_mux>;
+ clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
};
atl_clkin2_ck: atl_clkin2_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
- clocks = <&atl_gfclk_mux>;
+ clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
};
atl_clkin3_ck: atl_clkin3_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
- clocks = <&atl_gfclk_mux>;
+ clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
};
hdmi_clkin_ck: hdmi_clkin_ck {
@@ -809,70 +809,6 @@
assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
- mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <28>;
- reg = <0x0550>;
- };
-
- mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x0550>;
- };
-
- mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x0550>;
- };
-
- timer5_gfclk_mux: timer5_gfclk_mux@558 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
- ti,bit-shift = <24>;
- reg = <0x0558>;
- };
-
- timer6_gfclk_mux: timer6_gfclk_mux@560 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
- ti,bit-shift = <24>;
- reg = <0x0560>;
- };
-
- timer7_gfclk_mux: timer7_gfclk_mux@568 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
- ti,bit-shift = <24>;
- reg = <0x0568>;
- };
-
- timer8_gfclk_mux: timer8_gfclk_mux@570 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
- ti,bit-shift = <24>;
- reg = <0x0570>;
- };
-
- uart6_gfclk_mux: uart6_gfclk_mux@580 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x0580>;
- };
-
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -1188,39 +1124,8 @@
clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
-
- gpio1_dbclk: gpio1_dbclk@1838 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1838>;
- };
-
- dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin1>, <&sys_clkin2>;
- ti,bit-shift = <24>;
- reg = <0x1888>;
- };
-
- timer1_gfclk_mux: timer1_gfclk_mux@1840 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1840>;
- };
-
- uart10_gfclk_mux: uart10_gfclk_mux@1880 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1880>;
- };
};
+
&cm_core_clocks {
dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
#clock-cells = <0>;
@@ -1255,22 +1160,6 @@
reg = <0x021c>, <0x0220>;
};
- optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- #clock-cells = <0>;
- reg = <0x13b0>;
- ti,bit-shift = <8>;
- };
-
- optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- #clock-cells = <0>;
- reg = <0x13b8>;
- ti,bit-shift = <8>;
- };
-
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
@@ -1281,38 +1170,6 @@
ti,max-div = <2>;
};
- optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
- compatible = "ti,gate-clock";
- clocks = <&apll_pcie_ck>;
- #clock-cells = <0>;
- reg = <0x13b0>;
- ti,bit-shift = <9>;
- };
-
- optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
- compatible = "ti,gate-clock";
- clocks = <&apll_pcie_ck>;
- #clock-cells = <0>;
- reg = <0x13b8>;
- ti,bit-shift = <9>;
- };
-
- optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
- compatible = "ti,gate-clock";
- clocks = <&optfclk_pciephy_div>;
- #clock-cells = <0>;
- reg = <0x13b0>;
- ti,bit-shift = <10>;
- };
-
- optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
- compatible = "ti,gate-clock";
- clocks = <&optfclk_pciephy_div>;
- #clock-cells = <0>;
- reg = <0x13b8>;
- ti,bit-shift = <10>;
- };
-
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -1541,167 +1398,6 @@
reg = <0x06c0>;
};
- dss_32khz_clk: dss_32khz_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <11>;
- reg = <0x1120>;
- };
-
- dss_48mhz_clk: dss_48mhz_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_48m_fclk>;
- ti,bit-shift = <9>;
- reg = <0x1120>;
- };
-
- dss_dss_clk: dss_dss_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_per_h12x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x1120>;
- ti,set-rate-parent;
- };
-
- dss_hdmi_clk: dss_hdmi_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&hdmi_dpll_clk_mux>;
- ti,bit-shift = <10>;
- reg = <0x1120>;
- };
-
- dss_video1_clk: dss_video1_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&video1_dpll_clk_mux>;
- ti,bit-shift = <12>;
- reg = <0x1120>;
- };
-
- dss_video2_clk: dss_video2_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&video2_dpll_clk_mux>;
- ti,bit-shift = <13>;
- reg = <0x1120>;
- };
-
- gpio2_dbclk: gpio2_dbclk@1760 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1760>;
- };
-
- gpio3_dbclk: gpio3_dbclk@1768 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1768>;
- };
-
- gpio4_dbclk: gpio4_dbclk@1770 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1770>;
- };
-
- gpio5_dbclk: gpio5_dbclk@1778 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1778>;
- };
-
- gpio6_dbclk: gpio6_dbclk@1780 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1780>;
- };
-
- gpio7_dbclk: gpio7_dbclk@1810 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1810>;
- };
-
- gpio8_dbclk: gpio8_dbclk@1818 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1818>;
- };
-
- mmc1_clk32k: mmc1_clk32k@1328 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1328>;
- };
-
- mmc2_clk32k: mmc2_clk32k@1330 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1330>;
- };
-
- mmc3_clk32k: mmc3_clk32k@1820 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1820>;
- };
-
- mmc4_clk32k: mmc4_clk32k@1828 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1828>;
- };
-
- sata_ref_clk: sata_ref_clk@1388 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_clkin1>;
- ti,bit-shift = <8>;
- reg = <0x1388>;
- };
-
- usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_960m_gfclk>;
- ti,bit-shift = <8>;
- reg = <0x13f0>;
- };
-
- usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_960m_gfclk>;
- ti,bit-shift = <8>;
- reg = <0x1340>;
- };
-
usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1726,38 +1422,6 @@
reg = <0x0698>;
};
- atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
- ti,bit-shift = <24>;
- reg = <0x0c00>;
- };
-
- atl_gfclk_mux: atl_gfclk_mux@c00 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
- ti,bit-shift = <26>;
- reg = <0x0c00>;
- };
-
- rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
- ti,bit-shift = <24>;
- reg = <0x13d0>;
- };
-
- gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
- ti,bit-shift = <25>;
- reg = <0x13d0>;
- };
-
gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1787,362 +1451,6 @@
ti,dividers = <8>, <16>, <32>;
};
- mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <28>;
- reg = <0x1860>;
- };
-
- mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x1860>;
- };
-
- mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x1860>;
- };
-
- mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x1868>;
- assigned-clocks = <&mcasp3_ahclkx_mux>;
- assigned-clock-parents = <&abe_24m_fclk>;
- };
-
- mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x1868>;
- };
-
- mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x1898>;
- };
-
- mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x1898>;
- };
-
- mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x1878>;
- };
-
- mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x1878>;
- };
-
- mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x1904>;
- };
-
- mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x1904>;
- };
-
- mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x1908>;
- };
-
- mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x1908>;
- };
-
- mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <22>;
- reg = <0x1890>;
- };
-
- mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <24>;
- reg = <0x1890>;
- };
-
- mmc1_fclk_mux: mmc1_fclk_mux@1328 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1328>;
- };
-
- mmc1_fclk_div: mmc1_fclk_div@1328 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mmc1_fclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <4>;
- reg = <0x1328>;
- ti,index-power-of-two;
- };
-
- mmc2_fclk_mux: mmc2_fclk_mux@1330 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1330>;
- };
-
- mmc2_fclk_div: mmc2_fclk_div@1330 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mmc2_fclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <4>;
- reg = <0x1330>;
- ti,index-power-of-two;
- };
-
- mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1820>;
- };
-
- mmc3_gfclk_div: mmc3_gfclk_div@1820 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mmc3_gfclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <4>;
- reg = <0x1820>;
- ti,index-power-of-two;
- };
-
- mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1828>;
- };
-
- mmc4_gfclk_div: mmc4_gfclk_div@1828 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mmc4_gfclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <4>;
- reg = <0x1828>;
- ti,index-power-of-two;
- };
-
- qspi_gfclk_mux: qspi_gfclk_mux@1838 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1838>;
- };
-
- qspi_gfclk_div: qspi_gfclk_div@1838 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&qspi_gfclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <4>;
- reg = <0x1838>;
- ti,index-power-of-two;
- };
-
- timer10_gfclk_mux: timer10_gfclk_mux@1728 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1728>;
- };
-
- timer11_gfclk_mux: timer11_gfclk_mux@1730 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1730>;
- };
-
- timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x17c8>;
- };
-
- timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x17d0>;
- };
-
- timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x17d8>;
- };
-
- timer16_gfclk_mux: timer16_gfclk_mux@1830 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1830>;
- };
-
- timer2_gfclk_mux: timer2_gfclk_mux@1738 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1738>;
- };
-
- timer3_gfclk_mux: timer3_gfclk_mux@1740 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1740>;
- };
-
- timer4_gfclk_mux: timer4_gfclk_mux@1748 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1748>;
- };
-
- timer9_gfclk_mux: timer9_gfclk_mux@1750 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1750>;
- };
-
- uart1_gfclk_mux: uart1_gfclk_mux@1840 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1840>;
- };
-
- uart2_gfclk_mux: uart2_gfclk_mux@1848 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1848>;
- };
-
- uart3_gfclk_mux: uart3_gfclk_mux@1850 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1850>;
- };
-
- uart4_gfclk_mux: uart4_gfclk_mux@1858 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1858>;
- };
-
- uart5_gfclk_mux: uart5_gfclk_mux@1870 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1870>;
- };
-
- uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x18d0>;
- };
-
- uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x18e0>;
- };
-
- uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x18e8>;
- };
-
vip1_gclk_mux: vip1_gclk_mux@1020 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -2216,3 +1524,210 @@
reg = <0x6c4>;
};
};
+
+&cm_core_aon {
+ mpu_cm: mpu_cm@300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x300 0x100>;
+
+ mpu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ipu_cm: ipu_cm@500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x500 0x100>;
+
+ ipu_clkctrl: clk@40 {
+ compatible = "ti,clkctrl";
+ reg = <0x40 0x44>;
+ #clock-cells = <2>;
+ };
+ };
+
+ rtc_cm: rtc_cm@700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x700 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x700 0x100>;
+
+ rtc_clkctrl: clk@40 {
+ compatible = "ti,clkctrl";
+ reg = <0x40 0x8>;
+ #clock-cells = <2>;
+ };
+ };
+
+};
+
+&cm_core {
+ coreaon_cm: coreaon_cm@600 {
+ compatible = "ti,omap4-cm";
+ reg = <0x600 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x600 0x100>;
+
+ coreaon_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3main1_cm: l3main1_cm@700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x700 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x700 0x100>;
+
+ l3main1_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x74>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dma_cm: dma_cm@a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xa00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa00 0x100>;
+
+ dma_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ emif_cm: emif_cm@b00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xb00 0x100>;
+
+ emif_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ atl_cm: atl_cm@c00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xc00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xc00 0x100>;
+
+ atl_clkctrl: clk@0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4cfg_cm: l4cfg_cm@d00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xd00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xd00 0x100>;
+
+ l4cfg_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x84>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3instr_cm: l3instr_cm@e00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xe00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe00 0x100>;
+
+ l3instr_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dss_cm: dss_cm@1100 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1100 0x100>;
+
+ dss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3init_cm: l3init_cm@1300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1300 0x100>;
+
+ l3init_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xd4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4per_cm: l4per_cm@1700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1700 0x300>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1700 0x300>;
+
+ l4per_clkctrl: clk@0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0x20c>;
+ #clock-cells = <2>;
+
+ assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
+ assigned-clock-parents = <&abe_24m_fclk>;
+ };
+ };
+
+};
+
+&prm {
+ wkupaon_cm: wkupaon_cm@1800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1800 0x100>;
+
+ wkupaon_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x6c>;
+ #clock-cells = <2>;
+ };
+ };
+};
--
1.9.1
--
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^ permalink raw reply related
* [PATCHv2 15/20] ARM: dts: omap5: add clkctrl nodes
From: Tero Kristo @ 2017-12-08 15:17 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512746251-20123-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add clkctrl nodes for OMAP5 SoC. These are going to be acting as
replacement for part of the existing clock data and the existing
clkctrl hooks under hwmod data.
This patch also removes any obsolete clock nodes, and reroutes all users
for these to use the new clkctrl clocks instead.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/omap5.dtsi | 30 +-
arch/arm/boot/dts/omap54xx-clocks.dtsi | 623 +++++++++++----------------------
2 files changed, 222 insertions(+), 431 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index b0992b8..4bc5225 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
+#include <dt-bindings/clock/omap5.h>
/ {
#address-cells = <2>;
@@ -744,7 +745,7 @@
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
- clocks = <&timer1_gfclk_mux>;
+ clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
clock-names = "fck";
};
@@ -905,7 +906,8 @@
compatible = "ti,omap-usb2";
reg = <0x4a084000 0x7c>;
syscon-phy-power = <&scm_conf 0x300>;
- clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
+ clocks = <&usb_phy_cm_clk32k>,
+ <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
};
@@ -919,7 +921,7 @@
syscon-phy-power = <&scm_conf 0x370>;
clocks = <&usb_phy_cm_clk32k>,
<&sys_clkin>,
- <&usb_otg_ss_refclk960m>;
+ <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
clock-names = "wkupclk",
"sysclk",
"refclk";
@@ -987,7 +989,8 @@
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
syscon-phy-power = <&scm_conf 0x374>;
- clocks = <&sys_clkin>, <&sata_ref_clk>;
+ clocks = <&sys_clkin>,
+ <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
clock-names = "sysclk", "refclk";
#phy-cells = <0>;
};
@@ -999,7 +1002,7 @@
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>;
phy-names = "sata-phy";
- clocks = <&sata_ref_clk>;
+ clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
ti,hwmods = "sata";
ports-implemented = <0x1>;
};
@@ -1009,7 +1012,7 @@
reg = <0x58000000 0x80>;
status = "disabled";
ti,hwmods = "dss_core";
- clocks = <&dss_dss_clk>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
@@ -1020,7 +1023,7 @@
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
- clocks = <&dss_dss_clk>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
@@ -1029,7 +1032,7 @@
reg = <0x58002000 0x100>;
status = "disabled";
ti,hwmods = "dss_rfbi";
- clocks = <&dss_dss_clk>, <&l3_iclk_div>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
clock-names = "fck", "ick";
};
@@ -1042,7 +1045,8 @@
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_dsi1";
- clocks = <&dss_dss_clk>, <&dss_sys_clk>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
@@ -1055,7 +1059,8 @@
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_dsi2";
- clocks = <&dss_dss_clk>, <&dss_sys_clk>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
@@ -1069,7 +1074,8 @@
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_hdmi";
- clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma 76>;
dma-names = "audio_tx";
@@ -1143,7 +1149,7 @@
coefficients = <65 (-1791)>;
};
-/include/ "omap54xx-clocks.dtsi"
+#include "omap54xx-clocks.dtsi"
&gpu_thermal {
coefficients = <117 (-2992)>;
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 5291934..9619a74 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -432,22 +432,6 @@
reg = <0x0528>;
};
- dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
- ti,bit-shift = <26>;
- reg = <0x0538>;
- };
-
- dmic_gfclk: dmic_gfclk@538 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0538>;
- };
-
mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -464,86 +448,6 @@
reg = <0x0540>;
};
- mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
- ti,bit-shift = <26>;
- reg = <0x0548>;
- };
-
- mcbsp1_gfclk: mcbsp1_gfclk@548 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0548>;
- };
-
- mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
- ti,bit-shift = <26>;
- reg = <0x0550>;
- };
-
- mcbsp2_gfclk: mcbsp2_gfclk@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0550>;
- };
-
- mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
- ti,bit-shift = <26>;
- reg = <0x0558>;
- };
-
- mcbsp3_gfclk: mcbsp3_gfclk@558 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0558>;
- };
-
- timer5_gfclk_mux: timer5_gfclk_mux@568 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0568>;
- };
-
- timer6_gfclk_mux: timer6_gfclk_mux@570 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0570>;
- };
-
- timer7_gfclk_mux: timer7_gfclk_mux@578 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0578>;
- };
-
- timer8_gfclk_mux: timer8_gfclk_mux@580 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0580>;
- };
-
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -603,23 +507,8 @@
clock-mult = <1>;
clock-div = <1>;
};
-
- gpio1_dbclk: gpio1_dbclk@1938 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1938>;
- };
-
- timer1_gfclk_mux: timer1_gfclk_mux@1940 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1940>;
- };
};
+
&cm_core_clocks {
dpll_per_byp_mux: dpll_per_byp_mux@14c {
@@ -825,95 +714,6 @@
ti,dividers = <1>, <8>;
};
- dss_32khz_clk: dss_32khz_clk@1420 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <11>;
- reg = <0x1420>;
- };
-
- dss_48mhz_clk: dss_48mhz_clk@1420 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_48m_fclk>;
- ti,bit-shift = <9>;
- reg = <0x1420>;
- };
-
- dss_dss_clk: dss_dss_clk@1420 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_per_h12x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x1420>;
- ti,set-rate-parent;
- };
-
- dss_sys_clk: dss_sys_clk@1420 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dss_syc_gfclk_div>;
- ti,bit-shift = <10>;
- reg = <0x1420>;
- };
-
- gpio2_dbclk: gpio2_dbclk@1060 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1060>;
- };
-
- gpio3_dbclk: gpio3_dbclk@1068 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1068>;
- };
-
- gpio4_dbclk: gpio4_dbclk@1070 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1070>;
- };
-
- gpio5_dbclk: gpio5_dbclk@1078 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1078>;
- };
-
- gpio6_dbclk: gpio6_dbclk@1080 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1080>;
- };
-
- gpio7_dbclk: gpio7_dbclk@1110 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1110>;
- };
-
- gpio8_dbclk: gpio8_dbclk@1118 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1118>;
- };
-
iss_ctrlclk: iss_ctrlclk@1320 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -938,118 +738,6 @@
reg = <0x0f20>;
};
- mmc1_32khz_clk: mmc1_32khz_clk@1628 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1628>;
- };
-
- sata_ref_clk: sata_ref_clk@1688 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_clkin>;
- ti,bit-shift = <8>;
- reg = <0x1688>;
- };
-
- usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_usb_m2_ck>;
- ti,bit-shift = <13>;
- reg = <0x1658>;
- };
-
- usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_usb_m2_ck>;
- ti,bit-shift = <14>;
- reg = <0x1658>;
- };
-
- usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_usb_m2_ck>;
- ti,bit-shift = <7>;
- reg = <0x1658>;
- };
-
- usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <11>;
- reg = <0x1658>;
- };
-
- usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <12>;
- reg = <0x1658>;
- };
-
- usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <6>;
- reg = <0x1658>;
- };
-
- utmi_p1_gfclk: utmi_p1_gfclk@1658 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
- ti,bit-shift = <24>;
- reg = <0x1658>;
- };
-
- usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&utmi_p1_gfclk>;
- ti,bit-shift = <8>;
- reg = <0x1658>;
- };
-
- utmi_p2_gfclk: utmi_p2_gfclk@1658 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
- ti,bit-shift = <25>;
- reg = <0x1658>;
- };
-
- usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&utmi_p2_gfclk>;
- ti,bit-shift = <9>;
- reg = <0x1658>;
- };
-
- usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <10>;
- reg = <0x1658>;
- };
-
- usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@16f0 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_usb_clkdcoldo>;
- ti,bit-shift = <8>;
- reg = <0x16f0>;
- };
-
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1058,30 +746,6 @@
reg = <0x0640>;
};
- usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1668 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <8>;
- reg = <0x1668>;
- };
-
- usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1668 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <9>;
- reg = <0x1668>;
- };
-
- usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1668 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <10>;
- reg = <0x1668>;
- };
-
fdif_fclk: fdif_fclk@1328 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -1115,88 +779,6 @@
ti,max-div = <2>;
reg = <0x1638>;
};
-
- mmc1_fclk_mux: mmc1_fclk_mux@1628 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1628>;
- };
-
- mmc1_fclk: mmc1_fclk@1628 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mmc1_fclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <2>;
- reg = <0x1628>;
- };
-
- mmc2_fclk_mux: mmc2_fclk_mux@1630 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1630>;
- };
-
- mmc2_fclk: mmc2_fclk@1630 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mmc2_fclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <2>;
- reg = <0x1630>;
- };
-
- timer10_gfclk_mux: timer10_gfclk_mux@1028 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1028>;
- };
-
- timer11_gfclk_mux: timer11_gfclk_mux@1030 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1030>;
- };
-
- timer2_gfclk_mux: timer2_gfclk_mux@1038 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1038>;
- };
-
- timer3_gfclk_mux: timer3_gfclk_mux@1040 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1040>;
- };
-
- timer4_gfclk_mux: timer4_gfclk_mux@1048 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1048>;
- };
-
- timer9_gfclk_mux: timer9_gfclk_mux@1050 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1050>;
- };
};
&cm_core_clockdomains {
@@ -1394,3 +976,206 @@
reg = <0x021c>;
};
};
+
+&cm_core_aon {
+ mpu_cm: mpu_cm@300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x300 0x100>;
+
+ mpu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dsp_cm: dsp_cm@400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x400 0x100>;
+
+ dsp_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ abe_cm: abe_cm@500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x500 0x100>;
+
+ abe_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x64>;
+ #clock-cells = <2>;
+ };
+ };
+
+};
+
+&cm_core {
+ l3main1_cm: l3main1_cm@700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x700 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x700 0x100>;
+
+ l3main1_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3main2_cm: l3main2_cm@800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x800 0x100>;
+
+ l3main2_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ipu_cm: ipu_cm@900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x900 0x100>;
+
+ ipu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dma_cm: dma_cm@a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xa00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa00 0x100>;
+
+ dma_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ emif_cm: emif_cm@b00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xb00 0x100>;
+
+ emif_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4cfg_cm: l4cfg_cm@d00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xd00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xd00 0x100>;
+
+ l4cfg_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3instr_cm: l3instr_cm@e00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xe00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe00 0x100>;
+
+ l3instr_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4per_cm: l4per_cm@1000 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x200>;
+
+ l4per_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x15c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dss_cm: dss_cm@1400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1400 0x100>;
+
+ dss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3init_cm: l3init_cm@1600 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1600 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1600 0x100>;
+
+ l3init_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xd4>;
+ #clock-cells = <2>;
+ };
+ };
+};
+
+&prm {
+ wkupaon_cm: wkupaon_cm@1900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1900 0x100>;
+
+ wkupaon_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x5c>;
+ #clock-cells = <2>;
+ };
+ };
+};
--
1.9.1
--
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^ permalink raw reply related
* [PATCHv2 14/20] ARM: dts: omap4: add clkctrl nodes
From: Tero Kristo @ 2017-12-08 15:17 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512746251-20123-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
replacement for part of the existing clock data and the existing
clkctrl hooks under hwmod data.
This patch also removes any obsolete clock nodes, and reroutes all users
for these to use the new clkctrl clocks instead.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/omap4.dtsi | 24 +-
arch/arm/boot/dts/omap44xx-clocks.dtsi | 895 +++++++++++----------------------
2 files changed, 306 insertions(+), 613 deletions(-)
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 787ea2a..e912639 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
+#include <dt-bindings/clock/omap4.h>
/ {
compatible = "ti,omap4430", "ti,omap4";
@@ -683,7 +684,7 @@
reg-names = "sys", "gdd";
ti,hwmods = "hsi";
- clocks = <&hsi_fck>;
+ clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
clock-names = "hsi_fck";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
@@ -982,7 +983,7 @@
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
- clocks = <&dmt1_clk_mux>;
+ clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
clock-names = "fck";
};
@@ -1214,7 +1215,7 @@
reg = <0x58000000 0x80>;
status = "disabled";
ti,hwmods = "dss_core";
- clocks = <&dss_dss_clk>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
@@ -1225,7 +1226,7 @@
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
- clocks = <&dss_dss_clk>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
@@ -1234,7 +1235,7 @@
reg = <0x58002000 0x1000>;
status = "disabled";
ti,hwmods = "dss_rfbi";
- clocks = <&dss_dss_clk>, <&l3_div_ck>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
clock-names = "fck", "ick";
};
@@ -1243,7 +1244,7 @@
reg = <0x58003000 0x1000>;
status = "disabled";
ti,hwmods = "dss_venc";
- clocks = <&dss_tv_clk>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
clock-names = "fck";
};
@@ -1256,7 +1257,8 @@
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_dsi1";
- clocks = <&dss_dss_clk>, <&dss_sys_clk>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
@@ -1269,7 +1271,8 @@
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_dsi2";
- clocks = <&dss_dss_clk>, <&dss_sys_clk>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
@@ -1283,7 +1286,8 @@
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_hdmi";
- clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma 76>;
dma-names = "audio_tx";
@@ -1292,4 +1296,4 @@
};
};
-/include/ "omap44xx-clocks.dtsi"
+#include "omap44xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 05732ed..279ff2f 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -174,14 +174,6 @@
ti,index-power-of-two;
};
- aess_fclk: aess_fclk@528 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&abe_clk>;
- ti,bit-shift = <24>;
- ti,max-div = <2>;
- reg = <0x0528>;
- };
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
@@ -464,7 +456,7 @@
ocp_abe_iclk: ocp_abe_iclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
- clocks = <&aess_fclk>;
+ clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>;
ti,bit-shift = <24>;
reg = <0x0528>;
ti,dividers = <2>, <1>;
@@ -478,156 +470,13 @@
clock-div = <4>;
};
- dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
- ti,bit-shift = <25>;
- reg = <0x0538>;
- };
-
- func_dmic_abe_gfclk: func_dmic_abe_gfclk@538 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0538>;
- };
-
- mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
- ti,bit-shift = <25>;
- reg = <0x0540>;
- };
-
- func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0540>;
- };
-
- mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
- ti,bit-shift = <25>;
- reg = <0x0548>;
- };
-
- func_mcbsp1_gfclk: func_mcbsp1_gfclk@548 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0548>;
- };
-
- mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
- ti,bit-shift = <25>;
- reg = <0x0550>;
- };
-
- func_mcbsp2_gfclk: func_mcbsp2_gfclk@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0550>;
- };
-
- mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
- ti,bit-shift = <25>;
- reg = <0x0558>;
- };
-
- func_mcbsp3_gfclk: func_mcbsp3_gfclk@558 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0558>;
- };
-
- slimbus1_fclk_1: slimbus1_fclk_1@560 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_24m_clk>;
- ti,bit-shift = <9>;
- reg = <0x0560>;
- };
-
- slimbus1_fclk_0: slimbus1_fclk_0@560 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&abe_24m_fclk>;
- ti,bit-shift = <8>;
- reg = <0x0560>;
- };
-
- slimbus1_fclk_2: slimbus1_fclk_2@560 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&pad_clks_ck>;
- ti,bit-shift = <10>;
- reg = <0x0560>;
- };
-
- slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&slimbus_clk>;
- ti,bit-shift = <11>;
- reg = <0x0560>;
- };
-
- timer5_sync_mux: timer5_sync_mux@568 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0568>;
- };
-
- timer6_sync_mux: timer6_sync_mux@570 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0570>;
- };
-
- timer7_sync_mux: timer7_sync_mux@578 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0578>;
- };
-
- timer8_sync_mux: timer8_sync_mux@580 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0580>;
- };
-
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
+
&prm_clocks {
sys_clkin_ck: sys_clkin_ck@110 {
#clock-cells = <0>;
@@ -675,22 +524,6 @@
ti,max-div = <2>;
};
- gpio1_dbclk: gpio1_dbclk@1838 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1838>;
- };
-
- dmt1_clk_mux: dmt1_clk_mux@1840 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1840>;
- };
-
usim_ck: usim_ck@1858 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -708,45 +541,10 @@
reg = <0x1858>;
};
- pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@1a20 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
- ti,bit-shift = <20>;
- reg = <0x1a20>;
- };
-
- pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@1a20 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
- ti,bit-shift = <22>;
- reg = <0x1a20>;
- };
-
- stm_clk_div_ck: stm_clk_div_ck@1a20 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&pmd_stm_clock_mux_ck>;
- ti,bit-shift = <27>;
- ti,max-div = <64>;
- reg = <0x1a20>;
- ti,index-power-of-two;
- };
-
- trace_clk_div_div_ck: trace_clk_div_div_ck@1a20 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&pmd_trace_clk_mux_ck>;
- ti,bit-shift = <24>;
- reg = <0x1a20>;
- ti,dividers = <0>, <1>, <2>, <0>, <4>;
- };
-
trace_clk_div_ck: trace_clk_div_ck {
#clock-cells = <0>;
compatible = "ti,clkdm-gate-clock";
- clocks = <&trace_clk_div_div_ck>;
+ clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>;
};
};
@@ -975,155 +773,6 @@
ti,max-div = <2>;
};
- dss_sys_clk: dss_sys_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&syc_clk_div_ck>;
- ti,bit-shift = <10>;
- reg = <0x1120>;
- };
-
- dss_tv_clk: dss_tv_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&extalt_clkin_ck>;
- ti,bit-shift = <11>;
- reg = <0x1120>;
- };
-
- dss_dss_clk: dss_dss_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_per_m5x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x1120>;
- ti,set-rate-parent;
- };
-
- dss_48mhz_clk: dss_48mhz_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_48mc_fclk>;
- ti,bit-shift = <9>;
- reg = <0x1120>;
- };
-
- fdif_fck: fdif_fck@1028 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_m4x2_ck>;
- ti,bit-shift = <24>;
- ti,max-div = <4>;
- reg = <0x1028>;
- ti,index-power-of-two;
- };
-
- gpio2_dbclk: gpio2_dbclk@1460 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1460>;
- };
-
- gpio3_dbclk: gpio3_dbclk@1468 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1468>;
- };
-
- gpio4_dbclk: gpio4_dbclk@1470 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1470>;
- };
-
- gpio5_dbclk: gpio5_dbclk@1478 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1478>;
- };
-
- gpio6_dbclk: gpio6_dbclk@1480 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1480>;
- };
-
- sgx_clk_mux: sgx_clk_mux@1220 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1220>;
- };
-
- hsi_fck: hsi_fck@1338 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- ti,max-div = <4>;
- reg = <0x1338>;
- ti,index-power-of-two;
- };
-
- iss_ctrlclk: iss_ctrlclk@1020 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_96m_fclk>;
- ti,bit-shift = <8>;
- reg = <0x1020>;
- };
-
- mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@14e0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
- ti,bit-shift = <25>;
- reg = <0x14e0>;
- };
-
- per_mcbsp4_gfclk: per_mcbsp4_gfclk@14e0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
- ti,bit-shift = <24>;
- reg = <0x14e0>;
- };
-
- hsmmc1_fclk: hsmmc1_fclk@1328 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_64m_fclk>, <&func_96m_fclk>;
- ti,bit-shift = <24>;
- reg = <0x1328>;
- };
-
- hsmmc2_fclk: hsmmc2_fclk@1330 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_64m_fclk>, <&func_96m_fclk>;
- ti,bit-shift = <24>;
- reg = <0x1330>;
- };
-
- ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@13e0 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_48m_fclk>;
- ti,bit-shift = <8>;
- reg = <0x13e0>;
- };
-
sha2md5_fck: sha2md5_fck@15c8 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1132,222 +781,6 @@
reg = <0x15c8>;
};
- slimbus2_fclk_1: slimbus2_fclk_1@1538 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_abe_24m_fclk>;
- ti,bit-shift = <9>;
- reg = <0x1538>;
- };
-
- slimbus2_fclk_0: slimbus2_fclk_0@1538 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_24mc_fclk>;
- ti,bit-shift = <8>;
- reg = <0x1538>;
- };
-
- slimbus2_slimbus_clk: slimbus2_slimbus_clk@1538 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&pad_slimbus_core_clks_ck>;
- ti,bit-shift = <10>;
- reg = <0x1538>;
- };
-
- smartreflex_core_fck: smartreflex_core_fck@638 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0638>;
- };
-
- smartreflex_iva_fck: smartreflex_iva_fck@630 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0630>;
- };
-
- smartreflex_mpu_fck: smartreflex_mpu_fck@628 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0628>;
- };
-
- cm2_dm10_mux: cm2_dm10_mux@1428 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1428>;
- };
-
- cm2_dm11_mux: cm2_dm11_mux@1430 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1430>;
- };
-
- cm2_dm2_mux: cm2_dm2_mux@1438 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1438>;
- };
-
- cm2_dm3_mux: cm2_dm3_mux@1440 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1440>;
- };
-
- cm2_dm4_mux: cm2_dm4_mux@1448 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1448>;
- };
-
- cm2_dm9_mux: cm2_dm9_mux@1450 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1450>;
- };
-
- usb_host_fs_fck: usb_host_fs_fck@13d0 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_48mc_fclk>;
- ti,bit-shift = <1>;
- reg = <0x13d0>;
- };
-
- utmi_p1_gfclk: utmi_p1_gfclk@1358 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
- ti,bit-shift = <24>;
- reg = <0x1358>;
- };
-
- usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&utmi_p1_gfclk>;
- ti,bit-shift = <8>;
- reg = <0x1358>;
- };
-
- utmi_p2_gfclk: utmi_p2_gfclk@1358 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
- ti,bit-shift = <25>;
- reg = <0x1358>;
- };
-
- usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&utmi_p2_gfclk>;
- ti,bit-shift = <9>;
- reg = <0x1358>;
- };
-
- usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <10>;
- reg = <0x1358>;
- };
-
- usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_usb_m2_ck>;
- ti,bit-shift = <13>;
- reg = <0x1358>;
- };
-
- usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <11>;
- reg = <0x1358>;
- };
-
- usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <12>;
- reg = <0x1358>;
- };
-
- usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_usb_m2_ck>;
- ti,bit-shift = <14>;
- reg = <0x1358>;
- };
-
- usb_host_hs_func48mclk: usb_host_hs_func48mclk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_48mc_fclk>;
- ti,bit-shift = <15>;
- reg = <0x1358>;
- };
-
- usb_host_hs_fck: usb_host_hs_fck@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <1>;
- reg = <0x1358>;
- };
-
- otg_60m_gfclk: otg_60m_gfclk@1360 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
- ti,bit-shift = <24>;
- reg = <0x1360>;
- };
-
- usb_otg_hs_xclk: usb_otg_hs_xclk@1360 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&otg_60m_gfclk>;
- ti,bit-shift = <8>;
- reg = <0x1360>;
- };
-
- usb_otg_hs_ick: usb_otg_hs_ick@1360 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3_div_ck>;
- ti,bit-shift = <0>;
- reg = <0x1360>;
- };
-
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1355,44 +788,12 @@
ti,bit-shift = <8>;
reg = <0x0640>;
};
-
- usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1368 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <10>;
- reg = <0x1368>;
- };
-
- usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1368 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <8>;
- reg = <0x1368>;
- };
-
- usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1368 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <9>;
- reg = <0x1368>;
- };
-
- usb_tll_hs_ick: usb_tll_hs_ick@1368 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_div_ck>;
- ti,bit-shift = <0>;
- reg = <0x1368>;
- };
};
&cm2_clockdomains {
l3_init_clkdm: l3_init_clkdm {
compatible = "ti,clockdomain";
- clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>;
+ clocks = <&dpll_usb_ck>;
};
};
@@ -1631,3 +1032,291 @@
reg = <0x0224>;
};
};
+
+&cm1 {
+ mpuss_cm: mpuss_cm@300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x300 0x100>;
+
+ mpuss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ tesla_cm: tesla_cm@400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x400 0x100>;
+
+ tesla_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ abe_cm: abe_cm@500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x500 0x100>;
+
+ abe_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x6c>;
+ #clock-cells = <2>;
+ };
+ };
+
+};
+
+&cm2 {
+ l4_ao_cm: l4_ao_cm@600 {
+ compatible = "ti,omap4-cm";
+ reg = <0x600 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x600 0x100>;
+
+ l4_ao_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_1_cm: l3_1_cm@700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x700 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x700 0x100>;
+
+ l3_1_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_2_cm: l3_2_cm@800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x800 0x100>;
+
+ l3_2_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ducati_cm: ducati_cm@900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x900 0x100>;
+
+ ducati_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_dma_cm: l3_dma_cm@a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xa00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa00 0x100>;
+
+ l3_dma_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_emif_cm: l3_emif_cm@b00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xb00 0x100>;
+
+ l3_emif_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ d2d_cm: d2d_cm@c00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xc00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xc00 0x100>;
+
+ d2d_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_cfg_cm: l4_cfg_cm@d00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xd00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xd00 0x100>;
+
+ l4_cfg_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_instr_cm: l3_instr_cm@e00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xe00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe00 0x100>;
+
+ l3_instr_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x24>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ivahd_cm: ivahd_cm@f00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xf00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xf00 0x100>;
+
+ ivahd_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ iss_cm: iss_cm@1000 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x100>;
+
+ iss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_dss_cm: l3_dss_cm@1100 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1100 0x100>;
+
+ l3_dss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_gfx_cm: l3_gfx_cm@1200 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1200 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1200 0x100>;
+
+ l3_gfx_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_init_cm: l3_init_cm@1300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1300 0x100>;
+
+ l3_init_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_per_cm: l4_per_cm@1400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1400 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1400 0x200>;
+
+ l4_per_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x144>;
+ #clock-cells = <2>;
+ };
+ };
+
+};
+
+&prm {
+ l4_wkup_cm: l4_wkup_cm@1800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1800 0x100>;
+
+ l4_wkup_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x5c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ emu_sys_cm: emu_sys_cm@1a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1a00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1a00 0x100>;
+
+ emu_sys_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+};
--
1.9.1
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* [PATCHv2 00/20] ARM: dts: add omap clkctrl support
From: Tero Kristo @ 2017-12-08 15:17 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Hi,
Just reposting v2 of the relevant patches. The only change in this
version is the conversion of clkctrl clock handles to use the
dt-binding macros instead of hardcoded magic values. The contents
of the compiled .dtb files are completely unchanged in this.
e.g. clocks = <&l4per_clkctrl 0 0> => <&l4per_clkctrl OMAP4_UART3_CLKCTRL 0>
-Tero
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* Re: [RFC] irqchip: add support for LS1021A external interrupt lines
From: Alexander Stein @ 2017-12-08 15:11 UTC (permalink / raw)
To: Rasmus Villemoes
Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
Mark Rutland, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512743580-15358-1-git-send-email-rasmus.villemoes-rjjw5hvvQKZaa/9Udqfwiw@public.gmane.org>
Hi Rasmus,
thanks for your effort. unfortunatly I won't be able to test it currently :(
But some comments below.
On Friday, December 8, 2017, 3:33:00 PM CET Rasmus Villemoes wrote:
> The LS1021A allows inverting the polarity of six interrupt lines
> IRQ[0:5] via the scfg_intpcr register, effectively allowing
> IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_EDGE_FALLING for those. We just need to
> check the type, set the relevant bit in INTPCR accordingly, and fixup
> the type argument before calling the GIC's irq_set_type.
>
> In fact, the power-on-reset value of the INTPCR register is so that all
> six lines have their polarity inverted. Hence any hardware connected to
> those lines is unusable without this: If the line is indeed active low,
> the generic GIC code will reject an irq spec with IRQ_TYPE_LEVEL_LOW,
> while if the line is active high, we must obviously disable the polarity
> inversion before unmasking the interrupt.
>
> I suspect other layerscape SOCs may have something similar, but I have
> neither hardware nor documentation.
>
> Since we only need to keep a single pointer in the chip_data (the syscon
> regmap), the code could be a little simpler by dropping the struct
> extirq_chip_data and just store the regmap directly - but I don't know
> if I do need to add a lock or something else to the chip_data, so for
> this RFC I've kept the struct.
>
> Signed-off-by: Rasmus Villemoes <rasmus.villemoes-rjjw5hvvQKZaa/9Udqfwiw@public.gmane.org>
> ---
> Marc, Alexander, thanks a lot for your hints. This is what I came up
> with, mostly just copy-pasted from the mtk-sysirq case. I've tested
> that it works as expected on my board.
>
> .../interrupt-controller/fsl,ls1021a-extirq.txt | 19 +++
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-ls1021a.c | 157 +++++++++++++++++++++
> 3 files changed, 177 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls1021a-extirq.txt
> create mode 100644 drivers/irqchip/irq-ls1021a.c
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls1021a-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls1021a-extirq.txt
> new file mode 100644
> index 000000000000..53b04b6e1a80
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls1021a-extirq.txt
> @@ -0,0 +1,19 @@
> +* Freescale LS1021A external IRQs
> +
> +The LS1021A supports inverting the polarity of six external interrupt lines.
> +
> +Required properties:
> +- compatible: should be "fsl,ls1021a-extirq"
> +- interrupt-controller: Identifies the node as an interrupt controller
> +- #interrupt-cells: Use the same format as specified by GIC in arm,gic.txt.
Do you really need 3 interrupt-cells here? As you've written below you don't
support PPI anyway the 1st flag might be dropped then. So support just 2 cells:
* IRQ number (IRQ0 - IRQ5)
* IRQ flags
> +- interrupt-parent: phandle of GIC.
> +- syscon: phandle of Supplemental Configuration Unit (scfg).
> +
> +Example:
> + extirq: interrupt-controller@15701ac {
> + compatible = "fsl,ls1021a-extirq";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + syscon = <&scfg>;
> + };
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index b842dfdc903f..d4576dce24b2 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -80,3 +80,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
> obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
> obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
> obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
> +obj-$(CONFIG_SOC_LS1021A) += irq-ls1021a.o
I guess this should be kept sorted alphabetically.
> diff --git a/drivers/irqchip/irq-ls1021a.c b/drivers/irqchip/irq-ls1021a.c
> new file mode 100644
> index 000000000000..2ec4fc023549
> --- /dev/null
> +++ b/drivers/irqchip/irq-ls1021a.c
> @@ -0,0 +1,157 @@
> +#define pr_fmt(fmt) "irq-ls1021a: " fmt
> +
> +#include <linux/irq.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +
> +#define INTPCR_REG 0x01ac
> +#define NIRQ 6
> +
> +struct extirq_chip_data {
> + struct regmap *syscon;
> +};
> +
> +static int
> +ls1021a_extirq_set_type(struct irq_data *data, unsigned int type)
> +{
> + irq_hw_number_t hwirq = data->hwirq;
> + struct extirq_chip_data *chip_data = data->chip_data;
> + u32 value, mask;
> + int ret;
> +
> + mask = 1U << (31 - hwirq);
Is this really correct? IRQ0 is still at bit position 0. Don't be mislead
by the left most position in the register layout. This is just strange way
to express bit-endian access.
Anyway, please use BIT(x) instead.
> + if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
> + if (type == IRQ_TYPE_LEVEL_LOW)
> + type = IRQ_TYPE_LEVEL_HIGH;
> + else
> + type = IRQ_TYPE_EDGE_RISING;
> + value = mask;
> + } else {
> + value = 0;
> + }
> +
> + /* Don't do the INTPCR_REG update if the parent irq_set_type will EINVAL. */
> + if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
> + return -EINVAL;
I wonder if it is better to call data->parent_data->chip->irq_set_type(data, type)
here instead and call regmap if this suceeded.
> + /* regmap does internal locking, but do we need to provide our
> + * own across the parent irq_set_type call? */
> + regmap_update_bits(chip_data->syscon, INTPCR_REG, mask, value);
> +
> + data = data->parent_data;
> + ret = data->chip->irq_set_type(data, type);
> +
> + return ret;
> +}
> +
> +static struct irq_chip extirq_chip = {
> + .name = "LS1021A_EXTIRQ",
> + .irq_mask = irq_chip_mask_parent,
> + .irq_unmask = irq_chip_unmask_parent,
> + .irq_eoi = irq_chip_eoi_parent,
> + .irq_set_type = ls1021a_extirq_set_type,
> + .irq_retrigger = irq_chip_retrigger_hierarchy,
> + .irq_set_affinity = irq_chip_set_affinity_parent,
> +};
> +
> +static int
> +ls1021a_extirq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
> + unsigned long *hwirq, unsigned int *type)
> +{
> + if (!is_of_node(fwspec->fwnode))
> + return -EINVAL;
> +
> + if (fwspec->param_count != 3)
> + return -EINVAL;
> +
> + /* No PPI should point to this domain */
> + if (fwspec->param[0] != 0)
> + return -EINVAL;
> +
> + *hwirq = fwspec->param[1];
Is a check for the hwirq value required here? I'm not an expert on
irqchip API, so I just wonder.
> + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
> + return 0;
> +}
> +
> +static int
> +ls1021a_extirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> + unsigned int nr_irqs, void *arg)
> +{
> + static const unsigned xlate[NIRQ] = {163,164,165,167,168,169};
^^^^^^
No need for static here.
> + int i;
> + irq_hw_number_t hwirq;
> + struct irq_fwspec *fwspec = arg;
> + struct irq_fwspec gic_fwspec;
> +
> + if (fwspec->param_count != 3)
> + return -EINVAL;
> +
> + if (fwspec->param[0])
> + return -EINVAL;
> +
> + hwirq = fwspec->param[1];
Is there any guarantee hwirq is in range 0-5?
> + for (i = 0; i < nr_irqs; i++)
> + irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
> + &extirq_chip,
> + domain->host_data);
> +
> + gic_fwspec.fwnode = domain->parent->fwnode;
> + gic_fwspec.param_count = 3;
> + gic_fwspec.param[0] = 0;
As this param is fixed, you should be able to drop the 1st param in your
interrupt-cells.
> + gic_fwspec.param[1] = xlate[hwirq];
> + gic_fwspec.param[2] = fwspec->param[2];
> +
> + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_fwspec);
> +}
> +
> +static const struct irq_domain_ops extirq_domain_ops = {
> + .translate = ls1021a_extirq_domain_translate,
> + .alloc = ls1021a_extirq_domain_alloc,
> + .free = irq_domain_free_irqs_common,
> +};
> +
> +static int __init
> +ls1021a_extirq_of_init(struct device_node *node, struct device_node *parent)
> +{
> +
> + struct irq_domain *domain, *domain_parent;
> + struct extirq_chip_data *chip_data;
> + int ret;
> +
> + domain_parent = irq_find_host(parent);
> + if (!domain_parent) {
> + pr_err("interrupt-parent not found\n");
> + return -EINVAL;
> + }
Mh, does this mean if GIC has not been probed, this probe is not deferred?
Is there an API to check for that?
> + chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
^^^^^^^
devm_kzalloc
> + if (!chip_data)
> + return -ENOMEM;
> +
> + chip_data->syscon = syscon_regmap_lookup_by_phandle(node, "syscon");
> + if (IS_ERR(chip_data->syscon)) {
> + ret = PTR_ERR(chip_data->syscon);
> + goto out_free_chip;
> + }
> +
> + domain = irq_domain_add_hierarchy(domain_parent, 0, NIRQ, node,
> + &extirq_domain_ops, chip_data);
> + if (!domain) {
> + ret = -ENOMEM;
> + goto out_free_chip;
> + }
> +
> + return 0;
> +
> +out_free_chip:
> + kfree(chip_data);
> + return ret;
Using devm_kzalloc this label can be skipped.
> +}
> +
> +IRQCHIP_DECLARE(ls1021a_extirq, "fsl,ls1021a-extirq", ls1021a_extirq_of_init);
Best regards,
Alexander
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* Re: [PATCH 0/2] of: overlay: Crash fix and improvement
From: Rob Herring @ 2017-12-08 15:11 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Pantelis Antoniou, Frank Rowand, devicetree, linux-renesas-soc,
linux-kernel
In-Reply-To: <1512738783-17452-1-git-send-email-geert+renesas@glider.be>
On Fri, Dec 08, 2017 at 02:13:01PM +0100, Geert Uytterhoeven wrote:
> Hi Pantelis, Rob, Frank,
>
> This patch series fixes memory corruption when applying overlays.
>
> I first noticed this when using OF configfs. After lots of failed
> debugging attempts, I bisected it to "of: overlay: add per overlay sysfs
> attributes", which is not upstream. But that was a red herring: that
> commit enlarged struct fragment to exactly 64-bytes, which just made it
> more likely to cause random corruption when writing beyond the end of an
> array of fragment structures. With the smaller structure size before,
> such writes usually ended up in the unused holes between allocated
> blocks, causing no harm.
>
> The first patch is the real fix, and applies to both v4.15-rc2 and Rob's
> for-next branch.
> The second patch is a small improvement, and applies to Rob's for-next
> branch only.
>
> I've updated my topic/overlays and topic/renesas-overlays branches at
> git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
> accordingly.
>
> Thanks!
>
> Geert Uytterhoeven (2):
> of: overlay: Fix out-of-bounds write in init_overlay_changeset()
> of: overlay: Make node skipping in init_overlay_changeset() clearer
I've applied both and am updating my pull req to Linus. I hope that's
the end of it. If further fixes can't be reproduced with mainline, I'm
not going to be inclined to take them for 4.15.
Rob
^ permalink raw reply
* Re: [GIT PULL] DeviceTree fixes for 4.15, part 2
From: Rob Herring @ 2017-12-08 15:07 UTC (permalink / raw)
To: Linus Torvalds
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Frank Rowand,
Mark Rutland
In-Reply-To: <CAL_Jsq+EztEAQwqV4LLE5111MjnmV6hHCrzUbaRYLuMTWYY7Fg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Fri, Dec 8, 2017 at 8:10 AM, Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Hi Linus,
>
> Please pull another set of DT fixes.
Disregard this one. I've just gotten another overlay fix, so I'm going
to add that in.
Rob
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* Re: [PATCH v1 1/2] eeprom: at24: convert magic numbers to structs.
From: Bartosz Golaszewski @ 2017-12-08 15:05 UTC (permalink / raw)
To: Sven Van Asbroeck
Cc: Sven Van Asbroeck, Wolfram Sang, nsekhar-l0cyMroinI0,
Sakari Ailus, Javier Martinez Canillas, Divagar Mohandass,
devicetree-u79uwXL29TY76Z2rM5mHXA, Linux Kernel Mailing List,
linux-i2c
In-Reply-To: <CAGngYiWdnE9Ztu3uGeqAS+Ksag6-W84AORJnWb1Xzc7EMBwZNg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-12-08 15:17 GMT+01:00 Sven Van Asbroeck <thesven73-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>:
> Bartosz wrote:
>>> +#define AT24_OF_DEVICE_ID(_mfg, _name) \
>>> + { .compatible = #_mfg "," #_name, .data = &platdata_##_name }
>>
>> I don't like hiding the way the compatible is created here from the
>> user. It doesn't save any code neither. Please make the macro accept
>> the whole compatible string.
>>
>
> If the macro accepts the whole compatible string "mfg,chip-name" (e.g.
> "atmel,24c01")
> then how can I extract chip-name from that string? I need to attach
> chip-name to the
> platdata_ static structures. (e.g. "atmel,24c01" -> .data = platdata_24c01)
Just make it accept two parameters: the string and the data object
name. For example:
AT24_OF_DEVICE_ID("atmel,24c01", 24c01);
Thanks,
Bartosz
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* Re: [PATCH v3 05/33] nds32: Exception handling
From: Al Viro @ 2017-12-08 15:05 UTC (permalink / raw)
To: Greentime Hu
Cc: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, dhowells,
will.deacon, daniel.lezcano, linux-serial, geert.uytterhoeven,
linus.walleij, mark.rutland, greg, Vincent Chen
In-Reply-To: <8fad3e13c85cd90bd038cac7ead0e97e4438a0e0.1512723245.git.green.hu@gmail.com>
On Fri, Dec 08, 2017 at 05:11:48PM +0800, Greentime Hu wrote:
> diff --git a/arch/nds32/kernel/traps.c b/arch/nds32/kernel/traps.c
> new file mode 100644
> index 0000000..30a275d
> --- /dev/null
> +++ b/arch/nds32/kernel/traps.c
> @@ -0,0 +1,441 @@
> +/*
> + * Copyright (C) 2005-2017 Andes Technology Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/personality.h>
> +#include <linux/kallsyms.h>
> +#include <linux/hardirq.h>
> +#include <linux/kdebug.h>
> +#include <linux/sched/task_stack.h>
> +
> +#include <asm/proc-fns.h>
> +#include <asm/uaccess.h>
The only include of asm/uaccess.h should be in linux/uaccess.h; everything
else should include linux/uaccess.h. The same goes for other patches in
the series.
^ permalink raw reply
* Re: [PATCH v1 1/2] eeprom: at24: convert magic numbers to structs.
From: Bartosz Golaszewski @ 2017-12-08 15:05 UTC (permalink / raw)
To: Sven Van Asbroeck
Cc: Sven Van Asbroeck, Wolfram Sang, nsekhar-l0cyMroinI0,
Sakari Ailus, Javier Martinez Canillas, Divagar Mohandass,
devicetree-u79uwXL29TY76Z2rM5mHXA, Linux Kernel Mailing List,
linux-i2c
In-Reply-To: <CAGngYiXtUBbYocb885CPCaXNM=uckeiHc47FXKghDz_B-WNYrg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-12-08 15:10 GMT+01:00 Sven Van Asbroeck <thesven73-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>:
> Hi Bartosz, thanks for the encouragement !
>
> Bartosz wrote:
>> Also: please have the AT24/at24 prefix for symbols in the driver.
>
> These specific symbols are declared static, i.e. they're visible only
> inside at24.c.
> Do you think they should still have an at24 prefix ?
>
> +#define DECLARE_AT24_PLATDATA(_name, _len, _flags) \
> + static const struct at24_platform_data platdata_##_name = { \
> + .byte_len = _len, .flags = _flags, \
> + }
Yes, it's a common pattern in the kernel and it adds to readability.
Thanks,
Bartosz
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH V7 5/7] ACPI: properties: Implement get_match_data() callback
From: Rafael J. Wysocki @ 2017-12-08 14:51 UTC (permalink / raw)
To: Sinan Kaya
Cc: dmaengine, Timur Tabi, devicetree@vger.kernel.org,
ACPI Devel Maling List, Sakari Ailus, linux-arm-msm,
linux-arm-kernel@lists.infradead.org, Rafael J. Wysocki,
Len Brown, open list
In-Reply-To: <1512681031-11343-6-git-send-email-okaya@codeaurora.org>
On Thu, Dec 7, 2017 at 10:10 PM, Sinan Kaya <okaya@codeaurora.org> wrote:
> Now that we have a get_match_data() callback as part of the firmware node,
> implement the ACPI specific piece for it.
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
> Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> drivers/acpi/property.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c
> index e26ea20..466d150 100644
> --- a/drivers/acpi/property.c
> +++ b/drivers/acpi/property.c
> @@ -1271,9 +1271,17 @@ static int acpi_fwnode_graph_parse_endpoint(const struct fwnode_handle *fwnode,
> return 0;
> }
>
> +static void *
> +acpi_fwnode_device_get_match_data(const struct fwnode_handle *fwnode,
> + const struct device *dev)
> +{
> + return acpi_get_match_data(dev);
> +}
> +
> #define DECLARE_ACPI_FWNODE_OPS(ops) \
> const struct fwnode_operations ops = { \
> .device_is_available = acpi_fwnode_device_is_available, \
> + .device_get_match_data = acpi_fwnode_device_get_match_data, \
> .property_present = acpi_fwnode_property_present, \
> .property_read_int_array = \
> acpi_fwnode_property_read_int_array, \
> --
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
^ permalink raw reply
* Re: [PATCH V7 2/7] ACPI / bus: Introduce acpi_get_match_data() function
From: Rafael J. Wysocki @ 2017-12-08 14:51 UTC (permalink / raw)
To: Sinan Kaya
Cc: dmaengine, Timur Tabi, devicetree@vger.kernel.org,
ACPI Devel Maling List, Sakari Ailus, linux-arm-msm,
linux-arm-kernel@lists.infradead.org, Rafael J. Wysocki,
Len Brown, open list
In-Reply-To: <1512681031-11343-3-git-send-email-okaya@codeaurora.org>
On Thu, Dec 7, 2017 at 10:10 PM, Sinan Kaya <okaya@codeaurora.org> wrote:
> OF has of_device_get_match_data() function to extract driver specific data
> structure. Add a similar function for ACPI.
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
> ---
> drivers/acpi/bus.c | 18 ++++++++++++++++++
> include/linux/acpi.h | 6 ++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
> index 4d0979e..f87ed3b 100644
> --- a/drivers/acpi/bus.c
> +++ b/drivers/acpi/bus.c
> @@ -785,6 +785,24 @@ const struct acpi_device_id *acpi_match_device(const struct acpi_device_id *ids,
> }
> EXPORT_SYMBOL_GPL(acpi_match_device);
>
> +void *acpi_get_match_data(const struct device *dev)
> +{
> + const struct acpi_device_id *match;
> +
> + if (!dev->driver)
> + return NULL;
> +
> + if (!dev->driver->acpi_match_table)
> + return NULL;
You can safely check dev->driver and this in the same statement (as
long as the first check to be made is on the left).
> +
> + match = acpi_match_device(dev->driver->acpi_match_table, dev);
> + if (!match)
> + return NULL;
> +
> + return (void *)match->driver_data;
> +}
> +EXPORT_SYMBOL_GPL(acpi_get_match_data);
> +
> int acpi_match_device_ids(struct acpi_device *device,
> const struct acpi_device_id *ids)
> {
> diff --git a/include/linux/acpi.h b/include/linux/acpi.h
> index 502af53..a927260 100644
> --- a/include/linux/acpi.h
> +++ b/include/linux/acpi.h
> @@ -584,6 +584,7 @@ extern int acpi_nvs_for_each_region(int (*func)(__u64, __u64, void *),
> const struct acpi_device_id *acpi_match_device(const struct acpi_device_id *ids,
> const struct device *dev);
>
> +void *acpi_get_match_data(const struct device *dev);
> extern bool acpi_driver_match_device(struct device *dev,
> const struct device_driver *drv);
> int acpi_device_uevent_modalias(struct device *, struct kobj_uevent_env *);
> @@ -755,6 +756,11 @@ static inline const struct acpi_device_id *acpi_match_device(
> return NULL;
> }
>
> +static inline void *acpi_get_match_data(const struct device *dev)
> +{
> + return NULL;
> +}
> +
> static inline bool acpi_driver_match_device(struct device *dev,
> const struct device_driver *drv)
> {
> --
But anyway
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
^ permalink raw reply
* Re: [PATCH v4 4/4] arm64: dts: meson-axg: add clock DT info for Meson AXG SoC
From: Yixun Lan @ 2017-12-08 14:50 UTC (permalink / raw)
To: Kevin Hilman
Cc: yixun.lan, Neil Armstrong, Jerome Brunet, Rob Herring,
Mark Rutland, Michael Turquette, Stephen Boyd, Carlo Caione,
Qiufang Dai, linux-amlogic, devicetree, linux-clk,
linux-arm-kernel, linux-kernel
In-Reply-To: <7ho9nbmked.fsf@baylibre.com>
On 12/07/17 08:50, Kevin Hilman wrote:
> Yixun Lan <yixun.lan@amlogic.com> writes:
>
>> From: Qiufang Dai <qiufang.dai@amlogic.com>
>>
>> Try to add Hiubus DT info, and also enable clock DT info
>> for the Amlogic's Meson-AXG SoC.
>>
>> Acked-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index b932a784b02a..36a2e98338a8 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -7,6 +7,7 @@
>> #include <dt-bindings/gpio/gpio.h>
>> #include <dt-bindings/interrupt-controller/irq.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/axg-clkc.h>
>
> This #include will cause an unnessary dependency from the amlogic tree
> to the clock tree even though this patch is not currently using any of
> the #defines from that header. It will simplify the dependencies if you
> drop this #include from this patch.
>
> In my comment on the cover letter, I suggested adding a patch that also
> switches the UART over to the new clock provider. That is the patch
> that should add this #include, since it will actually need #defines from
> the header.
>
ok, make sense
> Doing it in that order means that we could merge this patch
> independently of the clock driver, and then merge the UART switch-over
> patch only after the driver (and headers) are merged.
I was planing to add UART DT part as separately patches (including the
UARt's pinctrl part information)
but as follow your suggestion, I could split the UART's clock DT info
into separate patch, and send along with this series.
>
> Kevin
>
> .
>
^ permalink raw reply
* [PATCH v7 13/13] ASoC: stm32: add DFSDM DAI support
From: Arnaud Pouliquen @ 2017-12-08 14:49 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw, Maxime Coquelin,
Alexandre Torgue, arnaud.pouliquen-qxv4g6HH51o
In-Reply-To: <1512744566-13233-1-git-send-email-arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Add driver to handle DAI interface for PDM microphones connected
to Digital Filter for Sigma Delta Modulators IP.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
---
V6 to V7 updates:
- SPDX-Licensing.
- Supress workaround in stm32_adfsdm_pcm_new as issue fixed in generic code in recent kernel version.
- Fix kbuild report issue on a log parameter type.
- Suppress test in stm32_adfsdm_set_sysclk on clock direction.
sound/soc/stm/Kconfig | 11 ++
sound/soc/stm/Makefile | 3 +
sound/soc/stm/stm32_adfsdm.c | 351 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 365 insertions(+)
create mode 100644 sound/soc/stm/stm32_adfsdm.c
diff --git a/sound/soc/stm/Kconfig b/sound/soc/stm/Kconfig
index 3398e6c..a78f770 100644
--- a/sound/soc/stm/Kconfig
+++ b/sound/soc/stm/Kconfig
@@ -28,4 +28,15 @@ config SND_SOC_STM32_SPDIFRX
help
Say Y if you want to enable S/PDIF capture for STM32
+config SND_SOC_STM32_DFSDM
+ tristate "SoC Audio support for STM32 DFSDM"
+ depends on (ARCH_STM32 && OF && STM32_DFSDM_ADC) || COMPILE_TEST
+ depends on SND_SOC
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+ select SND_SOC_DMIC
+ select IIO_BUFFER_CB
+ help
+ Select this option to enable the STM32 Digital Filter
+ for Sigma Delta Modulators (DFSDM) driver used
+ in various STM32 series for digital microphone capture.
endmenu
diff --git a/sound/soc/stm/Makefile b/sound/soc/stm/Makefile
index 4ed22e6..53e90e6 100644
--- a/sound/soc/stm/Makefile
+++ b/sound/soc/stm/Makefile
@@ -12,3 +12,6 @@ obj-$(CONFIG_SND_SOC_STM32_I2S) += snd-soc-stm32-i2s.o
# SPDIFRX
snd-soc-stm32-spdifrx-objs := stm32_spdifrx.o
obj-$(CONFIG_SND_SOC_STM32_SPDIFRX) += snd-soc-stm32-spdifrx.o
+
+#DFSDM
+obj-$(CONFIG_SND_SOC_STM32_DFSDM) += stm32_adfsdm.o
diff --git a/sound/soc/stm/stm32_adfsdm.c b/sound/soc/stm/stm32_adfsdm.c
new file mode 100644
index 0000000..eef725e
--- /dev/null
+++ b/sound/soc/stm/stm32_adfsdm.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This file is part of STM32 DFSDM ASoC DAI driver
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Authors: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
+ * Olivier Moysan <olivier.moysan-qxv4g6HH51o@public.gmane.org>
+ */
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <linux/iio/iio.h>
+#include <linux/iio/consumer.h>
+#include <linux/iio/adc/stm32-dfsdm-adc.h>
+
+#include <sound/pcm.h>
+#include <sound/soc.h>
+
+#define STM32_ADFSDM_DRV_NAME "stm32-adfsdm"
+
+#define DFSDM_MAX_PERIOD_SIZE (PAGE_SIZE / 2)
+#define DFSDM_MAX_PERIODS 6
+
+struct stm32_adfsdm_priv {
+ struct snd_soc_dai_driver dai_drv;
+ struct snd_pcm_substream *substream;
+ struct device *dev;
+
+ /* IIO */
+ struct iio_channel *iio_ch;
+ struct iio_cb_buffer *iio_cb;
+ bool iio_active;
+
+ /* PCM buffer */
+ unsigned char *pcm_buff;
+ unsigned int pos;
+};
+
+static const struct snd_pcm_hardware stm32_adfsdm_pcm_hw = {
+ .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
+ SNDRV_PCM_INFO_PAUSE,
+ .formats = SNDRV_PCM_FMTBIT_S32_LE,
+
+ .rate_min = 8000,
+ .rate_max = 32000,
+
+ .channels_min = 1,
+ .channels_max = 1,
+
+ .periods_min = 2,
+ .periods_max = DFSDM_MAX_PERIODS,
+
+ .period_bytes_max = DFSDM_MAX_PERIOD_SIZE,
+ .buffer_bytes_max = DFSDM_MAX_PERIODS * DFSDM_MAX_PERIOD_SIZE
+};
+
+static void stm32_adfsdm_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
+
+ if (priv->iio_active) {
+ iio_channel_stop_all_cb(priv->iio_cb);
+ priv->iio_active = false;
+ }
+}
+
+static int stm32_adfsdm_dai_prepare(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
+ int ret;
+
+ ret = iio_write_channel_attribute(priv->iio_ch,
+ substream->runtime->rate, 0,
+ IIO_CHAN_INFO_SAMP_FREQ);
+ if (ret < 0) {
+ dev_err(dai->dev, "%s: Failed to set %d sampling rate\n",
+ __func__, substream->runtime->rate);
+ return ret;
+ }
+
+ if (!priv->iio_active) {
+ ret = iio_channel_start_all_cb(priv->iio_cb);
+ if (!ret)
+ priv->iio_active = true;
+ else
+ dev_err(dai->dev, "%s: IIO channel start failed (%d)\n",
+ __func__, ret);
+ }
+
+ return ret;
+}
+
+static int stm32_adfsdm_set_sysclk(struct snd_soc_dai *dai, int clk_id,
+ unsigned int freq, int dir)
+{
+ struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
+ ssize_t size;
+ char str_freq[10];
+
+ dev_dbg(dai->dev, "%s: Enter for freq %d\n", __func__, freq);
+
+ /* Set IIO frequency if CODEC is master as clock comes from SPI_IN*/
+
+ snprintf(str_freq, sizeof(str_freq), "%d\n", freq);
+ size = iio_write_channel_ext_info(priv->iio_ch, "spi_clk_freq",
+ str_freq, sizeof(str_freq));
+ if (size != sizeof(str_freq)) {
+ dev_err(dai->dev, "%s: Failed to set SPI clock\n",
+ __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static const struct snd_soc_dai_ops stm32_adfsdm_dai_ops = {
+ .shutdown = stm32_adfsdm_shutdown,
+ .prepare = stm32_adfsdm_dai_prepare,
+ .set_sysclk = stm32_adfsdm_set_sysclk,
+};
+
+static const struct snd_soc_dai_driver stm32_adfsdm_dai = {
+ .capture = {
+ .channels_min = 1,
+ .channels_max = 1,
+ .formats = SNDRV_PCM_FMTBIT_S32_LE,
+ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
+ SNDRV_PCM_RATE_32000),
+ },
+ .ops = &stm32_adfsdm_dai_ops,
+};
+
+static const struct snd_soc_component_driver stm32_adfsdm_dai_component = {
+ .name = "stm32_dfsdm_audio",
+};
+
+static int stm32_afsdm_pcm_cb(const void *data, size_t size, void *private)
+{
+ struct stm32_adfsdm_priv *priv = private;
+ struct snd_soc_pcm_runtime *rtd = priv->substream->private_data;
+ u8 *pcm_buff = priv->pcm_buff;
+ u8 *src_buff = (u8 *)data;
+ unsigned int buff_size = snd_pcm_lib_buffer_bytes(priv->substream);
+ unsigned int period_size = snd_pcm_lib_period_bytes(priv->substream);
+ unsigned int old_pos = priv->pos;
+ unsigned int cur_size = size;
+
+ dev_dbg(rtd->dev, "%s: buff_add :%p, pos = %d, size = %zu\n",
+ __func__, &pcm_buff[priv->pos], priv->pos, size);
+
+ if ((priv->pos + size) > buff_size) {
+ memcpy(&pcm_buff[priv->pos], src_buff, buff_size - priv->pos);
+ cur_size -= buff_size - priv->pos;
+ priv->pos = 0;
+ }
+
+ memcpy(&pcm_buff[priv->pos], &src_buff[size - cur_size], cur_size);
+ priv->pos = (priv->pos + cur_size) % buff_size;
+
+ if (cur_size != size || (old_pos && (old_pos % period_size < size)))
+ snd_pcm_period_elapsed(priv->substream);
+
+ return 0;
+}
+
+static int stm32_adfsdm_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct stm32_adfsdm_priv *priv =
+ snd_soc_dai_get_drvdata(rtd->cpu_dai);
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ priv->pos = 0;
+ return stm32_dfsdm_get_buff_cb(priv->iio_ch->indio_dev,
+ stm32_afsdm_pcm_cb, priv);
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_STOP:
+ return stm32_dfsdm_release_buff_cb(priv->iio_ch->indio_dev);
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int stm32_adfsdm_pcm_open(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ int ret;
+
+ ret = snd_soc_set_runtime_hwparams(substream, &stm32_adfsdm_pcm_hw);
+ if (!ret)
+ priv->substream = substream;
+
+ return ret;
+}
+
+static int stm32_adfsdm_pcm_close(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct stm32_adfsdm_priv *priv =
+ snd_soc_dai_get_drvdata(rtd->cpu_dai);
+
+ snd_pcm_lib_free_pages(substream);
+ priv->substream = NULL;
+
+ return 0;
+}
+
+static snd_pcm_uframes_t stm32_adfsdm_pcm_pointer(
+ struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct stm32_adfsdm_priv *priv =
+ snd_soc_dai_get_drvdata(rtd->cpu_dai);
+
+ return bytes_to_frames(substream->runtime, priv->pos);
+}
+
+static int stm32_adfsdm_pcm_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct stm32_adfsdm_priv *priv =
+ snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ int ret;
+
+ ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
+ if (ret < 0)
+ return ret;
+ priv->pcm_buff = substream->runtime->dma_area;
+
+ return iio_channel_cb_set_buffer_watermark(priv->iio_cb,
+ params_period_size(params));
+}
+
+static int stm32_adfsdm_pcm_hw_free(struct snd_pcm_substream *substream)
+{
+ snd_pcm_lib_free_pages(substream);
+
+ return 0;
+}
+
+static struct snd_pcm_ops stm32_adfsdm_pcm_ops = {
+ .open = stm32_adfsdm_pcm_open,
+ .close = stm32_adfsdm_pcm_close,
+ .hw_params = stm32_adfsdm_pcm_hw_params,
+ .hw_free = stm32_adfsdm_pcm_hw_free,
+ .trigger = stm32_adfsdm_trigger,
+ .pointer = stm32_adfsdm_pcm_pointer,
+};
+
+static int stm32_adfsdm_pcm_new(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_pcm *pcm = rtd->pcm;
+ struct stm32_adfsdm_priv *priv =
+ snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ unsigned int size = DFSDM_MAX_PERIODS * DFSDM_MAX_PERIOD_SIZE;
+ int ret;
+
+ ret = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
+ priv->dev, size, size);
+ return ret;
+}
+
+static void stm32_adfsdm_pcm_free(struct snd_pcm *pcm)
+{
+ struct snd_pcm_substream *substream;
+ struct snd_soc_pcm_runtime *rtd;
+ struct stm32_adfsdm_priv *priv;
+
+ substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
+ if (substream) {
+ rtd = substream->private_data;
+ priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+
+ snd_pcm_lib_preallocate_free_for_all(pcm);
+ }
+}
+
+static struct snd_soc_platform_driver stm32_adfsdm_soc_platform = {
+ .ops = &stm32_adfsdm_pcm_ops,
+ .pcm_new = stm32_adfsdm_pcm_new,
+ .pcm_free = stm32_adfsdm_pcm_free,
+};
+
+static const struct of_device_id stm32_adfsdm_of_match[] = {
+ {.compatible = "st,stm32h7-dfsdm-dai"},
+ {}
+};
+MODULE_DEVICE_TABLE(of, stm32_adfsdm_of_match);
+
+static int stm32_adfsdm_probe(struct platform_device *pdev)
+{
+ struct stm32_adfsdm_priv *priv;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = &pdev->dev;
+ priv->dai_drv = stm32_adfsdm_dai;
+
+ dev_set_drvdata(&pdev->dev, priv);
+
+ ret = devm_snd_soc_register_component(&pdev->dev,
+ &stm32_adfsdm_dai_component,
+ &priv->dai_drv, 1);
+ if (ret < 0)
+ return ret;
+
+ /* Associate iio channel */
+ priv->iio_ch = devm_iio_channel_get_all(&pdev->dev);
+ if (IS_ERR(priv->iio_ch))
+ return PTR_ERR(priv->iio_ch);
+
+ priv->iio_cb = iio_channel_get_all_cb(&pdev->dev, NULL, NULL);
+ if (IS_ERR(priv->iio_cb))
+ return PTR_ERR(priv->iio_ch);
+
+ ret = devm_snd_soc_register_platform(&pdev->dev,
+ &stm32_adfsdm_soc_platform);
+ if (ret < 0)
+ dev_err(&pdev->dev, "%s: Failed to register PCM platform\n",
+ __func__);
+
+ return ret;
+}
+
+static struct platform_driver stm32_adfsdm_driver = {
+ .driver = {
+ .name = STM32_ADFSDM_DRV_NAME,
+ .of_match_table = stm32_adfsdm_of_match,
+ },
+ .probe = stm32_adfsdm_probe,
+};
+
+module_platform_driver(stm32_adfsdm_driver);
+
+MODULE_DESCRIPTION("stm32 DFSDM DAI driver");
+MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" STM32_ADFSDM_DRV_NAME);
--
2.7.4
^ permalink raw reply related
* [PATCH v7 12/13] ASoC: add bindings for stm32 DFSDM filter
From: Arnaud Pouliquen @ 2017-12-08 14:49 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw, Maxime Coquelin,
Alexandre Torgue, arnaud.pouliquen-qxv4g6HH51o
In-Reply-To: <1512744566-13233-1-git-send-email-arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Add bindings that describes audio settings to support
Digital Filter for pulse density modulation(PDM) microphone.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
V6 to V7 update:
- Minor update to add missing interrupt-cells in example.
.../devicetree/bindings/sound/st,stm32-adfsdm.txt | 63 ++++++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt b/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt
new file mode 100644
index 0000000..864f5b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt
@@ -0,0 +1,63 @@
+STMicroelectronics Audio Digital Filter Sigma Delta modulators(DFSDM)
+
+The DFSDM allows PDM microphones capture through SPI interface. The Audio
+interface is seems as a sub block of the DFSDM device.
+For details on DFSDM bindings refer to ../iio/adc/st,stm32-dfsdm-adc.txt
+
+Required properties:
+ - compatible: "st,stm32h7-dfsdm-dai".
+
+ - #sound-dai-cells : Must be equal to 0
+
+ - io-channels : phandle to iio dfsdm instance node.
+
+Example of a sound card using audio DFSDM node.
+
+ sound_card {
+ compatible = "audio-graph-card";
+
+ dais = <&cpu_port>;
+ };
+
+ dfsdm: dfsdm@40017000 {
+ compatible = "st,stm32h7-dfsdm";
+ reg = <0x40017000 0x400>;
+ clocks = <&rcc DFSDM1_CK>;
+ clock-names = "dfsdm";
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dfsdm_adc0: filter@0 {
+ compatible = "st,stm32-dfsdm-dmic";
+ reg = <0>;
+ interrupts = <110>;
+ dmas = <&dmamux1 101 0x400 0x00>;
+ dma-names = "rx";
+ st,adc-channels = <1>;
+ st,adc-channel-names = "dmic0";
+ st,adc-channel-types = "SPI_R";
+ st,adc-channel-clk-src = "CLKOUT";
+ st,filter-order = <5>;
+
+ dfsdm_dai0: dfsdm-dai {
+ compatible = "st,stm32h7-dfsdm-dai";
+ #sound-dai-cells = <0>;
+ io-channels = <&dfsdm_adc0 0>;
+ cpu_port: port {
+ dfsdm_endpoint: endpoint {
+ remote-endpoint = <&dmic0_endpoint>;
+ };
+ };
+ };
+ };
+
+ dmic0: dmic@0 {
+ compatible = "dmic-codec";
+ #sound-dai-cells = <0>;
+ port {
+ dmic0_endpoint: endpoint {
+ remote-endpoint = <&dfsdm_endpoint>;
+ };
+ };
+ };
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v7 11/13] IIO: consumer: allow to set buffer sizes
From: Arnaud Pouliquen @ 2017-12-08 14:49 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw, Maxime Coquelin,
Alexandre Torgue, arnaud.pouliquen-qxv4g6HH51o
In-Reply-To: <1512744566-13233-1-git-send-email-arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Add iio consumer API to set buffer size and watermark according
to sysfs API.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
drivers/iio/buffer/industrialio-buffer-cb.c | 11 +++++++++++
include/linux/iio/consumer.h | 11 +++++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/iio/buffer/industrialio-buffer-cb.c b/drivers/iio/buffer/industrialio-buffer-cb.c
index 4847534..ea63c83 100644
--- a/drivers/iio/buffer/industrialio-buffer-cb.c
+++ b/drivers/iio/buffer/industrialio-buffer-cb.c
@@ -104,6 +104,17 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev,
}
EXPORT_SYMBOL_GPL(iio_channel_get_all_cb);
+int iio_channel_cb_set_buffer_watermark(struct iio_cb_buffer *cb_buff,
+ size_t watermark)
+{
+ if (!watermark)
+ return -EINVAL;
+ cb_buff->buffer.watermark = watermark;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(iio_channel_cb_set_buffer_watermark);
+
int iio_channel_start_all_cb(struct iio_cb_buffer *cb_buff)
{
return iio_update_buffers(cb_buff->indio_dev, &cb_buff->buffer,
diff --git a/include/linux/iio/consumer.h b/include/linux/iio/consumer.h
index 2017f35..9887f4f 100644
--- a/include/linux/iio/consumer.h
+++ b/include/linux/iio/consumer.h
@@ -134,6 +134,17 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev,
void *private),
void *private);
/**
+ * iio_channel_cb_set_buffer_watermark() - set the buffer watermark.
+ * @cb_buffer: The callback buffer from whom we want the channel
+ * information.
+ * @watermark: buffer watermark in bytes.
+ *
+ * This function allows to configure the buffer watermark.
+ */
+int iio_channel_cb_set_buffer_watermark(struct iio_cb_buffer *cb_buffer,
+ size_t watermark);
+
+/**
* iio_channel_release_all_cb() - release and unregister the callback.
* @cb_buffer: The callback buffer that was allocated.
*/
--
2.7.4
^ permalink raw reply related
* [PATCH v7 10/13] IIO: ADC: add stm32 DFSDM support for PDM microphone
From: Arnaud Pouliquen @ 2017-12-08 14:49 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw, Maxime Coquelin,
Alexandre Torgue, arnaud.pouliquen-qxv4g6HH51o
In-Reply-To: <1512744566-13233-1-git-send-email-arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
This code offers a way to handle PDM audio microphones in
ASOC framework. Audio driver should use consumer API.
A specific management is implemented for DMA, with a
callback, to allows to handle audio buffers efficiently.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
---
V6 to V7 updates:
- SPDX-Licensing.
- Minor typo fixes.
.../ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32 | 16 +
drivers/iio/adc/stm32-dfsdm-adc.c | 508 ++++++++++++++++++++-
include/linux/iio/adc/stm32-dfsdm-adc.h | 18 +
3 files changed, 534 insertions(+), 8 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32
create mode 100644 include/linux/iio/adc/stm32-dfsdm-adc.h
diff --git a/Documentation/ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32
new file mode 100644
index 0000000..da98223
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32
@@ -0,0 +1,16 @@
+What: /sys/bus/iio/devices/iio:deviceX/in_voltage_spi_clk_freq
+KernelVersion: 4.14
+Contact: arnaud.pouliquen-qxv4g6HH51o@public.gmane.org
+Description:
+ For audio purpose only.
+ Used by audio driver to set/get the spi input frequency.
+ This is mandatory if DFSDM is slave on SPI bus, to
+ provide information on the SPI clock frequency during runtime
+ Notice that the SPI frequency should be a multiple of sample
+ frequency to ensure the precision.
+ if DFSDM input is SPI master
+ Reading SPI clkout frequency,
+ error on writing
+ If DFSDM input is SPI Slave:
+ Reading returns value previously set.
+ Writing value before starting conversions.
\ No newline at end of file
diff --git a/drivers/iio/adc/stm32-dfsdm-adc.c b/drivers/iio/adc/stm32-dfsdm-adc.c
index 68b5920..2d6aed5 100644
--- a/drivers/iio/adc/stm32-dfsdm-adc.c
+++ b/drivers/iio/adc/stm32-dfsdm-adc.c
@@ -6,19 +6,25 @@
* Author: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>.
*/
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/iio/buffer.h>
#include <linux/iio/hw-consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
+#include <linux/iio/trigger_consumer.h>
+#include <linux/iio/triggered_buffer.h>
#include <linux/module.h>
-#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "stm32-dfsdm.h"
+#define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
+
/* Conversion timeout */
#define DFSDM_TIMEOUT_US 100000
#define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
@@ -58,6 +64,18 @@ struct stm32_dfsdm_adc {
struct completion completion;
u32 *buffer;
+ /* Audio specific */
+ unsigned int spi_freq; /* SPI bus clock frequency */
+ unsigned int sample_freq; /* Sample frequency after filter decimation */
+ int (*cb)(const void *data, size_t size, void *cb_priv);
+ void *cb_priv;
+
+ /* DMA */
+ u8 *rx_buf;
+ unsigned int bufi; /* Buffer current position */
+ unsigned int buf_sz; /* Buffer size */
+ struct dma_chan *dma_chan;
+ dma_addr_t dma_buf;
};
struct stm32_dfsdm_str2field {
@@ -351,10 +369,63 @@ int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
return 0;
}
+static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
+ uintptr_t priv,
+ const struct iio_chan_spec *chan,
+ char *buf)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+
+ return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
+}
+
+static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
+ uintptr_t priv,
+ const struct iio_chan_spec *chan,
+ const char *buf, size_t len)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
+ struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[adc->ch_id];
+ unsigned int sample_freq = adc->sample_freq;
+ unsigned int spi_freq;
+ int ret;
+
+ dev_err(&indio_dev->dev, "enter %s\n", __func__);
+ /* If DFSDM is master on SPI, SPI freq can not be updated */
+ if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
+ return -EPERM;
+
+ ret = kstrtoint(buf, 0, &spi_freq);
+ if (ret)
+ return ret;
+
+ if (!spi_freq)
+ return -EINVAL;
+
+ if (sample_freq) {
+ if (spi_freq % sample_freq)
+ dev_warn(&indio_dev->dev,
+ "Sampling rate not accurate (%d)\n",
+ spi_freq / (spi_freq / sample_freq));
+
+ ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / sample_freq));
+ if (ret < 0) {
+ dev_err(&indio_dev->dev,
+ "No filter parameters that match!\n");
+ return ret;
+ }
+ }
+ adc->spi_freq = spi_freq;
+
+ return len;
+}
+
static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc, bool dma)
{
struct regmap *regmap = adc->dfsdm->regmap;
int ret;
+ unsigned int dma_en = 0, cont_en = 0;
ret = stm32_dfsdm_start_channel(adc->dfsdm, adc->ch_id);
if (ret < 0)
@@ -365,6 +436,24 @@ static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc, bool dma)
if (ret < 0)
goto stop_channels;
+ if (dma) {
+ /* Enable DMA transfer*/
+ dma_en = DFSDM_CR1_RDMAEN(1);
+ /* Enable conversion triggered by SPI clock*/
+ cont_en = DFSDM_CR1_RCONT(1);
+ }
+ /* Enable DMA transfer*/
+ ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
+ DFSDM_CR1_RDMAEN_MASK, dma_en);
+ if (ret < 0)
+ goto stop_channels;
+
+ /* Enable conversion triggered by SPI clock*/
+ ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
+ DFSDM_CR1_RCONT_MASK, cont_en);
+ if (ret < 0)
+ goto stop_channels;
+
ret = stm32_dfsdm_start_filter(adc->dfsdm, adc->fl_id);
if (ret < 0)
goto stop_channels;
@@ -398,6 +487,231 @@ static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc)
stm32_dfsdm_stop_channel(adc->dfsdm, adc->ch_id);
}
+static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
+ unsigned int val)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
+
+ /*
+ * DMA cyclic transfers are used, buffer is split into two periods.
+ * There should be :
+ * - always one buffer (period) DMA is working on
+ * - one buffer (period) driver pushed to ASoC side.
+ */
+ watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
+ adc->buf_sz = watermark * 2;
+
+ return 0;
+}
+
+static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
+{
+ struct dma_tx_state state;
+ enum dma_status status;
+
+ status = dmaengine_tx_status(adc->dma_chan,
+ adc->dma_chan->cookie,
+ &state);
+ if (status == DMA_IN_PROGRESS) {
+ /* Residue is size in bytes from end of buffer */
+ unsigned int i = adc->buf_sz - state.residue;
+ unsigned int size;
+
+ /* Return available bytes */
+ if (i >= adc->bufi)
+ size = i - adc->bufi;
+ else
+ size = adc->buf_sz + i - adc->bufi;
+
+ return size;
+ }
+
+ return 0;
+}
+
+static void stm32_dfsdm_audio_dma_buffer_done(void *data)
+{
+ struct iio_dev *indio_dev = data;
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ int available = stm32_dfsdm_adc_dma_residue(adc);
+ size_t old_pos;
+
+ /*
+ * FIXME: In Kernel interface does not support cyclic DMA buffer,and
+ * offers only an interface to push data samples per samples.
+ * For this reason IIO buffer interface is not used and interface is
+ * bypassed using a private callback registered by ASoC.
+ * This should be a temporary solution waiting a cyclic DMA engine
+ * support in IIO.
+ */
+
+ dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__,
+ adc->bufi, available);
+ old_pos = adc->bufi;
+
+ while (available >= indio_dev->scan_bytes) {
+ u32 *buffer = (u32 *)&adc->rx_buf[adc->bufi];
+
+ /* Mask 8 LSB that contains the channel ID */
+ *buffer = (*buffer & 0xFFFFFF00) << 8;
+ available -= indio_dev->scan_bytes;
+ adc->bufi += indio_dev->scan_bytes;
+ if (adc->bufi >= adc->buf_sz) {
+ if (adc->cb)
+ adc->cb(&adc->rx_buf[old_pos],
+ adc->buf_sz - old_pos, adc->cb_priv);
+ adc->bufi = 0;
+ old_pos = 0;
+ }
+ }
+ if (adc->cb)
+ adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
+ adc->cb_priv);
+}
+
+static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ struct dma_async_tx_descriptor *desc;
+ dma_cookie_t cookie;
+ int ret;
+
+ if (!adc->dma_chan)
+ return -EINVAL;
+
+ dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
+ adc->buf_sz, adc->buf_sz / 2);
+
+ /* Prepare a DMA cyclic transaction */
+ desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
+ adc->dma_buf,
+ adc->buf_sz, adc->buf_sz / 2,
+ DMA_DEV_TO_MEM,
+ DMA_PREP_INTERRUPT);
+ if (!desc)
+ return -EBUSY;
+
+ desc->callback = stm32_dfsdm_audio_dma_buffer_done;
+ desc->callback_param = indio_dev;
+
+ cookie = dmaengine_submit(desc);
+ ret = dma_submit_error(cookie);
+ if (ret) {
+ dmaengine_terminate_all(adc->dma_chan);
+ return ret;
+ }
+
+ /* Issue pending DMA requests */
+ dma_async_issue_pending(adc->dma_chan);
+
+ return 0;
+}
+
+static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ int ret;
+
+ /* Reset adc buffer index */
+ adc->bufi = 0;
+
+ ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
+ if (ret < 0)
+ return ret;
+
+ ret = stm32_dfsdm_start_conv(adc, true);
+ if (ret) {
+ dev_err(&indio_dev->dev, "Can't start conversion\n");
+ goto stop_dfsdm;
+ }
+
+ if (adc->dma_chan) {
+ ret = stm32_dfsdm_adc_dma_start(indio_dev);
+ if (ret) {
+ dev_err(&indio_dev->dev, "Can't start DMA\n");
+ goto err_stop_conv;
+ }
+ }
+
+ return 0;
+
+err_stop_conv:
+ stm32_dfsdm_stop_conv(adc);
+stop_dfsdm:
+ stm32_dfsdm_stop_dfsdm(adc->dfsdm);
+
+ return ret;
+}
+
+static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+
+ if (adc->dma_chan)
+ dmaengine_terminate_all(adc->dma_chan);
+
+ stm32_dfsdm_stop_conv(adc);
+
+ stm32_dfsdm_stop_dfsdm(adc->dfsdm);
+
+ return 0;
+}
+
+static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
+ .postenable = &stm32_dfsdm_postenable,
+ .predisable = &stm32_dfsdm_predisable,
+};
+
+/**
+ * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
+ * DMA transfer period is achieved.
+ *
+ * @iio_dev: Handle to IIO device.
+ * @cb: Pointer to callback function:
+ * - data: pointer to data buffer
+ * - size: size in byte of the data buffer
+ * - private: pointer to consumer private structure.
+ * @private: Pointer to consumer private structure.
+ */
+int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
+ int (*cb)(const void *data, size_t size,
+ void *private),
+ void *private)
+{
+ struct stm32_dfsdm_adc *adc;
+
+ if (!iio_dev)
+ return -EINVAL;
+ adc = iio_priv(iio_dev);
+
+ adc->cb = cb;
+ adc->cb_priv = private;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
+
+/**
+ * stm32_dfsdm_release_buff_cb - unregister buffer callback
+ *
+ * @iio_dev: Handle to IIO device.
+ */
+int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
+{
+ struct stm32_dfsdm_adc *adc;
+
+ if (!iio_dev)
+ return -EINVAL;
+ adc = iio_priv(iio_dev);
+
+ adc->cb = NULL;
+ adc->cb_priv = NULL;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
+
static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, int *res)
{
@@ -453,15 +767,41 @@ static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
{
struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
+ struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[adc->ch_id];
+ unsigned int spi_freq = adc->spi_freq;
int ret = -EINVAL;
- if (mask == IIO_CHAN_INFO_OVERSAMPLING_RATIO) {
+ switch (mask) {
+ case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
ret = stm32_dfsdm_set_osrs(fl, 0, val);
if (!ret)
adc->oversamp = val;
+
+ return ret;
+
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ if (!val)
+ return -EINVAL;
+ if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
+ spi_freq = adc->dfsdm->spi_master_freq;
+
+ if (spi_freq % val)
+ dev_warn(&indio_dev->dev,
+ "Sampling rate not accurate (%d)\n",
+ spi_freq / (spi_freq / val));
+
+ ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / val));
+ if (ret < 0) {
+ dev_err(&indio_dev->dev,
+ "Not able to find parameter that match!\n");
+ return ret;
+ }
+ adc->sample_freq = val;
+
+ return 0;
}
- return ret;
+ return -EINVAL;
}
static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
@@ -494,11 +834,22 @@ static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
*val = adc->oversamp;
return IIO_VAL_INT;
+
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ *val = adc->sample_freq;
+
+ return IIO_VAL_INT;
}
return -EINVAL;
}
+static const struct iio_info stm32_dfsdm_info_audio = {
+ .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
+ .read_raw = stm32_dfsdm_read_raw,
+ .write_raw = stm32_dfsdm_write_raw,
+};
+
static const struct iio_info stm32_dfsdm_info_adc = {
.read_raw = stm32_dfsdm_read_raw,
.write_raw = stm32_dfsdm_write_raw,
@@ -531,6 +882,60 @@ static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
return IRQ_HANDLED;
}
+/*
+ * Define external info for SPI Frequency and audio sampling rate that can be
+ * configured by ASoC driver through consumer.h API
+ */
+static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
+ /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
+ {
+ .name = "spi_clk_freq",
+ .shared = IIO_SHARED_BY_TYPE,
+ .read = dfsdm_adc_audio_get_spiclk,
+ .write = dfsdm_adc_audio_set_spiclk,
+ },
+ {},
+};
+
+static int stm32_dfsdm_dma_request(struct iio_dev *indio_dev)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ struct dma_slave_config config;
+ int ret;
+
+ adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
+ if (!adc->dma_chan)
+ return -EINVAL;
+
+ adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
+ DFSDM_DMA_BUFFER_SIZE,
+ &adc->dma_buf, GFP_KERNEL);
+ if (!adc->rx_buf) {
+ ret = -ENOMEM;
+ goto err_release;
+ }
+
+ /* Configure DMA channel to read data register */
+ memset(&config, 0, sizeof(config));
+ config.src_addr = (dma_addr_t)adc->dfsdm->phys_base;
+ config.src_addr += DFSDM_RDATAR(adc->fl_id);
+ config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+
+ ret = dmaengine_slave_config(adc->dma_chan, &config);
+ if (ret)
+ goto err_free;
+
+ return 0;
+
+err_free:
+ dma_free_coherent(adc->dma_chan->device->dev, DFSDM_DMA_BUFFER_SIZE,
+ adc->rx_buf, adc->dma_buf);
+err_release:
+ dma_release_channel(adc->dma_chan);
+
+ return ret;
+}
+
static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
struct iio_chan_spec *ch)
{
@@ -551,7 +956,12 @@ static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
- ch->scan_type.sign = 'u';
+ if (adc->dev_data->type == DFSDM_AUDIO) {
+ ch->scan_type.sign = 's';
+ ch->ext_info = dfsdm_adc_audio_ext_info;
+ } else {
+ ch->scan_type.sign = 'u';
+ }
ch->scan_type.realbits = 24;
ch->scan_type.storagebits = 32;
adc->ch_id = ch->channel;
@@ -560,6 +970,64 @@ static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
&adc->dfsdm->ch_list[ch->channel]);
}
+static int stm32_dfsdm_audio_init(struct iio_dev *indio_dev)
+{
+ struct iio_chan_spec *ch;
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ struct stm32_dfsdm_channel *d_ch;
+ int ret;
+
+ ret = stm32_dfsdm_dma_request(indio_dev);
+ if (ret) {
+ dev_err(&indio_dev->dev, "DMA request failed\n");
+ return ret;
+ }
+
+ indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
+
+ ret = iio_triggered_buffer_setup(indio_dev,
+ &iio_pollfunc_store_time,
+ NULL,
+ &stm32_dfsdm_buffer_setup_ops);
+ if (ret) {
+ dev_err(&indio_dev->dev, "Buffer setup failed\n");
+ goto err_dma_disable;
+ }
+
+ ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
+ if (!ch)
+ return -ENOMEM;
+
+ ch->scan_index = 0;
+ ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev, "channels init failed\n");
+ goto err_buffer_cleanup;
+ }
+ ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
+
+ d_ch = &adc->dfsdm->ch_list[adc->ch_id];
+ if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
+ adc->spi_freq = adc->dfsdm->spi_master_freq;
+
+ indio_dev->num_channels = 1;
+ indio_dev->channels = ch;
+
+ return 0;
+
+err_buffer_cleanup:
+ iio_triggered_buffer_cleanup(indio_dev);
+
+err_dma_disable:
+ if (adc->dma_chan) {
+ dma_free_coherent(adc->dma_chan->device->dev,
+ DFSDM_DMA_BUFFER_SIZE,
+ adc->rx_buf, adc->dma_buf);
+ dma_release_channel(adc->dma_chan);
+ }
+ return ret;
+}
+
static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev)
{
struct iio_chan_spec *ch;
@@ -612,11 +1080,20 @@ static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
.init = stm32_dfsdm_adc_init,
};
+static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
+ .type = DFSDM_AUDIO,
+ .init = stm32_dfsdm_audio_init,
+};
+
static const struct of_device_id stm32_dfsdm_adc_match[] = {
{
.compatible = "st,stm32-dfsdm-adc",
.data = &stm32h7_dfsdm_adc_data,
},
+ {
+ .compatible = "st,stm32-dfsdm-dmic",
+ .data = &stm32h7_dfsdm_audio_data,
+ },
{}
};
@@ -667,8 +1144,13 @@ static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
if (!name)
return -ENOMEM;
- iio->info = &stm32_dfsdm_info_adc;
- snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
+ if (dev_data->type == DFSDM_AUDIO) {
+ iio->info = &stm32_dfsdm_info_audio;
+ snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
+ } else {
+ iio->info = &stm32_dfsdm_info_adc;
+ snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
+ }
iio->name = name;
/*
@@ -700,7 +1182,10 @@ static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
- return iio_device_register(iio);
+ iio_device_register(iio);
+ if (dev_data->type == DFSDM_AUDIO)
+ return devm_of_platform_populate(&pdev->dev);
+ return 0;
}
static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
@@ -709,7 +1194,14 @@ static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
iio_device_unregister(indio_dev);
-
+ if (indio_dev->pollfunc)
+ iio_triggered_buffer_cleanup(indio_dev);
+ if (adc->dma_chan) {
+ dma_free_coherent(adc->dma_chan->device->dev,
+ DFSDM_DMA_BUFFER_SIZE,
+ adc->rx_buf, adc->dma_buf);
+ dma_release_channel(adc->dma_chan);
+ }
return 0;
}
diff --git a/include/linux/iio/adc/stm32-dfsdm-adc.h b/include/linux/iio/adc/stm32-dfsdm-adc.h
new file mode 100644
index 0000000..e7dc7a5
--- /dev/null
+++ b/include/linux/iio/adc/stm32-dfsdm-adc.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This file discribe the STM32 DFSDM IIO driver API for audio part
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>.
+ */
+
+#ifndef STM32_DFSDM_ADC_H
+#define STM32_DFSDM_ADC_H
+
+int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
+ int (*cb)(const void *data, size_t size,
+ void *private),
+ void *private);
+int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev);
+
+#endif
--
2.7.4
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