* Re: [PATCH V7 0/7] dmaengine: qcom_hidma: add support for bugfixed HW
From: Vinod Koul @ 2017-12-12 5:38 UTC (permalink / raw)
To: Sinan Kaya
Cc: dmaengine, timur, devicetree, linux-acpi, sakari.ailus,
linux-arm-msm, linux-arm-kernel
In-Reply-To: <1512681031-11343-1-git-send-email-okaya@codeaurora.org>
On Thu, Dec 07, 2017 at 04:10:24PM -0500, Sinan Kaya wrote:
> Introduce new ACPI and OF device ids for thw HW along with the helper
> functions.
>
> Changes from v6:
> * add const to the device callback parameter in fwnode.
> * reorganize the callbacks in the code
> * rename get_match_data() as device_get_match_data()
> * place pointer checks into acpi_get_match_data()
This fails for me at 3rd patch. I am on -rc1 is there a dependency?
--
~Vinod
^ permalink raw reply
* RE: [PATCH v2 1/5] dt-bindings: rtc: add bindings for i.MX53 SRTC
From: Patrick Brünn @ 2017-12-12 5:05 UTC (permalink / raw)
To: Fabio Estevam
Cc: Rob Herring, linux-kernel-dev, Shawn Guo, Sascha Hauer,
Alessandro Zummo, Alexandre Belloni, Patrick Bruenn, Mark Rutland,
open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Fabio Estevam, Juergen Borleis, Noel Vellemans,
Russell King, ARM/FREESCALE
In-Reply-To: <CAOMZO5DoiLW3DxLF=agHua9jO-+LgWA3xw6h7kyj_uot47pkjw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 1610 bytes --]
>From: Fabio Estevam [mailto:festevam@gmail.com]
>Sent: Dienstag, 12. Dezember 2017 00:08
>Hi Patrick,
>
Hi Fabio,
>On Mon, Dec 11, 2017 at 5:08 AM, Patrick Brünn <P.Bruenn@beckhoff.com>
>wrote:
>
>>>rtc@...
>>>
>> The rtc for which this series adds support is embedded within a function
>block called
>> "Secure Real Time Clock". This driver doesn't utilize all of the hardware
>features by
>> now. But maybe someone else wants to extend the functionalities, later.
>> For that possibility I wanted to name the node "srtc". Should I still change
>this?
>>
>> I believe you have a much better understanding of what should be done
>here. I don't
>> want to argue with you, just thought you might not had that information. So
>if I am
>> wrong just tell me and I will change it without further "complaining".
>
>From the Devicetree Specification document:
>
>"Generic Names Recommendation
>
>The name of a node should be somewhat generic, reflecting the function
>of the device and not its precise program-
>ming model. If appropriate, the name should be one of the following choices:
>...
>rtc
>"
>
>So better use 'rtc' as suggested by Rob.
Thanks for this clarification. I will wait a few days for more comments on the rest of the driver and then send a v4.
Regards, Patrick
Beckhoff Automation GmbH & Co. KG | Managing Director: Dipl. Phys. Hans Beckhoff
Registered office: Verl, Germany | Register court: Guetersloh HRA 7075
N‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·zøœzÚÞz)í…æèw*\x1fjg¬±¨\x1e¶‰šŽŠÝ¢j.ïÛ°\½½MŽúgjÌæa×\x02››–' ™©Þ¢¸\f¢·¦j:+v‰¨ŠwèjØm¶Ÿÿ¾\a«‘êçzZ+ƒùšŽŠÝ¢j"ú!¶i
^ permalink raw reply
* Re: [alsa-devel] [PATCH 5/8] ASoC: uniphier: add support for UniPhier AIO driver
From: Katsuhiro Suzuki @ 2017-12-12 4:33 UTC (permalink / raw)
To: 'Vinod Koul', Mark Brown
Cc: devicetree, alsa-devel, Masami Hiramatsu,
Yamada, Masahiro/山田 真弘, linux-kernel,
Jassi Brar, Rob Herring, linux-arm-kernel
In-Reply-To: <20171211174854.GZ18649@localhost>
Hello Vinod, Mark,
> -----Original Message-----
> From: Vinod Koul [mailto:vinod.koul@intel.com]
> Sent: Tuesday, December 12, 2017 2:49 AM
> To: Mark Brown <broonie@kernel.org>
> Cc: Suzuki, Katsuhiro/鈴木 勝博 <suzuki.katsuhiro@socionext.com>;
> devicetree@vger.kernel.org; alsa-devel@alsa-project.org; Masami Hiramatsu
> <masami.hiramatsu@linaro.org>; Yamada, Masahiro/山田 真弘
> <yamada.masahiro@socionext.com>; linux-kernel@vger.kernel.org; Jassi Brar
> <jaswinder.singh@linaro.org>; Rob Herring <robh+dt@kernel.org>;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: [alsa-devel] [PATCH 5/8] ASoC: uniphier: add support for UniPhier
> AIO driver
>
> On Mon, Dec 11, 2017 at 03:16:29PM +0000, Mark Brown wrote:
> > On Mon, Dec 11, 2017 at 06:21:58PM +0900, Katsuhiro Suzuki wrote:
> >
> > > But I can't find how to use/map this DAI in machine driver or Device-Tree
or
> > > something. I think that it's same as PCM DAI, am I correct?
> >
> > Yes, that probably makes sense from a binding point of view.
> >
> > > I read compress-offload.rst, but I can't find how do I test it. It seems
aplay
> > > of
> > > alsa-util doesn't know compress audio formats. Should I use PulseAudio or
> > > Android HAL to test compress audio APIs?
> >
> > IIRC tinyalsa has a compressed API test application - Vinod?
>
> I guess it was sheer luck that i saw this :) email in CC reads
> vinod.koul@linaro.org! I don't work for Linaro, not yet :D
>
> And to the answer the question, Yes we have compressed API test application
> in tinycompress which is located at git.alsa-project.org:tinycompress.git
>
> We have both compressed audio playback as well as record test app, cplay and
> crecord.
>
Ah, I didn't check tinyalsa, thanks a lot!
I'll try it.
Regards,
--
Katsuhiro Suzuki
> HTH
> --
> ~Vinod
^ permalink raw reply
* [PATCH 2/2] usb: host: xhci-plat: enable XHCI_MISSING_CAS if platform requested
From: Li Jun @ 2017-12-12 3:57 UTC (permalink / raw)
To: mathias.nyman-ral2JQCrhuEAvxtiuMwx3w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: linux-usb-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Li Jun
In-Reply-To: <1513051038-20311-1-git-send-email-jun.li-3arQi8VN3Tc@public.gmane.org>
In case there is CAS missing if device plugged in S3, we can use
'usb3-resume-missing-cas' device property to enable quirk flag
XHCI_MISSING_CAS.
Signed-off-by: Li Jun <jun.li-3arQi8VN3Tc@public.gmane.org>
---
drivers/usb/host/xhci-plat.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 6f03830..4ec711c 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -269,6 +269,9 @@ static int xhci_plat_probe(struct platform_device *pdev)
if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
xhci->quirks |= XHCI_BROKEN_PORT_PED;
+ if (device_property_read_bool(sysdev, "usb3-resume-missing-cas"))
+ xhci->quirks |= XHCI_MISSING_CAS;
+
/* imod_interval is the interrupt moderation value in nanoseconds. */
xhci->imod_interval = 40000;
device_property_read_u32(sysdev, "imod-interval-ns",
--
2.6.6
--
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^ permalink raw reply related
* [PATCH 1/2] dt-bindings: usb-xhci: add usb3-resume-missing-cas property
From: Li Jun @ 2017-12-12 3:57 UTC (permalink / raw)
To: mathias.nyman-ral2JQCrhuEAvxtiuMwx3w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: linux-usb-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Li Jun
Adding 'usb3-resume-missing-cas' property to enable XHCI_MISSING_CAS
quirk flag in case there is CAS missing if device plugged in S3.
Signed-off-by: Li Jun <jun.li-3arQi8VN3Tc@public.gmane.org>
---
Documentation/devicetree/bindings/usb/usb-xhci.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
index e2ea59b..c413e188 100644
--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
@@ -32,6 +32,8 @@ Optional properties:
- usb3-lpm-capable: determines if platform is USB3 LPM capable
- quirk-broken-port-ped: set if the controller has broken port disable mechanism
- imod-interval-ns: default interrupt moderation interval is 5000ns
+ - usb3-resume-missing-cas: set if the CAS(Cold Attach Status) may lose in case
+ usb3 device plugged in while system sleep.
Example:
usb@f0931000 {
--
2.6.6
--
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^ permalink raw reply related
* Re: [PATCH v2 2/2] drm/tinydrm: add driver for ST7735R panels
From: David Lechner @ 2017-12-12 2:55 UTC (permalink / raw)
To: Noralf Trønnes, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: limor-6aDhHjTmHzzR7s880joybQ, Linus Walleij, Rob Herring,
Mark Rutland, linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1d6124f3-613f-45b4-1862-aad7453239e6-L59+Z2yzLopAfugRpC6u6w@public.gmane.org>
On 12/11/2017 03:18 PM, Noralf Trønnes wrote:
>
> Den 10.12.2017 23.10, skrev David Lechner:
>> This adds a new driver for Sitronix ST7735R display panels.
>>
>> This has been tested using an Adafruit 1.8" TFT.
>>
>> Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
>> ---
>
>> +static void st7735r_pipe_enable(struct drm_simple_display_pipe *pipe,
>> + struct drm_crtc_state *crtc_state)
>> +{
>> + struct tinydrm_device *tdev = pipe_to_tinydrm(pipe);
>> + struct mipi_dbi *mipi = mipi_dbi_from_tinydrm(tdev);
>> + struct device *dev = tdev->drm->dev;
>> + int ret;
>> + u8 addr_mode;
>> +
>> + DRM_DEBUG_KMS("\n");
>> +
>> + mipi_dbi_hw_reset(mipi);
>> +
>> + ret = mipi_dbi_command(mipi, MIPI_DCS_SOFT_RESET);
>> + if (ret) {
>> + DRM_DEV_ERROR(dev, "Error sending command %d\n", ret);
>> + return;
>> + }
>> +
>> + msleep(150);
>> +
>> + mipi_dbi_command(mipi, MIPI_DCS_EXIT_SLEEP_MODE);
>> + msleep(500);
>> +
>> + mipi_dbi_command(mipi, ST7735R_FRMCTR1, 0x01, 0x2c, 0x2d);
>> + mipi_dbi_command(mipi, ST7735R_FRMCTR2, 0x01, 0x2c, 0x2d);
>> + mipi_dbi_command(mipi, ST7735R_FRMCTR3, 0x01, 0x2c, 0x2d, 0x01,
>> 0x2c,
>> + 0x2d);
>> + mipi_dbi_command(mipi, ST7735R_INVCTR, 0x07);
>> + mipi_dbi_command(mipi, ST7735R_PWCTR1, 0xa2, 0x02, 0x84);
>> + mipi_dbi_command(mipi, ST7735R_PWCTR2, 0xc5);
>> + mipi_dbi_command(mipi, ST7735R_PWCTR3, 0x0a, 0x00);
>> + mipi_dbi_command(mipi, ST7735R_PWCTR4, 0x8a, 0x2a);
>> + mipi_dbi_command(mipi, ST7735R_PWCTR5, 0x8a, 0xee);
>> + mipi_dbi_command(mipi, ST7735R_VMCTR1, 0x0e);
>> + mipi_dbi_command(mipi, MIPI_DCS_EXIT_INVERT_MODE);
>> + switch (mipi->rotation) {
>> + default:
>> + addr_mode = ST7735R_MX | ST7735R_MY;
>> + break;
>> + case 90:
>> + addr_mode = ST7735R_MX | ST7735R_MV;
>> + break;
>> + case 180:
>> + addr_mode = 0;
>> + break;
>> + case 270:
>> + addr_mode = ST7735R_MY | ST7735R_MV;
>> + break;
>> + }
>> + mipi_dbi_command(mipi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
>> + mipi_dbi_command(mipi, MIPI_DCS_SET_PIXEL_FORMAT,
>> + MIPI_DCS_PIXEL_FMT_16BIT);
>> + mipi_dbi_command(mipi, ST7735R_GAMCTRP1, 0x0f, 0x1a, 0x0f, 0x18,
>> 0x2f,
>> + 0x28, 0x20, 0x22, 0x1f, 0x1b, 0x23, 0x37, 0x00, 0x07,
>> + 0x02, 0x10);
>> + mipi_dbi_command(mipi, ST7735R_GAMCTRN1, 0x0f, 0x1b, 0x0f, 0x17,
>> 0x33,
>> + 0x2c, 0x29, 0x2e, 0x30, 0x30, 0x39, 0x3f, 0x00, 0x07,
>> + 0x03, 0x10);
>> + mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_ON);
>> +
>> + msleep(100);
>> +
>> + mipi_dbi_command(mipi, MIPI_DCS_ENTER_NORMAL_MODE);
>> +
>> + msleep(20);
>> +
>> + mipi_dbi_pipe_enable(pipe, crtc_state);
>> +}
>> +
>> +static const struct drm_simple_display_pipe_funcs st7735r_pipe_funcs = {
>> + .enable = st7735r_pipe_enable,
>> + .disable = mipi_dbi_pipe_disable,
>> + .update = tinydrm_display_pipe_update,
>> + .prepare_fb = tinydrm_display_pipe_prepare_fb,
>> +};
>> +
>> +static const struct drm_display_mode st7735r_mode = {
>> + TINYDRM_MODE(128, 160, 28, 35),
>> +};
>
> This naming talk has made me realise that these should be named after
> the panel since they're not generic controller functions.
> Maybe the mode can be generic, not sure if the physical size can/will
> differ, the resolution is very likely to be the same for all.
Adafruit has a 1.44" 128x128px display [1] with the same controller, so
the answer is no, the mode cannot be generic.
[1]: https://www.adafruit.com/product/2088
>
> What's your view on my descision to split the MIPI DBI compatible
> controllers into per controller drivers instead of having one driver
> that supports them all?
My first impression was that I didn't like it so much. But now, I
actually think that it is a good idea. I think it is a good compromise
between some boilerplate code in every driver and a driver with so many
quirks that it is very difficult to work on. It may make sense to
combine some very similar controllers, but as a rule of thumb, I think
one driver per controller will work nicely.
> I've been afraid that it will be a very big file with macro definitions
> per controller and enable functions per panel.
>
> This driver has 15 macros and ~80 panel specific lines.
> With one panel supported, half the driver is boilerplate.
> The mi0283qt panel (MIPI DBI compatible) is in the same ballpark.
>
> Adding helpers for panel reset/exit_sleep, for MIPI_DCS_SET_ADDRESS_MODE
> and for display_on/enter_normal/flush could cut it down some more if we
> made one driver to rule them all. Maybe the enable function per panel
> could be cut in half that way.
>
> I'm starting to wonder if one driver isn't such a bad solution after all...
I think as we add more drivers, the parts that get duplicated will
become obvious candidates for helper functions to refactor, but I don't
think trying to cram everything all into one driver is such a good idea.
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^ permalink raw reply
* Re: [PATCH net-next v5 2/2] net: ethernet: socionext: add AVE ethernet driver
From: Masami Hiramatsu @ 2017-12-12 2:29 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Kunihiko Hayashi, Mark Rutland, Andrew Lunn, Florian Fainelli,
devicetree-u79uwXL29TY76Z2rM5mHXA, netdev-u79uwXL29TY76Z2rM5mHXA,
Linux kernel mailing list, Masahiro Yamada, Rob Herring,
Philippe Ombredanne, Jassi Brar, David S. Miller,
linux-arm-kernel
In-Reply-To: <20171211134627.GU10595-l+eeeJia6m9URfEZ8mYm6t73F7V6hmMc@public.gmane.org>
Hi Russell,
2017-12-11 22:46 GMT+09:00 Russell King - ARM Linux <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>:
> On Mon, Dec 11, 2017 at 10:34:17PM +0900, Masami Hiramatsu wrote:
>> IMHO, even if we use SPDX license identifier, I recommend to use
>> C-style comments as many other files do, since it is C code.
>> If SPDX identifier requires C++ style, that is SPDX parser's issue
>> and should be fixed to get it from C-style comment.
>
> See the numerous emails on this subject already. The issue of C
> vs C++ comments has come up many times by many different people, but
> the result is the same. That's not going to happen. Linux kernel
> C files are required to use "//" for the SPDX identifier by order
> of Linus Torvalds.
OK, I got it.
>
> Linus has also revealed in that discussion that he has a preference
> for "//" style commenting for single comments, so it seems that the
> kernel coding style may change - but there is no desire for patches
> to "clean up" single line comments to use "//".
Thank you for making it clear.
Then what I'm considering is copyright notice lines. Those are usually
treat as the header lines, not single line. So
> +// SDPX-License-Identifier: GPL-2.0
> +// sni_ave.c - Socionext UniPhier AVE ethernet driver
> +// Copyright 2014 Panasonic Corporation
> +// Copyright 2015-2017 Socionext Inc.
is acceptable? or should we keep C-style header lines for new drivers?
> +// SDPX-License-Identifier: GPL-2.0
> +/*
> + * sni_ave.c - Socionext UniPhier AVE ethernet driver
> + * Copyright 2014 Panasonic Corporation
> + * Copyright 2015-2017 Socionext Inc.
> + */
I just concern that those lines are not "single". that's all. :)
>
> For further information, and to see the discussion that has already
> happened, the arguments that have been made about style, see the
> threads for the patch series that tglx has been posting wrt documenting
> the SPDX stuff for the kernel.
OK, got it.
https://lkml.org/lkml/2017/11/16/663
Thanks,
>
> Thanks (let's stop rehashing the same arguments.)
>
--
Masami Hiramatsu
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^ permalink raw reply
* Re: [PATCH v3 17/33] nds32: VDSO support
From: Vincent Chen @ 2017-12-12 1:58 UTC (permalink / raw)
To: Mark Rutland
Cc: Greentime Hu, Greentime, Linux Kernel Mailing List, Arnd Bergmann,
linux-arch, Thomas Gleixner, Jason Cooper, Marc Zyngier,
Rob Herring, netdev, DTML, Al Viro, David Howells, Will Deacon,
Daniel Lezcano, linux-serial, Geert Uytterhoeven, Linus Walleij,
Greg KH, Vincent Chen
In-Reply-To: <20171208121405.dy6raczdlbxtbnfo@lakrids.cambridge.arm.com>
2017-12-08 20:14 GMT+08:00 Mark Rutland <mark.rutland@arm.com>:
> On Fri, Dec 08, 2017 at 07:54:42PM +0800, Greentime Hu wrote:
>> 2017-12-08 18:21 GMT+08:00 Mark Rutland <mark.rutland@arm.com>:
>> > On Fri, Dec 08, 2017 at 05:12:00PM +0800, Greentime Hu wrote:
>> >> +static int grab_timer_node_info(void)
>> >> +{
>> >> + struct device_node *timer_node;
>> >> +
>> >> + timer_node = of_find_node_by_name(NULL, "timer");
>> >
>> > Please use a compatible string, rather than matching the timer by name.
>> >
>> > It's plausible that you have multiple nodes called "timer" in the DT,
>> > under different parent nodes, and this might not be the device you
>> > think it is. I see your dt in patch 24 has two timer nodes.
>> >
>> > It would be best if your clocksource driver exposed some stuct that you
>> > looked at here, so that you're guaranteed to user the same device.
>>
>> We'd like to use "timer" here because there are 2 different timer IPs
>> and we are sure that they won't be in the same SoC.
>> We think this implementation in VDSO should be platform independent to
>> get cycle-count register.
>> Our customer or other SoC provider who can use "timer" and define
>> cycle-count-offset or cycle-count-down then we can get the correct
>> cycle-count.
>
> This is not the right way to do things.
>
> So from a DT perspective, NAK.
>
> You should not add properties to arbitrary DT bindings to handle a Linux
> implementation detail.
>
> Please remove this DT code, and have the drivers for those timer blocks
> export this information to your vdso code somehow.
>
Hi, Mark:
Based on your suggestion, we define a new sturct timer_info to let
timer driver record the value
of cycle-count-offset and cycle-count-down in timer_init function. The
above code in timer driver
is validate only when CONFIG_NDS32 is defined.
>> We sent atcpit100 patch last time along with our arch, however we'd
>> like to send it to its sub system this time and my colleague is still
>> working on it.
>> He may send the timer patch next week.
>
> I think that it would make sense for that patch to be part of the arch
> port, especially given that (AFAICT) there is no dirver for the other
> timer IP that you mention.
>
> [...]
>
>> >> +int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
>> >> +{
>> >
>> >> + /*Map timer to user space */
>> >> + vdso_base += PAGE_SIZE;
>> >> + prot = __pgprot(_PAGE_V | _PAGE_M_UR_KR | _PAGE_D |
>> >> + _PAGE_G | _PAGE_C_DEV);
>> >> + ret = io_remap_pfn_range(vma, vdso_base, timer_res.start >> PAGE_SHIFT,
>> >> + PAGE_SIZE, prot);
>> >> + if (ret)
>> >> + goto up_fail;
>> >
>> > Maybe this is fine, but it looks a bit suspicious.
>> >
>> > Is it safe to map IO memory to a userspace process like this?
>> >
>> > In general that isn't safe, since userspace could access other registers
>> > (if those exist), perform accesses that change the state of hardware, or
>> > make unsupported access types (e.g. unaligned, atomic) that result in
>> > errors the kernel can't handle.
>> >
>> > Does none of that apply here?
>>
>> We only provide read permission to this page so hareware state won't
>> be chagned. It will trigger exception if we try to write.
>> We will check about the alignment/atomic issue of this region.
>
For alignment issue, we intentionally make an un-alignment read to
access this region and we
got "Segmentation fault" as expected.
Thanks,
Vincent
> Ok, thanks.
>
> This is another reason to only do this for devices/drivers that we have
> drivers for, since we can't know that this is safe in general.
>
> Thanks,
> Mark.
^ permalink raw reply
* Re: [PATCH v1 4/4] arm64: dts: mediatek: add mt2712 cpufreq related device nodes
From: Rafael J. Wysocki @ 2017-12-12 1:17 UTC (permalink / raw)
To: Viresh Kumar, Andrew-sh Cheng
Cc: matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w, mark.rutland-5wv7dgnIgG8,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171211075719.GD25177@vireshk-i7>
On Monday, December 11, 2017 8:57:19 AM CET Viresh Kumar wrote:
> On 08-12-17, 14:07, Andrew-sh Cheng wrote:
> > Add opp v2 information,
> > and also add clocks, regulators and opp information into cpu nodes
> >
> > Signed-off-by: Andrew-sh Cheng <andrew-sh.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> > arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 27 ++++++++++++++
> > arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 57 +++++++++++++++++++++++++++++
> > 2 files changed, 84 insertions(+)
>
> Acked-by: Viresh Kumar <viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Of course, DT bindings require ACKs from DT maintainers to be applied.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply
* RE: [PATCH] arm: dts: uniphier: add efuse node for UniPhier 32bit SoC
From: Keiji Hayashibara @ 2017-12-12 0:56 UTC (permalink / raw)
To: 'Masahiro Yamada'
Cc: Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel,
Linux Kernel Mailing List, Masami Hiramatsu, Jassi Brar,
Hayashi, Kunihiko/林 邦彦,
Owada, Kiyoshi/大和田 清志
In-Reply-To: <CAK7LNARmYfnYpACrUtYccBPyjnvXg0ymA=WZ=+nGAtanaXZk1w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hello Yamada-san,
Sorry, I will be careful next time.
I was checking with the command of
"get_maintainer.pl -f arch/arm/boot/dts/".
Thank you.
Best Regards,
Keiji Hayashibara
> From: Masahiro Yamada [mailto:yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org]
> Sent: Tuesday, December 12, 2017 1:06 AM
>
> 2017-12-04 17:12 GMT+09:00 Keiji Hayashibara <hayashibara.keiji-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>:
> > Add efuse node for UniPhier LD4, Pro4, sLD8, Pro5 and PXs2.
> > This efuse node is included in soc-glue.
> >
> > Signed-off-by: Keiji Hayashibara <hayashibara.keiji-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
> > ---
> > arch/arm/boot/dts/uniphier-ld4.dtsi | 18 ++++++++++++++++++
> > arch/arm/boot/dts/uniphier-pro4.dtsi | 23 +++++++++++++++++++++++
> > arch/arm/boot/dts/uniphier-pro5.dtsi | 33
> > +++++++++++++++++++++++++++++++++
> > arch/arm/boot/dts/uniphier-pxs2.dtsi | 18 ++++++++++++++++++
> > arch/arm/boot/dts/uniphier-sld8.dtsi | 18 ++++++++++++++++++
> > 5 files changed, 110 insertions(+)
>
>
> Applied to linux-uniphier,
> but please reconsider To: list next time.
>
> This patch was addressed to Rob and Mark, but they do not pick up platform DT patches.
>
>
> You do not need to get Rob's Ack for a patch like this.
>
>
> Binding is a contract between operation system and DT.
>
> The binding for this
> (Documentation/devicetree/bindings/nvmem/uniphier-efuse.txt)
> was approved by Rob and merged in the mainline.
>
> Given that this patch follows the binding correctly, it should be safe.
>
> Thanks.
>
>
>
> > diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi
> > b/arch/arm/boot/dts/uniphier-ld4.dtsi
> > index 01fc3e1..6883f3b 100644
> > --- a/arch/arm/boot/dts/uniphier-ld4.dtsi
> > +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
> > @@ -273,6 +273,24 @@
> > };
> > };
> >
> > + soc-glue@5f900000 {
> > + compatible = "socionext,uniphier-ld4-soc-glue-debug",
> > + "simple-mfd";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0x5f900000 0x2000>;
> > +
> > + efuse@100 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x100 0x28>;
> > + };
> > +
> > + efuse@130 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x130 0x8>;
> > + };
> > + };
> > +
> > timer@60000200 {
> > compatible = "arm,cortex-a9-global-timer";
> > reg = <0x60000200 0x20>; diff --git
> > a/arch/arm/boot/dts/uniphier-pro4.dtsi
> > b/arch/arm/boot/dts/uniphier-pro4.dtsi
> > index 7955c3a..150726b 100644
> > --- a/arch/arm/boot/dts/uniphier-pro4.dtsi
> > +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
> > @@ -294,6 +294,29 @@
> > };
> > };
> >
> > + soc-glue@5f900000 {
> > + compatible = "socionext,uniphier-pro4-soc-glue-debug",
> > + "simple-mfd";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0x5f900000 0x2000>;
> > +
> > + efuse@100 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x100 0x28>;
> > + };
> > +
> > + efuse@130 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x130 0x8>;
> > + };
> > +
> > + efuse@200 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x200 0x14>;
> > + };
> > + };
> > +
> > aidet: aidet@5fc20000 {
> > compatible = "socionext,uniphier-pro4-aidet";
> > reg = <0x5fc20000 0x200>; diff --git
> > a/arch/arm/boot/dts/uniphier-pro5.dtsi
> > b/arch/arm/boot/dts/uniphier-pro5.dtsi
> > index 6589b8a..f291dd6 100644
> > --- a/arch/arm/boot/dts/uniphier-pro5.dtsi
> > +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
> > @@ -355,6 +355,39 @@
> > };
> > };
> >
> > + soc-glue@5f900000 {
> > + compatible = "socionext,uniphier-pro5-soc-glue-debug",
> > + "simple-mfd";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0x5f900000 0x2000>;
> > +
> > + efuse@100 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x100 0x28>;
> > + };
> > +
> > + efuse@130 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x130 0x8>;
> > + };
> > +
> > + efuse@200 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x200 0x28>;
> > + };
> > +
> > + efuse@300 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x300 0x14>;
> > + };
> > +
> > + efuse@400 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x400 0x8>;
> > + };
> > + };
> > +
> > aidet: aidet@5fc20000 {
> > compatible = "socionext,uniphier-pro5-aidet";
> > reg = <0x5fc20000 0x200>; diff --git
> > a/arch/arm/boot/dts/uniphier-pxs2.dtsi
> > b/arch/arm/boot/dts/uniphier-pxs2.dtsi
> > index d82d6d8..8e54e87 100644
> > --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
> > +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
> > @@ -375,6 +375,24 @@
> > };
> > };
> >
> > + soc-glue@5f900000 {
> > + compatible = "socionext,uniphier-pxs2-soc-glue-debug",
> > + "simple-mfd";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0x5f900000 0x2000>;
> > +
> > + efuse@100 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x100 0x28>;
> > + };
> > +
> > + efuse@200 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x200 0x58>;
> > + };
> > + };
> > +
> > aidet: aidet@5fc20000 {
> > compatible = "socionext,uniphier-pxs2-aidet";
> > reg = <0x5fc20000 0x200>; diff --git
> > a/arch/arm/boot/dts/uniphier-sld8.dtsi
> > b/arch/arm/boot/dts/uniphier-sld8.dtsi
> > index 7188536..afafe7c 100644
> > --- a/arch/arm/boot/dts/uniphier-sld8.dtsi
> > +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
> > @@ -277,6 +277,24 @@
> > };
> > };
> >
> > + soc-glue@5f900000 {
> > + compatible = "socionext,uniphier-sld8-soc-glue-debug",
> > + "simple-mfd";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0x5f900000 0x2000>;
> > +
> > + efuse@100 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x100 0x28>;
> > + };
> > +
> > + efuse@200 {
> > + compatible = "socionext,uniphier-efuse";
> > + reg = <0x200 0x14>;
> > + };
> > + };
> > +
> > timer@60000200 {
> > compatible = "arm,cortex-a9-global-timer";
> > reg = <0x60000200 0x20>;
> > --
> > 2.7.4
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe devicetree"
> > in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo
> > info at http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> Best Regards
> Masahiro Yamada
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply
* [PATCH v5 4/4] ARM: dts: tegra20: Add video decoder node
From: Dmitry Osipenko @ 2017-12-12 0:26 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Stephen Warren,
Greg Kroah-Hartman, Mauro Carvalho Chehab, Hans Verkuil,
Vladimir Zapolskiy
Cc: devel, devicetree, linux-kernel, Rob Herring, linux-tegra,
Dan Carpenter, linux-media
In-Reply-To: <cover.1513038011.git.digetx@gmail.com>
Add Video Decoder Engine device node.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra20.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 36909df653c3..864a95872b8d 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -16,6 +16,11 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40000000 0x40000>;
+
+ vde_pool: vde {
+ reg = <0x400 0x3fc00>;
+ pool;
+ };
};
host1x@50000000 {
@@ -258,6 +263,28 @@
*/
};
+ vde@6001a000 {
+ compatible = "nvidia,tegra20-vde";
+ reg = <0x6001a000 0x1000 /* Syntax Engine */
+ 0x6001b000 0x1000 /* Video Bitstream Engine */
+ 0x6001c000 0x100 /* Macroblock Engine */
+ 0x6001c200 0x100 /* Post-processing Engine */
+ 0x6001c400 0x100 /* Motion Compensation Engine */
+ 0x6001c600 0x100 /* Transform Engine */
+ 0x6001c800 0x100 /* Pixel prediction block */
+ 0x6001ca00 0x100 /* Video DMA */
+ 0x6001d800 0x300>; /* Video frame controls */
+ reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
+ "tfe", "ppb", "vdma", "frameid";
+ iram = <&vde_pool>; /* IRAM region */
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
+ interrupt-names = "sync-token", "bsev", "sxe";
+ clocks = <&tegra_car TEGRA20_CLK_VDE>;
+ resets = <&tegra_car 61>;
+ };
+
apbmisc@70000800 {
compatible = "nvidia,tegra20-apbmisc";
reg = <0x70000800 0x64 /* Chip revision */
--
2.15.1
^ permalink raw reply related
* [PATCH v5 3/4] ARM: dts: tegra20: Add device tree node to describe IRAM
From: Dmitry Osipenko @ 2017-12-12 0:26 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Stephen Warren,
Greg Kroah-Hartman, Mauro Carvalho Chehab, Hans Verkuil,
Vladimir Zapolskiy
Cc: devel, devicetree, linux-kernel, Rob Herring, linux-tegra,
Dan Carpenter, linux-media
In-Reply-To: <cover.1513038011.git.digetx@gmail.com>
From: Vladimir Zapolskiy <vz@mleia.com>
All Tegra20 SoCs contain 256KiB IRAM, which is used to store
resume code and by a video decoder engine.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra20.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 914f59166a99..36909df653c3 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -10,6 +10,14 @@
compatible = "nvidia,tegra20";
interrupt-parent = <&lic>;
+ iram@40000000 {
+ compatible = "mmio-sram";
+ reg = <0x40000000 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x40000000 0x40000>;
+ };
+
host1x@50000000 {
compatible = "nvidia,tegra20-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
--
2.15.1
^ permalink raw reply related
* [PATCH v5 2/4] staging: media: Introduce NVIDIA Tegra video decoder driver
From: Dmitry Osipenko @ 2017-12-12 0:26 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Stephen Warren,
Greg Kroah-Hartman, Mauro Carvalho Chehab, Hans Verkuil,
Vladimir Zapolskiy
Cc: Rob Herring, Dan Carpenter, linux-media, devel, devicetree,
linux-tegra, linux-kernel
In-Reply-To: <cover.1513038011.git.digetx@gmail.com>
NVIDIA Tegra20/30/114/124/132 SoC's have video decoder engine that
supports standard set of video formats like H.264 / MPEG-4 / WMV / VC1.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
MAINTAINERS | 9 +
drivers/staging/media/Kconfig | 2 +
drivers/staging/media/Makefile | 1 +
drivers/staging/media/tegra-vde/Kconfig | 7 +
drivers/staging/media/tegra-vde/Makefile | 1 +
drivers/staging/media/tegra-vde/TODO | 4 +
drivers/staging/media/tegra-vde/tegra-vde.c | 1213 +++++++++++++++++++++++++++
drivers/staging/media/tegra-vde/uapi.h | 78 ++
8 files changed, 1315 insertions(+)
create mode 100644 drivers/staging/media/tegra-vde/Kconfig
create mode 100644 drivers/staging/media/tegra-vde/Makefile
create mode 100644 drivers/staging/media/tegra-vde/TODO
create mode 100644 drivers/staging/media/tegra-vde/tegra-vde.c
create mode 100644 drivers/staging/media/tegra-vde/uapi.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 7d195739f892..7f7c24949a06 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8706,6 +8706,15 @@ T: git git://linuxtv.org/media_tree.git
S: Maintained
F: drivers/media/dvb-frontends/stv6111*
+MEDIA DRIVERS FOR NVIDIA TEGRA - VDE
+M: Dmitry Osipenko <digetx@gmail.com>
+L: linux-media@vger.kernel.org
+L: linux-tegra@vger.kernel.org
+T: git git://linuxtv.org/media_tree.git
+S: Maintained
+F: Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
+F: drivers/staging/media/tegra-vde/
+
MEDIA INPUT INFRASTRUCTURE (V4L/DVB)
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
M: Mauro Carvalho Chehab <mchehab@kernel.org>
diff --git a/drivers/staging/media/Kconfig b/drivers/staging/media/Kconfig
index 3a09140700e6..227437f22acf 100644
--- a/drivers/staging/media/Kconfig
+++ b/drivers/staging/media/Kconfig
@@ -31,4 +31,6 @@ source "drivers/staging/media/imx/Kconfig"
source "drivers/staging/media/omap4iss/Kconfig"
+source "drivers/staging/media/tegra-vde/Kconfig"
+
endif
diff --git a/drivers/staging/media/Makefile b/drivers/staging/media/Makefile
index f25327163c67..59a47f69884f 100644
--- a/drivers/staging/media/Makefile
+++ b/drivers/staging/media/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx/
obj-$(CONFIG_VIDEO_DM365_VPFE) += davinci_vpfe/
obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/
obj-$(CONFIG_INTEL_ATOMISP) += atomisp/
+obj-$(CONFIG_TEGRA_VDE) += tegra-vde/
diff --git a/drivers/staging/media/tegra-vde/Kconfig b/drivers/staging/media/tegra-vde/Kconfig
new file mode 100644
index 000000000000..ec3ddddebdaa
--- /dev/null
+++ b/drivers/staging/media/tegra-vde/Kconfig
@@ -0,0 +1,7 @@
+config TEGRA_VDE
+ tristate "NVIDIA Tegra Video Decoder Engine driver"
+ depends on ARCH_TEGRA || COMPILE_TEST
+ select SRAM
+ help
+ Say Y here to enable support for the NVIDIA Tegra video decoder
+ driver.
diff --git a/drivers/staging/media/tegra-vde/Makefile b/drivers/staging/media/tegra-vde/Makefile
new file mode 100644
index 000000000000..444c1d62daa1
--- /dev/null
+++ b/drivers/staging/media/tegra-vde/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_TEGRA_VDE) += tegra-vde.o
diff --git a/drivers/staging/media/tegra-vde/TODO b/drivers/staging/media/tegra-vde/TODO
new file mode 100644
index 000000000000..31aaa3e66d80
--- /dev/null
+++ b/drivers/staging/media/tegra-vde/TODO
@@ -0,0 +1,4 @@
+TODO:
+ - Implement V4L2 API once it gains support for stateless decoders.
+
+Contact: Dmitry Osipenko <digetx@gmail.com>
diff --git a/drivers/staging/media/tegra-vde/tegra-vde.c b/drivers/staging/media/tegra-vde/tegra-vde.c
new file mode 100644
index 000000000000..c47659e96089
--- /dev/null
+++ b/drivers/staging/media/tegra-vde/tegra-vde.c
@@ -0,0 +1,1213 @@
+/*
+ * NVIDIA Tegra Video decoder driver
+ *
+ * Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/dma-buf.h>
+#include <linux/genalloc.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+#include <soc/tegra/pmc.h>
+
+#include "uapi.h"
+
+#define ICMDQUE_WR 0x00
+#define CMDQUE_CONTROL 0x08
+#define INTR_STATUS 0x18
+#define BSE_INT_ENB 0x40
+#define BSE_CONFIG 0x44
+
+#define BSE_ICMDQUE_EMPTY BIT(3)
+#define BSE_DMA_BUSY BIT(23)
+
+#define VDE_WR(__data, __addr) \
+do { \
+ dev_dbg(vde->miscdev.parent, \
+ "%s: %d: 0x%08X => " #__addr ")\n", \
+ __func__, __LINE__, (u32)(__data)); \
+ writel_relaxed(__data, __addr); \
+} while (0)
+
+struct video_frame {
+ struct dma_buf_attachment *y_dmabuf_attachment;
+ struct dma_buf_attachment *cb_dmabuf_attachment;
+ struct dma_buf_attachment *cr_dmabuf_attachment;
+ struct dma_buf_attachment *aux_dmabuf_attachment;
+ struct sg_table *y_sgt;
+ struct sg_table *cb_sgt;
+ struct sg_table *cr_sgt;
+ struct sg_table *aux_sgt;
+ dma_addr_t y_addr;
+ dma_addr_t cb_addr;
+ dma_addr_t cr_addr;
+ dma_addr_t aux_addr;
+ u32 frame_num;
+ u32 flags;
+};
+
+struct tegra_vde {
+ void __iomem *sxe;
+ void __iomem *bsev;
+ void __iomem *mbe;
+ void __iomem *ppe;
+ void __iomem *mce;
+ void __iomem *tfe;
+ void __iomem *ppb;
+ void __iomem *vdma;
+ void __iomem *frameid;
+ struct mutex lock;
+ struct miscdevice miscdev;
+ struct reset_control *rst;
+ struct gen_pool *iram_pool;
+ struct completion decode_completion;
+ struct clk *clk;
+ dma_addr_t iram_lists_addr;
+ u32 *iram;
+};
+
+static void tegra_vde_set_bits(struct tegra_vde *vde,
+ u32 mask, void __iomem *regs)
+{
+ u32 value = readl_relaxed(regs);
+
+ VDE_WR(value | mask, regs);
+}
+
+static int tegra_vde_wait_mbe(struct tegra_vde *vde)
+{
+ u32 tmp;
+
+ return readl_relaxed_poll_timeout(vde->mbe + 0x8C, tmp,
+ (tmp >= 0x10), 1, 100);
+}
+
+static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde,
+ unsigned int refs_nb,
+ bool setup_refs)
+{
+ u32 frame_idx_enb_mask = 0;
+ u32 value;
+ unsigned int frame_idx;
+ unsigned int idx;
+ int err;
+
+ VDE_WR(0xD0000000 | (0 << 23), vde->mbe + 0x80);
+ VDE_WR(0xD0200000 | (0 << 23), vde->mbe + 0x80);
+
+ err = tegra_vde_wait_mbe(vde);
+ if (err)
+ return err;
+
+ if (!setup_refs)
+ return 0;
+
+ for (idx = 0, frame_idx = 1; idx < refs_nb; idx++, frame_idx++) {
+ VDE_WR(0xD0000000 | (frame_idx << 23), vde->mbe + 0x80);
+ VDE_WR(0xD0200000 | (frame_idx << 23), vde->mbe + 0x80);
+
+ frame_idx_enb_mask |= frame_idx << (6 * (idx % 4));
+
+ if (idx % 4 == 3 || idx == refs_nb - 1) {
+ value = 0xC0000000;
+ value |= (idx >> 2) << 24;
+ value |= frame_idx_enb_mask;
+
+ VDE_WR(value, vde->mbe + 0x80);
+
+ err = tegra_vde_wait_mbe(vde);
+ if (err)
+ return err;
+
+ frame_idx_enb_mask = 0;
+ }
+ }
+
+ return 0;
+}
+
+static void tegra_vde_mbe_set_0xa_reg(struct tegra_vde *vde, int reg, u32 val)
+{
+ VDE_WR(0xA0000000 | (reg << 24) | (val & 0xFFFF), vde->mbe + 0x80);
+ VDE_WR(0xA0000000 | ((reg + 1) << 24) | (val >> 16), vde->mbe + 0x80);
+}
+
+static int tegra_vde_wait_bsev(struct tegra_vde *vde, bool wait_dma)
+{
+ struct device *dev = vde->miscdev.parent;
+ u32 value;
+ int err;
+
+ err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
+ !(value & BIT(2)), 1, 100);
+ if (err) {
+ dev_err(dev, "BSEV unknown bit timeout\n");
+ return err;
+ }
+
+ err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
+ (value & BSE_ICMDQUE_EMPTY), 1, 100);
+ if (err) {
+ dev_err(dev, "BSEV ICMDQUE flush timeout\n");
+ return err;
+ }
+
+ if (!wait_dma)
+ return 0;
+
+ err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
+ !(value & BSE_DMA_BUSY), 1, 100);
+ if (err) {
+ dev_err(dev, "BSEV DMA timeout\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int tegra_vde_push_to_bsev_icmdqueue(struct tegra_vde *vde,
+ u32 value, bool wait_dma)
+{
+ VDE_WR(value, vde->bsev + ICMDQUE_WR);
+
+ return tegra_vde_wait_bsev(vde, wait_dma);
+}
+
+static void tegra_vde_setup_frameid(struct tegra_vde *vde,
+ struct video_frame *frame,
+ unsigned int frameid,
+ u32 mbs_width, u32 mbs_height)
+{
+ u32 y_addr = frame ? frame->y_addr : 0x6CDEAD00;
+ u32 cb_addr = frame ? frame->cb_addr : 0x6CDEAD00;
+ u32 cr_addr = frame ? frame->cr_addr : 0x6CDEAD00;
+ u32 value1 = frame ? ((mbs_width << 16) | mbs_height) : 0;
+ u32 value2 = frame ? ((((mbs_width + 1) >> 1) << 6) | 1) : 0;
+
+ VDE_WR(y_addr >> 8, vde->frameid + 0x000 + frameid * 4);
+ VDE_WR(cb_addr >> 8, vde->frameid + 0x100 + frameid * 4);
+ VDE_WR(cr_addr >> 8, vde->frameid + 0x180 + frameid * 4);
+ VDE_WR(value1, vde->frameid + 0x080 + frameid * 4);
+ VDE_WR(value2, vde->frameid + 0x280 + frameid * 4);
+}
+
+static void tegra_setup_frameidx(struct tegra_vde *vde,
+ struct video_frame *frames,
+ unsigned int frames_nb,
+ u32 mbs_width, u32 mbs_height)
+{
+ unsigned int idx;
+
+ for (idx = 0; idx < frames_nb; idx++)
+ tegra_vde_setup_frameid(vde, &frames[idx], idx,
+ mbs_width, mbs_height);
+
+ for (; idx < 17; idx++)
+ tegra_vde_setup_frameid(vde, NULL, idx, 0, 0);
+}
+
+static void tegra_vde_setup_iram_entry(struct tegra_vde *vde,
+ unsigned int table,
+ unsigned int row,
+ u32 value1, u32 value2)
+{
+ u32 *iram_tables = vde->iram;
+
+ dev_dbg(vde->miscdev.parent, "IRAM table %u: row %u: 0x%08X 0x%08X\n",
+ table, row, value1, value2);
+
+ iram_tables[0x20 * table + row * 2] = value1;
+ iram_tables[0x20 * table + row * 2 + 1] = value2;
+}
+
+static void tegra_vde_setup_iram_tables(struct tegra_vde *vde,
+ struct video_frame *dpb_frames,
+ unsigned int ref_frames_nb,
+ unsigned int with_earlier_poc_nb)
+{
+ struct video_frame *frame;
+ u32 value, aux_addr;
+ int with_later_poc_nb;
+ unsigned int i, k;
+
+ dev_dbg(vde->miscdev.parent, "DPB: Frame 0: frame_num = %d\n",
+ dpb_frames[0].frame_num);
+
+ dev_dbg(vde->miscdev.parent, "REF L0:\n");
+
+ for (i = 0; i < 16; i++) {
+ if (i < ref_frames_nb) {
+ frame = &dpb_frames[i + 1];
+
+ aux_addr = frame->aux_addr;
+
+ value = (i + 1) << 26;
+ value |= !(frame->flags & FLAG_B_FRAME) << 25;
+ value |= 1 << 24;
+ value |= frame->frame_num;
+
+ dev_dbg(vde->miscdev.parent,
+ "\tFrame %d: frame_num = %d B_frame = %d\n",
+ i + 1, frame->frame_num,
+ (frame->flags & FLAG_B_FRAME));
+ } else {
+ aux_addr = 0x6ADEAD00;
+ value = 0;
+ }
+
+ tegra_vde_setup_iram_entry(vde, 0, i, value, aux_addr);
+ tegra_vde_setup_iram_entry(vde, 1, i, value, aux_addr);
+ tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
+ tegra_vde_setup_iram_entry(vde, 3, i, value, aux_addr);
+ }
+
+ if (!(dpb_frames[0].flags & FLAG_B_FRAME))
+ return;
+
+ if (with_earlier_poc_nb >= ref_frames_nb)
+ return;
+
+ with_later_poc_nb = ref_frames_nb - with_earlier_poc_nb;
+
+ dev_dbg(vde->miscdev.parent,
+ "REF L1: with_later_poc_nb %d with_earlier_poc_nb %d\n",
+ with_later_poc_nb, with_earlier_poc_nb);
+
+ for (i = 0, k = with_earlier_poc_nb; i < with_later_poc_nb; i++, k++) {
+ frame = &dpb_frames[k + 1];
+
+ aux_addr = frame->aux_addr;
+
+ value = (k + 1) << 26;
+ value |= !(frame->flags & FLAG_B_FRAME) << 25;
+ value |= 1 << 24;
+ value |= frame->frame_num;
+
+ dev_dbg(vde->miscdev.parent,
+ "\tFrame %d: frame_num = %d\n",
+ k + 1, frame->frame_num);
+
+ tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
+ }
+
+ for (k = 0; i < ref_frames_nb; i++, k++) {
+ frame = &dpb_frames[k + 1];
+
+ aux_addr = frame->aux_addr;
+
+ value = (k + 1) << 26;
+ value |= !(frame->flags & FLAG_B_FRAME) << 25;
+ value |= 1 << 24;
+ value |= frame->frame_num;
+
+ dev_dbg(vde->miscdev.parent,
+ "\tFrame %d: frame_num = %d\n",
+ k + 1, frame->frame_num);
+
+ tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
+ }
+}
+
+static int tegra_vde_setup_hw_context(struct tegra_vde *vde,
+ struct tegra_vde_h264_decoder_ctx *ctx,
+ struct video_frame *dpb_frames,
+ dma_addr_t bitstream_data_addr,
+ size_t bitstream_data_size,
+ unsigned int macroblocks_nb)
+{
+ struct device *dev = vde->miscdev.parent;
+ u32 value;
+ int err;
+
+ tegra_vde_set_bits(vde, 0x000A, vde->sxe + 0xF0);
+ tegra_vde_set_bits(vde, 0x000B, vde->bsev + CMDQUE_CONTROL);
+ tegra_vde_set_bits(vde, 0x8002, vde->mbe + 0x50);
+ tegra_vde_set_bits(vde, 0x000A, vde->mbe + 0xA0);
+ tegra_vde_set_bits(vde, 0x000A, vde->ppe + 0x14);
+ tegra_vde_set_bits(vde, 0x000A, vde->ppe + 0x28);
+ tegra_vde_set_bits(vde, 0x0A00, vde->mce + 0x08);
+ tegra_vde_set_bits(vde, 0x000A, vde->tfe + 0x00);
+ tegra_vde_set_bits(vde, 0x0005, vde->vdma + 0x04);
+
+ VDE_WR(0x00000000, vde->vdma + 0x1C);
+ VDE_WR(0x00000000, vde->vdma + 0x00);
+ VDE_WR(0x00000007, vde->vdma + 0x04);
+ VDE_WR(0x00000007, vde->frameid + 0x200);
+ VDE_WR(0x00000005, vde->tfe + 0x04);
+ VDE_WR(0x00000000, vde->mbe + 0x84);
+ VDE_WR(0x00000010, vde->sxe + 0x08);
+ VDE_WR(0x00000150, vde->sxe + 0x54);
+ VDE_WR(0x0000054C, vde->sxe + 0x58);
+ VDE_WR(0x00000E34, vde->sxe + 0x5C);
+ VDE_WR(0x063C063C, vde->mce + 0x10);
+ VDE_WR(0x0003FC00, vde->bsev + INTR_STATUS);
+ VDE_WR(0x0000150D, vde->bsev + BSE_CONFIG);
+ VDE_WR(0x00000100, vde->bsev + BSE_INT_ENB);
+ VDE_WR(0x00000000, vde->bsev + 0x98);
+ VDE_WR(0x00000060, vde->bsev + 0x9C);
+
+ memset(vde->iram + 128, 0, macroblocks_nb / 2);
+
+ tegra_setup_frameidx(vde, dpb_frames, ctx->dpb_frames_nb,
+ ctx->pic_width_in_mbs, ctx->pic_height_in_mbs);
+
+ tegra_vde_setup_iram_tables(vde, dpb_frames,
+ ctx->dpb_frames_nb - 1,
+ ctx->dpb_ref_frames_with_earlier_poc_nb);
+ wmb();
+
+ VDE_WR(0x00000000, vde->bsev + 0x8C);
+ VDE_WR(bitstream_data_addr + bitstream_data_size,
+ vde->bsev + 0x54);
+
+ value = ctx->pic_width_in_mbs << 11 | ctx->pic_height_in_mbs << 3;
+
+ VDE_WR(value, vde->bsev + 0x88);
+
+ err = tegra_vde_wait_bsev(vde, false);
+ if (err)
+ return err;
+
+ err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x800003FC, false);
+ if (err)
+ return err;
+
+ value = 0x01500000;
+ value |= ((vde->iram_lists_addr + 512) >> 2) & 0xFFFF;
+
+ err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true);
+ if (err)
+ return err;
+
+ err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x840F054C, false);
+ if (err)
+ return err;
+
+ err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x80000080, false);
+ if (err)
+ return err;
+
+ value = 0x0E340000 | ((vde->iram_lists_addr >> 2) & 0xFFFF);
+
+ err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true);
+ if (err)
+ return err;
+
+ value = 0x00800005;
+ value |= ctx->pic_width_in_mbs << 11;
+ value |= ctx->pic_height_in_mbs << 3;
+
+ VDE_WR(value, vde->sxe + 0x10);
+
+ value = !ctx->baseline_profile << 17;
+ value |= ctx->level_idc << 13;
+ value |= ctx->log2_max_pic_order_cnt_lsb << 7;
+ value |= ctx->pic_order_cnt_type << 5;
+ value |= ctx->log2_max_frame_num;
+
+ VDE_WR(value, vde->sxe + 0x40);
+
+ value = ctx->pic_init_qp << 25;
+ value |= !!(ctx->deblocking_filter_control_present_flag) << 2;
+ value |= !!ctx->pic_order_present_flag;
+
+ VDE_WR(value, vde->sxe + 0x44);
+
+ value = ctx->chroma_qp_index_offset;
+ value |= ctx->num_ref_idx_l0_active_minus1 << 5;
+ value |= ctx->num_ref_idx_l1_active_minus1 << 10;
+ value |= !!ctx->constrained_intra_pred_flag << 15;
+
+ VDE_WR(value, vde->sxe + 0x48);
+
+ value = 0x0C000000;
+ value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 24;
+
+ VDE_WR(value, vde->sxe + 0x4C);
+
+ value = 0x03800000;
+ value |= min_t(size_t, bitstream_data_size, SZ_1M);
+
+ VDE_WR(value, vde->sxe + 0x68);
+
+ VDE_WR(bitstream_data_addr, vde->sxe + 0x6C);
+
+ value = 0x10000005;
+ value |= ctx->pic_width_in_mbs << 11;
+ value |= ctx->pic_height_in_mbs << 3;
+
+ VDE_WR(value, vde->mbe + 0x80);
+
+ value = 0x26800000;
+ value |= ctx->level_idc << 4;
+ value |= !ctx->baseline_profile << 1;
+ value |= !!ctx->direct_8x8_inference_flag;
+
+ VDE_WR(value, vde->mbe + 0x80);
+
+ VDE_WR(0xF4000001, vde->mbe + 0x80);
+ VDE_WR(0x20000000, vde->mbe + 0x80);
+ VDE_WR(0xF4000101, vde->mbe + 0x80);
+
+ value = 0x20000000;
+ value |= ctx->chroma_qp_index_offset << 8;
+
+ VDE_WR(value, vde->mbe + 0x80);
+
+ err = tegra_vde_setup_mbe_frame_idx(vde,
+ ctx->dpb_frames_nb - 1,
+ ctx->pic_order_cnt_type == 0);
+ if (err) {
+ dev_err(dev, "MBE frames setup failed %d\n", err);
+ return err;
+ }
+
+ tegra_vde_mbe_set_0xa_reg(vde, 0, 0x000009FC);
+ tegra_vde_mbe_set_0xa_reg(vde, 2, 0x61DEAD00);
+ tegra_vde_mbe_set_0xa_reg(vde, 4, 0x62DEAD00);
+ tegra_vde_mbe_set_0xa_reg(vde, 6, 0x63DEAD00);
+ tegra_vde_mbe_set_0xa_reg(vde, 8, dpb_frames[0].aux_addr);
+
+ value = 0xFC000000;
+ value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 2;
+
+ if (!ctx->baseline_profile)
+ value |= !!(dpb_frames[0].flags & FLAG_REFERENCE) << 1;
+
+ VDE_WR(value, vde->mbe + 0x80);
+
+ err = tegra_vde_wait_mbe(vde);
+ if (err) {
+ dev_err(dev, "MBE programming failed %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static void tegra_vde_decode_frame(struct tegra_vde *vde,
+ unsigned int macroblocks_nb)
+{
+ reinit_completion(&vde->decode_completion);
+
+ VDE_WR(0x00000001, vde->bsev + 0x8C);
+ VDE_WR(0x20000000 | (macroblocks_nb - 1), vde->sxe + 0x00);
+}
+
+static void tegra_vde_detach_and_put_dmabuf(struct dma_buf_attachment *a,
+ struct sg_table *sgt,
+ enum dma_data_direction dma_dir)
+{
+ struct dma_buf *dmabuf = a->dmabuf;
+
+ dma_buf_unmap_attachment(a, sgt, dma_dir);
+ dma_buf_detach(dmabuf, a);
+ dma_buf_put(dmabuf);
+}
+
+static int tegra_vde_attach_dmabuf(struct device *dev,
+ int fd,
+ unsigned long offset,
+ unsigned int min_size,
+ struct dma_buf_attachment **a,
+ dma_addr_t *addr,
+ struct sg_table **s,
+ size_t *size,
+ enum dma_data_direction dma_dir)
+{
+ struct dma_buf_attachment *attachment;
+ struct dma_buf *dmabuf;
+ struct sg_table *sgt;
+ int err;
+
+ dmabuf = dma_buf_get(fd);
+ if (IS_ERR(dmabuf)) {
+ dev_err(dev, "Invalid dmabuf FD\n");
+ return PTR_ERR(dmabuf);
+ }
+
+ if ((u64)offset + min_size > dmabuf->size) {
+ dev_err(dev, "Too small dmabuf size %zu @0x%lX, "
+ "should be at least %d\n",
+ dmabuf->size, offset, min_size);
+ return -EINVAL;
+ }
+
+ attachment = dma_buf_attach(dmabuf, dev);
+ if (IS_ERR(attachment)) {
+ dev_err(dev, "Failed to attach dmabuf\n");
+ err = PTR_ERR(attachment);
+ goto err_put;
+ }
+
+ sgt = dma_buf_map_attachment(attachment, dma_dir);
+ if (IS_ERR(sgt)) {
+ dev_err(dev, "Failed to get dmabufs sg_table\n");
+ err = PTR_ERR(sgt);
+ goto err_detach;
+ }
+
+ if (sgt->nents != 1) {
+ dev_err(dev, "Sparse DMA region is unsupported\n");
+ err = -EINVAL;
+ goto err_unmap;
+ }
+
+ *addr = sg_dma_address(sgt->sgl) + offset;
+ *a = attachment;
+ *s = sgt;
+
+ if (size)
+ *size = dmabuf->size - offset;
+
+ return 0;
+
+err_unmap:
+ dma_buf_unmap_attachment(attachment, sgt, dma_dir);
+err_detach:
+ dma_buf_detach(dmabuf, attachment);
+err_put:
+ dma_buf_put(dmabuf);
+
+ return err;
+}
+
+static int tegra_vde_attach_dmabufs_to_frame(struct device *dev,
+ struct video_frame *frame,
+ struct tegra_vde_h264_frame *src,
+ enum dma_data_direction dma_dir,
+ bool baseline_profile,
+ size_t csize)
+{
+ int err;
+
+ err = tegra_vde_attach_dmabuf(dev, src->y_fd,
+ src->y_offset, csize * 4,
+ &frame->y_dmabuf_attachment,
+ &frame->y_addr,
+ &frame->y_sgt,
+ NULL, dma_dir);
+ if (err)
+ return err;
+
+ err = tegra_vde_attach_dmabuf(dev, src->cb_fd,
+ src->cb_offset, csize,
+ &frame->cb_dmabuf_attachment,
+ &frame->cb_addr,
+ &frame->cb_sgt,
+ NULL, dma_dir);
+ if (err)
+ goto err_release_y;
+
+ err = tegra_vde_attach_dmabuf(dev, src->cr_fd,
+ src->cr_offset, csize,
+ &frame->cr_dmabuf_attachment,
+ &frame->cr_addr,
+ &frame->cr_sgt,
+ NULL, dma_dir);
+ if (err)
+ goto err_release_cb;
+
+ if (baseline_profile) {
+ frame->aux_addr = 0x64DEAD00;
+ return 0;
+ }
+
+ err = tegra_vde_attach_dmabuf(dev, src->aux_fd,
+ src->aux_offset, csize,
+ &frame->aux_dmabuf_attachment,
+ &frame->aux_addr,
+ &frame->aux_sgt,
+ NULL, dma_dir);
+ if (err)
+ goto err_release_cr;
+
+ return 0;
+
+err_release_cr:
+ tegra_vde_detach_and_put_dmabuf(frame->cr_dmabuf_attachment,
+ frame->cr_sgt, dma_dir);
+err_release_cb:
+ tegra_vde_detach_and_put_dmabuf(frame->cb_dmabuf_attachment,
+ frame->cb_sgt, dma_dir);
+err_release_y:
+ tegra_vde_detach_and_put_dmabuf(frame->y_dmabuf_attachment,
+ frame->y_sgt, dma_dir);
+
+ return err;
+}
+
+static void tegra_vde_release_frame_dmabufs(struct video_frame *frame,
+ enum dma_data_direction dma_dir,
+ bool baseline_profile)
+{
+ if (!baseline_profile)
+ tegra_vde_detach_and_put_dmabuf(frame->aux_dmabuf_attachment,
+ frame->aux_sgt, dma_dir);
+
+ tegra_vde_detach_and_put_dmabuf(frame->cr_dmabuf_attachment,
+ frame->cr_sgt, dma_dir);
+
+ tegra_vde_detach_and_put_dmabuf(frame->cb_dmabuf_attachment,
+ frame->cb_sgt, dma_dir);
+
+ tegra_vde_detach_and_put_dmabuf(frame->y_dmabuf_attachment,
+ frame->y_sgt, dma_dir);
+}
+
+static int tegra_vde_validate_frame(struct device *dev,
+ struct tegra_vde_h264_frame *frame)
+{
+ if (frame->frame_num > 0x7FFFFF) {
+ dev_err(dev, "Bad frame_num %u\n", frame->frame_num);
+ return -EINVAL;
+ }
+
+ if (frame->y_offset & 0xFF) {
+ dev_err(dev, "Bad y_offset 0x%X\n", frame->y_offset);
+ return -EINVAL;
+ }
+
+ if (frame->cb_offset & 0xFF) {
+ dev_err(dev, "Bad cb_offset 0x%X\n", frame->cb_offset);
+ return -EINVAL;
+ }
+
+ if (frame->cr_offset & 0xFF) {
+ dev_err(dev, "Bad cr_offset 0x%X\n", frame->cr_offset);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int tegra_vde_validate_h264_ctx(struct device *dev,
+ struct tegra_vde_h264_decoder_ctx *ctx)
+{
+ if (ctx->dpb_frames_nb == 0 || ctx->dpb_frames_nb > 17) {
+ dev_err(dev, "Bad DPB size %u\n", ctx->dpb_frames_nb);
+ return -EINVAL;
+ }
+
+ if (ctx->level_idc > 15) {
+ dev_err(dev, "Bad level value %u\n", ctx->level_idc);
+ return -EINVAL;
+ }
+
+ if (ctx->pic_init_qp > 52) {
+ dev_err(dev, "Bad pic_init_qp value %u\n", ctx->pic_init_qp);
+ return -EINVAL;
+ }
+
+ if (ctx->log2_max_pic_order_cnt_lsb > 16) {
+ dev_err(dev, "Bad log2_max_pic_order_cnt_lsb value %u\n",
+ ctx->log2_max_pic_order_cnt_lsb);
+ return -EINVAL;
+ }
+
+ if (ctx->log2_max_frame_num > 16) {
+ dev_err(dev, "Bad log2_max_frame_num value %u\n",
+ ctx->log2_max_frame_num);
+ return -EINVAL;
+ }
+
+ if (ctx->chroma_qp_index_offset > 31) {
+ dev_err(dev, "Bad chroma_qp_index_offset value %u\n",
+ ctx->chroma_qp_index_offset);
+ return -EINVAL;
+ }
+
+ if (ctx->pic_order_cnt_type > 2) {
+ dev_err(dev, "Bad pic_order_cnt_type value %u\n",
+ ctx->pic_order_cnt_type);
+ return -EINVAL;
+ }
+
+ if (ctx->num_ref_idx_l0_active_minus1 > 15) {
+ dev_err(dev, "Bad num_ref_idx_l0_active_minus1 value %u\n",
+ ctx->num_ref_idx_l0_active_minus1);
+ return -EINVAL;
+ }
+
+ if (ctx->num_ref_idx_l1_active_minus1 > 15) {
+ dev_err(dev, "Bad num_ref_idx_l1_active_minus1 value %u\n",
+ ctx->num_ref_idx_l1_active_minus1);
+ return -EINVAL;
+ }
+
+ if (!ctx->pic_width_in_mbs || ctx->pic_width_in_mbs > 127) {
+ dev_err(dev, "Bad pic_width_in_mbs value %u\n",
+ ctx->pic_width_in_mbs);
+ return -EINVAL;
+ }
+
+ if (!ctx->pic_height_in_mbs || ctx->pic_height_in_mbs > 127) {
+ dev_err(dev, "Bad pic_height_in_mbs value %u\n",
+ ctx->pic_height_in_mbs);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int tegra_vde_ioctl_decode_h264(struct tegra_vde *vde,
+ unsigned long vaddr)
+{
+ struct device *dev = vde->miscdev.parent;
+ struct tegra_vde_h264_decoder_ctx ctx;
+ struct tegra_vde_h264_frame frames[17];
+ struct tegra_vde_h264_frame __user *frames_user;
+ struct video_frame *dpb_frames;
+ struct dma_buf_attachment *bitstream_data_dmabuf_attachment;
+ struct sg_table *bitstream_sgt;
+ enum dma_data_direction dma_dir;
+ dma_addr_t bitstream_data_addr;
+ dma_addr_t bsev_ptr;
+ size_t bitstream_data_size;
+ unsigned int macroblocks_nb;
+ unsigned int read_bytes;
+ unsigned int i;
+ long timeout;
+ int ret, err;
+
+ if (copy_from_user(&ctx, (void __user *)vaddr, sizeof(ctx)))
+ return -EFAULT;
+
+ ret = tegra_vde_validate_h264_ctx(dev, &ctx);
+ if (ret)
+ return ret;
+
+ ret = tegra_vde_attach_dmabuf(dev, ctx.bitstream_data_fd,
+ ctx.bitstream_data_offset, 0,
+ &bitstream_data_dmabuf_attachment,
+ &bitstream_data_addr,
+ &bitstream_sgt,
+ &bitstream_data_size,
+ DMA_TO_DEVICE);
+ if (ret)
+ return ret;
+
+ dpb_frames = kcalloc(ctx.dpb_frames_nb, sizeof(*dpb_frames),
+ GFP_KERNEL);
+ if (!dpb_frames) {
+ ret = -ENOMEM;
+ goto release_bitstream_dmabuf;
+ }
+
+ macroblocks_nb = ctx.pic_width_in_mbs * ctx.pic_height_in_mbs;
+ frames_user = u64_to_user_ptr(ctx.dpb_frames_ptr);
+
+ if (copy_from_user(frames, frames_user,
+ ctx.dpb_frames_nb * sizeof(*frames))) {
+ ret = -EFAULT;
+ goto free_dpb_frames;
+ }
+
+ for (i = 0; i < ctx.dpb_frames_nb; i++) {
+ ret = tegra_vde_validate_frame(dev, &frames[i]);
+ if (ret)
+ goto release_dpb_frames;
+
+ dpb_frames[i].flags = frames[i].flags;
+ dpb_frames[i].frame_num = frames[i].frame_num;
+
+ dma_dir = (i == 0) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+
+ ret = tegra_vde_attach_dmabufs_to_frame(dev, &dpb_frames[i],
+ &frames[i], dma_dir,
+ ctx.baseline_profile,
+ macroblocks_nb * 64);
+ if (ret)
+ goto release_dpb_frames;
+ }
+
+ ret = mutex_lock_interruptible(&vde->lock);
+ if (ret)
+ goto release_dpb_frames;
+
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0)
+ goto unlock;
+
+ /*
+ * We rely on the VDE registers reset value, otherwise VDE
+ * causes bus lockup.
+ */
+ ret = reset_control_reset(vde->rst);
+ if (ret) {
+ dev_err(dev, "Failed to reset HW: %d\n", ret);
+ goto put_runtime_pm;
+ }
+
+ ret = tegra_vde_setup_hw_context(vde, &ctx, dpb_frames,
+ bitstream_data_addr,
+ bitstream_data_size,
+ macroblocks_nb);
+ if (ret)
+ goto put_runtime_pm;
+
+ tegra_vde_decode_frame(vde, macroblocks_nb);
+
+ timeout = wait_for_completion_interruptible_timeout(
+ &vde->decode_completion, msecs_to_jiffies(1000));
+ if (timeout == 0) {
+ bsev_ptr = readl_relaxed(vde->bsev + 0x10);
+ macroblocks_nb = readl_relaxed(vde->sxe + 0xC8) & 0x1FFF;
+ read_bytes = bsev_ptr ? bsev_ptr - bitstream_data_addr : 0;
+
+ dev_err(dev, "Decoding failed: "
+ "read 0x%X bytes, %u macroblocks parsed\n",
+ read_bytes, macroblocks_nb);
+
+ ret = -EIO;
+ } else if (timeout < 0) {
+ ret = timeout;
+ }
+
+ err = reset_control_assert(vde->rst);
+ if (err)
+ dev_err(dev, "Failed to assert HW reset: %d\n", err);
+
+put_runtime_pm:
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+
+unlock:
+ mutex_unlock(&vde->lock);
+
+release_dpb_frames:
+ while (i--) {
+ dma_dir = (i == 0) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+
+ tegra_vde_release_frame_dmabufs(&dpb_frames[i], dma_dir,
+ ctx.baseline_profile);
+ }
+
+free_dpb_frames:
+ kfree(dpb_frames);
+
+release_bitstream_dmabuf:
+ tegra_vde_detach_and_put_dmabuf(bitstream_data_dmabuf_attachment,
+ bitstream_sgt, DMA_TO_DEVICE);
+
+ return ret;
+}
+
+static long tegra_vde_unlocked_ioctl(struct file *filp,
+ unsigned int cmd, unsigned long arg)
+{
+ struct miscdevice *miscdev = filp->private_data;
+ struct tegra_vde *vde = container_of(miscdev, struct tegra_vde,
+ miscdev);
+
+ switch (cmd) {
+ case TEGRA_VDE_IOCTL_DECODE_H264:
+ return tegra_vde_ioctl_decode_h264(vde, arg);
+ }
+
+ dev_err(miscdev->parent, "Invalid IOCTL command %u\n", cmd);
+
+ return -ENOTTY;
+}
+
+static const struct file_operations tegra_vde_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = tegra_vde_unlocked_ioctl,
+};
+
+static irqreturn_t tegra_vde_isr(int irq, void *data)
+{
+ struct tegra_vde *vde = data;
+
+ tegra_vde_set_bits(vde, 0, vde->frameid + 0x208);
+ complete(&vde->decode_completion);
+
+ return IRQ_HANDLED;
+}
+
+static int tegra_vde_runtime_suspend(struct device *dev)
+{
+ struct tegra_vde *vde = dev_get_drvdata(dev);
+ int err;
+
+ err = tegra_powergate_power_off(TEGRA_POWERGATE_VDEC);
+ if (err) {
+ dev_err(dev, "Failed to power down HW: %d\n", err);
+ return err;
+ }
+
+ clk_disable_unprepare(vde->clk);
+
+ return 0;
+}
+
+static int tegra_vde_runtime_resume(struct device *dev)
+{
+ struct tegra_vde *vde = dev_get_drvdata(dev);
+ int err;
+
+ err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_VDEC,
+ vde->clk, vde->rst);
+ if (err) {
+ dev_err(dev, "Failed to power up HW : %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static int tegra_vde_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *regs;
+ struct tegra_vde *vde;
+ int irq, err;
+
+ vde = devm_kzalloc(dev, sizeof(*vde), GFP_KERNEL);
+ if (!vde)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, vde);
+
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sxe");
+ if (!regs)
+ return -ENODEV;
+
+ vde->sxe = devm_ioremap_resource(dev, regs);
+ if (IS_ERR(vde->sxe))
+ return PTR_ERR(vde->sxe);
+
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bsev");
+ if (!regs)
+ return -ENODEV;
+
+ vde->bsev = devm_ioremap_resource(dev, regs);
+ if (IS_ERR(vde->bsev))
+ return PTR_ERR(vde->bsev);
+
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mbe");
+ if (!regs)
+ return -ENODEV;
+
+ vde->mbe = devm_ioremap_resource(dev, regs);
+ if (IS_ERR(vde->mbe))
+ return PTR_ERR(vde->mbe);
+
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe");
+ if (!regs)
+ return -ENODEV;
+
+ vde->ppe = devm_ioremap_resource(dev, regs);
+ if (IS_ERR(vde->ppe))
+ return PTR_ERR(vde->ppe);
+
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mce");
+ if (!regs)
+ return -ENODEV;
+
+ vde->mce = devm_ioremap_resource(dev, regs);
+ if (IS_ERR(vde->mce))
+ return PTR_ERR(vde->mce);
+
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tfe");
+ if (!regs)
+ return -ENODEV;
+
+ vde->tfe = devm_ioremap_resource(dev, regs);
+ if (IS_ERR(vde->tfe))
+ return PTR_ERR(vde->tfe);
+
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppb");
+ if (!regs)
+ return -ENODEV;
+
+ vde->ppb = devm_ioremap_resource(dev, regs);
+ if (IS_ERR(vde->ppb))
+ return PTR_ERR(vde->ppb);
+
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vdma");
+ if (!regs)
+ return -ENODEV;
+
+ vde->vdma = devm_ioremap_resource(dev, regs);
+ if (IS_ERR(vde->vdma))
+ return PTR_ERR(vde->vdma);
+
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "frameid");
+ if (!regs)
+ return -ENODEV;
+
+ vde->frameid = devm_ioremap_resource(dev, regs);
+ if (IS_ERR(vde->frameid))
+ return PTR_ERR(vde->frameid);
+
+ vde->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(vde->clk)) {
+ err = PTR_ERR(vde->clk);
+ dev_err(dev, "Could not get VDE clk %d\n", err);
+ return err;
+ }
+
+ vde->rst = devm_reset_control_get(dev, NULL);
+ if (IS_ERR(vde->rst)) {
+ err = PTR_ERR(vde->rst);
+ dev_err(dev, "Could not get VDE reset %d\n", err);
+ return err;
+ }
+
+ irq = platform_get_irq_byname(pdev, "sync-token");
+ if (irq < 0)
+ return irq;
+
+ err = devm_request_irq(dev, irq, tegra_vde_isr, 0,
+ dev_name(dev), vde);
+ if (err) {
+ dev_err(dev, "Could not request IRQ %d\n", err);
+ return err;
+ }
+
+ vde->iram_pool = of_gen_pool_get(dev->of_node, "iram", 0);
+ if (!vde->iram_pool) {
+ dev_err(dev, "Could not get IRAM pool\n");
+ return -EPROBE_DEFER;
+ }
+
+ vde->iram = gen_pool_dma_alloc(vde->iram_pool,
+ gen_pool_size(vde->iram_pool),
+ &vde->iram_lists_addr);
+ if (!vde->iram) {
+ dev_err(dev, "Could not reserve IRAM\n");
+ return -ENOMEM;
+ }
+
+ mutex_init(&vde->lock);
+ init_completion(&vde->decode_completion);
+
+ vde->miscdev.minor = MISC_DYNAMIC_MINOR;
+ vde->miscdev.name = "tegra_vde";
+ vde->miscdev.fops = &tegra_vde_fops;
+ vde->miscdev.parent = dev;
+
+ err = misc_register(&vde->miscdev);
+ if (err) {
+ dev_err(dev, "Failed to register misc device: %d\n", err);
+ goto err_gen_free;
+ }
+
+ pm_runtime_enable(dev);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_set_autosuspend_delay(dev, 300);
+
+ if (!pm_runtime_enabled(dev)) {
+ err = tegra_vde_runtime_resume(dev);
+ if (err)
+ goto err_misc_unreg;
+ }
+
+ return 0;
+
+err_misc_unreg:
+ misc_deregister(&vde->miscdev);
+
+err_gen_free:
+ gen_pool_free(vde->iram_pool, (unsigned long)vde->iram,
+ gen_pool_size(vde->iram_pool));
+
+ return err;
+}
+
+static int tegra_vde_remove(struct platform_device *pdev)
+{
+ struct tegra_vde *vde = platform_get_drvdata(pdev);
+ struct device *dev = &pdev->dev;
+ int err;
+
+ if (!pm_runtime_enabled(dev)) {
+ err = tegra_vde_runtime_suspend(dev);
+ if (err)
+ return err;
+ }
+
+ pm_runtime_dont_use_autosuspend(dev);
+ pm_runtime_disable(dev);
+
+ misc_deregister(&vde->miscdev);
+
+ gen_pool_free(vde->iram_pool, (unsigned long)vde->iram,
+ gen_pool_size(vde->iram_pool));
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra_vde_pm_suspend(struct device *dev)
+{
+ struct tegra_vde *vde = dev_get_drvdata(dev);
+ int err;
+
+ mutex_lock(&vde->lock);
+
+ err = pm_runtime_force_suspend(dev);
+ if (err < 0)
+ return err;
+
+ return 0;
+}
+
+static int tegra_vde_pm_resume(struct device *dev)
+{
+ struct tegra_vde *vde = dev_get_drvdata(dev);
+ int err;
+
+ err = pm_runtime_force_resume(dev);
+ if (err < 0)
+ return err;
+
+ mutex_unlock(&vde->lock);
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops tegra_vde_pm_ops = {
+ SET_RUNTIME_PM_OPS(tegra_vde_runtime_suspend,
+ tegra_vde_runtime_resume,
+ NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(tegra_vde_pm_suspend,
+ tegra_vde_pm_resume)
+};
+
+static const struct of_device_id tegra_vde_of_match[] = {
+ { .compatible = "nvidia,tegra20-vde", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, tegra_vde_of_match);
+
+static struct platform_driver tegra_vde_driver = {
+ .probe = tegra_vde_probe,
+ .remove = tegra_vde_remove,
+ .driver = {
+ .name = "tegra-vde",
+ .of_match_table = tegra_vde_of_match,
+ .pm = &tegra_vde_pm_ops,
+ },
+};
+module_platform_driver(tegra_vde_driver);
+
+MODULE_DESCRIPTION("NVIDIA Tegra Video Decoder driver");
+MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/staging/media/tegra-vde/uapi.h b/drivers/staging/media/tegra-vde/uapi.h
new file mode 100644
index 000000000000..a50c7bcae057
--- /dev/null
+++ b/drivers/staging/media/tegra-vde/uapi.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _UAPI_TEGRA_VDE_H_
+#define _UAPI_TEGRA_VDE_H_
+
+#include <linux/types.h>
+#include <asm/ioctl.h>
+
+#define FLAG_B_FRAME (1 << 0)
+#define FLAG_REFERENCE (1 << 1)
+
+struct tegra_vde_h264_frame {
+ __s32 y_fd;
+ __s32 cb_fd;
+ __s32 cr_fd;
+ __s32 aux_fd;
+ __u32 y_offset;
+ __u32 cb_offset;
+ __u32 cr_offset;
+ __u32 aux_offset;
+ __u32 frame_num;
+ __u32 flags;
+
+ __u32 reserved;
+} __attribute__((packed));
+
+struct tegra_vde_h264_decoder_ctx {
+ __s32 bitstream_data_fd;
+ __u32 bitstream_data_offset;
+
+ __u64 dpb_frames_ptr;
+ __u8 dpb_frames_nb;
+ __u8 dpb_ref_frames_with_earlier_poc_nb;
+
+ // SPS
+ __u8 baseline_profile;
+ __u8 level_idc;
+ __u8 log2_max_pic_order_cnt_lsb;
+ __u8 log2_max_frame_num;
+ __u8 pic_order_cnt_type;
+ __u8 direct_8x8_inference_flag;
+ __u8 pic_width_in_mbs;
+ __u8 pic_height_in_mbs;
+
+ // PPS
+ __u8 pic_init_qp;
+ __u8 deblocking_filter_control_present_flag;
+ __u8 constrained_intra_pred_flag;
+ __u8 chroma_qp_index_offset;
+ __u8 pic_order_present_flag;
+
+ // Slice header
+ __u8 num_ref_idx_l0_active_minus1;
+ __u8 num_ref_idx_l1_active_minus1;
+
+ __u32 reserved;
+} __attribute__((packed));
+
+#define VDE_IOCTL_BASE ('v' + 0x20)
+
+#define VDE_IO(nr) _IO(VDE_IOCTL_BASE, nr)
+#define VDE_IOR(nr, type) _IOR(VDE_IOCTL_BASE, nr, type)
+#define VDE_IOW(nr, type) _IOW(VDE_IOCTL_BASE, nr, type)
+#define VDE_IOWR(nr, type) _IOWR(VDE_IOCTL_BASE, nr, type)
+
+#define TEGRA_VDE_DECODE_H264 0x00
+
+#define TEGRA_VDE_IOCTL_DECODE_H264 \
+ VDE_IOW(TEGRA_VDE_DECODE_H264, struct tegra_vde_h264_decoder_ctx)
+
+#endif // _UAPI_TEGRA_VDE_H_
--
2.15.1
^ permalink raw reply related
* [PATCH v5 1/4] media: dt: bindings: Add binding for NVIDIA Tegra Video Decoder Engine
From: Dmitry Osipenko @ 2017-12-12 0:26 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Stephen Warren,
Greg Kroah-Hartman, Mauro Carvalho Chehab, Hans Verkuil,
Vladimir Zapolskiy
Cc: devel, devicetree, linux-kernel, Rob Herring, linux-tegra,
Dan Carpenter, linux-media
In-Reply-To: <cover.1513038011.git.digetx@gmail.com>
Add binding documentation for the Video Decoder Engine which is found
on NVIDIA Tegra20/30/114/124/132 SoC's.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/media/nvidia,tegra-vde.txt | 55 ++++++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
new file mode 100644
index 000000000000..470237ed6fe5
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
@@ -0,0 +1,55 @@
+NVIDIA Tegra Video Decoder Engine
+
+Required properties:
+- compatible : Must contain one of the following values:
+ - "nvidia,tegra20-vde"
+ - "nvidia,tegra30-vde"
+ - "nvidia,tegra114-vde"
+ - "nvidia,tegra124-vde"
+ - "nvidia,tegra132-vde"
+- reg : Must contain an entry for each entry in reg-names.
+- reg-names : Must include the following entries:
+ - sxe
+ - bsev
+ - mbe
+ - ppe
+ - mce
+ - tfe
+ - ppb
+ - vdma
+ - frameid
+- iram : Must contain phandle to the mmio-sram device node that represents
+ IRAM region used by VDE.
+- interrupts : Must contain an entry for each entry in interrupt-names.
+- interrupt-names : Must include the following entries:
+ - sync-token
+ - bsev
+ - sxe
+- clocks : Must include the following entries:
+ - vde
+- resets : Must include the following entries:
+ - vde
+
+Example:
+
+video-codec@6001a000 {
+ compatible = "nvidia,tegra20-vde";
+ reg = <0x6001a000 0x1000 /* Syntax Engine */
+ 0x6001b000 0x1000 /* Video Bitstream Engine */
+ 0x6001c000 0x100 /* Macroblock Engine */
+ 0x6001c200 0x100 /* Post-processing Engine */
+ 0x6001c400 0x100 /* Motion Compensation Engine */
+ 0x6001c600 0x100 /* Transform Engine */
+ 0x6001c800 0x100 /* Pixel prediction block */
+ 0x6001ca00 0x100 /* Video DMA */
+ 0x6001d800 0x300 /* Video frame controls */>;
+ reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
+ "tfe", "ppb", "vdma", "frameid";
+ iram = <&vde_pool>; /* IRAM region */
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
+ interrupt-names = "sync-token", "bsev", "sxe";
+ clocks = <&tegra_car TEGRA20_CLK_VDE>;
+ resets = <&tegra_car 61>;
+};
--
2.15.1
^ permalink raw reply related
* [PATCH v5 0/4] NVIDIA Tegra video decoder driver
From: Dmitry Osipenko @ 2017-12-12 0:26 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Stephen Warren,
Greg Kroah-Hartman, Mauro Carvalho Chehab, Hans Verkuil,
Vladimir Zapolskiy
Cc: Rob Herring, Dan Carpenter, linux-media-u79uwXL29TY76Z2rM5mHXA,
devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
VDE driver provides accelerated video decoding to NVIDIA Tegra SoC's,
it is a result of reverse-engineering efforts. Driver has been tested on
Toshiba AC100 and Acer A500, it should work on any Tegra20 device.
In userspace this driver is utilized by libvdpau-tegra [0] that implements
VDPAU interface, so any video player that supports VDPAU can provide
accelerated video decoding on Tegra20 on Linux.
[0] https://github.com/grate-driver/libvdpau-tegra
Change log:
v5:
- Moved driver to staging/media as per Hans's Verkuil request
- Addressed review comments to v4 from Vladimir Zapolskiy and
Dan Carpenter
- Updated 'TODO', reflecting that this driver require upcoming
support of stateless decoders by V4L2
- Dropped patch that enabled VDE driver in tegra_defconfig for now
as I realized that Tegra's DRM staging config is disabled there
and right now we are relying on it in libvdpau-tegra
- Added myself to MAINTAINERS in the "Introduce driver" patch as per
Vladimir's suggestion
v4:
- Added mmio-sram "IRAM DT node" patch from Vladimir Zapolskiy to
the series, I modified it to cover all Tegra's and not only Tegra20
- Utilized genalloc for the reservation of IRAM region as per
Vladimir's suggestion, VDE driver now selects SRAM driver in Kconfig
- Added defconfig patch to the series
- Described VDE registers in DT per HW unit, excluding BSE-A / UCQ
and holes between the units
- Extended DT compatibility property with Tegra30/114/124/132 in the
binding doc.
- Removed BSE-A interrupt from the DT binding because it's very
likely that Audio Bitstream Engine isn't integrated with VDE
- Removed UCQ interrupt from the DT binding because in TRM it is
represented as a distinct HW block that probably should have
its own driver
- Addressed v3 review comments: factored out DT binding addition
into a standalone patch, moved binding to media/, removed
clocks/resets-names
v3:
- Suppressed compilation warnings reported by 'kbuild test robot'
v2:
- Addressed v1 review comments from Stephen Warren and Dan Carpenter
- Implemented runtime PM
- Miscellaneous code cleanups
- Changed 'TODO'
- CC'd media maintainers for the review as per Greg's K-H request,
v1 can be viewed at https://lkml.org/lkml/2017/9/25/606
Dmitry Osipenko (3):
media: dt: bindings: Add binding for NVIDIA Tegra Video Decoder Engine
staging: media: Introduce NVIDIA Tegra video decoder driver
ARM: dts: tegra20: Add video decoder node
Vladimir Zapolskiy (1):
ARM: dts: tegra20: Add device tree node to describe IRAM
.../devicetree/bindings/media/nvidia,tegra-vde.txt | 55 +
MAINTAINERS | 9 +
arch/arm/boot/dts/tegra20.dtsi | 35 +
drivers/staging/media/Kconfig | 2 +
drivers/staging/media/Makefile | 1 +
drivers/staging/media/tegra-vde/Kconfig | 7 +
drivers/staging/media/tegra-vde/Makefile | 1 +
drivers/staging/media/tegra-vde/TODO | 4 +
drivers/staging/media/tegra-vde/tegra-vde.c | 1213 ++++++++++++++++++++
drivers/staging/media/tegra-vde/uapi.h | 78 ++
10 files changed, 1405 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
create mode 100644 drivers/staging/media/tegra-vde/Kconfig
create mode 100644 drivers/staging/media/tegra-vde/Makefile
create mode 100644 drivers/staging/media/tegra-vde/TODO
create mode 100644 drivers/staging/media/tegra-vde/tegra-vde.c
create mode 100644 drivers/staging/media/tegra-vde/uapi.h
--
2.15.1
^ permalink raw reply
* Re: [PATCH 0/3] Meson8 GPIO interrupt support
From: Kevin Hilman @ 2017-12-11 23:59 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: Marc Zyngier, carlo-KA+7E9HrN00dnm+yROfE0A,
tglx-hfZtesqFncYOwBW4kG4KsQ, jason-NLaQJdtUoK4Be96aLqz0jA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <CAFBinCDdJtE4g7iCgaw9KEYPhKWjt0YoDy2CfXcTKq+OTDPbLA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> writes:
> Hi Kevin,
>
> On Tue, Oct 31, 2017 at 11:13 AM, Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> wrote:
>> Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> writes:
>>
>>> On Mon, Oct 30 2017 at 12:05:20 am GMT, Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> wrote:
>>>> This is a simple follow-up of two series from Jerome:
>>>> - "irqchip: meson: add support for the gpio interrupt controller"
>>>> - "ARM: meson: enable gpio interrupt controller"
>>>>
>>>> This fills in the missing bits to have GPIO interrupt support on Meson8,
>>>> which includes:
>>>> - a new binding in the driver with the correct IRQ number
>>>> - enabling the GPIO interrupt controller in meson8.dts
>>>> - enabling the GPIO interrupt controller via Kconfig for MACH_MESON8
>>>>
>>>>
>>>> Martin Blumenstingl (3):
>>>> irqchip/meson-gpio: add support for Meson8 SoCs
>>>> ARM: dts: meson8: enable the GPIO interrupt controller
>>>> ARM: meson: enable MESON_IRQ_GPIO also for MACH_MESON8
>>>>
>>>> .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 +
>>>> arch/arm/boot/dts/meson8.dtsi | 5 +++++
>>>> arch/arm/mach-meson/Kconfig | 1 +
>>>> drivers/irqchip/irq-meson-gpio.c | 5 +++++
>>>> 4 files changed, 12 insertions(+)
>>>
>>> Kevin, Carlos: Are you OK with this one? It seems pretty minor, and I'm
>>> happy to queue it if I get an Ack for it. If you'd rather get it through
>>> via armsoc, let me know.
>>
>> Can you take the drivers/irqchip and bindings patch (PATCH 1/3) and I'll
>> take the rest to avoid conflicts with a bunch of other moving parts we
>> have in arch/arm.
> PATCH 1/3 even made it into v4.15
> can you please queue the remaining two patches for v4.16 - or do you
> want me to re-send these?
No need to resend, I've applied them to v4.16/dt.
Thanks for following up.
Kevin
--
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^ permalink raw reply
* [PATCH v10 13/13] MAINTAINERS: Add SLIMbus maintainer
From: srinivas.kandagatla @ 2017-12-11 23:43 UTC (permalink / raw)
To: Mark Brown, Greg Kroah-Hartman, alsa-devel
Cc: sdharia, Rob Herring, Mark Rutland, Jonathan Corbet, pombredanne,
j.neuschaefer, linux-arm-msm, devicetree, linux-kernel, linux-doc,
Srinivas Kandagatla
In-Reply-To: <20171211234307.14465-1-srinivas.kandagatla@linaro.org>
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Add myself as maintainer for slimbus.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aa71ab52fd76..f26bf2707709 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12500,6 +12500,14 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git
F: include/linux/srcu.h
F: kernel/rcu/srcu.c
+SERIAL LOW-POWER INTER-CHIP MEDIA BUS (SLIMbus)
+M: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+L: alsa-devel@alsa-project.org (moderated for non-subscribers)
+S: Maintained
+F: drivers/slimbus/
+F: Documentation/devicetree/bindings/slimbus/
+F: include/linux/slimbus.h
+
SMACK SECURITY MODULE
M: Casey Schaufler <casey@schaufler-ca.com>
L: linux-security-module@vger.kernel.org
--
2.15.0
^ permalink raw reply related
* [PATCH v10 12/13] slimbus: qcom: Add runtime-pm support using clock-pause
From: srinivas.kandagatla @ 2017-12-11 23:43 UTC (permalink / raw)
To: Mark Brown, Greg Kroah-Hartman, alsa-devel
Cc: sdharia, Rob Herring, Mark Rutland, Jonathan Corbet, pombredanne,
j.neuschaefer, linux-arm-msm, devicetree, linux-kernel, linux-doc,
Srinivas Kandagatla
In-Reply-To: <20171211234307.14465-1-srinivas.kandagatla@linaro.org>
From: Sagar Dharia <sdharia@codeaurora.org>
Slimbus HW mandates that clock-pause sequence has to be executed
before disabling relevant interface and core clocks.
Runtime-PM's autosuspend feature is used here to enter/exit low
power mode for Qualcomm's Slimbus controller. Autosuspend feature
enables driver to avoid changing power-modes too frequently since
entering clock-pause is an expensive sequence
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
drivers/slimbus/qcom-ctrl.c | 101 ++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 98 insertions(+), 3 deletions(-)
diff --git a/drivers/slimbus/qcom-ctrl.c b/drivers/slimbus/qcom-ctrl.c
index ace85ce3de90..35ad70dbfe3a 100644
--- a/drivers/slimbus/qcom-ctrl.c
+++ b/drivers/slimbus/qcom-ctrl.c
@@ -14,6 +14,7 @@
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/dma-mapping.h>
+#include <linux/pm_runtime.h>
#include "slimbus.h"
/* Manager registers */
@@ -65,6 +66,7 @@
((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16))
#define SLIM_ROOT_FREQ 24576000
+#define QCOM_SLIM_AUTOSUSPEND 1000
/* MAX message size over control channel */
#define SLIM_MSGQ_BUF_LEN 40
@@ -275,6 +277,30 @@ static irqreturn_t qcom_slim_interrupt(int irq, void *d)
return ret;
}
+static int qcom_clk_pause_wakeup(struct slim_controller *sctrl)
+{
+ struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
+
+ clk_prepare_enable(ctrl->hclk);
+ clk_prepare_enable(ctrl->rclk);
+ enable_irq(ctrl->irq);
+
+ writel_relaxed(1, ctrl->base + FRM_WAKEUP);
+ /* Make sure framer wakeup write goes through before ISR fires */
+ mb();
+ /*
+ * HW Workaround: Currently, slave is reporting lost-sync messages
+ * after SLIMbus comes out of clock pause.
+ * Transaction with slave fail before slave reports that message
+ * Give some time for that report to come
+ * SLIMbus wakes up in clock gear 10 at 24.576MHz. With each superframe
+ * being 250 usecs, we wait for 5-10 superframes here to ensure
+ * we get the message
+ */
+ usleep_range(1250, 2500);
+ return 0;
+}
+
void *slim_alloc_txbuf(struct qcom_slim_ctrl *ctrl, struct slim_msg_txn *txn,
struct completion *done)
{
@@ -511,6 +537,7 @@ static int qcom_slim_probe(struct platform_device *pdev)
sctrl->set_laddr = qcom_set_laddr;
sctrl->xfer_msg = qcom_xfer_msg;
+ sctrl->wakeup = qcom_clk_pause_wakeup;
ctrl->tx.n = QCOM_TX_MSGS;
ctrl->tx.sl_sz = SLIM_MSGQ_BUF_LEN;
ctrl->rx.n = QCOM_RX_MSGS;
@@ -618,14 +645,81 @@ static int qcom_slim_remove(struct platform_device *pdev)
{
struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev);
- disable_irq(ctrl->irq);
- clk_disable_unprepare(ctrl->hclk);
- clk_disable_unprepare(ctrl->rclk);
+ pm_runtime_disable(&pdev->dev);
slim_unregister_controller(&ctrl->ctrl);
destroy_workqueue(ctrl->rxwq);
return 0;
}
+/*
+ * If PM_RUNTIME is not defined, these 2 functions become helper
+ * functions to be called from system suspend/resume.
+ */
+#ifdef CONFIG_PM
+static int qcom_slim_runtime_suspend(struct device *device)
+{
+ struct platform_device *pdev = to_platform_device(device);
+ struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev);
+ int ret;
+
+ dev_dbg(device, "pm_runtime: suspending...\n");
+ ret = slim_ctrl_clk_pause(&ctrl->ctrl, false, SLIM_CLK_UNSPECIFIED);
+ if (ret) {
+ dev_err(device, "clk pause not entered:%d", ret);
+ } else {
+ disable_irq(ctrl->irq);
+ clk_disable_unprepare(ctrl->hclk);
+ clk_disable_unprepare(ctrl->rclk);
+ }
+ return ret;
+}
+
+static int qcom_slim_runtime_resume(struct device *device)
+{
+ struct platform_device *pdev = to_platform_device(device);
+ struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev);
+ int ret = 0;
+
+ dev_dbg(device, "pm_runtime: resuming...\n");
+ ret = slim_ctrl_clk_pause(&ctrl->ctrl, true, 0);
+ if (ret)
+ dev_err(device, "clk pause not exited:%d", ret);
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+static int qcom_slim_suspend(struct device *dev)
+{
+ int ret = 0;
+
+ if (!pm_runtime_enabled(dev) ||
+ (!pm_runtime_suspended(dev))) {
+ dev_dbg(dev, "system suspend");
+ ret = qcom_slim_runtime_suspend(dev);
+ }
+
+ return ret;
+}
+
+static int qcom_slim_resume(struct device *dev)
+{
+ if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
+ int ret;
+
+ dev_dbg(dev, "system resume");
+ ret = qcom_slim_runtime_resume(dev);
+ if (!ret) {
+ pm_runtime_mark_last_busy(dev);
+ pm_request_autosuspend(dev);
+ }
+ return ret;
+
+ }
+ return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
static const struct dev_pm_ops qcom_slim_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(qcom_slim_suspend, qcom_slim_resume)
SET_RUNTIME_PM_OPS(
@@ -647,6 +741,7 @@ static struct platform_driver qcom_slim_driver = {
.driver = {
.name = "qcom_slim_ctrl",
.of_match_table = qcom_slim_dt_match,
+ .pm = &qcom_slim_dev_pm_ops,
},
};
module_platform_driver(qcom_slim_driver);
--
2.15.0
^ permalink raw reply related
* [PATCH v10 11/13] slimbus: qcom: Add Qualcomm Slimbus controller driver
From: srinivas.kandagatla @ 2017-12-11 23:43 UTC (permalink / raw)
To: Mark Brown, Greg Kroah-Hartman, alsa-devel
Cc: sdharia, Rob Herring, Mark Rutland, Jonathan Corbet, pombredanne,
j.neuschaefer, linux-arm-msm, devicetree, linux-kernel, linux-doc,
Srinivas Kandagatla
In-Reply-To: <20171211234307.14465-1-srinivas.kandagatla@linaro.org>
From: Sagar Dharia <sdharia@codeaurora.org>
This controller driver programs manager, interface, and framer
devices for Qualcomm's slimbus HW block.
Manager component currently implements logical address setting,
and messaging interface.
Interface device reports bus synchronization information, and framer
device clocks the bus from the time it's woken up, until clock-pause
is executed by the manager device.
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
drivers/slimbus/Kconfig | 6 +
drivers/slimbus/Makefile | 4 +
drivers/slimbus/qcom-ctrl.c | 655 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 665 insertions(+)
create mode 100644 drivers/slimbus/qcom-ctrl.c
diff --git a/drivers/slimbus/Kconfig b/drivers/slimbus/Kconfig
index 9b6bb84d66ed..78bdd4808282 100644
--- a/drivers/slimbus/Kconfig
+++ b/drivers/slimbus/Kconfig
@@ -13,5 +13,11 @@ menuconfig SLIMBUS
if SLIMBUS
# SLIMbus controllers
+config SLIM_QCOM_CTRL
+ tristate "Qualcomm SLIMbus Manager Component"
+ depends on SLIMBUS
+ help
+ Select driver if Qualcomm's SLIMbus Manager Component is
+ programmed using Linux kernel.
endif
diff --git a/drivers/slimbus/Makefile b/drivers/slimbus/Makefile
index cd6833ed521a..a35a3da4eb78 100644
--- a/drivers/slimbus/Makefile
+++ b/drivers/slimbus/Makefile
@@ -4,3 +4,7 @@
#
obj-$(CONFIG_SLIMBUS) += slimbus.o
slimbus-y := core.o messaging.o sched.o
+
+#Controllers
+obj-$(CONFIG_SLIM_QCOM_CTRL) += slim-qcom-ctrl.o
+slim-qcom-ctrl-y := qcom-ctrl.o
diff --git a/drivers/slimbus/qcom-ctrl.c b/drivers/slimbus/qcom-ctrl.c
new file mode 100644
index 000000000000..ace85ce3de90
--- /dev/null
+++ b/drivers/slimbus/qcom-ctrl.c
@@ -0,0 +1,655 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2011-2017, The Linux Foundation
+ */
+
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/dma-mapping.h>
+#include "slimbus.h"
+
+/* Manager registers */
+#define MGR_CFG 0x200
+#define MGR_STATUS 0x204
+#define MGR_INT_EN 0x210
+#define MGR_INT_STAT 0x214
+#define MGR_INT_CLR 0x218
+#define MGR_TX_MSG 0x230
+#define MGR_RX_MSG 0x270
+#define MGR_IE_STAT 0x2F0
+#define MGR_VE_STAT 0x300
+#define MGR_CFG_ENABLE 1
+
+/* Framer registers */
+#define FRM_CFG 0x400
+#define FRM_STAT 0x404
+#define FRM_INT_EN 0x410
+#define FRM_INT_STAT 0x414
+#define FRM_INT_CLR 0x418
+#define FRM_WAKEUP 0x41C
+#define FRM_CLKCTL_DONE 0x420
+#define FRM_IE_STAT 0x430
+#define FRM_VE_STAT 0x440
+
+/* Interface registers */
+#define INTF_CFG 0x600
+#define INTF_STAT 0x604
+#define INTF_INT_EN 0x610
+#define INTF_INT_STAT 0x614
+#define INTF_INT_CLR 0x618
+#define INTF_IE_STAT 0x630
+#define INTF_VE_STAT 0x640
+
+/* Interrupt status bits */
+#define MGR_INT_TX_NACKED_2 BIT(25)
+#define MGR_INT_MSG_BUF_CONTE BIT(26)
+#define MGR_INT_RX_MSG_RCVD BIT(30)
+#define MGR_INT_TX_MSG_SENT BIT(31)
+
+/* Framer config register settings */
+#define FRM_ACTIVE 1
+#define CLK_GEAR 7
+#define ROOT_FREQ 11
+#define REF_CLK_GEAR 15
+#define INTR_WAKE 19
+
+#define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \
+ ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16))
+
+#define SLIM_ROOT_FREQ 24576000
+
+/* MAX message size over control channel */
+#define SLIM_MSGQ_BUF_LEN 40
+#define QCOM_TX_MSGS 2
+#define QCOM_RX_MSGS 8
+#define QCOM_BUF_ALLOC_RETRIES 10
+
+#define CFG_PORT(r, v) ((v) ? CFG_PORT_V2(r) : CFG_PORT_V1(r))
+
+/* V2 Component registers */
+#define CFG_PORT_V2(r) ((r ## _V2))
+#define COMP_CFG_V2 4
+#define COMP_TRUST_CFG_V2 0x3000
+
+/* V1 Component registers */
+#define CFG_PORT_V1(r) ((r ## _V1))
+#define COMP_CFG_V1 0
+#define COMP_TRUST_CFG_V1 0x14
+
+/* Resource group info for manager, and non-ported generic device-components */
+#define EE_MGR_RSC_GRP (1 << 10)
+#define EE_NGD_2 (2 << 6)
+#define EE_NGD_1 0
+
+struct slim_ctrl_buf {
+ void *base;
+ phys_addr_t phy;
+ spinlock_t lock;
+ int head;
+ int tail;
+ int sl_sz;
+ int n;
+};
+
+struct qcom_slim_ctrl {
+ struct slim_controller ctrl;
+ struct slim_framer framer;
+ struct device *dev;
+ void __iomem *base;
+ void __iomem *slew_reg;
+
+ struct slim_ctrl_buf rx;
+ struct slim_ctrl_buf tx;
+
+ struct completion **wr_comp;
+ int irq;
+ struct workqueue_struct *rxwq;
+ struct work_struct wd;
+ struct clk *rclk;
+ struct clk *hclk;
+};
+
+static void qcom_slim_queue_tx(struct qcom_slim_ctrl *ctrl, void *buf,
+ u8 len, u32 tx_reg)
+{
+ int count = (len + 3) >> 2;
+
+ __iowrite32_copy(ctrl->base + tx_reg, buf, count);
+
+ /* Ensure Oder of subsequent writes */
+ mb();
+}
+
+static void *slim_alloc_rxbuf(struct qcom_slim_ctrl *ctrl)
+{
+ unsigned long flags;
+ int idx;
+
+ spin_lock_irqsave(&ctrl->rx.lock, flags);
+ if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) {
+ spin_unlock_irqrestore(&ctrl->rx.lock, flags);
+ dev_err(ctrl->dev, "RX QUEUE full!");
+ return NULL;
+ }
+ idx = ctrl->rx.tail;
+ ctrl->rx.tail = (ctrl->rx.tail + 1) % ctrl->rx.n;
+ spin_unlock_irqrestore(&ctrl->rx.lock, flags);
+
+ return ctrl->rx.base + (idx * ctrl->rx.sl_sz);
+}
+
+void slim_ack_txn(struct qcom_slim_ctrl *ctrl, int err)
+{
+ struct completion *comp;
+ unsigned long flags;
+ int idx;
+
+ spin_lock_irqsave(&ctrl->tx.lock, flags);
+ idx = ctrl->tx.head;
+ ctrl->tx.head = (ctrl->tx.head + 1) % ctrl->tx.n;
+ spin_unlock_irqrestore(&ctrl->tx.lock, flags);
+
+ comp = ctrl->wr_comp[idx];
+ ctrl->wr_comp[idx] = NULL;
+
+ complete(comp);
+}
+
+static irqreturn_t qcom_slim_handle_tx_irq(struct qcom_slim_ctrl *ctrl,
+ u32 stat)
+{
+ int err = 0;
+
+ if (stat & MGR_INT_TX_MSG_SENT)
+ writel_relaxed(MGR_INT_TX_MSG_SENT,
+ ctrl->base + MGR_INT_CLR);
+
+ if (stat & MGR_INT_TX_NACKED_2) {
+ u32 mgr_stat = readl_relaxed(ctrl->base + MGR_STATUS);
+ u32 mgr_ie_stat = readl_relaxed(ctrl->base + MGR_IE_STAT);
+ u32 frm_stat = readl_relaxed(ctrl->base + FRM_STAT);
+ u32 frm_cfg = readl_relaxed(ctrl->base + FRM_CFG);
+ u32 frm_intr_stat = readl_relaxed(ctrl->base + FRM_INT_STAT);
+ u32 frm_ie_stat = readl_relaxed(ctrl->base + FRM_IE_STAT);
+ u32 intf_stat = readl_relaxed(ctrl->base + INTF_STAT);
+ u32 intf_intr_stat = readl_relaxed(ctrl->base + INTF_INT_STAT);
+ u32 intf_ie_stat = readl_relaxed(ctrl->base + INTF_IE_STAT);
+
+ writel_relaxed(MGR_INT_TX_NACKED_2, ctrl->base + MGR_INT_CLR);
+
+ dev_err(ctrl->dev, "TX Nack MGR:int:0x%x, stat:0x%x\n",
+ stat, mgr_stat);
+ dev_err(ctrl->dev, "TX Nack MGR:ie:0x%x\n", mgr_ie_stat);
+ dev_err(ctrl->dev, "TX Nack FRM:int:0x%x, stat:0x%x\n",
+ frm_intr_stat, frm_stat);
+ dev_err(ctrl->dev, "TX Nack FRM:cfg:0x%x, ie:0x%x\n",
+ frm_cfg, frm_ie_stat);
+ dev_err(ctrl->dev, "TX Nack INTF:intr:0x%x, stat:0x%x\n",
+ intf_intr_stat, intf_stat);
+ dev_err(ctrl->dev, "TX Nack INTF:ie:0x%x\n",
+ intf_ie_stat);
+ err = -ENOTCONN;
+ }
+
+ slim_ack_txn(ctrl, err);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t qcom_slim_handle_rx_irq(struct qcom_slim_ctrl *ctrl,
+ u32 stat)
+{
+ u32 *rx_buf, pkt[10];
+ bool q_rx = false;
+ u8 mc, mt, len;
+
+ pkt[0] = readl_relaxed(ctrl->base + MGR_RX_MSG);
+ mt = SLIM_HEADER_GET_MT(pkt[0]);
+ len = SLIM_HEADER_GET_RL(pkt[0]);
+ mc = SLIM_HEADER_GET_MC(pkt[0]>>8);
+
+ /*
+ * this message cannot be handled by ISR, so
+ * let work-queue handle it
+ */
+ if (mt == SLIM_MSG_MT_CORE && mc == SLIM_MSG_MC_REPORT_PRESENT) {
+ rx_buf = (u32 *)slim_alloc_rxbuf(ctrl);
+ if (!rx_buf) {
+ dev_err(ctrl->dev, "dropping RX:0x%x due to RX full\n",
+ pkt[0]);
+ goto rx_ret_irq;
+ }
+ rx_buf[0] = pkt[0];
+
+ } else {
+ rx_buf = pkt;
+ }
+
+ __ioread32_copy(rx_buf + 1, ctrl->base + MGR_RX_MSG + 4,
+ DIV_ROUND_UP(len, 4));
+
+ switch (mc) {
+
+ case SLIM_MSG_MC_REPORT_PRESENT:
+ q_rx = true;
+ break;
+ case SLIM_MSG_MC_REPLY_INFORMATION:
+ case SLIM_MSG_MC_REPLY_VALUE:
+ slim_msg_response(&ctrl->ctrl, (u8 *)(rx_buf + 1),
+ (u8)(*rx_buf >> 24), (len - 4));
+ break;
+ default:
+ dev_err(ctrl->dev, "unsupported MC,%x MT:%x\n",
+ mc, mt);
+ break;
+ }
+rx_ret_irq:
+ writel(MGR_INT_RX_MSG_RCVD, ctrl->base +
+ MGR_INT_CLR);
+ if (q_rx)
+ queue_work(ctrl->rxwq, &ctrl->wd);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t qcom_slim_interrupt(int irq, void *d)
+{
+ struct qcom_slim_ctrl *ctrl = d;
+ u32 stat = readl_relaxed(ctrl->base + MGR_INT_STAT);
+ int ret = IRQ_NONE;
+
+ if (stat & MGR_INT_TX_MSG_SENT || stat & MGR_INT_TX_NACKED_2)
+ ret = qcom_slim_handle_tx_irq(ctrl, stat);
+
+ if (stat & MGR_INT_RX_MSG_RCVD)
+ ret = qcom_slim_handle_rx_irq(ctrl, stat);
+
+ return ret;
+}
+
+void *slim_alloc_txbuf(struct qcom_slim_ctrl *ctrl, struct slim_msg_txn *txn,
+ struct completion *done)
+{
+ unsigned long flags;
+ int idx;
+
+ spin_lock_irqsave(&ctrl->tx.lock, flags);
+ if (((ctrl->tx.head + 1) % ctrl->tx.n) == ctrl->tx.tail) {
+ spin_unlock_irqrestore(&ctrl->tx.lock, flags);
+ dev_err(ctrl->dev, "controller TX buf unavailable");
+ return NULL;
+ }
+ idx = ctrl->tx.tail;
+ ctrl->wr_comp[idx] = done;
+ ctrl->tx.tail = (ctrl->tx.tail + 1) % ctrl->tx.n;
+
+ spin_unlock_irqrestore(&ctrl->tx.lock, flags);
+
+ return ctrl->tx.base + (idx * ctrl->tx.sl_sz);
+}
+
+
+static int qcom_xfer_msg(struct slim_controller *sctrl,
+ struct slim_msg_txn *txn)
+{
+ struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
+ DECLARE_COMPLETION_ONSTACK(done);
+ void *pbuf = slim_alloc_txbuf(ctrl, txn, &done);
+ unsigned long ms = txn->rl + HZ;
+ u8 *puc;
+ int ret = 0, timeout, retries = QCOM_BUF_ALLOC_RETRIES;
+ u8 la = txn->la;
+ u32 *head;
+ /* HW expects length field to be excluded */
+ txn->rl--;
+
+ /* spin till buffer is made available */
+ if (!pbuf) {
+ while (retries--) {
+ usleep_range(10000, 15000);
+ pbuf = slim_alloc_txbuf(ctrl, txn, &done);
+ if (pbuf)
+ break;
+ }
+ }
+
+ if (!retries && !pbuf)
+ return -ENOMEM;
+
+ puc = (u8 *)pbuf;
+ head = (u32 *)pbuf;
+
+ if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) {
+ *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt,
+ txn->mc, 0, la);
+ puc += 3;
+ } else {
+ *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt,
+ txn->mc, 1, la);
+ puc += 2;
+ }
+
+ if (slim_tid_txn(txn->mt, txn->mc))
+ *(puc++) = txn->tid;
+
+ if (slim_ec_txn(txn->mt, txn->mc)) {
+ *(puc++) = (txn->ec & 0xFF);
+ *(puc++) = (txn->ec >> 8) & 0xFF;
+ }
+
+ if (txn->msg && txn->msg->wbuf)
+ memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);
+
+ qcom_slim_queue_tx(ctrl, head, txn->rl, MGR_TX_MSG);
+ timeout = wait_for_completion_timeout(&done, msecs_to_jiffies(ms));
+
+ if (!timeout) {
+ dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
+ txn->mt);
+ ret = -ETIMEDOUT;
+ }
+
+ return ret;
+
+}
+
+static int qcom_set_laddr(struct slim_controller *sctrl,
+ struct slim_eaddr *ead, u8 laddr)
+{
+ struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
+ struct {
+ __be16 manf_id;
+ __be16 prod_code;
+ u8 dev_index;
+ u8 instance;
+ u8 laddr;
+ } __packed p;
+ struct slim_val_inf msg = {0};
+ DEFINE_SLIM_EDEST_TXN(txn, SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS,
+ 10, laddr, &msg);
+ int ret;
+
+ p.manf_id = cpu_to_be16(ead->manf_id);
+ p.prod_code = cpu_to_be16(ead->prod_code);
+ p.dev_index = ead->dev_index;
+ p.instance = ead->instance;
+ p.laddr = laddr;
+
+ msg.wbuf = (void *)&p;
+ msg.num_bytes = 7;
+ ret = slim_do_transfer(&ctrl->ctrl, &txn);
+
+ if (ret)
+ dev_err(ctrl->dev, "set LA:0x%x failed:ret:%d\n",
+ laddr, ret);
+ return ret;
+}
+
+static int slim_get_current_rxbuf(struct qcom_slim_ctrl *ctrl, void *buf)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&ctrl->rx.lock, flags);
+ if (ctrl->rx.tail == ctrl->rx.head) {
+ spin_unlock_irqrestore(&ctrl->rx.lock, flags);
+ return -ENODATA;
+ }
+ memcpy(buf, ctrl->rx.base + (ctrl->rx.head * ctrl->rx.sl_sz),
+ ctrl->rx.sl_sz);
+
+ ctrl->rx.head = (ctrl->rx.head + 1) % ctrl->rx.n;
+ spin_unlock_irqrestore(&ctrl->rx.lock, flags);
+
+ return 0;
+}
+
+static void qcom_slim_rxwq(struct work_struct *work)
+{
+ u8 buf[SLIM_MSGQ_BUF_LEN];
+ u8 mc, mt, len;
+ int ret;
+ struct qcom_slim_ctrl *ctrl = container_of(work, struct qcom_slim_ctrl,
+ wd);
+
+ while ((slim_get_current_rxbuf(ctrl, buf)) != -ENODATA) {
+ len = SLIM_HEADER_GET_RL(buf[0]);
+ mt = SLIM_HEADER_GET_MT(buf[0]);
+ mc = SLIM_HEADER_GET_MC(buf[1]);
+ if (mt == SLIM_MSG_MT_CORE &&
+ mc == SLIM_MSG_MC_REPORT_PRESENT) {
+ struct slim_eaddr ea;
+ u8 laddr;
+
+ ea.manf_id = be16_to_cpup((__be16 *)&buf[2]);
+ ea.prod_code = be16_to_cpup((__be16 *)&buf[4]);
+ ea.dev_index = buf[6];
+ ea.instance = buf[7];
+
+ ret = slim_device_report_present(&ctrl->ctrl, &ea,
+ &laddr);
+ if (ret < 0)
+ dev_err(ctrl->dev, "assign laddr failed:%d\n",
+ ret);
+ } else {
+ dev_err(ctrl->dev, "unexpected message:mc:%x, mt:%x\n",
+ mc, mt);
+ }
+ }
+}
+
+static void qcom_slim_prg_slew(struct platform_device *pdev,
+ struct qcom_slim_ctrl *ctrl)
+{
+ struct resource *slew_mem;
+
+ if (!ctrl->slew_reg) {
+ /* SLEW RATE register for this SLIMbus */
+ slew_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "slew");
+ ctrl->slew_reg = devm_ioremap(&pdev->dev, slew_mem->start,
+ resource_size(slew_mem));
+ if (!ctrl->slew_reg)
+ return;
+ }
+
+ writel_relaxed(1, ctrl->slew_reg);
+ /* Make sure SLIMbus-slew rate enabling goes through */
+ wmb();
+}
+
+static int qcom_slim_probe(struct platform_device *pdev)
+{
+ struct qcom_slim_ctrl *ctrl;
+ struct slim_controller *sctrl;
+ struct resource *slim_mem;
+ int ret, ver;
+
+ ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
+ if (!ctrl)
+ return -ENOMEM;
+
+ ctrl->hclk = devm_clk_get(&pdev->dev, "iface");
+ if (IS_ERR(ctrl->hclk))
+ return PTR_ERR(ctrl->hclk);
+
+ ctrl->rclk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(ctrl->rclk))
+ return PTR_ERR(ctrl->rclk);
+
+ ret = clk_set_rate(ctrl->rclk, SLIM_ROOT_FREQ);
+ if (ret) {
+ dev_err(&pdev->dev, "ref-clock set-rate failed:%d\n", ret);
+ return ret;
+ }
+
+ ctrl->irq = platform_get_irq(pdev, 0);
+ if (!ctrl->irq) {
+ dev_err(&pdev->dev, "no slimbus IRQ\n");
+ return -ENODEV;
+ }
+
+ sctrl = &ctrl->ctrl;
+ sctrl->dev = &pdev->dev;
+ ctrl->dev = &pdev->dev;
+ platform_set_drvdata(pdev, ctrl);
+ dev_set_drvdata(ctrl->dev, ctrl);
+
+ slim_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
+ ctrl->base = devm_ioremap_resource(ctrl->dev, slim_mem);
+ if (!ctrl->base) {
+ dev_err(&pdev->dev, "IOremap failed\n");
+ return -ENOMEM;
+ }
+
+ sctrl->set_laddr = qcom_set_laddr;
+ sctrl->xfer_msg = qcom_xfer_msg;
+ ctrl->tx.n = QCOM_TX_MSGS;
+ ctrl->tx.sl_sz = SLIM_MSGQ_BUF_LEN;
+ ctrl->rx.n = QCOM_RX_MSGS;
+ ctrl->rx.sl_sz = SLIM_MSGQ_BUF_LEN;
+ ctrl->wr_comp = kzalloc(sizeof(struct completion *) * QCOM_TX_MSGS,
+ GFP_KERNEL);
+ if (!ctrl->wr_comp)
+ return -ENOMEM;
+
+ spin_lock_init(&ctrl->rx.lock);
+ spin_lock_init(&ctrl->tx.lock);
+ INIT_WORK(&ctrl->wd, qcom_slim_rxwq);
+ ctrl->rxwq = create_singlethread_workqueue("qcom_slim_rx");
+ if (!ctrl->rxwq) {
+ dev_err(ctrl->dev, "Failed to start Rx WQ\n");
+ return -ENOMEM;
+ }
+
+ ctrl->framer.rootfreq = SLIM_ROOT_FREQ / 8;
+ ctrl->framer.superfreq =
+ ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8;
+ sctrl->a_framer = &ctrl->framer;
+ sctrl->clkgear = SLIM_MAX_CLK_GEAR;
+
+ qcom_slim_prg_slew(pdev, ctrl);
+
+ ret = devm_request_irq(&pdev->dev, ctrl->irq, qcom_slim_interrupt,
+ IRQF_TRIGGER_HIGH, "qcom_slim_irq", ctrl);
+ if (ret) {
+ dev_err(&pdev->dev, "request IRQ failed\n");
+ goto err_request_irq_failed;
+ }
+
+ ret = clk_prepare_enable(ctrl->hclk);
+ if (ret)
+ goto err_hclk_enable_failed;
+
+ ret = clk_prepare_enable(ctrl->rclk);
+ if (ret)
+ goto err_rclk_enable_failed;
+
+ ctrl->tx.base = dmam_alloc_coherent(&pdev->dev,
+ (ctrl->tx.sl_sz * ctrl->tx.n),
+ &ctrl->tx.phy, GFP_KERNEL);
+ if (!ctrl->tx.base) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ctrl->rx.base = dmam_alloc_coherent(&pdev->dev,
+ (ctrl->rx.sl_sz * ctrl->rx.n),
+ &ctrl->rx.phy, GFP_KERNEL);
+ if (!ctrl->rx.base) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ /* Register with framework before enabling frame, clock */
+ ret = slim_register_controller(&ctrl->ctrl);
+ if (ret) {
+ dev_err(ctrl->dev, "error adding controller\n");
+ goto err;
+ }
+
+ ver = readl_relaxed(ctrl->base);
+ /* Version info in 16 MSbits */
+ ver >>= 16;
+ /* Component register initialization */
+ writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver));
+ writel((EE_MGR_RSC_GRP | EE_NGD_2 | EE_NGD_1),
+ ctrl->base + CFG_PORT(COMP_TRUST_CFG, ver));
+
+ writel((MGR_INT_TX_NACKED_2 |
+ MGR_INT_MSG_BUF_CONTE | MGR_INT_RX_MSG_RCVD |
+ MGR_INT_TX_MSG_SENT), ctrl->base + MGR_INT_EN);
+ writel(1, ctrl->base + MGR_CFG);
+ /* Framer register initialization */
+ writel((1 << INTR_WAKE) | (0xA << REF_CLK_GEAR) |
+ (0xA << CLK_GEAR) | (1 << ROOT_FREQ) | (1 << FRM_ACTIVE) | 1,
+ ctrl->base + FRM_CFG);
+ writel(MGR_CFG_ENABLE, ctrl->base + MGR_CFG);
+ writel(1, ctrl->base + INTF_CFG);
+ writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver));
+
+ pm_runtime_use_autosuspend(&pdev->dev);
+ pm_runtime_set_autosuspend_delay(&pdev->dev, QCOM_SLIM_AUTOSUSPEND);
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_mark_last_busy(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+
+ dev_dbg(ctrl->dev, "QCOM SB controller is up:ver:0x%x!\n", ver);
+ return 0;
+
+err:
+ clk_disable_unprepare(ctrl->rclk);
+err_rclk_enable_failed:
+ clk_disable_unprepare(ctrl->hclk);
+err_hclk_enable_failed:
+err_request_irq_failed:
+ destroy_workqueue(ctrl->rxwq);
+ return ret;
+}
+
+static int qcom_slim_remove(struct platform_device *pdev)
+{
+ struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev);
+
+ disable_irq(ctrl->irq);
+ clk_disable_unprepare(ctrl->hclk);
+ clk_disable_unprepare(ctrl->rclk);
+ slim_unregister_controller(&ctrl->ctrl);
+ destroy_workqueue(ctrl->rxwq);
+ return 0;
+}
+
+static const struct dev_pm_ops qcom_slim_dev_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(qcom_slim_suspend, qcom_slim_resume)
+ SET_RUNTIME_PM_OPS(
+ qcom_slim_runtime_suspend,
+ qcom_slim_runtime_resume,
+ NULL
+ )
+};
+
+static const struct of_device_id qcom_slim_dt_match[] = {
+ { .compatible = "qcom,slim", },
+ { .compatible = "qcom,apq8064-slim", },
+ {}
+};
+
+static struct platform_driver qcom_slim_driver = {
+ .probe = qcom_slim_probe,
+ .remove = qcom_slim_remove,
+ .driver = {
+ .name = "qcom_slim_ctrl",
+ .of_match_table = qcom_slim_dt_match,
+ },
+};
+module_platform_driver(qcom_slim_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Qualcomm SLIMbus Controller");
--
2.15.0
^ permalink raw reply related
* [PATCH v10 10/13] dt-bindings: Add qcom slimbus controller bindings
From: srinivas.kandagatla @ 2017-12-11 23:43 UTC (permalink / raw)
To: Mark Brown, Greg Kroah-Hartman, alsa-devel
Cc: Mark Rutland, devicetree, Jonathan Corbet, linux-arm-msm,
linux-doc, j.neuschaefer, linux-kernel, Rob Herring,
Srinivas Kandagatla, pombredanne, sdharia
In-Reply-To: <20171211234307.14465-1-srinivas.kandagatla@linaro.org>
From: Sagar Dharia <sdharia@codeaurora.org>
This patch add device tree bindings for Qualcomm slimbus controller.
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/slimbus/slim-qcom-ctrl.txt | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/slimbus/slim-qcom-ctrl.txt
diff --git a/Documentation/devicetree/bindings/slimbus/slim-qcom-ctrl.txt b/Documentation/devicetree/bindings/slimbus/slim-qcom-ctrl.txt
new file mode 100644
index 000000000000..922dcb8ff24a
--- /dev/null
+++ b/Documentation/devicetree/bindings/slimbus/slim-qcom-ctrl.txt
@@ -0,0 +1,39 @@
+Qualcomm SLIMbus controller
+This controller is used if applications processor driver controls SLIMbus
+master component.
+
+Required properties:
+
+ - #address-cells - refer to Documentation/devicetree/bindings/slimbus/bus.txt
+ - #size-cells - refer to Documentation/devicetree/bindings/slimbus/bus.txt
+
+ - reg : Offset and length of the register region(s) for the device
+ - reg-names : Register region name(s) referenced in reg above
+ Required register resource entries are:
+ "ctrl": Physical address of controller register blocks
+ "slew": required for "qcom,apq8064-slim" SOC.
+ - compatible : should be "qcom,<SOC-NAME>-slim" for SOC specific compatible
+ followed by "qcom,slim" for fallback.
+ - interrupts : Interrupt number used by this controller
+ - clocks : Interface and core clocks used by this SLIMbus controller
+ - clock-names : Required clock-name entries are:
+ "iface" : Interface clock for this controller
+ "core" : Interrupt for controller core's BAM
+
+Example:
+
+ slim@28080000 {
+ compatible = "qcom,apq8064-slim", "qcom,slim";
+ reg = <0x28080000 0x2000>, <0x80207C 4>;
+ reg-names = "ctrl", "slew";
+ interrupts = <0 33 0>;
+ clocks = <&lcc SLIMBUS_SRC>, <&lcc AUDIO_SLIMBUS_CLK>;
+ clock-names = "iface", "core";
+ #address-cells = <2>;
+ #size-cell = <0>;
+
+ wcd9310: audio-codec@1,0{
+ compatible = "slim217,60";
+ reg = <1 0>;
+ };
+ };
--
2.15.0
^ permalink raw reply related
* [PATCH v10 09/13] slimbus: core: add common defines required for controllers
From: srinivas.kandagatla @ 2017-12-11 23:43 UTC (permalink / raw)
To: Mark Brown, Greg Kroah-Hartman, alsa-devel
Cc: Mark Rutland, devicetree, Jonathan Corbet, linux-arm-msm,
linux-doc, j.neuschaefer, linux-kernel, Rob Herring,
Srinivas Kandagatla, pombredanne, sdharia
In-Reply-To: <20171211234307.14465-1-srinivas.kandagatla@linaro.org>
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
This patch adds some common constant defines which are required
for qcom slim controller driver.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
drivers/slimbus/slimbus.h | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/slimbus/slimbus.h b/drivers/slimbus/slimbus.h
index db089134f673..79f8e05d92dd 100644
--- a/drivers/slimbus/slimbus.h
+++ b/drivers/slimbus/slimbus.h
@@ -11,9 +11,38 @@
#include <linux/completion.h>
#include <linux/slimbus.h>
+/* Standard values per SLIMbus spec needed by controllers and devices */
+#define SLIM_CL_PER_SUPERFRAME 6144
+#define SLIM_CL_PER_SUPERFRAME_DIV8 (SLIM_CL_PER_SUPERFRAME >> 3)
+
/* SLIMbus message types. Related to interpretation of message code. */
#define SLIM_MSG_MT_CORE 0x0
+/*
+ * SLIM Broadcast header format
+ * BYTE 0: MT[7:5] RL[4:0]
+ * BYTE 1: RSVD[7] MC[6:0]
+ * BYTE 2: RSVD[7:6] DT[5:4] PI[3:0]
+ */
+#define SLIM_MSG_MT_MASK GENMASK(2, 0)
+#define SLIM_MSG_MT_SHIFT 5
+#define SLIM_MSG_RL_MASK GENMASK(4, 0)
+#define SLIM_MSG_RL_SHIFT 0
+#define SLIM_MSG_MC_MASK GENMASK(6, 0)
+#define SLIM_MSG_MC_SHIFT 0
+#define SLIM_MSG_DT_MASK GENMASK(1, 0)
+#define SLIM_MSG_DT_SHIFT 4
+
+#define SLIM_HEADER_GET_MT(b) ((b >> SLIM_MSG_MT_SHIFT) & SLIM_MSG_MT_MASK)
+#define SLIM_HEADER_GET_RL(b) ((b >> SLIM_MSG_RL_SHIFT) & SLIM_MSG_RL_MASK)
+#define SLIM_HEADER_GET_MC(b) ((b >> SLIM_MSG_MC_SHIFT) & SLIM_MSG_MC_MASK)
+#define SLIM_HEADER_GET_DT(b) ((b >> SLIM_MSG_DT_SHIFT) & SLIM_MSG_DT_MASK)
+
+/* Device management messages used by this framework */
+#define SLIM_MSG_MC_REPORT_PRESENT 0x1
+#define SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS 0x2
+#define SLIM_MSG_MC_REPORT_ABSENT 0xF
+
/* Clock pause Reconfiguration messages */
#define SLIM_MSG_MC_BEGIN_RECONFIGURATION 0x40
#define SLIM_MSG_MC_NEXT_PAUSE_CLOCK 0x4A
@@ -94,6 +123,10 @@ struct slim_msg_txn {
#define DEFINE_SLIM_BCAST_TXN(name, mc, rl, la, msg) \
struct slim_msg_txn name = { rl, 0, mc, SLIM_MSG_DEST_BROADCAST, 0,\
0, la, msg, }
+
+#define DEFINE_SLIM_EDEST_TXN(name, mc, rl, la, msg) \
+ struct slim_msg_txn name = { rl, 0, mc, SLIM_MSG_DEST_ENUMADDR, 0,\
+ 0, la, msg, }
/**
* enum slim_clk_state: SLIMbus controller's clock state used internally for
* maintaining current clock state.
--
2.15.0
^ permalink raw reply related
* [PATCH v10 08/13] regmap: add SLIMbus support
From: srinivas.kandagatla @ 2017-12-11 23:43 UTC (permalink / raw)
To: Mark Brown, Greg Kroah-Hartman, alsa-devel
Cc: Mark Rutland, devicetree, Jonathan Corbet, linux-arm-msm,
linux-doc, j.neuschaefer, linux-kernel, Rob Herring,
Srinivas Kandagatla, pombredanne, sdharia
In-Reply-To: <20171211234307.14465-1-srinivas.kandagatla@linaro.org>
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
This patch adds support to read/write SLIMbus value elements.
Currently it only supports byte read/write. Adding this support in
regmap would give codec drivers more flexibility when there are more
than 2 control interfaces like SLIMbus, i2c.
Without this patch each codec driver has to directly call SLIMbus value
element apis, and this could would get messy once we want to add i2c
interface to it.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
drivers/base/regmap/Kconfig | 4 ++
drivers/base/regmap/Makefile | 1 +
drivers/base/regmap/regmap-slimbus.c | 80 ++++++++++++++++++++++++++++++++++++
include/linux/regmap.h | 18 ++++++++
4 files changed, 103 insertions(+)
create mode 100644 drivers/base/regmap/regmap-slimbus.c
diff --git a/drivers/base/regmap/Kconfig b/drivers/base/regmap/Kconfig
index 3a1535d812d8..cc162b48c6d7 100644
--- a/drivers/base/regmap/Kconfig
+++ b/drivers/base/regmap/Kconfig
@@ -21,6 +21,10 @@ config REGMAP_I2C
tristate
depends on I2C
+config REGMAP_SLIMBUS
+ tristate
+ depends on SLIMBUS
+
config REGMAP_SPI
tristate
depends on SPI
diff --git a/drivers/base/regmap/Makefile b/drivers/base/regmap/Makefile
index 0d298c446108..63dec9222892 100644
--- a/drivers/base/regmap/Makefile
+++ b/drivers/base/regmap/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_REGCACHE_COMPRESSED) += regcache-lzo.o
obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o
obj-$(CONFIG_REGMAP_AC97) += regmap-ac97.o
obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o
+obj-$(CONFIG_REGMAP_SLIMBUS) += regmap-slimbus.o
obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o
obj-$(CONFIG_REGMAP_SPMI) += regmap-spmi.o
obj-$(CONFIG_REGMAP_MMIO) += regmap-mmio.o
diff --git a/drivers/base/regmap/regmap-slimbus.c b/drivers/base/regmap/regmap-slimbus.c
new file mode 100644
index 000000000000..c90bee81d954
--- /dev/null
+++ b/drivers/base/regmap/regmap-slimbus.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017, Linaro Ltd.
+
+#include <linux/regmap.h>
+#include <linux/slimbus.h>
+#include <linux/module.h>
+
+#include "internal.h"
+
+static int regmap_slimbus_byte_reg_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+ struct slim_device *sdev = context;
+ int v;
+
+ v = slim_readb(sdev, reg);
+
+ if (v < 0)
+ return v;
+
+ *val = v;
+
+ return 0;
+}
+
+static int regmap_slimbus_byte_reg_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ struct slim_device *sdev = context;
+
+ return slim_writeb(sdev, reg, val);
+}
+
+static struct regmap_bus regmap_slimbus_bus = {
+ .reg_write = regmap_slimbus_byte_reg_write,
+ .reg_read = regmap_slimbus_byte_reg_read,
+ .reg_format_endian_default = REGMAP_ENDIAN_LITTLE,
+ .val_format_endian_default = REGMAP_ENDIAN_LITTLE,
+};
+
+static const struct regmap_bus *regmap_get_slimbus(struct slim_device *slim,
+ const struct regmap_config *config)
+{
+ if (config->val_bits == 8 && config->reg_bits == 8)
+ return ®map_slimbus_bus;
+
+ return ERR_PTR(-ENOTSUPP);
+}
+
+struct regmap *__regmap_init_slimbus(struct slim_device *slimbus,
+ const struct regmap_config *config,
+ struct lock_class_key *lock_key,
+ const char *lock_name)
+{
+ const struct regmap_bus *bus = regmap_get_slimbus(slimbus, config);
+
+ if (IS_ERR(bus))
+ return ERR_CAST(bus);
+
+ return __regmap_init(&slimbus->dev, bus, &slimbus->dev, config,
+ lock_key, lock_name);
+}
+EXPORT_SYMBOL_GPL(__regmap_init_slimbus);
+
+struct regmap *__devm_regmap_init_slimbus(struct slim_device *slimbus,
+ const struct regmap_config *config,
+ struct lock_class_key *lock_key,
+ const char *lock_name)
+{
+ const struct regmap_bus *bus = regmap_get_slimbus(slimbus, config);
+
+ if (IS_ERR(bus))
+ return ERR_CAST(bus);
+
+ return __devm_regmap_init(&slimbus->dev, bus, &slimbus, config,
+ lock_key, lock_name);
+}
+EXPORT_SYMBOL_GPL(__devm_regmap_init_slimbus);
+
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index 15eddc1353ba..b2207737a159 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -24,6 +24,7 @@ struct module;
struct device;
struct i2c_client;
struct irq_domain;
+struct slim_device;
struct spi_device;
struct spmi_device;
struct regmap;
@@ -499,6 +500,10 @@ struct regmap *__regmap_init_i2c(struct i2c_client *i2c,
const struct regmap_config *config,
struct lock_class_key *lock_key,
const char *lock_name);
+struct regmap *__regmap_init_slimbus(struct slim_device *slimbus,
+ const struct regmap_config *config,
+ struct lock_class_key *lock_key,
+ const char *lock_name);
struct regmap *__regmap_init_spi(struct spi_device *dev,
const struct regmap_config *config,
struct lock_class_key *lock_key,
@@ -615,6 +620,19 @@ int regmap_attach_dev(struct device *dev, struct regmap *map,
__regmap_lockdep_wrapper(__regmap_init_i2c, #config, \
i2c, config)
+/**
+ * regmap_init_slimbus() - Initialise register map
+ *
+ * @slimbus: Device that will be interacted with
+ * @config: Configuration for register map
+ *
+ * The return value will be an ERR_PTR() on error or a valid pointer to
+ * a struct regmap.
+ */
+#define regmap_init_slimbus(slimbus, config) \
+ __regmap_lockdep_wrapper(__regmap_init_slimbus, #config, \
+ slimbus, config)
+
/**
* regmap_init_spi() - Initialise register map
*
--
2.15.0
^ permalink raw reply related
* [PATCH v10 07/13] slimbus: Add support for 'clock-pause' feature
From: srinivas.kandagatla @ 2017-12-11 23:43 UTC (permalink / raw)
To: Mark Brown, Greg Kroah-Hartman, alsa-devel
Cc: Mark Rutland, devicetree, Jonathan Corbet, linux-arm-msm,
linux-doc, j.neuschaefer, linux-kernel, Rob Herring,
Srinivas Kandagatla, pombredanne, sdharia
In-Reply-To: <20171211234307.14465-1-srinivas.kandagatla@linaro.org>
From: Sagar Dharia <sdharia@codeaurora.org>
Per SLIMbus specification, a reconfiguration sequence known as
'clock pause' needs to be broadcast over the bus while entering low-
power mode. Clock-pause is initiated by the controller driver.
To exit clock-pause, controller typically wakes up the framer device.
Since wakeup precedure is controller-specific, framework calls it via
controller's function pointer to invoke it.
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
drivers/slimbus/Makefile | 2 +-
drivers/slimbus/core.c | 16 ++++++
drivers/slimbus/messaging.c | 35 ++++++++++++-
drivers/slimbus/sched.c | 121 ++++++++++++++++++++++++++++++++++++++++++++
drivers/slimbus/slimbus.h | 53 +++++++++++++++++++
5 files changed, 225 insertions(+), 2 deletions(-)
create mode 100644 drivers/slimbus/sched.c
diff --git a/drivers/slimbus/Makefile b/drivers/slimbus/Makefile
index 568a14c7be78..cd6833ed521a 100644
--- a/drivers/slimbus/Makefile
+++ b/drivers/slimbus/Makefile
@@ -3,4 +3,4 @@
# Makefile for kernel SLIMbus framework.
#
obj-$(CONFIG_SLIMBUS) += slimbus.o
-slimbus-y := core.o messaging.o
+slimbus-y := core.o messaging.o sched.o
diff --git a/drivers/slimbus/core.c b/drivers/slimbus/core.c
index 1accb20ed5cd..4988a8f4d905 100644
--- a/drivers/slimbus/core.c
+++ b/drivers/slimbus/core.c
@@ -9,6 +9,7 @@
#include <linux/init.h>
#include <linux/idr.h>
#include <linux/of.h>
+#include <linux/pm_runtime.h>
#include <linux/slimbus.h>
#include "slimbus.h"
@@ -218,6 +219,8 @@ int slim_register_controller(struct slim_controller *ctrl)
ida_init(&ctrl->laddr_ida);
idr_init(&ctrl->tid_idr);
mutex_init(&ctrl->lock);
+ mutex_init(&ctrl->sched.m_reconf);
+ init_completion(&ctrl->sched.pause_comp);
dev_dbg(ctrl->dev, "Bus [%s] registered:dev:%p\n",
ctrl->name, ctrl->dev);
@@ -249,6 +252,8 @@ int slim_unregister_controller(struct slim_controller *ctrl)
{
/* Remove all clients */
device_for_each_child(ctrl->dev, NULL, slim_ctrl_remove_device);
+ /* Enter Clock Pause */
+ slim_ctrl_clk_pause(ctrl, false, 0);
ida_simple_remove(&ctrl_ida, ctrl->id);
return 0;
@@ -416,6 +421,14 @@ int slim_device_report_present(struct slim_controller *ctrl,
struct slim_device *sbdev;
int ret;
+ ret = pm_runtime_get_sync(ctrl->dev);
+
+ if (ctrl->sched.clk_state != SLIM_CLK_ACTIVE) {
+ dev_err(ctrl->dev, "slim ctrl not active,state:%d, ret:%d\n",
+ ctrl->sched.clk_state, ret);
+ goto slimbus_not_active;
+ }
+
sbdev = slim_get_device(ctrl, e_addr);
if (IS_ERR(sbdev))
return -ENODEV;
@@ -427,6 +440,9 @@ int slim_device_report_present(struct slim_controller *ctrl,
ret = slim_device_alloc_laddr(sbdev, true);
+slimbus_not_active:
+ pm_runtime_mark_last_busy(ctrl->dev);
+ pm_runtime_put_autosuspend(ctrl->dev);
return ret;
}
EXPORT_SYMBOL_GPL(slim_device_report_present);
diff --git a/drivers/slimbus/messaging.c b/drivers/slimbus/messaging.c
index 031e67648d7c..755462a4c75e 100644
--- a/drivers/slimbus/messaging.c
+++ b/drivers/slimbus/messaging.c
@@ -4,6 +4,7 @@
*/
#include <linux/slab.h>
+#include <linux/pm_runtime.h>
#include "slimbus.h"
/**
@@ -46,6 +47,10 @@ void slim_msg_response(struct slim_controller *ctrl, u8 *reply, u8 tid, u8 len)
memcpy(msg->rbuf, reply, len);
if (txn->comp)
complete(txn->comp);
+
+ /* Remove runtime-pm vote now that response was received for TID txn */
+ pm_runtime_mark_last_busy(ctrl->dev);
+ pm_runtime_put_autosuspend(ctrl->dev);
}
EXPORT_SYMBOL_GPL(slim_msg_response);
@@ -65,10 +70,29 @@ EXPORT_SYMBOL_GPL(slim_msg_response);
int slim_do_transfer(struct slim_controller *ctrl, struct slim_msg_txn *txn)
{
DECLARE_COMPLETION_ONSTACK(done);
- bool need_tid;
+ bool need_tid = false, clk_pause_msg = false;
unsigned long flags;
int ret, tid, timeout;
+ /*
+ * do not vote for runtime-PM if the transactions are part of clock
+ * pause sequence
+ */
+ if (ctrl->sched.clk_state == SLIM_CLK_ENTERING_PAUSE &&
+ (txn->mt == SLIM_MSG_MT_CORE &&
+ txn->mc >= SLIM_MSG_MC_BEGIN_RECONFIGURATION &&
+ txn->mc <= SLIM_MSG_MC_RECONFIGURE_NOW))
+ clk_pause_msg = true;
+
+ if (!clk_pause_msg) {
+ ret = pm_runtime_get_sync(ctrl->dev);
+ if (ctrl->sched.clk_state != SLIM_CLK_ACTIVE) {
+ dev_err(ctrl->dev, "ctrl wrong state:%d, ret:%d\n",
+ ctrl->sched.clk_state, ret);
+ goto slim_xfer_err;
+ }
+ }
+
need_tid = slim_tid_txn(txn->mt, txn->mc);
if (need_tid) {
@@ -107,6 +131,15 @@ int slim_do_transfer(struct slim_controller *ctrl, struct slim_msg_txn *txn)
dev_err(ctrl->dev, "Tx:MT:0x%x, MC:0x%x, LA:0x%x failed:%d\n",
txn->mt, txn->mc, txn->la, ret);
+slim_xfer_err:
+ if (!clk_pause_msg && (!need_tid || ret == -ETIMEDOUT)) {
+ /*
+ * remove runtime-pm vote if this was TX only, or
+ * if there was error during this transaction
+ */
+ pm_runtime_mark_last_busy(ctrl->dev);
+ pm_runtime_mark_last_busy(ctrl->dev);
+ }
return ret;
}
EXPORT_SYMBOL_GPL(slim_do_transfer);
diff --git a/drivers/slimbus/sched.c b/drivers/slimbus/sched.c
new file mode 100644
index 000000000000..af84997d2742
--- /dev/null
+++ b/drivers/slimbus/sched.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2011-2017, The Linux Foundation
+ */
+
+#include <linux/errno.h>
+#include "slimbus.h"
+
+/**
+ * slim_ctrl_clk_pause() - Called by slimbus controller to enter/exit
+ * 'clock pause'
+ * @ctrl: controller requesting bus to be paused or woken up
+ * @wakeup: Wakeup this controller from clock pause.
+ * @restart: Restart time value per spec used for clock pause. This value
+ * isn't used when controller is to be woken up.
+ *
+ * Slimbus specification needs this sequence to turn-off clocks for the bus.
+ * The sequence involves sending 3 broadcast messages (reconfiguration
+ * sequence) to inform all devices on the bus.
+ * To exit clock-pause, controller typically wakes up active framer device.
+ * This API executes clock pause reconfiguration sequence if wakeup is false.
+ * If wakeup is true, controller's wakeup is called.
+ * For entering clock-pause, -EBUSY is returned if a message txn in pending.
+ */
+int slim_ctrl_clk_pause(struct slim_controller *ctrl, bool wakeup, u8 restart)
+{
+ int i, ret = 0;
+ unsigned long flags;
+ struct slim_sched *sched = &ctrl->sched;
+ struct slim_val_inf msg = {0, 0, NULL, NULL};
+
+ DEFINE_SLIM_BCAST_TXN(txn, SLIM_MSG_MC_BEGIN_RECONFIGURATION,
+ 3, SLIM_LA_MANAGER, &msg);
+
+ if (wakeup == false && restart > SLIM_CLK_UNSPECIFIED)
+ return -EINVAL;
+
+ mutex_lock(&sched->m_reconf);
+ if (wakeup) {
+ if (sched->clk_state == SLIM_CLK_ACTIVE) {
+ mutex_unlock(&sched->m_reconf);
+ return 0;
+ }
+
+ /*
+ * Fine-tune calculation based on clock gear,
+ * message-bandwidth after bandwidth management
+ */
+ ret = wait_for_completion_timeout(&sched->pause_comp,
+ msecs_to_jiffies(100));
+ if (!ret) {
+ mutex_unlock(&sched->m_reconf);
+ pr_err("Previous clock pause did not finish");
+ return -ETIMEDOUT;
+ }
+ ret = 0;
+
+ /*
+ * Slimbus framework will call controller wakeup
+ * Controller should make sure that it sets active framer
+ * out of clock pause
+ */
+ if (sched->clk_state == SLIM_CLK_PAUSED && ctrl->wakeup)
+ ret = ctrl->wakeup(ctrl);
+ if (!ret)
+ sched->clk_state = SLIM_CLK_ACTIVE;
+ mutex_unlock(&sched->m_reconf);
+
+ return ret;
+ }
+
+ /* already paused */
+ if (ctrl->sched.clk_state == SLIM_CLK_PAUSED) {
+ mutex_unlock(&sched->m_reconf);
+ return 0;
+ }
+
+ spin_lock_irqsave(&ctrl->txn_lock, flags);
+ for (i = 0; i < SLIM_MAX_TIDS; i++) {
+ /* Pending response for a message */
+ if (idr_find(&ctrl->tid_idr, i)) {
+ spin_unlock_irqrestore(&ctrl->txn_lock, flags);
+ mutex_unlock(&sched->m_reconf);
+ return -EBUSY;
+ }
+ }
+ spin_unlock_irqrestore(&ctrl->txn_lock, flags);
+
+ sched->clk_state = SLIM_CLK_ENTERING_PAUSE;
+
+ /* clock pause sequence */
+ ret = slim_do_transfer(ctrl, &txn);
+ if (ret)
+ goto clk_pause_ret;
+
+ txn.mc = SLIM_MSG_MC_NEXT_PAUSE_CLOCK;
+ txn.rl = 4;
+ msg.num_bytes = 1;
+ msg.wbuf = &restart;
+ ret = slim_do_transfer(ctrl, &txn);
+ if (ret)
+ goto clk_pause_ret;
+
+ txn.mc = SLIM_MSG_MC_RECONFIGURE_NOW;
+ txn.rl = 3;
+ msg.num_bytes = 1;
+ msg.wbuf = NULL;
+ ret = slim_do_transfer(ctrl, &txn);
+
+clk_pause_ret:
+ if (ret) {
+ sched->clk_state = SLIM_CLK_ACTIVE;
+ } else {
+ sched->clk_state = SLIM_CLK_PAUSED;
+ complete(&sched->pause_comp);
+ }
+ mutex_unlock(&sched->m_reconf);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(slim_ctrl_clk_pause);
diff --git a/drivers/slimbus/slimbus.h b/drivers/slimbus/slimbus.h
index 0d40c2578c28..db089134f673 100644
--- a/drivers/slimbus/slimbus.h
+++ b/drivers/slimbus/slimbus.h
@@ -14,6 +14,16 @@
/* SLIMbus message types. Related to interpretation of message code. */
#define SLIM_MSG_MT_CORE 0x0
+/* Clock pause Reconfiguration messages */
+#define SLIM_MSG_MC_BEGIN_RECONFIGURATION 0x40
+#define SLIM_MSG_MC_NEXT_PAUSE_CLOCK 0x4A
+#define SLIM_MSG_MC_RECONFIGURE_NOW 0x5F
+
+/* Clock pause values per SLIMbus spec */
+#define SLIM_CLK_FAST 0
+#define SLIM_CLK_CONST_PHASE 1
+#define SLIM_CLK_UNSPECIFIED 2
+
/* Destination type Values */
#define SLIM_MSG_DEST_LOGICALADDR 0
#define SLIM_MSG_DEST_ENUMADDR 1
@@ -80,6 +90,42 @@ struct slim_msg_txn {
#define DEFINE_SLIM_LDEST_TXN(name, mc, rl, la, msg) \
struct slim_msg_txn name = { rl, 0, mc, SLIM_MSG_DEST_LOGICALADDR, 0,\
0, la, msg, }
+
+#define DEFINE_SLIM_BCAST_TXN(name, mc, rl, la, msg) \
+ struct slim_msg_txn name = { rl, 0, mc, SLIM_MSG_DEST_BROADCAST, 0,\
+ 0, la, msg, }
+/**
+ * enum slim_clk_state: SLIMbus controller's clock state used internally for
+ * maintaining current clock state.
+ * @SLIM_CLK_ACTIVE: SLIMbus clock is active
+ * @SLIM_CLK_ENTERING_PAUSE: SLIMbus clock pause sequence is being sent on the
+ * bus. If this succeeds, state changes to SLIM_CLK_PAUSED. If the
+ * transition fails, state changes back to SLIM_CLK_ACTIVE
+ * @SLIM_CLK_PAUSED: SLIMbus controller clock has paused.
+ */
+enum slim_clk_state {
+ SLIM_CLK_ACTIVE,
+ SLIM_CLK_ENTERING_PAUSE,
+ SLIM_CLK_PAUSED,
+};
+
+/**
+ * struct slim_sched: Framework uses this structure internally for scheduling.
+ * @clk_state: Controller's clock state from enum slim_clk_state
+ * @pause_comp: Signals completion of clock pause sequence. This is useful when
+ * client tries to call SLIMbus transaction when controller is entering
+ * clock pause.
+ * @m_reconf: This mutex is held until current reconfiguration (data channel
+ * scheduling, message bandwidth reservation) is done. Message APIs can
+ * use the bus concurrently when this mutex is held since elemental access
+ * messages can be sent on the bus when reconfiguration is in progress.
+ */
+struct slim_sched {
+ enum slim_clk_state clk_state;
+ struct completion pause_comp;
+ struct mutex m_reconf;
+};
+
/**
* struct slim_controller - Controls every instance of SLIMbus
* (similar to 'master' on SPI)
@@ -95,6 +141,7 @@ struct slim_msg_txn {
* @devices: Slim device list
* @tid_idr: tid id allocator
* @txn_lock: Lock to protect table of transactions
+ * @sched: scheduler structure used by the controller
* @xfer_msg: Transfer a message on this controller (this can be a broadcast
* control/status message like data channel setup, or a unicast message
* like value element read/write.
@@ -105,6 +152,9 @@ struct slim_msg_txn {
* address table and get_laddr can be used in that case so that controller
* can do this assignment. Use case is when the master is on the remote
* processor side, who is resposible for allocating laddr.
+ * @wakeup: This function pointer implements controller-specific procedure
+ * to wake it up from clock-pause. Framework will call this to bring
+ * the controller out of clock pause.
*
* 'Manager device' is responsible for device management, bandwidth
* allocation, channel setup, and port associations per channel.
@@ -139,12 +189,14 @@ struct slim_controller {
struct list_head devices;
struct idr tid_idr;
spinlock_t txn_lock;
+ struct slim_sched sched;
int (*xfer_msg)(struct slim_controller *ctrl,
struct slim_msg_txn *tx);
int (*set_laddr)(struct slim_controller *ctrl,
struct slim_eaddr *ea, u8 laddr);
int (*get_laddr)(struct slim_controller *ctrl,
struct slim_eaddr *ea, u8 *laddr);
+ int (*wakeup)(struct slim_controller *ctrl);
};
int slim_device_report_present(struct slim_controller *ctrl,
@@ -154,6 +206,7 @@ int slim_register_controller(struct slim_controller *ctrl);
int slim_unregister_controller(struct slim_controller *ctrl);
void slim_msg_response(struct slim_controller *ctrl, u8 *reply, u8 tid, u8 l);
int slim_do_transfer(struct slim_controller *ctrl, struct slim_msg_txn *txn);
+int slim_ctrl_clk_pause(struct slim_controller *ctrl, bool wakeup, u8 restart);
static inline bool slim_tid_txn(u8 mt, u8 mc)
{
--
2.15.0
^ permalink raw reply related
* [PATCH v10 06/13] slimbus: Add messaging APIs to slimbus framework
From: srinivas.kandagatla @ 2017-12-11 23:43 UTC (permalink / raw)
To: Mark Brown, Greg Kroah-Hartman, alsa-devel
Cc: Mark Rutland, devicetree, Jonathan Corbet, linux-arm-msm,
linux-doc, j.neuschaefer, linux-kernel, Rob Herring,
Srinivas Kandagatla, pombredanne, sdharia
In-Reply-To: <20171211234307.14465-1-srinivas.kandagatla@linaro.org>
From: Sagar Dharia <sdharia@codeaurora.org>
SLIMbus devices use value-element, and information elements to
control device parameters (e.g. value element is used to represent
gain for codec, information element is used to represent interrupt
status for codec when codec interrupt fires).
Messaging APIs are used to set/get these value and information
elements. SLIMbus specification uses 8-bit "transaction IDs" for
messages where a read-value is anticipated. Framework uses a table
of pointers to store those TIDs and responds back to the caller in
O(1).
Caller can do synchronous and asynchronous reads/writes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
drivers/slimbus/Makefile | 2 +-
drivers/slimbus/messaging.c | 297 ++++++++++++++++++++++++++++++++++++++++++++
drivers/slimbus/slimbus.h | 67 ++++++++++
include/linux/slimbus.h | 40 ++++++
4 files changed, 405 insertions(+), 1 deletion(-)
create mode 100644 drivers/slimbus/messaging.c
diff --git a/drivers/slimbus/Makefile b/drivers/slimbus/Makefile
index 506ff17d6346..568a14c7be78 100644
--- a/drivers/slimbus/Makefile
+++ b/drivers/slimbus/Makefile
@@ -3,4 +3,4 @@
# Makefile for kernel SLIMbus framework.
#
obj-$(CONFIG_SLIMBUS) += slimbus.o
-slimbus-y := core.o
+slimbus-y := core.o messaging.o
diff --git a/drivers/slimbus/messaging.c b/drivers/slimbus/messaging.c
new file mode 100644
index 000000000000..031e67648d7c
--- /dev/null
+++ b/drivers/slimbus/messaging.c
@@ -0,0 +1,297 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2011-2017, The Linux Foundation
+ */
+
+#include <linux/slab.h>
+#include "slimbus.h"
+
+/**
+ * slim_msg_response() - Deliver Message response received from a device to the
+ * framework.
+ *
+ * @ctrl: Controller handle
+ * @reply: Reply received from the device
+ * @len: Length of the reply
+ * @tid: Transaction ID received with which framework can associate reply.
+ *
+ * Called by controller to inform framework about the response received.
+ * This helps in making the API asynchronous, and controller-driver doesn't need
+ * to manage 1 more table other than the one managed by framework mapping TID
+ * with buffers
+ */
+void slim_msg_response(struct slim_controller *ctrl, u8 *reply, u8 tid, u8 len)
+{
+ struct slim_msg_txn *txn;
+ struct slim_val_inf *msg;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ctrl->txn_lock, flags);
+ txn = idr_find(&ctrl->tid_idr, tid);
+ if (txn == NULL) {
+ spin_unlock_irqrestore(&ctrl->txn_lock, flags);
+ return;
+ }
+
+ msg = txn->msg;
+ if (msg == NULL || msg->rbuf == NULL) {
+ dev_err(ctrl->dev, "Got response to invalid TID:%d, len:%d\n",
+ tid, len);
+ return;
+ }
+
+ idr_remove(&ctrl->tid_idr, tid);
+ spin_unlock_irqrestore(&ctrl->txn_lock, flags);
+
+ memcpy(msg->rbuf, reply, len);
+ if (txn->comp)
+ complete(txn->comp);
+}
+EXPORT_SYMBOL_GPL(slim_msg_response);
+
+/**
+ * slim_do_transfer() - Process a SLIMbus-messaging transaction
+ *
+ * @ctrl: Controller handle
+ * @txn: Transaction to be sent over SLIMbus
+ *
+ * Called by controller to transmit messaging transactions not dealing with
+ * Interface/Value elements. (e.g. transmittting a message to assign logical
+ * address to a slave device
+ *
+ * Return: -ETIMEDOUT: If transmission of this message timed out
+ * (e.g. due to bus lines not being clocked or driven by controller)
+ */
+int slim_do_transfer(struct slim_controller *ctrl, struct slim_msg_txn *txn)
+{
+ DECLARE_COMPLETION_ONSTACK(done);
+ bool need_tid;
+ unsigned long flags;
+ int ret, tid, timeout;
+
+ need_tid = slim_tid_txn(txn->mt, txn->mc);
+
+ if (need_tid) {
+ spin_lock_irqsave(&ctrl->txn_lock, flags);
+ tid = idr_alloc(&ctrl->tid_idr, txn, 0,
+ SLIM_MAX_TIDS, GFP_KERNEL);
+ txn->tid = tid;
+
+ if (!txn->msg->comp)
+ txn->comp = &done;
+ else
+ txn->comp = txn->comp;
+
+ spin_unlock_irqrestore(&ctrl->txn_lock, flags);
+
+ if (tid < 0)
+ return tid;
+ }
+
+ ret = ctrl->xfer_msg(ctrl, txn);
+
+ if (ret && need_tid && !txn->msg->comp) {
+ unsigned long ms = txn->rl + HZ;
+
+ timeout = wait_for_completion_timeout(txn->comp,
+ msecs_to_jiffies(ms));
+ if (!timeout) {
+ ret = -ETIMEDOUT;
+ spin_lock_irqsave(&ctrl->txn_lock, flags);
+ idr_remove(&ctrl->tid_idr, tid);
+ spin_unlock_irqrestore(&ctrl->txn_lock, flags);
+ }
+ }
+
+ if (ret)
+ dev_err(ctrl->dev, "Tx:MT:0x%x, MC:0x%x, LA:0x%x failed:%d\n",
+ txn->mt, txn->mc, txn->la, ret);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(slim_do_transfer);
+
+static int slim_val_inf_sanity(struct slim_controller *ctrl,
+ struct slim_val_inf *msg, u8 mc)
+{
+ if (!msg || msg->num_bytes > 16 ||
+ (msg->start_offset + msg->num_bytes) > 0xC00)
+ goto reterr;
+ switch (mc) {
+ case SLIM_MSG_MC_REQUEST_VALUE:
+ case SLIM_MSG_MC_REQUEST_INFORMATION:
+ if (msg->rbuf != NULL)
+ return 0;
+ break;
+
+ case SLIM_MSG_MC_CHANGE_VALUE:
+ case SLIM_MSG_MC_CLEAR_INFORMATION:
+ if (msg->wbuf != NULL)
+ return 0;
+ break;
+
+ case SLIM_MSG_MC_REQUEST_CHANGE_VALUE:
+ case SLIM_MSG_MC_REQUEST_CLEAR_INFORMATION:
+ if (msg->rbuf != NULL && msg->wbuf != NULL)
+ return 0;
+ break;
+ }
+reterr:
+ dev_err(ctrl->dev, "Sanity check failed:msg:offset:0x%x, mc:%d\n",
+ msg->start_offset, mc);
+ return -EINVAL;
+}
+
+static u16 slim_slicesize(int code)
+{
+ static const u8 sizetocode[16] = {
+ 0, 1, 2, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7
+ };
+
+ clamp(code, 1, (int)ARRAY_SIZE(sizetocode));
+
+ return sizetocode[code - 1];
+}
+
+/**
+ * slim_xfer_msg() - Transfer a value info message on slim device
+ *
+ * @sbdev: slim device to which this msg has to be transfered
+ * @msg: value info message pointer
+ * @mc: message code of the message
+ *
+ * Called by drivers which want to transfer a vlaue or info elements.
+ *
+ * Return: -ETIMEDOUT: If transmission of this message timed out
+ */
+int slim_xfer_msg(struct slim_device *sbdev, struct slim_val_inf *msg,
+ u8 mc)
+{
+ DEFINE_SLIM_LDEST_TXN(txn_stack, mc, 6, sbdev->laddr, msg);
+ struct slim_msg_txn *txn = &txn_stack;
+ struct slim_controller *ctrl = sbdev->ctrl;
+ int ret;
+ u16 sl;
+
+ if (!ctrl)
+ return -EINVAL;
+
+ ret = slim_val_inf_sanity(ctrl, msg, mc);
+ if (ret)
+ return ret;
+
+ sl = slim_slicesize(msg->num_bytes);
+
+ dev_dbg(ctrl->dev, "SB xfer msg:os:%x, len:%d, MC:%x, sl:%x\n",
+ msg->start_offset, msg->num_bytes, mc, sl);
+
+ txn->ec = ((sl | (1 << 3)) | ((msg->start_offset & 0xFFF) << 4));
+
+ switch (mc) {
+ case SLIM_MSG_MC_REQUEST_CHANGE_VALUE:
+ case SLIM_MSG_MC_CHANGE_VALUE:
+ case SLIM_MSG_MC_REQUEST_CLEAR_INFORMATION:
+ case SLIM_MSG_MC_CLEAR_INFORMATION:
+ txn->rl += msg->num_bytes;
+ default:
+ break;
+ }
+
+ if (slim_tid_txn(txn->mt, txn->mc))
+ txn->rl++;
+
+ return slim_do_transfer(ctrl, txn);
+}
+EXPORT_SYMBOL_GPL(slim_xfer_msg);
+
+static void slim_fill_msg(struct slim_val_inf *msg, u32 addr,
+ size_t count, u8 *rbuf, u8 *wbuf)
+{
+ msg->start_offset = addr;
+ msg->num_bytes = count;
+ msg->rbuf = rbuf;
+ msg->wbuf = wbuf;
+}
+
+/**
+ * slim_read() - Read SLIMbus value element
+ *
+ * @sdev: client handle.
+ * @addr: address of value element to read.
+ * @count: number of bytes to read. Maximum bytes allowed are 16.
+ * @val: will return what the value element value was
+ *
+ * Return: -EINVAL for Invalid parameters, -ETIMEDOUT If transmission of
+ * this message timed out (e.g. due to bus lines not being clocked
+ * or driven by controller)
+ */
+int slim_read(struct slim_device *sdev, u32 addr, size_t count, u8 *val)
+{
+ struct slim_val_inf msg;
+
+ slim_fill_msg(&msg, addr, count, val, NULL);
+
+ return slim_xfer_msg(sdev, &msg, SLIM_MSG_MC_REQUEST_VALUE);
+}
+EXPORT_SYMBOL_GPL(slim_read);
+
+/**
+ * slim_readb() - Read byte from SLIMbus value element
+ *
+ * @sdev: client handle.
+ * @addr: address in the value element to read.
+ *
+ * Return: byte value of value element.
+ */
+int slim_readb(struct slim_device *sdev, u32 addr)
+{
+ int ret;
+ u8 buf;
+
+ ret = slim_read(sdev, addr, 1, &buf);
+ if (ret < 0)
+ return ret;
+ else
+ return buf;
+}
+EXPORT_SYMBOL_GPL(slim_readb);
+
+/**
+ * slim_write() - Write SLIMbus value element
+ *
+ * @sdev: client handle.
+ * @addr: address in the value element to write.
+ * @count: number of bytes to write. Maximum bytes allowed are 16.
+ * @val: value to write to value element
+ *
+ * Return: -EINVAL for Invalid parameters, -ETIMEDOUT If transmission of
+ * this message timed out (e.g. due to bus lines not being clocked
+ * or driven by controller)
+ */
+int slim_write(struct slim_device *sdev, u32 addr, size_t count, u8 *val)
+{
+ struct slim_val_inf msg;
+
+ slim_fill_msg(&msg, addr, count, val, NULL);
+
+ return slim_xfer_msg(sdev, &msg, SLIM_MSG_MC_CHANGE_VALUE);
+}
+EXPORT_SYMBOL_GPL(slim_write);
+
+/**
+ * slim_writeb() - Write byte to SLIMbus value element
+ *
+ * @sdev: client handle.
+ * @addr: address of value element to write.
+ * @value: value to write to value element
+ *
+ * Return: -EINVAL for Invalid parameters, -ETIMEDOUT If transmission of
+ * this message timed out (e.g. due to bus lines not being clocked
+ * or driven by controller)
+ *
+ */
+int slim_writeb(struct slim_device *sdev, u32 addr, u8 value)
+{
+ return slim_write(sdev, addr, 1, &value);
+}
+EXPORT_SYMBOL_GPL(slim_writeb);
diff --git a/drivers/slimbus/slimbus.h b/drivers/slimbus/slimbus.h
index 66657722f50f..0d40c2578c28 100644
--- a/drivers/slimbus/slimbus.h
+++ b/drivers/slimbus/slimbus.h
@@ -8,8 +8,17 @@
#include <linux/module.h>
#include <linux/device.h>
#include <linux/mutex.h>
+#include <linux/completion.h>
#include <linux/slimbus.h>
+/* SLIMbus message types. Related to interpretation of message code. */
+#define SLIM_MSG_MT_CORE 0x0
+
+/* Destination type Values */
+#define SLIM_MSG_DEST_LOGICALADDR 0
+#define SLIM_MSG_DEST_ENUMADDR 1
+#define SLIM_MSG_DEST_BROADCAST 3
+
/* Standard values per SLIMbus spec needed by controllers and devices */
#define SLIM_MAX_CLK_GEAR 10
#define SLIM_MIN_CLK_GEAR 1
@@ -17,6 +26,7 @@
/* Manager's logical address is set to 0xFF per spec */
#define SLIM_LA_MANAGER 0xFF
+#define SLIM_MAX_TIDS 256
/**
* struct slim_framer - Represents SLIMbus framer.
* Every controller may have multiple framers. There is 1 active framer device
@@ -37,6 +47,39 @@ struct slim_framer {
#define to_slim_framer(d) container_of(d, struct slim_framer, dev)
+/**
+ * struct slim_msg_txn - Message to be sent by the controller.
+ * This structure has packet header,
+ * payload and buffer to be filled (if any)
+ * @rl: Header field. remaining length.
+ * @mt: Header field. Message type.
+ * @mc: Header field. LSB is message code for type mt.
+ * @dt: Header field. Destination type.
+ * @ec: Element code. Used for elemental access APIs.
+ * @tid: Transaction ID. Used for messages expecting response.
+ * (relevant for message-codes involving read operation)
+ * @la: Logical address of the device this message is going to.
+ * (Not used when destination type is broadcast.)
+ * @msg: Elemental access message to be read/written
+ * @comp: completion if read/write is synchronous, used internally
+ * for tid based transactions.
+ */
+struct slim_msg_txn {
+ u8 rl;
+ u8 mt;
+ u8 mc;
+ u8 dt;
+ u16 ec;
+ u8 tid;
+ u8 la;
+ struct slim_val_inf *msg;
+ struct completion *comp;
+};
+
+/* Frequently used message transaction structures */
+#define DEFINE_SLIM_LDEST_TXN(name, mc, rl, la, msg) \
+ struct slim_msg_txn name = { rl, 0, mc, SLIM_MSG_DEST_LOGICALADDR, 0,\
+ 0, la, msg, }
/**
* struct slim_controller - Controls every instance of SLIMbus
* (similar to 'master' on SPI)
@@ -52,6 +95,9 @@ struct slim_framer {
* @devices: Slim device list
* @tid_idr: tid id allocator
* @txn_lock: Lock to protect table of transactions
+ * @xfer_msg: Transfer a message on this controller (this can be a broadcast
+ * control/status message like data channel setup, or a unicast message
+ * like value element read/write.
* @set_laddr: Setup logical address at laddr for the slave with elemental
* address e_addr. Drivers implementing controller will be expected to
* send unicast message to this device with its logical address.
@@ -93,6 +139,8 @@ struct slim_controller {
struct list_head devices;
struct idr tid_idr;
spinlock_t txn_lock;
+ int (*xfer_msg)(struct slim_controller *ctrl,
+ struct slim_msg_txn *tx);
int (*set_laddr)(struct slim_controller *ctrl,
struct slim_eaddr *ea, u8 laddr);
int (*get_laddr)(struct slim_controller *ctrl,
@@ -104,5 +152,24 @@ int slim_device_report_present(struct slim_controller *ctrl,
void slim_report_absent(struct slim_device *sbdev);
int slim_register_controller(struct slim_controller *ctrl);
int slim_unregister_controller(struct slim_controller *ctrl);
+void slim_msg_response(struct slim_controller *ctrl, u8 *reply, u8 tid, u8 l);
+int slim_do_transfer(struct slim_controller *ctrl, struct slim_msg_txn *txn);
+
+static inline bool slim_tid_txn(u8 mt, u8 mc)
+{
+ return (mt == SLIM_MSG_MT_CORE &&
+ (mc == SLIM_MSG_MC_REQUEST_INFORMATION ||
+ mc == SLIM_MSG_MC_REQUEST_CLEAR_INFORMATION ||
+ mc == SLIM_MSG_MC_REQUEST_VALUE ||
+ mc == SLIM_MSG_MC_REQUEST_CLEAR_INFORMATION));
+}
+static inline bool slim_ec_txn(u8 mt, u8 mc)
+{
+ return (mt == SLIM_MSG_MT_CORE &&
+ ((mc >= SLIM_MSG_MC_REQUEST_INFORMATION &&
+ mc <= SLIM_MSG_MC_REPORT_INFORMATION) ||
+ (mc >= SLIM_MSG_MC_REQUEST_VALUE &&
+ mc <= SLIM_MSG_MC_CHANGE_VALUE)));
+}
#endif /* _LINUX_SLIMBUS_H */
diff --git a/include/linux/slimbus.h b/include/linux/slimbus.h
index aeed98a683be..c36cf121d2cd 100644
--- a/include/linux/slimbus.h
+++ b/include/linux/slimbus.h
@@ -7,6 +7,7 @@
#define _LINUX_SLIMBUS_H
#include <linux/device.h>
#include <linux/module.h>
+#include <linux/completion.h>
#include <linux/mod_devicetable.h>
extern struct bus_type slimbus_bus;
@@ -88,6 +89,25 @@ struct slim_driver {
};
#define to_slim_driver(d) container_of(d, struct slim_driver, driver)
+/**
+ * struct slim_val_inf - Slimbus value or information element
+ * @start_offset: Specifies starting offset in information/value element map
+ * @rbuf: buffer to read the values
+ * @wbuf: buffer to write
+ * @num_bytes: upto 16. This ensures that the message will fit the slicesize
+ * per SLIMbus spec
+ * @comp: completion for asynchronous operations, valid only if TID is
+ * required for transaction, like REQUEST operations.
+ * Rest of the transactions are synchronous anyway.
+ */
+struct slim_val_inf {
+ u16 start_offset;
+ u8 num_bytes;
+ u8 *rbuf;
+ const u8 *wbuf;
+ struct completion *comp;
+};
+
/*
* use a macro to avoid include chaining to get THIS_MODULE
*/
@@ -121,4 +141,24 @@ static inline void slim_set_devicedata(struct slim_device *dev, void *data)
struct slim_device *slim_get_device(struct slim_controller *ctrl,
struct slim_eaddr *e_addr);
int slim_get_logical_addr(struct slim_device *sbdev);
+
+/* Information Element management messages */
+#define SLIM_MSG_MC_REQUEST_INFORMATION 0x20
+#define SLIM_MSG_MC_REQUEST_CLEAR_INFORMATION 0x21
+#define SLIM_MSG_MC_REPLY_INFORMATION 0x24
+#define SLIM_MSG_MC_CLEAR_INFORMATION 0x28
+#define SLIM_MSG_MC_REPORT_INFORMATION 0x29
+
+/* Value Element management messages */
+#define SLIM_MSG_MC_REQUEST_VALUE 0x60
+#define SLIM_MSG_MC_REQUEST_CHANGE_VALUE 0x61
+#define SLIM_MSG_MC_REPLY_VALUE 0x64
+#define SLIM_MSG_MC_CHANGE_VALUE 0x68
+
+int slim_xfer_msg(struct slim_device *sbdev, struct slim_val_inf *msg,
+ u8 mc);
+int slim_readb(struct slim_device *sdev, u32 addr);
+int slim_writeb(struct slim_device *sdev, u32 addr, u8 value);
+int slim_read(struct slim_device *sdev, u32 addr, size_t count, u8 *val);
+int slim_write(struct slim_device *sdev, u32 addr, size_t count, u8 *val);
#endif /* _LINUX_SLIMBUS_H */
--
2.15.0
^ permalink raw reply related
* [PATCH v10 05/13] slimbus: core: add support to device tree helper
From: srinivas.kandagatla @ 2017-12-11 23:42 UTC (permalink / raw)
To: Mark Brown, Greg Kroah-Hartman, alsa-devel
Cc: Mark Rutland, devicetree, Jonathan Corbet, linux-arm-msm,
linux-doc, j.neuschaefer, linux-kernel, Rob Herring,
Srinivas Kandagatla, pombredanne, sdharia
In-Reply-To: <20171211234307.14465-1-srinivas.kandagatla@linaro.org>
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
This patch adds support to parse slim devices from device tree.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
drivers/slimbus/core.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/drivers/slimbus/core.c b/drivers/slimbus/core.c
index ed53ae6bd1cc..1accb20ed5cd 100644
--- a/drivers/slimbus/core.c
+++ b/drivers/slimbus/core.c
@@ -8,6 +8,7 @@
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/idr.h>
+#include <linux/of.h>
#include <linux/slimbus.h>
#include "slimbus.h"
@@ -113,6 +114,9 @@ static int slim_add_device(struct slim_controller *ctrl,
sbdev->dev.driver = NULL;
sbdev->ctrl = ctrl;
+ if (node)
+ sbdev->dev.of_node = of_node_get(node);
+
dev_set_name(&sbdev->dev, "%x:%x:%x:%x",
sbdev->e_addr.manf_id,
sbdev->e_addr.prod_code,
@@ -143,6 +147,50 @@ static struct slim_device *slim_alloc_device(struct slim_controller *ctrl,
return sbdev;
}
+static void of_register_slim_devices(struct slim_controller *ctrl)
+{
+ struct device *dev = ctrl->dev;
+ struct device_node *node;
+
+ if (!ctrl->dev->of_node)
+ return;
+
+ for_each_child_of_node(ctrl->dev->of_node, node) {
+ struct slim_device *sbdev;
+ struct slim_eaddr e_addr;
+ const char *compat = NULL;
+ int reg[2], ret;
+ int manf_id, prod_code;
+
+ compat = of_get_property(node, "compatible", NULL);
+ if (!compat)
+ continue;
+
+ ret = sscanf(compat, "slim%x,%x", &manf_id, &prod_code);
+ if (ret != 2) {
+ dev_err(dev, "Manf ID & Product code not found %s\n",
+ compat);
+ continue;
+ }
+
+ ret = of_property_read_u32_array(node, "reg", reg, 2);
+ if (ret) {
+ dev_err(dev, "Device and Instance id not found:%d\n",
+ ret);
+ continue;
+ }
+
+ e_addr.dev_index = reg[0];
+ e_addr.instance = reg[1];
+ e_addr.manf_id = manf_id;
+ e_addr.prod_code = prod_code;
+
+ sbdev = slim_alloc_device(ctrl, &e_addr, node);
+ if (!sbdev)
+ continue;
+ }
+}
+
/*
* slim_register_controller() - Controller bring-up and registration.
*
@@ -174,6 +222,8 @@ int slim_register_controller(struct slim_controller *ctrl)
dev_dbg(ctrl->dev, "Bus [%s] registered:dev:%p\n",
ctrl->name, ctrl->dev);
+ of_register_slim_devices(ctrl);
+
return 0;
}
EXPORT_SYMBOL_GPL(slim_register_controller);
--
2.15.0
^ permalink raw reply related
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