* [PATCHv2 3/3] MAINTAINERS: Add entry for Socionext ethernet driver
From: jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w @ 2017-12-12 17:16 UTC (permalink / raw)
To: netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: davem-fT/PcQaiUtIeIZ0/mPfg9Q,
arnd.bergmann-QSEj5FYQhm4dnm+yROfE0A,
ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
Jassi Brar
In-Reply-To: <1513098873-20977-1-git-send-email-jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Add entry for the Socionext Netsec controller driver and DT bindings.
Acked-by: Ard Biesheuvel <ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9e0045e..0e1f0d4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12630,6 +12630,13 @@ F: drivers/md/raid*
F: include/linux/raid/
F: include/uapi/linux/raid/
+SOCIONEXT (SNI) NETSEC NETWORK DRIVER
+M: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
+L: netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+S: Maintained
+F: drivers/net/ethernet/socionext/netsec.c
+F: Documentation/devicetree/bindings/net/socionext-netsec.txt
+
SONIC NETWORK DRIVER
M: Thomas Bogendoerfer <tsbogend-I1c7kopa9pxLokYuJOExCg@public.gmane.org>
L: netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
--
2.7.4
--
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^ permalink raw reply related
* Re: [PATCHv2 2/3] net: socionext: Add Synquacer NetSec driver
From: Ard Biesheuvel @ 2017-12-12 17:24 UTC (permalink / raw)
To: Jassi Brar
Cc: <netdev@vger.kernel.org>, devicetree@vger.kernel.org,
David S. Miller, Arnd Bergmann, Rob Herring, Mark Rutland,
Jassi Brar
In-Reply-To: <1513098954-21093-1-git-send-email-jassisinghbrar@gmail.com>
Hi Jassi,
On 12 December 2017 at 17:15, <jassisinghbrar@gmail.com> wrote:
> From: Jassi Brar <jaswinder.singh@linaro.org>
>
> This driver adds support for Socionext "netsec" IP Gigabit
> Ethernet + PHY IP used in the Synquacer SC2A11 SoC.
>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
> ---
> drivers/net/ethernet/Kconfig | 1 +
> drivers/net/ethernet/Makefile | 1 +
> drivers/net/ethernet/socionext/Kconfig | 29 +
> drivers/net/ethernet/socionext/Makefile | 1 +
> drivers/net/ethernet/socionext/netsec.c | 1826 +++++++++++++++++++++++++++++++
> 5 files changed, 1858 insertions(+)
> create mode 100644 drivers/net/ethernet/socionext/Kconfig
> create mode 100644 drivers/net/ethernet/socionext/Makefile
> create mode 100644 drivers/net/ethernet/socionext/netsec.c
>
[...]
> diff --git a/drivers/net/ethernet/socionext/netsec.c b/drivers/net/ethernet/socionext/netsec.c
> new file mode 100644
> index 0000000..4472303a
> --- /dev/null
> +++ b/drivers/net/ethernet/socionext/netsec.c
> @@ -0,0 +1,1826 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <linux/types.h>
> +#include <linux/clk.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/acpi.h>
> +#include <linux/of_mdio.h>
> +#include <linux/etherdevice.h>
> +#include <linux/interrupt.h>
> +
> +#include <net/tcp.h>
> +#include <net/ip6_checksum.h>
> +
> +#define NETSEC_REG_SOFT_RST 0x104
> +#define NETSEC_REG_COM_INIT 0x120
> +
> +#define NETSEC_REG_TOP_STATUS 0x200
> +#define NETSEC_IRQ_RX BIT(1)
> +#define NETSEC_IRQ_TX BIT(0)
> +
> +#define NETSEC_REG_TOP_INTEN 0x204
> +#define NETSEC_REG_INTEN_SET 0x234
> +#define NETSEC_REG_INTEN_CLR 0x238
> +
> +#define NETSEC_REG_NRM_TX_STATUS 0x400
> +#define NETSEC_REG_NRM_TX_INTEN 0x404
> +#define NETSEC_REG_NRM_TX_INTEN_SET 0x428
> +#define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c
> +#define NRM_TX_ST_NTOWNR BIT(17)
> +#define NRM_TX_ST_TR_ERR BIT(16)
> +#define NRM_TX_ST_TXDONE BIT(15)
> +#define NRM_TX_ST_TMREXP BIT(14)
> +
> +#define NETSEC_REG_NRM_RX_STATUS 0x440
> +#define NETSEC_REG_NRM_RX_INTEN 0x444
> +#define NETSEC_REG_NRM_RX_INTEN_SET 0x468
> +#define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c
> +#define NRM_RX_ST_RC_ERR BIT(16)
> +#define NRM_RX_ST_PKTCNT BIT(15)
> +#define NRM_RX_ST_TMREXP BIT(14)
> +
> +#define NETSEC_REG_PKT_CMD_BUF 0xd0
> +
> +#define NETSEC_REG_CLK_EN 0x100
> +
> +#define NETSEC_REG_PKT_CTRL 0x140
> +
> +#define NETSEC_REG_DMA_TMR_CTRL 0x20c
> +#define NETSEC_REG_F_TAIKI_MC_VER 0x22c
> +#define NETSEC_REG_F_TAIKI_VER 0x230
> +#define NETSEC_REG_DMA_HM_CTRL 0x214
> +#define NETSEC_REG_DMA_MH_CTRL 0x220
> +#define NETSEC_REG_ADDR_DIS_CORE 0x218
> +#define NETSEC_REG_DMAC_HM_CMD_BUF 0x210
> +#define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c
> +
> +#define NETSEC_REG_NRM_TX_PKTCNT 0x410
> +
> +#define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414
> +#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418
> +
> +#define NETSEC_REG_NRM_TX_TMR 0x41c
> +
> +#define NETSEC_REG_NRM_RX_PKTCNT 0x454
> +#define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458
> +#define NETSEC_REG_NRM_TX_TXINT_TMR 0x420
> +#define NETSEC_REG_NRM_RX_RXINT_TMR 0x460
> +
> +#define NETSEC_REG_NRM_RX_TMR 0x45c
> +
> +#define NETSEC_REG_NRM_TX_DESC_START_UP 0x434
> +#define NETSEC_REG_NRM_TX_DESC_START_LW 0x408
> +#define NETSEC_REG_NRM_RX_DESC_START_UP 0x474
> +#define NETSEC_REG_NRM_RX_DESC_START_LW 0x448
> +
> +#define NETSEC_REG_NRM_TX_CONFIG 0x430
> +#define NETSEC_REG_NRM_RX_CONFIG 0x470
> +
> +#define MAC_REG_STATUS 0x1024
> +#define MAC_REG_DATA 0x11c0
> +#define MAC_REG_CMD 0x11c4
> +#define MAC_REG_FLOW_TH 0x11cc
> +#define MAC_REG_INTF_SEL 0x11d4
> +#define MAC_REG_DESC_INIT 0x11fc
> +#define MAC_REG_DESC_SOFT_RST 0x1204
> +#define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500
> +
> +#define GMAC_REG_MCR 0x0000
> +#define GMAC_REG_MFFR 0x0004
> +#define GMAC_REG_GAR 0x0010
> +#define GMAC_REG_GDR 0x0014
> +#define GMAC_REG_FCR 0x0018
> +#define GMAC_REG_BMR 0x1000
> +#define GMAC_REG_RDLAR 0x100c
> +#define GMAC_REG_TDLAR 0x1010
> +#define GMAC_REG_OMR 0x1018
> +
> +#define MHZ(n) ((n) * 1000 * 1000)
> +
> +#define NETSEC_TX_SHIFT_OWN_FIELD 31
> +#define NETSEC_TX_SHIFT_LD_FIELD 30
> +#define NETSEC_TX_SHIFT_DRID_FIELD 24
> +#define NETSEC_TX_SHIFT_PT_FIELD 21
> +#define NETSEC_TX_SHIFT_TDRID_FIELD 16
> +#define NETSEC_TX_SHIFT_CC_FIELD 15
> +#define NETSEC_TX_SHIFT_FS_FIELD 9
> +#define NETSEC_TX_LAST 8
> +#define NETSEC_TX_SHIFT_CO 7
> +#define NETSEC_TX_SHIFT_SO 6
> +#define NETSEC_TX_SHIFT_TRS_FIELD 4
> +
> +#define NETSEC_RX_PKT_OWN_FIELD 31
> +#define NETSEC_RX_PKT_LD_FIELD 30
> +#define NETSEC_RX_PKT_SDRID_FIELD 24
> +#define NETSEC_RX_PKT_FR_FIELD 23
> +#define NETSEC_RX_PKT_ER_FIELD 21
> +#define NETSEC_RX_PKT_ERR_FIELD 16
> +#define NETSEC_RX_PKT_TDRID_FIELD 12
> +#define NETSEC_RX_PKT_FS_FIELD 9
> +#define NETSEC_RX_PKT_LS_FIELD 8
> +#define NETSEC_RX_PKT_CO_FIELD 6
> +
> +#define NETSEC_RX_PKT_ERR_MASK 3
> +
> +#define NETSEC_MAX_TX_PKT_LEN 1518
> +#define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018
> +
> +#define NETSEC_RING_GMAC 15
> +#define NETSEC_RING_MAX 2
> +
> +#define NETSEC_TCP_SEG_LEN_MAX 1460
> +#define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960
> +
> +#define NETSEC_RX_CKSUM_NOTAVAIL 0
> +#define NETSEC_RX_CKSUM_OK 1
> +#define NETSEC_RX_CKSUM_NG 2
> +
> +#define NETSEC_TOP_IRQ_REG_CODE_LOAD_END BIT(20)
> +#define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4)
> +
> +#define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20)
> +#define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19)
> +
> +#define NETSEC_INT_PKTCNT_MAX 2047
> +
> +#define NETSEC_FLOW_START_TH_MAX 95
> +#define NETSEC_FLOW_STOP_TH_MAX 95
> +#define NETSEC_FLOW_PAUSE_TIME_MIN 5
> +
> +#define NETSEC_CLK_EN_REG_DOM_ALL 0x3f
> +
> +#define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28)
> +#define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27)
> +#define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3)
> +#define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2)
> +#define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1)
> +#define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0)
> +
> +#define NETSEC_CLK_EN_REG_DOM_G BIT(5)
> +#define NETSEC_CLK_EN_REG_DOM_C BIT(1)
> +#define NETSEC_CLK_EN_REG_DOM_D BIT(0)
> +
> +#define NETSEC_COM_INIT_REG_DB BIT(2)
> +#define NETSEC_COM_INIT_REG_CLS BIT(1)
> +#define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \
> + NETSEC_COM_INIT_REG_DB)
> +
> +#define NETSEC_SOFT_RST_REG_RESET 0
> +#define NETSEC_SOFT_RST_REG_RUN BIT(31)
> +
> +#define NETSEC_DMA_CTRL_REG_STOP 1
> +#define MH_CTRL__MODE_TRANS BIT(20)
> +
> +#define NETSEC_GMAC_CMD_ST_READ 0
> +#define NETSEC_GMAC_CMD_ST_WRITE BIT(28)
> +#define NETSEC_GMAC_CMD_ST_BUSY BIT(31)
> +
> +#define NETSEC_GMAC_BMR_REG_COMMON 0x00412080
> +#define NETSEC_GMAC_BMR_REG_RESET 0x00020181
> +#define NETSEC_GMAC_BMR_REG_SWR 0x00000001
> +
> +#define NETSEC_GMAC_OMR_REG_ST BIT(13)
> +#define NETSEC_GMAC_OMR_REG_SR BIT(1)
> +
> +#define NETSEC_GMAC_MCR_REG_IBN BIT(30)
> +#define NETSEC_GMAC_MCR_REG_CST BIT(25)
> +#define NETSEC_GMAC_MCR_REG_JE BIT(20)
> +#define NETSEC_MCR_PS BIT(15)
> +#define NETSEC_GMAC_MCR_REG_FES BIT(14)
> +#define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c
> +#define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c
> +
> +#define NETSEC_FCR_RFE BIT(2)
> +#define NETSEC_FCR_TFE BIT(1)
> +
> +#define NETSEC_GMAC_GAR_REG_GW BIT(1)
> +#define NETSEC_GMAC_GAR_REG_GB BIT(0)
> +
> +#define NETSEC_GMAC_GAR_REG_SHIFT_PA 11
> +#define NETSEC_GMAC_GAR_REG_SHIFT_GR 6
> +#define GMAC_REG_SHIFT_CR_GAR 2
> +
> +#define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2
> +#define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3
> +#define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0
> +#define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1
> +#define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4
> +#define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5
> +
> +#define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000
> +#define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000
> +
> +#define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000
> +
> +#define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31)
> +#define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30)
> +#define NETSEC_REG_DESC_TMR_MODE 4
> +#define NETSEC_REG_DESC_ENDIAN 0
> +
> +#define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1
> +#define NETSEC_MAC_DESC_INIT_REG_INIT 1
> +
> +#define NETSEC_EEPROM_MAC_ADDRESS 0x00
> +#define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08
> +#define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C
> +#define NETSEC_EEPROM_HM_ME_SIZE 0x10
> +#define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14
> +#define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18
> +#define NETSEC_EEPROM_MH_ME_SIZE 0x1C
> +#define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20
> +#define NETSEC_EEPROM_PKT_ME_SIZE 0x24
> +
> +#define DESC_NUM 128
> +#define NAPI_BUDGET (DESC_NUM / 2)
> +
> +#define DESC_SZ sizeof(struct netsec_de)
> +
> +#define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000)
> +
> +enum ring_id {
> + NETSEC_RING_TX = 0,
> + NETSEC_RING_RX
> +};
> +
> +struct netsec_desc {
> + struct sk_buff *skb;
> + dma_addr_t dma_addr;
> + void *addr;
> + u16 len;
> +};
> +
> +struct netsec_desc_ring {
> + phys_addr_t desc_phys;
> + struct netsec_desc *desc;
> + void *vaddr;
> + u16 pkt_cnt;
> + u16 head, tail;
> +};
> +
> +struct netsec_priv {
> + struct netsec_desc_ring desc_ring[NETSEC_RING_MAX];
> + struct ethtool_coalesce et_coalesce;
> + spinlock_t reglock; /* protect reg access */
> + struct napi_struct napi;
> + phy_interface_t phy_interface;
> + struct net_device *ndev;
> + struct device_node *phy_np;
> + struct phy_device *phydev;
> + struct mii_bus *mii_bus;
> + void __iomem *ioaddr;
> + void __iomem *eeprom_base;
This correctly reflects the change requested by Dave but ...
> + struct device *dev;
> + struct clk *clk[3];
> + u32 msg_enable;
> + u32 freq;
> + int clock_count;
> + bool rx_cksum_offload_flag;
> +};
> +
> +struct netsec_de { /* Netsec Descriptor layout */
> + u32 attr;
> + u32 data_buf_addr_up;
> + u32 data_buf_addr_lw;
> + u32 buf_len_info;
> +};
> +
> +struct netsec_tx_pkt_ctrl {
> + u16 tcp_seg_len;
> + bool tcp_seg_offload_flag;
> + bool cksum_offload_flag;
> +};
> +
> +struct netsec_rx_pkt_info {
> + int rx_cksum_result;
> + int err_code;
> + bool err_flag;
> +};
> +
> +static inline void netsec_write(struct netsec_priv *priv,
> + u32 reg_addr, u32 val)
> +{
> + writel(val, priv->ioaddr + reg_addr);
> +}
> +
> +static inline u32 netsec_read(struct netsec_priv *priv, u32 reg_addr)
> +{
> + return readl(priv->ioaddr + reg_addr);
> +}
> +
> +#define DRING_TAIL(r) ((r)->tail)
> +
> +#define DRING_HEAD(r) ((r)->head)
> +
> +#define MOVE_TAIL(r) do { \
> + if (++(r)->tail == DESC_NUM) \
> + (r)->tail = 0; \
> + } while (0)
> +
> +#define MOVE_HEAD(r) do { \
> + if (++(r)->head == DESC_NUM) \
> + (r)->head = 0; \
> + } while (0)
> +
> +#define JUMP_HEAD(r, n) do { \
> + int i; \
> + for (i = 0; i < (n); i++) \
> + MOVE_HEAD(r); \
> + } while (0)
> +
> +static inline int available_descs(struct netsec_desc_ring *r)
> +{
> + int filled;
> +
> + if ((r)->head >= (r)->tail)
> + filled = (r)->head - (r)->tail;
> + else
> + filled = (r)->head + DESC_NUM - (r)->tail;
> +
> + return DESC_NUM - filled;
> +}
> +
> +/*************************************************************/
> +/*********************** MDIO BUS OPS ************************/
> +/*************************************************************/
> +
> +#define TIMEOUT_SPINS_MAC 1000
> +#define TIMEOUT_SECONDARY_MS_MAC 100
> +
> +static u32 netsec_clk_type(u32 freq)
> +{
> + if (freq < MHZ(35))
> + return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
> + if (freq < MHZ(60))
> + return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
> + if (freq < MHZ(100))
> + return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
> + if (freq < MHZ(150))
> + return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
> + if (freq < MHZ(250))
> + return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
> +
> + return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
> +}
> +
> +static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)
> +{
> + u32 timeout = TIMEOUT_SPINS_MAC;
> +
> + while (--timeout && netsec_read(priv, addr) & mask)
> + cpu_relax();
> + if (timeout)
> + return 0;
> +
> + timeout = TIMEOUT_SECONDARY_MS_MAC;
> + while (--timeout && netsec_read(priv, addr) & mask)
> + usleep_range(1000, 2000);
> +
> + if (timeout)
> + return 0;
> +
> + netdev_WARN(priv->ndev, "%s: timeout\n", __func__);
> +
> + return -ETIMEDOUT;
> +}
> +
> +static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value)
> +{
> + netsec_write(priv, MAC_REG_DATA, value);
> + netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
> + return netsec_wait_while_busy(priv,
> + MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
> +}
> +
> +static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read)
> +{
> + int ret;
> +
> + netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
> + ret = netsec_wait_while_busy(priv,
> + MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
> + if (ret)
> + return ret;
> +
> + *read = netsec_read(priv, MAC_REG_DATA);
> +
> + return 0;
> +}
> +
> +static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
> + u32 addr, u32 mask)
> +{
> + u32 timeout = TIMEOUT_SPINS_MAC;
> + int ret, data;
> +
> + do {
> + ret = netsec_mac_read(priv, addr, &data);
> + if (ret)
> + break;
> + cpu_relax();
> + } while (--timeout && (data & mask));
> +
> + if (timeout)
> + return 0;
> +
> + timeout = TIMEOUT_SECONDARY_MS_MAC;
> + do {
> + usleep_range(1000, 2000);
> +
> + ret = netsec_mac_read(priv, addr, &data);
> + if (ret)
> + break;
> + cpu_relax();
> + } while (--timeout && (data & mask));
> +
> + if (timeout && !ret)
> + return 0;
> +
> + netdev_WARN(priv->ndev, "%s: timeout\n", __func__);
> +
> + return -ETIMEDOUT;
> +}
> +
> +static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
> +{
> + struct phy_device *phydev = priv->ndev->phydev;
> + u32 value = 0;
> +
> + value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
> + NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
> +
> + if (phydev->speed != SPEED_1000)
> + value |= NETSEC_MCR_PS;
> +
> + if (priv->phy_interface != PHY_INTERFACE_MODE_GMII &&
> + phydev->speed == SPEED_100)
> + value |= NETSEC_GMAC_MCR_REG_FES;
> +
> + value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
> +
> + if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII)
> + value |= NETSEC_GMAC_MCR_REG_IBN;
> +
> + if (netsec_mac_write(priv, GMAC_REG_MCR, value))
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int netsec_phy_write(struct mii_bus *bus,
> + int phy_addr, int reg, u16 val)
> +{
> + struct netsec_priv *priv = bus->priv;
> +
> + if (netsec_mac_write(priv, GMAC_REG_GDR, val))
> + return -ETIMEDOUT;
> + if (netsec_mac_write(priv, GMAC_REG_GAR,
> + phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
> + reg << NETSEC_GMAC_GAR_REG_SHIFT_GR |
> + NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
> + (netsec_clk_type(priv->freq) <<
> + GMAC_REG_SHIFT_CR_GAR)))
> + return -ETIMEDOUT;
> +
> + return netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
> + NETSEC_GMAC_GAR_REG_GB);
> +}
> +
> +static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
> +{
> + struct netsec_priv *priv = bus->priv;
> + u32 data;
> + int ret;
> +
> + if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
> + phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
> + reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
> + (netsec_clk_type(priv->freq) <<
> + GMAC_REG_SHIFT_CR_GAR)))
> + return -ETIMEDOUT;
> +
> + ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
> + NETSEC_GMAC_GAR_REG_GB);
> + if (ret)
> + return ret;
> +
> + ret = netsec_mac_read(priv, GMAC_REG_GDR, &data);
> + if (ret)
> + return ret;
> +
> + return data;
> +}
> +
> +/*************************************************************/
> +/*********************** ETHTOOL_OPS **************************/
> +/*************************************************************/
> +
> +static void netsec_et_get_drvinfo(struct net_device *net_device,
> + struct ethtool_drvinfo *info)
> +{
> + strlcpy(info->driver, "netsec", sizeof(info->driver));
> + strlcpy(info->bus_info, dev_name(net_device->dev.parent),
> + sizeof(info->bus_info));
> +}
> +
> +static int netsec_et_get_coalesce(struct net_device *net_device,
> + struct ethtool_coalesce *et_coalesce)
> +{
> + struct netsec_priv *priv = netdev_priv(net_device);
> +
> + *et_coalesce = priv->et_coalesce;
> +
> + return 0;
> +}
> +
> +static int netsec_et_set_coalesce(struct net_device *net_device,
> + struct ethtool_coalesce *et_coalesce)
> +{
> + struct netsec_priv *priv = netdev_priv(net_device);
> +
> + priv->et_coalesce = *et_coalesce;
> +
> + if (priv->et_coalesce.tx_coalesce_usecs < 50)
> + priv->et_coalesce.tx_coalesce_usecs = 50;
> + if (priv->et_coalesce.tx_max_coalesced_frames < 1)
> + priv->et_coalesce.tx_max_coalesced_frames = 1;
> +
> + netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT,
> + priv->et_coalesce.tx_max_coalesced_frames);
> + netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR,
> + priv->et_coalesce.tx_coalesce_usecs);
> + netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE);
> + netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP);
> +
> + if (priv->et_coalesce.rx_coalesce_usecs < 50)
> + priv->et_coalesce.rx_coalesce_usecs = 50;
> + if (priv->et_coalesce.rx_max_coalesced_frames < 1)
> + priv->et_coalesce.rx_max_coalesced_frames = 1;
> +
> + netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT,
> + priv->et_coalesce.rx_max_coalesced_frames);
> + netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR,
> + priv->et_coalesce.rx_coalesce_usecs);
> + netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT);
> + netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP);
> +
> + return 0;
> +}
> +
> +static u32 netsec_et_get_msglevel(struct net_device *dev)
> +{
> + struct netsec_priv *priv = netdev_priv(dev);
> +
> + return priv->msg_enable;
> +}
> +
> +static void netsec_et_set_msglevel(struct net_device *dev, u32 datum)
> +{
> + struct netsec_priv *priv = netdev_priv(dev);
> +
> + priv->msg_enable = datum;
> +}
> +
> +static const struct ethtool_ops netsec_ethtool_ops = {
> + .get_drvinfo = netsec_et_get_drvinfo,
> + .get_link_ksettings = phy_ethtool_get_link_ksettings,
> + .set_link_ksettings = phy_ethtool_set_link_ksettings,
> + .get_link = ethtool_op_get_link,
> + .get_coalesce = netsec_et_get_coalesce,
> + .set_coalesce = netsec_et_set_coalesce,
> + .get_msglevel = netsec_et_get_msglevel,
> + .set_msglevel = netsec_et_set_msglevel,
> +};
> +
> +/*************************************************************/
> +/*********************** NETDEV_OPS **************************/
> +/*************************************************************/
> +
> +static struct sk_buff *netsec_alloc_skb(struct netsec_priv *priv,
> + struct netsec_desc *desc)
> +{
> + struct sk_buff *skb;
> +
> + if (device_get_dma_attr(priv->dev) == DEV_DMA_COHERENT) {
> + skb = netdev_alloc_skb_ip_align(priv->ndev, desc->len);
> + } else {
> + desc->len = L1_CACHE_ALIGN(desc->len);
> + skb = netdev_alloc_skb(priv->ndev, desc->len);
> + }
> + if (!skb)
> + return NULL;
> +
> + desc->addr = skb->data;
> + desc->dma_addr = dma_map_single(priv->dev, desc->addr, desc->len,
> + DMA_FROM_DEVICE);
> + if (dma_mapping_error(priv->dev, desc->dma_addr)) {
> + dev_kfree_skb_any(skb);
> + return NULL;
> + }
> + return skb;
> +}
> +
> +static void netsec_set_rx_de(struct netsec_priv *priv,
> + struct netsec_desc_ring *dring, u16 idx,
> + const struct netsec_desc *desc,
> + struct sk_buff *skb)
> +{
> + struct netsec_de *de = dring->vaddr + DESC_SZ * idx;
> + u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
> + (1 << NETSEC_RX_PKT_FS_FIELD) |
> + (1 << NETSEC_RX_PKT_LS_FIELD);
> +
> + if (idx == DESC_NUM - 1)
> + attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
> +
> + de->data_buf_addr_up = upper_32_bits(desc->dma_addr);
> + de->data_buf_addr_lw = lower_32_bits(desc->dma_addr);
> + de->buf_len_info = desc->len;
> + de->attr = attr;
> + dma_wmb();
> +
> + dring->desc[idx].dma_addr = desc->dma_addr;
> + dring->desc[idx].addr = desc->addr;
> + dring->desc[idx].len = desc->len;
> + dring->desc[idx].skb = skb;
> +}
> +
> +static struct sk_buff *netsec_get_rx_de(struct netsec_priv *priv,
> + struct netsec_desc_ring *dring,
> + u16 idx,
> + struct netsec_rx_pkt_info *rxpi,
> + struct netsec_desc *desc, u16 *len)
> +{
> + struct netsec_de de = {};
> +
> + memcpy(&de, dring->vaddr + DESC_SZ * idx, DESC_SZ);
> +
> + *len = de.buf_len_info >> 16;
> +
> + rxpi->err_flag = (de.attr >> NETSEC_RX_PKT_ER_FIELD) & 1;
> + rxpi->rx_cksum_result = (de.attr >> NETSEC_RX_PKT_CO_FIELD) & 3;
> + rxpi->err_code = (de.attr >> NETSEC_RX_PKT_ERR_FIELD) &
> + NETSEC_RX_PKT_ERR_MASK;
> + *desc = dring->desc[idx];
> + return desc->skb;
> +}
> +
> +static struct sk_buff *netsec_get_rx_pkt_data(struct netsec_priv *priv,
> + struct netsec_rx_pkt_info *rxpi,
> + struct netsec_desc *desc,
> + u16 *len)
> +{
> + struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
> + struct sk_buff *tmp_skb, *skb = NULL;
> + struct netsec_desc td;
> + int tail;
> +
> + *rxpi = (struct netsec_rx_pkt_info){};
> +
> + td.len = priv->ndev->mtu + 22;
> +
> + tmp_skb = netsec_alloc_skb(priv, &td);
> +
> + dma_rmb();
> +
> + tail = DRING_TAIL(dring);
> +
> + if (!tmp_skb) {
> + netsec_set_rx_de(priv, dring, tail, &dring->desc[tail],
> + dring->desc[tail].skb);
> + } else {
> + skb = netsec_get_rx_de(priv, dring, tail, rxpi, desc, len);
> + netsec_set_rx_de(priv, dring, tail, &td, tmp_skb);
> + }
> +
> + MOVE_TAIL(dring);
> + dring->pkt_cnt--;
> +
> + return skb;
> +}
> +
> +static int netsec_clean_tx_dring(struct netsec_priv *priv, int budget)
> +{
> + struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
> + unsigned int pkts, bytes;
> +
> + dring->pkt_cnt += netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
> +
> + if (dring->pkt_cnt < budget)
> + budget = dring->pkt_cnt;
> +
> + pkts = 0;
> + bytes = 0;
> +
> + while (pkts < budget) {
> + struct netsec_desc *desc;
> + struct netsec_de *entry;
> + int tail, eop;
> +
> + tail = DRING_TAIL(dring);
> + MOVE_TAIL(dring);
> +
> + desc = &dring->desc[tail];
> + entry = dring->vaddr + DESC_SZ * tail;
> +
> + eop = (entry->attr >> NETSEC_TX_LAST) & 1;
> +
> + dma_unmap_single(priv->dev, desc->dma_addr, desc->len,
> + DMA_TO_DEVICE);
> + if (eop) {
> + pkts++;
> + bytes += desc->skb->len;
> + dev_kfree_skb(desc->skb);
> + }
> + *desc = (struct netsec_desc){};
> + }
> + dring->pkt_cnt -= budget;
> +
> + priv->ndev->stats.tx_packets += budget;
> + priv->ndev->stats.tx_bytes += bytes;
> +
> + netdev_completed_queue(priv->ndev, budget, bytes);
> +
> + return budget;
> +}
> +
> +static int netsec_process_tx(struct netsec_priv *priv, int budget)
> +{
> + struct net_device *ndev = priv->ndev;
> + int new, done = 0;
> +
> + do {
> + new = netsec_clean_tx_dring(priv, budget);
> + done += new;
> + budget -= new;
> + } while (new);
> +
> + if (done && netif_queue_stopped(ndev))
> + netif_wake_queue(ndev);
> +
> + return done;
> +}
> +
> +static int netsec_process_rx(struct netsec_priv *priv, int budget)
> +{
> + struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
> + struct net_device *ndev = priv->ndev;
> + struct netsec_rx_pkt_info rx_info;
> + int done = 0, rx_num = 0;
> + struct netsec_desc desc;
> + struct sk_buff *skb;
> + u16 len;
> +
> + while (done < budget) {
> + if (!rx_num) {
> + rx_num = netsec_read(priv, NETSEC_REG_NRM_RX_PKTCNT);
> + dring->pkt_cnt += rx_num;
> + JUMP_HEAD(dring, rx_num);
> +
> + rx_num = dring->pkt_cnt;
> + if (!rx_num)
> + break;
> + }
> + done++;
> + rx_num--;
> + skb = netsec_get_rx_pkt_data(priv, &rx_info, &desc, &len);
> + if (unlikely(!skb) || rx_info.err_flag) {
> + netif_err(priv, drv, priv->ndev,
> + "%s: rx fail err(%d)\n",
> + __func__, rx_info.err_code);
> + ndev->stats.rx_dropped++;
> + continue;
> + }
> +
> + dma_unmap_single(priv->dev, desc.dma_addr, desc.len,
> + DMA_FROM_DEVICE);
> + skb_put(skb, len);
> + skb->protocol = eth_type_trans(skb, priv->ndev);
> +
> + if (priv->rx_cksum_offload_flag &&
> + rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK)
> + skb->ip_summed = CHECKSUM_UNNECESSARY;
> +
> + if (napi_gro_receive(&priv->napi, skb) != GRO_DROP) {
> + ndev->stats.rx_packets++;
> + ndev->stats.rx_bytes += len;
> + }
> + }
> +
> + return done;
> +}
> +
> +static int netsec_napi_poll(struct napi_struct *napi, int budget)
> +{
> + struct netsec_priv *priv;
> + struct net_device *ndev;
> + int tx, rx, done, todo;
> +
> + priv = container_of(napi, struct netsec_priv, napi);
> + ndev = priv->ndev;
> +
> + todo = budget;
> + do {
> + if (!todo)
> + break;
> +
> + tx = netsec_process_tx(priv, todo);
> + todo -= tx;
> +
> + if (!todo)
> + break;
> +
> + rx = netsec_process_rx(priv, todo);
> + todo -= rx;
> + } while (rx || tx);
> +
> + done = budget - todo;
> +
> + if (done < budget && napi_complete_done(napi, done)) {
> + unsigned long flags;
> +
> + spin_lock_irqsave(&priv->reglock, flags);
> + netsec_write(priv, NETSEC_REG_INTEN_SET,
> + NETSEC_IRQ_RX | NETSEC_IRQ_TX);
> + spin_unlock_irqrestore(&priv->reglock, flags);
> + }
> +
> + return done;
> +}
> +
> +static void netsec_set_tx_de(struct netsec_priv *priv,
> + struct netsec_desc_ring *dring,
> + const struct netsec_tx_pkt_ctrl *tx_ctrl,
> + const struct netsec_desc *desc,
> + struct sk_buff *skb)
> +{
> + struct netsec_de *de;
> + int idx = DRING_HEAD(dring);
> + u32 attr;
> +
> + de = dring->vaddr + (DESC_SZ * idx);
> +
> + attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
> + (1 << NETSEC_TX_SHIFT_PT_FIELD) |
> + (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
> + (1 << NETSEC_TX_SHIFT_FS_FIELD) |
> + (1 << NETSEC_TX_LAST) |
> + (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) |
> + (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) |
> + (1 << NETSEC_TX_SHIFT_TRS_FIELD);
> + if (idx == DESC_NUM - 1)
> + attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD);
> +
> + de->data_buf_addr_up = upper_32_bits(desc->dma_addr);
> + de->data_buf_addr_lw = lower_32_bits(desc->dma_addr);
> + de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len;
> + de->attr = attr;
> + dma_wmb();
> +
> + dring->desc[idx] = *desc;
> + dring->desc[idx].skb = skb;
> +
> + MOVE_HEAD(dring);
> +}
> +
> +static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb,
> + struct net_device *ndev)
> +{
> + struct netsec_priv *priv = netdev_priv(ndev);
> + struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
> + struct netsec_tx_pkt_ctrl tx_ctrl = {};
> + struct netsec_desc tx_desc;
> + u16 tso_seg_len = 0;
> +
> + /* differentiate between full/emtpy ring */
> + if (available_descs(dring) < 2) {
> + netif_err(priv, drv, priv->ndev, "%s: TxQFull!\n", __func__);
> + netif_stop_queue(priv->ndev);
> + dma_wmb();
> + return NETDEV_TX_BUSY;
> + }
> +
> + if (skb->ip_summed == CHECKSUM_PARTIAL)
> + tx_ctrl.cksum_offload_flag = true;
> +
> + if (skb_is_gso(skb))
> + tso_seg_len = skb_shinfo(skb)->gso_size;
> +
> + if (tso_seg_len > 0) {
> + if (skb->protocol == htons(ETH_P_IP)) {
> + ip_hdr(skb)->tot_len = 0;
> + tcp_hdr(skb)->check =
> + ~tcp_v4_check(0, ip_hdr(skb)->saddr,
> + ip_hdr(skb)->daddr, 0);
> + } else {
> + ipv6_hdr(skb)->payload_len = 0;
> + tcp_hdr(skb)->check =
> + ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
> + &ipv6_hdr(skb)->daddr,
> + 0, IPPROTO_TCP, 0);
> + }
> +
> + tx_ctrl.tcp_seg_offload_flag = true;
> + tx_ctrl.tcp_seg_len = tso_seg_len;
> + }
> +
> + tx_desc.dma_addr = dma_map_single(priv->dev, skb->data,
> + skb_headlen(skb), DMA_TO_DEVICE);
> + if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) {
> + netif_err(priv, drv, priv->ndev,
> + "%s: DMA mapping failed\n", __func__);
> + ndev->stats.tx_dropped++;
> + dev_kfree_skb_any(skb);
> + return NETDEV_TX_OK;
> + }
> + tx_desc.addr = skb->data;
> + tx_desc.len = skb_headlen(skb);
> +
> + skb_tx_timestamp(skb);
> + netdev_sent_queue(priv->ndev, skb->len);
> +
> + netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb);
> + netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
> +
> + return NETDEV_TX_OK;
> +}
> +
> +static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id)
> +{
> + struct netsec_desc_ring *dring = &priv->desc_ring[id];
> + struct netsec_desc *desc;
> + u16 idx;
> +
> + if (!dring->vaddr || !dring->desc)
> + return;
> +
> + for (idx = 0; idx < DESC_NUM; idx++) {
> + desc = &dring->desc[idx];
> + if (!desc->addr)
> + continue;
> +
> + dma_unmap_single(priv->dev, desc->dma_addr, desc->len,
> + id == NETSEC_RING_RX ? DMA_FROM_DEVICE :
> + DMA_TO_DEVICE);
> + dev_kfree_skb(desc->skb);
> + }
> +
> + memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM);
> + memset(dring->vaddr, 0, DESC_SZ * DESC_NUM);
> +
> + dring->head = 0;
> + dring->tail = 0;
> + dring->pkt_cnt = 0;
> +}
> +
> +static void netsec_free_dring(struct netsec_priv *priv, int id)
> +{
> + struct netsec_desc_ring *dring = &priv->desc_ring[id];
> +
> + if (dring->vaddr) {
> + dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM,
> + dring->vaddr, dring->desc_phys);
> + dring->vaddr = NULL;
> + }
> +
> + kfree(dring->desc);
> + dring->desc = NULL;
> +}
> +
> +static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id)
> +{
> + struct netsec_desc_ring *dring = &priv->desc_ring[id];
> + int ret = 0;
> +
> + dring->vaddr = dma_zalloc_coherent(priv->dev, DESC_SZ * DESC_NUM,
> + &dring->desc_phys, GFP_KERNEL);
> + if (!dring->vaddr) {
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + dring->desc = kzalloc(DESC_NUM * sizeof(*dring->desc), GFP_KERNEL);
> + if (!dring->desc) {
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + return 0;
> +err:
> + netsec_free_dring(priv, id);
> +
> + return ret;
> +}
> +
> +static int netsec_setup_rx_dring(struct netsec_priv *priv)
> +{
> + struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
> + struct netsec_desc desc;
> + struct sk_buff *skb;
> + int n;
> +
> + desc.len = priv->ndev->mtu + 22;
> +
> + for (n = 0; n < DESC_NUM; n++) {
> + skb = netsec_alloc_skb(priv, &desc);
> + if (!skb) {
> + netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
> + return -ENOMEM;
> + }
> + netsec_set_rx_de(priv, dring, n, &desc, skb);
> + }
> +
> + return 0;
> +}
> +
> +static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg,
> + u32 addr_h, u32 addr_l, u32 size)
> +{
> + u64 base = (u64)addr_h << 32 | addr_l;
> + __le32 *ucode;
> + u32 i;
> +
> + ucode = memremap(base, size * sizeof(u32), MEMREMAP_WT);
> + if (!ucode)
> + return -ENOMEM;
> +
> + for (i = 0; i < size; i++)
> + netsec_write(priv, reg, le32_to_cpu(ucode[i]));
> +
> + memunmap(ucode);
> + return 0;
> +}
> +
> +static int netsec_netdev_load_microcode(struct netsec_priv *priv)
> +{
> + int err;
> +
> + err = netsec_netdev_load_ucode_region(
> + priv, NETSEC_REG_DMAC_HM_CMD_BUF,
> + le32_to_cpup(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H),
> + le32_to_cpup(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L),
> + le32_to_cpup(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE));
... here, and in other places below, you are still dereferencing
eeprom_base as if it is a pointer, which is not allowed with in the
__iomem address space. This should use readl() instead [which happens
to incorporate the endian swap as well]
> + if (err)
> + return err;
> +
> + err = netsec_netdev_load_ucode_region(
> + priv, NETSEC_REG_DMAC_MH_CMD_BUF,
> + le32_to_cpup(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H),
> + le32_to_cpup(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L),
> + le32_to_cpup(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE));
> + if (err)
> + return err;
> +
> + err = netsec_netdev_load_ucode_region(
> + priv, NETSEC_REG_PKT_CMD_BUF,
> + 0,
> + le32_to_cpup(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS),
> + le32_to_cpup(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE));
> + if (err)
> + return err;
> +
> + return 0;
> +}
> +
> +static int netsec_reset_hardware(struct netsec_priv *priv)
> +{
> + u32 value;
> + int err;
> +
> + /* stop DMA engines */
> + if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) {
> + netsec_write(priv, NETSEC_REG_DMA_HM_CTRL,
> + NETSEC_DMA_CTRL_REG_STOP);
> + netsec_write(priv, NETSEC_REG_DMA_MH_CTRL,
> + NETSEC_DMA_CTRL_REG_STOP);
> +
> + while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) &
> + NETSEC_DMA_CTRL_REG_STOP)
> + cpu_relax();
> +
> + while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) &
> + NETSEC_DMA_CTRL_REG_STOP)
> + cpu_relax();
> + }
> +
> + netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
> + netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
> + netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
> +
> + while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0)
> + cpu_relax();
> +
> + /* set desc_start addr */
> + netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
> + upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_phys));
> + netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
> + lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_phys));
> +
> + netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
> + upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_phys));
> + netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
> + lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_phys));
> +
> + /* set normal tx dring ring config */
> + netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG,
> + 1 << NETSEC_REG_DESC_ENDIAN);
> + netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG,
> + 1 << NETSEC_REG_DESC_ENDIAN);
> +
> + err = netsec_netdev_load_microcode(priv);
> + if (err) {
> + netif_err(priv, probe, priv->ndev,
> + "%s: failed to load microcode (%d)\n", __func__, err);
> + return err;
> + }
> +
> + /* start DMA engines */
> + netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
> + netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
> +
> + usleep_range(1000, 2000);
> +
> + if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) &
> + NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) {
> + netif_err(priv, probe, priv->ndev,
> + "microengine start failed\n");
> + return -ENXIO;
> + }
> + netsec_write(priv, NETSEC_REG_TOP_STATUS,
> + NETSEC_TOP_IRQ_REG_CODE_LOAD_END);
> +
> + value = NETSEC_PKT_CTRL_REG_MODE_NRM;
> + if (priv->ndev->mtu > ETH_DATA_LEN)
> + value |= NETSEC_PKT_CTRL_REG_EN_JUMBO;
> +
> + /* change to normal mode */
> + netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
> + netsec_write(priv, NETSEC_REG_PKT_CTRL, value);
> +
> + while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
> + NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0)
> + cpu_relax();
> +
> + /* clear any pending EMPTY/ERR irq status */
> + netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
> +
> + /* Disable TX & RX intr */
> + netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
> +
> + return 0;
> +}
> +
> +static int netsec_start_gmac(struct netsec_priv *priv)
> +{
> + struct phy_device *phydev = priv->ndev->phydev;
> + u32 value = 0;
> + int ret;
> +
> + if (phydev->speed != SPEED_1000)
> + value = (NETSEC_GMAC_MCR_REG_CST |
> + NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
> +
> + if (netsec_mac_write(priv, GMAC_REG_MCR, value))
> + return -ETIMEDOUT;
> + if (netsec_mac_write(priv, GMAC_REG_BMR,
> + NETSEC_GMAC_BMR_REG_RESET))
> + return -ETIMEDOUT;
> +
> + /* Wait soft reset */
> + usleep_range(1000, 5000);
> +
> + ret = netsec_mac_read(priv, GMAC_REG_BMR, &value);
> + if (ret)
> + return ret;
> + if (value & NETSEC_GMAC_BMR_REG_SWR)
> + return -EAGAIN;
> +
> + netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1);
> + if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))
> + return -ETIMEDOUT;
> +
> + netsec_write(priv, MAC_REG_DESC_INIT, 1);
> + if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
> + return -ETIMEDOUT;
> +
> + if (netsec_mac_write(priv, GMAC_REG_BMR,
> + NETSEC_GMAC_BMR_REG_COMMON))
> + return -ETIMEDOUT;
> + if (netsec_mac_write(priv, GMAC_REG_RDLAR,
> + NETSEC_GMAC_RDLAR_REG_COMMON))
> + return -ETIMEDOUT;
> + if (netsec_mac_write(priv, GMAC_REG_TDLAR,
> + NETSEC_GMAC_TDLAR_REG_COMMON))
> + return -ETIMEDOUT;
> + if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001))
> + return -ETIMEDOUT;
> +
> + ret = netsec_mac_update_to_phy_state(priv);
> + if (ret)
> + return ret;
> +
> + ret = netsec_mac_read(priv, GMAC_REG_OMR, &value);
> + if (ret)
> + return ret;
> +
> + value |= NETSEC_GMAC_OMR_REG_SR;
> + value |= NETSEC_GMAC_OMR_REG_ST;
> +
> + netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
> + netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
> +
> + netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce);
> +
> + if (netsec_mac_write(priv, GMAC_REG_OMR, value))
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int netsec_stop_gmac(struct netsec_priv *priv)
> +{
> + u32 value;
> + int ret;
> +
> + ret = netsec_mac_read(priv, GMAC_REG_OMR, &value);
> + if (ret)
> + return ret;
> + value &= ~NETSEC_GMAC_OMR_REG_SR;
> + value &= ~NETSEC_GMAC_OMR_REG_ST;
> +
> + /* disable all interrupts */
> + netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
> + netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
> +
> + return netsec_mac_write(priv, GMAC_REG_OMR, value);
> +}
> +
> +static void netsec_phy_adjust_link(struct net_device *ndev)
> +{
> + struct netsec_priv *priv = netdev_priv(ndev);
> +
> + if (ndev->phydev->link)
> + netsec_start_gmac(priv);
> + else
> + netsec_stop_gmac(priv);
> +
> + phy_print_status(ndev->phydev);
> +}
> +
> +static irqreturn_t netsec_irq_handler(int irq, void *dev_id)
> +{
> + struct netsec_priv *priv = dev_id;
> + u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS);
> + unsigned long flags;
> +
> + /* Disable interrupts */
> + if (status & NETSEC_IRQ_TX) {
> + val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS);
> + netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val);
> + }
> + if (status & NETSEC_IRQ_RX) {
> + val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS);
> + netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val);
> + }
> +
> + spin_lock_irqsave(&priv->reglock, flags);
> + netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
> + spin_unlock_irqrestore(&priv->reglock, flags);
> +
> + napi_schedule(&priv->napi);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int netsec_netdev_open(struct net_device *ndev)
> +{
> + struct netsec_priv *priv = netdev_priv(ndev);
> + int ret;
> +
> + pm_runtime_get_sync(priv->dev);
> +
> + ret = netsec_setup_rx_dring(priv);
> + if (ret) {
> + netif_err(priv, probe, priv->ndev,
> + "%s: fail setup ring\n", __func__);
> + goto err1;
> + }
> +
> + ret = request_irq(priv->ndev->irq, netsec_irq_handler,
> + IRQF_SHARED, "netsec", priv);
> + if (ret) {
> + netif_err(priv, drv, priv->ndev, "request_irq failed\n");
> + goto err2;
> + }
> +
> + if (dev_of_node(priv->dev)) {
> + if (!of_phy_connect(priv->ndev, priv->phy_np,
> + netsec_phy_adjust_link, 0,
> + priv->phy_interface)) {
> + netif_err(priv, link, priv->ndev, "missing PHY\n");
> + goto err3;
> + }
> + } else {
> + ret = phy_connect_direct(priv->ndev, priv->phydev,
> + netsec_phy_adjust_link,
> + priv->phy_interface);
> + if (ret) {
> + netif_err(priv, link, priv->ndev,
> + "phy_connect_direct() failed (%d)\n", ret);
> + goto err3;
> + }
> + }
> +
> + phy_start(ndev->phydev);
> +
> + netsec_start_gmac(priv);
> + napi_enable(&priv->napi);
> + netif_start_queue(ndev);
> +
> + /* Enable RX intr. */
> + netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX);
> +
> + return 0;
> +err3:
> + free_irq(priv->ndev->irq, priv);
> +err2:
> + netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
> +err1:
> + pm_runtime_put_sync(priv->dev);
> + return ret;
> +}
> +
> +static int netsec_netdev_stop(struct net_device *ndev)
> +{
> + struct netsec_priv *priv = netdev_priv(ndev);
> +
> + netif_stop_queue(priv->ndev);
> + dma_wmb();
> +
> + napi_disable(&priv->napi);
> +
> + netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
> + netsec_stop_gmac(priv);
> +
> + free_irq(priv->ndev->irq, priv);
> +
> + netsec_uninit_pkt_dring(priv, NETSEC_RING_TX);
> + netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
> +
> + phy_stop(ndev->phydev);
> + phy_disconnect(ndev->phydev);
> +
> + pm_runtime_put_sync(priv->dev);
> +
> + return 0;
> +}
> +
> +static int netsec_netdev_init(struct net_device *ndev)
> +{
> + struct netsec_priv *priv = netdev_priv(ndev);
> + int ret;
> +
> + ret = netsec_alloc_dring(priv, NETSEC_RING_TX);
> + if (ret)
> + return ret;
> +
> + ret = netsec_alloc_dring(priv, NETSEC_RING_RX);
> + if (ret)
> + goto err1;
> +
> + ret = netsec_reset_hardware(priv);
> + if (ret)
> + goto err2;
> +
> + return 0;
> +err2:
> + netsec_free_dring(priv, NETSEC_RING_RX);
> +err1:
> + netsec_free_dring(priv, NETSEC_RING_TX);
> + return ret;
> +}
> +
> +static void netsec_netdev_uninit(struct net_device *ndev)
> +{
> + struct netsec_priv *priv = netdev_priv(ndev);
> +
> + netsec_free_dring(priv, NETSEC_RING_RX);
> + netsec_free_dring(priv, NETSEC_RING_TX);
> +}
> +
> +static int netsec_netdev_set_features(struct net_device *ndev,
> + netdev_features_t features)
> +{
> + struct netsec_priv *priv = netdev_priv(ndev);
> +
> + priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM);
> +
> + return 0;
> +}
> +
> +static int netsec_netdev_ioctl(struct net_device *ndev, struct ifreq *ifr,
> + int cmd)
> +{
> + return phy_mii_ioctl(ndev->phydev, ifr, cmd);
> +}
> +
> +static const struct net_device_ops netsec_netdev_ops = {
> + .ndo_init = netsec_netdev_init,
> + .ndo_uninit = netsec_netdev_uninit,
> + .ndo_open = netsec_netdev_open,
> + .ndo_stop = netsec_netdev_stop,
> + .ndo_start_xmit = netsec_netdev_start_xmit,
> + .ndo_set_features = netsec_netdev_set_features,
> + .ndo_set_mac_address = eth_mac_addr,
> + .ndo_validate_addr = eth_validate_addr,
> + .ndo_do_ioctl = netsec_netdev_ioctl,
> +};
> +
> +/*************************************************************/
> +/*************************************************************/
> +
> +static int netsec_of_probe(struct platform_device *pdev,
> + struct netsec_priv *priv)
> +{
> + int clk_count, ret, i;
> +
> + priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
> + if (!priv->phy_np) {
> + dev_err(&pdev->dev, "missing required property 'phy-handle'\n");
> + return -EINVAL;
> + }
> +
> + /* we require named clocks if there is more than one */
> + clk_count = of_property_count_strings(pdev->dev.of_node, "clock-names");
> + if (clk_count > 1) {
> + if (clk_count > ARRAY_SIZE(priv->clk)) {
> + dev_err(&pdev->dev, "too many clocks specified (%d)\n",
> + clk_count);
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < clk_count; i++) {
> + const char *clk_name;
> +
> + ret = of_property_read_string_index(pdev->dev.of_node,
> + "clock-names", i,
> + &clk_name);
> + if (ret) {
> + dev_err(&pdev->dev,
> + "failed to parse 'clock-names'\n");
> + return ret;
> + }
> + priv->clk[i] = devm_clk_get(&pdev->dev, clk_name);
> + if (!strcmp(clk_name, "phy_refclk")) {
> + priv->freq = clk_get_rate(priv->clk[i]);
> + dev_dbg(&pdev->dev,
> + "found PHY refclock #%d freq %u\n",
> + i, priv->freq);
> + }
> + }
> + priv->clock_count = clk_count;
> + } else {
> + priv->clk[0] = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(priv->clk)) {
> + dev_err(&pdev->dev,
> + "missing required property 'clocks'\n");
> + return PTR_ERR(priv->clk);
> + }
> + priv->freq = clk_get_rate(priv->clk[0]);
> + priv->clock_count = 1;
> + }
> + return 0;
> +}
> +
> +static int netsec_acpi_probe(struct platform_device *pdev,
> + struct netsec_priv *priv, u32 *phy_addr)
> +{
> + int ret;
> +
> + if (!IS_ENABLED(CONFIG_ACPI))
> + return -ENODEV;
> +
> + ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr);
> + if (ret) {
> + dev_err(&pdev->dev,
> + "missing required property 'phy-channel'\n");
> + return ret;
> + }
> +
> + ret = device_property_read_u32(&pdev->dev,
> + "socionext,phy-clock-frequency",
> + &priv->freq);
> + if (ret)
> + dev_err(&pdev->dev,
> + "missing required property 'socionext,phy-clock-frequency'\n");
> + return ret;
> +}
> +
> +static void netsec_unregister_mdio(struct netsec_priv *priv)
> +{
> + struct phy_device *phydev = priv->phydev;
> +
> + if (!dev_of_node(priv->dev) && phydev) {
> + phy_device_remove(phydev);
> + phy_device_free(phydev);
> + }
> +
> + mdiobus_unregister(priv->mii_bus);
> +}
> +
> +static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr)
> +{
> + struct mii_bus *bus;
> + int ret;
> +
> + bus = devm_mdiobus_alloc(priv->dev);
> + if (!bus)
> + return -ENOMEM;
> +
> + snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev));
> + bus->priv = priv;
> + bus->name = "SNI NETSEC MDIO";
> + bus->read = netsec_phy_read;
> + bus->write = netsec_phy_write;
> + bus->parent = priv->dev;
> + priv->mii_bus = bus;
> +
> + if (dev_of_node(priv->dev)) {
> + ret = of_mdiobus_register(bus, dev_of_node(priv->dev));
> + if (ret) {
> + dev_err(priv->dev, "mdiobus register err(%d)\n", ret);
> + return ret;
> + }
> + } else {
> + /* Mask out all PHYs from auto probing. */
> + bus->phy_mask = ~0;
> + ret = mdiobus_register(bus);
> + if (ret) {
> + dev_err(priv->dev, "mdiobus register err(%d)\n", ret);
> + return ret;
> + }
> +
> + priv->phydev = get_phy_device(priv->mii_bus, phy_addr, false);
> + if (IS_ERR(priv->phydev)) {
> + ret = PTR_ERR(priv->phydev);
> + dev_err(priv->dev, "get_phy_device err(%d)\n", ret);
> + priv->phydev = NULL;
> + return -ENODEV;
> + }
> +
> + ret = phy_device_register(priv->phydev);
> + if (ret)
> + dev_err(priv->dev,
> + "phy_device_register err(%d)\n", ret);
> + }
> +
> + return ret;
> +}
> +
> +static int netsec_probe(struct platform_device *pdev)
> +{
> + struct resource *mmio_res, *eeprom_res, *irq_res;
> + u8 *mac, macbuf[ETH_ALEN];
> + struct netsec_priv *priv;
> + struct net_device *ndev;
> + u32 hw_ver, phy_addr = 0;
> + int ret;
> +
> + mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!mmio_res) {
> + dev_err(&pdev->dev, "No MMIO resource found.\n");
> + return -ENODEV;
> + }
> +
> + eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + if (!eeprom_res) {
> + dev_info(&pdev->dev, "No EEPROM resource found.\n");
> + return -ENODEV;
> + }
> +
> + irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
> + if (!irq_res) {
> + dev_err(&pdev->dev, "No IRQ resource found.\n");
> + return -ENODEV;
> + }
> +
> + ndev = alloc_etherdev(sizeof(*priv));
> + if (!ndev)
> + return -ENOMEM;
> +
> + priv = netdev_priv(ndev);
> +
> + spin_lock_init(&priv->reglock);
> + SET_NETDEV_DEV(ndev, &pdev->dev);
> + platform_set_drvdata(pdev, priv);
> + ndev->irq = irq_res->start;
> + priv->dev = &pdev->dev;
> + priv->ndev = ndev;
> +
> + priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV |
> + NETIF_MSG_LINK | NETIF_MSG_PROBE;
> +
> + priv->phy_interface = device_get_phy_mode(&pdev->dev);
> + if (priv->phy_interface < 0) {
> + dev_err(&pdev->dev, "missing required property 'phy-mode'\n");
> + ret = -ENODEV;
> + goto free_ndev;
> + }
> +
> + priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start,
> + resource_size(mmio_res));
> + if (!priv->ioaddr) {
> + dev_err(&pdev->dev, "devm_ioremap() failed\n");
> + ret = -ENXIO;
> + goto free_ndev;
> + }
> +
> + priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start,
> + resource_size(eeprom_res));
> + if (!priv->eeprom_base) {
> + dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n");
> + ret = -ENXIO;
> + goto free_ndev;
> + }
> +
> + mac = device_get_mac_address(&pdev->dev, macbuf, sizeof(macbuf));
> + if (mac)
> + ether_addr_copy(ndev->dev_addr, mac);
> +
> + if (priv->eeprom_base &&
> + (!mac || !is_valid_ether_addr(ndev->dev_addr))) {
> + const u8 *macp = priv->eeprom_base + NETSEC_EEPROM_MAC_ADDRESS;
> +
> + ndev->dev_addr[0] = macp[3];
> + ndev->dev_addr[1] = macp[2];
> + ndev->dev_addr[2] = macp[1];
> + ndev->dev_addr[3] = macp[0];
> + ndev->dev_addr[4] = macp[7];
> + ndev->dev_addr[5] = macp[6];
> + }
> +
> + if (!is_valid_ether_addr(ndev->dev_addr)) {
> + dev_warn(&pdev->dev, "No MAC address found, using random\n");
> + eth_hw_addr_random(ndev);
> + }
> +
> + if (dev_of_node(&pdev->dev))
> + ret = netsec_of_probe(pdev, priv);
> + else
> + ret = netsec_acpi_probe(pdev, priv, &phy_addr);
> + if (ret)
> + goto free_ndev;
> +
> + if (!priv->freq) {
> + dev_err(&pdev->dev, "missing PHY reference clock frequency\n");
> + ret = -ENODEV;
> + goto free_ndev;
> + }
> +
> + /* default for throughput */
> + priv->et_coalesce.rx_coalesce_usecs = 500;
> + priv->et_coalesce.rx_max_coalesced_frames = 8;
> + priv->et_coalesce.tx_coalesce_usecs = 500;
> + priv->et_coalesce.tx_max_coalesced_frames = 8;
> +
> + ret = device_property_read_u32(&pdev->dev, "max-frame-size",
> + &ndev->max_mtu);
> + if (ret < 0)
> + ndev->max_mtu = ETH_DATA_LEN;
> +
> + /* runtime_pm coverage just for probe, open/close also cover it */
> + pm_runtime_enable(&pdev->dev);
> + pm_runtime_get_sync(&pdev->dev);
> +
> + hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER);
> + /* this driver only supports F_TAIKI style NETSEC */
> + if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) !=
> + NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) {
> + ret = -ENODEV;
> + goto pm_disable;
> + }
> +
> + dev_info(&pdev->dev, "hardware revision %d.%d\n",
> + hw_ver >> 16, hw_ver & 0xffff);
> +
> + netif_napi_add(ndev, &priv->napi, netsec_napi_poll, NAPI_BUDGET);
> +
> + ndev->netdev_ops = &netsec_netdev_ops;
> + ndev->ethtool_ops = &netsec_ethtool_ops;
> +
> + ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO |
> + NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
> + ndev->hw_features = ndev->features;
> +
> + priv->rx_cksum_offload_flag = true;
> +
> + ret = netsec_register_mdio(priv, phy_addr);
> + if (ret)
> + goto unreg_napi;
> +
> + if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
> + dev_warn(&pdev->dev, "Failed to enable 64-bit DMA\n");
> +
> + ret = register_netdev(ndev);
> + if (ret) {
> + netif_err(priv, probe, ndev, "register_netdev() failed\n");
> + goto unreg_mii;
> + }
> +
> + pm_runtime_put_sync(&pdev->dev);
> + return 0;
> +
> +unreg_mii:
> + netsec_unregister_mdio(priv);
> +unreg_napi:
> + netif_napi_del(&priv->napi);
> +pm_disable:
> + pm_runtime_put_sync(&pdev->dev);
> + pm_runtime_disable(&pdev->dev);
> +free_ndev:
> + free_netdev(ndev);
> + dev_err(&pdev->dev, "init failed\n");
> +
> + return ret;
> +}
> +
> +static int netsec_remove(struct platform_device *pdev)
> +{
> + struct netsec_priv *priv = platform_get_drvdata(pdev);
> +
> + unregister_netdev(priv->ndev);
> +
> + netsec_unregister_mdio(priv);
> +
> + netif_napi_del(&priv->napi);
> +
> + pm_runtime_disable(&pdev->dev);
> + free_netdev(priv->ndev);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int netsec_runtime_suspend(struct device *dev)
> +{
> + struct netsec_priv *priv = dev_get_drvdata(dev);
> + int n;
> +
> + netsec_write(priv, NETSEC_REG_CLK_EN, 0);
> +
> + for (n = priv->clock_count - 1; n >= 0; n--)
> + clk_disable_unprepare(priv->clk[n]);
> +
> + return 0;
> +}
> +
> +static int netsec_runtime_resume(struct device *dev)
> +{
> + struct netsec_priv *priv = dev_get_drvdata(dev);
> + int n;
> +
> + /* first let the clocks back on */
> + for (n = 0; n < priv->clock_count; n++)
> + clk_prepare_enable(priv->clk[n]);
> +
> + netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D |
> + NETSEC_CLK_EN_REG_DOM_C |
> + NETSEC_CLK_EN_REG_DOM_G);
> + return 0;
> +}
> +#endif
> +
> +static const struct dev_pm_ops netsec_pm_ops = {
> + SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL)
> +};
> +
> +static const struct of_device_id netsec_dt_ids[] = {
> + { .compatible = "socionext,synquacer-netsec" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, netsec_dt_ids);
> +
> +#ifdef CONFIG_ACPI
> +static const struct acpi_device_id netsec_acpi_ids[] = {
> + { "SCX0001" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids);
> +#endif
> +
> +static struct platform_driver netsec_driver = {
> + .probe = netsec_probe,
> + .remove = netsec_remove,
> + .driver = {
> + .name = "netsec",
> + .pm = &netsec_pm_ops,
> + .of_match_table = netsec_dt_ids,
> + .acpi_match_table = ACPI_PTR(netsec_acpi_ids),
> + },
> +};
> +module_platform_driver(netsec_driver);
> +
> +MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>");
> +MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
> +MODULE_DESCRIPTION("NETSEC Ethernet driver");
> +MODULE_LICENSE("GPL");
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v2 3/6] ARM: sun4i: Convert to CCU
From: Priit Laes @ 2017-12-12 17:26 UTC (permalink / raw)
To: Kevin Hilman
Cc: Chen-Yu Tsai, Maxime Ripard, lkml, linux-arm-kernel, devicetree,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng, Russell King,
Mark Rutland, Rob Herring, Stephen Boyd, Michael Turquette,
Philipp Zabel, Olof Johansson
In-Reply-To: <CAOi56cUjqjcZRz6VSwUWcrW=4RQyqyZHtm1vuM3HT2ypdPJ78g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Mon, Dec 11, 2017 at 02:22:30PM -0800, Kevin Hilman wrote:
> On Sun, Mar 26, 2017 at 10:20 AM, Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org> wrote:
> > Convert sun4i-a10.dtsi to new CCU driver.
> >
> > Signed-off-by: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
>
> I finally got around to bisecting a mainline boot failure on
> sun4i-a10-cubieboard that's been happening for quite a while. Based
> on on kernelci.org, it showed up sometime during the v4.15 merge
> window[1]. It bisected down to this commit (in mainline as commit
> 41193869f2bdb585ce09bfdd16d9482aadd560ad).
>
> When it fails, there is no output on the serial console, so I don't
> know exactly how it's failing, just that it no longer boots.
We tried out latest 4.15 with various compilers and it works:
- gcc version 7.1.1 20170622 (Red Hat Cross 7.1.1-3) (GCC) - A10 Gemei G9 tablet
- gcc 7.2.0-debian - A10 Cubieboard
>
> Kevin
>
> [1] https://kernelci.org/boot/id/5a2e10cd59b51430a9afa173/
>
> > ---
> > arch/arm/boot/dts/sun4i-a10.dtsi | 636 ++++----------------------------
> > 1 file changed, 82 insertions(+), 554 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
> > index ba20b48..0d8320a 100644
> > --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> > +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> > @@ -45,7 +45,8 @@
> >
> > #include <dt-bindings/thermal/thermal.h>
> >
> > -#include <dt-bindings/clock/sun4i-a10-pll2.h>
> > +#include <dt-bindings/clock/sunxi-a10-a20-ccu.h>
> > +#include <dt-bindings/reset/sunxi-a10-a20-ccu.h>
> > #include <dt-bindings/dma/sun4i-a10.h>
> > #include <dt-bindings/pinctrl/sun4i-a10.h>
> >
> > @@ -65,9 +66,9 @@
> > compatible = "allwinner,simple-framebuffer",
> > "simple-framebuffer";
> > allwinner,pipeline = "de_be0-lcd0-hdmi";
> > - clocks = <&ahb_gates 36>, <&ahb_gates 43>,
> > - <&ahb_gates 44>, <&de_be0_clk>,
> > - <&tcon0_ch1_clk>, <&dram_gates 26>;
> > + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI1>,
> > + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
> > + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
> > status = "disabled";
> > };
> >
> > @@ -75,10 +76,11 @@
> > compatible = "allwinner,simple-framebuffer",
> > "simple-framebuffer";
> > allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
> > - clocks = <&ahb_gates 36>, <&ahb_gates 43>,
> > - <&ahb_gates 44>, <&ahb_gates 46>,
> > - <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>,
> > - <&dram_gates 25>, <&dram_gates 26>;
> > + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI1>,
> > + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
> > + <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
> > + <&ccu CLK_TCON0_CH1>,
> > + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
> > status = "disabled";
> > };
> >
> > @@ -86,9 +88,10 @@
> > compatible = "allwinner,simple-framebuffer",
> > "simple-framebuffer";
> > allwinner,pipeline = "de_fe0-de_be0-lcd0";
> > - clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>,
> > - <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,
> > - <&dram_gates 25>, <&dram_gates 26>;
> > + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
> > + <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
> > + <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH1>,
> > + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
> > status = "disabled";
> > };
> >
> > @@ -96,11 +99,11 @@
> > compatible = "allwinner,simple-framebuffer",
> > "simple-framebuffer";
> > allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
> > - clocks = <&ahb_gates 34>, <&ahb_gates 36>,
> > - <&ahb_gates 44>, <&ahb_gates 46>,
> > - <&de_be0_clk>, <&de_fe0_clk>,
> > - <&tcon0_ch1_clk>, <&dram_gates 5>,
> > - <&dram_gates 25>, <&dram_gates 26>;
> > + clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
> > + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
> > + <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
> > + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
> > + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
> > status = "disabled";
> > };
> > };
> > @@ -112,7 +115,7 @@
> > device_type = "cpu";
> > compatible = "arm,cortex-a8";
> > reg = <0x0>;
> > - clocks = <&cpu>;
> > + clocks = <&ccu CLK_CPU>;
> > clock-latency = <244144>; /* 8 32k periods */
> > operating-points = <
> > /* kHz uV */
> > @@ -168,18 +171,6 @@
> > #size-cells = <1>;
> > ranges;
> >
> > - /*
> > - * This is a dummy clock, to be used as placeholder on
> > - * other mux clocks when a specific parent clock is not
> > - * yet implemented. It should be dropped when the driver
> > - * is complete.
> > - */
> > - dummy: dummy {
> > - #clock-cells = <0>;
> > - compatible = "fixed-clock";
> > - clock-frequency = <0>;
> > - };
> > -
> > osc24M: clk@01c20050 {
> > #clock-cells = <0>;
> > compatible = "allwinner,sun4i-a10-osc-clk";
> > @@ -188,487 +179,12 @@
> > clock-output-names = "osc24M";
> > };
> >
> > - osc3M: osc3M_clk {
> > - compatible = "fixed-factor-clock";
> > - #clock-cells = <0>;
> > - clock-div = <8>;
> > - clock-mult = <1>;
> > - clocks = <&osc24M>;
> > - clock-output-names = "osc3M";
> > - };
> > -
> > osc32k: clk@0 {
> > #clock-cells = <0>;
> > compatible = "fixed-clock";
> > clock-frequency = <32768>;
> > clock-output-names = "osc32k";
> > };
> > -
> > - pll1: clk@01c20000 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-pll1-clk";
> > - reg = <0x01c20000 0x4>;
> > - clocks = <&osc24M>;
> > - clock-output-names = "pll1";
> > - };
> > -
> > - pll2: clk@01c20008 {
> > - #clock-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-pll2-clk";
> > - reg = <0x01c20008 0x8>;
> > - clocks = <&osc24M>;
> > - clock-output-names = "pll2-1x", "pll2-2x",
> > - "pll2-4x", "pll2-8x";
> > - };
> > -
> > - pll3: clk@01c20010 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-pll3-clk";
> > - reg = <0x01c20010 0x4>;
> > - clocks = <&osc3M>;
> > - clock-output-names = "pll3";
> > - };
> > -
> > - pll3x2: pll3x2_clk {
> > - compatible = "fixed-factor-clock";
> > - #clock-cells = <0>;
> > - clock-div = <1>;
> > - clock-mult = <2>;
> > - clocks = <&pll3>;
> > - clock-output-names = "pll3-2x";
> > - };
> > -
> > - pll4: clk@01c20018 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-pll1-clk";
> > - reg = <0x01c20018 0x4>;
> > - clocks = <&osc24M>;
> > - clock-output-names = "pll4";
> > - };
> > -
> > - pll5: clk@01c20020 {
> > - #clock-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-pll5-clk";
> > - reg = <0x01c20020 0x4>;
> > - clocks = <&osc24M>;
> > - clock-output-names = "pll5_ddr", "pll5_other";
> > - };
> > -
> > - pll6: clk@01c20028 {
> > - #clock-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-pll6-clk";
> > - reg = <0x01c20028 0x4>;
> > - clocks = <&osc24M>;
> > - clock-output-names = "pll6_sata", "pll6_other", "pll6";
> > - };
> > -
> > - pll7: clk@01c20030 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-pll3-clk";
> > - reg = <0x01c20030 0x4>;
> > - clocks = <&osc3M>;
> > - clock-output-names = "pll7";
> > - };
> > -
> > - pll7x2: pll7x2_clk {
> > - compatible = "fixed-factor-clock";
> > - #clock-cells = <0>;
> > - clock-div = <1>;
> > - clock-mult = <2>;
> > - clocks = <&pll7>;
> > - clock-output-names = "pll7-2x";
> > - };
> > -
> > - /* dummy is 200M */
> > - cpu: cpu@01c20054 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-cpu-clk";
> > - reg = <0x01c20054 0x4>;
> > - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
> > - clock-output-names = "cpu";
> > - };
> > -
> > - axi: axi@01c20054 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-axi-clk";
> > - reg = <0x01c20054 0x4>;
> > - clocks = <&cpu>;
> > - clock-output-names = "axi";
> > - };
> > -
> > - axi_gates: clk@01c2005c {
> > - #clock-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-axi-gates-clk";
> > - reg = <0x01c2005c 0x4>;
> > - clocks = <&axi>;
> > - clock-indices = <0>;
> > - clock-output-names = "axi_dram";
> > - };
> > -
> > - ahb: ahb@01c20054 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-ahb-clk";
> > - reg = <0x01c20054 0x4>;
> > - clocks = <&axi>;
> > - clock-output-names = "ahb";
> > - };
> > -
> > - ahb_gates: clk@01c20060 {
> > - #clock-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-ahb-gates-clk";
> > - reg = <0x01c20060 0x8>;
> > - clocks = <&ahb>;
> > - clock-indices = <0>, <1>,
> > - <2>, <3>,
> > - <4>, <5>, <6>,
> > - <7>, <8>, <9>,
> > - <10>, <11>, <12>,
> > - <13>, <14>, <16>,
> > - <17>, <18>, <20>,
> > - <21>, <22>, <23>,
> > - <24>, <25>, <26>,
> > - <32>, <33>, <34>,
> > - <35>, <36>, <37>,
> > - <40>, <41>, <43>,
> > - <44>, <45>,
> > - <46>, <47>,
> > - <50>, <52>;
> > - clock-output-names = "ahb_usb0", "ahb_ehci0",
> > - "ahb_ohci0", "ahb_ehci1",
> > - "ahb_ohci1", "ahb_ss", "ahb_dma",
> > - "ahb_bist", "ahb_mmc0", "ahb_mmc1",
> > - "ahb_mmc2", "ahb_mmc3", "ahb_ms",
> > - "ahb_nand", "ahb_sdram", "ahb_ace",
> > - "ahb_emac", "ahb_ts", "ahb_spi0",
> > - "ahb_spi1", "ahb_spi2", "ahb_spi3",
> > - "ahb_pata", "ahb_sata", "ahb_gps",
> > - "ahb_ve", "ahb_tvd", "ahb_tve0",
> > - "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
> > - "ahb_csi0", "ahb_csi1", "ahb_hdmi",
> > - "ahb_de_be0", "ahb_de_be1",
> > - "ahb_de_fe0", "ahb_de_fe1",
> > - "ahb_mp", "ahb_mali400";
> > - };
> > -
> > - apb0: apb0@01c20054 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-apb0-clk";
> > - reg = <0x01c20054 0x4>;
> > - clocks = <&ahb>;
> > - clock-output-names = "apb0";
> > - };
> > -
> > - apb0_gates: clk@01c20068 {
> > - #clock-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-apb0-gates-clk";
> > - reg = <0x01c20068 0x4>;
> > - clocks = <&apb0>;
> > - clock-indices = <0>, <1>,
> > - <2>, <3>,
> > - <5>, <6>,
> > - <7>, <10>;
> > - clock-output-names = "apb0_codec", "apb0_spdif",
> > - "apb0_ac97", "apb0_iis",
> > - "apb0_pio", "apb0_ir0",
> > - "apb0_ir1", "apb0_keypad";
> > - };
> > -
> > - apb1: clk@01c20058 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-apb1-clk";
> > - reg = <0x01c20058 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
> > - clock-output-names = "apb1";
> > - };
> > -
> > - apb1_gates: clk@01c2006c {
> > - #clock-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-apb1-gates-clk";
> > - reg = <0x01c2006c 0x4>;
> > - clocks = <&apb1>;
> > - clock-indices = <0>, <1>,
> > - <2>, <4>,
> > - <5>, <6>,
> > - <7>, <16>,
> > - <17>, <18>,
> > - <19>, <20>,
> > - <21>, <22>,
> > - <23>;
> > - clock-output-names = "apb1_i2c0", "apb1_i2c1",
> > - "apb1_i2c2", "apb1_can",
> > - "apb1_scr", "apb1_ps20",
> > - "apb1_ps21", "apb1_uart0",
> > - "apb1_uart1", "apb1_uart2",
> > - "apb1_uart3", "apb1_uart4",
> > - "apb1_uart5", "apb1_uart6",
> > - "apb1_uart7";
> > - };
> > -
> > - nand_clk: clk@01c20080 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-mod0-clk";
> > - reg = <0x01c20080 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "nand";
> > - };
> > -
> > - ms_clk: clk@01c20084 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-mod0-clk";
> > - reg = <0x01c20084 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "ms";
> > - };
> > -
> > - mmc0_clk: clk@01c20088 {
> > - #clock-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-mmc-clk";
> > - reg = <0x01c20088 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "mmc0",
> > - "mmc0_output",
> > - "mmc0_sample";
> > - };
> > -
> > - mmc1_clk: clk@01c2008c {
> > - #clock-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-mmc-clk";
> > - reg = <0x01c2008c 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "mmc1",
> > - "mmc1_output",
> > - "mmc1_sample";
> > - };
> > -
> > - mmc2_clk: clk@01c20090 {
> > - #clock-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-mmc-clk";
> > - reg = <0x01c20090 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "mmc2",
> > - "mmc2_output",
> > - "mmc2_sample";
> > - };
> > -
> > - mmc3_clk: clk@01c20094 {
> > - #clock-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-mmc-clk";
> > - reg = <0x01c20094 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "mmc3",
> > - "mmc3_output",
> > - "mmc3_sample";
> > - };
> > -
> > - ts_clk: clk@01c20098 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-mod0-clk";
> > - reg = <0x01c20098 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "ts";
> > - };
> > -
> > - ss_clk: clk@01c2009c {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-mod0-clk";
> > - reg = <0x01c2009c 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "ss";
> > - };
> > -
> > - spi0_clk: clk@01c200a0 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-mod0-clk";
> > - reg = <0x01c200a0 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "spi0";
> > - };
> > -
> > - spi1_clk: clk@01c200a4 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-mod0-clk";
> > - reg = <0x01c200a4 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "spi1";
> > - };
> > -
> > - spi2_clk: clk@01c200a8 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-mod0-clk";
> > - reg = <0x01c200a8 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "spi2";
> > - };
> > -
> > - pata_clk: clk@01c200ac {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-mod0-clk";
> > - reg = <0x01c200ac 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "pata";
> > - };
> > -
> > - ir0_clk: clk@01c200b0 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-mod0-clk";
> > - reg = <0x01c200b0 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "ir0";
> > - };
> > -
> > - ir1_clk: clk@01c200b4 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-mod0-clk";
> > - reg = <0x01c200b4 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "ir1";
> > - };
> > -
> > - spdif_clk: clk@01c200c0 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-mod1-clk";
> > - reg = <0x01c200c0 0x4>;
> > - clocks = <&pll2 SUN4I_A10_PLL2_8X>,
> > - <&pll2 SUN4I_A10_PLL2_4X>,
> > - <&pll2 SUN4I_A10_PLL2_2X>,
> > - <&pll2 SUN4I_A10_PLL2_1X>;
> > - clock-output-names = "spdif";
> > - };
> > -
> > - usb_clk: clk@01c200cc {
> > - #clock-cells = <1>;
> > - #reset-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-usb-clk";
> > - reg = <0x01c200cc 0x4>;
> > - clocks = <&pll6 1>;
> > - clock-output-names = "usb_ohci0", "usb_ohci1",
> > - "usb_phy";
> > - };
> > -
> > - spi3_clk: clk@01c200d4 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-mod0-clk";
> > - reg = <0x01c200d4 0x4>;
> > - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> > - clock-output-names = "spi3";
> > - };
> > -
> > - dram_gates: clk@01c20100 {
> > - #clock-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-dram-gates-clk";
> > - reg = <0x01c20100 0x4>;
> > - clocks = <&pll5 0>;
> > - clock-indices = <0>,
> > - <1>, <2>,
> > - <3>,
> > - <4>,
> > - <5>, <6>,
> > - <15>,
> > - <24>, <25>,
> > - <26>, <27>,
> > - <28>, <29>;
> > - clock-output-names = "dram_ve",
> > - "dram_csi0", "dram_csi1",
> > - "dram_ts",
> > - "dram_tvd",
> > - "dram_tve0", "dram_tve1",
> > - "dram_output",
> > - "dram_de_fe1", "dram_de_fe0",
> > - "dram_de_be0", "dram_de_be1",
> > - "dram_de_mp", "dram_ace";
> > - };
> > -
> > - de_be0_clk: clk@01c20104 {
> > - #clock-cells = <0>;
> > - #reset-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-display-clk";
> > - reg = <0x01c20104 0x4>;
> > - clocks = <&pll3>, <&pll7>, <&pll5 1>;
> > - clock-output-names = "de-be0";
> > - };
> > -
> > - de_be1_clk: clk@01c20108 {
> > - #clock-cells = <0>;
> > - #reset-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-display-clk";
> > - reg = <0x01c20108 0x4>;
> > - clocks = <&pll3>, <&pll7>, <&pll5 1>;
> > - clock-output-names = "de-be1";
> > - };
> > -
> > - de_fe0_clk: clk@01c2010c {
> > - #clock-cells = <0>;
> > - #reset-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-display-clk";
> > - reg = <0x01c2010c 0x4>;
> > - clocks = <&pll3>, <&pll7>, <&pll5 1>;
> > - clock-output-names = "de-fe0";
> > - };
> > -
> > - de_fe1_clk: clk@01c20110 {
> > - #clock-cells = <0>;
> > - #reset-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-display-clk";
> > - reg = <0x01c20110 0x4>;
> > - clocks = <&pll3>, <&pll7>, <&pll5 1>;
> > - clock-output-names = "de-fe1";
> > - };
> > -
> > -
> > - tcon0_ch0_clk: clk@01c20118 {
> > - #clock-cells = <0>;
> > - #reset-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
> > - reg = <0x01c20118 0x4>;
> > - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
> > - clock-output-names = "tcon0-ch0-sclk";
> > -
> > - };
> > -
> > - tcon1_ch0_clk: clk@01c2011c {
> > - #clock-cells = <0>;
> > - #reset-cells = <1>;
> > - compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
> > - reg = <0x01c2011c 0x4>;
> > - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
> > - clock-output-names = "tcon1-ch0-sclk";
> > -
> > - };
> > -
> > - tcon0_ch1_clk: clk@01c2012c {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
> > - reg = <0x01c2012c 0x4>;
> > - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
> > - clock-output-names = "tcon0-ch1-sclk";
> > -
> > - };
> > -
> > - tcon1_ch1_clk: clk@01c20130 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
> > - reg = <0x01c20130 0x4>;
> > - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
> > - clock-output-names = "tcon1-ch1-sclk";
> > -
> > - };
> > -
> > - ve_clk: clk@01c2013c {
> > - #clock-cells = <0>;
> > - #reset-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-ve-clk";
> > - reg = <0x01c2013c 0x4>;
> > - clocks = <&pll4>;
> > - clock-output-names = "ve";
> > - };
> > -
> > - codec_clk: clk@01c20140 {
> > - #clock-cells = <0>;
> > - compatible = "allwinner,sun4i-a10-codec-clk";
> > - reg = <0x01c20140 0x4>;
> > - clocks = <&pll2 SUN4I_A10_PLL2_1X>;
> > - clock-output-names = "codec";
> > - };
> > };
> >
> > soc@01c00000 {
> > @@ -717,7 +233,7 @@
> > compatible = "allwinner,sun4i-a10-dma";
> > reg = <0x01c02000 0x1000>;
> > interrupts = <27>;
> > - clocks = <&ahb_gates 6>;
> > + clocks = <&ccu CLK_AHB_DMA>;
> > #dma-cells = <2>;
> > };
> >
> > @@ -725,7 +241,7 @@
> > compatible = "allwinner,sun4i-a10-nand";
> > reg = <0x01c03000 0x1000>;
> > interrupts = <37>;
> > - clocks = <&ahb_gates 13>, <&nand_clk>;
> > + clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
> > clock-names = "ahb", "mod";
> > dmas = <&dma SUN4I_DMA_DEDICATED 3>;
> > dma-names = "rxtx";
> > @@ -738,7 +254,7 @@
> > compatible = "allwinner,sun4i-a10-spi";
> > reg = <0x01c05000 0x1000>;
> > interrupts = <10>;
> > - clocks = <&ahb_gates 20>, <&spi0_clk>;
> > + clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
> > clock-names = "ahb", "mod";
> > dmas = <&dma SUN4I_DMA_DEDICATED 27>,
> > <&dma SUN4I_DMA_DEDICATED 26>;
> > @@ -752,7 +268,7 @@
> > compatible = "allwinner,sun4i-a10-spi";
> > reg = <0x01c06000 0x1000>;
> > interrupts = <11>;
> > - clocks = <&ahb_gates 21>, <&spi1_clk>;
> > + clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
> > clock-names = "ahb", "mod";
> > dmas = <&dma SUN4I_DMA_DEDICATED 9>,
> > <&dma SUN4I_DMA_DEDICATED 8>;
> > @@ -766,7 +282,7 @@
> > compatible = "allwinner,sun4i-a10-emac";
> > reg = <0x01c0b000 0x1000>;
> > interrupts = <55>;
> > - clocks = <&ahb_gates 17>;
> > + clocks = <&ccu CLK_AHB_EMAC>;
> > allwinner,sram = <&emac_sram 1>;
> > status = "disabled";
> > };
> > @@ -782,10 +298,10 @@
> > mmc0: mmc@01c0f000 {
> > compatible = "allwinner,sun4i-a10-mmc";
> > reg = <0x01c0f000 0x1000>;
> > - clocks = <&ahb_gates 8>,
> > - <&mmc0_clk 0>,
> > - <&mmc0_clk 1>,
> > - <&mmc0_clk 2>;
> > + clocks = <&ccu CLK_AHB_MMC0>,
> > + <&ccu CLK_MMC0>,
> > + <&ccu CLK_MMC0_OUTPUT>,
> > + <&ccu CLK_MMC0_SAMPLE>;
> > clock-names = "ahb",
> > "mmc",
> > "output",
> > @@ -799,10 +315,10 @@
> > mmc1: mmc@01c10000 {
> > compatible = "allwinner,sun4i-a10-mmc";
> > reg = <0x01c10000 0x1000>;
> > - clocks = <&ahb_gates 9>,
> > - <&mmc1_clk 0>,
> > - <&mmc1_clk 1>,
> > - <&mmc1_clk 2>;
> > + clocks = <&ccu CLK_AHB_MMC1>,
> > + <&ccu CLK_MMC1>,
> > + <&ccu CLK_MMC1_OUTPUT>,
> > + <&ccu CLK_MMC1_SAMPLE>;
> > clock-names = "ahb",
> > "mmc",
> > "output",
> > @@ -816,10 +332,10 @@
> > mmc2: mmc@01c11000 {
> > compatible = "allwinner,sun4i-a10-mmc";
> > reg = <0x01c11000 0x1000>;
> > - clocks = <&ahb_gates 10>,
> > - <&mmc2_clk 0>,
> > - <&mmc2_clk 1>,
> > - <&mmc2_clk 2>;
> > + clocks = <&ccu CLK_AHB_MMC2>,
> > + <&ccu CLK_MMC2>,
> > + <&ccu CLK_MMC2_OUTPUT>,
> > + <&ccu CLK_MMC2_SAMPLE>;
> > clock-names = "ahb",
> > "mmc",
> > "output",
> > @@ -833,10 +349,10 @@
> > mmc3: mmc@01c12000 {
> > compatible = "allwinner,sun4i-a10-mmc";
> > reg = <0x01c12000 0x1000>;
> > - clocks = <&ahb_gates 11>,
> > - <&mmc3_clk 0>,
> > - <&mmc3_clk 1>,
> > - <&mmc3_clk 2>;
> > + clocks = <&ccu CLK_AHB_MMC3>,
> > + <&ccu CLK_MMC3>,
> > + <&ccu CLK_MMC3_OUTPUT>,
> > + <&ccu CLK_MMC3_SAMPLE>;
> > clock-names = "ahb",
> > "mmc",
> > "output",
> > @@ -850,7 +366,7 @@
> > usb_otg: usb@01c13000 {
> > compatible = "allwinner,sun4i-a10-musb";
> > reg = <0x01c13000 0x0400>;
> > - clocks = <&ahb_gates 0>;
> > + clocks = <&ccu CLK_AHB_OTG>;
> > interrupts = <38>;
> > interrupt-names = "mc";
> > phys = <&usbphy 0>;
> > @@ -865,9 +381,11 @@
> > compatible = "allwinner,sun4i-a10-usb-phy";
> > reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
> > reg-names = "phy_ctrl", "pmu1", "pmu2";
> > - clocks = <&usb_clk 8>;
> > + clocks = <&ccu CLK_USB_PHY>;
> > clock-names = "usb_phy";
> > - resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
> > + resets = <&ccu RST_USB_PHY0>,
> > + <&ccu RST_USB_PHY1>,
> > + <&ccu RST_USB_PHY2>;
> > reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
> > status = "disabled";
> > };
> > @@ -876,7 +394,7 @@
> > compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
> > reg = <0x01c14000 0x100>;
> > interrupts = <39>;
> > - clocks = <&ahb_gates 1>;
> > + clocks = <&ccu CLK_AHB_EHCI0>;
> > phys = <&usbphy 1>;
> > phy-names = "usb";
> > status = "disabled";
> > @@ -886,7 +404,7 @@
> > compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
> > reg = <0x01c14400 0x100>;
> > interrupts = <64>;
> > - clocks = <&usb_clk 6>, <&ahb_gates 2>;
> > + clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
> > phys = <&usbphy 1>;
> > phy-names = "usb";
> > status = "disabled";
> > @@ -896,7 +414,7 @@
> > compatible = "allwinner,sun4i-a10-crypto";
> > reg = <0x01c15000 0x1000>;
> > interrupts = <86>;
> > - clocks = <&ahb_gates 5>, <&ss_clk>;
> > + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
> > clock-names = "ahb", "mod";
> > };
> >
> > @@ -904,7 +422,7 @@
> > compatible = "allwinner,sun4i-a10-spi";
> > reg = <0x01c17000 0x1000>;
> > interrupts = <12>;
> > - clocks = <&ahb_gates 22>, <&spi2_clk>;
> > + clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
> > clock-names = "ahb", "mod";
> > dmas = <&dma SUN4I_DMA_DEDICATED 29>,
> > <&dma SUN4I_DMA_DEDICATED 28>;
> > @@ -918,7 +436,8 @@
> > compatible = "allwinner,sun4i-a10-ahci";
> > reg = <0x01c18000 0x1000>;
> > interrupts = <56>;
> > - clocks = <&pll6 0>, <&ahb_gates 25>;
> > + clocks = <&ccu CLK_PLL_PERIPH_SATA>,
> > + <&ccu CLK_AHB_SATA>;
> > status = "disabled";
> > };
> >
> > @@ -926,7 +445,7 @@
> > compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
> > reg = <0x01c1c000 0x100>;
> > interrupts = <40>;
> > - clocks = <&ahb_gates 3>;
> > + clocks = <&ccu CLK_AHB_EHCI1>;
> > phys = <&usbphy 2>;
> > phy-names = "usb";
> > status = "disabled";
> > @@ -936,7 +455,7 @@
> > compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
> > reg = <0x01c1c400 0x100>;
> > interrupts = <65>;
> > - clocks = <&usb_clk 7>, <&ahb_gates 4>;
> > + clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
> > phys = <&usbphy 2>;
> > phy-names = "usb";
> > status = "disabled";
> > @@ -946,7 +465,7 @@
> > compatible = "allwinner,sun4i-a10-spi";
> > reg = <0x01c1f000 0x1000>;
> > interrupts = <50>;
> > - clocks = <&ahb_gates 23>, <&spi3_clk>;
> > + clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
> > clock-names = "ahb", "mod";
> > dmas = <&dma SUN4I_DMA_DEDICATED 31>,
> > <&dma SUN4I_DMA_DEDICATED 30>;
> > @@ -956,6 +475,15 @@
> > #size-cells = <0>;
> > };
> >
> > + ccu: clock@01c20000 {
> > + compatible = "allwinner,sun4i-a10-ccu";
> > + reg = <0x01c20000 0x400>;
> > + clocks = <&osc24M>, <&osc32k>;
> > + clock-names = "hosc", "losc";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > intc: interrupt-controller@01c20400 {
> > compatible = "allwinner,sun4i-a10-ic";
> > reg = <0x01c20400 0x400>;
> > @@ -967,7 +495,7 @@
> > compatible = "allwinner,sun4i-a10-pinctrl";
> > reg = <0x01c20800 0x400>;
> > interrupts = <28>;
> > - clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
> > + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
> > clock-names = "apb", "hosc", "losc";
> > gpio-controller;
> > interrupt-controller;
> > @@ -1145,7 +673,7 @@
> > compatible = "allwinner,sun4i-a10-spdif";
> > reg = <0x01c21000 0x400>;
> > interrupts = <13>;
> > - clocks = <&apb0_gates 1>, <&spdif_clk>;
> > + clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
> > clock-names = "apb", "spdif";
> > dmas = <&dma SUN4I_DMA_NORMAL 2>,
> > <&dma SUN4I_DMA_NORMAL 2>;
> > @@ -1155,7 +683,7 @@
> >
> > ir0: ir@01c21800 {
> > compatible = "allwinner,sun4i-a10-ir";
> > - clocks = <&apb0_gates 6>, <&ir0_clk>;
> > + clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
> > clock-names = "apb", "ir";
> > interrupts = <5>;
> > reg = <0x01c21800 0x40>;
> > @@ -1164,7 +692,7 @@
> >
> > ir1: ir@01c21c00 {
> > compatible = "allwinner,sun4i-a10-ir";
> > - clocks = <&apb0_gates 7>, <&ir1_clk>;
> > + clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
> > clock-names = "apb", "ir";
> > interrupts = <6>;
> > reg = <0x01c21c00 0x40>;
> > @@ -1183,7 +711,7 @@
> > compatible = "allwinner,sun4i-a10-codec";
> > reg = <0x01c22c00 0x40>;
> > interrupts = <30>;
> > - clocks = <&apb0_gates 0>, <&codec_clk>;
> > + clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
> > clock-names = "apb", "codec";
> > dmas = <&dma SUN4I_DMA_NORMAL 19>,
> > <&dma SUN4I_DMA_NORMAL 19>;
> > @@ -1209,7 +737,7 @@
> > interrupts = <1>;
> > reg-shift = <2>;
> > reg-io-width = <4>;
> > - clocks = <&apb1_gates 16>;
> > + clocks = <&ccu CLK_APB1_UART0>;
> > status = "disabled";
> > };
> >
> > @@ -1219,7 +747,7 @@
> > interrupts = <2>;
> > reg-shift = <2>;
> > reg-io-width = <4>;
> > - clocks = <&apb1_gates 17>;
> > + clocks = <&ccu CLK_APB1_UART1>;
> > status = "disabled";
> > };
> >
> > @@ -1229,7 +757,7 @@
> > interrupts = <3>;
> > reg-shift = <2>;
> > reg-io-width = <4>;
> > - clocks = <&apb1_gates 18>;
> > + clocks = <&ccu CLK_APB1_UART2>;
> > status = "disabled";
> > };
> >
> > @@ -1239,7 +767,7 @@
> > interrupts = <4>;
> > reg-shift = <2>;
> > reg-io-width = <4>;
> > - clocks = <&apb1_gates 19>;
> > + clocks = <&ccu CLK_APB1_UART3>;
> > status = "disabled";
> > };
> >
> > @@ -1249,7 +777,7 @@
> > interrupts = <17>;
> > reg-shift = <2>;
> > reg-io-width = <4>;
> > - clocks = <&apb1_gates 20>;
> > + clocks = <&ccu CLK_APB1_UART4>;
> > status = "disabled";
> > };
> >
> > @@ -1259,7 +787,7 @@
> > interrupts = <18>;
> > reg-shift = <2>;
> > reg-io-width = <4>;
> > - clocks = <&apb1_gates 21>;
> > + clocks = <&ccu CLK_APB1_UART5>;
> > status = "disabled";
> > };
> >
> > @@ -1269,7 +797,7 @@
> > interrupts = <19>;
> > reg-shift = <2>;
> > reg-io-width = <4>;
> > - clocks = <&apb1_gates 22>;
> > + clocks = <&ccu CLK_APB1_UART6>;
> > status = "disabled";
> > };
> >
> > @@ -1279,7 +807,7 @@
> > interrupts = <20>;
> > reg-shift = <2>;
> > reg-io-width = <4>;
> > - clocks = <&apb1_gates 23>;
> > + clocks = <&ccu CLK_APB1_UART7>;
> > status = "disabled";
> > };
> >
> > @@ -1287,7 +815,7 @@
> > compatible = "allwinner,sun4i-a10-i2c";
> > reg = <0x01c2ac00 0x400>;
> > interrupts = <7>;
> > - clocks = <&apb1_gates 0>;
> > + clocks = <&ccu CLK_APB1_I2C0>;
> > status = "disabled";
> > #address-cells = <1>;
> > #size-cells = <0>;
> > @@ -1297,7 +825,7 @@
> > compatible = "allwinner,sun4i-a10-i2c";
> > reg = <0x01c2b000 0x400>;
> > interrupts = <8>;
> > - clocks = <&apb1_gates 1>;
> > + clocks = <&ccu CLK_APB1_I2C1>;
> > status = "disabled";
> > #address-cells = <1>;
> > #size-cells = <0>;
> > @@ -1307,7 +835,7 @@
> > compatible = "allwinner,sun4i-a10-i2c";
> > reg = <0x01c2b400 0x400>;
> > interrupts = <9>;
> > - clocks = <&apb1_gates 2>;
> > + clocks = <&ccu CLK_APB1_I2C2>;
> > status = "disabled";
> > #address-cells = <1>;
> > #size-cells = <0>;
> > @@ -1317,7 +845,7 @@
> > compatible = "allwinner,sun4i-a10-ps2";
> > reg = <0x01c2a000 0x400>;
> > interrupts = <62>;
> > - clocks = <&apb1_gates 6>;
> > + clocks = <&ccu CLK_APB1_PS20>;
> > status = "disabled";
> > };
> >
> > @@ -1325,7 +853,7 @@
> > compatible = "allwinner,sun4i-a10-ps2";
> > reg = <0x01c2a400 0x400>;
> > interrupts = <63>;
> > - clocks = <&apb1_gates 7>;
> > + clocks = <&ccu CLK_APB1_PS21>;
> > status = "disabled";
> > };
> > };
> > --
> > git-series 0.9.1
> >
> > --
> > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
> > For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply
* Re: [PATCHv2 1/3] dt-bindings: net: Add DT bindings for Socionext Netsec
From: Mark Rutland @ 2017-12-12 17:29 UTC (permalink / raw)
To: jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w
Cc: netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA,
davem-fT/PcQaiUtIeIZ0/mPfg9Q,
arnd.bergmann-QSEj5FYQhm4dnm+yROfE0A,
ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Jassi Brar
In-Reply-To: <1513098921-21042-1-git-send-email-jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi,
On Tue, Dec 12, 2017 at 10:45:21PM +0530, jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:
> From: Jassi Brar <jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> This patch adds documentation for Device-Tree bindings for the
> Socionext NetSec Controller driver.
>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> .../devicetree/bindings/net/socionext-netsec.txt | 43 ++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/socionext-netsec.txt
>
> diff --git a/Documentation/devicetree/bindings/net/socionext-netsec.txt b/Documentation/devicetree/bindings/net/socionext-netsec.txt
> new file mode 100644
> index 0000000..4695969
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/socionext-netsec.txt
> @@ -0,0 +1,45 @@
> +* Socionext NetSec Ethernet Controller IP
> +
> +Required properties:
> +- compatible: Should be "socionext,synquacer-netsec"
> +- reg: Address and length of the control register area, followed by the
> + address and length of the EEPROM holding the MAC address and
> + microengine firmware
> +- interrupts: Should contain ethernet controller interrupt
> +- clocks: phandle to the PHY reference clock, and any other clocks to be
> + switched by runtime_pm
> +- clock-names: Required only if more than a single clock is listed in 'clocks'.
> + The PHY reference clock must be named 'phy_refclk'
Please define the full set of clocks (and their names) explicitly. This
should be well-known.
Otherwise, this looks ok.
Thanks,
Mark.
> +- phy-mode: See ethernet.txt file in the same directory
> +- phy-handle: phandle to select child phy
> +
> +Optional properties: (See ethernet.txt file in the same directory)
> +- dma-coherent: Boolean property, must only be present if memory
> + accesses performed by the device are cache coherent
> +- local-mac-address
> +- mac-address
> +- max-speed
> +- max-frame-size
> +
> +Required properties for the child phy:
> +- reg: phy address
> +
> +Example:
> + eth0: netsec@522D0000 {
> + compatible = "socionext,synquacer-netsec";
> + reg = <0 0x522D0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>;
> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_netsec>;
> + phy-mode = "rgmii";
> + max-speed = <1000>;
> + max-frame-size = <9000>;
> + phy-handle = <ðphy0>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> + };
> --
> 2.7.4
>
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^ permalink raw reply
* Re: [PATCH] of_mdio / mdiobus: ensure mdio devices have fwnode correctly populated
From: Rob Herring @ 2017-12-12 17:29 UTC (permalink / raw)
To: Russell King
Cc: Andrew Lunn, Florian Fainelli, Frank Rowand, netdev,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <E1eOi7f-0002Rs-K7-eh5Bv4kxaXIk46pC+1QYvQNdhmdF6hFW@public.gmane.org>
On Tue, Dec 12, 2017 at 4:49 AM, Russell King
<rmk+kernel-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> wrote:
> Ensure that all mdio devices populate the struct device fwnode pointer
> as well as the of_node pointer to allow drivers that wish to use
> fwnode APIs to work.
>
> Signed-off-by: Russell King <rmk+kernel-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>
> ---
> drivers/net/phy/mdio_bus.c | 1 +
> drivers/of/of_mdio.c | 3 +++
> 2 files changed, 4 insertions(+)
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v3 31/33] dt-bindings: interrupt-controller: Andestech Internal Vector Interrupt Controller
From: Rob Herring @ 2017-12-12 17:33 UTC (permalink / raw)
To: Greentime Hu
Cc: greentime-MUIXKm3Oiri1Z/+hSey0Gg,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
linux-arch-u79uwXL29TY76Z2rM5mHXA, tglx-hfZtesqFncYOwBW4kG4KsQ,
jason-NLaQJdtUoK4Be96aLqz0jA, marc.zyngier-5wv7dgnIgG8,
netdev-u79uwXL29TY76Z2rM5mHXA, deanbo422-Re5JQEeQqe8AvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
viro-RmSDqhL/yNMiFSDQTTA3OLVCufUGDwFn,
dhowells-H+wXaHxf7aLQT0dZR+AlfA, will.deacon-5wv7dgnIgG8,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
linux-serial-u79uwXL29TY76Z2rM5mHXA,
geert.uytterhoeven-Re5JQEeQqe8AvxtiuMwx3w,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
greg-U8xfFu+wG4EAvxtiuMwx3w, Rick Chen
In-Reply-To: <a0bb0a384a74bc180c0d4e9aa5741bb52653211b.1512723245.git.green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Fri, Dec 08, 2017 at 05:12:14PM +0800, Greentime Hu wrote:
> From: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
>
> This patch adds an irqchip driver document for the Andestech Internal Vector
> Interrupt Controller.
>
> Signed-off-by: Rick Chen <rick-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
> Signed-off-by: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
> ---
> .../interrupt-controller/andestech,ativic32.txt | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
I acked v2. Please add acks when posting new versions.
Rob
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^ permalink raw reply
* Re: [PATCH V4 2/7] PCI: tegra: Use bus->sysdata to store and get host private data
From: Bjorn Helgaas @ 2017-12-12 17:34 UTC (permalink / raw)
To: Manikanta Maddireddy
Cc: cyndis-/1wQRMveznE, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, lorenzo.pieralisi-5wv7dgnIgG8,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, rjw-LthD3rsA81gm4RdzfppkhA,
tglx-hfZtesqFncYOwBW4kG4KsQ, vidyas-DDmLM1+adcrQT0dZR+AlfA,
kthota-DDmLM1+adcrQT0dZR+AlfA, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512723493-865-3-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Fri, Dec 08, 2017 at 02:28:08PM +0530, Manikanta Maddireddy wrote:
> Tegra host driver is using pci_find_host_bridge() to get private data,
> however pci_find_host_bridge() is causing module build failure because
> it is not exported. pci_find_host_bridge() can be avoided by using
> bus->sysdata to store and get private data.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Thanks a lot for doing this! Looks like it was even easier than I
expected :)
> ---
> V4:
> * new patch in V4
>
> drivers/pci/host/pci-tegra.c | 13 +++++--------
> 1 file changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 6f2f44539020..a549c5899e26 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -448,8 +448,7 @@ static unsigned long tegra_pcie_conf_offset(unsigned char b, unsigned int devfn,
>
> static int tegra_pcie_add_bus(struct pci_bus *bus)
> {
> - struct pci_host_bridge *host = pci_find_host_bridge(bus);
> - struct tegra_pcie *pcie = pci_host_bridge_priv(host);
> + struct tegra_pcie *pcie = bus->sysdata;
> struct tegra_pcie_bus *b;
>
> b = kzalloc(sizeof(*b), GFP_KERNEL);
> @@ -466,8 +465,7 @@ static int tegra_pcie_add_bus(struct pci_bus *bus)
>
> static void tegra_pcie_remove_bus(struct pci_bus *child)
> {
> - struct pci_host_bridge *host = pci_find_host_bridge(child);
> - struct tegra_pcie *pcie = pci_host_bridge_priv(host);
> + struct tegra_pcie *pcie = child->sysdata;
> struct tegra_pcie_bus *bus, *tmp;
>
> list_for_each_entry_safe(bus, tmp, &pcie->buses, list) {
> @@ -483,8 +481,7 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
> unsigned int devfn,
> int where)
> {
> - struct pci_host_bridge *host = pci_find_host_bridge(bus);
> - struct tegra_pcie *pcie = pci_host_bridge_priv(host);
> + struct tegra_pcie *pcie = bus->sysdata;
> void __iomem *addr = NULL;
> u32 val = 0;
> u32 offset = 0;
> @@ -675,8 +672,7 @@ static int tegra_pcie_request_resources(struct tegra_pcie *pcie)
>
> static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
> {
> - struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus);
> - struct tegra_pcie *pcie = pci_host_bridge_priv(host);
> + struct tegra_pcie *pcie = pdev->bus->sysdata;
> int irq;
>
> tegra_cpuidle_pcie_irqs_in_use();
> @@ -2570,6 +2566,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
> return -ENOMEM;
>
> pcie = pci_host_bridge_priv(host);
> + host->sysdata = pcie;
>
> pcie->soc = of_device_get_match_data(dev);
> INIT_LIST_HEAD(&pcie->buses);
> --
> 2.1.4
>
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^ permalink raw reply
* Re: [PATCH v4] ARM: dts: exynos: Add nodes for True Random Number Generator
From: Krzysztof Kozlowski @ 2017-12-12 17:44 UTC (permalink / raw)
To: Łukasz Stelmach
Cc: Andrew F . Davis, PrasannaKumar Muralidharan, Rob Herring,
Matt Mackall, Herbert Xu, Kukjin Kim, devicetree, linux-crypto,
linux-samsung-soc, linux-kernel, Marek Szyprowski,
Bartlomiej Zolnierkiewicz
In-Reply-To: <20171212120902.16561-1-l.stelmach@samsung.com>
On Tue, Dec 12, 2017 at 01:09:02PM +0100, Łukasz Stelmach wrote:
> Add nodes for the True Random Number Generator found in Samsung Exynos
> 5250+ SoCs.
>
> Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
> ---
> Changes since v3:
>
> - Rebased accroding to Krzysztof Kozłowski's request
>
> arch/arm/boot/dts/exynos5.dtsi | 5 +++++
> arch/arm/boot/dts/exynos5250.dtsi | 5 +++++
> arch/arm/boot/dts/exynos5410.dtsi | 5 +++++
> arch/arm/boot/dts/exynos5420.dtsi | 5 +++++
> 4 files changed, 20 insertions(+)
>
Thanks, applied.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4 3/3] dt-bindings: iio: temperature: add MLX90632 device bindings
From: Andreas Färber @ 2017-12-12 17:45 UTC (permalink / raw)
To: Crt Mori, Rob Herring
Cc: Jonathan Cameron, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171211092002.8687-1-cmo-fc6wVz46lShBDgjK7y7TUQ@public.gmane.org>
Am 11.12.2017 um 10:20 schrieb Crt Mori:
> Add device tree bindings for MLX90632 IR temperature sensor.
>
> Signed-off-by: Crt Mori <cmo-fc6wVz46lShBDgjK7y7TUQ@public.gmane.org>
> Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
> .../bindings/iio/temperature/mlx90632.txt | 28 ++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/temperature/mlx90632.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt b/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt
> new file mode 100644
> index 000000000000..0b05812001f8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt
[...]
> +Example:
> +
> +mlx90632@3a {
Shouldn't the node name be more general like temperature@3a?
> + compatible = "melexis,mlx90632";
> + reg = <0x3a>;
> +};
Also generally the dt-bindings patch should go before the first use of
the compatible string.
Regards,
Andreas
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SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
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HRB 21284 (AG Nürnberg)
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^ permalink raw reply
* Re: [PATCH 1/2] cpufreq: ARM: sort the Kconfig menu
From: Randy Dunlap @ 2017-12-12 17:45 UTC (permalink / raw)
To: Gregory CLEMENT, Rafael J. Wysocki, Viresh Kumar, linux-pm
Cc: Thomas Petazzoni, Andrew Lunn, Jason Cooper, devicetree,
Antoine Tenart, Andre Heider, Evan Wang, Nadav Haklai,
Rob Herring, Neta Zur Hershkovits, Miquèl Raynal, Victor Gu,
Hua Jing, Marcin Wojtas, Wilson Ding, linux-arm-kernel,
Sebastian Hesselbarth
In-Reply-To: <20171212165419.752-2-gregory.clement@free-electrons.com>
On 12/12/2017 08:54 AM, Gregory CLEMENT wrote:
> Group all the related big LITTLE configuration together and sort the
> other entries in alphabetic order.
>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
> drivers/cpufreq/Kconfig.arm | 82 ++++++++++++++++++++++-----------------------
> 1 file changed, 41 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index bdce4488ded1..0baf43837b51 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -2,6 +2,23 @@
> # ARM CPU Frequency scaling drivers
> #
>
> +config ACPI_CPPC_CPUFREQ
> + tristate "CPUFreq driver based on the ACPI CPPC spec"
> + depends on ACPI_PROCESSOR
> + select ACPI_CPPC_LIB
> + default n
Drop "default n" since that is the default default.
> + help
> + This adds a CPUFreq driver which uses CPPC methods
> + as described in the ACPIv5.1 spec. CPPC stands for
> + Collaborative Processor Performance Controls. It
> + is based on an abstract continuous scale of CPU
> + performance values which allows the remote power
> + processor to flexibly optimize for power and
> + performance. CPPC relies on power management firmware
> + support for its operation.
> +
> + If in doubt, say N.
> +
> # big LITTLE core layer and glue drivers
> config ARM_BIG_LITTLE_CPUFREQ
> tristate "Generic ARM big LITTLE CPUfreq driver"
> @@ -12,6 +29,30 @@ config ARM_BIG_LITTLE_CPUFREQ
> help
> This enables the Generic CPUfreq driver for ARM big.LITTLE platforms.
>
> +config ARM_DT_BL_CPUFREQ
> + tristate "Generic probing via DT for ARM big LITTLE CPUfreq driver"
> + depends on ARM_BIG_LITTLE_CPUFREQ && OF
> + help
> + This enables probing via DT for Generic CPUfreq driver for ARM
> + big.LITTLE platform. This gets frequency tables from DT.
> +
> +config ARM_SCPI_CPUFREQ
> + tristate "SCPI based CPUfreq driver"
> + depends on ARM_BIG_LITTLE_CPUFREQ && ARM_SCPI_PROTOCOL && COMMON_CLK_SCPI
> + help
Fix the help and tristate lines -- use tab instead of spaces.
> + This adds the CPUfreq driver support for ARM big.LITTLE platforms
> + using SCPI protocol for CPU power management.
> +
> + This driver uses SCPI Message Protocol driver to interact with the
> + firmware providing the CPU DVFS functionality.
> +
> +config ARM_VEXPRESS_SPC_CPUFREQ
> + tristate "Versatile Express SPC based CPUfreq driver"
> + depends on ARM_BIG_LITTLE_CPUFREQ && ARCH_VEXPRESS_SPC
> + help
Use tab instead of spaces above. Oh, and one line below.
> + This add the CPUfreq driver support for Versatile Express
> + big.LITTLE platforms using SPC for power management.
> +
> config ARM_BRCMSTB_AVS_CPUFREQ
> tristate "Broadcom STB AVS CPUfreq driver"
> depends on ARCH_BRCMSTB || COMPILE_TEST
--
~Randy
^ permalink raw reply
* Re: [PATCH v2] ARM: dts: exynos: Enable Mixer node for Exynos5800 Peach Pi machine
From: Krzysztof Kozlowski @ 2017-12-12 17:47 UTC (permalink / raw)
To: Javier Martinez Canillas
Cc: linux-kernel, Marek Szyprowski, Guillaume Tucker, Daniel Vetter,
Shuah Khan, devicetree, Kukjin Kim, Russell King,
linux-samsung-soc, Rob Herring, Mark Rutland, linux-arm-kernel
In-Reply-To: <20171212074208.30753-1-javierm@redhat.com>
On Tue, Dec 12, 2017 at 08:42:08AM +0100, Javier Martinez Canillas wrote:
> Commit 1cb686c08d12 ("ARM: dts: exynos: Add status property to Exynos 542x
> Mixer nodes") disabled the Mixer node by default in the DTSI and enabled
> for each Exynos 542x DTS. But unfortunately it missed to enable it for the
> Exynos5800 Peach Pi machine, since the 5800 is also an 542x SoC variant.
>
> Fixes: 1cb686c08d12 ("ARM: dts: exynos: Add status property to Exynos 542x Mixer nodes")
> Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
> Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
>
> ---
>
> Changes in v2:
> - Remove RFT tag.
> - Add Marek's Acked-by tag.
> - Add fixes tag.
>
> arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
Thanks, applied for current cycle (fixes).
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 0/3] Enable DMA on STM32 MCU based on cortex-M7
From: Alexandre Torgue @ 2017-12-12 18:02 UTC (permalink / raw)
To: Maxime Coquelin, arnd-r2nGTMty4D4, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
patrice.chotard-qxv4g6HH51o, lee.jones-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
This series enable DMA on several STM32 MCU based on cortex-M7.
To make it possible, a dedicated dma pool memory area has to be
created. This patchset activate also ARM_MPU flag which will configure
MPU (Memory Protection Unit) according to devicetree information (mem
and dma-pool). Note that on cortex-M7 DMA has to use a NO cache-able
memory region.
Regards
Alex
Alexandre Torgue (3):
ARM: dts: stm32: add DMA memory pool on MCU which embed a cortex-M7
ARM: configs: stm32: Enable ARM_MPU
ARM: dts: stm32: enable dma on MCU which embed a cortex-M7
arch/arm/boot/dts/stm32746g-eval.dts | 21 +++++++++++++++++++++
arch/arm/boot/dts/stm32f769-disco.dts | 21 +++++++++++++++++++++
arch/arm/boot/dts/stm32h743i-disco.dts | 21 +++++++++++++++++++++
arch/arm/boot/dts/stm32h743i-eval.dts | 21 +++++++++++++++++++++
arch/arm/configs/stm32_defconfig | 1 +
5 files changed, 85 insertions(+)
--
2.7.4
--
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^ permalink raw reply
* [PATCH 1/3] ARM: dts: stm32: add DMA memory pool on MCU which embed a cortex-M7
From: Alexandre Torgue @ 2017-12-12 18:02 UTC (permalink / raw)
To: Maxime Coquelin, arnd-r2nGTMty4D4, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
patrice.chotard-qxv4g6HH51o, lee.jones-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1513101746-18030-1-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org>
On cortex-M7 MCU, DMA have to use a non cache-able memory area. For this
reason a dedicated memory pool is created for DMA.
This patch creates a DMA memory pool of 1MB of each STM32 MCU which
embeds a cortex-M7 expect stm32f746-disco. Indeed, as stm32f746-disco has
only a 8MB SDRAM and it's tricky to reduce memory used by Kernel.
Signed-off-by: Alexandre Torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts
index 2d4e717..3f52a7b 100644
--- a/arch/arm/boot/dts/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/stm32746g-eval.dts
@@ -57,6 +57,19 @@
reg = <0xc0000000 0x2000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,dma {
+ compatible = "shared-dma-pool";
+ linux,dma-default;
+ no-map;
+ reg = <0xc1f00000 0x100000>;
+ };
+ };
+
aliases {
serial0 = &usart1;
};
diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts
index 4463ca1..08699a2 100644
--- a/arch/arm/boot/dts/stm32f769-disco.dts
+++ b/arch/arm/boot/dts/stm32f769-disco.dts
@@ -57,6 +57,19 @@
reg = <0xC0000000 0x1000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,dma {
+ compatible = "shared-dma-pool";
+ linux,dma-default;
+ no-map;
+ reg = <0xc0f00000 0x100000>;
+ };
+ };
+
aliases {
serial0 = &usart1;
};
diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts
index 79e841d..104545a 100644
--- a/arch/arm/boot/dts/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/stm32h743i-disco.dts
@@ -57,6 +57,19 @@
reg = <0xd0000000 0x2000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,dma {
+ compatible = "shared-dma-pool";
+ linux,dma-default;
+ no-map;
+ reg = <0xc1f00000 0x100000>;
+ };
+ };
+
aliases {
serial0 = &usart2;
};
diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts
index 9f0e72c..5bd4b16 100644
--- a/arch/arm/boot/dts/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -57,6 +57,19 @@
reg = <0xd0000000 0x2000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,dma {
+ compatible = "shared-dma-pool";
+ linux,dma-default;
+ no-map;
+ reg = <0xc1f00000 0x100000>;
+ };
+ };
+
aliases {
serial0 = &usart1;
};
--
2.7.4
--
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^ permalink raw reply related
* [PATCH 2/3] ARM: configs: stm32: Enable ARM_MPU
From: Alexandre Torgue @ 2017-12-12 18:02 UTC (permalink / raw)
To: Maxime Coquelin, arnd-r2nGTMty4D4, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
patrice.chotard-qxv4g6HH51o, lee.jones-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1513101746-18030-1-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org>
STM32 MCUs embed a Memory Protection Unit. Enabling this setting will
allow the Kernel to configure the MPU according to devicetree.
Signed-off-by: Alexandre Torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index bb358ff..e642bdf9 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -24,6 +24,7 @@ CONFIG_SET_MEM_PARAM=y
CONFIG_DRAM_BASE=0x90000000
CONFIG_FLASH_MEM_BASE=0x08000000
CONFIG_FLASH_SIZE=0x00200000
+CONFIG_ARM_MPU=y
CONFIG_PREEMPT=y
# CONFIG_ATAGS is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
--
2.7.4
--
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^ permalink raw reply related
* [PATCH 3/3] ARM: dts: stm32: enable dma on MCU which embed a cortex-M7
From: Alexandre Torgue @ 2017-12-12 18:02 UTC (permalink / raw)
To: Maxime Coquelin, arnd-r2nGTMty4D4, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
patrice.chotard-qxv4g6HH51o, lee.jones-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1513101746-18030-1-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org>
Enable dma1 and dma2 on:
-stm32746g-eval board
-stm32f769-disco board
-stm32h743i-disco board
-stm32h743i-eval board
Signed-off-by: Alexandre Torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts
index 3f52a7b..2662a27 100644
--- a/arch/arm/boot/dts/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/stm32746g-eval.dts
@@ -113,6 +113,14 @@
status = "okay";
};
+&dma1 {
+ status = "okay";
+};
+
+&dma2 {
+ status = "okay";
+};
+
&i2c1 {
pinctrl-0 = <&i2c1_pins_b>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts
index 08699a2..b9b1ffd 100644
--- a/arch/arm/boot/dts/stm32f769-disco.dts
+++ b/arch/arm/boot/dts/stm32f769-disco.dts
@@ -86,6 +86,14 @@
clock-frequency = <25000000>;
};
+&dma1 {
+ status = "okay";
+};
+
+&dma2 {
+ status = "okay";
+};
+
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts
index 104545a..2d9e553 100644
--- a/arch/arm/boot/dts/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/stm32h743i-disco.dts
@@ -79,6 +79,14 @@
clock-frequency = <125000000>;
};
+&dma1 {
+ status = "okay";
+};
+
+&dma2 {
+ status = "okay";
+};
+
&usart2 {
pinctrl-0 = <&usart2_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts
index 5bd4b16..3face6a 100644
--- a/arch/arm/boot/dts/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -97,6 +97,14 @@
clock-frequency = <25000000>;
};
+&dma1 {
+ status = "okay";
+};
+
+&dma2 {
+ status = "okay";
+};
+
&usart1 {
pinctrl-0 = <&usart1_pins>;
pinctrl-names = "default";
--
2.7.4
--
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^ permalink raw reply related
* Re: [PATCH] of: irq: Fix function description comment
From: Rob Herring @ 2017-12-12 18:03 UTC (permalink / raw)
To: Vasyl Gomonovych; +Cc: devicetree, frowand.list, linux-kernel
In-Reply-To: <1512600215-12580-1-git-send-email-gomonovych@gmail.com>
On Wed, Dec 06, 2017 at 11:43:34PM +0100, Vasyl Gomonovych wrote:
> Make small cleanup in function description for
> of_irq_parse_raw
>
> Signed-off-by: Vasyl Gomonovych <gomonovych@gmail.com>
> ---
> drivers/of/irq.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
Applied, thanks.
Rob
^ permalink raw reply
* Re: [PATCH v10 2/2] leds: lm3692x: Introduce LM3692x dual string driver
From: Dan Murphy @ 2017-12-12 18:03 UTC (permalink / raw)
To: robh+dt, mark.rutland, rpurdie, jacek.anaszewski, pavel
Cc: devicetree, linux-kernel, linux-leds
In-Reply-To: <20171212170040.16777-2-dmurphy@ti.com>
One minor change
On 12/12/2017 11:00 AM, Dan Murphy wrote:
> Introducing the LM3692x Dual-String white LED driver.
>
> Data sheet is located
> http://www.ti.com/lit/ds/snvsa29/snvsa29.pdf
>
> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> ---
>
> v10 - No changes - https://patchwork.kernel.org/patch/10105651/
>
> v9 - Change the no DT label case to pull the device name from the i2c_id struct
> so that the device name can be part of the sysfs node - https://patchwork.kernel.org/patch/10093759/
> v8 - No changes
> v7 - Reverted back to creating the LED label within the driver -
> https://patchwork.kernel.org/patch/10087473/
> v6 - Use new LED API to compose LED label as opposed to creating it. -
> https://patchwork.kernel.org/patch/10085565/
> v5 - Added OF dependency in Kconfig, added extra fault flag read to ensure that
> if a fault exists and it is not a artifact, fixed LED class label to be derived
> from either the DT child "label" node or create a label based on
> parent_node_name:led color:trigger, removed ifdef for CONFIG_OF and removed
> of_match_ptr - https://patchwork.kernel.org/patch/10081073/
> v4 - Converted to devm led class register, changed MODULE_LICENSE to GPL v2,
> set the led name based on child node name or label entry, removed fault and
> returned read_buf for fault checking, added mutex_destroy to remove function,
> and removed LED_FULL - https://patchwork.kernel.org/patch/10060109/
> v3 - Add missing Makefile and Kconfig from v1 and v2 - https://patchwork.kernel.org/patch/10060075/
> v2 - Added data sheet link, fixed linuxdoc format, returned on failure in init
> routine, return on fault_check failure, updated brightness calculation and
> fixed capitalization issue - https://patchwork.kernel.org/patch/10056675/
>
> drivers/leds/Kconfig | 7 +
> drivers/leds/Makefile | 1 +
> drivers/leds/leds-lm3692x.c | 393 ++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 401 insertions(+)
> create mode 100644 drivers/leds/leds-lm3692x.c
>
> diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
> index 318a28fd58fe..1d215b39cefd 100644
> --- a/drivers/leds/Kconfig
> +++ b/drivers/leds/Kconfig
> @@ -137,6 +137,13 @@ config LEDS_LM3642
> converter plus 1.5A constant current driver for a high-current
> white LED.
>
> +config LEDS_LM3692X
> + tristate "LED support for LM3692x Chips"
> + depends on LEDS_CLASS && I2C && OF
> + select REGMAP_I2C
> + help
> + This option enables support for the TI LM3692x family
> + of white LED string drivers used for backlighting.
>
> config LEDS_LOCOMO
> tristate "LED Support for Locomo device"
> diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
> index a2a6b5a4f86d..987884a5b9a5 100644
> --- a/drivers/leds/Makefile
> +++ b/drivers/leds/Makefile
> @@ -74,6 +74,7 @@ obj-$(CONFIG_LEDS_PM8058) += leds-pm8058.o
> obj-$(CONFIG_LEDS_MLXCPLD) += leds-mlxcpld.o
> obj-$(CONFIG_LEDS_NIC78BX) += leds-nic78bx.o
> obj-$(CONFIG_LEDS_MT6323) += leds-mt6323.o
> +obj-$(CONFIG_LEDS_LM3692X) += leds-lm3692x.o
>
> # LED SPI Drivers
> obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o
> diff --git a/drivers/leds/leds-lm3692x.c b/drivers/leds/leds-lm3692x.c
> new file mode 100644
> index 000000000000..7077f9459bce
> --- /dev/null
> +++ b/drivers/leds/leds-lm3692x.c
> @@ -0,0 +1,393 @@
> +/*
> + * TI lm3692x LED Driver
> + *
> + * Copyright (C) 2017 Texas Instruments
> + *
> + * Author: Dan Murphy <dmurphy@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * Data sheet is located
> + * http://www.ti.com/lit/ds/snvsa29/snvsa29.pdf
> + */
> +
> +#include <linux/i2c.h>
> +#include <linux/init.h>
> +#include <linux/leds.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of.h>
> +#include <linux/of_gpio.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/slab.h>
> +#include <uapi/linux/uleds.h>
> +
> +#define LM3692X_REV 0x0
> +#define LM3692X_RESET 0x1
> +#define LM3692X_EN 0x10
> +#define LM3692X_BRT_CTRL 0x11
> +#define LM3692X_PWM_CTRL 0x12
> +#define LM3692X_BOOST_CTRL 0x13
> +#define LM3692X_AUTO_FREQ_HI 0x15
> +#define LM3692X_AUTO_FREQ_LO 0x16
> +#define LM3692X_BL_ADJ_THRESH 0x17
> +#define LM3692X_BRT_LSB 0x18
> +#define LM3692X_BRT_MSB 0x19
> +#define LM3692X_FAULT_CTRL 0x1e
> +#define LM3692X_FAULT_FLAGS 0x1f
> +
> +#define LM3692X_SW_RESET BIT(0)
> +#define LM3692X_DEVICE_EN BIT(0)
> +#define LM3692X_LED1_EN BIT(1)
> +#define LM3692X_LED2_EN BIT(2)
> +
> +/* Brightness Control Bits */
> +#define LM3692X_BL_ADJ_POL BIT(0)
> +#define LM3692X_RAMP_RATE_125us 0x00
> +#define LM3692X_RAMP_RATE_250us BIT(1)
> +#define LM3692X_RAMP_RATE_500us BIT(2)
> +#define LM3692X_RAMP_RATE_1ms (BIT(1) | BIT(2))
> +#define LM3692X_RAMP_RATE_2ms BIT(3)
> +#define LM3692X_RAMP_RATE_4ms (BIT(3) | BIT(1))
> +#define LM3692X_RAMP_RATE_8ms (BIT(2) | BIT(3))
> +#define LM3692X_RAMP_RATE_16ms (BIT(1) | BIT(2) | BIT(3))
> +#define LM3692X_RAMP_EN BIT(4)
> +#define LM3692X_BRHT_MODE_REG 0x00
> +#define LM3692X_BRHT_MODE_PWM BIT(5)
> +#define LM3692X_BRHT_MODE_MULTI_RAMP BIT(6)
> +#define LM3692X_BRHT_MODE_RAMP_MULTI (BIT(5) | BIT(6))
> +#define LM3692X_MAP_MODE_EXP BIT(7)
> +
> +/* PWM Register Bits */
> +#define LM3692X_PWM_FILTER_100 BIT(0)
> +#define LM3692X_PWM_FILTER_150 BIT(1)
> +#define LM3692X_PWM_FILTER_200 (BIT(0) | BIT(1))
> +#define LM3692X_PWM_HYSTER_1LSB BIT(2)
> +#define LM3692X_PWM_HYSTER_2LSB BIT(3)
> +#define LM3692X_PWM_HYSTER_3LSB (BIT(3) | BIT(2))
> +#define LM3692X_PWM_HYSTER_4LSB BIT(4)
> +#define LM3692X_PWM_HYSTER_5LSB (BIT(4) | BIT(2))
> +#define LM3692X_PWM_HYSTER_6LSB (BIT(4) | BIT(3))
> +#define LM3692X_PWM_POLARITY BIT(5)
> +#define LM3692X_PWM_SAMP_4MHZ BIT(6)
> +#define LM3692X_PWM_SAMP_24MHZ BIT(7)
> +
> +/* Boost Control Bits */
> +#define LM3692X_OCP_PROT_1A BIT(0)
> +#define LM3692X_OCP_PROT_1_25A BIT(1)
> +#define LM3692X_OCP_PROT_1_5A (BIT(0) | BIT(1))
> +#define LM3692X_OVP_21V BIT(2)
> +#define LM3692X_OVP_25V BIT(3)
> +#define LM3692X_OVP_29V (BIT(2) | BIT(3))
> +#define LM3692X_MIN_IND_22UH BIT(4)
> +#define LM3692X_BOOST_SW_1MHZ BIT(5)
> +#define LM3692X_BOOST_SW_NO_SHIFT BIT(6)
> +
> +/* Fault Control Bits */
> +#define LM3692X_FAULT_CTRL_OVP BIT(0)
> +#define LM3692X_FAULT_CTRL_OCP BIT(1)
> +#define LM3692X_FAULT_CTRL_TSD BIT(2)
> +#define LM3692X_FAULT_CTRL_OPEN BIT(3)
> +
> +/* Fault Flag Bits */
> +#define LM3692X_FAULT_FLAG_OVP BIT(0)
> +#define LM3692X_FAULT_FLAG_OCP BIT(1)
> +#define LM3692X_FAULT_FLAG_TSD BIT(2)
> +#define LM3692X_FAULT_FLAG_SHRT BIT(3)
> +#define LM3692X_FAULT_FLAG_OPEN BIT(4)
> +
> +/**
> + * struct lm3692x_led -
> + * @lock - Lock for reading/writing the device
> + * @client - Pointer to the I2C client
> + * @led_dev - LED class device pointer
> + * @regmap - Devices register map
> + * @enable_gpio - VDDIO/EN gpio to enable communication interface
> + * @regulator - LED supply regulator pointer
> + * @label - LED label
> + */
> +struct lm3692x_led {
> + struct mutex lock;
> + struct i2c_client *client;
> + struct led_classdev led_dev;
> + struct regmap *regmap;
> + struct gpio_desc *enable_gpio;
> + struct regulator *regulator;
> + char label[LED_MAX_NAME_SIZE];
> +};
> +
> +static const struct reg_default lm3692x_reg_defs[] = {
> + {LM3692X_EN, 0xf},
> + {LM3692X_BRT_CTRL, 0x61},
> + {LM3692X_PWM_CTRL, 0x73},
> + {LM3692X_BOOST_CTRL, 0x6f},
> + {LM3692X_AUTO_FREQ_HI, 0x0},
> + {LM3692X_AUTO_FREQ_LO, 0x0},
> + {LM3692X_BL_ADJ_THRESH, 0x0},
> + {LM3692X_BRT_LSB, 0x7},
> + {LM3692X_BRT_MSB, 0xff},
> + {LM3692X_FAULT_CTRL, 0x7},
> +};
> +
> +static const struct regmap_config lm3692x_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 8,
> +
> + .max_register = LM3692X_FAULT_FLAGS,
> + .reg_defaults = lm3692x_reg_defs,
> + .num_reg_defaults = ARRAY_SIZE(lm3692x_reg_defs),
> + .cache_type = REGCACHE_RBTREE,
> +};
> +
> +static int lm3692x_fault_check(struct lm3692x_led *led)
> +{
> + int ret;
> + unsigned int read_buf;
> +
> + ret = regmap_read(led->regmap, LM3692X_FAULT_FLAGS, &read_buf);
> + if (ret)
> + return ret;
> +
> + if (read_buf)
> + dev_err(&led->client->dev, "Detected a fault 0x%X\n", read_buf);
> +
> + /* The first read may clear the fault. Check again to see if the fault
> + * still exits and return that value.
> + */
> + regmap_read(led->regmap, LM3692X_FAULT_FLAGS, &read_buf);
> + if (read_buf)
> + dev_err(&led->client->dev, "Second read of fault flags 0x%X\n",
> + read_buf);
> +
> + return read_buf;
> +}
> +
> +static int lm3692x_brightness_set(struct led_classdev *led_cdev,
> + enum led_brightness brt_val)
> +{
> + struct lm3692x_led *led =
> + container_of(led_cdev, struct lm3692x_led, led_dev);
> + int ret;
> + int led_brightness_lsb = (brt_val >> 5);
> +
> + mutex_lock(&led->lock);
> +
> + ret = lm3692x_fault_check(led);
> + if (ret) {
> + dev_err(&led->client->dev, "Cannot read/clear faults\n");
> + goto out;
> + }
> +
> + ret = regmap_write(led->regmap, LM3692X_BRT_MSB, brt_val);
> + if (ret) {
> + dev_err(&led->client->dev, "Cannot write MSB\n");
> + goto out;
> + }
> +
> + ret = regmap_write(led->regmap, LM3692X_BRT_LSB, led_brightness_lsb);
> + if (ret) {
> + dev_err(&led->client->dev, "Cannot write LSB\n");
> + goto out;
> + }
> +out:
> + mutex_unlock(&led->lock);
> + return ret;
> +}
> +
> +static int lm3692x_init(struct lm3692x_led *led)
> +{
> + int ret;
> +
> + if (led->regulator) {
> + ret = regulator_enable(led->regulator);
> + if (ret) {
> + dev_err(&led->client->dev,
> + "Failed to enable regulator\n");
> + return ret;
> + }
> + }
> +
> + if (led->enable_gpio)
> + gpiod_direction_output(led->enable_gpio, 1);
> +
> + ret = lm3692x_fault_check(led);
> + if (ret) {
> + dev_err(&led->client->dev, "Cannot read/clear faults\n");
> + goto out;
> + }
> +
> + ret = regmap_write(led->regmap, LM3692X_BRT_CTRL, 0x00);
> + if (ret)
> + goto out;
> +
> + /*
> + * For glitch free operation, the following data should
> + * only be written while device enable bit is 0
> + * per Section 7.5.14 of the data sheet
> + */
> + ret = regmap_write(led->regmap, LM3692X_PWM_CTRL,
> + LM3692X_PWM_FILTER_100 | LM3692X_PWM_SAMP_24MHZ);
> + if (ret)
> + goto out;
> +
> + ret = regmap_write(led->regmap, LM3692X_BOOST_CTRL,
> + LM3692X_BRHT_MODE_RAMP_MULTI |
> + LM3692X_BL_ADJ_POL |
> + LM3692X_RAMP_RATE_250us);
> + if (ret)
> + goto out;
> +
> + ret = regmap_write(led->regmap, LM3692X_AUTO_FREQ_HI, 0x00);
> + if (ret)
> + goto out;
> +
> + ret = regmap_write(led->regmap, LM3692X_AUTO_FREQ_LO, 0x00);
> + if (ret)
> + goto out;
> +
> + ret = regmap_write(led->regmap, LM3692X_BL_ADJ_THRESH, 0x00);
> + if (ret)
> + goto out;
> +
> + ret = regmap_write(led->regmap, LM3692X_BRT_CTRL,
> + LM3692X_BL_ADJ_POL | LM3692X_PWM_HYSTER_4LSB);
> + if (ret)
> + goto out;
> +
> + return ret;
> +out:
> + dev_err(&led->client->dev, "Fail writing initialization values\n");
> +
> + if (led->enable_gpio)
> + gpiod_direction_output(led->enable_gpio, 0);
> +
> + if (led->regulator) {
> + ret = regulator_disable(led->regulator);
> + if (ret)
> + dev_err(&led->client->dev,
> + "Failed to disable regulator\n");
> + }
> +
> + return ret;
> +}
> +
> +static int lm3692x_probe(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + int ret;
> + struct lm3692x_led *led;
> + struct device_node *np = client->dev.of_node;
> + struct device_node *child_node;
> + const char *name;
> +
> + led = devm_kzalloc(&client->dev, sizeof(*led), GFP_KERNEL);
> + if (!led)
> + return -ENOMEM;
> +
> + for_each_available_child_of_node(np, child_node) {
> + led->led_dev.default_trigger = of_get_property(child_node,
> + "linux,default-trigger",
> + NULL);
> +
> + ret = of_property_read_string(child_node, "label", &name);
> + if (!ret)
> + snprintf(led->label, sizeof(led->label), "%s:%s",
> + np->name, name);
This needs to be id->name like below
Dan
> + else
> + snprintf(led->label, sizeof(led->label),
> + "%s::backlight_cluster", id->name);
> + };
> +
> + led->enable_gpio = devm_gpiod_get_optional(&client->dev,
> + "enable", GPIOD_OUT_LOW);
> + if (IS_ERR(led->enable_gpio)) {
> + ret = PTR_ERR(led->enable_gpio);
> + dev_err(&client->dev, "Failed to get enable gpio: %d\n", ret);
> + return ret;
> + }
> +
> + led->regulator = devm_regulator_get(&client->dev, "vled");
> + if (IS_ERR(led->regulator))
> + led->regulator = NULL;
> +
> + led->client = client;
> + led->led_dev.name = led->label;
> + led->led_dev.brightness_set_blocking = lm3692x_brightness_set;
> +
> + mutex_init(&led->lock);
> +
> + i2c_set_clientdata(client, led);
> +
> + led->regmap = devm_regmap_init_i2c(client, &lm3692x_regmap_config);
> + if (IS_ERR(led->regmap)) {
> + ret = PTR_ERR(led->regmap);
> + dev_err(&client->dev, "Failed to allocate register map: %d\n",
> + ret);
> + return ret;
> + }
> +
> + ret = lm3692x_init(led);
> + if (ret)
> + return ret;
> +
> + ret = devm_led_classdev_register(&client->dev, &led->led_dev);
> + if (ret) {
> + dev_err(&client->dev, "led register err: %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int lm3692x_remove(struct i2c_client *client)
> +{
> + struct lm3692x_led *led = i2c_get_clientdata(client);
> + int ret;
> +
> + if (led->enable_gpio)
> + gpiod_direction_output(led->enable_gpio, 0);
> +
> + if (led->regulator) {
> + ret = regulator_disable(led->regulator);
> + if (ret)
> + dev_err(&led->client->dev,
> + "Failed to disable regulator\n");
> + }
> +
> + mutex_destroy(&led->lock);
> +
> + return 0;
> +}
> +
> +static const struct i2c_device_id lm3692x_id[] = {
> + { "lm36922", 0 },
> + { "lm36923", 1 },
> + { }
> +};
> +MODULE_DEVICE_TABLE(i2c, lm3692x_id);
> +
> +static const struct of_device_id of_lm3692x_leds_match[] = {
> + { .compatible = "ti,lm36922", },
> + { .compatible = "ti,lm36923", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, of_lm3692x_leds_match);
> +
> +static struct i2c_driver lm3692x_driver = {
> + .driver = {
> + .name = "lm3692x",
> + .of_match_table = of_lm3692x_leds_match,
> + },
> + .probe = lm3692x_probe,
> + .remove = lm3692x_remove,
> + .id_table = lm3692x_id,
> +};
> +module_i2c_driver(lm3692x_driver);
> +
> +MODULE_DESCRIPTION("Texas Instruments LM3692X LED driver");
> +MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
> +MODULE_LICENSE("GPL v2");
>
--
------------------
Dan Murphy
^ permalink raw reply
* [PATCH v11 1/2] dt: bindings: lm3692x: Add bindings for lm3692x LED driver
From: Dan Murphy @ 2017-12-12 18:15 UTC (permalink / raw)
To: robh+dt, mark.rutland, rpurdie, jacek.anaszewski, pavel
Cc: devicetree, linux-kernel, linux-leds, Dan Murphy
This adds the devicetree bindings for the LM3692x
I2C LED string driver.
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
v11 - No changes - https://patchwork.kernel.org/patch/10107893/
v10 - Changed label to add color - https://patchwork.kernel.org/patch/10105649/
v9 - Moved 2 nodes to Optional Child and renamed node names to device type
https://patchwork.kernel.org/patch/10093757/
v8 - Added address-cells and size-cells as well as child node reg - https://patchwork.kernel.org/patch/10091259/
v7 - No changes - https://patchwork.kernel.org/patch/10087475/
v6 - No changes -https://patchwork.kernel.org/patch/10085567/
v5 - No Changes - https://patchwork.kernel.org/patch/10081071/
v4 - Fix example node, added trigger entry, removed ambiguous x for compatible and
added common.txt pointer for label - https://patchwork.kernel.org/patch/10060107
v3 - No changes
v2 - No changes - https://patchwork.kernel.org/patch/10056677/
.../devicetree/bindings/leds/leds-lm3692x.txt | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/leds/leds-lm3692x.txt
diff --git a/Documentation/devicetree/bindings/leds/leds-lm3692x.txt b/Documentation/devicetree/bindings/leds/leds-lm3692x.txt
new file mode 100644
index 000000000000..6c9074f84a51
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/leds-lm3692x.txt
@@ -0,0 +1,49 @@
+* Texas Instruments - LM3692x Highly Efficient White LED Driver
+
+The LM3692x is an ultra-compact, highly efficient,
+white-LED driver designed for LCD display backlighting.
+
+The main difference between the LM36922 and LM36923 is the number of
+LED strings it supports. The LM36922 supports two strings while the LM36923
+supports three strings.
+
+Required properties:
+ - compatible:
+ "ti,lm36922"
+ "ti,lm36923"
+ - reg : I2C slave address
+ - #address-cells : 1
+ - #size-cells : 0
+
+Optional properties:
+ - enable-gpios : gpio pin to enable/disable the device.
+ - vled-supply : LED supply
+
+Required child properties:
+ - reg : 0
+
+Optional child properties:
+ - label : see Documentation/devicetree/bindings/leds/common.txt
+ - linux,default-trigger :
+ see Documentation/devicetree/bindings/leds/common.txt
+
+Example:
+
+led-controller@36 {
+ compatible = "ti,lm3692x";
+ reg = <0x36>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ vled-supply = <&vbatt>;
+
+ led@0 {
+ reg = <0>;
+ label = "white:backlight_cluster";
+ linux,default-trigger = "backlight";
+ };
+}
+
+For more product information please see the link below:
+http://www.ti.com/lit/ds/snvsa29/snvsa29.pdf
--
2.15.0.124.g7668cbc60
^ permalink raw reply related
* [PATCH v11 2/2] leds: lm3692x: Introduce LM3692x dual string driver
From: Dan Murphy @ 2017-12-12 18:15 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
rpurdie-Fm38FmjxZ/leoWH0uzbU5w,
jacek.anaszewski-Re5JQEeQqe8AvxtiuMwx3w, pavel-+ZI9xUNit7I
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-leds-u79uwXL29TY76Z2rM5mHXA, Dan Murphy
In-Reply-To: <20171212181550.22677-1-dmurphy-l0cyMroinI0@public.gmane.org>
Introducing the LM3692x Dual-String white LED driver.
Data sheet is located
http://www.ti.com/lit/ds/snvsa29/snvsa29.pdf
Signed-off-by: Dan Murphy <dmurphy-l0cyMroinI0@public.gmane.org>
---
v11 - change DT label case to id->name from np->name - https://patchwork.kernel.org/patch/10107895/
v10 - No changes - https://patchwork.kernel.org/patch/10105651/
v9 - Change the no DT label case to pull the device name from the i2c_id struct
so that the device name can be part of the sysfs node - https://patchwork.kernel.org/patch/10093759/
v8 - No changes
v7 - Reverted back to creating the LED label within the driver -
https://patchwork.kernel.org/patch/10087473/
v6 - Use new LED API to compose LED label as opposed to creating it. -
https://patchwork.kernel.org/patch/10085565/
v5 - Added OF dependency in Kconfig, added extra fault flag read to ensure that
if a fault exists and it is not a artifact, fixed LED class label to be derived
from either the DT child "label" node or create a label based on
parent_node_name:led color:trigger, removed ifdef for CONFIG_OF and removed
of_match_ptr - https://patchwork.kernel.org/patch/10081073/
v4 - Converted to devm led class register, changed MODULE_LICENSE to GPL v2,
set the led name based on child node name or label entry, removed fault and
returned read_buf for fault checking, added mutex_destroy to remove function,
and removed LED_FULL - https://patchwork.kernel.org/patch/10060109/
v3 - Add missing Makefile and Kconfig from v1 and v2 - https://patchwork.kernel.org/patch/10060075/
v2 - Added data sheet link, fixed linuxdoc format, returned on failure in init
routine, return on fault_check failure, updated brightness calculation and
fixed capitalization issue - https://patchwork.kernel.org/patch/10056675/
drivers/leds/Kconfig | 7 +
drivers/leds/Makefile | 1 +
drivers/leds/leds-lm3692x.c | 393 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 401 insertions(+)
create mode 100644 drivers/leds/leds-lm3692x.c
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 318a28fd58fe..1d215b39cefd 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -137,6 +137,13 @@ config LEDS_LM3642
converter plus 1.5A constant current driver for a high-current
white LED.
+config LEDS_LM3692X
+ tristate "LED support for LM3692x Chips"
+ depends on LEDS_CLASS && I2C && OF
+ select REGMAP_I2C
+ help
+ This option enables support for the TI LM3692x family
+ of white LED string drivers used for backlighting.
config LEDS_LOCOMO
tristate "LED Support for Locomo device"
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index a2a6b5a4f86d..987884a5b9a5 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -74,6 +74,7 @@ obj-$(CONFIG_LEDS_PM8058) += leds-pm8058.o
obj-$(CONFIG_LEDS_MLXCPLD) += leds-mlxcpld.o
obj-$(CONFIG_LEDS_NIC78BX) += leds-nic78bx.o
obj-$(CONFIG_LEDS_MT6323) += leds-mt6323.o
+obj-$(CONFIG_LEDS_LM3692X) += leds-lm3692x.o
# LED SPI Drivers
obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o
diff --git a/drivers/leds/leds-lm3692x.c b/drivers/leds/leds-lm3692x.c
new file mode 100644
index 000000000000..bfcffb8b9bd5
--- /dev/null
+++ b/drivers/leds/leds-lm3692x.c
@@ -0,0 +1,393 @@
+/*
+ * TI lm3692x LED Driver
+ *
+ * Copyright (C) 2017 Texas Instruments
+ *
+ * Author: Dan Murphy <dmurphy-l0cyMroinI0@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * Data sheet is located
+ * http://www.ti.com/lit/ds/snvsa29/snvsa29.pdf
+ */
+
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/leds.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/slab.h>
+#include <uapi/linux/uleds.h>
+
+#define LM3692X_REV 0x0
+#define LM3692X_RESET 0x1
+#define LM3692X_EN 0x10
+#define LM3692X_BRT_CTRL 0x11
+#define LM3692X_PWM_CTRL 0x12
+#define LM3692X_BOOST_CTRL 0x13
+#define LM3692X_AUTO_FREQ_HI 0x15
+#define LM3692X_AUTO_FREQ_LO 0x16
+#define LM3692X_BL_ADJ_THRESH 0x17
+#define LM3692X_BRT_LSB 0x18
+#define LM3692X_BRT_MSB 0x19
+#define LM3692X_FAULT_CTRL 0x1e
+#define LM3692X_FAULT_FLAGS 0x1f
+
+#define LM3692X_SW_RESET BIT(0)
+#define LM3692X_DEVICE_EN BIT(0)
+#define LM3692X_LED1_EN BIT(1)
+#define LM3692X_LED2_EN BIT(2)
+
+/* Brightness Control Bits */
+#define LM3692X_BL_ADJ_POL BIT(0)
+#define LM3692X_RAMP_RATE_125us 0x00
+#define LM3692X_RAMP_RATE_250us BIT(1)
+#define LM3692X_RAMP_RATE_500us BIT(2)
+#define LM3692X_RAMP_RATE_1ms (BIT(1) | BIT(2))
+#define LM3692X_RAMP_RATE_2ms BIT(3)
+#define LM3692X_RAMP_RATE_4ms (BIT(3) | BIT(1))
+#define LM3692X_RAMP_RATE_8ms (BIT(2) | BIT(3))
+#define LM3692X_RAMP_RATE_16ms (BIT(1) | BIT(2) | BIT(3))
+#define LM3692X_RAMP_EN BIT(4)
+#define LM3692X_BRHT_MODE_REG 0x00
+#define LM3692X_BRHT_MODE_PWM BIT(5)
+#define LM3692X_BRHT_MODE_MULTI_RAMP BIT(6)
+#define LM3692X_BRHT_MODE_RAMP_MULTI (BIT(5) | BIT(6))
+#define LM3692X_MAP_MODE_EXP BIT(7)
+
+/* PWM Register Bits */
+#define LM3692X_PWM_FILTER_100 BIT(0)
+#define LM3692X_PWM_FILTER_150 BIT(1)
+#define LM3692X_PWM_FILTER_200 (BIT(0) | BIT(1))
+#define LM3692X_PWM_HYSTER_1LSB BIT(2)
+#define LM3692X_PWM_HYSTER_2LSB BIT(3)
+#define LM3692X_PWM_HYSTER_3LSB (BIT(3) | BIT(2))
+#define LM3692X_PWM_HYSTER_4LSB BIT(4)
+#define LM3692X_PWM_HYSTER_5LSB (BIT(4) | BIT(2))
+#define LM3692X_PWM_HYSTER_6LSB (BIT(4) | BIT(3))
+#define LM3692X_PWM_POLARITY BIT(5)
+#define LM3692X_PWM_SAMP_4MHZ BIT(6)
+#define LM3692X_PWM_SAMP_24MHZ BIT(7)
+
+/* Boost Control Bits */
+#define LM3692X_OCP_PROT_1A BIT(0)
+#define LM3692X_OCP_PROT_1_25A BIT(1)
+#define LM3692X_OCP_PROT_1_5A (BIT(0) | BIT(1))
+#define LM3692X_OVP_21V BIT(2)
+#define LM3692X_OVP_25V BIT(3)
+#define LM3692X_OVP_29V (BIT(2) | BIT(3))
+#define LM3692X_MIN_IND_22UH BIT(4)
+#define LM3692X_BOOST_SW_1MHZ BIT(5)
+#define LM3692X_BOOST_SW_NO_SHIFT BIT(6)
+
+/* Fault Control Bits */
+#define LM3692X_FAULT_CTRL_OVP BIT(0)
+#define LM3692X_FAULT_CTRL_OCP BIT(1)
+#define LM3692X_FAULT_CTRL_TSD BIT(2)
+#define LM3692X_FAULT_CTRL_OPEN BIT(3)
+
+/* Fault Flag Bits */
+#define LM3692X_FAULT_FLAG_OVP BIT(0)
+#define LM3692X_FAULT_FLAG_OCP BIT(1)
+#define LM3692X_FAULT_FLAG_TSD BIT(2)
+#define LM3692X_FAULT_FLAG_SHRT BIT(3)
+#define LM3692X_FAULT_FLAG_OPEN BIT(4)
+
+/**
+ * struct lm3692x_led -
+ * @lock - Lock for reading/writing the device
+ * @client - Pointer to the I2C client
+ * @led_dev - LED class device pointer
+ * @regmap - Devices register map
+ * @enable_gpio - VDDIO/EN gpio to enable communication interface
+ * @regulator - LED supply regulator pointer
+ * @label - LED label
+ */
+struct lm3692x_led {
+ struct mutex lock;
+ struct i2c_client *client;
+ struct led_classdev led_dev;
+ struct regmap *regmap;
+ struct gpio_desc *enable_gpio;
+ struct regulator *regulator;
+ char label[LED_MAX_NAME_SIZE];
+};
+
+static const struct reg_default lm3692x_reg_defs[] = {
+ {LM3692X_EN, 0xf},
+ {LM3692X_BRT_CTRL, 0x61},
+ {LM3692X_PWM_CTRL, 0x73},
+ {LM3692X_BOOST_CTRL, 0x6f},
+ {LM3692X_AUTO_FREQ_HI, 0x0},
+ {LM3692X_AUTO_FREQ_LO, 0x0},
+ {LM3692X_BL_ADJ_THRESH, 0x0},
+ {LM3692X_BRT_LSB, 0x7},
+ {LM3692X_BRT_MSB, 0xff},
+ {LM3692X_FAULT_CTRL, 0x7},
+};
+
+static const struct regmap_config lm3692x_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = LM3692X_FAULT_FLAGS,
+ .reg_defaults = lm3692x_reg_defs,
+ .num_reg_defaults = ARRAY_SIZE(lm3692x_reg_defs),
+ .cache_type = REGCACHE_RBTREE,
+};
+
+static int lm3692x_fault_check(struct lm3692x_led *led)
+{
+ int ret;
+ unsigned int read_buf;
+
+ ret = regmap_read(led->regmap, LM3692X_FAULT_FLAGS, &read_buf);
+ if (ret)
+ return ret;
+
+ if (read_buf)
+ dev_err(&led->client->dev, "Detected a fault 0x%X\n", read_buf);
+
+ /* The first read may clear the fault. Check again to see if the fault
+ * still exits and return that value.
+ */
+ regmap_read(led->regmap, LM3692X_FAULT_FLAGS, &read_buf);
+ if (read_buf)
+ dev_err(&led->client->dev, "Second read of fault flags 0x%X\n",
+ read_buf);
+
+ return read_buf;
+}
+
+static int lm3692x_brightness_set(struct led_classdev *led_cdev,
+ enum led_brightness brt_val)
+{
+ struct lm3692x_led *led =
+ container_of(led_cdev, struct lm3692x_led, led_dev);
+ int ret;
+ int led_brightness_lsb = (brt_val >> 5);
+
+ mutex_lock(&led->lock);
+
+ ret = lm3692x_fault_check(led);
+ if (ret) {
+ dev_err(&led->client->dev, "Cannot read/clear faults\n");
+ goto out;
+ }
+
+ ret = regmap_write(led->regmap, LM3692X_BRT_MSB, brt_val);
+ if (ret) {
+ dev_err(&led->client->dev, "Cannot write MSB\n");
+ goto out;
+ }
+
+ ret = regmap_write(led->regmap, LM3692X_BRT_LSB, led_brightness_lsb);
+ if (ret) {
+ dev_err(&led->client->dev, "Cannot write LSB\n");
+ goto out;
+ }
+out:
+ mutex_unlock(&led->lock);
+ return ret;
+}
+
+static int lm3692x_init(struct lm3692x_led *led)
+{
+ int ret;
+
+ if (led->regulator) {
+ ret = regulator_enable(led->regulator);
+ if (ret) {
+ dev_err(&led->client->dev,
+ "Failed to enable regulator\n");
+ return ret;
+ }
+ }
+
+ if (led->enable_gpio)
+ gpiod_direction_output(led->enable_gpio, 1);
+
+ ret = lm3692x_fault_check(led);
+ if (ret) {
+ dev_err(&led->client->dev, "Cannot read/clear faults\n");
+ goto out;
+ }
+
+ ret = regmap_write(led->regmap, LM3692X_BRT_CTRL, 0x00);
+ if (ret)
+ goto out;
+
+ /*
+ * For glitch free operation, the following data should
+ * only be written while device enable bit is 0
+ * per Section 7.5.14 of the data sheet
+ */
+ ret = regmap_write(led->regmap, LM3692X_PWM_CTRL,
+ LM3692X_PWM_FILTER_100 | LM3692X_PWM_SAMP_24MHZ);
+ if (ret)
+ goto out;
+
+ ret = regmap_write(led->regmap, LM3692X_BOOST_CTRL,
+ LM3692X_BRHT_MODE_RAMP_MULTI |
+ LM3692X_BL_ADJ_POL |
+ LM3692X_RAMP_RATE_250us);
+ if (ret)
+ goto out;
+
+ ret = regmap_write(led->regmap, LM3692X_AUTO_FREQ_HI, 0x00);
+ if (ret)
+ goto out;
+
+ ret = regmap_write(led->regmap, LM3692X_AUTO_FREQ_LO, 0x00);
+ if (ret)
+ goto out;
+
+ ret = regmap_write(led->regmap, LM3692X_BL_ADJ_THRESH, 0x00);
+ if (ret)
+ goto out;
+
+ ret = regmap_write(led->regmap, LM3692X_BRT_CTRL,
+ LM3692X_BL_ADJ_POL | LM3692X_PWM_HYSTER_4LSB);
+ if (ret)
+ goto out;
+
+ return ret;
+out:
+ dev_err(&led->client->dev, "Fail writing initialization values\n");
+
+ if (led->enable_gpio)
+ gpiod_direction_output(led->enable_gpio, 0);
+
+ if (led->regulator) {
+ ret = regulator_disable(led->regulator);
+ if (ret)
+ dev_err(&led->client->dev,
+ "Failed to disable regulator\n");
+ }
+
+ return ret;
+}
+
+static int lm3692x_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int ret;
+ struct lm3692x_led *led;
+ struct device_node *np = client->dev.of_node;
+ struct device_node *child_node;
+ const char *name;
+
+ led = devm_kzalloc(&client->dev, sizeof(*led), GFP_KERNEL);
+ if (!led)
+ return -ENOMEM;
+
+ for_each_available_child_of_node(np, child_node) {
+ led->led_dev.default_trigger = of_get_property(child_node,
+ "linux,default-trigger",
+ NULL);
+
+ ret = of_property_read_string(child_node, "label", &name);
+ if (!ret)
+ snprintf(led->label, sizeof(led->label), "%s:%s",
+ id->name, name);
+ else
+ snprintf(led->label, sizeof(led->label),
+ "%s::backlight_cluster", id->name);
+ };
+
+ led->enable_gpio = devm_gpiod_get_optional(&client->dev,
+ "enable", GPIOD_OUT_LOW);
+ if (IS_ERR(led->enable_gpio)) {
+ ret = PTR_ERR(led->enable_gpio);
+ dev_err(&client->dev, "Failed to get enable gpio: %d\n", ret);
+ return ret;
+ }
+
+ led->regulator = devm_regulator_get(&client->dev, "vled");
+ if (IS_ERR(led->regulator))
+ led->regulator = NULL;
+
+ led->client = client;
+ led->led_dev.name = led->label;
+ led->led_dev.brightness_set_blocking = lm3692x_brightness_set;
+
+ mutex_init(&led->lock);
+
+ i2c_set_clientdata(client, led);
+
+ led->regmap = devm_regmap_init_i2c(client, &lm3692x_regmap_config);
+ if (IS_ERR(led->regmap)) {
+ ret = PTR_ERR(led->regmap);
+ dev_err(&client->dev, "Failed to allocate register map: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = lm3692x_init(led);
+ if (ret)
+ return ret;
+
+ ret = devm_led_classdev_register(&client->dev, &led->led_dev);
+ if (ret) {
+ dev_err(&client->dev, "led register err: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int lm3692x_remove(struct i2c_client *client)
+{
+ struct lm3692x_led *led = i2c_get_clientdata(client);
+ int ret;
+
+ if (led->enable_gpio)
+ gpiod_direction_output(led->enable_gpio, 0);
+
+ if (led->regulator) {
+ ret = regulator_disable(led->regulator);
+ if (ret)
+ dev_err(&led->client->dev,
+ "Failed to disable regulator\n");
+ }
+
+ mutex_destroy(&led->lock);
+
+ return 0;
+}
+
+static const struct i2c_device_id lm3692x_id[] = {
+ { "lm36922", 0 },
+ { "lm36923", 1 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, lm3692x_id);
+
+static const struct of_device_id of_lm3692x_leds_match[] = {
+ { .compatible = "ti,lm36922", },
+ { .compatible = "ti,lm36923", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, of_lm3692x_leds_match);
+
+static struct i2c_driver lm3692x_driver = {
+ .driver = {
+ .name = "lm3692x",
+ .of_match_table = of_lm3692x_leds_match,
+ },
+ .probe = lm3692x_probe,
+ .remove = lm3692x_remove,
+ .id_table = lm3692x_id,
+};
+module_i2c_driver(lm3692x_driver);
+
+MODULE_DESCRIPTION("Texas Instruments LM3692X LED driver");
+MODULE_AUTHOR("Dan Murphy <dmurphy-l0cyMroinI0@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
--
2.15.0.124.g7668cbc60
--
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^ permalink raw reply related
* [PATCH 0/5] Add Sound support for iWave RZ/G1M board
From: Biju Das @ 2017-12-12 18:25 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King
Cc: Simon Horman, Magnus Damm, Chris Paterson, devicetree,
linux-renesas-soc, linux-arm-kernel, Biju Das
This series aims to add sound support for iWave RZ/G1M board.
This patch series has documentation dependency on
https://patchwork.kernel.org/patch/10108014/
Biju Das (5):
ARM: shmobile: defconfig: Enable SGTL5000 audio codec
ARM: dts: r8a7743: Add audio clocks
ARM: dts: r8a7743: Add audio DMAC support
ARM: dts: r8a7743: Add sound support
ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio codec
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 24 +++
arch/arm/boot/dts/r8a7743.dtsi | 270 ++++++++++++++++++++++++++++++++
arch/arm/configs/shmobile_defconfig | 1 +
3 files changed, 295 insertions(+)
--
1.9.1
^ permalink raw reply
* [PATCH 1/5] ARM: shmobile: defconfig: Enable SGTL5000 audio codec
From: Biju Das @ 2017-12-12 18:25 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King
Cc: Simon Horman, Magnus Damm, Chris Paterson, devicetree,
linux-renesas-soc, linux-arm-kernel, Biju Das
In-Reply-To: <1513103111-45830-1-git-send-email-biju.das@bp.renesas.com>
The iWave RZ/G1M Q7 carrier board supports I2S audio codec "SGTL5000".
To increase hardware support enable the driver in the shmobile_defconfig
multiplatform configuration.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm/configs/shmobile_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 7b4fc01..d60dbe1 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -173,6 +173,7 @@ CONFIG_SND_SOC=y
CONFIG_SND_SOC_SH4_FSI=y
CONFIG_SND_SOC_RCAR=y
CONFIG_SND_SOC_AK4642=y
+CONFIG_SND_SOC_SGTL5000=y
CONFIG_SND_SOC_WM8978=y
CONFIG_SND_SIMPLE_SCU_CARD=y
CONFIG_USB=y
--
1.9.1
^ permalink raw reply related
* [PATCH 2/5] ARM: dts: r8a7743: Add audio clocks
From: Biju Das @ 2017-12-12 18:25 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King
Cc: Simon Horman, Magnus Damm, Chris Paterson, devicetree,
linux-renesas-soc, linux-arm-kernel, Biju Das
In-Reply-To: <1513103111-45830-1-git-send-email-biju.das@bp.renesas.com>
Describe the external audio clocks required by the sound driver.
Boards that provide audio clocks need to override the clock frequencies.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm/boot/dts/r8a7743.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index c09c667..2f0ec9d 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -1238,6 +1238,29 @@
clock-frequency = <0>;
};
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
--
1.9.1
^ permalink raw reply related
* [PATCH 3/5] ARM: dts: r8a7743: Add audio DMAC support
From: Biju Das @ 2017-12-12 18:25 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King
Cc: Simon Horman, Magnus Damm, Chris Paterson,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Biju Das
In-Reply-To: <1513103111-45830-1-git-send-email-biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
Instantiate the two audio DMA controllers on the r8a7743 device tree.
Signed-off-by: Biju Das <biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
Reviewed-by: Fabrizio Castro <fabrizio.castro-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
---
arch/arm/boot/dts/r8a7743.dtsi | 62 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 2f0ec9d..b60527a 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -359,6 +359,68 @@
dma-channels = <15>;
};
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7743",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a7743",
+ "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 501>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 501>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,r8a7743-usb-dmac",
"renesas,usb-dmac";
--
1.9.1
--
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^ permalink raw reply related
* [PATCH 4/5] ARM: dts: r8a7743: Add sound support
From: Biju Das @ 2017-12-12 18:25 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King
Cc: Simon Horman, Magnus Damm, Chris Paterson, devicetree,
linux-renesas-soc, linux-arm-kernel, Biju Das
In-Reply-To: <1513103111-45830-1-git-send-email-biju.das@bp.renesas.com>
Define the generic r8a7743(RZ/G1M) part of the sound device node.
This patch is based on the r8a7791 sound work by Kuninori Morimoto.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm/boot/dts/r8a7743.dtsi | 185 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 185 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index b60527a..59860c8 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -1290,6 +1290,191 @@
resets = <&cpg 319>;
status = "disabled";
};
+
+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7743",
+ "renesas,rcar_sound-gen2";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+ <&cpg CPG_CORE R8A7743_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6", "src.5",
+ "src.4", "src.3", "src.2", "src.1", "src.0",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma1 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma1 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma1 0x9a>;
+ dma-names = "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma1 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma1 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma1 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma1 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma1 0xba>;
+ dma-names = "rx", "tx";
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ };
+ };
};
/* External root clock */
--
1.9.1
^ permalink raw reply related
* [PATCH 5/5] ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio codec
From: Biju Das @ 2017-12-12 18:25 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King
Cc: Simon Horman, Magnus Damm, Chris Paterson, devicetree,
linux-renesas-soc, linux-arm-kernel, Biju Das
In-Reply-To: <1513103111-45830-1-git-send-email-biju.das@bp.renesas.com>
This patch enables SGTL5000 audio codec on the carrier board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index 54470c6..2070b14 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -20,6 +20,20 @@
stdout-path = "serial0:115200n8";
};
+ audio_clock: audio_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ reg_1p5v: 1p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P5V";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
@@ -83,6 +97,16 @@
compatible = "ti,bq32000";
reg = <0x68>;
};
+
+ sgtl5000: codec@0a {
+ compatible = "fsl,sgtl5000";
+ #sound-dai-cells = <0>;
+ reg = <0x0a>;
+ clocks = <&audio_clock>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ VDDD-supply = <®_1p5v>;
+ };
};
&pci0 {
--
1.9.1
^ permalink raw reply related
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