* [PATCH v4 2/6] dt: bindings: lp8860: Update DT label binding
From: Dan Murphy @ 2017-12-12 22:01 UTC (permalink / raw)
To: robh+dt, mark.rutland, rpurdie, jacek.anaszewski, pavel
Cc: devicetree, linux-kernel, linux-leds, Dan Murphy
In-Reply-To: <20171212220143.31210-1-dmurphy@ti.com>
Update the lp8860 label binding to the LED
standard as documented in
Documentation/devicetree/bindings/leds/common.txt
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
v4 - No changes
v3 - Added address and size cells, updated label with color and inserted spaces
around the reg node - https://patchwork.kernel.org/patch/10093749/
v2 - Added reg to child node and made it required
Documentation/devicetree/bindings/leds/leds-lp8860.txt | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/leds/leds-lp8860.txt b/Documentation/devicetree/bindings/leds/leds-lp8860.txt
index b9d09acbaa73..c3d64ade1e26 100644
--- a/Documentation/devicetree/bindings/leds/leds-lp8860.txt
+++ b/Documentation/devicetree/bindings/leds/leds-lp8860.txt
@@ -9,20 +9,33 @@ Required properties:
- compatible :
"ti,lp8860"
- reg : I2C slave address
- - label : Used for naming LEDs
+ - #address-cells : 1
+ - #size-cells : 0
Optional properties:
- enable-gpios : gpio pin to enable (active high)/disable the device.
- vled-supply : LED supply
+Required child properties:
+ - reg : 0
+
+Optional child properties:
+ - label : see Documentation/devicetree/bindings/leds/common.txt
+
Example:
led-controller@2d {
compatible = "ti,lp8860";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x2d>;
- label = "display_cluster";
enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
vled-supply = <&vbatt>;
+
+ led@0 {
+ reg = <0>;
+ label = "white:display_cluster";
+ };
}
For more product information please see the link below:
--
2.15.0.124.g7668cbc60
^ permalink raw reply related
* [PATCH v4 3/6] leds: lp8860: Update the dt parsing for LED labeling
From: Dan Murphy @ 2017-12-12 22:01 UTC (permalink / raw)
To: robh+dt, mark.rutland, rpurdie, jacek.anaszewski, pavel
Cc: devicetree, linux-kernel, linux-leds, Dan Murphy
In-Reply-To: <20171212220143.31210-1-dmurphy@ti.com>
Update the DT parsing for the label node so that
the label is retrieved from the device child as
opposed to being part of the parent.
This will align this driver with the LED
binding documentation
Documentation/devicetree/bindings/leds/common.txt
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
v4 - Fix checkpatch warning for code indentation - https://patchwork.kernel.org/patch/10108157/
v3 - Changed the label generation to pull the name from the i2c device id
as opposed to pulling the id from the parent dt node since that will just be
led-controller - https://patchwork.kernel.org/patch/10093753/
v2 - no changes
drivers/leds/leds-lp8860.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/leds/leds-lp8860.c b/drivers/leds/leds-lp8860.c
index 3e70775a2d54..46578fbc36be 100644
--- a/drivers/leds/leds-lp8860.c
+++ b/drivers/leds/leds-lp8860.c
@@ -22,6 +22,7 @@
#include <linux/of_gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/slab.h>
+#include <uapi/linux/uleds.h>
#define LP8860_DISP_CL1_BRT_MSB 0x00
#define LP8860_DISP_CL1_BRT_LSB 0x01
@@ -86,8 +87,6 @@
#define LP8860_CLEAR_FAULTS 0x01
-#define LP8860_DISP_LED_NAME "display_cluster"
-
/**
* struct lp8860_led -
* @lock - Lock for reading/writing the device
@@ -107,7 +106,7 @@ struct lp8860_led {
struct regmap *eeprom_regmap;
struct gpio_desc *enable_gpio;
struct regulator *regulator;
- const char *label;
+ char label[LED_MAX_NAME_SIZE];
};
struct lp8860_eeprom_reg {
@@ -365,19 +364,21 @@ static int lp8860_probe(struct i2c_client *client,
int ret;
struct lp8860_led *led;
struct device_node *np = client->dev.of_node;
+ struct device_node *child_node;
+ const char *name;
led = devm_kzalloc(&client->dev, sizeof(*led), GFP_KERNEL);
if (!led)
return -ENOMEM;
- led->label = LP8860_DISP_LED_NAME;
-
- if (client->dev.of_node) {
- ret = of_property_read_string(np, "label", &led->label);
- if (ret) {
- dev_err(&client->dev, "Missing label in dt\n");
- return -EINVAL;
- }
+ for_each_available_child_of_node(np, child_node) {
+ ret = of_property_read_string(child_node, "label", &name);
+ if (!ret)
+ snprintf(led->label, sizeof(led->label), "%s:%s",
+ id->name, name);
+ else
+ snprintf(led->label, sizeof(led->label),
+ "%s::display_cluster", id->name);
}
led->enable_gpio = devm_gpiod_get_optional(&client->dev,
--
2.15.0.124.g7668cbc60
^ permalink raw reply related
* [PATCH v4 4/6] dt: bindings: lp8860: Add trigger binding to the lp8860
From: Dan Murphy @ 2017-12-12 22:01 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
rpurdie-Fm38FmjxZ/leoWH0uzbU5w,
jacek.anaszewski-Re5JQEeQqe8AvxtiuMwx3w, pavel-+ZI9xUNit7I
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-leds-u79uwXL29TY76Z2rM5mHXA, Dan Murphy
In-Reply-To: <20171212220143.31210-1-dmurphy-l0cyMroinI0@public.gmane.org>
Add a default trigger optional node to the child node.
This will allow the driver to set the trigger for a backlight.
Signed-off-by: Dan Murphy <dmurphy-l0cyMroinI0@public.gmane.org>
---
v4 - No changes
v3 - Removed optional and rebased - https://patchwork.kernel.org/patch/10093755/
v2 - Moved binding changes to first patch in the series.
Documentation/devicetree/bindings/leds/leds-lp8860.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/leds/leds-lp8860.txt b/Documentation/devicetree/bindings/leds/leds-lp8860.txt
index c3d64ade1e26..cdb9e12bd0aa 100644
--- a/Documentation/devicetree/bindings/leds/leds-lp8860.txt
+++ b/Documentation/devicetree/bindings/leds/leds-lp8860.txt
@@ -21,6 +21,8 @@ Required child properties:
Optional child properties:
- label : see Documentation/devicetree/bindings/leds/common.txt
+ - linux,default-trigger :
+ see Documentation/devicetree/bindings/leds/common.txt
Example:
@@ -35,6 +37,7 @@ led-controller@2d {
led@0 {
reg = <0>;
label = "white:display_cluster";
+ linux,default-trigger = "backlight";
};
}
--
2.15.0.124.g7668cbc60
--
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^ permalink raw reply related
* [PATCH v4 5/6] leds: lp8860: Add DT parsing to retrieve the trigger node
From: Dan Murphy @ 2017-12-12 22:01 UTC (permalink / raw)
To: robh+dt, mark.rutland, rpurdie, jacek.anaszewski, pavel
Cc: devicetree, linux-kernel, linux-leds, Dan Murphy
In-Reply-To: <20171212220143.31210-1-dmurphy@ti.com>
Add the ability to parse the DT and set the default
trigger mode for the LED.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
v4 - No changes
v3 - no changes - https://patchwork.kernel.org/patch/10093751/
v2 - no changes
drivers/leds/leds-lp8860.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/leds/leds-lp8860.c b/drivers/leds/leds-lp8860.c
index 46578fbc36be..bb1d7bbc928c 100644
--- a/drivers/leds/leds-lp8860.c
+++ b/drivers/leds/leds-lp8860.c
@@ -372,6 +372,10 @@ static int lp8860_probe(struct i2c_client *client,
return -ENOMEM;
for_each_available_child_of_node(np, child_node) {
+ led->led_dev.default_trigger = of_get_property(child_node,
+ "linux,default-trigger",
+ NULL);
+
ret = of_property_read_string(child_node, "label", &name);
if (!ret)
snprintf(led->label, sizeof(led->label), "%s:%s",
--
2.15.0.124.g7668cbc60
^ permalink raw reply related
* [PATCH v4 6/6] leds: lp8860: Various fixes to align with LED framework
From: Dan Murphy @ 2017-12-12 22:01 UTC (permalink / raw)
To: robh+dt, mark.rutland, rpurdie, jacek.anaszewski, pavel
Cc: devicetree, linux-kernel, linux-leds, Dan Murphy
In-Reply-To: <20171212220143.31210-1-dmurphy@ti.com>
Update the driver to conform with the LED framework.
Use devm_led_classdev_register
Destroy mutex on exit
Remove dependency on CONFIG_OF in the driver and move
to the Kconfig
Update the MODULE_LICENSE to GPL v2
Remove setting of MAX brightness as the LED framework
does this.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
v4 - No changes
v3 - no changes - https://patchwork.kernel.org/patch/10093747/
v2 - no changes
drivers/leds/Kconfig | 2 +-
drivers/leds/leds-lp8860.c | 13 +++++--------
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 318a28fd58fe..ac4d9d8bf96b 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -347,7 +347,7 @@ config LEDS_LP8788
config LEDS_LP8860
tristate "LED support for the TI LP8860 4 channel LED driver"
- depends on LEDS_CLASS && I2C
+ depends on LEDS_CLASS && I2C && OF
select REGMAP_I2C
help
If you say yes here you get support for the TI LP8860 4 channel
diff --git a/drivers/leds/leds-lp8860.c b/drivers/leds/leds-lp8860.c
index bb1d7bbc928c..c7716f774431 100644
--- a/drivers/leds/leds-lp8860.c
+++ b/drivers/leds/leds-lp8860.c
@@ -399,7 +399,6 @@ static int lp8860_probe(struct i2c_client *client,
led->client = client;
led->led_dev.name = led->label;
- led->led_dev.max_brightness = LED_FULL;
led->led_dev.brightness_set_blocking = lp8860_brightness_set;
mutex_init(&led->lock);
@@ -426,7 +425,7 @@ static int lp8860_probe(struct i2c_client *client,
if (ret)
return ret;
- ret = led_classdev_register(&client->dev, &led->led_dev);
+ ret = devm_led_classdev_register(&client->dev, &led->led_dev);
if (ret) {
dev_err(&client->dev, "led register err: %d\n", ret);
return ret;
@@ -440,8 +439,6 @@ static int lp8860_remove(struct i2c_client *client)
struct lp8860_led *led = i2c_get_clientdata(client);
int ret;
- led_classdev_unregister(&led->led_dev);
-
if (led->enable_gpio)
gpiod_direction_output(led->enable_gpio, 0);
@@ -452,6 +449,8 @@ static int lp8860_remove(struct i2c_client *client)
"Failed to disable regulator\n");
}
+ mutex_destroy(&led->lock);
+
return 0;
}
@@ -461,18 +460,16 @@ static const struct i2c_device_id lp8860_id[] = {
};
MODULE_DEVICE_TABLE(i2c, lp8860_id);
-#ifdef CONFIG_OF
static const struct of_device_id of_lp8860_leds_match[] = {
{ .compatible = "ti,lp8860", },
{},
};
MODULE_DEVICE_TABLE(of, of_lp8860_leds_match);
-#endif
static struct i2c_driver lp8860_driver = {
.driver = {
.name = "lp8860",
- .of_match_table = of_match_ptr(of_lp8860_leds_match),
+ .of_match_table = of_lp8860_leds_match,
},
.probe = lp8860_probe,
.remove = lp8860_remove,
@@ -482,4 +479,4 @@ module_i2c_driver(lp8860_driver);
MODULE_DESCRIPTION("Texas Instruments LP8860 LED driver");
MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
--
2.15.0.124.g7668cbc60
^ permalink raw reply related
* Re: [RFC 0/5] Add I3C subsystem
From: Wolfram Sang @ 2017-12-12 22:01 UTC (permalink / raw)
To: Boris Brezillon
Cc: linux-i2c, Jonathan Corbet, linux-doc, Greg Kroah-Hartman,
Arnd Bergmann, Przemyslaw Sroka, Arkadiusz Golec, Alan Douglas,
Bartosz Folta, Damian Kos, Alicja Jurasik-Urbaniak, Jan Kotas,
Cyprian Wronka, Alexandre Belloni, Thomas Petazzoni,
Nishanth Menon, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell
In-Reply-To: <20171212205832.4b317b21@bbrezillon>
[-- Attachment #1: Type: text/plain, Size: 133 bytes --]
> MIPI has opened the I3C spec [1], it can be downloaded here [2].
Wow, that's good news. And so fast. Congrats and thanks a lot!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH v3 3/8] PCI: brcmstb: Add Broadcom STB PCIe host controller driver
From: Bjorn Helgaas @ 2017-12-12 22:16 UTC (permalink / raw)
To: Jim Quinlan
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bjorn Helgaas,
Catalin Marinas, Will Deacon, Rob Herring, Brian Norris,
Russell King, Robin Murphy, Christoph Hellwig, Florian Fainelli,
Jonas Gorski, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-pci-u79uwXL29TY76Z2rM5mHXA, Kevin Cernekee, Ralf Baechle,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Gregory Fong,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1510697532-32828-4-git-send-email-jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Tue, Nov 14, 2017 at 05:12:07PM -0500, Jim Quinlan wrote:
> This commit adds the basic Broadcom STB PCIe controller. Missing is
> the ability to process MSI and also handle dma-ranges for inbound
> memory accesses. These two functionalities are added in subsequent
> commits.
>
> The PCIe block contains an MDIO interface. This is a local interface
> only accessible by the PCIe controller. It cannot be used or shared
> by any other HW. As such, the small amount of code for this
> controller is included in this driver as there is little upside to put
> it elsewhere.
>
> Signed-off-by: Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> drivers/pci/host/Kconfig | 9 +
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host/pcie-brcmstb.c | 1124 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1134 insertions(+)
> create mode 100644 drivers/pci/host/pcie-brcmstb.c
>
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index b868803..751463e 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -220,4 +220,13 @@ config VMD
> To compile this driver as a module, choose M here: the
> module will be called vmd.
>
> +config PCIE_BRCMSTB
> + tristate "Broadcom Brcmstb PCIe platform host driver"
> + depends on ARCH_BRCMSTB || BMIPS_GENERIC
> + depends on OF
> + depends on SOC_BRCMSTB
> + default ARCH_BRCMSTB || BMIPS_GENERIC
> + help
> + Adds support for Broadcom Settop Box PCIe host controller.
> +
> endmenu
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index 1238278..a8b9923 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -21,6 +21,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
> obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> obj-$(CONFIG_VMD) += vmd.o
> +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
>
> # The following drivers are for devices that use the generic ACPI
> # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/host/pcie-brcmstb.c b/drivers/pci/host/pcie-brcmstb.c
> new file mode 100644
> index 0000000..d8a8f7a
> --- /dev/null
> +++ b/drivers/pci/host/pcie-brcmstb.c
> @@ -0,0 +1,1124 @@
> +/*
> + * Copyright (C) 2009 - 2017 Broadcom
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/compiler.h>
> +#include <linux/delay.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> +#include <linux/irqdomain.h>
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/log2.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_platform.h>
> +#include <linux/pci.h>
> +#include <linux/printk.h>
> +#include <linux/sizes.h>
> +#include <linux/slab.h>
> +#include <soc/brcmstb/memory_api.h>
> +#include <linux/string.h>
> +#include <linux/types.h>
> +
> +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
> +#define BRCM_PCIE_CAP_REGS 0x00ac
Add a blank line before multi-line comments.
> +/*
> + * Broadcom Settop Box PCIE Register Offsets. The names are from
> + * the chip's RDB and we use them here so that a script can correlate
> + * this code and the RDB to prevent discrepancies.
Use "PCIe" capitalization in English text and messages.
> + */
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
> +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
> +#define PCIE_RC_DL_MDIO_ADDR 0x1100
> +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
> +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
> +#define PCIE_MISC_MISC_CTRL 0x4008
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
> +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
> +#define PCIE_MISC_PCIE_CTRL 0x4064
> +#define PCIE_MISC_PCIE_STATUS 0x4068
> +#define PCIE_MISC_REVISION 0x406c
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> +#define PCIE_INTR2_CPU_BASE 0x4300
> +
> +/*
> + * Broadcom Settop Box PCIE Register Field shift and mask info. The
> + * names are from the chip's RDB and we use them here so that a script
> + * can correlate this code and the RDB to prevent discrepancies.
> + */
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2
> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
> +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
> +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
> +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
> +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
> +
> +#define BRCM_NUM_PCIE_OUT_WINS 0x4
> +#define BRCM_MAX_SCB 0x4
> +
> +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
> +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
> +
> +#define BURST_SIZE_128 0
> +#define BURST_SIZE_256 1
> +#define BURST_SIZE_512 2
> +
> +/* Offsets from PCIE_INTR2_CPU_BASE */
> +#define STATUS 0x0
> +#define SET 0x4
> +#define CLR 0x8
> +#define MASK_STATUS 0xc
> +#define MASK_SET 0x10
> +#define MASK_CLR 0x14
> +
> +#define PCIE_BUSNUM_SHIFT 20
> +#define PCIE_SLOT_SHIFT 15
> +#define PCIE_FUNC_SHIFT 12
> +
> +#if defined(__BIG_ENDIAN)
> +#define DATA_ENDIAN 2 /* PCIe->DDR inbound accesses */
> +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound accesses */
> +#else
> +#define DATA_ENDIAN 0
> +#define MMIO_ENDIAN 0
> +#endif
> +
> +#define MDIO_PORT0 0x0
> +#define MDIO_DATA_MASK 0x7fffffff
> +#define MDIO_DATA_SHIFT 0x0
> +#define MDIO_PORT_MASK 0xf0000
> +#define MDIO_PORT_SHIFT 0x16
> +#define MDIO_REGAD_MASK 0xffff
> +#define MDIO_REGAD_SHIFT 0x0
> +#define MDIO_CMD_MASK 0xfff00000
> +#define MDIO_CMD_SHIFT 0x14
> +#define MDIO_CMD_READ 0x1
> +#define MDIO_CMD_WRITE 0x0
> +#define MDIO_DATA_DONE_MASK 0x80000000
> +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
> +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
> +#define SSC_REGS_ADDR 0x1100
> +#define SET_ADDR_OFFSET 0x1f
> +#define SSC_CNTL_OFFSET 0x2
> +#define SSC_CNTL_OVRD_EN_MASK 0x8000
> +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
> +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
> +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
> +#define SSC_STATUS_OFFSET 0x1
> +#define SSC_STATUS_SSC_MASK 0x400
> +#define SSC_STATUS_SSC_SHIFT 0xa
> +#define SSC_STATUS_PLL_LOCK_MASK 0x800
> +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
> +
> +#define IDX_ADDR(pcie) \
> + ((pcie)->reg_offsets[EXT_CFG_INDEX])
> +#define DATA_ADDR(pcie) \
> + ((pcie)->reg_offsets[EXT_CFG_DATA])
> +#define PCIE_RGR1_SW_INIT_1(pcie) \
> + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
> +
> +enum {
> + RGR1_SW_INIT_1,
> + EXT_CFG_INDEX,
> + EXT_CFG_DATA,
> +};
> +
> +enum {
> + RGR1_SW_INIT_1_INIT_MASK,
> + RGR1_SW_INIT_1_INIT_SHIFT,
> + RGR1_SW_INIT_1_PERST_MASK,
> + RGR1_SW_INIT_1_PERST_SHIFT,
> +};
> +
> +enum pcie_type {
> + BCM7425,
> + BCM7435,
> + GENERIC,
> + BCM7278,
> +};
> +
> +struct brcm_window {
> + dma_addr_t pcie_addr;
> + phys_addr_t cpu_addr;
> + dma_addr_t size;
> +};
> +
> +/* Internal PCIe Host Controller Information.*/
> +struct brcm_pcie {
> + struct list_head list;
> + struct device *dev;
> + void __iomem *base;
> + struct list_head resources;
> + int irq;
> + struct clk *clk;
> + struct pci_bus *root_bus;
> + struct device_node *dn;
> + int id;
> + bool suspended;
> + int num_out_wins;
> + bool ssc;
> + int gen;
> + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
> + unsigned int rev;
> + const int *reg_offsets;
> + const int *reg_field_info;
> + enum pcie_type type;
> +};
> +
> +struct pcie_cfg_data {
> + const int *reg_field_info;
> + const int *offsets;
> + const enum pcie_type type;
> +};
> +
> +static const int pcie_reg_field_info[] = {
> + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
> + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
> +};
> +
> +static const int pcie_reg_field_info_bcm7278[] = {
> + [RGR1_SW_INIT_1_INIT_MASK] = 0x1,
> + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x0,
> +};
> +
> +static const int pcie_offset_bcm7425[] = {
> + [RGR1_SW_INIT_1] = 0x8010,
> + [EXT_CFG_INDEX] = 0x8300,
> + [EXT_CFG_DATA] = 0x8304,
> +};
> +
> +static const struct pcie_cfg_data bcm7425_cfg = {
> + .reg_field_info = pcie_reg_field_info,
> + .offsets = pcie_offset_bcm7425,
> + .type = BCM7425,
> +};
> +
> +static const int pcie_offsets[] = {
> + [RGR1_SW_INIT_1] = 0x9210,
> + [EXT_CFG_INDEX] = 0x9000,
> + [EXT_CFG_DATA] = 0x9004,
> +};
> +
> +static const struct pcie_cfg_data bcm7435_cfg = {
> + .reg_field_info = pcie_reg_field_info,
> + .offsets = pcie_offsets,
> + .type = BCM7435,
> +};
> +
> +static const struct pcie_cfg_data generic_cfg = {
> + .reg_field_info = pcie_reg_field_info,
> + .offsets = pcie_offsets,
> + .type = GENERIC,
> +};
> +
> +static const int pcie_offset_bcm7278[] = {
> + [RGR1_SW_INIT_1] = 0xc010,
> + [EXT_CFG_INDEX] = 0x9000,
> + [EXT_CFG_DATA] = 0x9004,
> +};
> +
> +static const struct pcie_cfg_data bcm7278_cfg = {
> + .reg_field_info = pcie_reg_field_info_bcm7278,
> + .offsets = pcie_offset_bcm7278,
> + .type = BCM7278,
> +};
> +
> +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> + int where);
> +
> +static struct pci_ops brcm_pcie_ops = {
> + .map_bus = brcm_pcie_map_conf,
> + .read = pci_generic_config_read,
> + .write = pci_generic_config_write,
> +};
> +
> +#if defined(CONFIG_MIPS)
> +/* Broadcom MIPs HW implicitly does the swapping if necessary */
> +#define bcm_readl(a) __raw_readl(a)
> +#define bcm_writel(d, a) __raw_writel(d, a)
> +#define bcm_readw(a) __raw_readw(a)
> +#define bcm_writew(d, a) __raw_writew(d, a)
> +#else
> +#define bcm_readl(a) readl(a)
> +#define bcm_writel(d, a) writel(d, a)
> +#define bcm_readw(a) readw(a)
> +#define bcm_writew(d, a) writew(d, a)
> +#endif
> +
> +/*
> + * These macros are designed to sxtract/insert fields to host controller's
> + * register set.
s/are designed to s/ e/ (I assume they actually *do* extract/insert)
> + */
> +#define RD_FLD(base, reg, field) \
> + rd_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
> +#define WR_FLD(base, reg, field, val) \
> + wr_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
> +#define WR_FLD_RB(base, reg, field, val) \
> + wr_fld_rb(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
> +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
> + wr_fld(base + reg + off, reg##_##field##_MASK, \
> + reg##_##field##_SHIFT, val)
> +#define EXTRACT_FIELD(val, reg, field) \
> + ((val & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
> +#define INSERT_FIELD(val, reg, field, field_val) \
> + ((val & ~reg##_##field##_MASK) | \
> + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
> +
> +static struct list_head brcm_pcie = LIST_HEAD_INIT(brcm_pcie);
> +static phys_addr_t scb_size[BRCM_MAX_SCB];
> +static int num_memc;
> +static DEFINE_MUTEX(brcm_pcie_lock);
> +
> +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
> +{
> + return (bcm_readl(p) & mask) >> shift;
> +}
> +
> +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
> +{
> + u32 reg = bcm_readl(p);
> +
> + reg = (reg & ~mask) | ((val << shift) & mask);
> + bcm_writel(reg, p);
> +}
> +
> +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
> +{
> + wr_fld(p, mask, shift, val);
> + (void)bcm_readl(p);
> +}
> +
> +static const char *link_speed_to_str(int s)
> +{
> + switch (s) {
> + case 1:
> + return "2.5";
> + case 2:
> + return "5.0";
> + case 3:
> + return "8.0";
> + default:
> + break;
> + }
> + return "???";
> +}
> +
> +/*
> + * The roundup_pow_of_two() from log2.h invokes
> + * __roundup_pow_of_two(unsigned long), but we really need a
> + * such a function to take a native u64 since unsigned long
> + * is 32 bits on some configurations. So we provide this helper
> + * function below.
> + */
> +static u64 roundup_pow_of_two_64(u64 n)
> +{
> + return 1ULL << fls64(n - 1);
> +}
> +
> +/*
> + * This is to convert the size of the inbound bar region to the
> + * non-liniear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
s/bar/BAR/ (This doesn't sound like a BAR in the PCI spec sense, but if
that's what you call it, might as well spell it as the acronym)
s/non-liniear/non-linear/
> + */
> +int encode_ibar_size(u64 size)
> +{
> + int log2_in = ilog2(size);
> +
> + if (log2_in >= 12 && log2_in <= 15)
> + /* Covers 4KB to 32KB (inclusive) */
> + return (log2_in - 12) + 0x1c;
> + else if (log2_in >= 16 && log2_in <= 37)
> + /* Covers 64KB to 32GB, (inclusive) */
> + return log2_in - 15;
> + /* Something is awry so disable */
> + return 0;
> +}
> +
> +static u32 mdio_form_pkt(int port, int regad, int cmd)
> +{
> + u32 pkt = 0;
> +
> + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
> + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
> + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
> +
> + return pkt;
> +}
> +
> +/* negative return value indicates error */
> +static int mdio_read(void __iomem *base, u8 port, u8 regad)
> +{
> + int tries;
> + u32 data;
> +
> + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
> + base + PCIE_RC_DL_MDIO_ADDR);
> + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> +
> + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
> + udelay(10);
> + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> + }
> +
> + return MDIO_RD_DONE(data)
> + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
> + : -EIO;
> +}
> +
> +/* negative return value indicates error */
> +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
> +{
> + int tries;
> + u32 data;
> +
> + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
> + base + PCIE_RC_DL_MDIO_ADDR);
> + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
> + base + PCIE_RC_DL_MDIO_WR_DATA);
> +
> + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
> + udelay(10);
> + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> + }
> +
> + return MDIO_WT_DONE(data) ? 0 : -EIO;
> +}
> +
> +/* configures device for ssc mode; negative return value indicates error */
I guess "ssc" means Spread Spectrum Clocking? Maybe spell out the
first occurrence and spell as acronym in English text?
> +static int set_ssc(void __iomem *base)
> +{
> + int tmp;
> + u16 wrdata;
> + int pll, ssc;
> +
> + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
> + if (tmp < 0)
> + return tmp;
> +
> + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
> + if (tmp < 0)
> + return tmp;
> +
> + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
> + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
> + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
> + if (tmp < 0)
> + return tmp;
> +
> + usleep_range(1000, 2000);
> + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
> + if (tmp < 0)
> + return tmp;
> +
> + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
> + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
> +
> + return (ssc && pll) ? 0 : -EIO;
> +}
> +
> +/* limits operation to a specific generation (1, 2, or 3) */
> +static void set_gen(void __iomem *base, int gen)
> +{
> + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> +
> + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
> + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> +
> + lnkctl2 = (lnkctl2 & ~0xf) | gen;
> + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> +}
> +
> +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
> + unsigned int win, phys_addr_t cpu_addr,
> + dma_addr_t pcie_addr, dma_addr_t size)
> +{
> + void __iomem *base = pcie->base;
> + phys_addr_t cpu_addr_mb, limit_addr_mb;
> + u32 tmp;
> +
> + /* Set the base of the pcie_addr window */
> + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
> + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
> + bcm_writel(upper_32_bits(pcie_addr),
> + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
> +
> + cpu_addr_mb = cpu_addr >> 20;
> + limit_addr_mb = (cpu_addr + size - 1) >> 20;
> +
> + /* Write the addr base low register */
> + WR_FLD_WITH_OFFSET(base, (win * 4),
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> + BASE, cpu_addr_mb);
> + /* Write the addr limit low register */
> + WR_FLD_WITH_OFFSET(base, (win * 4),
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> + LIMIT, limit_addr_mb);
> +
> + if (pcie->type != BCM7435 && pcie->type != BCM7425) {
> + /* Write the cpu addr high register */
> + tmp = (u32)(cpu_addr_mb >>
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> + WR_FLD_WITH_OFFSET(base, (win * 8),
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
> + BASE, tmp);
> + /* Write the cpu limit high register */
> + tmp = (u32)(limit_addr_mb >>
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> + WR_FLD_WITH_OFFSET(base, (win * 8),
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
> + LIMIT, tmp);
> + }
> +}
> +
> +/* Configuration space read/write support */
> +static int cfg_index(int busnr, int devfn, int reg)
> +{
> + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
> + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
> + | (busnr << PCIE_BUSNUM_SHIFT)
> + | (reg & ~3);
> +}
> +
> +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> +
> + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
> +}
> +
> +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
> + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
> +
> + return (dla && plu) ? true : false;
> +}
> +
> +static bool brcm_pcie_valid_device(struct brcm_pcie *pcie, struct pci_bus *bus,
> + int dev)
> +{
> + if (pci_is_root_bus(bus)) {
> + if (dev > 0)
> + return false;
> + } else {
> + /* If there is no link, then there is no device */
> + if (!brcm_pcie_link_up(pcie))
> + return false;
This is racy, since the link can go down after you check but before
you do the config access. I assume your hardware can deal with a
config access that targets a link that is down?
> + }
> +
> + return true;
> +}
> +
> +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> + int where)
> +{
> + struct brcm_pcie *pcie = bus->sysdata;
> + void __iomem *base = pcie->base;
> + int idx;
> +
> + if (!brcm_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
> + return NULL;
> +
> + /* Accesses to the RC go right to the RC registers */
> + if (pci_is_root_bus(bus))
> + return base + where;
> +
> + /* For devices, write to the config space index register */
> + idx = cfg_index(bus->number, devfn, where);
> + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
> + return base + DATA_ADDR(pcie) + (where & 0x3);
I guess this is protected by a higher-level config access lock?
> +}
> +
> +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
> + unsigned int val)
> +{
> + unsigned int offset;
> + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
> + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
> +
> + if (pcie->type != BCM7278) {
> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
> + val);
> + } else if (of_machine_is_compatible("brcm,bcm7278a0")) {
> + /*
> + * The two PCIe instances on 7278a0 are not even consistent with
> + * respect to each other for internal offsets, here we offset
> + * by 0x14000 + RGR1_SW_INIT_1's relative offset to account for
> + * that.
> + */
> + offset = pcie->id ? 0x14010 : pcie->reg_offsets[RGR1_SW_INIT_1];
> + wr_fld_rb(pcie->base + offset, mask, shift, val);
> + } else {
> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
> + val);
> + }
> +}
> +
> +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
> + unsigned int val)
> +{
> + if (pcie->type != BCM7278)
> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
> + PCIE_RGR1_SW_INIT_1_PERST_MASK,
> + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
> + else
> + /* Assert = 0, de-assert = 1 on 7278 */
> + WR_FLD_RB(pcie->base, PCIE_MISC_PCIE_CTRL, PCIE_PERSTB, !val);
> +}
> +
> +static int brcm_pcie_add_controller(struct brcm_pcie *pcie)
> +{
> + mutex_lock(&brcm_pcie_lock);
> + list_add_tail(&pcie->list, &brcm_pcie);
> + mutex_unlock(&brcm_pcie_lock);
> +
> + return 0;
> +}
> +
> +static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
> +{
> + struct list_head *pos, *q;
> + struct brcm_pcie *tmp;
> +
> + mutex_lock(&brcm_pcie_lock);
> + list_for_each_safe(pos, q, &brcm_pcie) {
> + tmp = list_entry(pos, struct brcm_pcie, list);
> + if (tmp == pcie) {
> + list_del(pos);
> + if (list_empty(&brcm_pcie))
> + num_memc = 0;
> + break;
> + }
> + }
> + mutex_unlock(&brcm_pcie_lock);
I'm missing something. I don't see that num_memc is ever set to
anything *other* than zero.
This pattern of keeping a list of controllers is highly unusual and
needs some explanation.
> +}
> +
> +static int brcm_pcie_parse_request_of_pci_ranges(struct brcm_pcie *pcie)
> +{
> + struct resource_entry *win;
> + int ret;
> +
> + ret = of_pci_get_host_bridge_resources(pcie->dn, 0, 0xff,
> + &pcie->resources, NULL);
> + if (ret) {
> + dev_err(pcie->dev, "failed to get host resources\n");
> + return ret;
> + }
> +
> + resource_list_for_each_entry(win, &pcie->resources) {
> + struct resource *parent, *res = win->res;
> + dma_addr_t offset = (dma_addr_t)win->offset;
> +
> + if (resource_type(res) == IORESOURCE_IO) {
> + parent = &ioport_resource;
> + } else if (resource_type(res) == IORESOURCE_MEM) {
> + if (pcie->num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
> + dev_err(pcie->dev, "too many outbound wins\n");
> + return -EINVAL;
> + }
> + pcie->out_wins[pcie->num_out_wins].cpu_addr
> + = (phys_addr_t)res->start;
> + pcie->out_wins[pcie->num_out_wins].pcie_addr
> + = (dma_addr_t)(res->start
> + - (phys_addr_t)offset);
> + pcie->out_wins[pcie->num_out_wins].size
> + = (dma_addr_t)(res->end - res->start + 1);
> + pcie->num_out_wins++;
> + parent = &iomem_resource;
> + } else {
> + continue;
> + }
> +
> + ret = devm_request_resource(pcie->dev, parent, res);
> + if (ret) {
> + dev_err(pcie->dev, "failed to get res %pR\n", res);
> + return ret;
> + }
> + }
> + return 0;
> +}
> +
> +static int brcm_pcie_setup(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> + unsigned int scb_size_val;
> + u64 rc_bar2_size = 0, rc_bar2_offset = 0, total_mem_size = 0;
Unnecessary initializations (at least of rc_bar2_size, I didn't check
the rest).
Add
struct device *dev = pcie->dev;
then use it below.
> + u32 tmp, burst;
> + int i, j, ret, limit;
> + u16 nlw, cls, lnksta;
> + bool ssc_good = false;
> +
> + /* reset the bridge and the endpoint device */
> + /* field: PCIE_BRIDGE_SW_INIT = 1 */
Not sure what these "field: ..." comments mean. Are they for some
automated tool? To a human, it looks like they repeat what the code
does.
> + brcm_pcie_bridge_sw_init_set(pcie, 1);
> +
> + /* field: PCIE_SW_PERST = 1, on 7278, we start de-asserted already */
> + if (pcie->type != BCM7278)
> + brcm_pcie_perst_set(pcie, 1);
> +
> + usleep_range(100, 200);
> +
> + /* take the bridge out of reset */
> + /* field: PCIE_BRIDGE_SW_INIT = 0 */
> + brcm_pcie_bridge_sw_init_set(pcie, 0);
> +
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> + /* wait for serdes to be stable */
> + usleep_range(100, 200);
> +
> + /* Grab the PCIe hw revision number */
> + tmp = bcm_readl(base + PCIE_MISC_REVISION);
> + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
> +
> + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
> + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
> + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
> + burst = (pcie->type == GENERIC || pcie->type == BCM7278)
> + ? BURST_SIZE_512 : BURST_SIZE_256;
> + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE, burst);
> + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
> +
> + /*
> + * Set up inbound memory view for the EP (called RC_BAR2,
> + * not to be confused with the BARs that are advertised by
> + * the EP).
> + */
> + for (i = 0; i < num_memc; i++)
> + total_mem_size += scb_size[i];
> +
> + /*
> + * The PCIe host controller by design must set the inbound
> + * viewport to be a contiguous arrangement of all of the
> + * system's memory. In addition, its size mut be a power of
> + * two. To further complicate matters, the viewport must
> + * start on a pcie-address that is aligned on a multiple of its
> + * size. If a portion of the viewport does not represent
> + * system memory -- e.g. 3GB of memory requires a 4GB viewport
> + * -- we can map the outbound memory in or after 3GB and even
> + * though the viewport will overlap the outbound memory the
> + * controller will know to send outbound memory downstream and
> + * everything else upstream.
> + */
> + rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
> +
> + /*
> + * Set simple configuration based on memory sizes
> + * only. We always start the viewport at address 0.
> + */
> + rc_bar2_offset = 0;
> +
> + tmp = lower_32_bits(rc_bar2_offset);
> + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> + encode_ibar_size(rc_bar2_size));
> + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
> + bcm_writel(upper_32_bits(rc_bar2_offset),
> + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
> +
> + /* field: SCB0_SIZE, default = 0xf (1 GB) */
> + scb_size_val = scb_size[0]
> + ? ilog2(scb_size[0]) - 15 : 0xf;
> + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
> +
> + /* field: SCB1_SIZE, default = 0xf (1 GB) */
> + if (num_memc > 1) {
> + scb_size_val = scb_size[1]
> + ? ilog2(scb_size[1]) - 15 : 0xf;
> + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB1_SIZE, scb_size_val);
> + }
> +
> + /* field: SCB2_SIZE, default = 0xf (1 GB) */
> + if (num_memc > 2) {
> + scb_size_val = scb_size[2]
> + ? ilog2(scb_size[2]) - 15 : 0xf;
> + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB2_SIZE, scb_size_val);
> + }
> +
> + /* disable the PCIe->GISB memory window (RC_BAR1) */
> + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
> +
> + /* disable the PCIe->SCB memory window (RC_BAR3) */
> + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
> +
> + if (!pcie->suspended) {
> + /* clear any interrupts we find on boot */
> + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
> + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
> + }
> +
> + /* Mask all interrupts since we are not handling any yet */
> + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
> + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
> +
> + if (pcie->gen)
> + set_gen(base, pcie->gen);
> +
> + /* take the EP device out of reset */
> + /* field: PCIE_SW_PERST = 0 */
> + brcm_pcie_perst_set(pcie, 0);
<raises eyebrows> Take the *EP* out of reset? The host controller
driver shouldn't be touching an EP directly. Maybe the comment
doesn't match what the code actually does.
> +
> + /*
> + * Give the RC/EP time to wake up, before trying to configure RC.
> + * Intermittently check status for link-up, up to a total of 100ms
> + * when we don't know if the device is there, and up to 1000ms if
> + * we do know the device is there.
> + */
> + limit = pcie->suspended ? 1000 : 100;
> + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
> + j += i, i = i * 2)
> + msleep(i + j > limit ? limit - j : i);
> +
> + if (!brcm_pcie_link_up(pcie)) {
> + dev_info(pcie->dev, "link down\n");
> + return -ENODEV;
> + }
> +
> + if (!brcm_pcie_rc_mode(pcie)) {
> + dev_err(pcie->dev, "PCIe misconfigured; is in EP mode\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < pcie->num_out_wins; i++)
> + brcm_pcie_set_outbound_win(pcie, i, pcie->out_wins[i].cpu_addr,
> + pcie->out_wins[i].pcie_addr,
> + pcie->out_wins[i].size);
> +
> + /*
> + * For config space accesses on the RC, show the right class for
> + * a PCIe-PCIe bridge (the default setting is to be EP mode).
> + */
> + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
> +
> + if (pcie->ssc) {
> + ret = set_ssc(base);
> + if (ret == 0)
> + ssc_good = true;
> + else
> + dev_err(pcie->dev,
> + "failed attempt to enter ssc mode\n");
> + }
> +
> + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
> + cls = lnksta & PCI_EXP_LNKSTA_CLS;
> + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
> + dev_info(pcie->dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
> + nlw, ssc_good ? "(SSC)" : "(!SSC)");
> +
> + /* PCIe->SCB endian mode for BAR */
> + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
> + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
> + ENDIAN_MODE_BAR2, DATA_ENDIAN);
> +
> + /*
> + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
> + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
> + */
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
> +
> + return 0;
> +}
> +
> +static void enter_l23(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> + int tries, l23;
> +
> + /* assert request for L23 */
> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
> + /* poll L23 status */
> + for (tries = 0, l23 = 0; tries < 1000 && !l23; tries++)
> + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> + if (!l23)
> + dev_err(pcie->dev, "failed to enter L23\n");
What does "L23" mean? Some power management thing?
> +}
> +
> +static void turn_off(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> +
> + if (brcm_pcie_link_up(pcie))
> + enter_l23(pcie);
> + /* Reset endpoint device */
> + brcm_pcie_perst_set(pcie, 1);
> + /* deassert request for L23 in case it was asserted */
> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
> + /* SERDES_IDDQ = 1 */
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
> + /* Shutdown PCIe bridge */
> + brcm_pcie_bridge_sw_init_set(pcie, 1);
> +}
> +
> +static int brcm_pcie_suspend(struct device *dev)
> +{
> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> +
> + turn_off(pcie);
> + clk_disable_unprepare(pcie->clk);
> + pcie->suspended = true;
> +
> + return 0;
> +}
> +
> +static int brcm_pcie_resume(struct device *dev)
> +{
> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> + void __iomem *base;
> + int ret;
> +
> + base = pcie->base;
> + clk_prepare_enable(pcie->clk);
> +
> + /* Take bridge out of reset so we can access the SERDES reg */
Some comments above and below spell it "serdes"; here you spell it
"SERDES".
> + brcm_pcie_bridge_sw_init_set(pcie, 0);
> +
> + /* SERDES_IDDQ = 0 */
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> + /* wait for serdes to be stable */
> + usleep_range(100, 200);
> +
> + ret = brcm_pcie_setup(pcie);
> + if (ret)
> + return ret;
> +
> + pcie->suspended = false;
> +
> + return 0;
> +}
> +
> +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
> +{
> + turn_off(pcie);
> + clk_disable_unprepare(pcie->clk);
> + clk_put(pcie->clk);
> + brcm_pcie_remove_controller(pcie);
> +}
> +
> +static int brcm_pcie_remove(struct platform_device *pdev)
> +{
> + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
> +
> + pci_stop_root_bus(pcie->root_bus);
> + pci_remove_root_bus(pcie->root_bus);
> + _brcm_pcie_remove(pcie);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id brcm_pcie_match[] = {
> + { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
> + { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
> + { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
> + { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
> +
> +static int brcm_pcie_probe(struct platform_device *pdev)
> +{
> + struct device_node *dn = pdev->dev.of_node;
> + const struct of_device_id *of_id;
> + const struct pcie_cfg_data *data;
> + int ret;
> + struct brcm_pcie *pcie;
> + struct resource *res;
> + void __iomem *base;
> + u32 tmp;
> + struct pci_host_bridge *bridge;
> + struct pci_bus *child;
> +
> + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
> + if (!bridge)
> + return -ENOMEM;
> +
> + pcie = pci_host_bridge_priv(bridge);
> + INIT_LIST_HEAD(&pcie->resources);
> +
> + of_id = of_match_node(brcm_pcie_match, dn);
> + if (!of_id) {
> + dev_err(&pdev->dev, "failed to look up compatible string\n");
> + return -EINVAL;
> + }
> +
> + if (of_property_read_u32(dn, "dma-ranges", &tmp) == 0) {
> + dev_err(&pdev->dev, "cannot yet handle dma-ranges\n");
> + return -EINVAL;
> + }
> +
> + data = of_id->data;
> + pcie->reg_offsets = data->offsets;
> + pcie->reg_field_info = data->reg_field_info;
> + pcie->type = data->type;
> + pcie->dn = dn;
> + pcie->dev = &pdev->dev;
> +
> + pcie->id = of_get_pci_domain_nr(dn);
Why do you call of_get_pci_domain_nr() directly? No other driver
does.
> + if (pcie->id < 0)
> + return pcie->id;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -EINVAL;
> +
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
> + if (IS_ERR(pcie->clk)) {
> + dev_err(&pdev->dev, "could not get clock\n");
> + pcie->clk = NULL;
> + }
> + pcie->base = base;
> +
> + ret = of_pci_get_max_link_speed(dn);
> + pcie->gen = (ret < 0) ? 0 : ret;
> +
> + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
> +
> + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
> + if (ret == 0)
> + /* keep going, as we don't use this intr yet */
> + dev_warn(pcie->dev, "cannot get pcie interrupt\n");
> + else
> + pcie->irq = ret;
> +
> + ret = brcm_pcie_parse_request_of_pci_ranges(pcie);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(pcie->clk);
> + if (ret) {
> + dev_err(&pdev->dev, "could not enable clock\n");
> + return ret;
> + }
> +
> + ret = brcm_pcie_add_controller(pcie);
> + if (ret)
> + return ret;
> +
> + ret = brcm_pcie_setup(pcie);
> + if (ret)
> + goto fail;
> +
> + list_splice_init(&pcie->resources, &bridge->windows);
> + bridge->dev.parent = &pdev->dev;
> + bridge->busnr = 0;
> + bridge->ops = &brcm_pcie_ops;
> + bridge->sysdata = pcie;
> + bridge->map_irq = of_irq_parse_and_map_pci;
> + bridge->swizzle_irq = pci_common_swizzle;
> +
> + ret = pci_scan_root_bus_bridge(bridge);
> + if (ret < 0) {
> + dev_err(pcie->dev, "Scanning root bridge failed");
> + goto fail;
> + }
> +
> + pci_assign_unassigned_bus_resources(bridge->bus);
> + list_for_each_entry(child, &bridge->bus->children, node)
> + pcie_bus_configure_settings(child);
> + pci_bus_add_devices(bridge->bus);
> + platform_set_drvdata(pdev, pcie);
> + pcie->root_bus = bridge->bus;
> +
> + return 0;
> +
> +fail:
> + _brcm_pcie_remove(pcie);
> + return ret;
> +}
> +
> +static const struct dev_pm_ops brcm_pcie_pm_ops = {
> + .suspend_noirq = brcm_pcie_suspend,
> + .resume_noirq = brcm_pcie_resume,
> +};
> +
> +static struct platform_driver __refdata brcm_pcie_driver = {
Why do you need __refdata? There's only only other occurrence in
drivers/pci, and I'm dubious about that one as well.
> + .probe = brcm_pcie_probe,
> + .remove = brcm_pcie_remove,
> + .driver = {
> + .name = "brcm-pcie",
> + .owner = THIS_MODULE,
> + .of_match_table = brcm_pcie_match,
> + .pm = &brcm_pcie_pm_ops,
> + },
> +};
> +
> +module_platform_driver(brcm_pcie_driver);
> +
> +MODULE_LICENSE("GPL");
Copyright notice above says "GPL v2", which is not the same as the
"GPL" here.
> +MODULE_DESCRIPTION("Broadcom STB PCIE RC driver");
> +MODULE_AUTHOR("Broadcom");
> --
> 1.9.0.138.g2de3478
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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^ permalink raw reply
* Re: [PATCH v3 4/8] PCI: brcmstb: Add dma-range mapping for inbound traffic
From: Bjorn Helgaas @ 2017-12-12 22:32 UTC (permalink / raw)
To: Jim Quinlan
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bjorn Helgaas,
Catalin Marinas, Will Deacon, Rob Herring, Brian Norris,
Russell King, Robin Murphy, Christoph Hellwig, Florian Fainelli,
Jonas Gorski, linux-pci-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Gregory Fong,
Kevin Cernekee, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Ralf Baechle
In-Reply-To: <1510697532-32828-5-git-send-email-jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Tue, Nov 14, 2017 at 05:12:08PM -0500, Jim Quinlan wrote:
> The Broadcom STB PCIe host controller is intimately related to the
> memory subsystem. This close relationship adds complexity to how cpu
> system memory is mapped to PCIe memory. Ideally, this mapping is an
> identity mapping, or an identity mapping off by a constant. Not so in
> this case.
>
> Consider the Broadcom reference board BCM97445LCC_4X8 which has 6 GB
> of system memory. Here is how the PCIe controller maps the
> system memory to PCIe memory:
>
> memc0-a@[ 0....3fffffff] <=> pci@[ 0....3fffffff]
> memc0-b@[100000000...13fffffff] <=> pci@[ 40000000....7fffffff]
> memc1-a@[ 40000000....7fffffff] <=> pci@[ 80000000....bfffffff]
> memc1-b@[300000000...33fffffff] <=> pci@[ c0000000....ffffffff]
> memc2-a@[ 80000000....bfffffff] <=> pci@[100000000...13fffffff]
> memc2-b@[c00000000...c3fffffff] <=> pci@[140000000...17fffffff]
>
> Although there are some "gaps" that can be added between the
> individual mappings by software, the permutation of memory regions for
> the most part is fixed by HW. The solution of having something close
> to an identity mapping is not possible.
>
> The idea behind this HW design is that the same PCIe module can
> act as an RC or EP, and if it acts as an EP it concatenates all
> of system memory into a BAR so anything can be accessed. Unfortunately,
> when the PCIe block is in the role of an RC it also presents this
> "BAR" to downstream PCIe devices, rather than offering an identity map
> between its system memory and PCIe space.
>
> Suppose that an endpoint driver allocs some DMA memory. Suppose this
> memory is located at 0x6000_0000, which is in the middle of memc1-a.
> The driver wants a dma_addr_t value that it can pass on to the EP to
> use. Without doing any custom mapping, the EP will use this value for
> DMA: the driver will get a dma_addr_t equal to 0x6000_0000. But this
> won't work; the device needs a dma_addr_t that reflects the PCIe space
> address, namely 0xa000_0000.
>
> So, essentially the solution to this problem must modify the
> dma_addr_t returned by the DMA routines routines. There are two
> ways (I know of) of doing this:
>
> (a) overriding/redefining the dma_to_phys() and phys_to_dma() calls
> that are used by the dma_ops routines. This is the approach of
>
> arch/mips/cavium-octeon/dma-octeon.c
>
> In ARM and ARM64 these two routines are defiend in asm/dma-mapping.h
> as static inline functions.
>
> (b) Subscribe to a notifier that notifies when a device is added to a
> bus. When this happens, set_dma_ops() can be called for the device.
> This method is mentioned in:
>
> http://lxr.free-electrons.com/source/drivers/of/platform.c?v=3.16#L152
>
> where it says as a comment
>
> "In case if platform code need to use own special DMA
> configuration, it can use Platform bus notifier and
> handle BUS_NOTIFY_ADD_DEVICE event to fix up DMA
> configuration."
>
> Solution (b) is what this commit does. It uses its own set of
> dma_ops which are wrappers around the arch_dma_ops. The
> wrappers translate the dma addresses before/after invoking
> the arch_dma_ops, as appropriate.
>
> Signed-off-by: Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> drivers/pci/host/Makefile | 4 +-
> drivers/pci/host/pcie-brcmstb-dma.c | 319 ++++++++++++++++++++++++++++++++++++
> drivers/pci/host/pcie-brcmstb.c | 139 +++++++++++++++-
> drivers/pci/host/pcie-brcmstb.h | 22 +++
> 4 files changed, 474 insertions(+), 10 deletions(-)
> create mode 100644 drivers/pci/host/pcie-brcmstb-dma.c
> create mode 100644 drivers/pci/host/pcie-brcmstb.h
>
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index a8b9923..6b94c9c 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -21,7 +21,9 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
> obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> obj-$(CONFIG_VMD) += vmd.o
> -obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> +
> +obj-$(CONFIG_PCIE_BRCMSTB) += brcmstb-pcie.o
> +brcmstb-pcie-objs := pcie-brcmstb.o pcie-brcmstb-dma.o
I do not like the addition of more files for this driver (we might
have talked about this before, I can't remember). If we end up with
2, 3, 4 files for every vendor it's going to be a hassle to manage.
It looks like the only caller of the pcie-brcmstb-dma.c is
pcie-brcmstb.c, so for now, at least, I don't see the point of
splitting them. They can always be split later if necessary.
> # The following drivers are for devices that use the generic ACPI
> # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/host/pcie-brcmstb-dma.c b/drivers/pci/host/pcie-brcmstb-dma.c
> new file mode 100644
> index 0000000..6c397be
> --- /dev/null
> +++ b/drivers/pci/host/pcie-brcmstb-dma.c
> @@ -0,0 +1,319 @@
> +/*
> + * Copyright (C) 2015-2017 Broadcom
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
Spurious blank comment line.
> + */
> +#include <linux/dma-mapping.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_pci.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +#include <linux/smp.h>
> +
> +#include "pcie-brcmstb.h"
> +
> +static const struct dma_map_ops *arch_dma_ops;
> +static const struct dma_map_ops *brcm_dma_ops_ptr;
> +
> +static dma_addr_t brcm_to_pci(dma_addr_t addr)
> +{
> + struct of_pci_range *p;
> +
> + if (!num_dma_ranges)
> + return addr;
> +
> + for (p = dma_ranges; p < &dma_ranges[num_dma_ranges]; p++)
> + if (addr >= p->cpu_addr && addr < (p->cpu_addr + p->size))
> + return addr - p->cpu_addr + p->pci_addr;
> +
> + return addr;
> +}
> +
> +static dma_addr_t brcm_to_cpu(dma_addr_t addr)
> +{
> + struct of_pci_range *p;
> +
> + if (!num_dma_ranges)
> + return addr;
> +
> + for (p = dma_ranges; p < &dma_ranges[num_dma_ranges]; p++)
> + if (addr >= p->pci_addr && addr < (p->pci_addr + p->size))
> + return addr - p->pci_addr + p->cpu_addr;
> +
> + return addr;
> +}
> +
> +static void *brcm_alloc(struct device *dev, size_t size, dma_addr_t *handle,
> + gfp_t gfp, unsigned long attrs)
> +{
> + void *ret;
> +
> + ret = arch_dma_ops->alloc(dev, size, handle, gfp, attrs);
> + if (ret)
> + *handle = brcm_to_pci(*handle);
> + return ret;
> +}
> +
> +static void brcm_free(struct device *dev, size_t size, void *cpu_addr,
> + dma_addr_t handle, unsigned long attrs)
> +{
> + handle = brcm_to_cpu(handle);
> + arch_dma_ops->free(dev, size, cpu_addr, handle, attrs);
> +}
> +
> +static int brcm_mmap(struct device *dev, struct vm_area_struct *vma,
> + void *cpu_addr, dma_addr_t dma_addr, size_t size,
> + unsigned long attrs)
> +{
> + dma_addr = brcm_to_cpu(dma_addr);
> + return arch_dma_ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
> +}
> +
> +static int brcm_get_sgtable(struct device *dev, struct sg_table *sgt,
> + void *cpu_addr, dma_addr_t handle, size_t size,
> + unsigned long attrs)
> +{
> + handle = brcm_to_cpu(handle);
> + return arch_dma_ops->get_sgtable(dev, sgt, cpu_addr, handle, size,
> + attrs);
> +}
> +
> +static dma_addr_t brcm_map_page(struct device *dev, struct page *page,
> + unsigned long offset, size_t size,
> + enum dma_data_direction dir,
> + unsigned long attrs)
> +{
> + return brcm_to_pci(arch_dma_ops->map_page(dev, page, offset, size,
> + dir, attrs));
> +}
> +
> +static void brcm_unmap_page(struct device *dev, dma_addr_t handle,
> + size_t size, enum dma_data_direction dir,
> + unsigned long attrs)
> +{
> + handle = brcm_to_cpu(handle);
> + arch_dma_ops->unmap_page(dev, handle, size, dir, attrs);
> +}
> +
> +static int brcm_map_sg(struct device *dev, struct scatterlist *sgl,
> + int nents, enum dma_data_direction dir,
> + unsigned long attrs)
> +{
> + int i, j;
> + struct scatterlist *sg;
> +
> + for_each_sg(sgl, sg, nents, i) {
> +#ifdef CONFIG_NEED_SG_DMA_LENGTH
> + sg->dma_length = sg->length;
> +#endif
> + sg->dma_address =
> + brcm_dma_ops_ptr->map_page(dev, sg_page(sg), sg->offset,
> + sg->length, dir, attrs);
> + if (dma_mapping_error(dev, sg->dma_address))
> + goto bad_mapping;
> + }
> + return nents;
> +
> +bad_mapping:
> + for_each_sg(sgl, sg, i, j)
> + brcm_dma_ops_ptr->unmap_page(dev, sg_dma_address(sg),
> + sg_dma_len(sg), dir, attrs);
> + return 0;
> +}
> +
> +static void brcm_unmap_sg(struct device *dev,
> + struct scatterlist *sgl, int nents,
> + enum dma_data_direction dir,
> + unsigned long attrs)
> +{
> + int i;
> + struct scatterlist *sg;
> +
> + for_each_sg(sgl, sg, nents, i)
> + brcm_dma_ops_ptr->unmap_page(dev, sg_dma_address(sg),
> + sg_dma_len(sg), dir, attrs);
> +}
> +
> +static void brcm_sync_single_for_cpu(struct device *dev,
> + dma_addr_t handle, size_t size,
> + enum dma_data_direction dir)
> +{
> + handle = brcm_to_cpu(handle);
> + arch_dma_ops->sync_single_for_cpu(dev, handle, size, dir);
> +}
> +
> +static void brcm_sync_single_for_device(struct device *dev,
> + dma_addr_t handle, size_t size,
> + enum dma_data_direction dir)
> +{
> + handle = brcm_to_cpu(handle);
> + arch_dma_ops->sync_single_for_device(dev, handle, size, dir);
> +}
> +
> +static dma_addr_t brcm_map_resource(struct device *dev, phys_addr_t phys,
> + size_t size,
> + enum dma_data_direction dir,
> + unsigned long attrs)
> +{
> + if (arch_dma_ops->map_resource)
> + return brcm_to_pci(arch_dma_ops->map_resource
> + (dev, phys, size, dir, attrs));
> + return brcm_to_pci((dma_addr_t)phys);
> +}
> +
> +static void brcm_unmap_resource(struct device *dev, dma_addr_t handle,
> + size_t size, enum dma_data_direction dir,
> + unsigned long attrs)
> +{
> + if (arch_dma_ops->unmap_resource)
> + arch_dma_ops->unmap_resource(dev, brcm_to_cpu(handle), size,
> + dir, attrs);
> +}
> +
> +void brcm_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl,
> + int nents, enum dma_data_direction dir)
> +{
> + struct scatterlist *sg;
> + int i;
> +
> + for_each_sg(sgl, sg, nents, i)
> + brcm_dma_ops_ptr->sync_single_for_cpu(dev, sg_dma_address(sg),
> + sg->length, dir);
> +}
> +
> +void brcm_sync_sg_for_device(struct device *dev, struct scatterlist *sgl,
> + int nents, enum dma_data_direction dir)
> +{
> + struct scatterlist *sg;
> + int i;
> +
> + for_each_sg(sgl, sg, nents, i)
> + brcm_dma_ops_ptr->sync_single_for_device(dev,
> + sg_dma_address(sg),
> + sg->length, dir);
> +}
> +
> +static int brcm_mapping_error(struct device *dev, dma_addr_t dma_addr)
> +{
> + return arch_dma_ops->mapping_error(dev, dma_addr);
> +}
> +
> +static int brcm_dma_supported(struct device *dev, u64 mask)
> +{
> + if (num_dma_ranges) {
> + /*
> + * It is our translated addresses that the EP will "see", so
> + * we check all of the ranges for the largest possible value.
> + */
> + int i;
> +
> + for (i = 0; i < num_dma_ranges; i++)
> + if (dma_ranges[i].pci_addr + dma_ranges[i].size - 1
> + > mask)
> + return 0;
> + return 1;
> + }
> +
> + return arch_dma_ops->dma_supported(dev, mask);
> +}
> +
> +#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
> +u64 brcm_get_required_mask)(struct device *dev)
> +{
> + return arch_dma_ops->get_required_mask(dev);
> +}
> +#endif
> +
> +static const struct dma_map_ops brcm_dma_ops = {
> + .alloc = brcm_alloc,
> + .free = brcm_free,
> + .mmap = brcm_mmap,
> + .get_sgtable = brcm_get_sgtable,
> + .map_page = brcm_map_page,
> + .unmap_page = brcm_unmap_page,
> + .map_sg = brcm_map_sg,
> + .unmap_sg = brcm_unmap_sg,
> + .map_resource = brcm_map_resource,
> + .unmap_resource = brcm_unmap_resource,
> + .sync_single_for_cpu = brcm_sync_single_for_cpu,
> + .sync_single_for_device = brcm_sync_single_for_device,
> + .sync_sg_for_cpu = brcm_sync_sg_for_cpu,
> + .sync_sg_for_device = brcm_sync_sg_for_device,
> + .mapping_error = brcm_mapping_error,
> + .dma_supported = brcm_dma_supported,
> +#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
> + .get_required_mask = brcm_get_required_mask,
> +#endif
> +};
> +
> +static void brcm_set_dma_ops(struct device *dev)
> +{
> + int ret;
> +
> + if (IS_ENABLED(CONFIG_ARM64)) {
> + /*
> + * We are going to invoke get_dma_ops(). That
> + * function, at this point in time, invokes
> + * get_arch_dma_ops(), and for ARM64 that function
> + * returns a pointer to dummy_dma_ops. So then we'd
> + * like to call arch_setup_dma_ops(), but that isn't
> + * exported. Instead, we call of_dma_configure(),
> + * which is exported, and this calls
> + * arch_setup_dma_ops(). Once we do this the call to
> + * get_dma_ops() will work properly because
> + * dev->dma_ops will be set.
> + */
> + ret = of_dma_configure(dev, dev->of_node);
> + if (ret) {
> + dev_err(dev, "of_dma_configure() failed: %d\n", ret);
> + return;
> + }
> + }
> +
> + arch_dma_ops = get_dma_ops(dev);
> + if (!arch_dma_ops) {
> + dev_err(dev, "failed to get arch_dma_ops\n");
> + return;
> + }
> +
> + set_dma_ops(dev, &brcm_dma_ops);
> +}
> +
> +static int brcmstb_platform_notifier(struct notifier_block *nb,
> + unsigned long event, void *__dev)
> +{
> + struct device *dev = __dev;
> +
> + brcm_dma_ops_ptr = &brcm_dma_ops;
> + if (event != BUS_NOTIFY_ADD_DEVICE)
> + return NOTIFY_DONE;
> +
> + brcm_set_dma_ops(dev);
> + return NOTIFY_OK;
> +}
> +
> +static struct notifier_block brcmstb_platform_nb = {
> + .notifier_call = brcmstb_platform_notifier,
> +};
> +
> +int brcm_register_notifier(void)
> +{
> + return bus_register_notifier(&pci_bus_type, &brcmstb_platform_nb);
> +}
> +
> +int brcm_unregister_notifier(void)
> +{
> + return bus_unregister_notifier(&pci_bus_type, &brcmstb_platform_nb);
> +}
> diff --git a/drivers/pci/host/pcie-brcmstb.c b/drivers/pci/host/pcie-brcmstb.c
> index d8a8f7a..5f4c6aa 100644
> --- a/drivers/pci/host/pcie-brcmstb.c
> +++ b/drivers/pci/host/pcie-brcmstb.c
> @@ -35,6 +35,7 @@
> #include <soc/brcmstb/memory_api.h>
> #include <linux/string.h>
> #include <linux/types.h>
> +#include "pcie-brcmstb.h"
>
> /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
> #define BRCM_PCIE_CAP_REGS 0x00ac
> @@ -332,6 +333,10 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> ((val & ~reg##_##field##_MASK) | \
> (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
>
> +/* Also used by pci-brcmstb-dma.c */
> +struct of_pci_range *dma_ranges;
> +int num_dma_ranges;
These names are too generic for global symbols.
> +
> static struct list_head brcm_pcie = LIST_HEAD_INIT(brcm_pcie);
> static phys_addr_t scb_size[BRCM_MAX_SCB];
> static int num_memc;
> @@ -642,25 +647,42 @@ static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
>
> static int brcm_pcie_add_controller(struct brcm_pcie *pcie)
> {
> + int ret = 0;
> +
> mutex_lock(&brcm_pcie_lock);
> + if (list_empty(&brcm_pcie)) {
> + ret = brcm_register_notifier();
> + if (ret) {
> + dev_err(pcie->dev,
> + "failed to register pci bus notifier\n");
> + goto done;
> + }
> + }
> list_add_tail(&pcie->list, &brcm_pcie);
> +done:
> mutex_unlock(&brcm_pcie_lock);
> -
> - return 0;
> + return ret;
> }
>
> static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
> {
> struct list_head *pos, *q;
> struct brcm_pcie *tmp;
> + static const char *err_msg = "failed to unregister pci bus notifier\n";
>
> mutex_lock(&brcm_pcie_lock);
> list_for_each_safe(pos, q, &brcm_pcie) {
> tmp = list_entry(pos, struct brcm_pcie, list);
> if (tmp == pcie) {
> list_del(pos);
> - if (list_empty(&brcm_pcie))
> + if (list_empty(&brcm_pcie)) {
> + if (brcm_unregister_notifier())
> + dev_err(pcie->dev, err_msg);
> + kfree(dma_ranges);
> + dma_ranges = NULL;
> + num_dma_ranges = 0;
> num_memc = 0;
> + }
> break;
> }
> }
> @@ -712,6 +734,75 @@ static int brcm_pcie_parse_request_of_pci_ranges(struct brcm_pcie *pcie)
> return 0;
> }
>
> +static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
> + struct device_node *node)
> +{
> + const int na = 3, ns = 2;
> + int rlen;
> +
> + parser->node = node;
> + parser->pna = of_n_addr_cells(node);
> + parser->np = parser->pna + na + ns;
> +
> + parser->range = of_get_property(node, "dma-ranges", &rlen);
> + if (!parser->range)
> + return -ENOENT;
> +
> + parser->end = parser->range + rlen / sizeof(__be32);
> +
> + return 0;
> +}
> +
> +static int brcm_pcie_parse_map_dma_ranges(struct brcm_pcie *pcie)
> +{
> + int i, ret = 0;
> + struct of_pci_range_parser parser;
> + struct device_node *dn = pcie->dn;
> +
> + mutex_lock(&brcm_pcie_lock);
> + if (dma_ranges)
> + goto done;
> +
> + /*
> + * Parse dma-ranges property if present. If there are multiple
> + * PCI controllers, we only have to parse from one of them since
> + * the others will have an identical mapping.
> + */
> + if (!pci_dma_range_parser_init(&parser, dn)) {
> + unsigned int max_ranges
> + = (parser.end - parser.range) / parser.np;
> +
> + dma_ranges = kcalloc(max_ranges, sizeof(struct of_pci_range),
> + GFP_KERNEL);
> + if (!dma_ranges) {
> + ret = -ENOMEM;
> + goto done;
> + }
> + for (i = 0; of_pci_range_parser_one(&parser, dma_ranges + i);
> + i++)
> + num_dma_ranges++;
> + }
> +
> + for (i = 0, num_memc = 0; i < BRCM_MAX_SCB; i++) {
> + u64 size = brcmstb_memory_memc_size(i);
> +
> + if (size == (u64)-1) {
> + dev_err(pcie->dev, "cannot get memc%d size", i);
> + ret = -EINVAL;
> + goto done;
> + } else if (size) {
> + scb_size[i] = roundup_pow_of_two_64(size);
> + num_memc++;
> + } else {
> + break;
> + }
> + }
> +
> +done:
> + mutex_unlock(&brcm_pcie_lock);
> + return ret;
> +}
> +
> static int brcm_pcie_setup(struct brcm_pcie *pcie)
> {
> void __iomem *base = pcie->base;
> @@ -781,6 +872,38 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> */
> rc_bar2_offset = 0;
>
> + if (dma_ranges) {
> + /*
> + * The best-case scenario is to place the inbound
> + * region in the first 4GB of pci-space, as some
> + * legacy devices can only address 32bits.
> + * We would also like to put the MSI under 4GB
> + * as well, since some devices require a 32bit
> + * MSI target address.
> + */
> + if (total_mem_size <= 0xc0000000ULL &&
> + rc_bar2_size <= 0x100000000ULL) {
> + rc_bar2_offset = 0;
> + } else {
> + /*
> + * The system memory is 4GB or larger so we
> + * cannot start the inbound region at location
> + * 0 (since we have to allow some space for
> + * outbound memory @ 3GB). So instead we
> + * start it at the 1x multiple of its size
> + */
> + rc_bar2_offset = rc_bar2_size;
> + }
> +
> + } else {
> + /*
> + * Set simple configuration based on memory sizes
> + * only. We always start the viewport at address 0,
> + * and set the MSI target address accordingly.
> + */
> + rc_bar2_offset = 0;
> + }
> +
> tmp = lower_32_bits(rc_bar2_offset);
> tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> encode_ibar_size(rc_bar2_size));
> @@ -995,7 +1118,6 @@ static int brcm_pcie_probe(struct platform_device *pdev)
> struct brcm_pcie *pcie;
> struct resource *res;
> void __iomem *base;
> - u32 tmp;
> struct pci_host_bridge *bridge;
> struct pci_bus *child;
>
> @@ -1012,11 +1134,6 @@ static int brcm_pcie_probe(struct platform_device *pdev)
> return -EINVAL;
> }
>
> - if (of_property_read_u32(dn, "dma-ranges", &tmp) == 0) {
> - dev_err(&pdev->dev, "cannot yet handle dma-ranges\n");
> - return -EINVAL;
> - }
> -
> data = of_id->data;
> pcie->reg_offsets = data->offsets;
> pcie->reg_field_info = data->reg_field_info;
> @@ -1059,6 +1176,10 @@ static int brcm_pcie_probe(struct platform_device *pdev)
> if (ret)
> return ret;
>
> + ret = brcm_pcie_parse_map_dma_ranges(pcie);
> + if (ret)
> + return ret;
> +
> ret = clk_prepare_enable(pcie->clk);
> if (ret) {
> dev_err(&pdev->dev, "could not enable clock\n");
> diff --git a/drivers/pci/host/pcie-brcmstb.h b/drivers/pci/host/pcie-brcmstb.h
> new file mode 100644
> index 0000000..d7233f0
> --- /dev/null
> +++ b/drivers/pci/host/pcie-brcmstb.h
> @@ -0,0 +1,22 @@
> +#ifndef __BRCMSTB_PCI_H
> +#define __BRCMSTB_PCI_H
> +/*
> + * Copyright (C) 2015 - 2017 Broadcom
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +int brcm_register_notifier(void);
> +int brcm_unregister_notifier(void);
> +
> +extern struct of_pci_range *dma_ranges;
> +extern int num_dma_ranges;
> +
> +#endif /* __BRCMSTB_PCI_H */
> --
> 1.9.0.138.g2de3478
>
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^ permalink raw reply
* Re: [PATCH v3 6/8] PCI: brcmstb: Add MSI capability
From: Bjorn Helgaas @ 2017-12-12 22:43 UTC (permalink / raw)
To: Jim Quinlan
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bjorn Helgaas,
Catalin Marinas, Will Deacon, Rob Herring, Brian Norris,
Russell King, Robin Murphy, Christoph Hellwig, Florian Fainelli,
Jonas Gorski, linux-pci-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Gregory Fong,
Kevin Cernekee, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Ralf Baechle
In-Reply-To: <1510697532-32828-7-git-send-email-jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Tue, Nov 14, 2017 at 05:12:10PM -0500, Jim Quinlan wrote:
> This commit adds MSI to the Broadcom STB PCIe host controller. It does
> not add MSIX since that functionality is not in the HW. The MSI
> controller is physically located within the PCIe block, however, there
> is no reason why the MSI controller could not be moved elsewhere in
> the future.
>
> Since the internal Brcmstb MSI controller is intertwined with the PCIe
> controller, it is not its own platform device but rather part of the
> PCIe platform device.
>
> Signed-off-by: Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> drivers/pci/host/pcie-brcmstb.c | 372 ++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 359 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-brcmstb.c b/drivers/pci/host/pcie-brcmstb.c
> index 5f4c6aa..89bad31 100644
> --- a/drivers/pci/host/pcie-brcmstb.c
> +++ b/drivers/pci/host/pcie-brcmstb.c
> @@ -11,6 +11,7 @@
> * GNU General Public License for more details.
> */
>
> +#include <linux/bitops.h>
> #include <linux/clk.h>
> #include <linux/compiler.h>
> #include <linux/delay.h>
> @@ -18,15 +19,16 @@
> #include <linux/interrupt.h>
> #include <linux/io.h>
> #include <linux/ioport.h>
> +#include <linux/irqchip/chained_irq.h>
> #include <linux/irqdomain.h>
> #include <linux/kernel.h>
> #include <linux/list.h>
> #include <linux/log2.h>
> #include <linux/module.h>
> +#include <linux/msi.h>
> #include <linux/of_address.h>
> #include <linux/of_irq.h>
> #include <linux/of_pci.h>
> -#include <linux/of_pci.h>
> #include <linux/of_platform.h>
> #include <linux/pci.h>
> #include <linux/printk.h>
> @@ -56,6 +58,9 @@
> #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
> #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
> #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
> +#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
> +#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
> +#define PCIE_MISC_MSI_DATA_CONFIG 0x404c
> #define PCIE_MISC_PCIE_CTRL 0x4064
> #define PCIE_MISC_PCIE_STATUS 0x4068
> #define PCIE_MISC_REVISION 0x406c
> @@ -64,6 +69,7 @@
> #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
> #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> #define PCIE_INTR2_CPU_BASE 0x4300
> +#define PCIE_MSI_INTR2_BASE 0x4500
>
> /*
> * Broadcom Settop Box PCIE Register Field shift and mask info. The
> @@ -124,6 +130,8 @@
>
> #define BRCM_NUM_PCIE_OUT_WINS 0x4
> #define BRCM_MAX_SCB 0x4
> +#define BRCM_INT_PCI_MSI_NR 32
> +#define BRCM_PCIE_HW_REV_33 0x0303
>
> #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
> #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
> @@ -212,6 +220,30 @@ struct brcm_window {
> dma_addr_t size;
> };
>
> +struct brcm_msi {
> + struct irq_domain *msi_domain;
> + struct irq_domain *inner_domain;
> + struct mutex lock; /* guards the alloc/free operations */
> + u64 target_addr;
> + int irq;
> + /* intr_base is the base pointer for interrupt status/set/clr regs */
> + void __iomem *intr_base;
> + /* intr_legacy_mask indicates how many bits are MSI interrupts */
> + u32 intr_legacy_mask;
> + /*
> + * intr_legacy_offset indicates bit position of MSI_01. It is
> + * to map the register bit position to a hwirq that starts at 0.
> + */
> + u32 intr_legacy_offset;
> + /* used indicates which MSI interrupts have been alloc'd */
> + unsigned long used;
> +
> + void __iomem *base;
> + struct device *dev;
> + struct device_node *dn;
> + unsigned int rev;
I think you aligned the structure elements for brcm_pcie, so do the
same here.
> +};
> +
> /* Internal PCIe Host Controller Information.*/
> struct brcm_pcie {
> struct list_head list;
> @@ -227,7 +259,10 @@ struct brcm_pcie {
> int num_out_wins;
> bool ssc;
> int gen;
> + u64 msi_target_addr;
> struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
> + struct brcm_msi *msi;
> + bool msi_internal;
> unsigned int rev;
> const int *reg_offsets;
> const int *reg_field_info;
> @@ -240,6 +275,13 @@ struct pcie_cfg_data {
> const enum pcie_type type;
> };
>
> +struct brcm_info {
> + int rev;
> + u64 msi_target_addr;
> + void __iomem *base;
> + struct brcm_msi *msi;
And here.
> +};
> +
> static const int pcie_reg_field_info[] = {
> [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
> [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
> @@ -546,6 +588,264 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
> }
> }
>
> +static struct irq_chip brcm_msi_irq_chip = {
> + .name = "Brcm_MSI",
> + .irq_mask = pci_msi_mask_irq,
> + .irq_unmask = pci_msi_unmask_irq,
> +};
> +
> +static struct msi_domain_info brcm_msi_domain_info = {
> + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
> + MSI_FLAG_PCI_MSIX),
> + .chip = &brcm_msi_irq_chip,
> +};
> +
> +static void brcm_pcie_msi_isr(struct irq_desc *desc)
> +{
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + struct brcm_msi *msi;
> + unsigned long status, virq;
> + u32 mask, bit, hwirq;
> + struct device *dev;
> +
> + chained_irq_enter(chip, desc);
> + msi = irq_desc_get_handler_data(desc);
> + mask = msi->intr_legacy_mask;
> + dev = msi->dev;
> +
> + while ((status = bcm_readl(msi->intr_base + STATUS) & mask)) {
> + for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) {
> + /* clear the interrupt */
> + bcm_writel(1 << bit, msi->intr_base + CLR);
> +
> + /* Account for legacy interrupt offset */
> + hwirq = bit - msi->intr_legacy_offset;
> +
> + virq = irq_find_mapping(msi->inner_domain, hwirq);
> + if (virq) {
> + if (msi->used & (1 << hwirq))
> + generic_handle_irq(virq);
> + else
> + dev_info(dev, "unhandled MSI %d\n",
> + hwirq);
> + } else {
> + /* Unknown MSI, just clear it */
> + dev_dbg(dev, "unexpected MSI\n");
> + }
> + }
> + }
> + chained_irq_exit(chip, desc);
> +}
> +
> +static void brcm_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
> +{
> + struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
> + u32 temp;
> +
> + msg->address_lo = lower_32_bits(msi->target_addr);
> + msg->address_hi = upper_32_bits(msi->target_addr);
> + temp = bcm_readl(msi->base + PCIE_MISC_MSI_DATA_CONFIG);
> + msg->data = ((temp >> 16) & (temp & 0xffff)) | data->hwirq;
> +}
> +
> +static int brcm_msi_set_affinity(struct irq_data *irq_data,
> + const struct cpumask *mask, bool force)
> +{
> + return -EINVAL;
> +}
> +
> +static struct irq_chip brcm_msi_bottom_irq_chip = {
> + .name = "Brcm_MSI",
> + .irq_compose_msi_msg = brcm_compose_msi_msg,
> + .irq_set_affinity = brcm_msi_set_affinity,
> +};
> +
> +static int brcm_msi_alloc(struct brcm_msi *msi)
> +{
> + int bit, hwirq;
> +
> + mutex_lock(&msi->lock);
> + bit = ~msi->used ? ffz(msi->used) : -1;
> +
> + if (bit >= 0 && bit < BRCM_INT_PCI_MSI_NR) {
> + msi->used |= (1 << bit);
> + hwirq = bit - msi->intr_legacy_offset;
> + } else {
> + hwirq = -ENOSPC;
> + }
> +
> + mutex_unlock(&msi->lock);
> + return hwirq;
> +}
> +
> +static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
> +{
> + mutex_lock(&msi->lock);
> + msi->used &= ~(1 << (hwirq + msi->intr_legacy_offset));
> + mutex_unlock(&msi->lock);
> +}
> +
> +static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> + unsigned int nr_irqs, void *args)
> +{
> + struct brcm_msi *msi = domain->host_data;
> + int hwirq;
> +
> + hwirq = brcm_msi_alloc(msi);
> +
> + if (hwirq < 0)
> + return hwirq;
> +
> + irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
> + &brcm_msi_bottom_irq_chip, domain->host_data,
> + handle_simple_irq, NULL, NULL);
> + return 0;
> +}
> +
> +static void brcm_irq_domain_free(struct irq_domain *domain,
> + unsigned int virq, unsigned int nr_irqs)
> +{
> + struct irq_data *d = irq_domain_get_irq_data(domain, virq);
> + struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
> +
> + brcm_msi_free(msi, d->hwirq);
> +}
> +
> +void brcm_msi_set_regs(struct brcm_msi *msi)
Static?
> +{
> + u32 data_val, msi_lo, msi_hi;
> +
> + if (msi->rev >= BRCM_PCIE_HW_REV_33) {
> + /*
> + * ffe0 -- least sig 5 bits are 0 indicating 32 msgs
> + * 6540 -- this is our arbitrary unique data value
> + */
> + data_val = 0xffe06540;
> + } else {
> + /*
> + * fff8 -- least sig 3 bits are 0 indicating 8 msgs
> + * 6540 -- this is our arbitrary unique data value
> + */
> + data_val = 0xfff86540;
> + }
> +
> + /*
> + * Make sure we are not masking MSIs. Note that MSIs can be masked,
> + * but that occurs on the PCIe EP device
> + */
> + bcm_writel(0xffffffff & msi->intr_legacy_mask,
> + msi->intr_base + MASK_CLR);
> +
> + msi_lo = lower_32_bits(msi->target_addr);
> + msi_hi = upper_32_bits(msi->target_addr);
> + /*
> + * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
> + * enable, which we set to 1.
> + */
> + bcm_writel(msi_lo | 1, msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
> + bcm_writel(msi_hi, msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
> + bcm_writel(data_val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
> +}
> +
> +static const struct irq_domain_ops msi_domain_ops = {
> + .alloc = brcm_irq_domain_alloc,
> + .free = brcm_irq_domain_free,
> +};
> +
> +static int brcm_allocate_domains(struct brcm_msi *msi)
> +{
> + struct fwnode_handle *fwnode = of_node_to_fwnode(msi->dn);
> + struct device *dev = msi->dev;
> +
> + msi->inner_domain = irq_domain_add_linear(NULL, BRCM_INT_PCI_MSI_NR,
> + &msi_domain_ops, msi);
> + if (!msi->inner_domain) {
> + dev_err(dev, "failed to create IRQ domain\n");
> + return -ENOMEM;
> + }
> +
> + msi->msi_domain = pci_msi_create_irq_domain(fwnode,
> + &brcm_msi_domain_info,
> + msi->inner_domain);
> + if (!msi->msi_domain) {
> + dev_err(dev, "failed to create MSI domain\n");
> + irq_domain_remove(msi->inner_domain);
> + return -ENOMEM;
> + }
> +
> + return 0;
> +}
> +
> +static void brcm_free_domains(struct brcm_msi *msi)
> +{
> + irq_domain_remove(msi->msi_domain);
> + irq_domain_remove(msi->inner_domain);
> +}
> +
> +void brcm_msi_remove(struct brcm_msi *msi)
Static?
> +{
> + if (!msi)
> + return;
> + irq_set_chained_handler(msi->irq, NULL);
> + irq_set_handler_data(msi->irq, NULL);
> + brcm_free_domains(msi);
> +}
> +
> +int brcm_msi_probe(struct platform_device *pdev, struct brcm_info *info)
Static?
I don't think we're probing a separate device here, so this isn't
quite the right name. I see it looks like you're using a pattern from
altera or xgene. But those have some weird structure where they have
extra of_match_tables, and you don't.
> +{
> + struct brcm_msi *msi;
> + int irq, ret;
> +
> + irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
> + if (irq <= 0) {
> + dev_err(&pdev->dev, "cannot map msi intr\n");
> + return -ENODEV;
> + }
> +
> + msi = devm_kzalloc(&pdev->dev, sizeof(struct brcm_msi), GFP_KERNEL);
> + if (!msi)
> + return -ENOMEM;
> +
> + msi->dev = &pdev->dev;
> + msi->base = info->base;
> + msi->rev = info->rev;
> + msi->dn = pdev->dev.of_node;
> + msi->target_addr = info->msi_target_addr;
> + msi->irq = irq;
> +
> + ret = brcm_allocate_domains(msi);
> + if (ret)
> + return ret;
> +
> + irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
> +
> + if (msi->rev >= BRCM_PCIE_HW_REV_33) {
> + msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
> + /*
> + * This version of PCIe hw has only 32 intr bits
> + * starting at bit position 0.
> + */
> + msi->intr_legacy_mask = 0xffffffff;
> + msi->intr_legacy_offset = 0x0;
> + msi->used = 0x0;
> +
> + } else {
> + msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
> + /*
> + * This version of PCIe hw has only 8 intr bits starting
> + * at bit position 24.
> + */
> + msi->intr_legacy_mask = 0xff000000;
> + msi->intr_legacy_offset = 24;
> + msi->used = 0x00ffffff;
> + }
> +
> + brcm_msi_set_regs(msi);
> + info->msi = msi;
> +
> + return 0;
> +}
> +
> /* Configuration space read/write support */
> static int cfg_index(int busnr, int devfn, int reg)
> {
> @@ -812,6 +1112,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> int i, j, ret, limit;
> u16 nlw, cls, lnksta;
> bool ssc_good = false;
> + u64 msi_target_addr;
>
> /* reset the bridge and the endpoint device */
> /* field: PCIE_BRIDGE_SW_INIT = 1 */
> @@ -855,14 +1156,17 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> * The PCIe host controller by design must set the inbound
> * viewport to be a contiguous arrangement of all of the
> * system's memory. In addition, its size mut be a power of
> - * two. To further complicate matters, the viewport must
> - * start on a pcie-address that is aligned on a multiple of its
> - * size. If a portion of the viewport does not represent
> - * system memory -- e.g. 3GB of memory requires a 4GB viewport
> - * -- we can map the outbound memory in or after 3GB and even
> - * though the viewport will overlap the outbound memory the
> - * controller will know to send outbound memory downstream and
> - * everything else upstream.
> + * two. Further, the MSI target address must NOT be placed
> + * inside this region, as the decoding logic will consider its
> + * address to be inbound memory traffic. To further
> + * complicate matters, the viewport must start on a
> + * pcie-address that is aligned on a multiple of its size.
> + * If a portion of the viewport does not represent system
> + * memory -- e.g. 3GB of memory requires a 4GB viewport --
> + * we can map the outbound memory in or after 3GB and even
> + * though the viewport will overlap the outbound memory
> + * the controller will know to send outbound memory downstream
> + * and everything else upstream.
> */
> rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
>
> @@ -875,7 +1179,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> if (dma_ranges) {
> /*
> * The best-case scenario is to place the inbound
> - * region in the first 4GB of pci-space, as some
> + * region in the first 4GB of pcie-space, as some
> * legacy devices can only address 32bits.
> * We would also like to put the MSI under 4GB
> * as well, since some devices require a 32bit
> @@ -884,6 +1188,14 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> if (total_mem_size <= 0xc0000000ULL &&
> rc_bar2_size <= 0x100000000ULL) {
> rc_bar2_offset = 0;
> + /* If the viewport is less then 4GB we can fit
> + * the MSI target address under 4GB. Otherwise
> + * put it right below 64GB.
> + */
> + msi_target_addr =
> + (rc_bar2_size == 0x100000000ULL)
> + ? BRCM_MSI_TARGET_ADDR_GT_4GB
> + : BRCM_MSI_TARGET_ADDR_LT_4GB;
> } else {
> /*
> * The system memory is 4GB or larger so we
> @@ -893,8 +1205,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> * start it at the 1x multiple of its size
> */
> rc_bar2_offset = rc_bar2_size;
> - }
>
> + /* Since we are starting the viewport at 4GB or
> + * higher, put the MSI target address below 4GB
> + */
> + msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
> + }
> } else {
> /*
> * Set simple configuration based on memory sizes
> @@ -902,7 +1218,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> * and set the MSI target address accordingly.
> */
> rc_bar2_offset = 0;
> +
> + msi_target_addr = (rc_bar2_size >= 0x100000000ULL)
> + ? BRCM_MSI_TARGET_ADDR_GT_4GB
> + : BRCM_MSI_TARGET_ADDR_LT_4GB;
> }
> + pcie->msi_target_addr = msi_target_addr;
>
> tmp = lower_32_bits(rc_bar2_offset);
> tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> @@ -1076,6 +1397,9 @@ static int brcm_pcie_resume(struct device *dev)
> if (ret)
> return ret;
>
> + if (pcie->msi && pcie->msi_internal)
> + brcm_msi_set_regs(pcie->msi);
> +
> pcie->suspended = false;
>
> return 0;
> @@ -1083,6 +1407,7 @@ static int brcm_pcie_resume(struct device *dev)
>
> static void _brcm_pcie_remove(struct brcm_pcie *pcie)
> {
> + brcm_msi_remove(pcie->msi);
> turn_off(pcie);
> clk_disable_unprepare(pcie->clk);
> clk_put(pcie->clk);
> @@ -1111,7 +1436,7 @@ static int brcm_pcie_remove(struct platform_device *pdev)
>
> static int brcm_pcie_probe(struct platform_device *pdev)
> {
> - struct device_node *dn = pdev->dev.of_node;
> + struct device_node *dn = pdev->dev.of_node, *msi_dn;
> const struct of_device_id *of_id;
> const struct pcie_cfg_data *data;
> int ret;
> @@ -1194,6 +1519,28 @@ static int brcm_pcie_probe(struct platform_device *pdev)
> if (ret)
> goto fail;
>
> + msi_dn = of_parse_phandle(pcie->dn, "msi-parent", 0);
> + /* Use the internal MSI if no msi-parent property */
> + if (!msi_dn)
> + msi_dn = pcie->dn;
> +
> + if (pci_msi_enabled() && msi_dn == pcie->dn) {
> + struct brcm_info info;
> +
> + info.rev = pcie->rev;
> + info.msi_target_addr = pcie->msi_target_addr;
> + info.base = pcie->base;
> +
> + ret = brcm_msi_probe(pdev, &info);
> + if (ret)
> + dev_err(pcie->dev,
> + "probe of internal MSI failed: %d)", ret);
> + else
> + pcie->msi_internal = true;
> +
> + pcie->msi = info.msi;
> + }
> +
> list_splice_init(&pcie->resources, &bridge->windows);
> bridge->dev.parent = &pdev->dev;
> bridge->busnr = 0;
> @@ -1216,7 +1563,6 @@ static int brcm_pcie_probe(struct platform_device *pdev)
> pcie->root_bus = bridge->bus;
>
> return 0;
> -
> fail:
> _brcm_pcie_remove(pcie);
> return ret;
> --
> 1.9.0.138.g2de3478
>
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^ permalink raw reply
* Re: [PATCH v3 0/3] Bluetooth: hci_ll: Get BD address from NVMEM
From: Marcel Holtmann @ 2017-12-12 22:52 UTC (permalink / raw)
To: David Lechner
Cc: devicetree, open list:BLUETOOTH DRIVERS, Rob Herring,
Mark Rutland, Gustavo F. Padovan, Johan Hedberg,
Network Development, linux-kernel
In-Reply-To: <1513115958-23761-1-git-send-email-david@lechnology.com>
Hi David,
> This series adds supporting getting the BD address from a NVMEM provider
> for "LL" HCI controllers (Texas Instruments).
>
> v3 changes:
> * Additional comments on why swapping bytes is needed.
> * Fixed comment style and trailing whitespace.
> * Rework error handling for nvmem cell code.
>
> v2 changes:
> * Fixed typos in dt-bindings
> * Use "bd-address" instead of "mac-address"
> * Updated dt-bindings to specify the byte order of "bd-address"
> * New patch "Bluetooth: hci_ll: add support for setting public address"
> * Dropped patch "Bluetooth: hci_ll: add constant for vendor-specific command"
> that is already in bluetooth-next
> * Rework error handling
> * Use bdaddr_t, bacmp and other bluetooth utils
>
> David Lechner (3):
> Bluetooth: hci_ll: add support for setting public address
> dt-bindings: Add optional nvmem BD address bindings to ti,wlink-st
> Bluetooth: hci_ll: Add optional nvmem BD address source
>
> .../devicetree/bindings/net/ti,wilink-st.txt | 5 ++
> drivers/bluetooth/hci_ll.c | 77 ++++++++++++++++++++++
> 2 files changed, 82 insertions(+)
I applied to first 2 patches to bluetooth-next tree, but the 3rd is throwing a warning.
CC drivers/bluetooth/hci_ll.o
drivers/bluetooth/hci_ll.c: In function ‘hci_ti_probe’:
drivers/bluetooth/hci_ll.c:814:41: error: passing argument 2 of ‘nvmem_cell_read’ from incompatible pointer type [-Werror=incompatible-pointer-types]
bdaddr = nvmem_cell_read(bdaddr_cell, &len);
^
In file included from drivers/bluetooth/hci_ll.c:56:0:
./include/linux/nvmem-consumer.h:81:21: note: expected ‘size_t * {aka long unsigned int *}’ but argument is of type ‘int *’
static inline void *nvmem_cell_read(struct nvmem_cell *cell, size_t *len)
^~~~~~~~~~~~~~~
Regards
Marcel
^ permalink raw reply
* Re: [PATCH 1/1] dt-bindings: arm: document supported STM32 SoC family
From: Rob Herring @ 2017-12-12 23:17 UTC (permalink / raw)
To: Ludovic Barre
Cc: Mark Rutland, Maxime Coquelin, Alexandre Torgue,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Gwenael Treuveur
In-Reply-To: <20171212210348.proilmqmxf4yl5jn@rob-hp-laptop>
On Tue, Dec 12, 2017 at 03:03:48PM -0600, Rob Herring wrote:
> On Fri, Dec 08, 2017 at 02:56:34PM +0100, Ludovic Barre wrote:
> > From: Ludovic Barre <ludovic.barre-qxv4g6HH51o@public.gmane.org>
> >
> > This adds a list of supported STM32 SoC bindings.
> >
> > Signed-off-by: Gwenael Treuveur <gwenael.treuveur-qxv4g6HH51o@public.gmane.org>
> > Signed-off-by: Ludovic Barre <ludovic.barre-qxv4g6HH51o@public.gmane.org>
> > ---
> > Documentation/devicetree/bindings/arm/stm32.txt | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/arm/stm32.txt
>
> Applied, thanks.
Now dropped as this will conflict with your other series. Send this with
the other series or indicate who should apply.
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Rob
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^ permalink raw reply
* Re: [PATCH 2/6] ARM: stm32: add initial support for STM32MP157
From: Rob Herring @ 2017-12-12 23:24 UTC (permalink / raw)
To: Ludovic Barre
Cc: Russell King, Linus Walleij, Arnd Bergmann, Maxime Coquelin,
Alexandre Torgue, linux-arm-kernel, linux-kernel, devicetree
In-Reply-To: <1512742277-28205-3-git-send-email-ludovic.Barre@st.com>
On Fri, Dec 08, 2017 at 03:11:13PM +0100, Ludovic Barre wrote:
> From: Ludovic Barre <ludovic.barre@st.com>
>
> This patch adds initial support of STM32MP157 microprocessor (MPU)
> based on Arm Cortex-A7. Under new ARCH_STM32_MPU flag we select the
> needed Cortex-A infrastructure (like gic, timer,...)
>
> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
> ---
> Documentation/arm/stm32/stm32mp157-overview.txt | 12 ++++++++++++
> Documentation/devicetree/bindings/arm/stm32.txt | 1 +
Please split bindings to separate patches.
> arch/arm/mach-stm32/Kconfig | 22 ++++++++++++++++++++--
> arch/arm/mach-stm32/Makefile | 1 +
> arch/arm/mach-stm32/board-mpu-dt.c | 16 ++++++++++++++++
> 5 files changed, 50 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/arm/stm32/stm32mp157-overview.txt
> create mode 100644 arch/arm/mach-stm32/board-mpu-dt.c
>
> diff --git a/Documentation/arm/stm32/stm32mp157-overview.txt b/Documentation/arm/stm32/stm32mp157-overview.txt
> new file mode 100644
> index 0000000..8a3e7cb
> --- /dev/null
> +++ b/Documentation/arm/stm32/stm32mp157-overview.txt
I think new documentation files should be rst format and fit into the
built documentation. We don't have an SoC description doc for most SoCs.
> @@ -0,0 +1,12 @@
> + STM32MP157 Overview
> + ===================
> +
> + Introduction
> + ------------
> + The STM32MP157 is a Cortex-A MPU aimed at various applications.
> + It features:
> + - Dual core Cortex-A7 application core
> + - 2D/3D image composition with GPU
> + - Standard memories interface support
> + - Standard connectivity, widely inherited from the STM32 MCU family
> + - Comprehensive security support
Perhaps make this part of the kconfig entry help.
> diff --git a/Documentation/devicetree/bindings/arm/stm32.txt b/Documentation/devicetree/bindings/arm/stm32.txt
> index 05762b0..6808ed9 100644
> --- a/Documentation/devicetree/bindings/arm/stm32.txt
> +++ b/Documentation/devicetree/bindings/arm/stm32.txt
> @@ -7,3 +7,4 @@ using one of the following compatible strings:
> st,stm32f469
> st,stm32f746
> st,stm32h743
> + st,stm32mp157
> diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
> index c8059ea..2b227c7 100644
> --- a/arch/arm/mach-stm32/Kconfig
> +++ b/arch/arm/mach-stm32/Kconfig
> @@ -1,12 +1,12 @@
> menuconfig ARCH_STM32
> - bool "STMicrolectronics STM32 family" if ARM_SINGLE_ARMV7M
> + bool "STMicrolectronics STM32 family" if ARM_SINGLE_ARMV7M || ARCH_MULTI_V7
> select ARCH_HAS_RESET_CONTROLLER
> select CLKSRC_STM32
> select PINCTRL
> select RESET_CONTROLLER
> select STM32_EXTI
> help
> - Support for STMicroelectronics STM32 MCU family
> + Support for STMicroelectronics STM32 MCU/MPU family
>
> if ARCH_STM32
>
> @@ -40,4 +40,22 @@ config MACH_STM32H743
>
> endif
>
> +if ARCH_MULTI_V7
> +
> +config ARCH_STM32_MPU
> + bool "STMicrolectronics STM32 MPU"
> + default y
> + select ARM_GIC
> + select HAVE_ARM_ARCH_TIMER
> + select ARM_PSCI
> + help
> + Support for STMicroelectronics STM32 Microprocessors.
> +
> +config MACH_STM32MP157
Is this actually used?
> + bool "STMicrolectronics STM32MP157"
> + depends on ARCH_STM32_MPU
> + default y
> +
> +endif
> +
> endif
^ permalink raw reply
* Re: [PATCH 3/6] pinctrl: stm32: Add STM32MP157 MPU support
From: Rob Herring @ 2017-12-12 23:25 UTC (permalink / raw)
To: Ludovic Barre
Cc: Russell King, Linus Walleij, Arnd Bergmann, Maxime Coquelin,
Alexandre Torgue,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512742277-28205-4-git-send-email-ludovic.Barre-qxv4g6HH51o@public.gmane.org>
On Fri, Dec 08, 2017 at 03:11:14PM +0100, Ludovic Barre wrote:
> From: Ludovic Barre <ludovic.barre-qxv4g6HH51o@public.gmane.org>
>
> This driver consists of 2 controllers due to a hole in mapping:
> -1 controller for GPIO bankA to K.
> -1 controller for GPIO bankZ.
>
> Signed-off-by: Alexandre Torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
> Signed-off-by: Ludovic Barre <ludovic.barre-qxv4g6HH51o@public.gmane.org>
> ---
> .../bindings/pinctrl/st,stm32-pinctrl.txt | 2 +
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> drivers/pinctrl/stm32/Kconfig | 6 +
> drivers/pinctrl/stm32/Makefile | 1 +
> drivers/pinctrl/stm32/pinctrl-stm32mp157.c | 2188 ++++++++++++++++++++
> 4 files changed, 2197 insertions(+)
> create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32mp157.c
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^ permalink raw reply
* Re: [RFC] irqchip: add support for LS1021A external interrupt lines
From: Rob Herring @ 2017-12-12 23:28 UTC (permalink / raw)
To: Rasmus Villemoes
Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, Mark Rutland,
Alexander Stein, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512743580-15358-1-git-send-email-rasmus.villemoes-rjjw5hvvQKZaa/9Udqfwiw@public.gmane.org>
On Fri, Dec 08, 2017 at 03:33:00PM +0100, Rasmus Villemoes wrote:
> The LS1021A allows inverting the polarity of six interrupt lines
> IRQ[0:5] via the scfg_intpcr register, effectively allowing
> IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_EDGE_FALLING for those. We just need to
> check the type, set the relevant bit in INTPCR accordingly, and fixup
> the type argument before calling the GIC's irq_set_type.
>
> In fact, the power-on-reset value of the INTPCR register is so that all
> six lines have their polarity inverted. Hence any hardware connected to
> those lines is unusable without this: If the line is indeed active low,
> the generic GIC code will reject an irq spec with IRQ_TYPE_LEVEL_LOW,
> while if the line is active high, we must obviously disable the polarity
> inversion before unmasking the interrupt.
>
> I suspect other layerscape SOCs may have something similar, but I have
> neither hardware nor documentation.
>
> Since we only need to keep a single pointer in the chip_data (the syscon
> regmap), the code could be a little simpler by dropping the struct
> extirq_chip_data and just store the regmap directly - but I don't know
> if I do need to add a lock or something else to the chip_data, so for
> this RFC I've kept the struct.
>
> Signed-off-by: Rasmus Villemoes <rasmus.villemoes-rjjw5hvvQKZaa/9Udqfwiw@public.gmane.org>
> ---
> Marc, Alexander, thanks a lot for your hints. This is what I came up
> with, mostly just copy-pasted from the mtk-sysirq case. I've tested
> that it works as expected on my board.
>
> .../interrupt-controller/fsl,ls1021a-extirq.txt | 19 +++
Please split to separate patch.
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-ls1021a.c | 157 +++++++++++++++++++++
> 3 files changed, 177 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls1021a-extirq.txt
> create mode 100644 drivers/irqchip/irq-ls1021a.c
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls1021a-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls1021a-extirq.txt
> new file mode 100644
> index 000000000000..53b04b6e1a80
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls1021a-extirq.txt
> @@ -0,0 +1,19 @@
> +* Freescale LS1021A external IRQs
> +
> +The LS1021A supports inverting the polarity of six external interrupt lines.
> +
> +Required properties:
> +- compatible: should be "fsl,ls1021a-extirq"
> +- interrupt-controller: Identifies the node as an interrupt controller
> +- #interrupt-cells: Use the same format as specified by GIC in arm,gic.txt.
> +- interrupt-parent: phandle of GIC.
> +- syscon: phandle of Supplemental Configuration Unit (scfg).
Can this be a child of that node instead?
> +
> +Example:
> + extirq: interrupt-controller@15701ac {
Unit-address without reg is not valid. Building with W=1 will tell you
this.
> + compatible = "fsl,ls1021a-extirq";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + syscon = <&scfg>;
> + };
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^ permalink raw reply
* Re: [PATCH] leds: as3645a: Fix checkpatch warnings
From: Laurent Pinchart @ 2017-12-12 23:35 UTC (permalink / raw)
To: Dan Murphy
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
rpurdie-Fm38FmjxZ/leoWH0uzbU5w,
jacek.anaszewski-Re5JQEeQqe8AvxtiuMwx3w, pavel-+ZI9xUNit7I,
sakari.ailus-X3B1VOXEql0, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-leds-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171212215011.30066-1-dmurphy-l0cyMroinI0@public.gmane.org>
Hi Dan,
Thank you for the patch.
On Tuesday, 12 December 2017 23:50:11 EET Dan Murphy wrote:
> Fix two checkpatch warnings for 80 char
> length and for a quoted string across multiple
> line warnings.
>
> Signed-off-by: Dan Murphy <dmurphy-l0cyMroinI0@public.gmane.org>
Acked-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> ---
> drivers/leds/leds-as3645a.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/leds/leds-as3645a.c b/drivers/leds/leds-as3645a.c
> index 9a257f969300..f883616d9e60 100644
> --- a/drivers/leds/leds-as3645a.c
> +++ b/drivers/leds/leds-as3645a.c
> @@ -360,7 +360,8 @@ static int as3645a_set_flash_brightness(struct
> led_classdev_flash *fled, {
> struct as3645a *flash = fled_to_as3645a(fled);
>
> - flash->flash_current = as3645a_current_to_reg(flash, true, brightness_ua);
> + flash->flash_current = as3645a_current_to_reg(flash, true,
> + brightness_ua);
>
> return as3645a_set_current(flash);
> }
> @@ -455,8 +456,8 @@ static int as3645a_detect(struct as3645a *flash)
>
> /* Verify the chip model and version. */
> if (model != 0x01 || rfu != 0x00) {
> - dev_err(dev, "AS3645A not detected "
> - "(model %d rfu %d)\n", model, rfu);
> + dev_err(dev, "AS3645A not detected (model %d rfu %d)\n",
> + model, rfu);
> return -ENODEV;
> }
--
Regards,
Laurent Pinchart
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^ permalink raw reply
* Re: [PATCH v6 03/17] mfd: madera: Add common support for Cirrus Logic Madera codecs
From: Linus Walleij @ 2017-12-12 23:51 UTC (permalink / raw)
To: Richard Fitzgerald
Cc: Lee Jones, Mark Brown, Alexandre Courbot, Rob Herring,
Thomas Gleixner, Jason Cooper, alsa-devel,
open list:WOLFSON MICROELECTRONICS DRIVERS, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org, Charles Keepax, Nikesh Oswal
In-Reply-To: <e11d1657-0dfe-4de6-8928-0512ae3c1f1a@EX17.ad.cirrus.com>
On Thu, Dec 7, 2017 at 11:52 AM, Richard Fitzgerald
<rf@opensource.wolfsonmicro.com> wrote:
> On 07/12/17 08:54, Linus Walleij wrote:
>> If what you want is unconditional pin control enabled for this circuit,
>> then have MFD_MADERA select PINCTRL.
> So the short version of this email thread is that it should be "select
> PINCTRL" ?
If by "it" you mean MFD_MADERA tne I guess yes :D
I was just confused because I couldn't figure out what you were
trying to do.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH V7 0/7] dmaengine: qcom_hidma: add support for bugfixed HW
From: Sinan Kaya @ 2017-12-13 0:09 UTC (permalink / raw)
To: Rafael J. Wysocki, Vinod Koul
Cc: dmaengine, Timur Tabi, devicetree@vger.kernel.org,
ACPI Devel Maling List, Sakari Ailus, linux-arm-msm,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <CAJZ5v0ijQFO_PuwhBRrKovo4EW9Dck9fiT38wiCw6P5hHUjNuw@mail.gmail.com>
On 12/12/2017 7:36 AM, Rafael J. Wysocki wrote:
> On Tue, Dec 12, 2017 at 6:38 AM, Vinod Koul <vinod.koul@intel.com> wrote:
>> On Thu, Dec 07, 2017 at 04:10:24PM -0500, Sinan Kaya wrote:
>>> Introduce new ACPI and OF device ids for thw HW along with the helper
>>> functions.
>>>
>>> Changes from v6:
>>> * add const to the device callback parameter in fwnode.
>>> * reorganize the callbacks in the code
>>> * rename get_match_data() as device_get_match_data()
>>> * place pointer checks into acpi_get_match_data()
>>
>> This fails for me at 3rd patch. I am on -rc1 is there a dependency?
>
> There shouldn't be any.
>
> According to git, all changes to the files touched by the [3/7] are in
> -rc1 already.
>
Let me know if you were able to resolve the conflict. I can rebase against
a development tree if you can point me to there.
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH 0/2] Bluetooth: Add device tree compatible for TI CC2560
From: David Lechner @ 2017-12-13 0:29 UTC (permalink / raw)
To: devicetree, linux-bluetooth
Cc: David Lechner, Rob Herring, Mark Rutland, Marcel Holtmann,
Johan Hedberg, netdev, linux-kernel
This series updates the bindings TI WiLink 7/8 Bluetooth to add TI CC256x
chips as well. A compatible string is also added to the hci_ll driver for
TI CC2560.
David Lechner (2):
dt-bindings: net: add TI CC2560 Bluetooth chip
Bluetooth: hci_ll: add "ti,cc2560" compatible string
.../bindings/net/{ti,wilink-st.txt => ti-bluetooth.txt} | 13 +++++++++++--
drivers/bluetooth/hci_ll.c | 1 +
2 files changed, 12 insertions(+), 2 deletions(-)
rename Documentation/devicetree/bindings/net/{ti,wilink-st.txt => ti-bluetooth.txt} (78%)
--
2.7.4
^ permalink raw reply
* [PATCH 1/2] dt-bindings: net: add TI CC2560 Bluetooth chip
From: David Lechner @ 2017-12-13 0:29 UTC (permalink / raw)
To: devicetree, linux-bluetooth
Cc: David Lechner, Rob Herring, Mark Rutland, Marcel Holtmann,
Johan Hedberg, netdev, linux-kernel
In-Reply-To: <1513124971-23717-1-git-send-email-david@lechnology.com>
This adds a compatible string for the Texas Instruments CC2560 Bluetooth
chip to the existing TI WiLink shared transport bindings. These chips are
similar enough that the same bindings work for both. The file is renamed
to ti-bluetooth.txt to make it more generic.
Signed-off-by: David Lechner <david@lechnology.com>
---
.../bindings/net/{ti,wilink-st.txt => ti-bluetooth.txt} | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
rename Documentation/devicetree/bindings/net/{ti,wilink-st.txt => ti-bluetooth.txt} (78%)
diff --git a/Documentation/devicetree/bindings/net/ti,wilink-st.txt b/Documentation/devicetree/bindings/net/ti-bluetooth.txt
similarity index 78%
rename from Documentation/devicetree/bindings/net/ti,wilink-st.txt
rename to Documentation/devicetree/bindings/net/ti-bluetooth.txt
index a45a508..6d03ff8 100644
--- a/Documentation/devicetree/bindings/net/ti,wilink-st.txt
+++ b/Documentation/devicetree/bindings/net/ti-bluetooth.txt
@@ -1,10 +1,18 @@
-TI WiLink 7/8 (wl12xx/wl18xx) Shared Transport BT/FM/GPS devices
+Texas Instruments Bluetooth Chips
+---------------------------------
+
+This documents the binding structure and common properties for serial
+attached TI Bluetooth devices. The following chips are included in this
+binding:
+
+* TI CC256x Bluetooth devices
+* TI WiLink 7/8 (wl12xx/wl18xx) Shared Transport BT/FM/GPS devices
TI WiLink devices have a UART interface for providing Bluetooth, FM radio,
and GPS over what's called "shared transport". The shared transport is
standard BT HCI protocol with additional channels for the other functions.
-These devices also have a separate WiFi interface as described in
+TI WiLink devices also have a separate WiFi interface as described in
wireless/ti,wlcore.txt.
This bindings follows the UART slave device binding in
@@ -12,6 +20,7 @@ This bindings follows the UART slave device binding in
Required properties:
- compatible: should be one of the following:
+ "ti,cc2560"
"ti,wl1271-st"
"ti,wl1273-st"
"ti,wl1281-st"
--
2.7.4
^ permalink raw reply related
* [PATCH 2/2] Bluetooth: hci_ll: add "ti,cc2560" compatible string
From: David Lechner @ 2017-12-13 0:29 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA
Cc: David Lechner, Rob Herring, Mark Rutland, Marcel Holtmann,
Johan Hedberg, netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1513124971-23717-1-git-send-email-david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
This adds the "ti,cc2560" compatible string for a TI CC2560 chip.
Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
---
drivers/bluetooth/hci_ll.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/bluetooth/hci_ll.c b/drivers/bluetooth/hci_ll.c
index 9de106f..1b4417a 100644
--- a/drivers/bluetooth/hci_ll.c
+++ b/drivers/bluetooth/hci_ll.c
@@ -842,6 +842,7 @@ static void hci_ti_remove(struct serdev_device *serdev)
}
static const struct of_device_id hci_ti_of_match[] = {
+ { .compatible = "ti,cc2560" },
{ .compatible = "ti,wl1271-st" },
{ .compatible = "ti,wl1273-st" },
{ .compatible = "ti,wl1281-st" },
--
2.7.4
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^ permalink raw reply related
* Re: [PATCH v2 06/13] dt-bindings: mips: Add bindings for Microsemi SoCs
From: Rob Herring @ 2017-12-13 0:44 UTC (permalink / raw)
To: Alexandre Belloni; +Cc: Ralf Baechle, linux-mips, linux-kernel, devicetree
In-Reply-To: <20171208154618.20105-7-alexandre.belloni@free-electrons.com>
On Fri, Dec 08, 2017 at 04:46:11PM +0100, Alexandre Belloni wrote:
> Add bindings for Microsemi SoCs. Currently only Ocelot is supported.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> Documentation/devicetree/bindings/mips/mscc.txt | 46 +++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH V7 0/7] dmaengine: qcom_hidma: add support for bugfixed HW
From: Sinan Kaya @ 2017-12-13 0:44 UTC (permalink / raw)
To: Rafael J. Wysocki, Vinod Koul
Cc: dmaengine, Timur Tabi, devicetree@vger.kernel.org,
ACPI Devel Maling List, Sakari Ailus, linux-arm-msm,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <0ed35958-22c9-50e5-3b6a-732821de6d20@codeaurora.org>
On 12/12/2017 7:09 PM, Sinan Kaya wrote:
> On 12/12/2017 7:36 AM, Rafael J. Wysocki wrote:
>> On Tue, Dec 12, 2017 at 6:38 AM, Vinod Koul <vinod.koul@intel.com> wrote:
>>> On Thu, Dec 07, 2017 at 04:10:24PM -0500, Sinan Kaya wrote:
>>>> Introduce new ACPI and OF device ids for thw HW along with the helper
>>>> functions.
>>>>
>>>> Changes from v6:
>>>> * add const to the device callback parameter in fwnode.
>>>> * reorganize the callbacks in the code
>>>> * rename get_match_data() as device_get_match_data()
>>>> * place pointer checks into acpi_get_match_data()
>>>
>>> This fails for me at 3rd patch. I am on -rc1 is there a dependency?
>>
>> There shouldn't be any.
>>
>> According to git, all changes to the files touched by the [3/7] are in
>> -rc1 already.
>>
>
> Let me know if you were able to resolve the conflict. I can rebase against
> a development tree if you can point me to there.
>
Apparently, my patches were based of 4.14 kernel.
I just rebased to 4.15-rc1.
I can post a new version. Let me know.
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* Re: [PATCH v3 09/33] nds32: Cache and TLB routines
From: Guo Ren @ 2017-12-13 2:16 UTC (permalink / raw)
To: Greentime Hu
Cc: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial,
geert.uytterhoeven, linus.walleij, mark.rutland, greg,
Vincent Chen
In-Reply-To: <9d0e976c3e60bf6834dffb6ef798ad2a03e1c9ac.1512723245.git.green.hu@gmail.com>
On Fri, Dec 08, 2017 at 05:11:52PM +0800, Greentime Hu wrote:
> From: Greentime Hu <greentime@andestech.com>
[...]
> diff --git a/arch/nds32/mm/cacheflush.c b/arch/nds32/mm/cacheflush.c
[...]
> +#ifndef CONFIG_CPU_CACHE_ALIASING
> +void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
> + pte_t * pte)
[...]
> + if (vma->vm_mm == current->active_mm) {
> +
> + __nds32__mtsr_dsb(addr, NDS32_SR_TLB_VPN);
> + __nds32__tlbop_rwr(*pte);
> + __nds32__isb();
If there is an interruption between "mtsr_dsb" and "tlbop_rwr" and a
update_mmu_cache() is invoked again, then an error page mapping is
set up in your tlb-buffer when tlbop_rwr is excuted from interrupt.
Because it's another addr in NDS32_SR_TLB_VPN.
It seems that tlb-hardrefill can help build tlb-buffer mapping, why you
update it in this software way?
Guo Ren
^ permalink raw reply
* RE: [PATCH net-next v5 0/4] net: fec: fix refclk enable for SMSC LAN8710/20
From: Andy Duan @ 2017-12-13 2:21 UTC (permalink / raw)
To: Richard Leitner, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
andrew-g2DYL2Zd6BY@public.gmane.org,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Cc: davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org,
geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org,
sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org,
baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org,
david.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
lukma-ynQEQJNshbs@public.gmane.org,
netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
richard.leitner-WcANXNA0UjBBDgjK7y7TUQ@public.gmane.org
In-Reply-To: <20171211121700.10200-1-dev-M/VWbR8SM2SsTnJN9+BGXg@public.gmane.org>
From: Richard Leitner <dev-M/VWbR8SM2SsTnJN9+BGXg@public.gmane.org> Sent: Monday, December 11, 2017 8:17 PM
>This patch series fixes the use of the SMSC LAN8710/20 with a Freescale ETH
>when the refclk is generated by the FSL.
>
>This patchset depends on the "phylib: Add device reset GPIO support" patch
>submitted by Geert Uytterhoeven/Sergei Shtylyov, which was merged to net-
>next as commit bafbdd527d56 ("phylib: Add device reset GPIO support").
>
>Changes v5:
> - fix reset delay calculation (max_t instead of min_t)
>
>Changes v4:
> - simplify dts parsing
> - simplify reset delay evaluation and execution
> - fec: ensure to only reset once during fec_enet_open()
> - remove dependency notes from commit message
> - add reviews and acks
>
>Changes v3:
> - use phylib to hard-reset the PHY
> - implement reset delays in phylib
> - add new phylib API & flag (PHY_RST_AFTER_CLK_EN) to determine if
> a PHY is affected
>
>Changes v2:
> - simplify and fix fec_reset_phy function to support multiple calls
> - include: linux: phy: harmonize phy_id{,_mask} type
> - reset the phy instead of not turning the clock on and off
> (which would have caused a power consumption regression)
>
>Richard Leitner (4):
> phylib: Add device reset delay support
> phylib: add reset after clk enable support
> net: phy: smsc: LAN8710/20: add PHY_RST_AFTER_CLK_EN flag
> net: fec: add phy_reset_after_clk_enable() support
>
> Documentation/devicetree/bindings/net/phy.txt | 10 ++++++++++
> drivers/net/ethernet/freescale/fec_main.c | 20 ++++++++++++++++++++
> drivers/net/phy/mdio_device.c | 13 +++++++++++--
> drivers/net/phy/phy_device.c | 24 ++++++++++++++++++++++++
> drivers/net/phy/smsc.c | 2 +-
> drivers/of/of_mdio.c | 4 ++++
> include/linux/mdio.h | 2 ++
> include/linux/phy.h | 2 ++
> 8 files changed, 74 insertions(+), 3 deletions(-)
>
>--
>2.11.0
The series look fine better. Thanks.
Acked-by: Fugang Duan <fugang.duan-3arQi8VN3Tc@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH V7 0/7] dmaengine: qcom_hidma: add support for bugfixed HW
From: Vinod Koul @ 2017-12-13 3:19 UTC (permalink / raw)
To: Sinan Kaya
Cc: Rafael J. Wysocki, dmaengine, Timur Tabi,
devicetree@vger.kernel.org, ACPI Devel Maling List, Sakari Ailus,
linux-arm-msm, linux-arm-kernel@lists.infradead.org
In-Reply-To: <9de34cfa-361e-38bf-0c06-ecff0fc26a5c@codeaurora.org>
On Tue, Dec 12, 2017 at 07:44:27PM -0500, Sinan Kaya wrote:
> On 12/12/2017 7:09 PM, Sinan Kaya wrote:
> > On 12/12/2017 7:36 AM, Rafael J. Wysocki wrote:
> >> On Tue, Dec 12, 2017 at 6:38 AM, Vinod Koul <vinod.koul@intel.com> wrote:
> >>> On Thu, Dec 07, 2017 at 04:10:24PM -0500, Sinan Kaya wrote:
> >>>> Introduce new ACPI and OF device ids for thw HW along with the helper
> >>>> functions.
> >>>>
> >>>> Changes from v6:
> >>>> * add const to the device callback parameter in fwnode.
> >>>> * reorganize the callbacks in the code
> >>>> * rename get_match_data() as device_get_match_data()
> >>>> * place pointer checks into acpi_get_match_data()
> >>>
> >>> This fails for me at 3rd patch. I am on -rc1 is there a dependency?
> >>
> >> There shouldn't be any.
> >>
> >> According to git, all changes to the files touched by the [3/7] are in
> >> -rc1 already.
> >>
> >
> > Let me know if you were able to resolve the conflict. I can rebase against
> > a development tree if you can point me to there.
> >
>
> Apparently, my patches were based of 4.14 kernel.
>
> I just rebased to 4.15-rc1.
>
> I can post a new version. Let me know.
Sure that should help
--
~Vinod
^ permalink raw reply
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