* Re: [PATCH 1/3] dt-bindings: chosen: Add clocksource and clockevent selection
From: Boris Brezillon @ 2017-12-14 20:01 UTC (permalink / raw)
To: Rob Herring
Cc: Alexandre Belloni, Mark Rutland, devicetree@vger.kernel.org,
Daniel Lezcano, linux-kernel@vger.kernel.org, Thomas Gleixner,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <CAL_JsqLm5n6s=cr2hBZp4H9pDPKHUOPWs94JMWYFYJ3hsMMxZQ@mail.gmail.com>
Hi Rob,
On Wed, 13 Dec 2017 16:57:50 -0600
Rob Herring <robh+dt@kernel.org> wrote:
> On Wed, Dec 13, 2017 at 12:53 PM, Alexandre Belloni
> <alexandre.belloni@free-electrons.com> wrote:
> > The clocksource and clockevent timer are probed early in the boot process.
> > At that time it is difficult for linux to know whether a particular timer
> > can be used as the clocksource or the clockevent or by another driver,
> > especially when they are all identical or have similar features.
>
> If all identical, then it shouldn't matter. "similar" means some
> difference. Describe those differences.
We had this discussion already. Those timers might be connected to
external pins and may serve the role of PWM generators or capture
devices. We can also chain timers and provide a clocksource with a
better resolution or one that wraps less often. In the end it's all
about how the user plans to use its system, and this has to be
described somehow. Assuming that the software can decide by itself
which timer should be used or how many of them should be chained is
just an utopia.
>
> > Until now, multiple strategies have been used to solve that:
> > - use Kconfig option as MXC_USE_EPIT or ATMEL_TCB_CLKSRC_BLOCK
>
> Compile time probably means only one option is really used.
Compile time selection prevents using the same kernel for different
boards (in other words, no multi-v7), so not really an option here.
>
> > - use a kernel parameter as the "clocksource" early_param in mach-omap2
>
> Yeah, OMAP was one of the previous times this came up and also
> attempted something like this. This parameter predates selecting
> timers based on features described in DT. Look at commit
> 2eb03937df3ebc (ARM: OMAP3: Update clocksource timer selection).
Then, would you accept to have a property saying that a specific timer
is a free-running timer (suitable for clocksource) or a programmable
timer (suitable for clkevent)? Or are you saying that you don't like the
way timers are differentiated on omap?
>
> > - registering the first seen timer as a clockevent and the second one as
> > a clocksource as in rk_timer_init or dw_apb_timer_init
> >
> > Add a linux,clocksource and a linux,clockevent node in chosen with a timer
> > property pointing to the timer to use. Other properties, like the targeted
> > precision may be added later.
>
> Open ended expansion of this does not help convince me it is needed.
It's not an open ended expansion, we're just trying to find a way to
describe which timer blocks should be used as free running timers
(clksource) and which one should be used as programmable timers
(clkevent). Automatically selecting timer blocks to assign to the
clkevent or clocksource is not so easy (as has been explained earlier)
because at the time the system registers its clksource/clkevent devices
we might not have all the necessary information to know which timer
blocks will be reserved for other usage later on. The use case I have
in mind is DT overlays, where one of the overlay is using a timer as a
PWM generator. If the clkevent or clksource has already claimed the
timer connected to the pins the overlay is using, then we're screwed,
and there's no way the system can know that ahead of time except by
pre-assigning a timer to the clksource or clkevent feature.
So really, we need a way to assign a specific timer to a specific
feature. You've refused the different proposals we made so far, so
what's your alternative? I mean a real alternative that solve the "an
auto-selected timer might be claimed by another driver at some point"
problem.
Thanks,
Boris
^ permalink raw reply
* Re: [PATCH v2 6/7] i3c: master: Add driver for Cadence IP
From: Boris Brezillon @ 2017-12-14 20:17 UTC (permalink / raw)
To: Randy Dunlap
Cc: Wolfram Sang, linux-i2c, Jonathan Corbet, linux-doc,
Greg Kroah-Hartman, Arnd Bergmann, Przemyslaw Sroka,
Arkadiusz Golec, Alan Douglas, Bartosz Folta, Damian Kos,
Alicja Jurasik-Urbaniak, Cyprian Wronka, Suresh Punnoose,
Thomas Petazzoni, Nishanth Menon, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala
In-Reply-To: <d0685c1d-a3ed-b3c1-7e3f-b69b02e8a7be@infradead.org>
Hi Randy,
On Thu, 14 Dec 2017 11:54:16 -0800
Randy Dunlap <rdunlap@infradead.org> wrote:
> On 12/14/2017 07:16 AM, Boris Brezillon wrote:
> > Add a driver for Cadence I3C master IP.
> >
> > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> > ---
> > Changes in v2:
> > - Add basic IBI support. Note that the IP is not really reliable with
> > regards to IBI because you can't extract IBI payloads as soon as you
> > have more than one IBI waiting in the HW queue. This is something
> > that will hopefully be addressed in future revisions of this IP
> > - Add a simple xfer queueing mechanism to optimize message queuing.
> > - Fix a few bugs
> > - Add support for Hot Join
> > ---
> > drivers/i3c/master/Kconfig | 5 +
> > drivers/i3c/master/Makefile | 1 +
> > drivers/i3c/master/i3c-master-cdns.c | 1797 ++++++++++++++++++++++++++++++++++
> > 3 files changed, 1803 insertions(+)
> > create mode 100644 drivers/i3c/master/i3c-master-cdns.c
> >
> > diff --git a/drivers/i3c/master/Kconfig b/drivers/i3c/master/Kconfig
> > index e69de29bb2d1..56b9a18543b2 100644
> > --- a/drivers/i3c/master/Kconfig
> > +++ b/drivers/i3c/master/Kconfig
> > @@ -0,0 +1,5 @@
> > +config CDNS_I3C_MASTER
> > + tristate "Cadence I3C master driver"
> > + depends on I3C
> > + help
> > + Enable this driver if you want to support Cadence I3C master block.
> > diff --git a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile
> > index e69de29bb2d1..4c4304aa9534 100644
> > --- a/drivers/i3c/master/Makefile
> > +++ b/drivers/i3c/master/Makefile
> > @@ -0,0 +1 @@
> > +obj-$(CONFIG_CDNS_I3C_MASTER) += i3c-master-cdns.o
> > diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c
> > new file mode 100644
> > index 000000000000..3e3ef37c01c2
> > --- /dev/null
> > +++ b/drivers/i3c/master/i3c-master-cdns.c
> > @@ -0,0 +1,1797 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> > + */
> > +
>
> Rule #1 from submit-checklist.rst:
> 1) If you use a facility then #include the file that defines/declares
> that facility. Don't depend on other header files pulling in ones
> that you use.
>
>
> #include <linux/bitops.h>
> for BIT(x) and hweight8() and clear_bit() and find_next_bit()
> and hweight32()
>
> > +#include <linux/clk.h>
>
> #include <linux/err.h>
> for IS_ERR(), PTR_ERR()
>
> #include <linux/errno.h>
> for error codes
>
> > +#include <linux/i3c/master.h>
> > +#include <linux/interrupt.h>
>
> #include <linux/io.h>
> for writel()
>
> > +#include <linux/iopoll.h>
>
> #include <linux/ioport.h>
> for IORESOURCE_MEM
>
> #include <linux/kernel.h>
> for DIV_ROUND_UP()
>
> #include <linux/list.h>
> for list() macros and INIT_LIST_HEAD()
>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
>
> #include <linux/spinlock.h>
>
> #include <linux/workqueue.h>
> for workqueue functions and INIT_WORK()
Will fix that.
>
> > +
> > +#define DEV_ID 0x0
> > +#define DEV_ID_I3C_MASTER 0x5034
>
> [snip]
>
>
>
> > +#define I3C_DDR_FIRST_DATA_WORD_PREAMBLE 0x2
> > +#define I3C_DDR_DATA_WORD_PREAMBLE 0x3
> > +
> > +#define I3C_DDR_PREAMBLE(p) ((p) << 18)
> > +
> > +static u32 prepare_ddr_word(u16 payload)
> > +{
> > + u32 ret;
> > + u16 pb;
> > +
> > + ret = (u32)payload << 2;
> > +
> > + /* Calculate parity. */
> > + pb = (payload >> 15) ^ (payload >> 13) ^ (payload >> 11) ^
> > + (payload >> 9) ^ (payload >> 7) ^ (payload >> 5) ^
> > + (payload >> 3) ^ (payload >> 1);
> > + ret |= (pb & 1) << 1;
> > + pb = (payload >> 14) ^ (payload >> 12) ^ (payload >> 10) ^
> > + (payload >> 8) ^ (payload >> 6) ^ (payload >> 4) ^
> > + (payload >> 2) ^ payload ^ 1;
> > + ret |= (pb & 1);
> > +
> > + return ret;
> > +}
> > +
> > +static u32 prepare_ddr_data_word(u16 data, bool first)
> > +{
> > + return prepare_ddr_word(data) | I3C_DDR_PREAMBLE(first ? 2 : 3);
>
> Just defined macros for 2 & 3 above. Use them instead of magic numbers?
Oops, that was my intention, just forgot to use the macros I had
defined.
>
> > +}
> > +
> > +#define I3C_DDR_READ_CMD BIT(15)
> > +
> > +static u32 prepare_ddr_cmd_word(u16 cmd)
> > +{
> > + return prepare_ddr_word(cmd) | I3C_DDR_PREAMBLE(1);
> > +}
> > +
> > +static u32 prepare_ddr_crc_word(u8 crc5)
> > +{
> > + return (((u32)crc5 & 0x1f) << 9) | (0xc << 14) |
> > + I3C_DDR_PREAMBLE(1);
> > +}
> > +
> > +static u8 update_crc5(u8 crc5, u16 word)
> > +{
> > + u8 crc0;
> > + int i;
> > +
> > + /*
> > + * crc0 = next_data_bit ^ crc[4]
> > + * 1 2 3 4
> > + * crc[4:0] = { crc[3:2], crc[1]^crc0, crc[0], crc0 }
> > + */
> > + for (i = 0; i < 16; ++i) {
> > + crc0 = ((word >> (15 - i)) ^ (crc5 >> 4)) & 0x1;
> > + crc5 = ((crc5 << 1) & (0x18 | 0x2)) |
> > + (((crc5 >> 1) ^ crc0) << 2) | crc0;
> > + }
> > +
> > + return crc5 & 0x1F;
> > +}
> > +
>
> [snip]
>
>
>
> > +static int cdns_i3c_master_do_daa_locked(struct cdns_i3c_master *master)
> > +{
> > + unsigned long i3c_lim_period, pres_step, i3c_scl_lim;
> > + struct i3c_device_info devinfo;
> > + struct i3c_device *i3cdev;
> > + u32 prescl1, ctrl, devs;
> > + int ret, slot, ncycles;
> > +
> > + ret = i3c_master_entdaa_locked(&master->base);
> > + if (ret)
> > + return ret;
> > +
> > + /* Now, add discovered devices to the bus. */
> > + i3c_scl_lim = master->i3c_scl_lim;
> > + devs = readl(master->regs + DEVS_CTRL);
> > + for (slot = find_next_bit(&master->free_dev_slots, BITS_PER_LONG, 1);
> > + slot < BITS_PER_LONG;
> > + slot = find_next_bit(&master->free_dev_slots,
> > + BITS_PER_LONG, slot + 1)) {
> > + struct cdns_i3c_i2c_dev_data *data;
> > + u32 rr, max_fscl = 0;
> > + u8 addr;
> > +
> > + if (!(devs & DEVS_CTRL_DEV_ACTIVE(slot)))
> > + continue;
> > +
> > + data = kzalloc(sizeof(*data), GFP_KERNEL);
> > + if (!data)
> > + return -ENOMEM;
> > +
> > + data->ibi = -1;
> > + data->id = slot;
> > + rr = readl(master->regs + DEV_ID_RR0(slot));
> > + addr = DEV_ID_RR0_GET_DEV_ADDR(rr);
> > + i3cdev = i3c_master_add_i3c_dev_locked(&master->base, addr);
> > + if (IS_ERR(i3cdev))
> > + return PTR_ERR(i3cdev);
> > +
> > + i3c_device_get_info(i3cdev, &devinfo);
> > + clear_bit(data->id, &master->free_dev_slots);
> > + i3c_device_set_master_data(i3cdev, data);
> > +
> > + max_fscl = max(I3C_CCC_MAX_SDR_FSCL(devinfo.max_read_ds),
> > + I3C_CCC_MAX_SDR_FSCL(devinfo.max_write_ds));
> > + switch (max_fscl) {
> > + case I3C_SDR_DR_FSCL_8MHZ:
> > + max_fscl = 8000000;
> > + break;
> > + case I3C_SDR_DR_FSCL_6MHZ:
> > + max_fscl = 6000000;
> > + break;
> > + case I3C_SDR_DR_FSCL_4MHZ:
> > + max_fscl = 4000000;
> > + break;
> > + case I3C_SDR_DR_FSCL_2MHZ:
> > + max_fscl = 2000000;
> > + break;
> > + case I3C_SDR_DR_FSCL_MAX:
> > + default:
> > + max_fscl = 0;
> > + break;
> > + }
> > +
> > + if (max_fscl && (max_fscl < i3c_scl_lim || !i3c_scl_lim))
> > + i3c_scl_lim = max_fscl;
> > + }
> > +
> > + i3c_master_defslvs_locked(&master->base);
> > +
> > + pres_step = 1000000000 / (master->base.bus->scl_rate.i3c * 4);
>
> Does that build OK on 32-bit target arch?
It's a 32 bit integer divided by another 32 bit integer, and yes, I
tested it on a 32 platform. This being said, I should use NSEC_PER_SEC
instead of 1000000000.
>
> > +
> > + /* No bus limitation to apply, bail out. */
> > + if (!i3c_scl_lim ||
> > + (master->i3c_scl_lim && master->i3c_scl_lim <= i3c_scl_lim))
> > + return 0;
> > +
> > + /* Configure PP_LOW to meet I3C slave limitations. */
> > + prescl1 = readl(master->regs + PRESCL_CTRL1) &
> > + ~PRESCL_CTRL1_PP_LOW_MASK;
> > + ctrl = readl(master->regs + CTRL) & ~CTRL_DEV_EN;
> > +
> > + i3c_lim_period = DIV_ROUND_UP(1000000000, i3c_scl_lim);
> > + ncycles = DIV_ROUND_UP(i3c_lim_period, pres_step) - 4;
> > + if (ncycles < 0)
> > + ncycles = 0;
> > + prescl1 |= PRESCL_CTRL1_PP_LOW(ncycles);
> > +
> > + /* Disable I3C master before updating PRESCL_CTRL1. */
> > + ret = cdns_i3c_master_disable(master);
> > + if (!ret) {
> > + writel(prescl1, master->regs + PRESCL_CTRL1);
> > + master->i3c_scl_lim = i3c_scl_lim;
> > + }
> > + cdns_i3c_master_enable(master);
> > +
> > + return ret;
> > +}
> > +
> > +static int cdns_i3c_master_bus_init(struct i3c_master_controller *m)
> > +{
> > + struct cdns_i3c_master *master = to_cdns_i3c_master(m);
> > + unsigned long pres_step, sysclk_rate, max_i2cfreq;
> > + u32 ctrl, prescl0, prescl1, pres, low;
> > + struct i3c_device_info info = { };
> > + struct i3c_ccc_events events;
> > + struct i2c_device *i2cdev;
> > + struct i3c_device *i3cdev;
> > + int ret, slot, ncycles;
> > + u8 last_addr = 0;
> > +
> > + switch (m->bus->mode) {
> > + case I3C_BUS_MODE_PURE:
> > + ctrl = CTRL_PURE_BUS_MODE;
> > + break;
> > +
> > + case I3C_BUS_MODE_MIXED_FAST:
> > + ctrl = CTRL_MIXED_FAST_BUS_MODE;
> > + break;
> > +
> > + case I3C_BUS_MODE_MIXED_SLOW:
> > + ctrl = CTRL_MIXED_SLOW_BUS_MODE;
> > + break;
> > +
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + sysclk_rate = clk_get_rate(master->sysclk);
> > + if (!sysclk_rate)
> > + return -EINVAL;
> > +
> > + pres = DIV_ROUND_UP(sysclk_rate, (m->bus->scl_rate.i3c * 4)) - 1;
> > + if (pres > PRESCL_CTRL0_MAX)
> > + return -ERANGE;
> > +
> > + m->bus->scl_rate.i3c = sysclk_rate / ((pres + 1) * 4);
> > +
> > + prescl0 = PRESCL_CTRL0_I3C(pres);
> > +
> > + low = ((I3C_BUS_TLOW_OD_MIN_NS * sysclk_rate) / (pres + 1)) - 2;
> > + prescl1 = PRESCL_CTRL1_OD_LOW(low);
> > +
> > + max_i2cfreq = m->bus->scl_rate.i2c;
> > +
> > + pres = (sysclk_rate / (max_i2cfreq * 5)) - 1;
> > + if (pres > PRESCL_CTRL0_MAX)
> > + return -ERANGE;
> > +
> > + m->bus->scl_rate.i2c = sysclk_rate / ((pres + 1) * 5);
> > +
> > + prescl0 |= PRESCL_CTRL0_I2C(pres);
> > +
> > + writel(DEVS_CTRL_DEV_CLR_ALL, master->regs + DEVS_CTRL);
> > +
> > + i3c_bus_for_each_i2cdev(m->bus, i2cdev) {
> > + ret = cdns_i3c_master_attach_i2c_dev(master, i2cdev);
> > + if (ret)
> > + goto err_detach_devs;
> > + }
> > +
> > + writel(prescl0, master->regs + PRESCL_CTRL0);
> > +
> > + /* Calculate OD and PP low. */
> > + pres_step = 1000000000 / (m->bus->scl_rate.i3c * 4);
> > + ncycles = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, pres_step) - 2;
> > + if (ncycles < 0)
> > + ncycles = 0;
> > + prescl1 = PRESCL_CTRL1_OD_LOW(ncycles);
> > + writel(prescl1, master->regs + PRESCL_CTRL1);
> > +
> > + i3c_bus_for_each_i3cdev(m->bus, i3cdev) {
> > + ret = cdns_i3c_master_attach_i3c_dev(master, i3cdev);
> > + if (ret)
> > + goto err_detach_devs;
> > + }
> > +
> > + /* Get an address for the master. */
> > + ret = i3c_master_get_free_addr(m, 0);
> > + if (ret < 0)
> > + goto err_detach_devs;
> > +
> > + writel(prepare_rr0_dev_address(ret) | DEV_ID_RR0_IS_I3C,
> > + master->regs + DEV_ID_RR0(0));
> > +
> > + cdns_i3c_master_dev_rr_to_info(master, 0, &info);
> > + if (info.bcr & I3C_BCR_HDR_CAP)
> > + info.hdr_cap = I3C_CCC_HDR_MODE(I3C_HDR_DDR);
> > +
> > + ret = i3c_master_set_info(&master->base, &info);
> > + if (ret)
> > + goto err_detach_devs;
> > +
> > + /* Prepare RR slots before lauching DAA. */
>
> launching
>
> > + for (slot = find_next_bit(&master->free_dev_slots, BITS_PER_LONG, 1);
> > + slot < BITS_PER_LONG;
> > + slot = find_next_bit(&master->free_dev_slots,
> > + BITS_PER_LONG, slot + 1)) {
> > + ret = i3c_master_get_free_addr(m, last_addr + 1);
> > + if (ret < 0)
> > + goto err_disable_master;
> > +
> > + last_addr = ret;
> > + writel(prepare_rr0_dev_address(last_addr) | DEV_ID_RR0_IS_I3C,
> > + master->regs + DEV_ID_RR0(slot));
> > + writel(0, master->regs + DEV_ID_RR1(slot));
> > + writel(0, master->regs + DEV_ID_RR2(slot));
> > + }
> > +
> > + /*
> > + * Enable Hot-Join and when a Hot-Join request happen, disable all
>
> happens,
>
> > + * events coming from this device.
> > + *
> > + * We will issue ENTDAA afterwards from the threaded IRQ handler.
> > + */
> > + ctrl |= CTRL_HJ_ACK | CTRL_HJ_DISEC | CTRL_HALT_EN;
> > + writel(ctrl, master->regs + CTRL);
> > +
> > + cdns_i3c_master_enable(master);
> > +
> > + /*
> > + * Reset all dynamic addresses on the bus, because we don't know what
> > + * happened before this point (the bootloader may have assigned dynamic
> > + * addresses that we're not aware of).
> > + */
> > + ret = i3c_master_rstdaa_locked(m, I3C_BROADCAST_ADDR);
> > + if (ret)
> > + goto err_disable_master;
> > +
> > + /* Disable all slave events (interrupts) before starting DAA. */
> > + events.events = I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR |
> > + I3C_CCC_EVENT_HJ;
> > + ret = i3c_master_disec_locked(m, I3C_BROADCAST_ADDR, &events);
> > + if (ret)
> > + goto err_disable_master;
> > +
> > + ret = cdns_i3c_master_do_daa_locked(master);
> > + if (ret < 0)
> > + goto err_disable_master;
> > +
> > + /* Unmask Hot-Join and Marstership request interrupts. */
>
> Is that Mastership ?
It is. I'll fix the other typos you pointed.
>
> > + events.events = I3C_CCC_EVENT_HJ | I3C_CCC_EVENT_MR;
> > + ret = i3c_master_enec_locked(m, I3C_BROADCAST_ADDR, &events);
> > + if (ret)
> > + pr_info("Failed to re-enable H-J");
>
> Not very good info...
What do you mean? Is it the H-J that bothers you (I can replace it by
'Hot-Join'), or is it something else?
Thanks for the review.
Boris
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: chosen: Add clocksource and clockevent selection
From: Rob Herring @ 2017-12-14 20:24 UTC (permalink / raw)
To: Boris Brezillon
Cc: Alexandre Belloni, Mark Rutland, devicetree@vger.kernel.org,
Daniel Lezcano, linux-kernel@vger.kernel.org, Thomas Gleixner,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20171214210120.6b436e0d@bbrezillon>
On Thu, Dec 14, 2017 at 2:01 PM, Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
> Hi Rob,
>
> On Wed, 13 Dec 2017 16:57:50 -0600
> Rob Herring <robh+dt@kernel.org> wrote:
>
>> On Wed, Dec 13, 2017 at 12:53 PM, Alexandre Belloni
>> <alexandre.belloni@free-electrons.com> wrote:
>> > The clocksource and clockevent timer are probed early in the boot process.
>> > At that time it is difficult for linux to know whether a particular timer
>> > can be used as the clocksource or the clockevent or by another driver,
>> > especially when they are all identical or have similar features.
>>
>> If all identical, then it shouldn't matter. "similar" means some
>> difference. Describe those differences.
>
> We had this discussion already. Those timers might be connected to
> external pins and may serve the role of PWM generators or capture
> devices. We can also chain timers and provide a clocksource with a
> better resolution or one that wraps less often. In the end it's all
> about how the user plans to use its system, and this has to be
> described somehow. Assuming that the software can decide by itself
> which timer should be used or how many of them should be chained is
> just an utopia.
Anything that an end-user has to tweak shouldn't be in DT. A board should be able to ship with a dtb and a user should be able to change settings without changing the dtb.
>> > Until now, multiple strategies have been used to solve that:
>> > - use Kconfig option as MXC_USE_EPIT or ATMEL_TCB_CLKSRC_BLOCK
>>
>> Compile time probably means only one option is really used.
>
> Compile time selection prevents using the same kernel for different
> boards (in other words, no multi-v7), so not really an option here.
Agreed. I'm saying because of that, that's not really a strong argument that those platforms also need your proposal.
>> > - use a kernel parameter as the "clocksource" early_param in mach-omap2
>>
>> Yeah, OMAP was one of the previous times this came up and also
>> attempted something like this. This parameter predates selecting
>> timers based on features described in DT. Look at commit
>> 2eb03937df3ebc (ARM: OMAP3: Update clocksource timer selection).
>
> Then, would you accept to have a property saying that a specific timer
> is a free-running timer (suitable for clocksource) or a programmable
> timer (suitable for clkevent)? Or are you saying that you don't like the
> way timers are differentiated on omap?
No, I like the OMAP way. However, their properties are properties of the h/w, not how you want to use them.
>> > - registering the first seen timer as a clockevent and the second one as
>> > a clocksource as in rk_timer_init or dw_apb_timer_init
>> >
>> > Add a linux,clocksource and a linux,clockevent node in chosen with a timer
>> > property pointing to the timer to use. Other properties, like the targeted
>> > precision may be added later.
>>
>> Open ended expansion of this does not help convince me it is needed.
>
> It's not an open ended expansion, we're just trying to find a way to
> describe which timer blocks should be used as free running timers
> (clksource) and which one should be used as programmable timers
> (clkevent). Automatically selecting timer blocks to assign to the
> clkevent or clocksource is not so easy (as has been explained earlier)
> because at the time the system registers its clksource/clkevent devices
> we might not have all the necessary information to know which timer
> blocks will be reserved for other usage later on. The use case I have
> in mind is DT overlays, where one of the overlay is using a timer as a
> PWM generator. If the clkevent or clksource has already claimed the
> timer connected to the pins the overlay is using, then we're screwed,
> and there's no way the system can know that ahead of time except by
> pre-assigning a timer to the clksource or clkevent feature.
If the timer can be a pwm, then it should have a #pwm-cells property. Then don't use timers with #pwm-cells property.
> So really, we need a way to assign a specific timer to a specific
> feature. You've refused the different proposals we made so far, so
> what's your alternative? I mean a real alternative that solve the "an
> auto-selected timer might be claimed by another driver at some point"
> problem.
Kernel command line is fine for me.
^ permalink raw reply
* Re: [PATCH v2 6/7] i3c: master: Add driver for Cadence IP
From: Randy Dunlap @ 2017-12-14 20:25 UTC (permalink / raw)
To: Boris Brezillon
Cc: Wolfram Sang, linux-i2c, Jonathan Corbet, linux-doc,
Greg Kroah-Hartman, Arnd Bergmann, Przemyslaw Sroka,
Arkadiusz Golec, Alan Douglas, Bartosz Folta, Damian Kos,
Alicja Jurasik-Urbaniak, Cyprian Wronka, Suresh Punnoose,
Thomas Petazzoni, Nishanth Menon, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala
In-Reply-To: <20171214211722.1c2f269d@bbrezillon>
On 12/14/2017 12:17 PM, Boris Brezillon wrote:
>>> + events.events = I3C_CCC_EVENT_HJ | I3C_CCC_EVENT_MR;
>>> + ret = i3c_master_enec_locked(m, I3C_BROADCAST_ADDR, &events);
>>> + if (ret)
>>> + pr_info("Failed to re-enable H-J");
>> Not very good info...
> What do you mean? Is it the H-J that bothers you (I can replace it by
> 'Hot-Join'), or is it something else?
Who is the message for? If it's for developers, you could use
pr_debug(). If it's for users, it needs more clarity.
Does it print the source of the message? (module name e.g.)
and yes, Hot-Join would be better IMO.
--
~Randy
^ permalink raw reply
* Re: [PATCH v3 3/8] PCI: brcmstb: Add Broadcom STB PCIe host controller driver
From: Jim Quinlan @ 2017-12-14 20:30 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Jim Quinlan, linux-kernel, Bjorn Helgaas, Catalin Marinas,
Will Deacon, Rob Herring, Brian Norris, Russell King,
Robin Murphy, Christoph Hellwig, Florian Fainelli, Jonas Gorski,
Mark Rutland, devicetree, linux-mips, linux-pci, Kevin Cernekee,
Ralf Baechle, bcm-kernel-feedback-list, Gregory Fong,
linux-arm-kernel
In-Reply-To: <20171212221642.GB95453@bhelgaas-glaptop.roam.corp.google.com>
[-- Attachment #1: Type: text/plain, Size: 48913 bytes --]
On Tue, Dec 12, 2017 at 5:16 PM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> On Tue, Nov 14, 2017 at 05:12:07PM -0500, Jim Quinlan wrote:
> > This commit adds the basic Broadcom STB PCIe controller. Missing is
> > the ability to process MSI and also handle dma-ranges for inbound
> > memory accesses. These two functionalities are added in subsequent
> > commits.
> >
> > The PCIe block contains an MDIO interface. This is a local interface
> > only accessible by the PCIe controller. It cannot be used or shared
> > by any other HW. As such, the small amount of code for this
> > controller is included in this driver as there is little upside to put
> > it elsewhere.
> >
> > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > ---
> > drivers/pci/host/Kconfig | 9 +
> > drivers/pci/host/Makefile | 1 +
> > drivers/pci/host/pcie-brcmstb.c | 1124 ++++++++++++++++++++++++++++++
> +++++++++
> > 3 files changed, 1134 insertions(+)
> > create mode 100644 drivers/pci/host/pcie-brcmstb.c
> >
> > diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> > index b868803..751463e 100644
> > --- a/drivers/pci/host/Kconfig
> > +++ b/drivers/pci/host/Kconfig
> > @@ -220,4 +220,13 @@ config VMD
> > To compile this driver as a module, choose M here: the
> > module will be called vmd.
> >
> > +config PCIE_BRCMSTB
> > + tristate "Broadcom Brcmstb PCIe platform host driver"
> > + depends on ARCH_BRCMSTB || BMIPS_GENERIC
> > + depends on OF
> > + depends on SOC_BRCMSTB
> > + default ARCH_BRCMSTB || BMIPS_GENERIC
> > + help
> > + Adds support for Broadcom Settop Box PCIe host controller.
> > +
> > endmenu
> > diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> > index 1238278..a8b9923 100644
> > --- a/drivers/pci/host/Makefile
> > +++ b/drivers/pci/host/Makefile
> > @@ -21,6 +21,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
> > obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> > obj-$(CONFIG_VMD) += vmd.o
> > +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> >
> > # The following drivers are for devices that use the generic ACPI
> > # pci_root.c driver but don't support standard ECAM config access.
> > diff --git a/drivers/pci/host/pcie-brcmstb.c b/drivers/pci/host/pcie-
> brcmstb.c
> > new file mode 100644
> > index 0000000..d8a8f7a
> > --- /dev/null
> > +++ b/drivers/pci/host/pcie-brcmstb.c
> > @@ -0,0 +1,1124 @@
> > +/*
> > + * Copyright (C) 2009 - 2017 Broadcom
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/compiler.h>
> > +#include <linux/delay.h>
> > +#include <linux/init.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/ioport.h>
> > +#include <linux/irqdomain.h>
> > +#include <linux/kernel.h>
> > +#include <linux/list.h>
> > +#include <linux/log2.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_pci.h>
> > +#include <linux/of_pci.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/pci.h>
> > +#include <linux/printk.h>
> > +#include <linux/sizes.h>
> > +#include <linux/slab.h>
> > +#include <soc/brcmstb/memory_api.h>
> > +#include <linux/string.h>
> > +#include <linux/types.h>
> > +
> > +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs
> */
> > +#define BRCM_PCIE_CAP_REGS 0x00ac
>
> Add a blank line before multi-line comments.
>
> > +/*
> > + * Broadcom Settop Box PCIE Register Offsets. The names are from
> > + * the chip's RDB and we use them here so that a script can correlate
> > + * this code and the RDB to prevent discrepancies.
>
> Use "PCIe" capitalization in English text and messages.
>
> > + */
> > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
> > +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
> > +#define PCIE_RC_DL_MDIO_ADDR 0x1100
> > +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
> > +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
> > +#define PCIE_MISC_MISC_CTRL 0x4008
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
> > +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
> > +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
> > +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
> > +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
> > +#define PCIE_MISC_PCIE_CTRL 0x4064
> > +#define PCIE_MISC_PCIE_STATUS 0x4068
> > +#define PCIE_MISC_REVISION 0x406c
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> > +#define PCIE_INTR2_CPU_BASE 0x4300
> > +
> > +/*
> > + * Broadcom Settop Box PCIE Register Field shift and mask info. The
> > + * names are from the chip's RDB and we use them here so that a script
> > + * can correlate this code and the RDB to prevent discrepancies.
> > + */
> > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK
> 0xc
> > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT
> 0x2
> > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
> > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
> > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK
> 0x1000
> > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT
> 0xc
> > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
> > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
> > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK
> 0x300000
> > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
> > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
> > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
> > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
> > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
> > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
> > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
> > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK
> 0x1f
> > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT
> 0x0
> > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK
> 0x1f
> > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT
> 0x0
> > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK
> 0x1f
> > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT
> 0x0
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT
> 0x2
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT
> 0x7
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
> > +#define PCIE_MISC_REVISION_MAJMIN_MASK
> 0xffff
> > +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS
> 0xc
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK
> 0xff
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK
> 0x2
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK
> 0x08000000
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
> > +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
> > +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT
> 0x0
> > +
> > +#define BRCM_NUM_PCIE_OUT_WINS 0x4
> > +#define BRCM_MAX_SCB 0x4
> > +
> > +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
> > +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
> > +
> > +#define BURST_SIZE_128 0
> > +#define BURST_SIZE_256 1
> > +#define BURST_SIZE_512 2
> > +
> > +/* Offsets from PCIE_INTR2_CPU_BASE */
> > +#define STATUS 0x0
> > +#define SET 0x4
> > +#define CLR 0x8
> > +#define MASK_STATUS 0xc
> > +#define MASK_SET 0x10
> > +#define MASK_CLR 0x14
> > +
> > +#define PCIE_BUSNUM_SHIFT 20
> > +#define PCIE_SLOT_SHIFT 15
> > +#define PCIE_FUNC_SHIFT 12
> > +
> > +#if defined(__BIG_ENDIAN)
> > +#define DATA_ENDIAN 2 /* PCIe->DDR inbound
> accesses */
> > +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound accesses */
> > +#else
> > +#define DATA_ENDIAN 0
> > +#define MMIO_ENDIAN 0
> > +#endif
> > +
> > +#define MDIO_PORT0 0x0
> > +#define MDIO_DATA_MASK 0x7fffffff
> > +#define MDIO_DATA_SHIFT 0x0
> > +#define MDIO_PORT_MASK 0xf0000
> > +#define MDIO_PORT_SHIFT 0x16
> > +#define MDIO_REGAD_MASK 0xffff
> > +#define MDIO_REGAD_SHIFT 0x0
> > +#define MDIO_CMD_MASK 0xfff00000
> > +#define MDIO_CMD_SHIFT 0x14
> > +#define MDIO_CMD_READ 0x1
> > +#define MDIO_CMD_WRITE 0x0
> > +#define MDIO_DATA_DONE_MASK 0x80000000
> > +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 :
> 0)
> > +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 :
> 1)
> > +#define SSC_REGS_ADDR 0x1100
> > +#define SET_ADDR_OFFSET 0x1f
> > +#define SSC_CNTL_OFFSET 0x2
> > +#define SSC_CNTL_OVRD_EN_MASK 0x8000
> > +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
> > +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
> > +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
> > +#define SSC_STATUS_OFFSET 0x1
> > +#define SSC_STATUS_SSC_MASK 0x400
> > +#define SSC_STATUS_SSC_SHIFT 0xa
> > +#define SSC_STATUS_PLL_LOCK_MASK 0x800
> > +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
> > +
> > +#define IDX_ADDR(pcie) \
> > + ((pcie)->reg_offsets[EXT_CFG_INDEX])
> > +#define DATA_ADDR(pcie) \
> > + ((pcie)->reg_offsets[EXT_CFG_DATA])
> > +#define PCIE_RGR1_SW_INIT_1(pcie) \
> > + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
> > +
> > +enum {
> > + RGR1_SW_INIT_1,
> > + EXT_CFG_INDEX,
> > + EXT_CFG_DATA,
> > +};
> > +
> > +enum {
> > + RGR1_SW_INIT_1_INIT_MASK,
> > + RGR1_SW_INIT_1_INIT_SHIFT,
> > + RGR1_SW_INIT_1_PERST_MASK,
> > + RGR1_SW_INIT_1_PERST_SHIFT,
> > +};
> > +
> > +enum pcie_type {
> > + BCM7425,
> > + BCM7435,
> > + GENERIC,
> > + BCM7278,
> > +};
> > +
> > +struct brcm_window {
> > + dma_addr_t pcie_addr;
> > + phys_addr_t cpu_addr;
> > + dma_addr_t size;
> > +};
> > +
> > +/* Internal PCIe Host Controller Information.*/
> > +struct brcm_pcie {
> > + struct list_head list;
> > + struct device *dev;
> > + void __iomem *base;
> > + struct list_head resources;
> > + int irq;
> > + struct clk *clk;
> > + struct pci_bus *root_bus;
> > + struct device_node *dn;
> > + int id;
> > + bool suspended;
> > + int num_out_wins;
> > + bool ssc;
> > + int gen;
> > + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
> > + unsigned int rev;
> > + const int *reg_offsets;
> > + const int *reg_field_info;
> > + enum pcie_type type;
> > +};
> > +
> > +struct pcie_cfg_data {
> > + const int *reg_field_info;
> > + const int *offsets;
> > + const enum pcie_type type;
> > +};
> > +
> > +static const int pcie_reg_field_info[] = {
> > + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
> > + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
> > +};
> > +
> > +static const int pcie_reg_field_info_bcm7278[] = {
> > + [RGR1_SW_INIT_1_INIT_MASK] = 0x1,
> > + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x0,
> > +};
> > +
> > +static const int pcie_offset_bcm7425[] = {
> > + [RGR1_SW_INIT_1] = 0x8010,
> > + [EXT_CFG_INDEX] = 0x8300,
> > + [EXT_CFG_DATA] = 0x8304,
> > +};
> > +
> > +static const struct pcie_cfg_data bcm7425_cfg = {
> > + .reg_field_info = pcie_reg_field_info,
> > + .offsets = pcie_offset_bcm7425,
> > + .type = BCM7425,
> > +};
> > +
> > +static const int pcie_offsets[] = {
> > + [RGR1_SW_INIT_1] = 0x9210,
> > + [EXT_CFG_INDEX] = 0x9000,
> > + [EXT_CFG_DATA] = 0x9004,
> > +};
> > +
> > +static const struct pcie_cfg_data bcm7435_cfg = {
> > + .reg_field_info = pcie_reg_field_info,
> > + .offsets = pcie_offsets,
> > + .type = BCM7435,
> > +};
> > +
> > +static const struct pcie_cfg_data generic_cfg = {
> > + .reg_field_info = pcie_reg_field_info,
> > + .offsets = pcie_offsets,
> > + .type = GENERIC,
> > +};
> > +
> > +static const int pcie_offset_bcm7278[] = {
> > + [RGR1_SW_INIT_1] = 0xc010,
> > + [EXT_CFG_INDEX] = 0x9000,
> > + [EXT_CFG_DATA] = 0x9004,
> > +};
> > +
> > +static const struct pcie_cfg_data bcm7278_cfg = {
> > + .reg_field_info = pcie_reg_field_info_bcm7278,
> > + .offsets = pcie_offset_bcm7278,
> > + .type = BCM7278,
> > +};
> > +
> > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned
> int devfn,
> > + int where);
> > +
> > +static struct pci_ops brcm_pcie_ops = {
> > + .map_bus = brcm_pcie_map_conf,
> > + .read = pci_generic_config_read,
> > + .write = pci_generic_config_write,
> > +};
> > +
> > +#if defined(CONFIG_MIPS)
> > +/* Broadcom MIPs HW implicitly does the swapping if necessary */
> > +#define bcm_readl(a) __raw_readl(a)
> > +#define bcm_writel(d, a) __raw_writel(d, a)
> > +#define bcm_readw(a) __raw_readw(a)
> > +#define bcm_writew(d, a) __raw_writew(d, a)
> > +#else
> > +#define bcm_readl(a) readl(a)
> > +#define bcm_writel(d, a) writel(d, a)
> > +#define bcm_readw(a) readw(a)
> > +#define bcm_writew(d, a) writew(d, a)
> > +#endif
> > +
> > +/*
> > + * These macros are designed to sxtract/insert fields to host
> controller's
> > + * register set.
>
> s/are designed to s/ e/ (I assume they actually *do* extract/insert)
>
> > + */
> > +#define RD_FLD(base, reg, field) \
> > + rd_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
> > +#define WR_FLD(base, reg, field, val) \
> > + wr_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT,
> val)
> > +#define WR_FLD_RB(base, reg, field, val) \
> > + wr_fld_rb(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT,
> val)
> > +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
> > + wr_fld(base + reg + off, reg##_##field##_MASK, \
> > + reg##_##field##_SHIFT, val)
> > +#define EXTRACT_FIELD(val, reg, field) \
> > + ((val & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
> > +#define INSERT_FIELD(val, reg, field, field_val) \
> > + ((val & ~reg##_##field##_MASK) | \
> > + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
> > +
> > +static struct list_head brcm_pcie = LIST_HEAD_INIT(brcm_pcie);
> > +static phys_addr_t scb_size[BRCM_MAX_SCB];
> > +static int num_memc;
> > +static DEFINE_MUTEX(brcm_pcie_lock);
> > +
> > +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
> > +{
> > + return (bcm_readl(p) & mask) >> shift;
> > +}
> > +
> > +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
> > +{
> > + u32 reg = bcm_readl(p);
> > +
> > + reg = (reg & ~mask) | ((val << shift) & mask);
> > + bcm_writel(reg, p);
> > +}
> > +
> > +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
> > +{
> > + wr_fld(p, mask, shift, val);
> > + (void)bcm_readl(p);
> > +}
> > +
> > +static const char *link_speed_to_str(int s)
> > +{
> > + switch (s) {
> > + case 1:
> > + return "2.5";
> > + case 2:
> > + return "5.0";
> > + case 3:
> > + return "8.0";
> > + default:
> > + break;
> > + }
> > + return "???";
> > +}
> > +
> > +/*
> > + * The roundup_pow_of_two() from log2.h invokes
> > + * __roundup_pow_of_two(unsigned long), but we really need a
> > + * such a function to take a native u64 since unsigned long
> > + * is 32 bits on some configurations. So we provide this helper
> > + * function below.
> > + */
> > +static u64 roundup_pow_of_two_64(u64 n)
> > +{
> > + return 1ULL << fls64(n - 1);
> > +}
> > +
> > +/*
> > + * This is to convert the size of the inbound bar region to the
> > + * non-liniear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
>
> s/bar/BAR/ (This doesn't sound like a BAR in the PCI spec sense, but if
> that's what you call it, might as well spell it as the acronym)
>
> s/non-liniear/non-linear/
>
> > + */
> > +int encode_ibar_size(u64 size)
> > +{
> > + int log2_in = ilog2(size);
> > +
> > + if (log2_in >= 12 && log2_in <= 15)
> > + /* Covers 4KB to 32KB (inclusive) */
> > + return (log2_in - 12) + 0x1c;
> > + else if (log2_in >= 16 && log2_in <= 37)
> > + /* Covers 64KB to 32GB, (inclusive) */
> > + return log2_in - 15;
> > + /* Something is awry so disable */
> > + return 0;
> > +}
> > +
> > +static u32 mdio_form_pkt(int port, int regad, int cmd)
> > +{
> > + u32 pkt = 0;
> > +
> > + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
> > + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
> > + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
> > +
> > + return pkt;
> > +}
> > +
> > +/* negative return value indicates error */
> > +static int mdio_read(void __iomem *base, u8 port, u8 regad)
> > +{
> > + int tries;
> > + u32 data;
> > +
> > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
> > + base + PCIE_RC_DL_MDIO_ADDR);
> > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > +
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
> > + udelay(10);
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > + }
> > +
> > + return MDIO_RD_DONE(data)
> > + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
> > + : -EIO;
> > +}
> > +
> > +/* negative return value indicates error */
> > +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
> > +{
> > + int tries;
> > + u32 data;
> > +
> > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
> > + base + PCIE_RC_DL_MDIO_ADDR);
> > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
> > + base + PCIE_RC_DL_MDIO_WR_DATA);
> > +
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
> > + udelay(10);
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > + }
> > +
> > + return MDIO_WT_DONE(data) ? 0 : -EIO;
> > +}
> > +
> > +/* configures device for ssc mode; negative return value indicates
> error */
>
> I guess "ssc" means Spread Spectrum Clocking? Maybe spell out the
> first occurrence and spell as acronym in English text?
>
> > +static int set_ssc(void __iomem *base)
> > +{
> > + int tmp;
> > + u16 wrdata;
> > + int pll, ssc;
> > +
> > + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
> > + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
> > + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + usleep_range(1000, 2000);
> > + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
> > + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
> > +
> > + return (ssc && pll) ? 0 : -EIO;
> > +}
> > +
> > +/* limits operation to a specific generation (1, 2, or 3) */
> > +static void set_gen(void __iomem *base, int gen)
> > +{
> > + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS +
> PCI_EXP_LNKCTL2);
> > +
> > + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
> > + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > +
> > + lnkctl2 = (lnkctl2 & ~0xf) | gen;
> > + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> > +}
> > +
> > +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
> > + unsigned int win, phys_addr_t
> cpu_addr,
> > + dma_addr_t pcie_addr, dma_addr_t
> size)
> > +{
> > + void __iomem *base = pcie->base;
> > + phys_addr_t cpu_addr_mb, limit_addr_mb;
> > + u32 tmp;
> > +
> > + /* Set the base of the pcie_addr window */
> > + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
> > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
> > + bcm_writel(upper_32_bits(pcie_addr),
> > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
> > +
> > + cpu_addr_mb = cpu_addr >> 20;
> > + limit_addr_mb = (cpu_addr + size - 1) >> 20;
> > +
> > + /* Write the addr base low register */
> > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > + BASE, cpu_addr_mb);
> > + /* Write the addr limit low register */
> > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > + LIMIT, limit_addr_mb);
> > +
> > + if (pcie->type != BCM7435 && pcie->type != BCM7425) {
> > + /* Write the cpu addr high register */
> > + tmp = (u32)(cpu_addr_mb >>
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_
> BASE_LIMIT_NUM_MASK_BITS);
> > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
> > + BASE, tmp);
> > + /* Write the cpu limit high register */
> > + tmp = (u32)(limit_addr_mb >>
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_
> BASE_LIMIT_NUM_MASK_BITS);
> > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
> > + LIMIT, tmp);
> > + }
> > +}
> > +
> > +/* Configuration space read/write support */
> > +static int cfg_index(int busnr, int devfn, int reg)
> > +{
> > + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
> > + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
> > + | (busnr << PCIE_BUSNUM_SHIFT)
> > + | (reg & ~3);
> > +}
> > +
> > +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > +
> > + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
> > +}
> > +
> > +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS,
> PCIE_DL_ACTIVE);
> > + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS,
> PCIE_PHYLINKUP);
> > +
> > + return (dla && plu) ? true : false;
> > +}
> > +
> > +static bool brcm_pcie_valid_device(struct brcm_pcie *pcie, struct
> pci_bus *bus,
> > + int dev)
> > +{
> > + if (pci_is_root_bus(bus)) {
> > + if (dev > 0)
> > + return false;
> > + } else {
> > + /* If there is no link, then there is no device */
> > + if (!brcm_pcie_link_up(pcie))
> > + return false;
>
> This is racy, since the link can go down after you check but before
> you do the config access. I assume your hardware can deal with a
> config access that targets a link that is down?
>
> > + }
> > +
> > + return true;
> > +}
> > +
> > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned
> int devfn,
> > + int where)
> > +{
> > + struct brcm_pcie *pcie = bus->sysdata;
> > + void __iomem *base = pcie->base;
> > + int idx;
> > +
> > + if (!brcm_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
> > + return NULL;
> > +
> > + /* Accesses to the RC go right to the RC registers */
> > + if (pci_is_root_bus(bus))
> > + return base + where;
> > +
> > + /* For devices, write to the config space index register */
> > + idx = cfg_index(bus->number, devfn, where);
> > + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
> > + return base + DATA_ADDR(pcie) + (where & 0x3);
>
> I guess this is protected by a higher-level config access lock?
>
All pci config space accessor functions --
pci_bus_{read,write}_{byte,word,dword}() -- use a spinlock (pci_lock).
These routines, covered by the spinlock, call pci_generic_{read,write}(),
and those two functions call ops->map_bus(), aka our brcm_pcie_map_conf().
Unless CONFIG_PCI_LOCKLESS_CONFIG is set to "y", which it is not.
> > +}
> > +
> > +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
> > + unsigned int val)
> > +{
> > + unsigned int offset;
> > + unsigned int shift = pcie->reg_field_info[RGR1_SW_
> INIT_1_INIT_SHIFT];
> > + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
> > +
> > + if (pcie->type != BCM7278) {
> > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask,
> shift,
> > + val);
> > + } else if (of_machine_is_compatible("brcm,bcm7278a0")) {
> > + /*
> > + * The two PCIe instances on 7278a0 are not even
> consistent with
> > + * respect to each other for internal offsets, here we
> offset
> > + * by 0x14000 + RGR1_SW_INIT_1's relative offset to
> account for
> > + * that.
> > + */
> > + offset = pcie->id ? 0x14010 : pcie->reg_offsets[RGR1_SW_
> INIT_1];
> > + wr_fld_rb(pcie->base + offset, mask, shift, val);
> > + } else {
> > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask,
> shift,
> > + val);
> > + }
> > +}
> > +
> > +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
> > + unsigned int val)
> > +{
> > + if (pcie->type != BCM7278)
> > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
> > + PCIE_RGR1_SW_INIT_1_PERST_MASK,
> > + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
> > + else
> > + /* Assert = 0, de-assert = 1 on 7278 */
> > + WR_FLD_RB(pcie->base, PCIE_MISC_PCIE_CTRL, PCIE_PERSTB,
> !val);
> > +}
> > +
> > +static int brcm_pcie_add_controller(struct brcm_pcie *pcie)
> > +{
> > + mutex_lock(&brcm_pcie_lock);
> > + list_add_tail(&pcie->list, &brcm_pcie);
> > + mutex_unlock(&brcm_pcie_lock);
> > +
> > + return 0;
> > +}
> > +
> > +static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
> > +{
> > + struct list_head *pos, *q;
> > + struct brcm_pcie *tmp;
> > +
> > + mutex_lock(&brcm_pcie_lock);
> > + list_for_each_safe(pos, q, &brcm_pcie) {
> > + tmp = list_entry(pos, struct brcm_pcie, list);
> > + if (tmp == pcie) {
> > + list_del(pos);
> > + if (list_empty(&brcm_pcie))
> > + num_memc = 0;
> > + break;
> > + }
> > + }
> > + mutex_unlock(&brcm_pcie_lock);
>
> I'm missing something. I don't see that num_memc is ever set to
> anything *other* than zero.
>
> This pattern of keeping a list of controllers is highly unusual and
> needs some explanation.
>
> > +}
> > +
> > +static int brcm_pcie_parse_request_of_pci_ranges(struct brcm_pcie
> *pcie)
> > +{
> > + struct resource_entry *win;
> > + int ret;
> > +
> > + ret = of_pci_get_host_bridge_resources(pcie->dn, 0, 0xff,
> > + &pcie->resources, NULL);
> > + if (ret) {
> > + dev_err(pcie->dev, "failed to get host resources\n");
> > + return ret;
> > + }
> > +
> > + resource_list_for_each_entry(win, &pcie->resources) {
> > + struct resource *parent, *res = win->res;
> > + dma_addr_t offset = (dma_addr_t)win->offset;
> > +
> > + if (resource_type(res) == IORESOURCE_IO) {
> > + parent = &ioport_resource;
> > + } else if (resource_type(res) == IORESOURCE_MEM) {
> > + if (pcie->num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
> > + dev_err(pcie->dev, "too many outbound
> wins\n");
> > + return -EINVAL;
> > + }
> > + pcie->out_wins[pcie->num_out_wins].cpu_addr
> > + = (phys_addr_t)res->start;
> > + pcie->out_wins[pcie->num_out_wins].pcie_addr
> > + = (dma_addr_t)(res->start
> > + - (phys_addr_t)offset);
> > + pcie->out_wins[pcie->num_out_wins].size
> > + = (dma_addr_t)(res->end - res->start + 1);
> > + pcie->num_out_wins++;
> > + parent = &iomem_resource;
> > + } else {
> > + continue;
> > + }
> > +
> > + ret = devm_request_resource(pcie->dev, parent, res);
> > + if (ret) {
> > + dev_err(pcie->dev, "failed to get res %pR\n", res);
> > + return ret;
> > + }
> > + }
> > + return 0;
> > +}
> > +
> > +static int brcm_pcie_setup(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + unsigned int scb_size_val;
> > + u64 rc_bar2_size = 0, rc_bar2_offset = 0, total_mem_size = 0;
>
> Unnecessary initializations (at least of rc_bar2_size, I didn't check
> the rest).
>
> Add
>
> struct device *dev = pcie->dev;
>
> then use it below.
>
> > + u32 tmp, burst;
> > + int i, j, ret, limit;
> > + u16 nlw, cls, lnksta;
> > + bool ssc_good = false;
> > +
> > + /* reset the bridge and the endpoint device */
> > + /* field: PCIE_BRIDGE_SW_INIT = 1 */
>
> Not sure what these "field: ..." comments mean. Are they for some
> automated tool? To a human, it looks like they repeat what the code
> does.
>
> > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > +
> > + /* field: PCIE_SW_PERST = 1, on 7278, we start de-asserted already
> */
> > + if (pcie->type != BCM7278)
> > + brcm_pcie_perst_set(pcie, 1);
> > +
> > + usleep_range(100, 200);
> > +
> > + /* take the bridge out of reset */
> > + /* field: PCIE_BRIDGE_SW_INIT = 0 */
> > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > +
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > + /* wait for serdes to be stable */
> > + usleep_range(100, 200);
> > +
> > + /* Grab the PCIe hw revision number */
> > + tmp = bcm_readl(base + PCIE_MISC_REVISION);
> > + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
> > +
> > + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
> > + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
> > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
> > + burst = (pcie->type == GENERIC || pcie->type == BCM7278)
> > + ? BURST_SIZE_512 : BURST_SIZE_256;
> > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE,
> burst);
> > + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
> > +
> > + /*
> > + * Set up inbound memory view for the EP (called RC_BAR2,
> > + * not to be confused with the BARs that are advertised by
> > + * the EP).
> > + */
> > + for (i = 0; i < num_memc; i++)
> > + total_mem_size += scb_size[i];
> > +
> > + /*
> > + * The PCIe host controller by design must set the inbound
> > + * viewport to be a contiguous arrangement of all of the
> > + * system's memory. In addition, its size mut be a power of
> > + * two. To further complicate matters, the viewport must
> > + * start on a pcie-address that is aligned on a multiple of its
> > + * size. If a portion of the viewport does not represent
> > + * system memory -- e.g. 3GB of memory requires a 4GB viewport
> > + * -- we can map the outbound memory in or after 3GB and even
> > + * though the viewport will overlap the outbound memory the
> > + * controller will know to send outbound memory downstream and
> > + * everything else upstream.
> > + */
> > + rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
> > +
> > + /*
> > + * Set simple configuration based on memory sizes
> > + * only. We always start the viewport at address 0.
> > + */
> > + rc_bar2_offset = 0;
> > +
> > + tmp = lower_32_bits(rc_bar2_offset);
> > + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> > + encode_ibar_size(rc_bar2_size));
> > + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
> > + bcm_writel(upper_32_bits(rc_bar2_offset),
> > + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
> > +
> > + /* field: SCB0_SIZE, default = 0xf (1 GB) */
> > + scb_size_val = scb_size[0]
> > + ? ilog2(scb_size[0]) - 15 : 0xf;
> > + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
> > +
> > + /* field: SCB1_SIZE, default = 0xf (1 GB) */
> > + if (num_memc > 1) {
> > + scb_size_val = scb_size[1]
> > + ? ilog2(scb_size[1]) - 15 : 0xf;
> > + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB1_SIZE, scb_size_val);
> > + }
> > +
> > + /* field: SCB2_SIZE, default = 0xf (1 GB) */
> > + if (num_memc > 2) {
> > + scb_size_val = scb_size[2]
> > + ? ilog2(scb_size[2]) - 15 : 0xf;
> > + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB2_SIZE, scb_size_val);
> > + }
> > +
> > + /* disable the PCIe->GISB memory window (RC_BAR1) */
> > + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
> > +
> > + /* disable the PCIe->SCB memory window (RC_BAR3) */
> > + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
> > +
> > + if (!pcie->suspended) {
> > + /* clear any interrupts we find on boot */
> > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
> > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
> > + }
> > +
> > + /* Mask all interrupts since we are not handling any yet */
> > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > +
> > + if (pcie->gen)
> > + set_gen(base, pcie->gen);
> > +
> > + /* take the EP device out of reset */
> > + /* field: PCIE_SW_PERST = 0 */
> > + brcm_pcie_perst_set(pcie, 0);
>
> <raises eyebrows> Take the *EP* out of reset? The host controller
> driver shouldn't be touching an EP directly. Maybe the comment
> doesn't match what the code actually does.
>
> > +
> > + /*
> > + * Give the RC/EP time to wake up, before trying to configure RC.
> > + * Intermittently check status for link-up, up to a total of 100ms
> > + * when we don't know if the device is there, and up to 1000ms if
> > + * we do know the device is there.
> > + */
> > + limit = pcie->suspended ? 1000 : 100;
> > + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
> > + j += i, i = i * 2)
> > + msleep(i + j > limit ? limit - j : i);
> > +
> > + if (!brcm_pcie_link_up(pcie)) {
> > + dev_info(pcie->dev, "link down\n");
> > + return -ENODEV;
> > + }
> > +
> > + if (!brcm_pcie_rc_mode(pcie)) {
> > + dev_err(pcie->dev, "PCIe misconfigured; is in EP mode\n");
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < pcie->num_out_wins; i++)
> > + brcm_pcie_set_outbound_win(pcie, i,
> pcie->out_wins[i].cpu_addr,
> > + pcie->out_wins[i].pcie_addr,
> > + pcie->out_wins[i].size);
> > +
> > + /*
> > + * For config space accesses on the RC, show the right class for
> > + * a PCIe-PCIe bridge (the default setting is to be EP mode).
> > + */
> > + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
> > +
> > + if (pcie->ssc) {
> > + ret = set_ssc(base);
> > + if (ret == 0)
> > + ssc_good = true;
> > + else
> > + dev_err(pcie->dev,
> > + "failed attempt to enter ssc mode\n");
> > + }
> > +
> > + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
> > + cls = lnksta & PCI_EXP_LNKSTA_CLS;
> > + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
> > + dev_info(pcie->dev, "link up, %s Gbps x%u %s\n",
> link_speed_to_str(cls),
> > + nlw, ssc_good ? "(SSC)" : "(!SSC)");
> > +
> > + /* PCIe->SCB endian mode for BAR */
> > + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
> > + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
> > + ENDIAN_MODE_BAR2, DATA_ENDIAN);
> > +
> > + /*
> > + * Refclk from RC should be gated with CLKREQ# input when ASPM
> L0s,L1
> > + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
> > + */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG,
> CLKREQ_DEBUG_ENABLE, 1);
> > +
> > + return 0;
> > +}
> > +
> > +static void enter_l23(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + int tries, l23;
> > +
> > + /* assert request for L23 */
> > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
> > + /* poll L23 status */
> > + for (tries = 0, l23 = 0; tries < 1000 && !l23; tries++)
> > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS,
> PCIE_LINK_IN_L23);
> > + if (!l23)
> > + dev_err(pcie->dev, "failed to enter L23\n");
>
> What does "L23" mean? Some power management thing?
>
> > +}
> > +
> > +static void turn_off(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > +
> > + if (brcm_pcie_link_up(pcie))
> > + enter_l23(pcie);
> > + /* Reset endpoint device */
> > + brcm_pcie_perst_set(pcie, 1);
> > + /* deassert request for L23 in case it was asserted */
> > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
> > + /* SERDES_IDDQ = 1 */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
> > + /* Shutdown PCIe bridge */
> > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > +}
> > +
> > +static int brcm_pcie_suspend(struct device *dev)
> > +{
> > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > +
> > + turn_off(pcie);
> > + clk_disable_unprepare(pcie->clk);
> > + pcie->suspended = true;
> > +
> > + return 0;
> > +}
> > +
> > +static int brcm_pcie_resume(struct device *dev)
> > +{
> > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > + void __iomem *base;
> > + int ret;
> > +
> > + base = pcie->base;
> > + clk_prepare_enable(pcie->clk);
> > +
> > + /* Take bridge out of reset so we can access the SERDES reg */
>
> Some comments above and below spell it "serdes"; here you spell it
> "SERDES".
>
> > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > +
> > + /* SERDES_IDDQ = 0 */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > + /* wait for serdes to be stable */
> > + usleep_range(100, 200);
> > +
> > + ret = brcm_pcie_setup(pcie);
> > + if (ret)
> > + return ret;
> > +
> > + pcie->suspended = false;
> > +
> > + return 0;
> > +}
> > +
> > +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
> > +{
> > + turn_off(pcie);
> > + clk_disable_unprepare(pcie->clk);
> > + clk_put(pcie->clk);
> > + brcm_pcie_remove_controller(pcie);
> > +}
> > +
> > +static int brcm_pcie_remove(struct platform_device *pdev)
> > +{
> > + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
> > +
> > + pci_stop_root_bus(pcie->root_bus);
> > + pci_remove_root_bus(pcie->root_bus);
> > + _brcm_pcie_remove(pcie);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id brcm_pcie_match[] = {
> > + { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
> > + { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
> > + { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
> > + { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
> > +
> > +static int brcm_pcie_probe(struct platform_device *pdev)
> > +{
> > + struct device_node *dn = pdev->dev.of_node;
> > + const struct of_device_id *of_id;
> > + const struct pcie_cfg_data *data;
> > + int ret;
> > + struct brcm_pcie *pcie;
> > + struct resource *res;
> > + void __iomem *base;
> > + u32 tmp;
> > + struct pci_host_bridge *bridge;
> > + struct pci_bus *child;
> > +
> > + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
> > + if (!bridge)
> > + return -ENOMEM;
> > +
> > + pcie = pci_host_bridge_priv(bridge);
> > + INIT_LIST_HEAD(&pcie->resources);
> > +
> > + of_id = of_match_node(brcm_pcie_match, dn);
> > + if (!of_id) {
> > + dev_err(&pdev->dev, "failed to look up compatible
> string\n");
> > + return -EINVAL;
> > + }
> > +
> > + if (of_property_read_u32(dn, "dma-ranges", &tmp) == 0) {
> > + dev_err(&pdev->dev, "cannot yet handle dma-ranges\n");
> > + return -EINVAL;
> > + }
> > +
> > + data = of_id->data;
> > + pcie->reg_offsets = data->offsets;
> > + pcie->reg_field_info = data->reg_field_info;
> > + pcie->type = data->type;
> > + pcie->dn = dn;
> > + pcie->dev = &pdev->dev;
> > +
> > + pcie->id = of_get_pci_domain_nr(dn);
>
> Why do you call of_get_pci_domain_nr() directly? No other driver
> does.
>
> > + if (pcie->id < 0)
> > + return pcie->id;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res)
> > + return -EINVAL;
> > +
> > + base = devm_ioremap_resource(&pdev->dev, res);
> > + if (IS_ERR(base))
> > + return PTR_ERR(base);
> > +
> > + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
> > + if (IS_ERR(pcie->clk)) {
> > + dev_err(&pdev->dev, "could not get clock\n");
> > + pcie->clk = NULL;
> > + }
> > + pcie->base = base;
> > +
> > + ret = of_pci_get_max_link_speed(dn);
> > + pcie->gen = (ret < 0) ? 0 : ret;
> > +
> > + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
> > +
> > + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
> > + if (ret == 0)
> > + /* keep going, as we don't use this intr yet */
> > + dev_warn(pcie->dev, "cannot get pcie interrupt\n");
> > + else
> > + pcie->irq = ret;
> > +
> > + ret = brcm_pcie_parse_request_of_pci_ranges(pcie);
> > + if (ret)
> > + return ret;
> > +
> > + ret = clk_prepare_enable(pcie->clk);
> > + if (ret) {
> > + dev_err(&pdev->dev, "could not enable clock\n");
> > + return ret;
> > + }
> > +
> > + ret = brcm_pcie_add_controller(pcie);
> > + if (ret)
> > + return ret;
> > +
> > + ret = brcm_pcie_setup(pcie);
> > + if (ret)
> > + goto fail;
> > +
> > + list_splice_init(&pcie->resources, &bridge->windows);
> > + bridge->dev.parent = &pdev->dev;
> > + bridge->busnr = 0;
> > + bridge->ops = &brcm_pcie_ops;
> > + bridge->sysdata = pcie;
> > + bridge->map_irq = of_irq_parse_and_map_pci;
> > + bridge->swizzle_irq = pci_common_swizzle;
> > +
> > + ret = pci_scan_root_bus_bridge(bridge);
> > + if (ret < 0) {
> > + dev_err(pcie->dev, "Scanning root bridge failed");
> > + goto fail;
> > + }
> > +
> > + pci_assign_unassigned_bus_resources(bridge->bus);
> > + list_for_each_entry(child, &bridge->bus->children, node)
> > + pcie_bus_configure_settings(child);
> > + pci_bus_add_devices(bridge->bus);
> > + platform_set_drvdata(pdev, pcie);
> > + pcie->root_bus = bridge->bus;
> > +
> > + return 0;
> > +
> > +fail:
> > + _brcm_pcie_remove(pcie);
> > + return ret;
> > +}
> > +
> > +static const struct dev_pm_ops brcm_pcie_pm_ops = {
> > + .suspend_noirq = brcm_pcie_suspend,
> > + .resume_noirq = brcm_pcie_resume,
> > +};
> > +
> > +static struct platform_driver __refdata brcm_pcie_driver = {
>
> Why do you need __refdata? There's only only other occurrence in
> drivers/pci, and I'm dubious about that one as well.
>
> > + .probe = brcm_pcie_probe,
> > + .remove = brcm_pcie_remove,
> > + .driver = {
> > + .name = "brcm-pcie",
> > + .owner = THIS_MODULE,
> > + .of_match_table = brcm_pcie_match,
> > + .pm = &brcm_pcie_pm_ops,
> > + },
> > +};
> > +
> > +module_platform_driver(brcm_pcie_driver);
> > +
> > +MODULE_LICENSE("GPL");
>
> Copyright notice above says "GPL v2", which is not the same as the
> "GPL" here.
>
> > +MODULE_DESCRIPTION("Broadcom STB PCIE RC driver");
> > +MODULE_AUTHOR("Broadcom");
> > --
> > 1.9.0.138.g2de3478
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
[-- Attachment #2: Type: text/html, Size: 64116 bytes --]
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: chosen: Add clocksource and clockevent selection
From: Boris Brezillon @ 2017-12-14 20:37 UTC (permalink / raw)
To: Rob Herring
Cc: Alexandre Belloni, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Daniel Lezcano,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Thomas Gleixner,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <20171214210120.6b436e0d@bbrezillon>
On Thu, 14 Dec 2017 21:01:20 +0100
Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Hi Rob,
>
> On Wed, 13 Dec 2017 16:57:50 -0600
> Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>
> > On Wed, Dec 13, 2017 at 12:53 PM, Alexandre Belloni
> > <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> > > The clocksource and clockevent timer are probed early in the boot process.
> > > At that time it is difficult for linux to know whether a particular timer
> > > can be used as the clocksource or the clockevent or by another driver,
> > > especially when they are all identical or have similar features.
> >
> > If all identical, then it shouldn't matter. "similar" means some
> > difference. Describe those differences.
>
> We had this discussion already. Those timers might be connected to
> external pins and may serve the role of PWM generators or capture
> devices. We can also chain timers and provide a clocksource with a
> better resolution or one that wraps less often. In the end it's all
> about how the user plans to use its system, and this has to be
> described somehow. Assuming that the software can decide by itself
> which timer should be used or how many of them should be chained is
> just an utopia.
>
> >
> > > Until now, multiple strategies have been used to solve that:
> > > - use Kconfig option as MXC_USE_EPIT or ATMEL_TCB_CLKSRC_BLOCK
> >
> > Compile time probably means only one option is really used.
>
> Compile time selection prevents using the same kernel for different
> boards (in other words, no multi-v7), so not really an option here.
>
> >
> > > - use a kernel parameter as the "clocksource" early_param in mach-omap2
> >
> > Yeah, OMAP was one of the previous times this came up and also
> > attempted something like this. This parameter predates selecting
> > timers based on features described in DT. Look at commit
> > 2eb03937df3ebc (ARM: OMAP3: Update clocksource timer selection).
>
> Then, would you accept to have a property saying that a specific timer
> is a free-running timer (suitable for clocksource) or a programmable
> timer (suitable for clkevent)? Or are you saying that you don't like the
> way timers are differentiated on omap?
>
> >
> > > - registering the first seen timer as a clockevent and the second one as
> > > a clocksource as in rk_timer_init or dw_apb_timer_init
> > >
> > > Add a linux,clocksource and a linux,clockevent node in chosen with a timer
> > > property pointing to the timer to use. Other properties, like the targeted
> > > precision may be added later.
> >
> > Open ended expansion of this does not help convince me it is needed.
>
> It's not an open ended expansion, we're just trying to find a way to
> describe which timer blocks should be used as free running timers
> (clksource) and which one should be used as programmable timers
> (clkevent). Automatically selecting timer blocks to assign to the
> clkevent or clocksource is not so easy (as has been explained earlier)
> because at the time the system registers its clksource/clkevent devices
> we might not have all the necessary information to know which timer
> blocks will be reserved for other usage later on. The use case I have
> in mind is DT overlays, where one of the overlay is using a timer as a
> PWM generator. If the clkevent or clksource has already claimed the
> timer connected to the pins the overlay is using, then we're screwed,
> and there's no way the system can know that ahead of time except by
> pre-assigning a timer to the clksource or clkevent feature.
>
> So really, we need a way to assign a specific timer to a specific
> feature. You've refused the different proposals we made so far, so
> what's your alternative? I mean a real alternative that solve the "an
> auto-selected timer might be claimed by another driver at some point"
> problem.
Okay, it seems I was wrong, you already agreed on a generic
atmel,tcb-timer compatible [1], so it seems the only thing we're missing
is a way to assign a timer to a clocksource or a clkevent.
[1]https://patchwork.kernel.org/patch/9755341/
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^ permalink raw reply
* Re: DT dtc warnings
From: Krzysztof Kozlowski @ 2017-12-14 20:40 UTC (permalink / raw)
To: Rob Herring
Cc: Barry Song, Kukjin Kim, Maxime Ripard, Chen-Yu Tsai,
Nicolas Ferre, Alexandre Belloni, Patrice Chotard, Peter Rosin,
Santosh Shilimkar, arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Mathieu Malaterre
In-Reply-To: <CAL_JsqJKCzjx3zNigu_0T=Ku=_P2SQEjTx=uVbvr_QxJQR7kYg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Thu, Dec 14, 2017 at 7:21 PM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> Hi all,
>
> Below is a current list of ARM boards with more than 40 dtc warnings
> when building with W=1. There's a treewide patch in flight to fix some
> unit-address warnings[1], so those aren't included here. The list is
> grouped by maintainer. AT91, Exynos, and Allwinner continue to be at
> the top of the list and have been for some time (though having
> multiple boards for an SoC can cause lots of duplicated warnings).
>
> Please help fix these. More checks are being added[2].
>
> Rob
>
> [1] https://patchwork.kernel.org/patch/10112725/
> [2] https://www.spinics.net/lists/devicetree-compiler/msg01620.html
>
>
> 77 - arch/arm/boot/dts/prima2-evb.dts
>
> 50 - arch/arm/boot/dts/exynos5250-arndale.dts
> 50 - arch/arm/boot/dts/exynos5250-smdk5250.dts
> 50 - arch/arm/boot/dts/exynos5250-snow.dts
> 50 - arch/arm/boot/dts/exynos5250-snow-rev5.dts
> 50 - arch/arm/boot/dts/exynos5250-spring.dts
> 71 - arch/arm/boot/dts/exynos5420-arndale-octa.dts
> 71 - arch/arm/boot/dts/exynos5420-peach-pit.dts
> 71 - arch/arm/boot/dts/exynos5420-smdk5420.dts
> 71 - arch/arm/boot/dts/exynos5422-odroidhc1.dts
> 71 - arch/arm/boot/dts/exynos5422-odroidxu3.dts
> 71 - arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> 71 - arch/arm/boot/dts/exynos5422-odroidxu4.dts
> 71 - arch/arm/boot/dts/exynos5800-peach-pi.dts
>
Sure, I can take care of this but in such case it would be better if
Mathieu's (+Cc) patch would be split per-subarch maintainer. I can
base my patch on top of his... but there might be conflicts when
applying to my tree.
Different topic - why not enabling these warnings by default?
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v2 6/7] i3c: master: Add driver for Cadence IP
From: Boris Brezillon @ 2017-12-14 20:44 UTC (permalink / raw)
To: Randy Dunlap
Cc: Wolfram Sang, linux-i2c, Jonathan Corbet, linux-doc,
Greg Kroah-Hartman, Arnd Bergmann, Przemyslaw Sroka,
Arkadiusz Golec, Alan Douglas, Bartosz Folta, Damian Kos,
Alicja Jurasik-Urbaniak, Cyprian Wronka, Suresh Punnoose,
Thomas Petazzoni, Nishanth Menon, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala
In-Reply-To: <8245f2de-eb0a-319b-8f45-d8d5dac36239@infradead.org>
On Thu, 14 Dec 2017 12:25:14 -0800
Randy Dunlap <rdunlap@infradead.org> wrote:
> On 12/14/2017 12:17 PM, Boris Brezillon wrote:
> >>> + events.events = I3C_CCC_EVENT_HJ | I3C_CCC_EVENT_MR;
> >>> + ret = i3c_master_enec_locked(m, I3C_BROADCAST_ADDR, &events);
> >>> + if (ret)
> >>> + pr_info("Failed to re-enable H-J");
> >> Not very good info...
> > What do you mean? Is it the H-J that bothers you (I can replace it by
> > 'Hot-Join'), or is it something else?
>
> Who is the message for? If it's for developers, you could use
> pr_debug(). If it's for users, it needs more clarity.
I think it's of interest to anyone including users. If we fail to
re-enable Hot-Join that means hotplug is no longer working which is
a bad news.
>
> Does it print the source of the message? (module name e.g.)
I could replace it by
dev_err(m->parent, "Failed to re-enable Hot-Join");
> and yes, Hot-Join would be better IMO.
>
^ permalink raw reply
* Re: DT dtc warnings
From: Santosh Shilimkar @ 2017-12-14 20:50 UTC (permalink / raw)
To: Rob Herring, Barry Song, Kukjin Kim, Krzysztof Kozlowski,
Maxime Ripard, Chen-Yu Tsai, Nicolas Ferre, Alexandre Belloni,
Patrice Chotard, Peter Rosin, Santosh Shilimkar,
arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Nishanth Menon
In-Reply-To: <CAL_JsqJKCzjx3zNigu_0T=Ku=_P2SQEjTx=uVbvr_QxJQR7kYg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hui Rob,
12/14/2017 10:21 AM, Rob Herring wrote:
> Hi all,
>
> Below is a current list of ARM boards with more than 40 dtc warnings
> when building with W=1. There's a treewide patch in flight to fix some
> unit-address warnings[1], so those aren't included here. The list is
> grouped by maintainer. AT91, Exynos, and Allwinner continue to be at
> the top of the list and have been for some time (though having
> multiple boards for an SoC can cause lots of duplicated warnings).
>
> Please help fix these. More checks are being added[2].
>
[...]
>
> 52 - arch/arm/boot/dts/keystone-k2e-evm.dts
> 73 - arch/arm/boot/dts/keystone-k2l-evm.dts
> 97 - arch/arm/boot/dts/keystone-k2hk-evm.dts
>
Nishant is going to help me to address keystone ones.
Regards,
Santosh
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^ permalink raw reply
* Re: DT dtc warnings
From: Krzysztof Kozlowski @ 2017-12-14 21:01 UTC (permalink / raw)
To: Rob Herring
Cc: Barry Song, Kukjin Kim, Maxime Ripard, Chen-Yu Tsai,
Nicolas Ferre, Alexandre Belloni, Patrice Chotard, Peter Rosin,
Santosh Shilimkar, arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Mathieu Malaterre
In-Reply-To: <CAJKOXPc7M3jeV_hNBBRJKGs3vtNzdrGbW_YETw2n0fXxhqjZ_g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Thu, Dec 14, 2017 at 9:40 PM, Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Thu, Dec 14, 2017 at 7:21 PM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>> Hi all,
>>
>> Below is a current list of ARM boards with more than 40 dtc warnings
>> when building with W=1. There's a treewide patch in flight to fix some
>> unit-address warnings[1], so those aren't included here. The list is
>> grouped by maintainer. AT91, Exynos, and Allwinner continue to be at
>> the top of the list and have been for some time (though having
>> multiple boards for an SoC can cause lots of duplicated warnings).
>>
>> Please help fix these. More checks are being added[2].
>>
>> Rob
>>
>> [1] https://patchwork.kernel.org/patch/10112725/
>> [2] https://www.spinics.net/lists/devicetree-compiler/msg01620.html
>>
>>
>> 77 - arch/arm/boot/dts/prima2-evb.dts
>>
>> 50 - arch/arm/boot/dts/exynos5250-arndale.dts
>> 50 - arch/arm/boot/dts/exynos5250-smdk5250.dts
>> 50 - arch/arm/boot/dts/exynos5250-snow.dts
>> 50 - arch/arm/boot/dts/exynos5250-snow-rev5.dts
>> 50 - arch/arm/boot/dts/exynos5250-spring.dts
>> 71 - arch/arm/boot/dts/exynos5420-arndale-octa.dts
>> 71 - arch/arm/boot/dts/exynos5420-peach-pit.dts
>> 71 - arch/arm/boot/dts/exynos5420-smdk5420.dts
>> 71 - arch/arm/boot/dts/exynos5422-odroidhc1.dts
>> 71 - arch/arm/boot/dts/exynos5422-odroidxu3.dts
>> 71 - arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
>> 71 - arch/arm/boot/dts/exynos5422-odroidxu4.dts
>> 71 - arch/arm/boot/dts/exynos5800-peach-pi.dts
>>
>
> Sure, I can take care of this but in such case it would be better if
> Mathieu's (+Cc) patch would be split per-subarch maintainer. I can
> base my patch on top of his... but there might be conflicts when
> applying to my tree.
>
> Different topic - why not enabling these warnings by default?
Can anyone help why this W=1 triggers warning like these:
arch/arm/boot/dts/exynos3250-artik5-eval.dtb: Warning
(simple_bus_reg): Node /soc/syscon-poweroff missing or empty
reg/ranges property
arch/arm/boot/dts/exynos3250-artik5-eval.dtb: Warning
(simple_bus_reg): Node /soc/syscon-reboot missing or empty reg/ranges
property
For a node without unit address?
http://elixir.free-electrons.com/linux/v4.15-rc3/source/arch/arm/boot/dts/exynos-syscon-restart.dtsi
AFAIR, if node does not have unit-address then it should not have
reg/ranges property. Or maybe it is coming from parent's simple-bus?
Best regards,
Krzysztof
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^ permalink raw reply
* [PATCH] ARM: dts: exynos: Use lower case hex addresses in node names
From: Krzysztof Kozlowski @ 2017-12-14 21:02 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Kukjin Kim,
Krzysztof Kozlowski, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Cc: Mathieu Malaterre
Convert all hex addresses in node names to lower case to fix warnings
like:
arch/arm/boot/dts/exynos5422-odroidhc1.dtb: Warning (simple_bus_reg):
Node /soc/nocp@10CA1000 simple-bus unit address format error, expected "10ca1000"
Conversion was done using sed:
$ sed -e 's/@\(.*\) {/@\L\1 {/' -i arch/arm/boot/dts/exynos*.dts*
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++--------
arch/arm/boot/dts/exynos4.dtsi | 56 +++++++++++++-------------
arch/arm/boot/dts/exynos4210.dtsi | 8 ++--
arch/arm/boot/dts/exynos4412-pinctrl.dtsi | 2 +-
arch/arm/boot/dts/exynos4412.dtsi | 22 +++++------
arch/arm/boot/dts/exynos5.dtsi | 22 +++++------
arch/arm/boot/dts/exynos5250.dtsi | 66 +++++++++++++++----------------
arch/arm/boot/dts/exynos5260.dtsi | 26 ++++++------
arch/arm/boot/dts/exynos5420.dtsi | 44 ++++++++++-----------
arch/arm/boot/dts/exynos5440.dtsi | 14 +++----
10 files changed, 147 insertions(+), 147 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 2bd3872221a1..8d47571b3984 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -164,31 +164,31 @@
syscon = <&pmu_system_controller>;
};
- pd_cam: cam-power-domain@10023C00 {
+ pd_cam: cam-power-domain@10023c00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C00 0x20>;
#power-domain-cells = <0>;
};
- pd_mfc: mfc-power-domain@10023C40 {
+ pd_mfc: mfc-power-domain@10023c40 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C40 0x20>;
#power-domain-cells = <0>;
};
- pd_g3d: g3d-power-domain@10023C60 {
+ pd_g3d: g3d-power-domain@10023c60 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C60 0x20>;
#power-domain-cells = <0>;
};
- pd_lcd0: lcd0-power-domain@10023C80 {
+ pd_lcd0: lcd0-power-domain@10023c80 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C80 0x20>;
#power-domain-cells = <0>;
};
- pd_isp: isp-power-domain@10023CA0 {
+ pd_isp: isp-power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
#power-domain-cells = <0>;
@@ -204,7 +204,7 @@
<&cmu CLK_FIN_PLL>;
};
- cmu_dmc: clock-controller@105C0000 {
+ cmu_dmc: clock-controller@105c0000 {
compatible = "samsung,exynos3250-cmu-dmc";
reg = <0x105C0000 0x2000>;
#clock-cells = <1>;
@@ -219,7 +219,7 @@
status = "disabled";
};
- tmu: tmu@100C0000 {
+ tmu: tmu@100c0000 {
compatible = "samsung,exynos3250-tmu";
reg = <0x100C0000 0x100>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
@@ -287,7 +287,7 @@
status = "disabled";
};
- sysmmu_jpeg: sysmmu@11A60000 {
+ sysmmu_jpeg: sysmmu@11a60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11a60000 0x1000>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
@@ -313,7 +313,7 @@
status = "disabled";
};
- dsi_0: dsi@11C80000 {
+ dsi_0: dsi@11c80000 {
compatible = "samsung,exynos3250-mipi-dsi";
reg = <0x11C80000 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -328,7 +328,7 @@
status = "disabled";
};
- sysmmu_fimd0: sysmmu@11E20000 {
+ sysmmu_fimd0: sysmmu@11e20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11e20000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
@@ -386,7 +386,7 @@
status = "disabled";
};
- exynos_usbphy: exynos-usbphy@125B0000 {
+ exynos_usbphy: exynos-usbphy@125b0000 {
compatible = "samsung,exynos3250-usb2-phy";
reg = <0x125B0000 0x100>;
samsung,pmureg-phandle = <&pmu_system_controller>;
@@ -425,7 +425,7 @@
};
};
- adc: adc@126C0000 {
+ adc: adc@126c0000 {
compatible = "samsung,exynos3250-adc",
"samsung,exynos-adc-v2";
reg = <0x126C0000 0x100>;
@@ -544,7 +544,7 @@
status = "disabled";
};
- i2c_4: i2c@138A0000 {
+ i2c_4: i2c@138a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -557,7 +557,7 @@
status = "disabled";
};
- i2c_5: i2c@138B0000 {
+ i2c_5: i2c@138b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -570,7 +570,7 @@
status = "disabled";
};
- i2c_6: i2c@138C0000 {
+ i2c_6: i2c@138c0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -583,7 +583,7 @@
status = "disabled";
};
- i2c_7: i2c@138D0000 {
+ i2c_7: i2c@138d0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -641,7 +641,7 @@
status = "disabled";
};
- pwm: pwm@139D0000 {
+ pwm: pwm@139d0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x139D0000 0x1000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 2db6cfe5d908..f44aa383f626 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -101,28 +101,28 @@
syscon = <&pmu_system_controller>;
};
- pd_mfc: mfc-power-domain@10023C40 {
+ pd_mfc: mfc-power-domain@10023c40 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C40 0x20>;
#power-domain-cells = <0>;
label = "MFC";
};
- pd_g3d: g3d-power-domain@10023C60 {
+ pd_g3d: g3d-power-domain@10023c60 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C60 0x20>;
#power-domain-cells = <0>;
label = "G3D";
};
- pd_lcd0: lcd0-power-domain@10023C80 {
+ pd_lcd0: lcd0-power-domain@10023c80 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C80 0x20>;
#power-domain-cells = <0>;
label = "LCD0";
};
- pd_tv: tv-power-domain@10023C20 {
+ pd_tv: tv-power-domain@10023c20 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C20 0x20>;
#power-domain-cells = <0>;
@@ -130,21 +130,21 @@
label = "TV";
};
- pd_cam: cam-power-domain@10023C00 {
+ pd_cam: cam-power-domain@10023c00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C00 0x20>;
#power-domain-cells = <0>;
label = "CAM";
};
- pd_gps: gps-power-domain@10023CE0 {
+ pd_gps: gps-power-domain@10023ce0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CE0 0x20>;
#power-domain-cells = <0>;
label = "GPS";
};
- pd_gps_alive: gps-alive-power-domain@10023D00 {
+ pd_gps_alive: gps-alive-power-domain@10023d00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023D00 0x20>;
#power-domain-cells = <0>;
@@ -184,7 +184,7 @@
interrupt-parent = <&gic>;
};
- dsi_0: dsi@11C80000 {
+ dsi_0: dsi@11c80000 {
compatible = "samsung,exynos4210-mipi-dsi";
reg = <0x11C80000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
@@ -297,7 +297,7 @@
status = "disabled";
};
- keypad: keypad@100A0000 {
+ keypad: keypad@100a0000 {
compatible = "samsung,s5pv210-keypad";
reg = <0x100A0000 0x100>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
@@ -342,7 +342,7 @@
status = "disabled";
};
- exynos_usbphy: exynos-usbphy@125B0000 {
+ exynos_usbphy: exynos-usbphy@125b0000 {
compatible = "samsung,exynos4210-usb2-phy";
reg = <0x125B0000 0x100>;
samsung,pmureg-phandle = <&pmu_system_controller>;
@@ -538,7 +538,7 @@
status = "disabled";
};
- i2c_4: i2c@138A0000 {
+ i2c_4: i2c@138a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -551,7 +551,7 @@
status = "disabled";
};
- i2c_5: i2c@138B0000 {
+ i2c_5: i2c@138b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -564,7 +564,7 @@
status = "disabled";
};
- i2c_6: i2c@138C0000 {
+ i2c_6: i2c@138c0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -577,7 +577,7 @@
status = "disabled";
};
- i2c_7: i2c@138D0000 {
+ i2c_7: i2c@138d0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
@@ -590,7 +590,7 @@
status = "disabled";
};
- i2c_8: i2c@138E0000 {
+ i2c_8: i2c@138e0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-hdmiphy-i2c";
@@ -651,7 +651,7 @@
status = "disabled";
};
- pwm: pwm@139D0000 {
+ pwm: pwm@139d0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x139D0000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
@@ -720,7 +720,7 @@
status = "disabled";
};
- tmu: tmu@100C0000 {
+ tmu: tmu@100c0000 {
#include "exynos4412-tmu-sensor-conf.dtsi"
};
@@ -743,7 +743,7 @@
iommus = <&sysmmu_rotator>;
};
- hdmi: hdmi@12D00000 {
+ hdmi: hdmi@12d00000 {
compatible = "samsung,exynos4210-hdmi";
reg = <0x12D00000 0x70000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -759,7 +759,7 @@
status = "disabled";
};
- hdmicec: cec@100B0000 {
+ hdmicec: cec@100b0000 {
compatible = "samsung,s5p-cec";
reg = <0x100B0000 0x200>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -772,7 +772,7 @@
status = "disabled";
};
- mixer: mixer@12C10000 {
+ mixer: mixer@12c10000 {
compatible = "samsung,exynos4210-mixer";
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
@@ -911,7 +911,7 @@
#iommu-cells = <0>;
};
- sysmmu_tv: sysmmu@12E20000 {
+ sysmmu_tv: sysmmu@12e20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12E20000 0x1000>;
interrupt-parent = <&combiner>;
@@ -922,7 +922,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc0: sysmmu@11A20000 {
+ sysmmu_fimc0: sysmmu@11a20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11A20000 0x1000>;
interrupt-parent = <&combiner>;
@@ -933,7 +933,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc1: sysmmu@11A30000 {
+ sysmmu_fimc1: sysmmu@11a30000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11A30000 0x1000>;
interrupt-parent = <&combiner>;
@@ -944,7 +944,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc2: sysmmu@11A40000 {
+ sysmmu_fimc2: sysmmu@11a40000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11A40000 0x1000>;
interrupt-parent = <&combiner>;
@@ -955,7 +955,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc3: sysmmu@11A50000 {
+ sysmmu_fimc3: sysmmu@11a50000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11A50000 0x1000>;
interrupt-parent = <&combiner>;
@@ -966,7 +966,7 @@
#iommu-cells = <0>;
};
- sysmmu_jpeg: sysmmu@11A60000 {
+ sysmmu_jpeg: sysmmu@11a60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11A60000 0x1000>;
interrupt-parent = <&combiner>;
@@ -977,7 +977,7 @@
#iommu-cells = <0>;
};
- sysmmu_rotator: sysmmu@12A30000 {
+ sysmmu_rotator: sysmmu@12a30000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12A30000 0x1000>;
interrupt-parent = <&combiner>;
@@ -987,7 +987,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimd0: sysmmu@11E20000 {
+ sysmmu_fimd0: sysmmu@11e20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11E20000 0x1000>;
interrupt-parent = <&combiner>;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 03dd61f64809..ce161ad1215d 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -82,7 +82,7 @@
};
};
- pd_lcd1: lcd1-power-domain@10023CA0 {
+ pd_lcd1: lcd1-power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
#power-domain-cells = <0>;
@@ -156,7 +156,7 @@
reg = <0x03860000 0x1000>;
};
- tmu: tmu@100C0000 {
+ tmu: tmu@100c0000 {
compatible = "samsung,exynos4210-tmu";
interrupt-parent = <&combiner>;
reg = <0x100C0000 0x100>;
@@ -229,7 +229,7 @@
};
};
- mixer: mixer@12C10000 {
+ mixer: mixer@12c10000 {
clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
"sclk_mixer";
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
@@ -245,7 +245,7 @@
status = "disabled";
};
- sysmmu_g2d: sysmmu@12A20000 {
+ sysmmu_g2d: sysmmu@12a20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12A20000 0x1000>;
interrupt-parent = <&combiner>;
diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
index 4eebd4721a5f..ef7b89d3db9e 100644
--- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
@@ -925,7 +925,7 @@
};
};
- pinctrl_3: pinctrl@106E0000 {
+ pinctrl_3: pinctrl@106e0000 {
gpv0: gpv0 {
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 282525ac7554..cec5bef44bdb 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -38,7 +38,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu0: cpu@A00 {
+ cpu0: cpu@a00 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA00>;
@@ -50,21 +50,21 @@
#cooling-cells = <2>; /* min followed by max */
};
- cpu@A01 {
+ cpu@a01 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA01>;
operating-points-v2 = <&cpu0_opp_table>;
};
- cpu@A02 {
+ cpu@a02 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA02>;
operating-points-v2 = <&cpu0_opp_table>;
};
- cpu@A03 {
+ cpu@a03 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA03>;
@@ -168,7 +168,7 @@
};
};
- pd_isp: isp-power-domain@10023CA0 {
+ pd_isp: isp-power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
#power-domain-cells = <0>;
@@ -233,7 +233,7 @@
samsung,syscon-phandle = <&pmu_system_controller>;
};
- adc: adc@126C0000 {
+ adc: adc@126c0000 {
compatible = "samsung,exynos-adc-v1";
reg = <0x126C0000 0x100>;
interrupt-parent = <&combiner>;
@@ -272,7 +272,7 @@
status = "disabled";
};
- fimc_lite_1: fimc-lite@123A0000 {
+ fimc_lite_1: fimc-lite@123a0000 {
compatible = "samsung,exynos4212-fimc-lite";
reg = <0x123A0000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@@ -385,7 +385,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc_fd: sysmmu@122A0000 {
+ sysmmu_fimc_fd: sysmmu@122a0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x122A0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -396,7 +396,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc_mcuctl: sysmmu@122B0000 {
+ sysmmu_fimc_mcuctl: sysmmu@122b0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x122B0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -407,7 +407,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc_lite0: sysmmu@123B0000 {
+ sysmmu_fimc_lite0: sysmmu@123b0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x123B0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -419,7 +419,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc_lite1: sysmmu@123C0000 {
+ sysmmu_fimc_lite1: sysmmu@123c0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x123C0000 0x1000>;
interrupt-parent = <&combiner>;
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index b3c8428de389..1b1dd3850638 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -106,31 +106,31 @@
reg = <0x10050000 0x5000>;
};
- serial_0: serial@12C00000 {
+ serial_0: serial@12c00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
};
- serial_1: serial@12C10000 {
+ serial_1: serial@12c10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
- serial_2: serial@12C20000 {
+ serial_2: serial@12c20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
};
- serial_3: serial@12C30000 {
+ serial_3: serial@12c30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C30000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
};
- i2c_0: i2c@12C60000 {
+ i2c_0: i2c@12c60000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
@@ -140,7 +140,7 @@
status = "disabled";
};
- i2c_1: i2c@12C70000 {
+ i2c_1: i2c@12c70000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
@@ -150,7 +150,7 @@
status = "disabled";
};
- i2c_2: i2c@12C80000 {
+ i2c_2: i2c@12c80000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
@@ -160,7 +160,7 @@
status = "disabled";
};
- i2c_3: i2c@12C90000 {
+ i2c_3: i2c@12c90000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
@@ -170,14 +170,14 @@
status = "disabled";
};
- pwm: pwm@12DD0000 {
+ pwm: pwm@12dd0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x12DD0000 0x100>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
#pwm-cells = <3>;
};
- rtc: rtc@101E0000 {
+ rtc: rtc@101e0000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
@@ -195,7 +195,7 @@
status = "disabled";
};
- dp: dp-controller@145B0000 {
+ dp: dp-controller@145b0000 {
compatible = "samsung,exynos5-dp";
reg = <0x145B0000 0x1000>;
interrupts = <10 3>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index bdd742e3f3c3..571c89605a39 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -132,7 +132,7 @@
label = "G3D";
};
- pd_disp1: power-domain@100440A0 {
+ pd_disp1: power-domain@100440a0 {
compatible = "samsung,exynos4210-pd";
reg = <0x100440A0 0x20>;
#power-domain-cells = <0>;
@@ -143,7 +143,7 @@
clock-names = "oscclk", "clk0", "clk1";
};
- pd_mau: power-domain@100440C0 {
+ pd_mau: power-domain@100440c0 {
compatible = "samsung,exynos4210-pd";
reg = <0x100440C0 0x20>;
#power-domain-cells = <0>;
@@ -180,7 +180,7 @@
clock-frequency = <24000000>;
};
- mct@101C0000 {
+ mct@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
interrupt-controller;
@@ -252,7 +252,7 @@
interrupt-parent = <&gic>;
};
- watchdog@101D0000 {
+ watchdog@101d0000 {
compatible = "samsung,exynos5250-wdt";
reg = <0x101D0000 0x100>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
@@ -272,7 +272,7 @@
iommu-names = "left", "right";
};
- rotator: rotator@11C00000 {
+ rotator: rotator@11c00000 {
compatible = "samsung,exynos5250-rotator";
reg = <0x11C00000 0x64>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -290,7 +290,7 @@
#include "exynos4412-tmu-sensor-conf.dtsi"
};
- sata: sata@122F0000 {
+ sata: sata@122f0000 {
compatible = "snps,dwc-ahci";
samsung,sata-freq = <66>;
reg = <0x122F0000 0x1ff>;
@@ -313,7 +313,7 @@
};
/* i2c_0-3 are defined in exynos5.dtsi */
- i2c_4: i2c@12CA0000 {
+ i2c_4: i2c@12ca0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CA0000 0x100>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -326,7 +326,7 @@
status = "disabled";
};
- i2c_5: i2c@12CB0000 {
+ i2c_5: i2c@12cb0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CB0000 0x100>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
@@ -339,7 +339,7 @@
status = "disabled";
};
- i2c_6: i2c@12CC0000 {
+ i2c_6: i2c@12cc0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CC0000 0x100>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
@@ -352,7 +352,7 @@
status = "disabled";
};
- i2c_7: i2c@12CD0000 {
+ i2c_7: i2c@12cd0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CD0000 0x100>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
@@ -365,7 +365,7 @@
status = "disabled";
};
- i2c_8: i2c@12CE0000 {
+ i2c_8: i2c@12ce0000 {
compatible = "samsung,s3c2440-hdmiphy-i2c";
reg = <0x12CE0000 0x1000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
@@ -381,7 +381,7 @@
};
};
- i2c_9: i2c@121D0000 {
+ i2c_9: i2c@121d0000 {
compatible = "samsung,exynos5-sata-phy-i2c";
reg = <0x121D0000 0x100>;
#address-cells = <1>;
@@ -505,7 +505,7 @@
power-domains = <&pd_mau>;
};
- i2s1: i2s@12D60000 {
+ i2s1: i2s@12d60000 {
compatible = "samsung,s3c6410-i2s";
status = "disabled";
reg = <0x12D60000 0x100>;
@@ -519,7 +519,7 @@
power-domains = <&pd_mau>;
};
- i2s2: i2s@12D70000 {
+ i2s2: i2s@12d70000 {
compatible = "samsung,s3c6410-i2s";
status = "disabled";
reg = <0x12D70000 0x100>;
@@ -606,7 +606,7 @@
interrupt-parent = <&gic>;
ranges;
- pdma0: pdma@121A0000 {
+ pdma0: pdma@121a0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
@@ -617,7 +617,7 @@
#dma-requests = <32>;
};
- pdma1: pdma@121B0000 {
+ pdma1: pdma@121b0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
@@ -639,7 +639,7 @@
#dma-requests = <1>;
};
- mdma1: mdma@11C10000 {
+ mdma1: mdma@11c10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
@@ -706,7 +706,7 @@
status = "disabled";
};
- hdmicec: cec@101B0000 {
+ hdmicec: cec@101b0000 {
compatible = "samsung,s5p-cec";
reg = <0x101B0000 0x200>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -737,7 +737,7 @@
#phy-cells = <0>;
};
- adc: adc@12D10000 {
+ adc: adc@12d10000 {
compatible = "samsung,exynos-adc-v1";
reg = <0x12D10000 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@@ -749,7 +749,7 @@
status = "disabled";
};
- sysmmu_g2d: sysmmu@10A60000 {
+ sysmmu_g2d: sysmmu@10a60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x10A60000 0x1000>;
interrupt-parent = <&combiner>;
@@ -781,7 +781,7 @@
#iommu-cells = <0>;
};
- sysmmu_rotator: sysmmu@11D40000 {
+ sysmmu_rotator: sysmmu@11d40000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11D40000 0x1000>;
interrupt-parent = <&combiner>;
@@ -791,7 +791,7 @@
#iommu-cells = <0>;
};
- sysmmu_jpeg: sysmmu@11F20000 {
+ sysmmu_jpeg: sysmmu@11f20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11F20000 0x1000>;
interrupt-parent = <&combiner>;
@@ -822,7 +822,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc_fd: sysmmu@132A0000 {
+ sysmmu_fimc_fd: sysmmu@132a0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x132A0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -852,7 +852,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc_mcuctl: sysmmu@132B0000 {
+ sysmmu_fimc_mcuctl: sysmmu@132b0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x132B0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -862,7 +862,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc_odc: sysmmu@132C0000 {
+ sysmmu_fimc_odc: sysmmu@132c0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x132C0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -872,7 +872,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc_dis0: sysmmu@132D0000 {
+ sysmmu_fimc_dis0: sysmmu@132d0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x132D0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -892,7 +892,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc_3dnr: sysmmu@132F0000 {
+ sysmmu_fimc_3dnr: sysmmu@132f0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x132F0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -902,7 +902,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc_lite0: sysmmu@13C40000 {
+ sysmmu_fimc_lite0: sysmmu@13c40000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13C40000 0x1000>;
interrupt-parent = <&combiner>;
@@ -913,7 +913,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimc_lite1: sysmmu@13C50000 {
+ sysmmu_fimc_lite1: sysmmu@13c50000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13C50000 0x1000>;
interrupt-parent = <&combiner>;
@@ -924,7 +924,7 @@
#iommu-cells = <0>;
};
- sysmmu_gsc0: sysmmu@13E80000 {
+ sysmmu_gsc0: sysmmu@13e80000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13E80000 0x1000>;
interrupt-parent = <&combiner>;
@@ -935,7 +935,7 @@
#iommu-cells = <0>;
};
- sysmmu_gsc1: sysmmu@13E90000 {
+ sysmmu_gsc1: sysmmu@13e90000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13E90000 0x1000>;
interrupt-parent = <&combiner>;
@@ -946,7 +946,7 @@
#iommu-cells = <0>;
};
- sysmmu_gsc2: sysmmu@13EA0000 {
+ sysmmu_gsc2: sysmmu@13ea0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13EA0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -957,7 +957,7 @@
#iommu-cells = <0>;
};
- sysmmu_gsc3: sysmmu@13EB0000 {
+ sysmmu_gsc3: sysmmu@13eb0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13EB0000 0x1000>;
interrupt-parent = <&combiner>;
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 5e88c9645975..12c6b011576b 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -106,13 +106,13 @@
#clock-cells = <1>;
};
- clock_g2d: clock-controller@10A00000 {
+ clock_g2d: clock-controller@10a00000 {
compatible = "samsung,exynos5260-clock-g2d";
reg = <0x10A00000 0x10000>;
#clock-cells = <1>;
};
- clock_mif: clock-controller@10CE0000 {
+ clock_mif: clock-controller@10ce0000 {
compatible = "samsung,exynos5260-clock-mif";
reg = <0x10CE0000 0x10000>;
#clock-cells = <1>;
@@ -130,25 +130,25 @@
#clock-cells = <1>;
};
- clock_fsys: clock-controller@122E0000 {
+ clock_fsys: clock-controller@122e0000 {
compatible = "samsung,exynos5260-clock-fsys";
reg = <0x122E0000 0x10000>;
#clock-cells = <1>;
};
- clock_aud: clock-controller@128C0000 {
+ clock_aud: clock-controller@128c0000 {
compatible = "samsung,exynos5260-clock-aud";
reg = <0x128C0000 0x10000>;
#clock-cells = <1>;
};
- clock_isp: clock-controller@133C0000 {
+ clock_isp: clock-controller@133c0000 {
compatible = "samsung,exynos5260-clock-isp";
reg = <0x133C0000 0x10000>;
#clock-cells = <1>;
};
- clock_gscl: clock-controller@13F00000 {
+ clock_gscl: clock-controller@13f00000 {
compatible = "samsung,exynos5260-clock-gscl";
reg = <0x13F00000 0x10000>;
#clock-cells = <1>;
@@ -179,7 +179,7 @@
reg = <0x10000000 0x100>;
};
- mct: mct@100B0000 {
+ mct: mct@100b0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x100B0000 0x1000>;
clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
@@ -198,7 +198,7 @@
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
};
- cci: cci@10F00000 {
+ cci: cci@10f00000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
@@ -236,18 +236,18 @@
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
};
- pinctrl_2: pinctrl@128B0000 {
+ pinctrl_2: pinctrl@128b0000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x128B0000 0x1000>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
};
- pmu_system_controller: system-controller@10D50000 {
+ pmu_system_controller: system-controller@10d50000 {
compatible = "samsung,exynos5260-pmu", "syscon";
reg = <0x10D50000 0x10000>;
};
- uart0: serial@12C00000 {
+ uart0: serial@12c00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
@@ -256,7 +256,7 @@
status = "disabled";
};
- uart1: serial@12C10000 {
+ uart1: serial@12c10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
@@ -265,7 +265,7 @@
status = "disabled";
};
- uart2: serial@12C20000 {
+ uart2: serial@12c20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index e451b7b4d1ca..340443e2f004 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -238,37 +238,37 @@
status = "disabled";
};
- nocp_mem0_0: nocp@10CA1000 {
+ nocp_mem0_0: nocp@10ca1000 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1000 0x200>;
status = "disabled";
};
- nocp_mem0_1: nocp@10CA1400 {
+ nocp_mem0_1: nocp@10ca1400 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1400 0x200>;
status = "disabled";
};
- nocp_mem1_0: nocp@10CA1800 {
+ nocp_mem1_0: nocp@10ca1800 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1800 0x200>;
status = "disabled";
};
- nocp_mem1_1: nocp@10CA1C00 {
+ nocp_mem1_1: nocp@10ca1c00 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1C00 0x200>;
status = "disabled";
};
- nocp_g3d_0: nocp@11A51000 {
+ nocp_g3d_0: nocp@11a51000 {
compatible = "samsung,exynos5420-nocp";
reg = <0x11A51000 0x200>;
status = "disabled";
};
- nocp_g3d_1: nocp@11A51400 {
+ nocp_g3d_1: nocp@11a51400 {
compatible = "samsung,exynos5420-nocp";
reg = <0x11A51400 0x200>;
status = "disabled";
@@ -310,7 +310,7 @@
label = "MSC";
};
- disp_pd: power-domain@100440C0 {
+ disp_pd: power-domain@100440c0 {
compatible = "samsung,exynos4210-pd";
reg = <0x100440C0 0x20>;
#power-domain-cells = <0>;
@@ -323,7 +323,7 @@
clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
};
- mau_pd: power-domain@100440E0 {
+ mau_pd: power-domain@100440e0 {
compatible = "samsung,exynos4210-pd";
reg = <0x100440E0 0x20>;
#power-domain-cells = <0>;
@@ -386,7 +386,7 @@
power-domains = <&mau_pd>;
};
- pdma0: pdma@121A0000 {
+ pdma0: pdma@121a0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
@@ -397,7 +397,7 @@
#dma-requests = <32>;
};
- pdma1: pdma@121B0000 {
+ pdma1: pdma@121b0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
@@ -419,7 +419,7 @@
#dma-requests = <1>;
};
- mdma1: mdma@11C10000 {
+ mdma1: mdma@11c10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
@@ -460,7 +460,7 @@
status = "disabled";
};
- i2s1: i2s@12D60000 {
+ i2s1: i2s@12d60000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x12D60000 0x100>;
dmas = <&pdma1 12
@@ -476,7 +476,7 @@
status = "disabled";
};
- i2s2: i2s@12D70000 {
+ i2s2: i2s@12d70000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x12D70000 0x100>;
dmas = <&pdma0 12
@@ -565,7 +565,7 @@
status = "disabled";
};
- adc: adc@12D10000 {
+ adc: adc@12d10000 {
compatible = "samsung,exynos-adc-v2";
reg = <0x12D10000 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@@ -577,7 +577,7 @@
status = "disabled";
};
- hsi2c_8: i2c@12E00000 {
+ hsi2c_8: i2c@12e00000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E00000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
@@ -590,7 +590,7 @@
status = "disabled";
};
- hsi2c_9: i2c@12E10000 {
+ hsi2c_9: i2c@12e10000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E10000 0x1000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
@@ -603,7 +603,7 @@
status = "disabled";
};
- hsi2c_10: i2c@12E20000 {
+ hsi2c_10: i2c@12e20000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E20000 0x1000>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
@@ -632,11 +632,11 @@
#sound-dai-cells = <0>;
};
- hdmiphy: hdmiphy@145D0000 {
+ hdmiphy: hdmiphy@145d0000 {
reg = <0x145D0000 0x20>;
};
- hdmicec: cec@101B0000 {
+ hdmicec: cec@101b0000 {
compatible = "samsung,s5p-cec";
reg = <0x101B0000 0x200>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -661,7 +661,7 @@
status = "disabled";
};
- rotator: rotator@11C00000 {
+ rotator: rotator@11c00000 {
compatible = "samsung,exynos5250-rotator";
reg = <0x11C00000 0x64>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -690,7 +690,7 @@
iommus = <&sysmmu_gscl1>;
};
- jpeg_0: jpeg@11F50000 {
+ jpeg_0: jpeg@11f50000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F50000 0x1000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
@@ -699,7 +699,7 @@
iommus = <&sysmmu_jpeg0>;
};
- jpeg_1: jpeg@11F60000 {
+ jpeg_1: jpeg@11f60000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F60000 0x1000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 9c3c75ae5e48..3acf3f2d643e 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -35,7 +35,7 @@
#clock-cells = <1>;
};
- gic: interrupt-controller@2E0000 {
+ gic: interrupt-controller@2e0000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
@@ -108,7 +108,7 @@
>;
};
- serial_0: serial@B0000 {
+ serial_0: serial@b0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xB0000 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -116,7 +116,7 @@
clock-names = "uart", "clk_uart_baud0";
};
- serial_1: serial@C0000 {
+ serial_1: serial@c0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xC0000 0x1000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
@@ -124,7 +124,7 @@
clock-names = "uart", "clk_uart_baud0";
};
- spi_0: spi@D0000 {
+ spi_0: spi@d0000 {
compatible = "samsung,exynos5440-spi";
reg = <0xD0000 0x100>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
@@ -136,7 +136,7 @@
clock-names = "spi", "spi_busclk0";
};
- pin_ctrl: pinctrl@E0000 {
+ pin_ctrl: pinctrl@e0000 {
compatible = "samsung,exynos5440-pinctrl";
reg = <0xE0000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
@@ -168,7 +168,7 @@
};
};
- i2c@F0000 {
+ i2c@f0000 {
compatible = "samsung,exynos5440-i2c";
reg = <0xF0000 0x1000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
@@ -233,7 +233,7 @@
#include "exynos5440-tmu-sensor-conf.dtsi"
};
- tmuctrl_1: tmuctrl@16011C {
+ tmuctrl_1: tmuctrl@16011c {
compatible = "samsung,exynos5440-tmu";
reg = <0x16011C 0x230>, <0x160368 0x10>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
--
2.11.0
^ permalink raw reply related
* Re: DT dtc warnings
From: Rob Herring @ 2017-12-14 21:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Barry Song, Kukjin Kim, Maxime Ripard, Chen-Yu Tsai,
Nicolas Ferre, Alexandre Belloni, Patrice Chotard, Peter Rosin,
Santosh Shilimkar, arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Mathieu Malaterre
In-Reply-To: <CAJKOXPc7M3jeV_hNBBRJKGs3vtNzdrGbW_YETw2n0fXxhqjZ_g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Thu, Dec 14, 2017 at 2:40 PM, Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Thu, Dec 14, 2017 at 7:21 PM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>> Hi all,
>>
>> Below is a current list of ARM boards with more than 40 dtc warnings
>> when building with W=1. There's a treewide patch in flight to fix some
>> unit-address warnings[1], so those aren't included here. The list is
>> grouped by maintainer. AT91, Exynos, and Allwinner continue to be at
>> the top of the list and have been for some time (though having
>> multiple boards for an SoC can cause lots of duplicated warnings).
>>
>> 50 - arch/arm/boot/dts/exynos5250-arndale.dts
>> 50 - arch/arm/boot/dts/exynos5250-smdk5250.dts
>> 50 - arch/arm/boot/dts/exynos5250-snow.dts
>> 50 - arch/arm/boot/dts/exynos5250-snow-rev5.dts
>> 50 - arch/arm/boot/dts/exynos5250-spring.dts
>> 71 - arch/arm/boot/dts/exynos5420-arndale-octa.dts
>> 71 - arch/arm/boot/dts/exynos5420-peach-pit.dts
>> 71 - arch/arm/boot/dts/exynos5420-smdk5420.dts
>> 71 - arch/arm/boot/dts/exynos5422-odroidhc1.dts
>> 71 - arch/arm/boot/dts/exynos5422-odroidxu3.dts
>> 71 - arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
>> 71 - arch/arm/boot/dts/exynos5422-odroidxu4.dts
>> 71 - arch/arm/boot/dts/exynos5800-peach-pi.dts
>>
>
> Sure, I can take care of this but in such case it would be better if
> Mathieu's (+Cc) patch would be split per-subarch maintainer. I can
> base my patch on top of his... but there might be conflicts when
> applying to my tree.
>
> Different topic - why not enabling these warnings by default?
Because the warning police don't like lots of warnings. Neither did
Linus, but he only sees the unittest ones[1]. The ones that are actual
binding errors rather than best practice are on by default.
The plan is to enable once the warnings are all gone.
Rob
[1] https://www.spinics.net/lists/devicetree/msg202057.html
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^ permalink raw reply
* Re: [PATCH v2 1/2] leds: as3645a: Fix quoted string split warning
From: Jacek Anaszewski @ 2017-12-14 21:11 UTC (permalink / raw)
To: Dan Murphy, robh+dt, mark.rutland, rpurdie, pavel, sakari.ailus,
laurent.pinchart
Cc: devicetree, linux-kernel, linux-leds
In-Reply-To: <20171214173727.10070-1-dmurphy@ti.com>
Hi Dan,
Thanks for the patch set.
Bot patches applied to the for-next branch.
--
Best regards,
Jacek Anaszewski
On 12/14/2017 06:37 PM, Dan Murphy wrote:
> Fix a warning for a split quoted string across
> lines.
>
> WARNING: quoted string split across lines
> 459: FILE: drivers/leds/leds-as3645a.c:459:
> dev_err(dev, "AS3645A not detected "
> "(model %d rfu %d)\n", model, rfu);
>
> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> ---
>
> v2 - Split the warning fixes into 2 patches and fixed commit message -
> https://patchwork.kernel.org/patch/10108325/
>
> drivers/leds/leds-as3645a.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/leds/leds-as3645a.c b/drivers/leds/leds-as3645a.c
> index 9a257f969300..49fdd7c0a6f6 100644
> --- a/drivers/leds/leds-as3645a.c
> +++ b/drivers/leds/leds-as3645a.c
> @@ -455,8 +455,8 @@ static int as3645a_detect(struct as3645a *flash)
>
> /* Verify the chip model and version. */
> if (model != 0x01 || rfu != 0x00) {
> - dev_err(dev, "AS3645A not detected "
> - "(model %d rfu %d)\n", model, rfu);
> + dev_err(dev, "AS3645A not detected (model %d rfu %d)\n",
> + model, rfu);
> return -ENODEV;
> }
>
>
^ permalink raw reply
* Re: DT dtc warnings
From: Fabio Estevam @ 2017-12-14 21:13 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Barry Song, Kukjin Kim, Maxime Ripard, Chen-Yu Tsai,
Nicolas Ferre, Alexandre Belloni, Patrice Chotard, Peter Rosin,
Santosh Shilimkar, arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Mathieu Malaterre
In-Reply-To: <CAJKOXPfCDT+7wPkz3g6AiKgLvFp4rnicYQgYn8A_yaPe4YhD5A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Thu, Dec 14, 2017 at 7:01 PM, Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> Can anyone help why this W=1 triggers warning like these:
> arch/arm/boot/dts/exynos3250-artik5-eval.dtb: Warning
> (simple_bus_reg): Node /soc/syscon-poweroff missing or empty
> reg/ranges property
> arch/arm/boot/dts/exynos3250-artik5-eval.dtb: Warning
> (simple_bus_reg): Node /soc/syscon-reboot missing or empty reg/ranges
> property
>
> For a node without unit address?
> http://elixir.free-electrons.com/linux/v4.15-rc3/source/arch/arm/boot/dts/exynos-syscon-restart.dtsi
>
> AFAIR, if node does not have unit-address then it should not have
> reg/ranges property. Or maybe it is coming from parent's simple-bus?
syscon-poweroff and syscon-reboot should be outside the soc bus.
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^ permalink raw reply
* Re: DT dtc warnings
From: Krzysztof Kozlowski @ 2017-12-14 21:19 UTC (permalink / raw)
To: Fabio Estevam
Cc: Rob Herring, Barry Song, Kukjin Kim, Maxime Ripard, Chen-Yu Tsai,
Nicolas Ferre, Alexandre Belloni, Patrice Chotard, Peter Rosin,
Santosh Shilimkar, arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Mathieu Malaterre
In-Reply-To: <CAOMZO5BGX1U90bGrff42rZKKOSQK3NB=-k_4BX04Tsi=yX0Odg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Thu, Dec 14, 2017 at 10:13 PM, Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On Thu, Dec 14, 2017 at 7:01 PM, Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>
>> Can anyone help why this W=1 triggers warning like these:
>> arch/arm/boot/dts/exynos3250-artik5-eval.dtb: Warning
>> (simple_bus_reg): Node /soc/syscon-poweroff missing or empty
>> reg/ranges property
>> arch/arm/boot/dts/exynos3250-artik5-eval.dtb: Warning
>> (simple_bus_reg): Node /soc/syscon-reboot missing or empty reg/ranges
>> property
>>
>> For a node without unit address?
>> http://elixir.free-electrons.com/linux/v4.15-rc3/source/arch/arm/boot/dts/exynos-syscon-restart.dtsi
>>
>> AFAIR, if node does not have unit-address then it should not have
>> reg/ranges property. Or maybe it is coming from parent's simple-bus?
>
> syscon-poweroff and syscon-reboot should be outside the soc bus.
Thanks for reply!
Isn't this property of a SoC? The registers used by
syscon-poweroff/reboot are part of SoC power management unit. It does
not refer to any externals. Why then it should be put outside of soc?
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v5] i2c: Add support for NXP PCA984x family.
From: Peter Rosin @ 2017-12-14 21:22 UTC (permalink / raw)
To: Adrian Fiergolski
Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <20171214112003.13701-1-adrian.fiergolski-vJEk5272eHo@public.gmane.org>
On 2017-12-14 12:20, Adrian Fiergolski wrote:
> This patch extends the current i2c-mux-pca954x driver and adds support for
> a newer PCA984x family of the I2C switches and multiplexers from NXP.
>
> Signed-off-by: Adrian Fiergolski <adrian.fiergolski-vJEk5272eHo@public.gmane.org>
> ---
> I have applied recent Peter's comments.
Look like you missed the pair about .enable assignments for the [pca_9847]
and [pca_9849] entries of chips[].
Cheers,
Peter
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^ permalink raw reply
* Re: [PATCH v2 5/7] dt-bindings: i3c: Document core bindings
From: Peter Rosin @ 2017-12-14 21:47 UTC (permalink / raw)
To: Boris Brezillon, Wolfram Sang, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
Jonathan Corbet, linux-doc-u79uwXL29TY76Z2rM5mHXA,
Greg Kroah-Hartman, Arnd Bergmann
Cc: Przemyslaw Sroka, Arkadiusz Golec, Alan Douglas, Bartosz Folta,
Damian Kos, Alicja Jurasik-Urbaniak, Cyprian Wronka,
Suresh Punnoose, Thomas Petazzoni, Nishanth Menon, Rob Herring,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Vitor Soares,
Geert Uytterhoeven, Linus Walleij
In-Reply-To: <20171214151610.19153-6-boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On 2017-12-14 16:16, Boris Brezillon wrote:
> +Optional properties
> +-------------------
> +- reg: static address. Only valid is the device has a static address.
> +- i3c-dynamic-address: dynamic address to be assigned to this device. This
> + property depends on the reg property.
> +
> +Example:
> +
> + i3c-master@0d040000 {
i3c-master@d040000
(same in patch 7/7)
Cheers,
Peter
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^ permalink raw reply
* Re: [PATCH v2 6/7] i3c: master: Add driver for Cadence IP
From: Randy Dunlap @ 2017-12-14 22:10 UTC (permalink / raw)
To: Boris Brezillon
Cc: Wolfram Sang, linux-i2c-u79uwXL29TY76Z2rM5mHXA, Jonathan Corbet,
linux-doc-u79uwXL29TY76Z2rM5mHXA, Greg Kroah-Hartman,
Arnd Bergmann, Przemyslaw Sroka, Arkadiusz Golec, Alan Douglas,
Bartosz Folta, Damian Kos, Alicja Jurasik-Urbaniak,
Cyprian Wronka, Suresh Punnoose, Thomas Petazzoni, Nishanth Menon,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala
In-Reply-To: <20171214214442.55902041@bbrezillon>
On 12/14/2017 12:44 PM, Boris Brezillon wrote:
> On Thu, 14 Dec 2017 12:25:14 -0800
> Randy Dunlap <rdunlap-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org> wrote:
>
>> On 12/14/2017 12:17 PM, Boris Brezillon wrote:
>>>>> + events.events = I3C_CCC_EVENT_HJ | I3C_CCC_EVENT_MR;
>>>>> + ret = i3c_master_enec_locked(m, I3C_BROADCAST_ADDR, &events);
>>>>> + if (ret)
>>>>> + pr_info("Failed to re-enable H-J");
>>>> Not very good info...
>>> What do you mean? Is it the H-J that bothers you (I can replace it by
>>> 'Hot-Join'), or is it something else?
>>
>> Who is the message for? If it's for developers, you could use
>> pr_debug(). If it's for users, it needs more clarity.
>
> I think it's of interest to anyone including users. If we fail to
> re-enable Hot-Join that means hotplug is no longer working which is
> a bad news.
>
>>
>> Does it print the source of the message? (module name e.g.)
>
> I could replace it by
>
> dev_err(m->parent, "Failed to re-enable Hot-Join");
>
Yes, that's a good plan.
Thanks.
>
>
>> and yes, Hot-Join would be better IMO.
--
~Randy
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^ permalink raw reply
* Re: [PATCH] leds: as3645a: Fix checkpatch warnings
From: Pavel Machek @ 2017-12-14 22:49 UTC (permalink / raw)
To: Jacek Anaszewski
Cc: Dan Murphy, robh+dt, mark.rutland, rpurdie, sakari.ailus,
laurent.pinchart, devicetree, linux-kernel, linux-leds
In-Reply-To: <ac821766-4bb8-d5d4-feaf-6750e8ceb894@gmail.com>
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On Wed 2017-12-13 21:29:29, Jacek Anaszewski wrote:
> Hi Dan,
>
> checkpatch.pl doesn't want to be mentioned in the patch subject :-)
>
> "WARNING: A patch subject line should describe the change not the tool
> that found it"
That is pretty stupid rule. Everyone and their dog knows what
"checkpatch fixes" are.
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply
* Re: [PATCH] leds: as3645a: Fix checkpatch warnings
From: Pavel Machek @ 2017-12-14 22:50 UTC (permalink / raw)
To: Dan Murphy
Cc: Jacek Anaszewski, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, rpurdie-Fm38FmjxZ/leoWH0uzbU5w,
sakari.ailus-X3B1VOXEql0, laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-leds-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <799ae164-701a-87ce-fadf-8278f01c10d6-l0cyMroinI0@public.gmane.org>
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On Wed 2017-12-13 14:49:38, Dan Murphy wrote:
> Pavel and Laurent
>
> On 12/13/2017 02:43 PM, Jacek Anaszewski wrote:
> > Dan,
> >
> > On 12/13/2017 09:41 PM, Dan Murphy wrote:
> >> Jacek
> >>
> >> On 12/13/2017 02:29 PM, Jacek Anaszewski wrote:
> >>> Hi Dan,
> >>>
> >>> checkpatch.pl doesn't want to be mentioned in the patch subject :-)
> >>>
> >>
> >> Ack
> >>
> >>> "WARNING: A patch subject line should describe the change not the tool
> >>> that found it"
> >>>
> >>> Preferably I'd see two separate patches.
> >>>
> >>
> >> So you want me to split them up? I have no issue with that.
> >
> > Yeah, it will be easier to come up with concise but meaningful
> > subjects.
> >
>
> When I split these up can I add your Acked-by to each patch or would you prefer to resend your
> Acked-by for each patch?
You can keep the ack...
...and my preference would be for trivial fixes like these to be just
applied. No need to resend 3 versions etc...
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply
* Re: [PATCH v3 3/8] PCI: brcmstb: Add Broadcom STB PCIe host controller driver
From: Bjorn Helgaas @ 2017-12-14 22:51 UTC (permalink / raw)
To: Jim Quinlan
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bjorn Helgaas,
Catalin Marinas, Will Deacon, Rob Herring, Brian Norris,
Russell King, Robin Murphy, Christoph Hellwig, Florian Fainelli,
Jonas Gorski, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
Linux-MIPS, linux-pci, Kevin Cernekee, Ralf Baechle,
bcm-kernel-feedback-list, Gregory Fong, linux-arm-kernel
In-Reply-To: <CANCKTBvtqNWZYXpLdUnEWwA2=14XhJ6adR5muOAYubY_1SxZWw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Wed, Dec 13, 2017 at 06:53:53PM -0500, Jim Quinlan wrote:
> On Tue, Dec 12, 2017 at 5:16 PM, Bjorn Helgaas <helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> > On Tue, Nov 14, 2017 at 05:12:07PM -0500, Jim Quinlan wrote:
> >> This commit adds the basic Broadcom STB PCIe controller. Missing is
> >> the ability to process MSI and also handle dma-ranges for inbound
> >> memory accesses. These two functionalities are added in subsequent
> >> commits.
> >>
> >> The PCIe block contains an MDIO interface. This is a local interface
> >> only accessible by the PCIe controller. It cannot be used or shared
> >> by any other HW. As such, the small amount of code for this
> >> controller is included in this driver as there is little upside to put
> >> it elsewhere.
> ...
> >> +static bool brcm_pcie_valid_device(struct brcm_pcie *pcie, struct pci_bus *bus,
> >> + int dev)
> >> +{
> >> + if (pci_is_root_bus(bus)) {
> >> + if (dev > 0)
> >> + return false;
> >> + } else {
> >> + /* If there is no link, then there is no device */
> >> + if (!brcm_pcie_link_up(pcie))
> >> + return false;
> >
> > This is racy, since the link can go down after you check but before
> > you do the config access. I assume your hardware can deal with a
> > config access that targets a link that is down?
>
> Yes, that can happen but there is really nothing that can be done if
> the link goes down in that vulnerability window. What do you suggest
> doing?
Most hardware drops writes and returns ~0 on reads if the link is
down. I assume your hardware does something similar, and that should
be enough. You shouldn't have to check whether the link is up.
The hardware might report errors, e.g., via AER, if the link is down.
And we might not not handle those nicely. If we have issues there, we
should find out and fix them.
I see that dwc, altera, rockchip, and xilinx all do check for link up
there, too. I can't remember if they had a legitimate reason, or if I
just missed it.
> >> +static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
> >> +{
> >> + struct list_head *pos, *q;
> >> + struct brcm_pcie *tmp;
> >> +
> >> + mutex_lock(&brcm_pcie_lock);
> >> + list_for_each_safe(pos, q, &brcm_pcie) {
> >> + tmp = list_entry(pos, struct brcm_pcie, list);
> >> + if (tmp == pcie) {
> >> + list_del(pos);
> >> + if (list_empty(&brcm_pcie))
> >> + num_memc = 0;
> >> + break;
> >> + }
> >> + }
> >> + mutex_unlock(&brcm_pcie_lock);
> >
> > I'm missing something. I don't see that num_memc is ever set to
> > anything *other* than zero.
> The num_memc is set and used in the dma commit. I will remove its
> declaration from this commit.
Thanks, that will make the patches much easier to read.
> >> + pcie->id = of_get_pci_domain_nr(dn);
> >
> > Why do you call of_get_pci_domain_nr() directly? No other driver
> > does.
>
> We use the domain as the controller number (id). We use the id to
> identify and fix a HW bug that only affects the 2nd controller; see
> the clause
> " } else if (of_machine_is_compatible("brcm,bcm7278a0")) {".
pci_register_host_bridge() already sets bus->domain_nr for every host
bridge. That path calls of_get_pci_domain_nr() eventually. But I
guess that's too late for your use case, because you have this:
brcm_pcie_probe
brcm_pcie_setup
brcm_pcie_bridge_sw_init_set
if (of_machine_is_compatible("brcm,bcm7278a0")) {
offset = pcie->id ? ... <--- use
pci_scan_root_bus_bridge
pci_register_host_bridge
bus->domain_nr = pci_bus_find_domain_nr <--- available
I guess you haven't added a binding for brcm,bcm7278a0 yet?
I'm not really sure that using the linux,pci-domain DT property is the
best way to distinguish the two controllers. Maybe Rob has an
opinion?
> >> + if (pcie->id < 0)
> >> + return pcie->id;
Bjorn
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^ permalink raw reply
* Re: DT dtc warnings
From: Fabio Estevam @ 2017-12-14 23:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Barry Song, Kukjin Kim, Maxime Ripard, Chen-Yu Tsai,
Nicolas Ferre, Alexandre Belloni, Patrice Chotard, Peter Rosin,
Santosh Shilimkar, arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Mathieu Malaterre
In-Reply-To: <CAJKOXPea5nx+i+vWJcMGqct1=gP5OHbDSAzqTCBYr1RvFW-1gw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Thu, Dec 14, 2017 at 7:19 PM, Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> Thanks for reply!
>
> Isn't this property of a SoC? The registers used by
> syscon-poweroff/reboot are part of SoC power management unit. It does
> not refer to any externals. Why then it should be put outside of soc?
If these nodes have registers, then they should have a unit address
and reg property.
Regards,
Fabio Estevam
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^ permalink raw reply
* Re: [PATCH net-next v6 1/2] dt-bindings: net: add DT bindings for Socionext UniPhier AVE
From: Florian Fainelli @ 2017-12-14 23:24 UTC (permalink / raw)
To: Kunihiko Hayashi, David Miller, netdev-u79uwXL29TY76Z2rM5mHXA
Cc: Andrew Lunn, Rob Herring, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Masahiro Yamada,
Masami Hiramatsu, Jassi Brar
In-Reply-To: <1513245910-15961-2-git-send-email-hayashi.kunihiko-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
On 12/14/2017 02:05 AM, Kunihiko Hayashi wrote:
> DT bindings for the AVE ethernet controller found on Socionext's
> UniPhier platforms.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
> Signed-off-by: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
> .../bindings/net/socionext,uniphier-ave4.txt | 48 ++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
>
> diff --git a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
> new file mode 100644
> index 0000000..4700377
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
> @@ -0,0 +1,48 @@
> +* Socionext AVE ethernet controller
> +
> +This describes the devicetree bindings for AVE ethernet controller
> +implemented on Socionext UniPhier SoCs.
> +
> +Required properties:
> + - compatible: Should be
> + - "socionext,uniphier-pro4-ave4" : for Pro4 SoC
> + - "socionext,uniphier-pxs2-ave4" : for PXs2 SoC
> + - "socionext,uniphier-ld11-ave4" : for LD11 SoC
> + - "socionext,uniphier-ld20-ave4" : for LD20 SoC
> + - reg: Address where registers are mapped and size of region.
> + - interrupts: Should contain the MAC interrupt.
> + - phy-mode: See ethernet.txt in the same directory. Allow to choose
> + "rgmii", "rmii", or "mii" according to the PHY.
> + - phy-handle: Should point to the external phy device.
> + See ethernet.txt file in the same directory.
> + - clocks: A phandle to the clock for the MAC.
> +
> +Optional properties:
> + - resets: A phandle to the reset control for the MAC
> + - local-mac-address: See ethernet.txt in the same directory.
> +
> +Required subnode:
> + - mdio: Device tree subnode with the following required properties:
> + - #address-cells: Must be <1>.
> + - #size-cells: Must be <0>.
> + - reg: phy ID number, usually a small integer.
Almost, the "reg" property applies to the MDIO child nodes: the Ethernet
PHYs/MDIO devices. For the MDIO controller itself, the "reg" property,
if specified, would be relative to the Ethernet controller's base
register address.
Please drop this property's description here.
> +
> +Example:
> +
> + ether: ethernet@65000000 {
> + compatible = "socionext,uniphier-ld20-ave4";
> + reg = <0x65000000 0x8500>;
> + interrupts = <0 66 4>;
> + phy-mode = "rgmii";
> + phy-handle = <ðphy>;
> + clocks = <&sys_clk 6>;
> + resets = <&sys_rst 6>;
> + local-mac-address = [00 00 00 00 00 00];
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ethphy: ethphy@1 {
> + reg = <1>;
> + };
> + };
> + };
>
--
Florian
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^ permalink raw reply
* Re: [patch v14 2/4] drivers: jtag: Add Aspeed SoC 24xx and 25xx families JTAG master driver
From: Joel Stanley @ 2017-12-15 1:34 UTC (permalink / raw)
To: Oleksandr Shamray
Cc: Greg KH, Arnd Bergmann, Linux Kernel Mailing List, Linux ARM,
devicetree, OpenBMC Maillist, Jiří Pírko,
Tobias Klauser, linux-serial-u79uwXL29TY76Z2rM5mHXA,
Vadim Pasternak, system-sw-low-level-VPRAkNaXOzVWk0Htik3J/w,
Rob Herring, openocd-devel-owner-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
linux-api-u79uwXL29TY76Z2rM5mHXA, David S . Miller,
mchehab-DgEjT+Ai2ygdnm+yROfE0A, Jiri Pirko
In-Reply-To: <1513268971-13518-3-git-send-email-oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
On Fri, Dec 15, 2017 at 2:59 AM, Oleksandr Shamray
<oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org> wrote:
> Driver adds support of Aspeed 2500/2400 series SOC JTAG master controller.
Looks good. I have a few small things below, but I am happy to see
this merged from my point of view as ASPEED maintainer.
Cheers,
Joel
> +
> +menuconfig JTAG_ASPEED
> + tristate "Aspeed SoC JTAG controller support"
> + depends on JTAG && HAS_IOMEM
Add ARCH_ASPEED || COMPILE_TEST
> + ---help---
> + This provides a support for Aspeed JTAG device, equipped on
> + Aspeed SoC 24xx and 25xx families. Drivers allows programming
> + of hardware devices, connected to SoC through the JTAG interface.
> +
> + If you want this support, you should say Y here.
> +
> + To compile this driver as a module, choose M here: the module will
> + be called jtag-aspeed.
> diff --git a/drivers/jtag/Makefile b/drivers/jtag/Makefile
> index af37493..04a855e 100644
> --- a/drivers/jtag/Makefile
> +++ b/drivers/jtag/Makefile
> @@ -1 +1,2 @@
> obj-$(CONFIG_JTAG) += jtag.o
> +obj-$(CONFIG_JTAG_ASPEED) += jtag-aspeed.o
> diff --git a/drivers/jtag/jtag-aspeed.c b/drivers/jtag/jtag-aspeed.c
> new file mode 100644
> index 0000000..99277d2
> --- /dev/null
> +++ b/drivers/jtag/jtag-aspeed.c
> @@ -0,0 +1,783 @@
> +static int aspeed_jtag_xfer(struct jtag *jtag, struct jtag_xfer *xfer,
> + u8 *xfer_data)
> +{
> + static const u8 sm_update_shiftir[] = {1, 1, 0, 0};
> + static const u8 sm_update_shiftdr[] = {1, 0, 0};
> + static const u8 sm_pause_idle[] = {1, 1, 0};
> + static const u8 sm_pause_update[] = {1, 1};
> + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
> + unsigned long *data = (unsigned long *)xfer_data;
> + unsigned long remain_xfer = xfer->length;
> + unsigned long offset;
> + char dbg_str[256];
> + int pos = 0;
> + int i;
> +
> + for (offset = 0, i = 0; offset < xfer->length;
> + offset += ASPEED_JTAG_DATA_CHUNK_SIZE, i++) {
It looks like offset is unused.
> + pos += snprintf(&dbg_str[pos], sizeof(dbg_str) - pos,
> + "0x%08lx ", data[i]);
> + }
> +
> + dev_dbg(aspeed_jtag->dev, "aspeed_jtag %s %s xfer, mode:%s, END:%d, len:%lu, TDI[%s]\n",
> + xfer->type == JTAG_SIR_XFER ? "SIR" : "SDR",
> + xfer->direction == JTAG_READ_XFER ? "READ" : "WRITE",
> + aspeed_jtag->mode & JTAG_XFER_HW_MODE ? "HW" : "SW",
> + xfer->endstate, remain_xfer, dbg_str);
> +
> + if (!(aspeed_jtag->mode & JTAG_XFER_HW_MODE)) {
> + /* SW mode */
> + aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
> + ASPEED_JTAG_SW_MODE_TDIO, ASPEED_JTAG_SW);
> +
> + if (aspeed_jtag->status != JTAG_STATE_IDLE) {
> + /*IR/DR Pause->Exit2 IR / DR->Update IR /DR */
> + aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_update,
> + sizeof(sm_pause_update));
> + }
> +
> + if (xfer->type == JTAG_SIR_XFER)
> + /* ->IRSCan->CapIR->ShiftIR */
> + aspeed_jtag_sm_cycle(aspeed_jtag, sm_update_shiftir,
> + sizeof(sm_update_shiftir));
> + else
> + /* ->DRScan->DRCap->DRShift */
> + aspeed_jtag_sm_cycle(aspeed_jtag, sm_update_shiftdr,
> + sizeof(sm_update_shiftdr));
> +
> + aspeed_jtag_xfer_sw(aspeed_jtag, xfer, data);
> +
> + /* DIPause/DRPause */
> + aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0);
> +
> + if (xfer->endstate == JTAG_STATE_IDLE) {
> + /* ->DRExit2->DRUpdate->IDLE */
> + aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_idle,
> + sizeof(sm_pause_idle));
> + }
> + } else {
> + /* hw mode */
> + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW);
> + aspeed_jtag_xfer_hw(aspeed_jtag, xfer, data);
> + }
> +
> + aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
> + ASPEED_JTAG_SW_MODE_TDIO, ASPEED_JTAG_SW);
> + aspeed_jtag->status = xfer->endstate;
> + return 0;
> +}
>
> +
> +static irqreturn_t aspeed_jtag_interrupt(s32 this_irq, void *dev_id)
> +{
> + struct aspeed_jtag *aspeed_jtag = dev_id;
> + irqreturn_t ret;
> + u32 status;
> +
> + status = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_ISR);
> + dev_dbg(aspeed_jtag->dev, "status %x\n", status);
> +
> + if (status & ASPEED_JTAG_ISR_INT_MASK) {
> + aspeed_jtag_write(aspeed_jtag,
> + (status & ASPEED_JTAG_ISR_INT_MASK)
> + | (status & ASPEED_JTAG_ISR_INT_EN_MASK),
> + ASPEED_JTAG_ISR);
> + aspeed_jtag->flag |= status & ASPEED_JTAG_ISR_INT_MASK;
> + }
> +
> + if (aspeed_jtag->flag) {
> + wake_up_interruptible(&aspeed_jtag->jtag_wq);
> + ret = IRQ_HANDLED;
> + } else {
> + dev_err(aspeed_jtag->dev, "aspeed_jtag irq status:%x\n",
using dev_err will give you sensible prefixes for any messages that
print out. You could remove "aspeed_jtag" from this any any other
prints you have.
> + status);
> + ret = IRQ_NONE;
> + }
> + return ret;
> +}
> +
> +int aspeed_jtag_init(struct platform_device *pdev,
> + struct aspeed_jtag *aspeed_jtag)
> +{
> + struct resource *res;
> + int err;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + aspeed_jtag->reg_base = devm_ioremap_resource(aspeed_jtag->dev, res);
> + if (IS_ERR(aspeed_jtag->reg_base))
> + return -ENOMEM;
> +
> + aspeed_jtag->pclk = devm_clk_get(aspeed_jtag->dev, NULL);
> + if (IS_ERR(aspeed_jtag->pclk)) {
> + dev_err(aspeed_jtag->dev, "devm_clk_get failed\n");
> + return PTR_ERR(aspeed_jtag->pclk);
> + }
> +
> + clk_prepare_enable(aspeed_jtag->pclk);
Can you move this below the platform_get_irq? that way you can return
an error if the getting the IRQ fails, without having to clean up the
clock.
> +
> + aspeed_jtag->irq = platform_get_irq(pdev, 0);
> + if (aspeed_jtag->irq < 0) {
> + dev_err(aspeed_jtag->dev, "no irq specified\n");
> + err = -ENOENT;
> + goto clk_unprep;
> + }
> +
> + /* Enable clock */
> + aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_CTL_ENG_EN |
> + ASPEED_JTAG_CTL_ENG_OUT_EN, ASPEED_JTAG_CTRL);
> + aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
> + ASPEED_JTAG_SW_MODE_TDIO, ASPEED_JTAG_SW);
> +
> + err = devm_request_irq(aspeed_jtag->dev, aspeed_jtag->irq,
> + aspeed_jtag_interrupt, 0,
> + "aspeed-jtag", aspeed_jtag);
> + if (err) {
> + dev_err(aspeed_jtag->dev, "aspeed_jtag unable to get IRQ");
> + goto clk_unprep;
> + }
> + dev_dbg(&pdev->dev, "aspeed_jtag:IRQ %d.\n", aspeed_jtag->irq);
Again, remove the aspeed_jtag prefix.
> +
> + aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_ISR_INST_PAUSE |
> + ASPEED_JTAG_ISR_INST_COMPLETE |
> + ASPEED_JTAG_ISR_DATA_PAUSE |
> + ASPEED_JTAG_ISR_DATA_COMPLETE |
> + ASPEED_JTAG_ISR_INST_PAUSE_EN |
> + ASPEED_JTAG_ISR_INST_COMPLETE_EN |
> + ASPEED_JTAG_ISR_DATA_PAUSE_EN |
> + ASPEED_JTAG_ISR_DATA_COMPLETE_EN,
> + ASPEED_JTAG_ISR);
> +
> + aspeed_jtag->flag = 0;
> + aspeed_jtag->mode = 0;
> + init_waitqueue_head(&aspeed_jtag->jtag_wq);
> + return 0;
> +
> +clk_unprep:
> + clk_disable_unprepare(aspeed_jtag->pclk);
> + return err;
> +}
> +
> +int aspeed_jtag_deinit(struct platform_device *pdev,
> + struct aspeed_jtag *aspeed_jtag)
> +{
> + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_ISR);
> + /* Disable clock */
> + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_CTRL);
> + clk_disable_unprepare(aspeed_jtag->pclk);
> + return 0;
> +}
> +
> +static const struct jtag_ops aspeed_jtag_ops = {
> + .freq_get = aspeed_jtag_freq_get,
> + .freq_set = aspeed_jtag_freq_set,
> + .status_get = aspeed_jtag_status_get,
> + .idle = aspeed_jtag_idle,
> + .xfer = aspeed_jtag_xfer,
> + .mode_set = aspeed_jtag_mode_set
> +};
> +
> +static int aspeed_jtag_probe(struct platform_device *pdev)
> +{
> + struct aspeed_jtag *aspeed_jtag;
> + struct device *dev;
> + struct jtag *jtag;
> + int err;
> +
> + dev = &pdev->dev;
> + if (!of_device_is_compatible(pdev->dev.of_node,
> + "aspeed,ast2500-jtag") &&
> + !of_device_is_compatible(pdev->dev.of_node,
> + "aspeed,ast2400-jtag"))
> + return -ENODEV;
Given the Aspeed device only ever probes with device tree, can you
drop these redundant checks?
> +
> + jtag = jtag_alloc(sizeof(*aspeed_jtag), &aspeed_jtag_ops);
> + if (!jtag)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, jtag);
> + aspeed_jtag = jtag_priv(jtag);
> + aspeed_jtag->dev = &pdev->dev;
> +
> + /* Initialize device*/
> + err = aspeed_jtag_init(pdev, aspeed_jtag);
> + if (err)
> + goto err_jtag_init;
> +
> + /* Initialize JTAG core structure*/
> + err = jtag_register(jtag);
> + if (err)
> + goto err_jtag_register;
> +
> + return 0;
> +
> +err_jtag_register:
> + aspeed_jtag_deinit(pdev, aspeed_jtag);
> +err_jtag_init:
> + jtag_free(jtag);
> + return err;
> +}
> +
> +static int aspeed_jtag_remove(struct platform_device *pdev)
> +{
> + struct jtag *jtag;
> +
> + jtag = platform_get_drvdata(pdev);
> + aspeed_jtag_deinit(pdev, jtag_priv(jtag));
> + jtag_unregister(jtag);
> + jtag_free(jtag);
> + return 0;
> +}
> +
> +static const struct of_device_id aspeed_jtag_of_match[] = {
> + { .compatible = "aspeed,ast2400-jtag", },
> + { .compatible = "aspeed,ast2500-jtag", },
> + {}
> +};
> +
> +static struct platform_driver aspeed_jtag_driver = {
> + .probe = aspeed_jtag_probe,
> + .remove = aspeed_jtag_remove,
> + .driver = {
> + .name = ASPEED_JTAG_NAME,
> + .of_match_table = aspeed_jtag_of_match,
> + },
> +};
> +module_platform_driver(aspeed_jtag_driver);
> +
> +MODULE_AUTHOR("Oleksandr Shamray <oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>");
> +MODULE_DESCRIPTION("ASPEED JTAG driver");
> +MODULE_LICENSE("GPL v2");
> --
> 1.7.1
>
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^ permalink raw reply
* Re: [PATCH v2] ARM64: dts: meson-axg: add ethernet mac controller
From: Yixun Lan @ 2017-12-15 1:46 UTC (permalink / raw)
To: Jerome Brunet, devicetree-u79uwXL29TY76Z2rM5mHXA, Kevin Hilman
Cc: yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ, Neil Armstrong,
Giuseppe Cavallaro, Alexandre Torgue, Carlo Caione,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
netdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1513269947.2261.9.camel-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Hi Jerome:
On 12/15/17 00:45, Jerome Brunet wrote:
> On Thu, 2017-12-14 at 11:02 +0800, Yixun Lan wrote:
>> ---
>> Changes in v2 since [1]:
>> - rebase to kevin's v4.16/dt64 branch
>> - add Neil's Reviewed-by
>> - move clock info to board.dts instead of in soc.dtsi
>
> You got this comment regarding the pwm clock setup. the setup of the pwm clocks
> depends on the use case, so should defined depending on the requirement on the
> board
>
Yes, I thought it was a convention to put the clock into board.dts ..
I think it's more clear if you could have a three level hierarchy:
arch.dtsi. soc.dtsi, board.dts
most of clock and pinctrl could go to soc.dtsi
> This is not the case for the ethmac, the clock setup will be same for every
> board, unless I missed something. the clock bindings should be defined in
> meson-axg.dtsi, I think
>
yes, clock should be same
I will send another series to fix this
also will fold the DT separation (for soc.dtsi vs board.dts)
>> - drop "meson-axg-dwmac" compatible string, since we didn't use this
>> we could re-add it later when we really need.
>> - note: to make ethernet work properly,it depend on clock & pinctrl[2],
>> to compile the DTS, the patch [3] is required.
>> the code part will be taken via clock & pinctrl subsystem tree.
>
> .
>
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^ permalink raw reply
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