* Re: [PATCH v2 1/3] mmc: dt-bindings: add mmc support to MT7623 SoC
From: Ulf Hansson @ 2017-12-15 7:11 UTC (permalink / raw)
To: Matthias Brugger
Cc: sean.wang-NuS5LvNUpcJWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <86e53802-9bb4-35eb-66e1-f9a401e31863-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 14 December 2017 at 12:16, Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Hi Ulf,
>
> On 12/07/2017 07:43 AM, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote:
>> From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>>
>> Add the devicetree binding for MT7623 SoC using MT2701 as the fallback.
>>
>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> ---
>> Documentation/devicetree/bindings/mmc/mtk-sd.txt | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
>> index 72d2a73..9b80176 100644
>> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
>> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
>> @@ -12,6 +12,8 @@ Required properties:
>> "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
>> "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
>> "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
>> + "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
>> +
>> - reg: physical base address of the controller and length
>> - interrupts: Should contain MSDC interrupt number
>> - clocks: Should contain phandle for the clock feeding the MMC controller
>>
>
> Are you fine to take this patch through your branch, or shall I take it through
> mine?
I have pick it up, thanks!
>
> @Sean it seems you forgot to send this patch to Ulf as well. In the future
> please take care to send the patch to all relevant people and mailinglist.
Yeah, thanks for looping me in this time!
Kind regards
Uffe
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* Re: [PATCH v2 1/5] extcon: usbc-cros-ec: add support to notify USB type cables.
From: Chanwoo Choi @ 2017-12-15 6:48 UTC (permalink / raw)
To: Enric Balletbo i Serra, MyungJoo Ham, Lee Jones, Rob Herring,
Heiko Stuebner
Cc: groeck-F7+t8E8rja9g9hUCZPvPmw, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Benson Leung
In-Reply-To: <20171213103219.1464-1-enric.balletbo-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Hi Enric,
Looks good to me. After reviewing the Lee Jones,
I'll take it on next branch.
Regards,
Chanwoo Choi
On 2017년 12월 13일 19:32, Enric Balletbo i Serra wrote:
> From: Benson Leung <bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
>
> Extend the driver to notify host and device type cables and the presence
> of power.
>
> Signed-off-by: Benson Leung <bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> Reviewed-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> ---
> Changes since v1:
> - Use the BIT macro. Requested by Lee Jones.
> - Add the Reviewed-by: Chanwoo Choi.
>
> drivers/extcon/extcon-usbc-cros-ec.c | 142 ++++++++++++++++++++++++++++++++++-
> include/linux/mfd/cros_ec_commands.h | 17 +++++
> 2 files changed, 155 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/extcon/extcon-usbc-cros-ec.c b/drivers/extcon/extcon-usbc-cros-ec.c
> index 6187f73..6721ab0 100644
> --- a/drivers/extcon/extcon-usbc-cros-ec.c
> +++ b/drivers/extcon/extcon-usbc-cros-ec.c
> @@ -34,16 +34,26 @@ struct cros_ec_extcon_info {
>
> struct notifier_block notifier;
>
> + unsigned int dr; /* data role */
> + bool pr; /* power role (true if VBUS enabled) */
> bool dp; /* DisplayPort enabled */
> bool mux; /* SuperSpeed (usb3) enabled */
> unsigned int power_type;
> };
>
> static const unsigned int usb_type_c_cable[] = {
> + EXTCON_USB,
> + EXTCON_USB_HOST,
> EXTCON_DISP_DP,
> EXTCON_NONE,
> };
>
> +enum usb_data_roles {
> + DR_NONE,
> + DR_HOST,
> + DR_DEVICE,
> +};
> +
> /**
> * cros_ec_pd_command() - Send a command to the EC.
> * @info: pointer to struct cros_ec_extcon_info
> @@ -150,6 +160,7 @@ static int cros_ec_usb_get_role(struct cros_ec_extcon_info *info,
> pd_control.port = info->port_id;
> pd_control.role = USB_PD_CTRL_ROLE_NO_CHANGE;
> pd_control.mux = USB_PD_CTRL_MUX_NO_CHANGE;
> + pd_control.swap = USB_PD_CTRL_SWAP_NONE;
> ret = cros_ec_pd_command(info, EC_CMD_USB_PD_CONTROL, 1,
> &pd_control, sizeof(pd_control),
> &resp, sizeof(resp));
> @@ -183,11 +194,72 @@ static int cros_ec_pd_get_num_ports(struct cros_ec_extcon_info *info)
> return resp.num_ports;
> }
>
> +static const char *cros_ec_usb_role_string(unsigned int role)
> +{
> + return role == DR_NONE ? "DISCONNECTED" :
> + (role == DR_HOST ? "DFP" : "UFP");
> +}
> +
> +static const char *cros_ec_usb_power_type_string(unsigned int type)
> +{
> + switch (type) {
> + case USB_CHG_TYPE_NONE:
> + return "USB_CHG_TYPE_NONE";
> + case USB_CHG_TYPE_PD:
> + return "USB_CHG_TYPE_PD";
> + case USB_CHG_TYPE_PROPRIETARY:
> + return "USB_CHG_TYPE_PROPRIETARY";
> + case USB_CHG_TYPE_C:
> + return "USB_CHG_TYPE_C";
> + case USB_CHG_TYPE_BC12_DCP:
> + return "USB_CHG_TYPE_BC12_DCP";
> + case USB_CHG_TYPE_BC12_CDP:
> + return "USB_CHG_TYPE_BC12_CDP";
> + case USB_CHG_TYPE_BC12_SDP:
> + return "USB_CHG_TYPE_BC12_SDP";
> + case USB_CHG_TYPE_OTHER:
> + return "USB_CHG_TYPE_OTHER";
> + case USB_CHG_TYPE_VBUS:
> + return "USB_CHG_TYPE_VBUS";
> + case USB_CHG_TYPE_UNKNOWN:
> + return "USB_CHG_TYPE_UNKNOWN";
> + default:
> + return "USB_CHG_TYPE_UNKNOWN";
> + }
> +}
> +
> +static bool cros_ec_usb_power_type_is_wall_wart(unsigned int type,
> + unsigned int role)
> +{
> + switch (type) {
> + /* FIXME : Guppy, Donnettes, and other chargers will be miscategorized
> + * because they identify with USB_CHG_TYPE_C, but we can't return true
> + * here from that code because that breaks Suzy-Q and other kinds of
> + * USB Type-C cables and peripherals.
> + */
> + case USB_CHG_TYPE_PROPRIETARY:
> + case USB_CHG_TYPE_BC12_DCP:
> + return true;
> + case USB_CHG_TYPE_PD:
> + case USB_CHG_TYPE_C:
> + case USB_CHG_TYPE_BC12_CDP:
> + case USB_CHG_TYPE_BC12_SDP:
> + case USB_CHG_TYPE_OTHER:
> + case USB_CHG_TYPE_VBUS:
> + case USB_CHG_TYPE_UNKNOWN:
> + case USB_CHG_TYPE_NONE:
> + default:
> + return false;
> + }
> +}
> +
> static int extcon_cros_ec_detect_cable(struct cros_ec_extcon_info *info,
> bool force)
> {
> struct device *dev = info->dev;
> int role, power_type;
> + unsigned int dr = DR_NONE;
> + bool pr = false;
> bool polarity = false;
> bool dp = false;
> bool mux = false;
> @@ -206,9 +278,12 @@ static int extcon_cros_ec_detect_cable(struct cros_ec_extcon_info *info,
> dev_err(dev, "failed getting role err = %d\n", role);
> return role;
> }
> + dev_dbg(dev, "disconnected\n");
> } else {
> int pd_mux_state;
>
> + dr = (role & PD_CTRL_RESP_ROLE_DATA) ? DR_HOST : DR_DEVICE;
> + pr = (role & PD_CTRL_RESP_ROLE_POWER);
> pd_mux_state = cros_ec_usb_get_pd_mux_state(info);
> if (pd_mux_state < 0)
> pd_mux_state = USB_PD_MUX_USB_ENABLED;
> @@ -216,20 +291,62 @@ static int extcon_cros_ec_detect_cable(struct cros_ec_extcon_info *info,
> dp = pd_mux_state & USB_PD_MUX_DP_ENABLED;
> mux = pd_mux_state & USB_PD_MUX_USB_ENABLED;
> hpd = pd_mux_state & USB_PD_MUX_HPD_IRQ;
> - }
>
> - if (force || info->dp != dp || info->mux != mux ||
> - info->power_type != power_type) {
> + dev_dbg(dev,
> + "connected role 0x%x pwr type %d dr %d pr %d pol %d mux %d dp %d hpd %d\n",
> + role, power_type, dr, pr, polarity, mux, dp, hpd);
> + }
>
> + /*
> + * When there is no USB host (e.g. USB PD charger),
> + * we are not really a UFP for the AP.
> + */
> + if (dr == DR_DEVICE &&
> + cros_ec_usb_power_type_is_wall_wart(power_type, role))
> + dr = DR_NONE;
> +
> + if (force || info->dr != dr || info->pr != pr || info->dp != dp ||
> + info->mux != mux || info->power_type != power_type) {
> + bool host_connected = false, device_connected = false;
> +
> + dev_dbg(dev, "Type/Role switch! type = %s role = %s\n",
> + cros_ec_usb_power_type_string(power_type),
> + cros_ec_usb_role_string(dr));
> + info->dr = dr;
> + info->pr = pr;
> info->dp = dp;
> info->mux = mux;
> info->power_type = power_type;
>
> - extcon_set_state(info->edev, EXTCON_DISP_DP, dp);
> + if (dr == DR_DEVICE)
> + device_connected = true;
> + else if (dr == DR_HOST)
> + host_connected = true;
>
> + extcon_set_state(info->edev, EXTCON_USB, device_connected);
> + extcon_set_state(info->edev, EXTCON_USB_HOST, host_connected);
> + extcon_set_state(info->edev, EXTCON_DISP_DP, dp);
> + extcon_set_property(info->edev, EXTCON_USB,
> + EXTCON_PROP_USB_VBUS,
> + (union extcon_property_value)(int)pr);
> + extcon_set_property(info->edev, EXTCON_USB_HOST,
> + EXTCON_PROP_USB_VBUS,
> + (union extcon_property_value)(int)pr);
> + extcon_set_property(info->edev, EXTCON_USB,
> + EXTCON_PROP_USB_TYPEC_POLARITY,
> + (union extcon_property_value)(int)polarity);
> + extcon_set_property(info->edev, EXTCON_USB_HOST,
> + EXTCON_PROP_USB_TYPEC_POLARITY,
> + (union extcon_property_value)(int)polarity);
> extcon_set_property(info->edev, EXTCON_DISP_DP,
> EXTCON_PROP_USB_TYPEC_POLARITY,
> (union extcon_property_value)(int)polarity);
> + extcon_set_property(info->edev, EXTCON_USB,
> + EXTCON_PROP_USB_SS,
> + (union extcon_property_value)(int)mux);
> + extcon_set_property(info->edev, EXTCON_USB_HOST,
> + EXTCON_PROP_USB_SS,
> + (union extcon_property_value)(int)mux);
> extcon_set_property(info->edev, EXTCON_DISP_DP,
> EXTCON_PROP_USB_SS,
> (union extcon_property_value)(int)mux);
> @@ -237,6 +354,8 @@ static int extcon_cros_ec_detect_cable(struct cros_ec_extcon_info *info,
> EXTCON_PROP_DISP_HPD,
> (union extcon_property_value)(int)hpd);
>
> + extcon_sync(info->edev, EXTCON_USB);
> + extcon_sync(info->edev, EXTCON_USB_HOST);
> extcon_sync(info->edev, EXTCON_DISP_DP);
>
> } else if (hpd) {
> @@ -322,13 +441,28 @@ static int extcon_cros_ec_probe(struct platform_device *pdev)
> return ret;
> }
>
> + extcon_set_property_capability(info->edev, EXTCON_USB,
> + EXTCON_PROP_USB_VBUS);
> + extcon_set_property_capability(info->edev, EXTCON_USB_HOST,
> + EXTCON_PROP_USB_VBUS);
> + extcon_set_property_capability(info->edev, EXTCON_USB,
> + EXTCON_PROP_USB_TYPEC_POLARITY);
> + extcon_set_property_capability(info->edev, EXTCON_USB_HOST,
> + EXTCON_PROP_USB_TYPEC_POLARITY);
> extcon_set_property_capability(info->edev, EXTCON_DISP_DP,
> EXTCON_PROP_USB_TYPEC_POLARITY);
> + extcon_set_property_capability(info->edev, EXTCON_USB,
> + EXTCON_PROP_USB_SS);
> + extcon_set_property_capability(info->edev, EXTCON_USB_HOST,
> + EXTCON_PROP_USB_SS);
> extcon_set_property_capability(info->edev, EXTCON_DISP_DP,
> EXTCON_PROP_USB_SS);
> extcon_set_property_capability(info->edev, EXTCON_DISP_DP,
> EXTCON_PROP_DISP_HPD);
>
> + info->dr = DR_NONE;
> + info->pr = false;
> +
> platform_set_drvdata(pdev, info);
>
> /* Get PD events from the EC */
> diff --git a/include/linux/mfd/cros_ec_commands.h b/include/linux/mfd/cros_ec_commands.h
> index 2b16e95..a83f649 100644
> --- a/include/linux/mfd/cros_ec_commands.h
> +++ b/include/linux/mfd/cros_ec_commands.h
> @@ -2904,16 +2904,33 @@ enum usb_pd_control_mux {
> USB_PD_CTRL_MUX_AUTO = 5,
> };
>
> +enum usb_pd_control_swap {
> + USB_PD_CTRL_SWAP_NONE = 0,
> + USB_PD_CTRL_SWAP_DATA = 1,
> + USB_PD_CTRL_SWAP_POWER = 2,
> + USB_PD_CTRL_SWAP_VCONN = 3,
> + USB_PD_CTRL_SWAP_COUNT
> +};
> +
> struct ec_params_usb_pd_control {
> uint8_t port;
> uint8_t role;
> uint8_t mux;
> + uint8_t swap;
> } __packed;
>
> #define PD_CTRL_RESP_ENABLED_COMMS (1 << 0) /* Communication enabled */
> #define PD_CTRL_RESP_ENABLED_CONNECTED (1 << 1) /* Device connected */
> #define PD_CTRL_RESP_ENABLED_PD_CAPABLE (1 << 2) /* Partner is PD capable */
>
> +#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */
> +#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */
> +#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */
> +#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */
> +#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */
> +#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */
> +#define PD_CTRL_RESP_ROLE_EXT_POWERED BIT(6) /* Partner externally powerd */
> +
> struct ec_response_usb_pd_control_v1 {
> uint8_t enabled;
> uint8_t role;
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
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^ permalink raw reply
* [PATCH v2 19/19] ARM: dts: aspeed-plametto: Add flash layout
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
The OpenBMC flash layout is used by Palmetto systems.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index a8f0c046e83e..cc18137386f2 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -34,6 +34,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
+#include "openbmc-flash-layout.dtsi"
};
};
--
2.14.1
^ permalink raw reply related
* [PATCH v2 18/19] ARM: dts: aspeed-romulus: Update Romulus system
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
- Fix incorrect RAM size
- Remove alias; these are now specified in the dtsi
- Add newly upstreamed devices
- Include OpenBMC flash layout
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 153 ++++++++++++++++++++++++++-
1 file changed, 148 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index a7a9386f964d..bfdf643584df 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -7,17 +7,13 @@
model = "Romulus BMC";
compatible = "ibm,romulus-bmc", "aspeed,ast2500";
- aliases {
- serial4 = &uart5;
- };
-
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
- reg = <0x80000000 0x40000000>;
+ reg = <0x80000000 0x20000000>;
};
reserved-memory {
@@ -29,6 +25,73 @@
no-map;
reg = <0xbf000000 0x01000000>; /* 16M */
};
+
+ flash_memory: region@98000000 {
+ no-map;
+ reg = <0x98000000 0x04000000>; /* 64M */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ fault {
+ gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ identify {
+ gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+ };
+
+ power {
+ gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ fsi: gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
+ mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ checkstop {
+ label = "checkstop";
+ gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(J, 2)>;
+ };
+ };
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ label = "pnor";
+ m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ label = "pnor";
+ m25p,fast-read;
};
};
@@ -38,6 +101,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
+#include "openbmc-flash-layout.dtsi"
};
};
@@ -53,6 +117,12 @@
};
};
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
&uart1 {
/* Rear RS-232 connector */
status = "okay";
@@ -81,6 +151,10 @@
pinctrl-0 = <&pinctrl_rmii1_default>;
};
+&i2c1 {
+ status = "okay";
+};
+
&i2c2 {
status = "okay";
};
@@ -133,8 +207,77 @@
&i2c12 {
status = "okay";
+
+ max31785@52 {
+ compatible = "maxim,max31785";
+ reg = <0x52>;
+ };
+};
+
+&gpio {
+ nic_func_mode0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "nic_func_mode0";
+ };
+ nic_func_mode1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "nic_func_mode1";
+ };
};
&vuart {
status = "okay";
};
+
+&gfx {
+ status = "okay";
+};
+
+&pinctrl {
+ aspeed,external-nodes = <&gfx &lhc>;
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x08>;
+ };
+
+ fan@1 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x09>;
+ };
+
+ fan@2 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
+ };
+
+ fan@3 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
+ };
+
+ fan@4 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
+ };
+
+ fan@5 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
+ };
+
+ fan@6 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
+ };
+};
--
2.14.1
^ permalink raw reply related
* [PATCH v2 17/19] ARM: dts: aspeed: Add Qanta Q71L BMC machine
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Rick Altherr, Cédric Le Goater, Benjamin Herrenschmidt,
Jeremy Kerr, devicetree, linux-arm-kernel, linux-kernel,
linux-aspeed, Peter Hanson
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
From: Rick Altherr <raltherr@google.com>
The Qanta Q71L BMC is an ASPEED ast2400 based BMC that is part of a
Qanta x86 server.
This adds the device tree description for most upstream components. It
is a squashed commit from the OpenBMC kernel tree.
Signed-off-by: Peter Hanson <peterh@google.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Patrick Venture <venture@google.com>
Signed-off-by: Rick Altherr <raltherr@google.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 458 +++++++++++++++++++++++++++
2 files changed, 460 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 48c55f307aa9..5ab5d9169511 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1106,5 +1106,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-opp-palmetto.dtb \
aspeed-bmc-opp-romulus.dtb \
aspeed-bmc-opp-witherspoon.dtb \
- aspeed-bmc-opp-zaius.dtb
+ aspeed-bmc-opp-zaius.dtb \
+ aspeed-bmc-quanta-q71l.dtb
endif
diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
new file mode 100644
index 000000000000..2f40bab63149
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "aspeed-g4.dtsi"
+
+/ {
+ model = "Quanta Q71L BMC";
+ compatible = "quanta,q71l-bmc", "aspeed,ast2400";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory {
+ reg = <0x40000000 0x8000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vga_memory: framebuffer@47800000 {
+ no-map;
+ reg = <0x47800000 0x00800000>; /* 8MB */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ power {
+ gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ identify {
+ gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>;
+ };
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 11>;
+ };
+
+ i2c1mux: i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */
+ i2c-parent = <&i2c1>;
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ label = "bmc";
+ m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ };
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default
+ &pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
+};
+
+&lpc_snoop {
+ status = "okay";
+ snoop-ports = <0x80>;
+};
+
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ /* temp2 inlet */
+ tmp75@4c {
+ compatible = "ti,tmp75";
+ reg = <0x4c>;
+ };
+
+ /* temp3 */
+ tmp75@4e {
+ compatible = "ti,tmp75";
+ reg = <0x4e>;
+ };
+
+ /* temp1 */
+ tmp75@4f {
+ compatible = "ti,tmp75";
+ reg = <0x4f>;
+ };
+
+ /* Baseboard FRU */
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
+
+ /* FP FRU */
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ /* 0: PCIe Slot 2,
+ * Slot 3,
+ * Slot 6,
+ * Slot 7
+ */
+ i2c-switch@74 {
+ compatible = "nxp,pca9546";
+ reg = <0x74>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux@77 next. */
+
+ i2c_pcie2: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_pcie3: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_pcie6: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_pcie7: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+
+ /* 0: PCIe Slot 1,
+ * Slot 4,
+ * Slot 5,
+ * Slot 8,
+ * Slot 9,
+ * Slot 10,
+ * SSD 1,
+ * SSD 2
+ */
+ i2c-switch@77 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x77>;
+ i2c-mux-idle-disconnect; /* may use mux@74 next. */
+
+ i2c_pcie1: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_pcie4: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_pcie5: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_pcie8: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ i2c_pcie9: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ i2c_pcie10: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ i2c_ssd1: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ i2c_ssd2: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+
+ /* BIOS FRU */
+ eeprom@56 {
+ compatible = "atmel,24c64";
+ reg = <0x56>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* 0: PSU4
+ * PSU1
+ * PSU3
+ * PSU2
+ */
+ i2c-switch@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c_psu4: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_psu1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_psu3: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_psu2: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+
+ /* PDB FRU */
+ eeprom@52 {
+ compatible = "atmel,24c64";
+ reg = <0x52>;
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ /* BMC FRU */
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+};
+
+&vuart {
+ status = "okay";
+};
+
+&wdt2 {
+ status = "okay";
+};
+
+&pwm_tacho {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm2_default
+ &pinctrl_pwm3_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan@1 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan@2 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan@3 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+
+ fan@4 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+ fan@5 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+ };
+
+ fan@6 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+ };
+
+ fan@7 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+ };
+};
+
+&i2c1mux {
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Memory Riser 1 FRU */
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+
+ /* Memory Riser 2 FRU */
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
+ /* Memory Riser 3 FRU */
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ /* Memory Riser 4 FRU */
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
+ };
+
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Memory Riser 5 FRU */
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+
+ /* Memory Riser 6 FRU */
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
+ /* Memory Riser 7 FRU */
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ /* Memory Riser 8 FRU */
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
+ };
+};
--
2.14.1
^ permalink raw reply related
* [PATCH v2 16/19] ARM: dts: aspeed: Add Ingrasys Zaius BMC machine
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed,
Robert Lippert, Peter Hanson, Rick Altherr
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
From: Xo Wang <xow@google.com>
Zaius is a POWER9 platform announced at OpenPOWER Summit 2016. This adds
basic DTS support for its AST2500 BMC.
This adds the device tree description for most upstream components. It
is a squashed commit of all of the patches from the OpenBMC kernel tree.
Signed-off-by: Xo Wang <xow@google.com>
Signed-off-by: Patrick Venture <venture@google.com>
Signed-off-by: Robert Lippert <rlippert@google.com>
Signed-off-by: Peter Hanson <peterh@google.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Rick Altherr <raltherr@google.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/Makefile | 4 +-
arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 427 +++++++++++++++++++++++++++++
2 files changed, 429 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 15a9207319c1..48c55f307aa9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1105,6 +1105,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-bmc-opp-palmetto.dtb \
aspeed-bmc-opp-romulus.dtb \
- aspeed-bmc-opp-witherspoon.dtb
-
+ aspeed-bmc-opp-witherspoon.dtb \
+ aspeed-bmc-opp-zaius.dtb
endif
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
new file mode 100644
index 000000000000..90d77012495d
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "Zaius BMC";
+ compatible = "ingrasys,zaius-bmc", "aspeed,ast2500";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region@98000000 {
+ no-map;
+ reg = <0x98000000 0x04000000>; /* 64M */
+ };
+ };
+
+ onewire0 {
+ compatible = "w1-gpio";
+ gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
+ };
+
+ onewire1 {
+ compatible = "w1-gpio";
+ gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ };
+
+ onewire2 {
+ compatible = "w1-gpio";
+ gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ };
+
+ onewire3 {
+ compatible = "w1-gpio";
+ gpios = <&gpio ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ checkstop {
+ label = "checkstop";
+ gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(F, 7)>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ sys_boot_status {
+ label = "System boot status";
+ gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_LOW>;
+ };
+
+ attention {
+ label = "Attention";
+ gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>;
+ };
+
+ plt_fault {
+ label = "Platform fault";
+ gpios = <&gpio ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ hdd_fault {
+ label = "Onboard drive fault";
+ gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ fsi: gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ trans-gpios = <&gpio ASPEED_GPIO(O, 6) GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ clock-gpios = <&gpio ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
+ mux-gpios = <&gpio ASPEED_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
+ <&adc 13>, <&adc 14>, <&adc 15>;
+ };
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 12>;
+ };
+
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ label = "bmc";
+ m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ label = "pnor";
+ m25p,fast-read;
+ };
+};
+
+&spi2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2ck_default
+ &pinctrl_spi2cs0_default
+ &pinctrl_spi2cs1_default
+ &pinctrl_spi2miso_default
+ &pinctrl_spi2mosi_default>;
+
+ flash@0 {
+ status = "okay";
+ };
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default>;
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&lpc_snoop {
+ status = "okay";
+ snoop-ports = <0x80>;
+};
+
+
+&uart5 {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+
+ rtc@68 {
+ compatible = "nxp,pcf8523";
+ reg = <0x68>;
+ };
+
+ ucd90160@64 {
+ compatible = "ti,ucd90160";
+ reg = <0x64>;
+ };
+
+ /* Power sequencer UCD90160 PMBUS @64h
+ * FRU AT24C64D @50h
+ * RTC PCF8523 @68h
+ * Clock buffer 9DBL04 @6dh
+ */
+};
+
+&i2c1 {
+ status = "okay";
+
+ i2c-switch@71 {
+ compatible = "nxp,pca9546";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* MUX1 PCA9546A @71h
+ * PCIe 0
+ * PCIe 1
+ * PCIe 2
+ * TPM header
+ */
+};
+
+&i2c2 {
+ status = "disabled";
+
+ /* OCP Mezz Connector A (OOB SMBUS) */
+};
+
+&i2c3 {
+ status = "disabled";
+
+ /* OCP Mezz Connector A (PCIe slot SMBUS) */
+};
+
+&i2c4 {
+ status = "okay";
+
+ i2c-switch@71 {
+ compatible = "nxp,pca9546";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* MUX1 PCA9546A @71h
+ * PCIe 3
+ * PCIe 4
+ */
+};
+
+
+&i2c5 {
+ status = "disabled";
+
+ /* CPU0 PRM 0.7V */
+ /* CPU0 PRM 1.2V CH03 */
+ /* CPU0 PRM 0.8V */
+ /* CPU0 PRM 1.2V CH47 */
+};
+
+&i2c6 {
+ status = "disabled";
+
+ /* CPU1 PRM 0.7V */
+ /* CPU1 PRM 1.2V CH03 */
+ /* CPU1 PRM 0.8V */
+ /* CPU1 PRM 1.2V CH47 */
+};
+
+&i2c7 {
+ status = "okay";
+
+ pca9541a@70 {
+ compatible = "nxp,pca9541";
+ reg = <0x70>;
+
+ i2c-arb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hotswap@54 {
+ compatible = "ti,lm5066i";
+ reg = <0x54>;
+ };
+ };
+ };
+
+ /* Master selector PCA9541A @70h (other master: CPU0)
+ * LM5066I PMBUS @10h
+ */
+
+ /* 12V Quarter Brick DC/DC Converter Q54SJ12050 @61h */
+ power-brick@61 {
+ compatible = "delta,dps800";
+ reg = <0x61>;
+ };
+
+ /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */
+ /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */
+ /* CPU0 VR ISL68137 0.8V PMBUS @60h */
+ /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @41h */
+ /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */
+};
+
+&i2c8 {
+ status = "okay";
+
+ /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @65h */
+ /* CPU1 VR ISL68137 1.2V CH03 PMBUS @44h */
+ /* CPU1 VR ISL68137 0.8V PMBUS @61h */
+ /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */
+ /* CPU0 VR ISL68137 1.2V CH47 PMBUS @45h */
+};
+
+
+&i2c9 {
+ status = "disabled";
+
+ /* Fan board */
+};
+
+&i2c10 {
+ status = "disabled";
+};
+
+&i2c11 {
+ status = "disabled";
+
+ /* GPU sideband */
+};
+
+&i2c12 {
+ status = "disabled";
+};
+
+&i2c13 {
+ status = "disabled";
+
+ /* MUX PI3USB102
+ * CPU0 debug
+ * CPU1 debug
+ */
+};
+
+&pinctrl {
+ aspeed,external-nodes = <&gfx &lhc>;
+
+ pinctrl_gpioh_unbiased: gpioi_unbiased {
+ pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7";
+ bias-disable;
+ };
+};
+
+&gpio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpioh_unbiased>;
+
+ line_iso_u146_en {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(O, 4) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "iso_u164_en";
+ };
+
+ ncsi_mux_en_n {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "ncsi_mux_en_n";
+ };
+
+ line_bmc_i2c2_sw_rst_n {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "bmc_i2c2_sw_rst_n";
+ };
+
+ line_bmc_i2c5_sw_rst_n {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "bmc_i2c5_sw_rst_n";
+ };
+};
+
+&vuart {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
+ &pinctrl_pwm2_default &pinctrl_pwm3_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan@1 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan@2 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan@3 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+};
--
2.14.1
^ permalink raw reply related
* [PATCH v2 15/19] ARM: dts: aspeed: Add Witherspoon BMC machine
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed,
Brandon Wyman, Matt Spinler, Brad Bishop, Edward A . James
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
The Witherspoon BMC is an ASPEED ast2500 based BMC that is part of an
OpenPower Power9 server.
This adds the device tree description for most upstream components. It
is a squashed commit from the OpenBMC kernel tree.
Signed-off-by: Brandon Wyman <bjwyman@gmail.com>
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Edward A. James <eajames@us.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Brandon Wyman <bjwyman@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
--
v2:
Add Brandon's reviewed-by tag
---
arch/arm/boot/dts/Makefile | 4 +-
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 547 +++++++++++++++++++++++
2 files changed, 550 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5d1e9d37bf3a..15a9207319c1 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1104,5 +1104,7 @@ dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-bmc-opp-palmetto.dtb \
- aspeed-bmc-opp-romulus.dtb
+ aspeed-bmc-opp-romulus.dtb \
+ aspeed-bmc-opp-witherspoon.dtb
+
endif
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
new file mode 100644
index 000000000000..9a0937512e5b
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -0,0 +1,547 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/leds/leds-pca955x.h>
+
+/ {
+ model = "Witherspoon BMC";
+ compatible = "ibm,witherspoon-bmc", "aspeed,ast2500";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region@98000000 {
+ no-map;
+ reg = <0x98000000 0x04000000>; /* 64M */
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <1000>;
+
+ fan0-presence {
+ label = "fan0-presence";
+ gpios = <&pca0 4 GPIO_ACTIVE_LOW>;
+ linux,code = <4>;
+ };
+
+ fan1-presence {
+ label = "fan1-presence";
+ gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
+ linux,code = <5>;
+ };
+
+ fan2-presence {
+ label = "fan2-presence";
+ gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
+ linux,code = <6>;
+ };
+
+ fan3-presence {
+ label = "fan3-presence";
+ gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
+ linux,code = <7>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ fan0 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 0 GPIO_ACTIVE_LOW>;
+ };
+
+ fan1 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 1 GPIO_ACTIVE_LOW>;
+ };
+
+ fan2 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 2 GPIO_ACTIVE_LOW>;
+ };
+
+ fan3 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 3 GPIO_ACTIVE_LOW>;
+ };
+
+ front-fault {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 13 GPIO_ACTIVE_LOW>;
+ };
+
+ front-power {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 14 GPIO_ACTIVE_LOW>;
+ };
+
+ front-id {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 15 GPIO_ACTIVE_LOW>;
+ };
+
+ rear-fault {
+ gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ rear-id {
+ gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>;
+ };
+
+ rear-power {
+ gpios = <&gpio ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>;
+ };
+
+ power-button {
+ gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ fsi: gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>;
+ mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ };
+
+ iio-hwmon-dps310 {
+ compatible = "iio-hwmon";
+ io-channels = <&dps 0>;
+ };
+
+ iio-hwmon-bmp280 {
+ compatible = "iio-hwmon";
+ io-channels = <&bmp 1>;
+ };
+
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ label = "bmc";
+ m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ label = "alt";
+ m25p,fast-read;
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ label = "pnor";
+ m25p,fast-read;
+ };
+};
+
+&uart1 {
+ /* Rear RS-232 connector */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default
+ &pinctrl_nrts1_default
+ &pinctrl_ndtr1_default
+ &pinctrl_ndsr1_default
+ &pinctrl_ncts1_default
+ &pinctrl_ndcd1_default
+ &pinctrl_nri1_default>;
+};
+
+&uart2 {
+ /* APSS */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&i2c2 {
+ status = "okay";
+
+ /* MUX ->
+ * Samtec 1
+ * Samtec 2
+ */
+};
+
+&i2c3 {
+ status = "okay";
+
+ bmp: bmp280@77 {
+ compatible = "bosch,bmp280";
+ reg = <0x77>;
+ #io-channel-cells = <1>;
+ };
+
+ max31785@52 {
+ compatible = "maxim,max31785a";
+ reg = <0x52>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ dps: dps310@76 {
+ compatible = "infineon,dps310";
+ reg = <0x76>;
+ #io-channel-cells = <0>;
+ };
+
+ pca0: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ power-supply@68 {
+ compatible = "ibm,cffps1";
+ reg = <0x68>;
+ };
+
+ power-supply@69 {
+ compatible = "ibm,cffps1";
+ reg = <0x69>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@70 {
+ compatible = "infineon,ir35221";
+ reg = <0x70>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+};
+
+
+&i2c5 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@70 {
+ compatible = "infineon,ir35221";
+ reg = <0x70>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+};
+
+&i2c10 {
+ /* MUX
+ * -> PCIe Slot 3
+ * -> PCIe Slot 4
+ */
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+
+ pca9552: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N",
+ "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF",
+ "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF",
+ "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF",
+ "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF",
+ "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF",
+ "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF",
+ "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N";
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ ucd90160@64 {
+ compatible = "ti,ucd90160";
+ reg = <0x64>;
+ };
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+};
+
+&pinctrl {
+ aspeed,external-nodes = <&gfx &lhc>;
+};
+
+&wdt1 {
+ aspeed,reset-type = "none";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+};
--
2.14.1
^ permalink raw reply related
* [PATCH v2 14/19] ARM: dts: aspeed: Sort ASPEED entries in makefile
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20171215062443.23059-1-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
In preperation for adding more boards.
Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0381e9caf21..5d1e9d37bf3a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1101,7 +1101,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt8127-moose.dtb \
mt8135-evbp1.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
-dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
- aspeed-bmc-opp-romulus.dtb \
- aspeed-ast2500-evb.dtb
+dtb-$(CONFIG_ARCH_ASPEED) += \
+ aspeed-ast2500-evb.dtb \
+ aspeed-bmc-opp-palmetto.dtb \
+ aspeed-bmc-opp-romulus.dtb
endif
--
2.14.1
--
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^ permalink raw reply related
* [PATCH v2 13/19] ARM: dts: Add OpenBMC flash layout
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
This is a layout used by OpenBMC systems. It describes the fixed flash
layout of a 32MB mtd device.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/openbmc-flash-layout.dtsi | 32 +++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 arch/arm/boot/dts/openbmc-flash-layout.dtsi
diff --git a/arch/arm/boot/dts/openbmc-flash-layout.dtsi b/arch/arm/boot/dts/openbmc-flash-layout.dtsi
new file mode 100644
index 000000000000..63ad8db7a431
--- /dev/null
+++ b/arch/arm/boot/dts/openbmc-flash-layout.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u-boot@0 {
+ reg = <0x0 0x60000>;
+ label = "u-boot";
+ };
+
+ u-boot-env@60000 {
+ reg = <0x60000 0x20000>;
+ label = "u-boot-env";
+ };
+
+ kernel@80000 {
+ reg = <0x80000 0x440000>;
+ label = "kernel";
+ };
+
+ rofs@0c0000 {
+ reg = <0x4c0000 0x1740000>;
+ label = "rofs";
+ };
+
+ rwfs@1c00000 {
+ reg = <0x1c00000 0x400000>;
+ label = "rwfs";
+ };
+};
--
2.14.1
^ permalink raw reply related
* [PATCH v2 12/19] ARM: dts: aspeed: Update license headers
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
In b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier
to files with no license") these files had the GPL-2.0 licence added
automatically. Update them to be GPL 2.0+ in line with other IBM kernel
contributions.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +-
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 2 +-
arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 2 +-
arch/arm/boot/dts/aspeed-g4.dtsi | 2 +-
arch/arm/boot/dts/aspeed-g5.dtsi | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index 602bc10fdaf4..3e6f38e5d5d0 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index c786bc2f2919..a8f0c046e83e 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g4.dtsi"
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 8067793129ea..a7a9386f964d 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 2d7ac577d6b5..9c175832babc 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/gpio/aspeed-gpio.h>
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 030a760696fd..360329eab7c3 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/gpio/aspeed-gpio.h>
--
2.14.1
^ permalink raw reply related
* [PATCH v2 11/19] ARM: dts: aspeed: Remove skeleton.dtsi
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
We don't require it for any of the ASPEED systems.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 1 -
arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b3580f37f507..2d7ac577d6b5 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -1,5 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
-#include "skeleton.dtsi"
#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/gpio/aspeed-gpio.h>
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 50766f0629f8..030a760696fd 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -1,5 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
-#include "skeleton.dtsi"
#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/gpio/aspeed-gpio.h>
--
2.14.1
^ permalink raw reply related
* [PATCH v2 10/19] ARM: dts: aspeed: Add LPC Snoop device
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
LPC snoop hardware on the ASPEED BMC, used for monitoring
host I/O port activity.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 7 +++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index f6fee40c04c0..b3580f37f507 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -236,6 +236,13 @@
status = "disabled";
};
+ lpc_snoop: lpc-snoop@0 {
+ compatible = "aspeed,ast2500-lpc-snoop";
+ reg = <0x0 0x80>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 96a9d2fe3f0d..50766f0629f8 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -287,6 +287,12 @@
status = "disabled";
};
+ lpc_snoop: lpc-snoop@0 {
+ compatible = "aspeed,ast2500-lpc-snoop";
+ reg = <0x0 0x80>;
+ interrupts = <8>;
+ status = "disabled";
+ };
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
--
2.14.1
^ permalink raw reply related
* [PATCH v2 09/19] ARM: dts: aspeed: Add PWM and tachometer node
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20171215062443.23059-1-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 9 +++++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 9 +++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index fa52a01f50b5..f6fee40c04c0 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -189,6 +189,15 @@
clocks = <&syscon ASPEED_CLK_APB>;
};
+ pwm_tacho: pwm-tacho-controller@1e786000 {
+ compatible = "aspeed,ast2400-pwm-tacho";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1e786000 0x1000>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ status = "disabled";
+ };
+
vuart: serial@1e787000 {
compatible = "aspeed,ast2400-vuart";
reg = <0x1e787000 0x40>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 5e6db2aa5c23..96a9d2fe3f0d 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -239,6 +239,15 @@
status = "disabled";
};
+ pwm_tacho: pwm-tacho-controller@1e786000 {
+ compatible = "aspeed,ast2500-pwm-tacho";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1e786000 0x1000>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ status = "disabled";
+ };
+
vuart: serial@1e787000 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787000 0x40>;
--
2.14.1
--
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^ permalink raw reply related
* [PATCH v2 08/19] ARM: dts: aspeed: Add clock phandle to GPIO
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
This enables a feature where the driver can debounce inputs.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 1 +
arch/arm/boot/dts/aspeed-g5.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index afac0ca0cb10..fa52a01f50b5 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -144,6 +144,7 @@
reg = <0x1e780000 0x1000>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 220>;
+ clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index f3689caf6fe2..5e6db2aa5c23 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -187,6 +187,7 @@
reg = <0x1e780000 0x1000>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 220>;
+ clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
};
--
2.14.1
^ permalink raw reply related
* [PATCH v2 07/19] ARM: dts: aspeed: Add flash controller clocks
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++
2 files changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 2e3666d4fbeb..afac0ca0cb10 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -56,6 +56,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-fmc";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
interrupts = <19>;
flash@0 {
@@ -71,6 +72,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-spi";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 24bb2d16b900..f3689caf6fe2 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -56,6 +56,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
interrupts = <19>;
flash@0 {
@@ -81,6 +82,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
@@ -100,6 +102,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
--
2.14.1
^ permalink raw reply related
* [PATCH v2 06/19] ARM: dts: aspeed: Add watchdog clocks
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20171215062443.23059-1-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++
2 files changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index cf407b4db630..2e3666d4fbeb 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -177,11 +177,13 @@
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2400-wdt";
reg = <0x1e785000 0x1c>;
+ clocks = <&syscon ASPEED_CLK_APB>;
};
wdt2: watchdog@1e785020 {
compatible = "aspeed,ast2400-wdt";
reg = <0x1e785020 0x1c>;
+ clocks = <&syscon ASPEED_CLK_APB>;
};
vuart: serial@1e787000 {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index ab26156d6822..24bb2d16b900 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -219,16 +219,19 @@
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785000 0x20>;
+ clocks = <&syscon ASPEED_CLK_APB>;
};
wdt2: watchdog@1e785020 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785020 0x20>;
+ clocks = <&syscon ASPEED_CLK_APB>;
};
wdt3: watchdog@1e785040 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785040 0x20>;
+ clocks = <&syscon ASPEED_CLK_APB>;
status = "disabled";
};
--
2.14.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v2 05/19] ARM: dts: aspeed: Add MAC clocks
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
arch/arm/boot/dts/aspeed-g5.dtsi | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index c87883a7f250..cf407b4db630 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -91,6 +91,7 @@
compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
interrupts = <2>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
status = "disabled";
};
@@ -98,6 +99,7 @@
compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
reg = <0x1e680000 0x180>;
interrupts = <3>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 90bc09d93ea6..ab26156d6822 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -125,6 +125,7 @@
compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
interrupts = <2>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
status = "disabled";
};
@@ -132,6 +133,7 @@
compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e680000 0x180>;
interrupts = <3>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
status = "disabled";
};
--
2.14.1
^ permalink raw reply related
* [PATCH v2 04/19] ARM: dts: aspeed: Add proper clock references
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
This device tree will break existing kernels that do not have the clk
patches applied (no clocksource, as we don't know the speed of the APB
clock. You can boot if you pass a lpj value on the command line, but
won't have a uart).
Older device trees running with the newer kernel will function as well
as pre-4.16 kernels. That is, that some IP blocks (i2c, pwm/tach, adc)
will not work as the kernel lacks reset controller and clock enabling.
This is being changed as existing device trees use fixed-clocks in order
to boot without a clk driver. The newly added clk driver provides proper
clock support, including gating, so we move the device trees over to
properly request clocks.
The SCU compatible string is updated as the g4-scu string made it into
the tree before we decided on aspeed,astX000-<ip> as the format for the
strings. The old string will be removed from the bindings in a future
patch.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v2:
- Add more detail to the commit message
---
arch/arm/boot/dts/aspeed-g4.dtsi | 102 +++++++++++++++-----------------------
arch/arm/boot/dts/aspeed-g5.dtsi | 104 +++++++++++++++------------------------
2 files changed, 82 insertions(+), 124 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index a3bc5da7d42c..c87883a7f250 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
+#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
@@ -107,47 +108,12 @@
ranges;
syscon: syscon@1e6e2000 {
- compatible = "aspeed,g4-scu", "syscon", "simple-mfd";
+ compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
-
- clk_clkin: clk_clkin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <48000000>;
- };
-
- clk_hpll: clk_hpll@70 {
- #clock-cells = <0>;
- compatible = "aspeed,g4-hpll-clock", "fixed-clock";
- reg = <0x70>;
- clocks = <&clk_clkin>;
- clock-frequency = <384000000>;
- };
-
- clk_ahb: clk_ahb@70 {
- #clock-cells = <0>;
- compatible = "aspeed,g4-ahb-clock", "fixed-clock";
- reg = <0x70>;
- clocks = <&clk_hpll>;
- clock-frequency = <192000000>;
- };
-
- clk_apb: clk_apb@8 {
- #clock-cells = <0>;
- compatible = "aspeed,g4-apb-clock", "fixed-clock";
- reg = <0x08>;
- clocks = <&clk_hpll>;
- clock-frequency = <48000000>;
- };
-
- clk_uart: clk_uart@2c{
- #clock-cells = <0>;
- compatible = "aspeed,g4-uart-clock", "fixed-clock";
- reg = <0x2c>;
- clock-frequency = <24000000>;
- };
+ #clock-cells = <1>;
+ #reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,g4-pinctrl";
@@ -157,7 +123,7 @@
adc: adc@1e6e9000 {
compatible = "aspeed,ast2400-adc";
reg = <0x1e6e9000 0xb0>;
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
#io-channel-cells = <1>;
status = "disabled";
};
@@ -182,7 +148,7 @@
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
interrupts = <16 17 18 35 36 37 38 39>;
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
clock-names = "PCLK";
};
@@ -191,7 +157,7 @@
reg = <0x1e783000 0x20>;
reg-shift = <2>;
interrupts = <9>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
no-loopback-test;
status = "disabled";
};
@@ -201,7 +167,7 @@
reg = <0x1e784000 0x20>;
reg-shift = <2>;
interrupts = <10>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
no-loopback-test;
status = "disabled";
};
@@ -220,8 +186,8 @@
compatible = "aspeed,ast2400-vuart";
reg = <0x1e787000 0x40>;
reg-shift = <2>;
- interrupts = <10>;
- clocks = <&clk_uart>;
+ interrupts = <8>;
+ clocks = <&syscon ASPEED_CLK_APB>;
no-loopback-test;
status = "disabled";
};
@@ -266,7 +232,7 @@
reg = <0x1e78d000 0x20>;
reg-shift = <2>;
interrupts = <32>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
no-loopback-test;
status = "disabled";
};
@@ -276,7 +242,7 @@
reg = <0x1e78e000 0x20>;
reg-shift = <2>;
interrupts = <33>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
no-loopback-test;
status = "disabled";
};
@@ -286,7 +252,7 @@
reg = <0x1e78f000 0x20>;
reg-shift = <2>;
interrupts = <34>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
no-loopback-test;
status = "disabled";
};
@@ -317,7 +283,8 @@
reg = <0x40 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <0>;
interrupt-parent = <&i2c_ic>;
@@ -332,7 +299,8 @@
reg = <0x80 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <1>;
interrupt-parent = <&i2c_ic>;
@@ -347,7 +315,8 @@
reg = <0xc0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <2>;
interrupt-parent = <&i2c_ic>;
@@ -363,7 +332,8 @@
reg = <0x100 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <3>;
interrupt-parent = <&i2c_ic>;
@@ -379,7 +349,8 @@
reg = <0x140 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <4>;
interrupt-parent = <&i2c_ic>;
@@ -395,7 +366,8 @@
reg = <0x180 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <5>;
interrupt-parent = <&i2c_ic>;
@@ -411,7 +383,8 @@
reg = <0x1c0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <6>;
interrupt-parent = <&i2c_ic>;
@@ -427,7 +400,8 @@
reg = <0x300 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <7>;
interrupt-parent = <&i2c_ic>;
@@ -443,7 +417,8 @@
reg = <0x340 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <8>;
interrupt-parent = <&i2c_ic>;
@@ -459,7 +434,8 @@
reg = <0x380 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <9>;
interrupt-parent = <&i2c_ic>;
@@ -475,7 +451,8 @@
reg = <0x3c0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <10>;
interrupt-parent = <&i2c_ic>;
@@ -491,7 +468,8 @@
reg = <0x400 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <11>;
interrupt-parent = <&i2c_ic>;
@@ -507,7 +485,8 @@
reg = <0x440 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <12>;
interrupt-parent = <&i2c_ic>;
@@ -523,7 +502,8 @@
reg = <0x480 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <13>;
interrupt-parent = <&i2c_ic>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 7861631940fe..90bc09d93ea6 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
+#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
@@ -141,55 +142,18 @@
ranges;
syscon: syscon@1e6e2000 {
- compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
+ compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
-
- clk_clkin: clk_clkin@70 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-clkin-clock", "fixed-clock";
- reg = <0x70>;
- clock-frequency = <24000000>;
- };
-
- clk_hpll: clk_hpll@24 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-hpll-clock", "fixed-clock";
- reg = <0x24>;
- clocks = <&clk_clkin>;
- clock-frequency = <792000000>;
- };
-
- clk_ahb: clk_ahb@70 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-ahb-clock", "fixed-clock";
- reg = <0x70>;
- clocks = <&clk_hpll>;
- clock-frequency = <198000000>;
- };
-
- clk_apb: clk_apb@8 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-apb-clock", "fixed-clock";
- reg = <0x08>;
- clocks = <&clk_hpll>;
- clock-frequency = <24750000>;
- };
-
- clk_uart: clk_uart@2c {
- #clock-cells = <0>;
- compatible = "aspeed,uart-clock", "fixed-clock";
- reg = <0x2c>;
- clock-frequency = <24000000>;
- };
+ #clock-cells = <1>;
+ #reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,g5-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
};
-
};
gfx: display@1e6e6000 {
@@ -201,7 +165,7 @@
adc: adc@1e6e9000 {
compatible = "aspeed,ast2500-adc";
reg = <0x1e6e9000 0xb0>;
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
#io-channel-cells = <1>;
status = "disabled";
};
@@ -226,7 +190,7 @@
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
interrupts = <16 17 18 35 36 37 38 39>;
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
clock-names = "PCLK";
};
@@ -235,7 +199,7 @@
reg = <0x1e783000 0x20>;
reg-shift = <2>;
interrupts = <9>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
no-loopback-test;
status = "disabled";
};
@@ -245,7 +209,7 @@
reg = <0x1e784000 0x20>;
reg-shift = <2>;
interrupts = <10>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
no-loopback-test;
status = "disabled";
};
@@ -270,8 +234,8 @@
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787000 0x40>;
reg-shift = <2>;
- interrupts = <10>;
- clocks = <&clk_uart>;
+ interrupts = <8>;
+ clocks = <&syscon ASPEED_CLK_APB>;
no-loopback-test;
status = "disabled";
};
@@ -318,7 +282,7 @@
reg = <0x1e78d000 0x20>;
reg-shift = <2>;
interrupts = <32>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
no-loopback-test;
status = "disabled";
};
@@ -328,7 +292,7 @@
reg = <0x1e78e000 0x20>;
reg-shift = <2>;
interrupts = <33>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
no-loopback-test;
status = "disabled";
};
@@ -338,7 +302,7 @@
reg = <0x1e78f000 0x20>;
reg-shift = <2>;
interrupts = <34>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
no-loopback-test;
status = "disabled";
};
@@ -369,7 +333,8 @@
reg = <0x40 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <0>;
interrupt-parent = <&i2c_ic>;
@@ -384,7 +349,8 @@
reg = <0x80 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <1>;
interrupt-parent = <&i2c_ic>;
@@ -399,7 +365,8 @@
reg = <0xc0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <2>;
interrupt-parent = <&i2c_ic>;
@@ -415,7 +382,8 @@
reg = <0x100 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <3>;
interrupt-parent = <&i2c_ic>;
@@ -431,7 +399,8 @@
reg = <0x140 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <4>;
interrupt-parent = <&i2c_ic>;
@@ -447,7 +416,8 @@
reg = <0x180 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <5>;
interrupt-parent = <&i2c_ic>;
@@ -463,7 +433,8 @@
reg = <0x1c0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <6>;
interrupt-parent = <&i2c_ic>;
@@ -479,7 +450,8 @@
reg = <0x300 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <7>;
interrupt-parent = <&i2c_ic>;
@@ -495,7 +467,8 @@
reg = <0x340 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <8>;
interrupt-parent = <&i2c_ic>;
@@ -511,7 +484,8 @@
reg = <0x380 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <9>;
interrupt-parent = <&i2c_ic>;
@@ -527,7 +501,8 @@
reg = <0x3c0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <10>;
interrupt-parent = <&i2c_ic>;
@@ -543,7 +518,8 @@
reg = <0x400 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <11>;
interrupt-parent = <&i2c_ic>;
@@ -559,7 +535,8 @@
reg = <0x440 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <12>;
interrupt-parent = <&i2c_ic>;
@@ -575,7 +552,8 @@
reg = <0x480 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <13>;
interrupt-parent = <&i2c_ic>;
--
2.14.1
^ permalink raw reply related
* [PATCH v2 03/19] ARM: dts: aspeed: Add LPC and child devices
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
From: Andrew Jeffery <andrew@aj.id.au>
Ensure the ordering is correct and add all of the children in the SoC
device trees for the ast2400 and ast2500.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 35 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 27 +++++++++++++++++----------
2 files changed, 52 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 100d092e6c07..a3bc5da7d42c 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -226,6 +226,41 @@
status = "disabled";
};
+ lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2400-lpc", "simple-mfd";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
+
+ lpc_bmc: lpc-bmc@0 {
+ compatible = "aspeed,ast2400-lpc-bmc";
+ reg = <0x0 0x80>;
+ };
+
+ lpc_host: lpc-host@80 {
+ compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
+ reg = <0x80 0x1e0>;
+ reg-io-width = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80 0x1e0>;
+
+ lpc_ctrl: lpc-ctrl@0 {
+ compatible = "aspeed,ast2400-lpc-ctrl";
+ reg = <0x0 0x80>;
+ status = "disabled";
+ };
+
+ lhc: lhc@20 {
+ compatible = "aspeed,ast2500-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
+ };
+ };
+ };
+
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 1f9d28313f82..7861631940fe 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -266,6 +266,16 @@
status = "disabled";
};
+ vuart: serial@1e787000 {
+ compatible = "aspeed,ast2500-vuart";
+ reg = <0x1e787000 0x40>;
+ reg-shift = <2>;
+ interrupts = <10>;
+ clocks = <&clk_uart>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
lpc: lpc@1e789000 {
compatible = "aspeed,ast2500-lpc", "simple-mfd";
reg = <0x1e789000 0x1000>;
@@ -289,6 +299,13 @@
reg-io-width = <4>;
+ lpc_ctrl: lpc-ctrl@0 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x0 0x80>;
+ status = "disabled";
+ };
+
+
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
@@ -296,16 +313,6 @@
};
};
- vuart: serial@1e787000 {
- compatible = "aspeed,ast2500-vuart";
- reg = <0x1e787000 0x40>;
- reg-shift = <2>;
- interrupts = <10>;
- clocks = <&clk_uart>;
- no-loopback-test;
- status = "disabled";
- };
-
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
--
2.14.1
^ permalink raw reply related
* [PATCH v2 02/19] dt-bindings: gpio: Add ASPEED constants
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
These are used to by the device tree to map pin numbers to constants
required by the GPIO bindings.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 1 +
arch/arm/boot/dts/aspeed-g5.dtsi | 1 +
include/dt-bindings/gpio/aspeed-gpio.h | 49 ++++++++++++++++++++++++++++++++++
3 files changed, 51 insertions(+)
create mode 100644 include/dt-bindings/gpio/aspeed-gpio.h
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 45d815a86d42..100d092e6c07 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Aspeed BMC";
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 5c4ecdba3a6b..1f9d28313f82 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Aspeed BMC";
diff --git a/include/dt-bindings/gpio/aspeed-gpio.h b/include/dt-bindings/gpio/aspeed-gpio.h
new file mode 100644
index 000000000000..56fc4889b2c4
--- /dev/null
+++ b/include/dt-bindings/gpio/aspeed-gpio.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header provides constants for binding aspeed,*-gpio.
+ *
+ * The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H
+#define _DT_BINDINGS_GPIO_ASPEED_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define ASPEED_GPIO_PORT_A 0
+#define ASPEED_GPIO_PORT_B 1
+#define ASPEED_GPIO_PORT_C 2
+#define ASPEED_GPIO_PORT_D 3
+#define ASPEED_GPIO_PORT_E 4
+#define ASPEED_GPIO_PORT_F 5
+#define ASPEED_GPIO_PORT_G 6
+#define ASPEED_GPIO_PORT_H 7
+#define ASPEED_GPIO_PORT_I 8
+#define ASPEED_GPIO_PORT_J 9
+#define ASPEED_GPIO_PORT_K 10
+#define ASPEED_GPIO_PORT_L 11
+#define ASPEED_GPIO_PORT_M 12
+#define ASPEED_GPIO_PORT_N 13
+#define ASPEED_GPIO_PORT_O 14
+#define ASPEED_GPIO_PORT_P 15
+#define ASPEED_GPIO_PORT_Q 16
+#define ASPEED_GPIO_PORT_R 17
+#define ASPEED_GPIO_PORT_S 18
+#define ASPEED_GPIO_PORT_T 19
+#define ASPEED_GPIO_PORT_U 20
+#define ASPEED_GPIO_PORT_V 21
+#define ASPEED_GPIO_PORT_W 22
+#define ASPEED_GPIO_PORT_X 23
+#define ASPEED_GPIO_PORT_Y 24
+#define ASPEED_GPIO_PORT_Z 25
+#define ASPEED_GPIO_PORT_AA 26
+#define ASPEED_GPIO_PORT_AB 27
+#define ASPEED_GPIO_PORT_AC 28
+
+#define ASPEED_GPIO(port, offset) \
+ ((ASPEED_GPIO_PORT_##port * 8) + offset)
+
+#endif
--
2.14.1
^ permalink raw reply related
* [PATCH v2 01/19] dt-bindings: clock: Add ASPEED constants
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20171215062443.23059-1-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
These will be merged as part of the clock driver. This commit is
included so the tree will build without the clock series being applied.
Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
---
v2:
- remove NUM_CLKS define. There's no need for it to be part of ABI
---
include/dt-bindings/clock/aspeed-clock.h | 52 ++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 include/dt-bindings/clock/aspeed-clock.h
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
new file mode 100644
index 000000000000..d3558d897a4d
--- /dev/null
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+#ifndef DT_BINDINGS_ASPEED_CLOCK_H
+#define DT_BINDINGS_ASPEED_CLOCK_H
+
+#define ASPEED_CLK_GATE_ECLK 0
+#define ASPEED_CLK_GATE_GCLK 1
+#define ASPEED_CLK_GATE_MCLK 2
+#define ASPEED_CLK_GATE_VCLK 3
+#define ASPEED_CLK_GATE_BCLK 4
+#define ASPEED_CLK_GATE_DCLK 5
+#define ASPEED_CLK_GATE_REFCLK 6
+#define ASPEED_CLK_GATE_USBPORT2CLK 7
+#define ASPEED_CLK_GATE_LCLK 8
+#define ASPEED_CLK_GATE_USBUHCICLK 9
+#define ASPEED_CLK_GATE_D1CLK 10
+#define ASPEED_CLK_GATE_YCLK 11
+#define ASPEED_CLK_GATE_USBPORT1CLK 12
+#define ASPEED_CLK_GATE_UART1CLK 13
+#define ASPEED_CLK_GATE_UART2CLK 14
+#define ASPEED_CLK_GATE_UART5CLK 15
+#define ASPEED_CLK_GATE_ESPICLK 16
+#define ASPEED_CLK_GATE_MAC1CLK 17
+#define ASPEED_CLK_GATE_MAC2CLK 18
+#define ASPEED_CLK_GATE_RSACLK 19
+#define ASPEED_CLK_GATE_UART3CLK 20
+#define ASPEED_CLK_GATE_UART4CLK 21
+#define ASPEED_CLK_GATE_SDCLKCLK 22
+#define ASPEED_CLK_GATE_LHCCLK 23
+#define ASPEED_CLK_HPLL 24
+#define ASPEED_CLK_AHB 25
+#define ASPEED_CLK_APB 26
+#define ASPEED_CLK_UART 27
+#define ASPEED_CLK_SDIO 28
+#define ASPEED_CLK_ECLK 29
+#define ASPEED_CLK_ECLK_MUX 30
+#define ASPEED_CLK_LHCLK 31
+#define ASPEED_CLK_MAC 32
+#define ASPEED_CLK_BCLK 33
+#define ASPEED_CLK_MPLL 34
+
+#define ASPEED_RESET_XDMA 0
+#define ASPEED_RESET_MCTP 1
+#define ASPEED_RESET_ADC 2
+#define ASPEED_RESET_JTAG_MASTER 3
+#define ASPEED_RESET_MIC 4
+#define ASPEED_RESET_PWM 5
+#define ASPEED_RESET_PCIVGA 6
+#define ASPEED_RESET_I2C 7
+#define ASPEED_RESET_AHB 8
+
+#endif
--
2.14.1
--
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^ permalink raw reply related
* [PATCH v2 00/19] ARM: dts: aspeed: updates and new machines
From: Joel Stanley @ 2017-12-15 6:24 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
This series of device tree patches for the ASPEED BMC machines
moves all systems to use the soon to be merged clk driver, and
updates machines to use all of the drivers we have upstream.
v2: Address review from Arnd
- Remove NUM_CLKS from dt header
- Send VUART patch as a fix, drop it from this series
- Add reasoning for breaking old kernel in the 'proper clock
references' patch
In addition it adds three new OpenBMC systems that have been developed
in the OpenBMC kernel tree over the past year: two Power9 OpenPower
systems, and a port by Google to a Quanta x86 server.
I have boot tested these on Romulus and Palmetto, as well as boot tested
all device trees in Qemu.
Please review the boards you are familiar with. I will merge these in to
the ASPEED ARM SoC tree for inclusion in 4.16.
Andrew Jeffery (1):
ARM: dts: aspeed: Add LPC and child devices
Joel Stanley (16):
dt-bindings: clock: Add ASPEED constants
dt-bindings: gpio: Add ASPEED constants
ARM: dts: aspeed: Add proper clock references
ARM: dts: aspeed: Add MAC clocks
ARM: dts: aspeed: Add watchdog clocks
ARM: dts: aspeed: Add flash controller clocks
ARM: dts: aspeed: Add clock phandle to GPIO
ARM: dts: aspeed: Add PWM and tachometer node
ARM: dts: aspeed: Add LPC Snoop device
ARM: dts: aspeed: Remove skeleton.dtsi
ARM: dts: aspeed: Update license headers
ARM: dts: Add OpenBMC flash layout
ARM: dts: aspeed: Sort ASPEED entries in makefile
ARM: dts: aspeed: Add Witherspoon BMC machine
ARM: dts: aspeed-romulus: Update Romulus system
ARM: dts: aspeed-plametto: Add flash layout
Rick Altherr (1):
ARM: dts: aspeed: Add Qanta Q71L BMC machine
Xo Wang (1):
ARM: dts: aspeed: Add Ingrasys Zaius BMC machine
arch/arm/boot/dts/Makefile | 8 +-
arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +-
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 3 +-
arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 155 ++++++-
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 547 +++++++++++++++++++++++
arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 427 ++++++++++++++++++
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 458 +++++++++++++++++++
arch/arm/boot/dts/aspeed-g4.dtsi | 164 ++++---
arch/arm/boot/dts/aspeed-g5.dtsi | 155 ++++---
arch/arm/boot/dts/openbmc-flash-layout.dtsi | 32 ++
include/dt-bindings/clock/aspeed-clock.h | 52 +++
include/dt-bindings/gpio/aspeed-gpio.h | 49 ++
12 files changed, 1906 insertions(+), 146 deletions(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
create mode 100644 arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
create mode 100644 arch/arm/boot/dts/openbmc-flash-layout.dtsi
create mode 100644 include/dt-bindings/clock/aspeed-clock.h
create mode 100644 include/dt-bindings/gpio/aspeed-gpio.h
--
2.14.1
--
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^ permalink raw reply
* Re: [PATCH 0/4] Sunxi: Add SMP support on A83T
From: Corentin Labbe @ 2017-12-15 6:10 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mylène Josserand, wens, linux, robh+dt, mark.rutland,
thomas.petazzoni, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20171212082425.iv37nrpotbb33vh6@flea.lan>
On Tue, Dec 12, 2017 at 09:24:25AM +0100, Maxime Ripard wrote:
> Hi,
>
> On Mon, Dec 11, 2017 at 08:35:34PM +0100, Corentin Labbe wrote:
> > On Mon, Dec 11, 2017 at 08:49:57AM +0100, Mylène Josserand wrote:
> > > This series adds SMP support for Allwinner Sun8i-a83t
> > > with MCPM (Multi-Cluster Power Management).
> > > Series information:
> > > - Based on last linux-next (next-20171211)
> > > - Had dependencies on Chen Yu's patch that add MCPM
> > > support:
> > > https://patchwork.kernel.org/patch/6402801/
> > >
> > > Patch 01: Convert the mcpm driver (initially for A80) to be able
> > > to use it for A83T. This SoC has a bit flip that needs to be handled.
> > > Patch 02: Add registers nodes (prcm, cpucfg and r_cpucfg) needed
> > > for MCPM.
> > > Patch 03: Add CCI-400 node for a83t.
> > > Patch 04: Fix the use of virtual timers that hangs the kernel in
> > > case of SMP support.
> >
> > As we discussed in private, Chen Yu's patch should be added in your series.
>
> Not really, she mentionned the dependency in the cover letter, and
> it's a good way to do things too. Sure, you can do it your way, but
> there's no preference.
>
If the goal of this series is to be applied, the dependency must be applied also.
And since the dependency is 2 years old (and part of a serie which does not apply now), I think cherry picking the patch and send it for review is better.
> > Furthermore, MCPM is not automaticaly selected via imply.
>
> Well, yes, is that an issue?
>
After reading the imply documentation, no.
> > With all patchs I hit a bug:
> > [ 0.898668] BUG: sleeping function called from invalid context at kernel/locking/mutex.c:238
>
> I guess this is with CONFIG_PROVE_LOCKING enabled?
>
No, the BUG() printed is enabled by default
> > [ 0.911162] in_atomic(): 1, irqs_disabled(): 0, pid: 1, name: swapper/0
> > [ 0.917776] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.15.0-rc2-next-20171211+ #73
>
> What are the changes you've made?
>
Just adding wens's patch and this series.
> > [ 0.925418] Hardware name: Allwinner sun8i Family
> > [ 0.930118] Backtrace:
> > [ 0.932596] [<c010cc50>] (dump_backtrace) from [<c010cf0c>] (show_stack+0x18/0x1c)
> > [ 0.940158] r7:c0b261e4 r6:60000013 r5:00000000 r4:c0b51958
> > [ 0.945820] [<c010cef4>] (show_stack) from [<c06baccc>] (dump_stack+0x8c/0xa0)
> > [ 0.953045] [<c06bac40>] (dump_stack) from [<c0149d40>] (___might_sleep+0x150/0x170)
> > [ 0.960779] r7:c0b261e4 r6:00000000 r5:000000ee r4:ee844000
> > [ 0.966437] [<c0149bf0>] (___might_sleep) from [<c0149dc8>] (__might_sleep+0x68/0xa0)
> > [ 0.974253] r4:c0861690
> > [ 0.976796] [<c0149d60>] (__might_sleep) from [<c06d2918>] (mutex_lock+0x24/0x68)
> > [ 0.984269] r6:c0892f6c r5:ffffffff r4:c0b1bb24
> > [ 0.988891] [<c06d28f4>] (mutex_lock) from [<c01ccb6c>] (perf_pmu_register+0x24/0x3e4)
> > [ 0.996795] r5:ffffffff r4:ee98b014
> > [ 1.000375] [<c01ccb48>] (perf_pmu_register) from [<c03efabc>] (cci_pmu_probe+0x340/0x484)
> > [ 1.008631] r10:c0892f6c r9:c0bfd5f0 r8:eea19010 r7:c0b261e4 r6:c0b26240 r5:eea19000
> > [ 1.016447] r4:ee98b010
> > [ 1.018989] [<c03ef77c>] (cci_pmu_probe) from [<c045e21c>] (platform_drv_probe+0x58/0xb8)
> > [ 1.027158] r10:00000000 r9:c0b2610c r8:00000000 r7:fffffdfb r6:c0b2610c r5:ffffffed
> > [ 1.034974] r4:eea19010
> > [ 1.037511] [<c045e1c4>] (platform_drv_probe) from [<c045c984>] (driver_probe_device+0x254/0x330)
> > [ 1.046371] r7:00000000 r6:c0bff498 r5:c0bff494 r4:eea19010
> > [ 1.052026] [<c045c730>] (driver_probe_device) from [<c045cbc4>] (__device_attach_driver+0xa0/0xd4)
> > [ 1.061062] r10:00000000 r9:c0bff470 r8:00000000 r7:00000001 r6:eea19010 r5:ee845ac0
> > [ 1.068879] r4:c0b2610c r3:00000000
> > [ 1.072454] [<c045cb24>] (__device_attach_driver) from [<c045ad68>] (bus_for_each_drv+0x68/0x9c)
> > [ 1.081228] r7:00000001 r6:c045cb24 r5:ee845ac0 r4:00000000
> > [ 1.086883] [<c045ad00>] (bus_for_each_drv) from [<c045c60c>] (__device_attach+0xb8/0x11c)
> > [ 1.095135] r6:c0b3e848 r5:eea19044 r4:eea19010
> > [ 1.099750] [<c045c554>] (__device_attach) from [<c045cc44>] (device_initial_probe+0x14/0x18)
> > [ 1.108263] r7:c0b0a4c8 r6:c0b3e848 r5:eea19010 r4:eea19018
> > [ 1.113919] [<c045cc30>] (device_initial_probe) from [<c045bb58>] (bus_probe_device+0x8c/0x94)
> > [ 1.122523] [<c045bacc>] (bus_probe_device) from [<c0459db8>] (device_add+0x40c/0x5a0)
> > [ 1.130429] r7:c0b0a4c8 r6:eea19010 r5:eea18a10 r4:eea19018
> > [ 1.136089] [<c04599ac>] (device_add) from [<c0582a58>] (of_device_add+0x3c/0x44)
> > [ 1.143564] r10:00000000 r9:00000000 r8:00000000 r7:eedf21a4 r6:eea18a10 r5:00000000
> > [ 1.151380] r4:eea19000
> > [ 1.153915] [<c0582a1c>] (of_device_add) from [<c0582f80>] (of_platform_device_create_pdata+0x7c/0xac)
> > [ 1.163210] [<c0582f04>] (of_platform_device_create_pdata) from [<c0583100>] (of_platform_bus_create+0xf4/0x1f0)
> > [ 1.173372] r9:00000000 r8:00000000 r7:00000001 r6:00000000 r5:eedf2154 r4:00000000
> > [ 1.181107] [<c058300c>] (of_platform_bus_create) from [<c0583374>] (of_platform_populate+0x74/0xd4)
> > [ 1.190229] r10:00000001 r9:eea18a10 r8:00000000 r7:00000000 r6:00000000 r5:eedf1d04
> > [ 1.198045] r4:eedf2154
> > [ 1.200580] [<c0583300>] (of_platform_populate) from [<c03ef2a8>] (cci_platform_probe+0x3c/0x54)
> > [ 1.209356] r10:00000000 r9:c0b26168 r8:00000000 r7:fffffdfb r6:c0b26168 r5:ffffffed
> > [ 1.217172] r4:eea18a00
> > [ 1.219708] [<c03ef26c>] (cci_platform_probe) from [<c045e21c>] (platform_drv_probe+0x58/0xb8)
> > [ 1.228306] r5:ffffffed r4:eea18a10
> > [ 1.231881] [<c045e1c4>] (platform_drv_probe) from [<c045c984>] (driver_probe_device+0x254/0x330)
> > [ 1.240742] r7:00000000 r6:c0bff498 r5:c0bff494 r4:eea18a10
> > [ 1.246397] [<c045c730>] (driver_probe_device) from [<c045cbc4>] (__device_attach_driver+0xa0/0xd4)
> > [ 1.255433] r10:00000000 r9:c0bff470 r8:00000000 r7:00000001 r6:eea18a10 r5:ee845ce8
> > [ 1.263250] r4:c0b26168 r3:00000000
> > [ 1.266825] [<c045cb24>] (__device_attach_driver) from [<c045ad68>] (bus_for_each_drv+0x68/0x9c)
> > [ 1.275598] r7:00000001 r6:c045cb24 r5:ee845ce8 r4:00000000
> > [ 1.281253] [<c045ad00>] (bus_for_each_drv) from [<c045c60c>] (__device_attach+0xb8/0x11c)
> > [ 1.289506] r6:c0b3e848 r5:eea18a44 r4:eea18a10
> > [ 1.294120] [<c045c554>] (__device_attach) from [<c045cc44>] (device_initial_probe+0x14/0x18)
> > [ 1.302633] r7:c0b0a4c8 r6:c0b3e848 r5:eea18a10 r4:eea18a18
> > [ 1.308288] [<c045cc30>] (device_initial_probe) from [<c045bb58>] (bus_probe_device+0x8c/0x94)
> > [ 1.316890] [<c045bacc>] (bus_probe_device) from [<c0459db8>] (device_add+0x40c/0x5a0)
> > [ 1.324796] r7:c0b0a4c8 r6:eea18a10 r5:ee993810 r4:eea18a18
> > [ 1.330450] [<c04599ac>] (device_add) from [<c0582a58>] (of_device_add+0x3c/0x44)
> > [ 1.337926] r10:00000000 r9:c07759d8 r8:00000000 r7:eedf1d54 r6:ee993810 r5:00000000
> > [ 1.345743] r4:eea18a00
> > [ 1.348277] [<c0582a1c>] (of_device_add) from [<c0582f80>] (of_platform_device_create_pdata+0x7c/0xac)
> > [ 1.357572] [<c0582f04>] (of_platform_device_create_pdata) from [<c0583100>] (of_platform_bus_create+0xf4/0x1f0)
> > [ 1.367734] r9:c07759d8 r8:00000000 r7:00000001 r6:00000000 r5:eedf1d04 r4:00000000
> > [ 1.375469] [<c058300c>] (of_platform_bus_create) from [<c058315c>] (of_platform_bus_create+0x150/0x1f0)
> > [ 1.384938] r10:ee993810 r9:c07759d8 r8:00000000 r7:00000001 r6:00000000 r5:eedefe1c
> > [ 1.392754] r4:eedf1d04
> > [ 1.395289] [<c058300c>] (of_platform_bus_create) from [<c0583374>] (of_platform_populate+0x74/0xd4)
> > [ 1.404411] r10:00000001 r9:00000000 r8:00000000 r7:c07759d8 r6:00000000 r5:eedee844
> > [ 1.412228] r4:eedefe1c
> > [ 1.414769] [<c0583300>] (of_platform_populate) from [<c0a25ee8>] (of_platform_default_populate_init+0x80/0x94)
> > [ 1.424844] r10:c0a37848 r9:00000000 r8:c0b59680 r7:c0a37834 r6:ffffe000 r5:c0775ce8
> > [ 1.432661] r4:00000000
> > [ 1.435200] [<c0a25e68>] (of_platform_default_populate_init) from [<c0102794>] (do_one_initcall+0x5c/0x194)
> > [ 1.444925] r5:c0a25e68 r4:c0b0a4c8
> > [ 1.448506] [<c0102738>] (do_one_initcall) from [<c0a00f88>] (kernel_init_freeable+0x1d4/0x268)
> > [ 1.457195] r9:00000004 r8:c0b59680 r7:c0a37834 r6:c0b59680 r5:c0a47308 r4:c090cfb8
> > [ 1.464932] [<c0a00db4>] (kernel_init_freeable) from [<c06cf3b0>] (kernel_init+0x10/0x118)
> > [ 1.473187] r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c06cf3a0
> > [ 1.481004] r4:00000000
> > [ 1.483540] [<c06cf3a0>] (kernel_init) from [<c01010e8>] (ret_from_fork+0x14/0x2c)
> > [ 1.491098] Exception stack(0xee845fb0 to 0xee845ff8)
> > [ 1.496146] 5fa0: 00000000 00000000 00000000 00000000
> > [ 1.504313] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> > [ 1.512480] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000
> > [ 1.519084] r5:c06cf3a0 r4:00000000
> > [ 1.522737] ARM CCI_400_r1 PMU driver probed
> >
> > And only CPU 0 show up.
>
> This looks more like a bug in the CCI code, and not in this serie
> itself. Can you share your whole boot logs?
>
This week end I will retry and send it.
Regards
Corentin Labbe
^ permalink raw reply
* Re: [PATCH 04/14] ARM: dts: dra76x: Create a common file with MMC/SD IOdelay data
From: Kishon Vijay Abraham I @ 2017-12-15 6:09 UTC (permalink / raw)
To: Tony Lindgren
Cc: bcousson-rdvid1DuHRBWk0Htik3J/w, Santosh Shilimkar, Rob Herring,
Mark Rutland, Russell King, linux-mmc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
nsekhar-l0cyMroinI0
In-Reply-To: <20171214151531.GI14441-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
Hi Tony,
On Thursday 14 December 2017 08:45 PM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org> [171214 13:44]:
>> +&dra7_pmx_core {
>> + mmc1_pins_default: mmc1_pins_default {
>> + pinctrl-single,pins = <
>> + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
>> + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
>> + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
>> + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
>> + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
>> + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>> + >;
>> + };
>> +
>> + mmc1_pins_sdr12: mmc1_pins_sdr12 {
>> + pinctrl-single,pins = <
>> + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
>> + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
>> + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
>> + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
>> + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
>> + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>> + >;
>> + };
>
> Can't you just do:
>
> pinctrl-0 = <&mmc1_pins_default>;
> pinctrl-1 = <&mmc1_pins_default>;
> pinctrl-2 = <&mmc1_pins_hs>;
> pinctrl-names = "default", "sdr12", "sdr25";
just wanted to make sure every mode has it's own pinctrl group so that it's
easy to review. Initially we were thinking something like
mmc1_pins_default_sdr12_sdr25.
But if you'd prefer we just use mmc1_pins_default for all modes that uses
default pinmux configuration, I can change it that way too.
Thanks
Kishon
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^ permalink raw reply
* RE: [PATCH v3 2/2] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver
From: Dhaval Rajeshbhai Shah @ 2017-12-15 6:00 UTC (permalink / raw)
To: Randy Dunlap, arnd-r2nGTMty4D4@public.gmane.org,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org,
pombredanne-od1rfyK75/E@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org, Hyun Kwon
In-Reply-To: <29198c0a-783e-8aa0-00e4-44b1fa1acef7-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 19325 bytes --]
Hi Randy,
Thanks a lot for the review.
> -----Original Message-----
> From: Randy Dunlap [mailto:rdunlap@infradead.org]
> Sent: Thursday, December 14, 2017 10:43 AM
> To: Dhaval Rajeshbhai Shah <DSHAH@xilinx.com>; arnd@arndb.de;
> gregkh@linuxfoundation.org; pombredanne@nexb.com; robh+dt@kernel.org;
> mark.rutland@arm.com
> Cc: devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> michal.simek@xilinx.com; Hyun Kwon <hyunk@xilinx.com>; Dhaval Rajeshbhai
> Shah <DSHAH@xilinx.com>
> Subject: Re: [PATCH v3 2/2] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver
>
> On 12/13/2017 09:55 PM, Dhaval Shah wrote:
> > Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP
> > design created. This driver provides the processing system and
> > programmable logic isolation. Set the frequency based on the clock
> > information get from the logicoreIP register set.
> >
> > It is put in drivers/misc as there is no subsystem for this logicoreIP.
> >
> > Signed-off-by: Dhaval Shah <dshah@xilinx.com>
> > ---
> > Changes since v3:
> > No Changes.
> > Changes since v2:
> > * Removed the "default n" from the Kconfig
> > * More help text added to explain more about the logicoreIP driver
> > * SPDX id is relocated at top of the file with // style comment
> > * Removed the export API and header file and make it a single driver
> > which provides logocoreIP init.
> > * Provide the information in commit message as well for the why driver
> > in drivers/misc.
> >
> > drivers/misc/Kconfig | 15 ++
> > drivers/misc/Makefile | 1 +
> > drivers/misc/xlnx_vcu.c | 629
> > ++++++++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 645 insertions(+)
> > create mode 100644 drivers/misc/xlnx_vcu.c
> >
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > f1a5c23..24ea516 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -496,6 +496,21 @@ config PCI_ENDPOINT_TEST
> > Enable this configuration option to enable the host side test driver
> > for PCI Endpoint.
> >
> > +config XILINX_VCU
> > + tristate "Xilinx VCU logicoreIP Init"
> > + help
>
> Please indent the help text (below) by 2 additional spaces, as documented in
> coding-style.rst.
I will update this.
>
> > + Provides the driver to enable and disable the isolation between the
> > + processing system and programmable logic part by using the
> logicoreIP
> > + register set. This driver also configure the frequency based on
> > +the
>
> configures
>
I will update this.
> > + clock information get from the logicoreIP register set.
>
> drop ^get^
>
I will update this.
> > +
> > + If you say yes here you get support for the logcoreIP.
>
> logicoreIP.
>
> > +
> > + If unsure, say N.
> > +
> > + To compile this driver as a module, choose M here: the
> > + module will be called xlnx_vcu.
> > +
> > source "drivers/misc/c2port/Kconfig"
> > source "drivers/misc/eeprom/Kconfig"
> > source "drivers/misc/cb710/Kconfig"
> > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> > 5ca5f64..a6bd0b1 100644
> > --- a/drivers/misc/Makefile
> > +++ b/drivers/misc/Makefile
> > @@ -55,6 +55,7 @@ obj-$(CONFIG_CXL_BASE) += cxl/
> > obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
> > obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
> > obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
> > +obj-$(CONFIG_XILINX_VCU) += xlnx_vcu.o
> >
> > lkdtm-$(CONFIG_LKDTM) += lkdtm_core.o
> > lkdtm-$(CONFIG_LKDTM) += lkdtm_bugs.o
> > diff --git a/drivers/misc/xlnx_vcu.c b/drivers/misc/xlnx_vcu.c new
> > file mode 100644 index 0000000..41819f0
> > --- /dev/null
> > +++ b/drivers/misc/xlnx_vcu.c
> > @@ -0,0 +1,629 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Xilinx VCU Init
> > + *
> > + * Copyright (C) 2016 - 2017 Xilinx, Inc.
> > + *
> > + * Contacts Dhaval Shah <dshah@xilinx.com>
> > + */
> > +#include <linux/clk.h>
> > +#include <linux/device.h>
> > +#include <linux/errno.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/platform_device.h>
> > +> +/* Address map for different registers implemented in the VCU
> > +> +LogiCORE IP. */
>
> [snip]
>
>
> > +/**
> > + * xvcu_read - Read from the VCU register space
> > + * @iomem: vcu reg space base address
> > + * @offset: vcu reg offset from base
> > + *
> > + * Return: Returns 32bit value from VCU register specified
> > + *
> > + */
> > +static u32 xvcu_read(void __iomem *iomem, u32 offset)
>
> You could inline the read() and write() functions...
>
I will check and will update if required.
> > +{
> > + return ioread32(iomem + offset);
> > +}
> > +
> > +/**
> > + * xvcu_write - Write to the VCU register space
> > + * @iomem: vcu reg space base address
> > + * @offset: vcu reg offset from base
> > + * @value: Value to write
> > + */
> > +static void xvcu_write(void __iomem *iomem, u32 offset, u32 value) {
> > + iowrite32(value, iomem + offset);
> > +}
> > +
> > +/**
> > + * xvcu_write_field_reg - Write to the vcu reg field
> > + * @iomem: vcu reg space base address
> > + * @offset: vcu reg offset from base
> > + * @field: vcu reg field to write to
> > + * @mask: vcu reg mask
> > + * @shift: vcu reg number of bits to shift the bitfield
> > + */
> > +static void xvcu_write_field_reg(void __iomem *iomem, int offset,
> > + u32 field, u32 mask, int shift)
> > +{
> > + u32 val = xvcu_read(iomem, offset);
> > +
> > + val &= ~(mask << shift);
> > + val |= (field & mask) << shift;
> > +
> > + xvcu_write(iomem, offset, val);
> > +}
> > +
> > +/**
> > + * xvcu_set_vcu_pll_info - Set the VCU PLL info
> > + * @xvcu: Pointer to the xvcu_device structure
> > + *
> > + * Programming the VCU PLL based on the user configuration
> > + * (ref clock freq, core clock freq, mcu clock freq).
> > + * Core clock frequency has higher priority than mcu clock frequency
> > + * Errors in following cases
> > + * - When mcu or clock clock get from logicoreIP is 0
> > + * - When VCU PLL DIV related bits value other than 1
> > + * - When proper data not found for given data
> > + * - When sis570_1 clocksource related operation failed
> > + *
> > + * Return: Returns status, either success or error+reason
> > + */
> > +static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu) {
> > + u32 refclk, coreclk, mcuclk, inte, deci;
> > + u32 divisor_mcu, divisor_core, fvco;
> > + u32 clkoutdiv, vcu_pll_ctrl, pll_clk;
> > + u32 cfg_val, mod, ctrl;
> > + int ret;
> > + unsigned int i;
> > + const struct xvcu_pll_cfg *found = NULL;
> > +
> > + inte = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK);
> > + deci = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK_DEC);
> > + coreclk = xvcu_read(xvcu->logicore_reg_ba, VCU_CORE_CLK) * MHZ;
> > + mcuclk = xvcu_read(xvcu->logicore_reg_ba, VCU_MCU_CLK) * MHZ;
> > + if (!mcuclk || !coreclk) {
> > + dev_err(xvcu->dev, "Invalid mcu and core clock data\n");
> > + return -EINVAL;
> > + }
> > +
> > + refclk = (inte * MHZ) + (deci * (MHZ / FRAC));
> > + dev_dbg(xvcu->dev, "Ref clock from logicoreIP is %uHz\n", refclk);
> > + dev_dbg(xvcu->dev, "Core clock from logicoreIP is %uHz\n", coreclk);
> > + dev_dbg(xvcu->dev, "Mcu clock from logicoreIP is %uHz\n", mcuclk);
> > +
> > + clk_disable_unprepare(xvcu->pll_ref);
> > + ret = clk_set_rate(xvcu->pll_ref, refclk);
> > + if (ret)
> > + dev_warn(xvcu->dev, "failed to set logicoreIP refclk rate\n");
> > +
> > + ret = clk_prepare_enable(xvcu->pll_ref);
> > + if (ret) {
> > + dev_err(xvcu->dev, "failed to enable pll_ref clock source\n");
> > + return ret;
> > + }
> > +
> > + refclk = clk_get_rate(xvcu->pll_ref);
> > +
> > + /* The divide-by-2 should be always enabled (==1)
>
> multi-line comment style:
> /*
> * The divide-by-2 should always be enabled (==1)
>
I will update this.
> > + * to meet the timing in the design.
> > + * Otherwise, it's an error
> > + */
> > + vcu_pll_ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_PLL_CTRL);
> > + clkoutdiv = vcu_pll_ctrl >> VCU_PLL_CTRL_CLKOUTDIV_SHIFT;
> > + clkoutdiv = clkoutdiv && VCU_PLL_CTRL_CLKOUTDIV_MASK;
> > + if (clkoutdiv != 1) {
> > + dev_err(xvcu->dev, "clkoutdiv value is invalid\n");
> > + return -EINVAL;
> > + }
> > +
> > + for (i = ARRAY_SIZE(xvcu_pll_cfg) - 1; i > 0; i--) {
> > + const struct xvcu_pll_cfg *cfg = &xvcu_pll_cfg[i];
> > +
> > + fvco = cfg->fbdiv * refclk;
> > + if (fvco >= FVCO_MIN && fvco <= FVCO_MAX) {
> > + pll_clk = fvco / VCU_PLL_DIV2;
> > + if (fvco % VCU_PLL_DIV2 != 0)
> > + pll_clk++;
> > + mod = pll_clk % coreclk;
> > + if (mod < LIMIT) {
> > + divisor_core = pll_clk / coreclk;
> > + } else if (coreclk - mod < LIMIT) {
> > + divisor_core = pll_clk / coreclk;
> > + divisor_core++;
> > + } else {
> > + continue;
> > + }
> > + if (divisor_core >= DIVISOR_MIN &&
> > + divisor_core <= DIVISOR_MAX) {
> > + found = cfg;
> > + divisor_mcu = pll_clk / mcuclk;
> > + mod = pll_clk % mcuclk;
> > + if (mcuclk - mod < LIMIT)
> > + divisor_mcu++;
> > + break;
> > + }
> > + }
> > + }
> > +
> > + if (!found) {
> > + dev_err(xvcu->dev, "Invalid clock combination.\n");
> > + return -EINVAL;
> > + }
> > +
> > + xvcu->coreclk = pll_clk / divisor_core;
> > + mcuclk = pll_clk / divisor_mcu;
> > + dev_dbg(xvcu->dev, "Actual Ref clock freq is %uHz\n", refclk);
> > + dev_dbg(xvcu->dev, "Actual Core clock freq is %uHz\n", xvcu->coreclk);
> > + dev_dbg(xvcu->dev, "Actual Mcu clock freq is %uHz\n", mcuclk);
> > +
> > + vcu_pll_ctrl &= ~(VCU_PLL_CTRL_FBDIV_MASK <<
> VCU_PLL_CTRL_FBDIV_SHIFT);
> > + vcu_pll_ctrl |= (found->fbdiv & VCU_PLL_CTRL_FBDIV_MASK) <<
> > + VCU_PLL_CTRL_FBDIV_SHIFT;
> > + vcu_pll_ctrl &= ~(VCU_PLL_CTRL_POR_IN_MASK <<
> > + VCU_PLL_CTRL_POR_IN_SHIFT);
> > + vcu_pll_ctrl |= (VCU_PLL_CTRL_DEFAULT &
> VCU_PLL_CTRL_POR_IN_MASK) <<
> > + VCU_PLL_CTRL_POR_IN_SHIFT;
> > + vcu_pll_ctrl &= ~(VCU_PLL_CTRL_PWR_POR_MASK <<
> > + VCU_PLL_CTRL_PWR_POR_SHIFT);
> > + vcu_pll_ctrl |= (VCU_PLL_CTRL_DEFAULT &
> VCU_PLL_CTRL_PWR_POR_MASK) <<
> > + VCU_PLL_CTRL_PWR_POR_SHIFT;
> > + xvcu_write(xvcu->vcu_slcr_ba, VCU_PLL_CTRL, vcu_pll_ctrl);
> > +
> > + /* Set divisor for the core and mcu clock */
> > + ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_ENC_CORE_CTRL);
> > + ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT);
> > + ctrl |= (divisor_core & VCU_PLL_DIVISOR_MASK) <<
> > + VCU_PLL_DIVISOR_SHIFT;
> > + ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT);
> > + ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) <<
> VCU_SRCSEL_SHIFT;
> > + xvcu_write(xvcu->vcu_slcr_ba, VCU_ENC_CORE_CTRL, ctrl);
> > +
> > + ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_DEC_CORE_CTRL);
> > + ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT);
> > + ctrl |= (divisor_core & VCU_PLL_DIVISOR_MASK) <<
> > + VCU_PLL_DIVISOR_SHIFT;
> > + ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT);
> > + ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) <<
> VCU_SRCSEL_SHIFT;
> > + xvcu_write(xvcu->vcu_slcr_ba, VCU_DEC_CORE_CTRL, ctrl);
> > +
> > + ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_ENC_MCU_CTRL);
> > + ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT);
> > + ctrl |= (divisor_mcu & VCU_PLL_DIVISOR_MASK) <<
> VCU_PLL_DIVISOR_SHIFT;
> > + ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT);
> > + ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) <<
> VCU_SRCSEL_SHIFT;
> > + xvcu_write(xvcu->vcu_slcr_ba, VCU_ENC_MCU_CTRL, ctrl);
> > +
> > + ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_DEC_MCU_CTRL);
> > + ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT);
> > + ctrl |= (divisor_mcu & VCU_PLL_DIVISOR_MASK) <<
> VCU_PLL_DIVISOR_SHIFT;
> > + ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT);
> > + ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) <<
> VCU_SRCSEL_SHIFT;
> > + xvcu_write(xvcu->vcu_slcr_ba, VCU_DEC_MCU_CTRL, ctrl);
> > +
> > + /* Set RES, CP, LFHF, LOCK_CNT and LOCK_DLY cfg values */
> > + cfg_val = (found->res << VCU_PLL_CFG_RES_SHIFT) |
> > + (found->cp << VCU_PLL_CFG_CP_SHIFT) |
> > + (found->lfhf << VCU_PLL_CFG_LFHF_SHIFT) |
> > + (found->lock_cnt << VCU_PLL_CFG_LOCK_CNT_SHIFT) |
> > + (found->lock_dly << VCU_PLL_CFG_LOCK_DLY_SHIFT);
> > + xvcu_write(xvcu->vcu_slcr_ba, VCU_PLL_CFG, cfg_val);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * xvcu_set_pll - PLL init sequence
> > + * @xvcu: Pointer to the xvcu_device structure
> > + *
> > + * Call the api to set the PLL info and once that is done then
> > + * init the PLL sequence to make the PLL stable.
> > + *
> > + * Return: Returns status, either success or error+reason
> > + */
> > +static int xvcu_set_pll(struct xvcu_device *xvcu) {
> > + u32 lock_status;
> > + unsigned long timeout;
> > + int ret;
> > +
> > + ret = xvcu_set_vcu_pll_info(xvcu);
> > + if (ret) {
> > + dev_err(xvcu->dev, "failed to set pll info\n");
> > + return ret;
> > + }
> > +
> > + xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL,
> > + 1, VCU_PLL_CTRL_BYPASS_MASK,
> > + VCU_PLL_CTRL_BYPASS_SHIFT);
> > + xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL,
> > + 1, VCU_PLL_CTRL_RESET_MASK,
> > + VCU_PLL_CTRL_RESET_SHIFT);
> > + xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL,
> > + 0, VCU_PLL_CTRL_RESET_MASK,
> > + VCU_PLL_CTRL_RESET_SHIFT);
> > + /* Defined the timeout for the max time to wait the
>
> comment style.
>
I will update this.
> > + * PLL_STATUS to be locked.
> > + */
> > + timeout = jiffies + msecs_to_jiffies(2000);
> > + do {
> > + lock_status = xvcu_read(xvcu->vcu_slcr_ba, VCU_PLL_STATUS);
> > + if (lock_status & VCU_PLL_STATUS_LOCK_STATUS_MASK) {
> > + xvcu_write_field_reg(xvcu->vcu_slcr_ba,
> VCU_PLL_CTRL,
> > + 0, VCU_PLL_CTRL_BYPASS_MASK,
> > + VCU_PLL_CTRL_BYPASS_SHIFT);
> > + return 0;
> > + }
> > + } while (!time_after(jiffies, timeout));
> > +
> > + /* PLL is not locked even after the timeout of the 2sec */
> > + dev_err(xvcu->dev, "PLL is not locked\n");
> > + return -ETIMEDOUT;
> > +}
> > +
> > +/**
> > + * xvcu_probe - Probe existence of the logicoreIP
> > + * and initialize PLL
> > + *
> > + * @pdev: Pointer to the platform_device structure
> > + *
> > + * Return: Returns 0 on success
> > + * Negative error code otherwise
> > + */
> > +static int xvcu_probe(struct platform_device *pdev) {
> > + struct resource *res;
> > + struct xvcu_device *xvcu;
> > + int ret;
> > +
> > + xvcu = devm_kzalloc(&pdev->dev, sizeof(*xvcu), GFP_KERNEL);
> > + if (!xvcu)
> > + return -ENOMEM;
> > +
> > + xvcu->dev = &pdev->dev;
> > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> "vcu_slcr");
> > + if (!res) {
> > + dev_err(&pdev->dev, "get vcu_slcr memory resource
> failed.\n");
> > + return -ENODEV;
> > + }
> > +
> > + xvcu->vcu_slcr_ba = devm_ioremap_nocache(&pdev->dev,
> > + res->start, resource_size(res));
> > + if (!xvcu->vcu_slcr_ba) {
> > + dev_err(&pdev->dev, "vcu_slcr register mapping failed.\n");
> > + return -ENOMEM;
> > + }
> > +
> > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> "logicore");
> > + if (!res) {
> > + dev_err(&pdev->dev, "get logicore memory resource
> failed.\n");
> > + return -ENODEV;
> > + }
> > +
> > + xvcu->logicore_reg_ba = devm_ioremap_nocache(&pdev->dev,
> > + res->start, resource_size(res));
> > + if (!xvcu->logicore_reg_ba) {
> > + dev_err(&pdev->dev, "logicore register mapping failed.\n");
> > + return -ENOMEM;
> > + }
> > +
> > + xvcu->aclk = devm_clk_get(&pdev->dev, "aclk");
> > + if (IS_ERR(xvcu->aclk)) {
> > + dev_err(&pdev->dev, "Could not get aclk clock\n");
> > + return PTR_ERR(xvcu->aclk);
> > + }
> > +
> > + xvcu->pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
> > + if (IS_ERR(xvcu->pll_ref)) {
> > + dev_err(&pdev->dev, "Could not get pll_ref clock\n");
> > + return PTR_ERR(xvcu->pll_ref);
> > + }
> > +
> > + ret = clk_prepare_enable(xvcu->aclk);
> > + if (ret) {
> > + dev_err(&pdev->dev, "aclk clock enable failed\n");
> > + return ret;
> > + }
> > +
> > + ret = clk_prepare_enable(xvcu->pll_ref);
> > + if (ret) {
> > + dev_err(&pdev->dev, "pll_ref clock enable failed\n");
> > + goto error_aclk;
> > + }
> > +
> > + /* Do the Gasket isolation and put the VCU out of reset
>
> comment style.
>
I will update this.
> > + * Bit 0 : Gasket isolation
> > + * Bit 1 : put VCU out of reset
> > + */
> > + xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT,
> > +VCU_GASKET_VALUE);
> > +
> > + /* Do the PLL Settings based on the ref clk,core and mcu clk freq */
> > + ret = xvcu_set_pll(xvcu);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Failed to set the pll\n");
> > + goto error_pll_ref;
> > + }
> > +
> > + dev_set_drvdata(&pdev->dev, xvcu);
> > +
> > + dev_info(&pdev->dev, "%s: Probed successfully\n", __func__);
> > +
> > + return 0;
> > +
> > +error_pll_ref:
> > + clk_disable_unprepare(xvcu->pll_ref);
> > +error_aclk:
> > + clk_disable_unprepare(xvcu->aclk);
> > + return ret;
> > +}
> > +
> > +/**
> > + * xvcu_remove - Insert gasket isolation
> > + * and disable the clock
> > + * @pdev: Pointer to the platform_device structure
> > + *
> > + * Return: Returns 0 on success
> > + * Negative error code otherwise
> > + */
> > +static int xvcu_remove(struct platform_device *pdev) {
> > + struct xvcu_device *xvcu;
> > +
> > + xvcu = platform_get_drvdata(pdev);
> > + if (!xvcu)
> > + return -ENODEV;
> > +
> > + /* Add the the Gasket isolation and put the VCU in reset.
>
> style.
>
I will update this.
> > + */
> > + xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0);
> > +
> > + clk_disable_unprepare(xvcu->pll_ref);
> > + clk_disable_unprepare(xvcu->aclk);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id xvcu_of_id_table[] = {
> > + { .compatible = "xlnx,vcu" },
> > + { .compatible = "xlnx,vcu-logicoreip-1.0" },
> > + { }
> > +};
> > +MODULE_DEVICE_TABLE(of, xvcu_of_id_table);
> > +
> > +static struct platform_driver xvcu_driver = {
> > + .driver = {
> > + .name = "xilinx-vcu",
> > + .of_match_table = xvcu_of_id_table,
> > + },
> > + .probe = xvcu_probe,
> > + .remove = xvcu_remove,
> > +};
> > +
> > +module_platform_driver(xvcu_driver);
> > +
> > +MODULE_AUTHOR("Dhaval Shah <dshah@xilinx.com>");
> > +MODULE_DESCRIPTION("Xilinx VCU init Driver"); MODULE_LICENSE("GPL
> > +v2");
> >
>
> The code has several divide operations. Does it build OK for 32-bit target?
>
Yes. I have verified on both 32 bit and 64 bit target.
> --
> ~Randy
Thanks & Regards,
Dhaval
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