* [PATCH v4 02/16] media: doc: add document for rkisp1 meta buffer format
From: Jacob Chen @ 2017-12-18 12:03 UTC (permalink / raw)
To: linux-rockchip
Cc: linux-kernel, linux-arm-kernel, mchehab, linux-media,
sakari.ailus, hans.verkuil, tfiga, zhengsq, laurent.pinchart, zyc,
eddie.cai.linux, jeffy.chen, allon.huang, devicetree, heiko,
robh+dt, Joao.Pinto, Luis.Oliveira, Jose.Abreu, Jacob Chen,
Jacob Chen
In-Reply-To: <20171218120320.3850-1-jacob-chen@iotwrt.com>
From: Jacob Chen <jacob2.chen@rock-chips.com>
This commit add docuemnt for rkisp1 meta buffer format
Signed-off-by: Jacob Chen <jacob-chen@rock-chips.com>
---
Documentation/media/uapi/v4l/meta-formats.rst | 2 ++
.../media/uapi/v4l/pixfmt-meta-rkisp1-params.rst | 17 +++++++++++++++++
.../media/uapi/v4l/pixfmt-meta-rkisp1-stat.rst | 18 ++++++++++++++++++
3 files changed, 37 insertions(+)
create mode 100644 Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-params.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-stat.rst
diff --git a/Documentation/media/uapi/v4l/meta-formats.rst b/Documentation/media/uapi/v4l/meta-formats.rst
index 01e24e3df571..1b8281423aa2 100644
--- a/Documentation/media/uapi/v4l/meta-formats.rst
+++ b/Documentation/media/uapi/v4l/meta-formats.rst
@@ -14,3 +14,5 @@ These formats are used for the :ref:`metadata` interface only.
pixfmt-meta-vsp1-hgo
pixfmt-meta-vsp1-hgt
+ pixfmt-meta-rkisp1-params
+ pixfmt-meta-rkisp1-stat
diff --git a/Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-params.rst b/Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-params.rst
new file mode 100644
index 000000000000..ed344d463b52
--- /dev/null
+++ b/Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-params.rst
@@ -0,0 +1,17 @@
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _v4l2-meta-fmt-rkisp1-params:
+
+*******************************
+V4L2_META_FMT_RK_ISP1_PARAMS
+*******************************
+
+Rockchip ISP1 Parameters Data
+
+Description
+===========
+
+This format describes input parameters for the Rockchip ISP1.
+
+The data use c-struct :c:type:`rkisp1_isp_params_cfg`, which is defined in
+the ``linux/rkisp1-config.h`` header file, See it for details.
diff --git a/Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-stat.rst b/Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-stat.rst
new file mode 100644
index 000000000000..5ecc4031295f
--- /dev/null
+++ b/Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-stat.rst
@@ -0,0 +1,18 @@
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _v4l2-meta-fmt-rkisp1-stat:
+
+*******************************
+V4L2_META_FMT_RK_ISP1_STAT_3A
+*******************************
+
+Rockchip ISP1 Statistics Data
+
+Description
+===========
+
+This format describes image color statistics information generated by the Rockchip
+ISP1.
+
+The data use c-struct :c:type:`rkisp1_stat_buffer`, which is defined in
+the ``linux/cifisp_stat.h`` header file, See it for details.
--
2.15.1
^ permalink raw reply related
* [PATCH v4 01/16] media: videodev2.h, v4l2-ioctl: add rkisp1 meta buffer format
From: Jacob Chen @ 2017-12-18 12:03 UTC (permalink / raw)
To: linux-rockchip
Cc: linux-kernel, linux-arm-kernel, mchehab, linux-media,
sakari.ailus, hans.verkuil, tfiga, zhengsq, laurent.pinchart, zyc,
eddie.cai.linux, jeffy.chen, allon.huang, devicetree, heiko,
robh+dt, Joao.Pinto, Luis.Oliveira, Jose.Abreu, Jacob Chen
In-Reply-To: <20171218120320.3850-1-jacob-chen@iotwrt.com>
From: Shunqian Zheng <zhengsq@rock-chips.com>
Add the Rockchip ISP1 specific processing parameter format
V4L2_META_FMT_RK_ISP1_PARAMS and metadata format
V4L2_META_FMT_RK_ISP1_STAT_3A for 3A.
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
---
drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++
include/uapi/linux/videodev2.h | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
index d6587b3ec33e..0604ae9ea444 100644
--- a/drivers/media/v4l2-core/v4l2-ioctl.c
+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
@@ -1252,6 +1252,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
case V4L2_TCH_FMT_TU08: descr = "8-bit unsigned touch data"; break;
case V4L2_META_FMT_VSP1_HGO: descr = "R-Car VSP1 1-D Histogram"; break;
case V4L2_META_FMT_VSP1_HGT: descr = "R-Car VSP1 2-D Histogram"; break;
+ case V4L2_META_FMT_RK_ISP1_PARAMS: descr = "Rockchip ISP1 3A params"; break;
+ case V4L2_META_FMT_RK_ISP1_STAT_3A: descr = "Rockchip ISP1 3A statistics"; break;
default:
/* Compressed formats */
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index 7c871291c1fa..961545e64c12 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -691,6 +691,10 @@ struct v4l2_pix_format {
#define V4L2_META_FMT_VSP1_HGO v4l2_fourcc('V', 'S', 'P', 'H') /* R-Car VSP1 1-D Histogram */
#define V4L2_META_FMT_VSP1_HGT v4l2_fourcc('V', 'S', 'P', 'T') /* R-Car VSP1 2-D Histogram */
+/* Vendor specific - used for IPU3 camera sub-system */
+#define V4L2_META_FMT_RK_ISP1_PARAMS v4l2_fourcc('R', 'K', '1', 'P') /* Rockchip ISP1 params */
+#define V4L2_META_FMT_RK_ISP1_STAT_3A v4l2_fourcc('R', 'K', '1', 'S') /* Rockchip ISP1 3A statistics */
+
/* priv field value to indicates that subsequent fields are valid. */
#define V4L2_PIX_FMT_PRIV_MAGIC 0xfeedcafe
--
2.15.1
^ permalink raw reply related
* [PATCH v4 00/16] Rockchip ISP1 Driver
From: Jacob Chen @ 2017-12-18 12:03 UTC (permalink / raw)
To: linux-rockchip
Cc: linux-kernel, linux-arm-kernel, mchehab, linux-media,
sakari.ailus, hans.verkuil, tfiga, zhengsq, laurent.pinchart, zyc,
eddie.cai.linux, jeffy.chen, allon.huang, devicetree, heiko,
robh+dt, Joao.Pinto, Luis.Oliveira, Jose.Abreu, Jacob Chen
From: Jacob Chen <jacob2.chen@rock-chips.com>
changes in V4:
- fix some bugs during development
- move quantization settings to rkisp1 subdev
- correct some spelling problems
- describe ports in dt-binding documents
changes in V3:
- add some comments
- fix wrong use of v4l2_async_subdev_notifier_register
- optimize two paths capture at a time
- remove compose
- re-struct headers
- add a tmp wiki page: http://opensource.rock-chips.com/wiki_Rockchip-isp1
changes in V2:
mipi-phy:
- use async probing
- make it be a child device of the GRF
isp:
- add dummy buffer
- change the way to get bus configuration, which make it possible to
add parallel sensor support in the future(without mipi-phy driver).
This patch series add a ISP(Camera) v4l2 driver for rockchip rk3288/rk3399 SoC.
Wiki Pages:
http://opensource.rock-chips.com/wiki_Rockchip-isp1
Jacob Chen (12):
media: doc: add document for rkisp1 meta buffer format
media: rkisp1: add Rockchip MIPI Synopsys DPHY driver
media: rkisp1: add Rockchip ISP1 subdev driver
media: rkisp1: add ISP1 statistics driver
media: rkisp1: add ISP1 params driver
media: rkisp1: add capture device driver
media: rkisp1: add rockchip isp1 core driver
dt-bindings: Document the Rockchip ISP1 bindings
dt-bindings: Document the Rockchip MIPI RX D-PHY bindings
ARM: dts: rockchip: add isp node for rk3288
ARM: dts: rockchip: add rx0 mipi-phy for rk3288
MAINTAINERS: add entry for Rockchip ISP1 driver
Jeffy Chen (1):
media: rkisp1: Add user space ABI definitions
Shunqian Zheng (3):
media: videodev2.h, v4l2-ioctl: add rkisp1 meta buffer format
arm64: dts: rockchip: add isp0 node for rk3399
arm64: dts: rockchip: add rx0 mipi-phy for rk3399
.../devicetree/bindings/media/rockchip-isp1.txt | 69 +
.../bindings/media/rockchip-mipi-dphy.txt | 88 +
Documentation/media/uapi/v4l/meta-formats.rst | 2 +
.../media/uapi/v4l/pixfmt-meta-rkisp1-params.rst | 17 +
.../media/uapi/v4l/pixfmt-meta-rkisp1-stat.rst | 18 +
MAINTAINERS | 10 +
arch/arm/boot/dts/rk3288.dtsi | 24 +
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 25 +
drivers/media/platform/Kconfig | 10 +
drivers/media/platform/Makefile | 1 +
drivers/media/platform/rockchip/isp1/Makefile | 8 +
drivers/media/platform/rockchip/isp1/capture.c | 1704 ++++++++++++++++++++
drivers/media/platform/rockchip/isp1/capture.h | 194 +++
drivers/media/platform/rockchip/isp1/common.h | 137 ++
drivers/media/platform/rockchip/isp1/dev.c | 653 ++++++++
drivers/media/platform/rockchip/isp1/dev.h | 120 ++
drivers/media/platform/rockchip/isp1/isp_params.c | 1537 ++++++++++++++++++
drivers/media/platform/rockchip/isp1/isp_params.h | 76 +
drivers/media/platform/rockchip/isp1/isp_stats.c | 522 ++++++
drivers/media/platform/rockchip/isp1/isp_stats.h | 85 +
.../media/platform/rockchip/isp1/mipi_dphy_sy.c | 787 +++++++++
drivers/media/platform/rockchip/isp1/regs.c | 264 +++
drivers/media/platform/rockchip/isp1/regs.h | 1577 ++++++++++++++++++
drivers/media/platform/rockchip/isp1/rkisp1.c | 1211 ++++++++++++++
drivers/media/platform/rockchip/isp1/rkisp1.h | 132 ++
drivers/media/v4l2-core/v4l2-ioctl.c | 2 +
include/uapi/linux/rkisp1-config.h | 757 +++++++++
include/uapi/linux/videodev2.h | 4 +
28 files changed, 10034 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/rockchip-isp1.txt
create mode 100644 Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt
create mode 100644 Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-params.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-stat.rst
create mode 100644 drivers/media/platform/rockchip/isp1/Makefile
create mode 100644 drivers/media/platform/rockchip/isp1/capture.c
create mode 100644 drivers/media/platform/rockchip/isp1/capture.h
create mode 100644 drivers/media/platform/rockchip/isp1/common.h
create mode 100644 drivers/media/platform/rockchip/isp1/dev.c
create mode 100644 drivers/media/platform/rockchip/isp1/dev.h
create mode 100644 drivers/media/platform/rockchip/isp1/isp_params.c
create mode 100644 drivers/media/platform/rockchip/isp1/isp_params.h
create mode 100644 drivers/media/platform/rockchip/isp1/isp_stats.c
create mode 100644 drivers/media/platform/rockchip/isp1/isp_stats.h
create mode 100644 drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
create mode 100644 drivers/media/platform/rockchip/isp1/regs.c
create mode 100644 drivers/media/platform/rockchip/isp1/regs.h
create mode 100644 drivers/media/platform/rockchip/isp1/rkisp1.c
create mode 100644 drivers/media/platform/rockchip/isp1/rkisp1.h
create mode 100644 include/uapi/linux/rkisp1-config.h
--
2.15.1
^ permalink raw reply
* Re: [PATCH v3 07/12] dt-bindings: Document the Rockchip MIPI RX D-PHY bindings
From: Jacob Chen @ 2017-12-18 12:02 UTC (permalink / raw)
To: Laurent Pinchart
Cc: open list:ARM/Rockchip SoC..., linux-kernel, linux-arm-kernel,
Mauro Carvalho Chehab, Linux Media Mailing List, Sakari Ailus,
Hans Verkuil, Tomasz Figa, Shunqian Zheng,
钟以崇, Eddie Cai, Jeffy Chen, Allon Huang,
devicetree, Heiko Stuebner, robh+dt, Joao Pinto, Luis Oliveira,
Jose Abreu
In-Reply-To: <2576683.vP2aWnt5jG@avalon>
Hi all,
2017-12-12 0:45 GMT+08:00 Laurent Pinchart <laurent.pinchart@ideasonboard.com>:
> Hello Jacob,
>
> Thank you for the patch.
>
> On Wednesday, 6 December 2017 13:19:34 EET Jacob Chen wrote:
>> From: Jacob Chen <jacob2.chen@rock-chips.com>
>>
>> Add DT bindings documentation for Rockchip MIPI D-PHY RX
>>
>> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
>> ---
>> .../bindings/media/rockchip-mipi-dphy.txt | 71 +++++++++++++++++++
>> 1 file changed, 71 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt
>>
>> diff --git a/Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt
>> b/Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt new file
>> mode 100644
>> index 000000000000..cef9450db051
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt
>> @@ -0,0 +1,71 @@
>> +Rockchip SoC MIPI RX D-PHY
>> +-------------------------------------------------------------
>> +
>> +Required properties:
>> +
>> +- compatible: value should be one of the following
>> + "rockchip,rk3288-mipi-dphy";
>> + "rockchip,rk3399-mipi-dphy";
>> +- rockchip,grf: GRF regs.
>> +- bus-width : maximum number of data lanes supported (SoC specific);
>
> Bus width isn't a standard property, should this be rockchip,data-lanes or
> rockchip,#data-lanes ?
I forgot to remove it, it's no unnecessary now.
>
>> +- clocks : list of clock specifiers, corresponding to entries in
>> + clock-names property;
>> +- clock-names: required clock name.
>> +
>> +The device node should contain two 'port' child node, according to the
>
> s/child node/child nodes/
>
>> bindings
>> +defined in Documentation/devicetree/bindings/media/video-interfaces.txt.
>> +The first port should be connected to sensor nodes, and the second port
>> should be
>> +connected to isp node. The following are properties specific to those
>> nodes.
>> +
>> +endpoint node
>> +-------------
>> +
>> +- data-lanes : (required) an array specifying active physical MIPI-CSI2
>> + data input lanes and their mapping to logical lanes; the
>> + array's content is unused, only its length is meaningful;
>
> I assume this means that the D-PHY can't reroute lanes. I would mention that
> explicitly, and require that the data-lanes values start at one at are
> consecutive instead of ignoring them.
>
>> +Device node example
>> +-------------------
>> +
>> + mipi_dphy_rx0: mipi-dphy-rx0 {
>> + compatible = "rockchip,rk3399-mipi-dphy";
>> + clocks = <&cru SCLK_MIPIDPHY_REF>,
>> + <&cru SCLK_DPHY_RX0_CFG>,
>> + <&cru PCLK_VIO_GRF>;
>> + clock-names = "dphy-ref", "dphy-cfg", "grf";
>> + power-domains = <&power RK3399_PD_VIO>;
>> + bus-width = <4>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + mipi_in_wcam: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&wcam_out>;
>> + data-lanes = <1 2>;
>> + };
>> + mipi_in_ucam: endpoint@1 {
>> + reg = <1>;
>> + remote-endpoint = <&ucam_out>;
>> + data-lanes = <1>;
>> + };
>
> What do those two camera correspond to ? Can they be active at the same time,
> or do they use the same data lanes ? If they use the same data lanes, how does
> this work, is there a multiplexer on the board ?
>
They can not be active at the same time, and there is no multiplexer.
If they use the same mipi phy, then only one sensor is allowed to be actived.
See "MIPI Details" chapter
http://opensource.rock-chips.com/wiki_Rockchip-isp1
Let me enumerates soime hardware connections that is common in
rockchip tablet desgin.
rk3288:
-
ISP0 --> mipi TX1/RX1 --> front sensor
--> mipi RX0 --> rear sensor
-
ISP0 --> parallel --> front sensor
--> mipi RX0 --> rear sensor
rk3399
-
mipi TX1/RX1 , mipi TX0 --> dual-mipi screen
ISP0 --> mipi RX0 --> front sensor
--> rear sensor
-
ISP1 --> mipi TX1/RX1 --> front sensor
ISP0 --> mipi RX0 --> rear sensor
Only the last connection allow two sensor work at same time.
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + dphy_rx0_out: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&isp0_mipi_in>;
>> + };
>> + };
>> + };
>> + };
>> \ No newline at end of file
>
> --
> Regards,
>
> Laurent Pinchart
>
^ permalink raw reply
* Re: [PATCH] dt-bindings: display: panel: Fix compatible string for Toshiba LT089AC29000
From: Lucas Stach @ 2017-12-18 11:53 UTC (permalink / raw)
To: Jonathan Neuschäfer, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Thierry Reding, David Airlie, Rob Herring, Mark Rutland,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171217023433.11542-1-j.neuschaefer-hi6Y0CQ0nG0@public.gmane.org>
Am Sonntag, den 17.12.2017, 03:34 +0100 schrieb Jonathan Neuschäfer:
> The compatible string for this panel was specified as
> toshiba,lt089ac29000.txt. I believe this is a mistake.
>
> Fixes: 06e733e41f87 ("drm/panel: simple: add Toshiba LT089AC19000")
> > Cc: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Signed-off-by: Jonathan Neuschäfer <j.neuschaefer-hi6Y0CQ0nG0@public.gmane.org>
Yes, this is an obvious copy-and-paste issue.
Acked-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
> .../devicetree/bindings/display/panel/toshiba,lt089ac29000.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/display/panel/toshiba,lt089ac29000.txt b/Documentation/devicetree/bindings/display/panel/toshiba,lt089ac29000.txt
> index 4c0caaf246c9..89826116628c 100644
> --- a/Documentation/devicetree/bindings/display/panel/toshiba,lt089ac29000.txt
> +++ b/Documentation/devicetree/bindings/display/panel/toshiba,lt089ac29000.txt
> @@ -1,7 +1,7 @@
> Toshiba 8.9" WXGA (1280x768) TFT LCD panel
>
> Required properties:
> -- compatible: should be "toshiba,lt089ac29000.txt"
> +- compatible: should be "toshiba,lt089ac29000"
> - power-supply: as specified in the base binding
>
> This binding is compatible with the simple-panel binding, which is specified
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/2] ARM: dts: sun8i: h3: nanopi-m1-plus: fix missing ethernet 0 in aliases
From: Philipp Rossak @ 2017-12-18 11:52 UTC (permalink / raw)
To: Maxime Ripard
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, wens-jdAy2FN1RRM,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20171218064508.iyi4cyjkwesoezf5-ZC1Zs529Oq4@public.gmane.org>
Sorry!
I will fix it!
On 18.12.2017 07:45, Maxime Ripard wrote:
> Hi,
>
> On Fri, Dec 15, 2017 at 11:39:00PM +0100, Philipp Rossak wrote:
>> Signed-off-by: Philipp Rossak <embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> Please add a commit log here.
>
^ permalink raw reply
* [PATCH v4 4/4] ARM: imx_v6_v7_defconfig: enable RTC_DRV_MXC_V2
From: linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w @ 2017-12-18 11:51 UTC (permalink / raw)
Cc: Patrick Bruenn, Shawn Guo, Sascha Hauer, Alessandro Zummo,
Alexandre Belloni, Rob Herring, Mark Rutland,
open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Fabio Estevam, Juergen Borleis, Noel Vellemans,
Russell King,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Ph
In-Reply-To: <20171218115133.16371-1-linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
From: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
Enable SRTC driver for i.MX53 in default config
Signed-off-by: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
---
v3:
- imx_v4_v5_defconfig was the wrong default config for i.MX53
Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Alessandro Zummo <a.zummo-BfzFCNDTiLLj+vYz1yj4TQ@public.gmane.org>
Cc: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list)
Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
Cc: Juergen Borleis <jbe-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Cc: Noel Vellemans <Noel.Vellemans-8UENEgx6w+makBO8gow8eQ@public.gmane.org>
Cc: Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> (maintainer:ARM PORT)
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne-od1rfyK75/E@public.gmane.org>
Cc: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 0d4494922561..548c11142a4e 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -349,6 +349,7 @@ CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_M41T80=y
CONFIG_RTC_DRV_MC13XXX=y
CONFIG_RTC_DRV_MXC=y
+CONFIG_RTC_DRV_MXC_V2=y
CONFIG_RTC_DRV_SNVS=y
CONFIG_DMADEVICES=y
CONFIG_FSL_EDMA=y
--
2.11.0
--
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^ permalink raw reply related
* [PATCH v4 3/4] rtc: add mxc driver for i.MX53 SRTC
From: linux-kernel-dev @ 2017-12-18 11:51 UTC (permalink / raw)
Cc: Patrick Bruenn, Alessandro Zummo, Alexandre Belloni, Rob Herring,
Mark Rutland, open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Fabio Estevam, Juergen Borleis, Noel Vellemans,
Shawn Guo, Sascha Hauer, Russell King,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Ph
In-Reply-To: <20171218115133.16371-1-linux-kernel-dev@beckhoff.com>
From: Patrick Bruenn <p.bruenn@beckhoff.com>
Neither rtc-imxdi, rtc-mxc nor rtc-snvs are compatible with i.MX53.
This is driver enables support for the low power domain SRTC features:
- 32-bit MSB of non-rollover time counter
- 32-bit alarm register
Select the new config option RTC_DRV_MXC_V2 to build this driver
Based on:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/rtc/rtc-mxc_v2.c?h=imx_2.6.35_11.09.01
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
---
v3:
- introduce new config option with the same patch, which adds the driver
- call rtc_update_irq() only if necessary
- merge mxc_rtc_write_alarm_locked() with mxc_rtc_set_alarm()
- only use clk_enable/disable (without "prepare") during operation
- rebase on v4.15-rc3
- consistently use rtc_tm_to_time64() and time64_t
- refactor mxc_rtc_read_time(): don't lock for readl() only;
don't rtc_valid_tm(); use time64_t
- check returncode of mxc_rtc_wait_for_flag()
- restructure mxc_rtc_sync_lp_locked() to replace pr_err() with
dev_err_once(); remove explicit 'inline'
- don't touch imx_v4_v5_defconfig, instead add to imx_v6_v7_defconfig
v2:
- have seperate patches for dt-binding, CONFIG option, imx53.dtsi and driver
- add SPDX-License-Identifier and cleanup copyright notice
- replace __raw_readl/writel() with readl/writel()
- fix PM_SLEEP callbacks
- add CONFIG_RTC_DRV_MXC_V2 to build rtc-mxc_v2.c
- remove misleading or obvious comments and fix style of the remaining
- avoid endless loop while waiting for hw
- implement consistent locking; make spinlock a member of dev struct
- enable clk only for register accesses
- remove all udelay() calls since they are obsolete or redundant
(we are already waiting for register flags to change)
- init platform_data before registering irq callback
- let set_time() fail, when 32 bit rtc counter exceeded
- make names more consistent
- cleanup and reorder includes
- cleanup and remove unused defines
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc@vger.kernel.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel@vger.kernel.org (open list)
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Juergen Borleis <jbe@pengutronix.de>
Cc: Noel Vellemans <Noel.Vellemans@visionbms.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Russell King <linux@armlinux.org.uk> (maintainer:ARM PORT)
Cc: linux-arm-kernel@lists.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Lothar Waßmann <LW@KARO-electronics.de>
---
drivers/rtc/Kconfig | 10 ++
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mxc_v2.c | 422 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 433 insertions(+)
create mode 100644 drivers/rtc/rtc-mxc_v2.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index b59a31b079a5..440edebf5c71 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1689,6 +1689,16 @@ config RTC_DRV_MXC
This driver can also be built as a module, if so, the module
will be called "rtc-mxc".
+config RTC_DRV_MXC_V2
+ tristate "Freescale MXC Real Time Clock for i.MX53"
+ depends on ARCH_MXC
+ help
+ If you say yes here you get support for the Freescale MXC
+ SRTC module in i.MX53 processor.
+
+ This driver can also be built as a module, if so, the module
+ will be called "rtc-mxc_v2".
+
config RTC_DRV_SNVS
tristate "Freescale SNVS RTC support"
select REGMAP_MMIO
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index f2f50c11dc38..dcf60e61ae5c 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -106,6 +106,7 @@ obj-$(CONFIG_RTC_DRV_MT6397) += rtc-mt6397.o
obj-$(CONFIG_RTC_DRV_MT7622) += rtc-mt7622.o
obj-$(CONFIG_RTC_DRV_MV) += rtc-mv.o
obj-$(CONFIG_RTC_DRV_MXC) += rtc-mxc.o
+obj-$(CONFIG_RTC_DRV_MXC_V2) += rtc-mxc_v2.o
obj-$(CONFIG_RTC_DRV_NUC900) += rtc-nuc900.o
obj-$(CONFIG_RTC_DRV_OMAP) += rtc-omap.o
obj-$(CONFIG_RTC_DRV_OPAL) += rtc-opal.o
diff --git a/drivers/rtc/rtc-mxc_v2.c b/drivers/rtc/rtc-mxc_v2.c
new file mode 100644
index 000000000000..b637095b0716
--- /dev/null
+++ b/drivers/rtc/rtc-mxc_v2.c
@@ -0,0 +1,422 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Real Time Clock (RTC) Driver for i.MX53
+ * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
+ * Copyright (c) 2017 Beckhoff Automation GmbH & Co. KG
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+
+#define SRTC_LPPDR_INIT 0x41736166 /* init for glitch detect */
+
+#define SRTC_LPCR_EN_LP BIT(3) /* lp enable */
+#define SRTC_LPCR_WAE BIT(4) /* lp wakeup alarm enable */
+#define SRTC_LPCR_ALP BIT(7) /* lp alarm flag */
+#define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
+#define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */
+#define SRTC_LPCR_IE BIT(15) /* lp init state exit bit */
+
+#define SRTC_LPSR_ALP BIT(3) /* lp alarm flag */
+#define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
+#define SRTC_LPSR_IES BIT(15) /* lp init state exit status */
+
+#define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
+#define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
+#define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
+#define SRTC_LPCR 0x10 /* LP Control Reg */
+#define SRTC_LPSR 0x14 /* LP Status Reg */
+#define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
+
+/* max. number of retries to read registers, 120 was max during test */
+#define REG_READ_TIMEOUT 2000
+
+struct mxc_rtc_data {
+ struct rtc_device *rtc;
+ void __iomem *ioaddr;
+ struct clk *clk;
+ spinlock_t lock; /* protects register access */
+ int irq;
+};
+
+/*
+ * This function does write synchronization for writes to the lp srtc block.
+ * To take care of the asynchronous CKIL clock, all writes from the IP domain
+ * will be synchronized to the CKIL domain.
+ * The caller should hold the pdata->lock
+ */
+static void mxc_rtc_sync_lp_locked(struct device *dev, void __iomem *ioaddr)
+{
+ unsigned int i;
+
+ /* Wait for 3 CKIL cycles */
+ for (i = 0; i < 3; i++) {
+ const u32 count = readl(ioaddr + SRTC_LPSCLR);
+ unsigned int timeout = REG_READ_TIMEOUT;
+
+ while ((readl(ioaddr + SRTC_LPSCLR)) == count) {
+ if (!--timeout) {
+ dev_err_once(dev, "SRTC_LPSCLR stuck! Check your hw.\n");
+ return;
+ }
+ }
+ }
+}
+
+/* This function is the RTC interrupt service routine. */
+static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
+{
+ struct device *dev = dev_id;
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ void __iomem *ioaddr = pdata->ioaddr;
+ unsigned long flags;
+ u32 lp_status;
+ u32 lp_cr;
+
+ spin_lock_irqsave(&pdata->lock, flags);
+ if (clk_enable(pdata->clk)) {
+ spin_unlock_irqrestore(&pdata->lock, flags);
+ return IRQ_NONE;
+ }
+
+ lp_status = readl(ioaddr + SRTC_LPSR);
+ lp_cr = readl(ioaddr + SRTC_LPCR);
+
+ /* update irq data & counter */
+ if (lp_status & SRTC_LPSR_ALP) {
+ if (lp_cr & SRTC_LPCR_ALP)
+ rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);
+
+ /* disable further lp alarm interrupts */
+ lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+ }
+
+ /* Update interrupt enables */
+ writel(lp_cr, ioaddr + SRTC_LPCR);
+
+ /* clear interrupt status */
+ writel(lp_status, ioaddr + SRTC_LPSR);
+
+ mxc_rtc_sync_lp_locked(dev, ioaddr);
+ clk_disable(pdata->clk);
+ spin_unlock_irqrestore(&pdata->lock, flags);
+ return IRQ_HANDLED;
+}
+
+/*
+ * Enable clk and aquire spinlock
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_lock(struct mxc_rtc_data *const pdata)
+{
+ int ret;
+
+ spin_lock_irq(&pdata->lock);
+ ret = clk_enable(pdata->clk);
+ if (ret) {
+ spin_unlock_irq(&pdata->lock);
+ return ret;
+ }
+ return 0;
+}
+
+static int mxc_rtc_unlock(struct mxc_rtc_data *const pdata)
+{
+ clk_disable(pdata->clk);
+ spin_unlock_irq(&pdata->lock);
+ return 0;
+}
+
+/*
+ * This function reads the current RTC time into tm in Gregorian date.
+ *
+ * @param tm contains the RTC time value upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ const int clk_failed = clk_enable(pdata->clk);
+
+ if (!clk_failed) {
+ const time64_t now = readl(pdata->ioaddr + SRTC_LPSCMR);
+
+ rtc_time64_to_tm(now, tm);
+ clk_disable(pdata->clk);
+ return 0;
+ }
+ return clk_failed;
+}
+
+/*
+ * This function sets the internal RTC time based on tm in Gregorian date.
+ *
+ * @param tm the time value to be set in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ time64_t time = rtc_tm_to_time64(tm);
+ int ret;
+
+ if (time > U32_MAX) {
+ dev_err(dev, "RTC exceeded by %llus\n", time - U32_MAX);
+ return -EINVAL;
+ }
+
+ ret = mxc_rtc_lock(pdata);
+ if (ret)
+ return ret;
+
+ writel(time, pdata->ioaddr + SRTC_LPSCMR);
+ mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
+ return mxc_rtc_unlock(pdata);
+}
+
+/*
+ * This function reads the current alarm value into the passed in \b alrm
+ * argument. It updates the \b alrm's pending field value based on the whether
+ * an alarm interrupt occurs or not.
+ *
+ * @param alrm contains the RTC alarm value upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ void __iomem *ioaddr = pdata->ioaddr;
+ int ret;
+
+ ret = mxc_rtc_lock(pdata);
+ if (ret)
+ return ret;
+
+ rtc_time_to_tm(readl(ioaddr + SRTC_LPSAR), &alrm->time);
+ alrm->pending = !!(readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP);
+ return mxc_rtc_unlock(pdata);
+}
+
+/*
+ * Enable/Disable alarm interrupt
+ * The caller should hold the pdata->lock
+ */
+static void mxc_rtc_alarm_irq_enable_locked(struct mxc_rtc_data *pdata,
+ unsigned int enable)
+{
+ u32 lp_cr = readl(pdata->ioaddr + SRTC_LPCR);
+
+ if (enable)
+ lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+ else
+ lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+
+ writel(lp_cr, pdata->ioaddr + SRTC_LPCR);
+}
+
+static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ int ret = mxc_rtc_lock(pdata);
+
+ if (ret)
+ return ret;
+
+ mxc_rtc_alarm_irq_enable_locked(pdata, enable);
+ return mxc_rtc_unlock(pdata);
+}
+
+/*
+ * This function sets the RTC alarm based on passed in alrm.
+ *
+ * @param alrm the alarm value to be set in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ const time64_t time = rtc_tm_to_time64(&alrm->time);
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ int ret = mxc_rtc_lock(pdata);
+
+ if (ret)
+ return ret;
+
+ if (time > U32_MAX) {
+ dev_err(dev, "Hopefully I am out of service by then :-(\n");
+ return -EINVAL;
+ }
+
+ writel((u32)time, pdata->ioaddr + SRTC_LPSAR);
+
+ /* clear alarm interrupt status bit */
+ writel(SRTC_LPSR_ALP, pdata->ioaddr + SRTC_LPSR);
+ mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
+
+ mxc_rtc_alarm_irq_enable_locked(pdata, alrm->enabled);
+ mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
+ mxc_rtc_unlock(pdata);
+ return ret;
+}
+
+static const struct rtc_class_ops mxc_rtc_ops = {
+ .read_time = mxc_rtc_read_time,
+ .set_time = mxc_rtc_set_time,
+ .read_alarm = mxc_rtc_read_alarm,
+ .set_alarm = mxc_rtc_set_alarm,
+ .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
+};
+
+static int mxc_rtc_wait_for_flag(void *__iomem ioaddr, int flag)
+{
+ unsigned int timeout = REG_READ_TIMEOUT;
+
+ while (!(readl(ioaddr) & flag)) {
+ if (!--timeout)
+ return -EBUSY;
+ }
+ return 0;
+}
+
+static int mxc_rtc_probe(struct platform_device *pdev)
+{
+ struct mxc_rtc_data *pdata;
+ struct resource *res;
+ void __iomem *ioaddr;
+ int ret = 0;
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pdata->ioaddr))
+ return PTR_ERR(pdata->ioaddr);
+
+ ioaddr = pdata->ioaddr;
+
+ pdata->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pdata->clk)) {
+ dev_err(&pdev->dev, "unable to get rtc clock!\n");
+ return PTR_ERR(pdata->clk);
+ }
+
+ spin_lock_init(&pdata->lock);
+ pdata->irq = platform_get_irq(pdev, 0);
+ if (pdata->irq < 0)
+ return pdata->irq;
+
+ device_init_wakeup(&pdev->dev, 1);
+
+ ret = clk_prepare_enable(pdata->clk);
+ if (ret)
+ return ret;
+ /* initialize glitch detect */
+ writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
+
+ /* clear lp interrupt status */
+ writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
+
+ /* move out of init state */
+ writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), ioaddr + SRTC_LPCR);
+ ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_IES);
+ if (ret) {
+ dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_IES\n");
+ clk_disable_unprepare(pdata->clk);
+ return ret;
+ }
+
+ /* move out of non-valid state */
+ writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
+ SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
+ ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_NVES);
+ if (ret) {
+ dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_NVES\n");
+ clk_disable_unprepare(pdata->clk);
+ return ret;
+ }
+
+ clk_disable(pdata->clk);
+ platform_set_drvdata(pdev, pdata);
+ ret =
+ devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, 0,
+ pdev->name, &pdev->dev);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "interrupt not available.\n");
+ clk_unprepare(pdata->clk);
+ return ret;
+ }
+
+ pdata->rtc =
+ devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
+ THIS_MODULE);
+ if (IS_ERR(pdata->rtc)) {
+ clk_unprepare(pdata->clk);
+ return PTR_ERR(pdata->rtc);
+ }
+
+ return 0;
+}
+
+static int __exit mxc_rtc_remove(struct platform_device *pdev)
+{
+ struct mxc_rtc_data *pdata = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(pdata->clk);
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int mxc_rtc_suspend(struct device *dev)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+
+ if (device_may_wakeup(dev))
+ enable_irq_wake(pdata->irq);
+
+ return 0;
+}
+
+static int mxc_rtc_resume(struct device *dev)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+
+ if (device_may_wakeup(dev))
+ disable_irq_wake(pdata->irq);
+
+ return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);
+
+static const struct of_device_id mxc_ids[] = {
+ { .compatible = "fsl,imx53-rtc", },
+ {}
+};
+
+static struct platform_driver mxc_rtc_driver = {
+ .driver = {
+ .name = "mxc_rtc_v2",
+ .of_match_table = mxc_ids,
+ .pm = &mxc_rtc_pm_ops,
+ },
+ .probe = mxc_rtc_probe,
+ .remove = mxc_rtc_remove,
+};
+
+module_platform_driver(mxc_rtc_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Real Time Clock (RTC) Driver for i.MX53");
+MODULE_LICENSE("GPL");
--
2.11.0
^ permalink raw reply related
* [PATCH v4 2/4] ARM: dts: imx53: add srtc node
From: linux-kernel-dev @ 2017-12-18 11:51 UTC (permalink / raw)
Cc: Patrick Bruenn, Shawn Guo, Sascha Hauer, Alessandro Zummo,
Alexandre Belloni, Rob Herring, Mark Rutland,
open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Fabio Estevam, Juergen Borleis, Noel Vellemans,
Russell King,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Ph
In-Reply-To: <20171218115133.16371-1-linux-kernel-dev@beckhoff.com>
From: Patrick Bruenn <p.bruenn@beckhoff.com>
rtc-mxc_v2 driver will add support for the i.MX53 SRTC
Note: we keep the 'srtc' label to avoid duplicate with imx53-m53.dtsi
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
---
v4:
- replace "srtc" node name with generic "rtc"
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc@vger.kernel.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel@vger.kernel.org (open list)
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Juergen Borleis <jbe@pengutronix.de>
Cc: Noel Vellemans <Noel.Vellemans@visionbms.com>
Cc: Russell King <linux@armlinux.org.uk> (maintainer:ARM PORT)
Cc: linux-arm-kernel@lists.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Lothar Waßmann <LW@KARO-electronics.de>
---
arch/arm/boot/dts/imx53.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 84f17f7abb71..beca1c830623 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -433,6 +433,13 @@
clock-names = "ipg", "per";
};
+ srtc: rtc@53fa4000 {
+ compatible = "fsl,imx53-rtc";
+ reg = <0x53fa4000 0x4000>;
+ interrupts = <24>;
+ clocks = <&clks IMX5_CLK_SRTC_GATE>;
+ };
+
iomuxc: iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc";
reg = <0x53fa8000 0x4000>;
--
2.11.0
^ permalink raw reply related
* [PATCH v4 1/4] dt-bindings: rtc: add bindings for i.MX53 SRTC
From: linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w @ 2017-12-18 11:51 UTC (permalink / raw)
Cc: Patrick Bruenn, Alessandro Zummo, Alexandre Belloni, Rob Herring,
Mark Rutland, open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Fabio Estevam, Juergen Borleis, Noel Vellemans,
Shawn Guo, Sascha Hauer, Russell King,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Ph
In-Reply-To: <20171218115133.16371-1-linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
From: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
Document the binding for i.MX53 SRTC implemented by rtc-mxc_v2
Signed-off-by: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
---
v4:
- replace "srtc" node name with generic "rtc"
v2:
- added "Secure" and (SRTC) to the description
Cc: Alessandro Zummo <a.zummo-BfzFCNDTiLLj+vYz1yj4TQ@public.gmane.org>
Cc: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list)
Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
Cc: Juergen Borleis <jbe-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Cc: Noel Vellemans <Noel.Vellemans-8UENEgx6w+makBO8gow8eQ@public.gmane.org>
Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> (maintainer:ARM PORT)
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne-od1rfyK75/E@public.gmane.org>
Cc: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
---
Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
diff --git a/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt b/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
new file mode 100644
index 000000000000..79d7e87b0d91
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
@@ -0,0 +1,17 @@
+* i.MX53 Secure Real Time Clock (SRTC)
+
+Required properties:
+- compatible: should be: "fsl,imx53-rtc"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- clocks: should contain the phandle for the rtc clock
+- interrupts: rtc alarm interrupt
+
+Example:
+
+rtc@53fa4000 {
+ compatible = "fsl,imx53-rtc";
+ reg = <0x53fa4000 0x4000>;
+ interrupts = <24>;
+ clocks = <&clks IMX5_CLK_SRTC_GATE>;
+};
--
2.11.0
--
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^ permalink raw reply related
* [PATCH v4 0/4] rtc: add mxc driver for i.MX53 SRTC
From: linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w @ 2017-12-18 11:51 UTC (permalink / raw)
Cc: Patrick Bruenn, Alessandro Zummo, Alexandre Belloni, Rob Herring,
Mark Rutland, open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Fabio Estevam, Juergen Borleis, Noel Vellemans,
Shawn Guo, Sascha Hauer, Russell King,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Ph
From: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
Neither rtc-imxdi, rtc-mxc nor rtc-snvs are compatible with i.MX53.
This is driver enables support for the low power domain SRTC features:
- 32-bit MSB of non-rollover time counter
- 32-bit alarm register
Select the new config option RTC_DRV_MXC_V2 to build this driver
Based on:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/rtc/rtc-mxc_v2.c?h=imx_2.6.35_11.09.01
Signed-off-by: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
---
v4:
- rename "srtc" node into generic "rtc" keep the label as "srtc" to avoid
duplication with imx53-m53.dtsi
- fix Signed-off-by: in bindings-patch
v3:
- introduce new config option with the same patch, which adds the driver
- call rtc_update_irq() only if necessary
- merge mxc_rtc_write_alarm_locked() with mxc_rtc_set_alarm()
- only use clk_enable/disable (without "prepare") during operation
- rebase on v4.15-rc3
- consistently use rtc_tm_to_time64() and time64_t
- refactor mxc_rtc_read_time(): don't lock for readl() only;
don't rtc_valid_tm(); use time64_t
- check returncode of mxc_rtc_wait_for_flag()
- restructure mxc_rtc_sync_lp_locked() to replace pr_err() with
dev_err_once(); remove explicit 'inline'
- don't touch imx_v4_v5_defconfig, instead add to imx_v6_v7_defconfig
v2:
- have seperate patches for dt-binding, CONFIG option, imx53.dtsi and driver
- add SPDX-License-Identifier and cleanup copyright notice
- replace __raw_readl/writel() with readl/writel()
- fix PM_SLEEP callbacks
- add CONFIG_RTC_DRV_MXC_V2 to build rtc-mxc_v2.c
- remove misleading or obvious comments and fix style of the remaining
- avoid endless loop while waiting for hw
- implement consistent locking; make spinlock a member of dev struct
- enable clk only for register accesses
- remove all udelay() calls since they are obsolete or redundant
(we are already waiting for register flags to change)
- init platform_data before registering irq callback
- let set_time() fail, when 32 bit rtc counter exceeded
- make names more consistent
- cleanup and reorder includes
- cleanup and remove unused defines
Cc: Alessandro Zummo <a.zummo-BfzFCNDTiLLj+vYz1yj4TQ@public.gmane.org>
Cc: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list)
Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
Cc: Juergen Borleis <jbe-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Cc: Noel Vellemans <Noel.Vellemans-8UENEgx6w+makBO8gow8eQ@public.gmane.org>
Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> (maintainer:ARM PORT)
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne-od1rfyK75/E@public.gmane.org>
Cc: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
---
Patrick Bruenn (4):
dt-bindings: rtc: add bindings for i.MX53 SRTC
ARM: dts: imx53: add srtc node
rtc: add mxc driver for i.MX53 SRTC
ARM: imx_v6_v7_defconfig: enable RTC_DRV_MXC_V2
.../devicetree/bindings/rtc/rtc-mxc_v2.txt | 17 +
arch/arm/boot/dts/imx53.dtsi | 7 +
arch/arm/configs/imx_v6_v7_defconfig | 1 +
drivers/rtc/Kconfig | 10 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mxc_v2.c | 422 +++++++++++++++++++++
6 files changed, 458 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
create mode 100644 drivers/rtc/rtc-mxc_v2.c
--
2.11.0
--
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^ permalink raw reply
* Re: [PATCH v4 13/36] nds32: Device specific operations
From: Greentime Hu @ 2017-12-18 11:44 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Greentime, Linux Kernel Mailing List, linux-arch, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Networking, Vincent Chen,
DTML, Al Viro, David Howells, Will Deacon, Daniel Lezcano,
linux-serial-u79uwXL29TY76Z2rM5mHXA, Geert Uytterhoeven,
Linus Walleij, Mark Rutland, Greg KH, Guo Ren
In-Reply-To: <CAK8P3a0xQ4mYnkxjWTTEcvpJg6SfcA4WZKNkopa93_6Mz_YOGw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-12-18 19:26 GMT+08:00 Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>:
> On Mon, Dec 18, 2017 at 7:46 AM, Greentime Hu <green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>
>> +#define __ASM_NDS32_IO_H
>> +
>> +extern void iounmap(void __iomem *addr);
>
> The prototype here should probably include 'volatile' to avoid warnings in an
> allmodconfig build.
>
Thanks. I will update it like this.
extern void iounmap(volatile void __iomem *addr);
--
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^ permalink raw reply
* Re: [PATCH 0/2] Use SPDX-License-Identifier for rockchip devicetree files
From: Matthias Brugger @ 2017-12-18 11:43 UTC (permalink / raw)
To: klaus.goger-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5, Heiko Stübner
Cc: Mark Rutland, Emil Renner Berthing, Huibin Hong, Catalin Marinas,
Linus Walleij, Will Deacon, Kever Yang, LKML, Finley Xiao,
Joseph Chen, Romain Perier, Randy Li, Matthias Kaehlcke,
Sugar Zhang, Simon Xue, Heinrich Schuchardt, Brian Norris,
Russell King, FUKAUMI Naoki, Jaehoon Chung,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Chen-Yu Tsai,
Jacob Chen, Jagan
In-Reply-To: <24788EB1-9868-41E9-B97C-7D85D8C3761D-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org>
On 12/15/2017 05:27 PM, klaus.goger@theobroma-systems.com wrote:
>> On 15.12.2017, at 16:20, Heiko Stübner <heiko@sntech.de> wrote:
>>
>> Am Freitag, 15. Dezember 2017, 15:42:48 CET schrieb Philippe Ombredanne:
>>> On Fri, Dec 15, 2017 at 3:28 PM, Heiko Stübner <heiko@sntech.de> wrote:
>>>> Am Freitag, 15. Dezember 2017, 14:45:34 CET schrieb Philippe Ombredanne:
>>>>> Klaus,
>>>>>
>>>>> On Fri, Dec 15, 2017 at 12:44 PM, Klaus Goger
>>>>>
>>>>> <klaus.goger@theobroma-systems.com> wrote:
>>>>>> This patch series replaces all the license text in rockchip devicetree
>>>>>> files text with a proper SPDX-License-Identifier.
>>>>>> It follows the guidelines submitted[1] by Thomas Gleixner that are not
>>>>>> yet merged.
>>>>>>
>>>>>> These series also fixes the issue with contradicting statements in most
>>>>>> licenses. The introduction text claims to be GPL or X11[2] but the
>>>>>> following verbatim copy of the license is actually a MIT[3] license.
>>>>>> The X11 license includes a advertise clause and trademark information
>>>>>> related to the X Consortium. As these X Consortium specfic points are
>>>>>> irrelevant for us we stick with the actuall license text.
>>>>>>
>>>>>> [1] https://patchwork.kernel.org/patch/10091607/
>>>>>> [2] https://spdx.org/licenses/X11.html
>>>>>> [3] https://spdx.org/licenses/MIT.html
>>>>>
>>>>> FWIW, the X11 license name was not always something clearly defined.
>>>>> SPDX calls it clearly MIT which is the most widely accepted name for
>>>>> the corresponding text. And this is also what we have in Thomas doc
>>>>> patches that should be the kernel reference.
>>>>>
>>>>> Also, as a general note, you want to make sure that such as patch set
>>>>> is not merged by mistake until you have collected an explicit review
>>>>> or ack from all the copyright holders involved.
>>>>
>>>> Just for my understanding, is it really necessary to get Acks from _all_
>>>> previous contributors?
>>>>
>>>> I see that Thomas patches moving license texts into the kernel itself do
>>>> not seem to have landed yet, but when the actual license text does _not_
>>>> change and only its location to a common place inside the kernel sources,
>>>> it feels a bit overkill trying to get Acks from _everybody_ that
>>>> contributed to Rockchip devicetrees for the last 4 years.
>>>>
>>>> If we would actually want to change the license I would definitly feel
>>>> differently, but the license text does not change.
>>>
>>> Well you are technically right. But there is a social and politeness
>>> angle to this too. So may be getting the ack of all contributors is
>>> not always needed, but getting it is best and the right to do and at
>>> least getting for the named copyright holders should be there.
>>>
>>> That's only only my take: leaving aside any technical legal issue, say
>>> I would be on the receiving end as one of the holder or contributors:
>>> I would find it really great and nice to have my ack requested. And I
>>> would be a dork not to give it. So I like to do to others the same I
>>> would appreciate done to me (within reason, as I sometimes shoot
>>> myself in the foot ;) )
>>
>> Hehe ... I didn't plan on merging this without ample time for people
>> to either ACK or NAK the change, so was planning on keeping to social
>> protocol ;-) . Just the "all" threw me for a loop.
>>
>> And having that as PATCH without RFC also communicates that people
>> should take a look, as RFC patches are often overlooked.
>>
>> As Klaus seems to have included most people that have contributed in the
>> past, I would guess we should receive any existing complaints about that
>> change :-) .
>
> I added the full list from the get_maintainers script. Some of the original authors
> got dropped as the current contribution level dropped below the scripts limit.
> I added the missing email addresses from the copyright headers to the CC list.
>
> Convenience links to the original patches for the added people:
>
> https://patchwork.kernel.org/patch/10114845/
> https://patchwork.kernel.org/patch/10114843/
>
For both patches:
Acked-by: Matthias Brugger <mbrugger@suse.com>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply
* [PATCH] ARM64: meson-axg: enable hardware rng
From: Jerome Brunet @ 2017-12-18 11:35 UTC (permalink / raw)
To: Kevin Hilman, Carlo Caione
Cc: Jerome Brunet, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Enable the hardware random generator
Signed-off-by: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
Hi Kevin,
This patch depends on the changes adding the ethernet controller [0],
for including the axg clock binding header.
Cheers
Jerome
[0]: https://lkml.kernel.org/r/20171216035527.96952-2-yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index dea1bc31b4de..c741fc16486f 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -212,6 +212,13 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
+ hwrng: rng {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x18 0x0 0x4>;
+ clocks = <&clkc CLKID_RNG0>;
+ clock-names = "core";
+ };
+
pinctrl_periphs: pinctrl@480 {
compatible = "amlogic,meson-axg-periphs-pinctrl";
#address-cells = <2>;
--
2.14.3
--
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^ permalink raw reply related
* RE: [PATCH 1/5] ARM: dts: iwg20d-q7-common: Sound PIO support
From: Biju Das @ 2017-12-18 11:28 UTC (permalink / raw)
To: Simon Horman
Cc: Rob Herring, Mark Rutland, Kuninori Morimoto, Magnus Damm,
Chris Paterson, Fabrizio Castro, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
In-Reply-To: <20171218112221.krf6bh6sya56du5u@verge.net.au>
Hi Simon,
Thanks. I will send v2.
Regards,
Biju
> -----Original Message-----
> From: Simon Horman [mailto:horms@verge.net.au]
> Sent: 18 December 2017 11:22
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Kuninori Morimoto
> <kuninori.morimoto.gx@renesas.com>; Magnus Damm
> <magnus.damm@gmail.com>; Chris Paterson <Chris.Paterson2@renesas.com>;
> Fabrizio Castro <fabrizio.castro@bp.renesas.com>;
> devicetree@vger.kernel.org; linux-renesas-soc@vger.kernel.org
> Subject: Re: [PATCH 1/5] ARM: dts: iwg20d-q7-common: Sound PIO support
>
> On Fri, Dec 15, 2017 at 02:50:49PM +0000, Biju Das wrote:
> > Enable sound PIO support on carrier board.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > ---
> > arch/arm/boot/dts/iwg20d-q7-common.dtsi | 46
> > +++++++++++++++++++++++++++++++++
>
> It appears that the nodes in this file are in (or close to in) alphabetical order.
> Please add new nodes in a manner that preserves that. If necessary please
> provide a clean-up patch to shift nodes into alphabetical order.
[https://www2.renesas.eu/media/email/unicef_2017.jpg]
This Christmas, instead of sending out cards, Renesas Electronics Europe have decided to support Unicef with a donation. For further details click here<https://www.unicef.org/> to find out about the valuable work they do, helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a prosperous New Year.
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply
* Re: [PATCH v4 13/36] nds32: Device specific operations
From: Arnd Bergmann @ 2017-12-18 11:26 UTC (permalink / raw)
To: Greentime Hu
Cc: Greentime, Linux Kernel Mailing List, linux-arch, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Networking, Vincent Chen,
DTML, Al Viro, David Howells, Will Deacon, Daniel Lezcano,
linux-serial, Geert Uytterhoeven, Linus Walleij, Mark Rutland,
Greg KH, ren_guo, Philip
In-Reply-To: <ec54d5ac8067e2ff542f69fc2967182922870b83.1513577007.git.green.hu@gmail.com>
On Mon, Dec 18, 2017 at 7:46 AM, Greentime Hu <green.hu@gmail.com> wrote:
> +#define __ASM_NDS32_IO_H
> +
> +extern void iounmap(void __iomem *addr);
The prototype here should probably include 'volatile' to avoid warnings in an
allmodconfig build.
Arnd
^ permalink raw reply
* Re: [PATCH 1/5] ARM: dts: iwg20d-q7-common: Sound PIO support
From: Simon Horman @ 2017-12-18 11:22 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Kuninori Morimoto, Magnus Damm,
Chris Paterson, Fabrizio Castro, devicetree, linux-renesas-soc
In-Reply-To: <1513349453-54689-2-git-send-email-biju.das@bp.renesas.com>
On Fri, Dec 15, 2017 at 02:50:49PM +0000, Biju Das wrote:
> Enable sound PIO support on carrier board.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---
> arch/arm/boot/dts/iwg20d-q7-common.dtsi | 46 +++++++++++++++++++++++++++++++++
It appears that the nodes in this file are in (or close to in) alphabetical
order. Please add new nodes in a manner that preserves that. If necessary
please provide a clean-up patch to shift nodes into alphabetical order.
^ permalink raw reply
* Re: [PATCH v3 07/33] nds32: MMU initialization
From: Greentime Hu @ 2017-12-18 11:21 UTC (permalink / raw)
To: Guo Ren
Cc: Greentime, Linux Kernel Mailing List, Arnd Bergmann, linux-arch,
Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring, netdev,
Vincent Chen, DTML, Al Viro, David Howells, Will Deacon,
Daniel Lezcano, linux-serial-u79uwXL29TY76Z2rM5mHXA,
Geert Uytterhoeven, Linus Walleij, Mark Rutland, Greg KH
In-Reply-To: <20171218090848.GA5823@gary-OptiPlex-3050>
Hi, Guo Ren:
2017-12-18 17:08 GMT+08:00 Guo Ren <ren_guo-Y+KPrCd2zL4AvxtiuMwx3w@public.gmane.org>:
> Hi Greentime,
>
> On Fri, Dec 08, 2017 at 05:11:50PM +0800, Greentime Hu wrote:
> [...]
>>
>> diff --git a/arch/nds32/mm/highmem.c b/arch/nds32/mm/highmem.c
> [...]
>> +void *kmap(struct page *page)
>> +{
>> + unsigned long vaddr;
>> + might_sleep();
>> + if (!PageHighMem(page))
>> + return page_address(page);
>> + vaddr = (unsigned long)kmap_high(page);
> Here should invalid the cpu_mmu_tlb's entry, Or invalid it in the
> set_pte().
>
> eg:
> vaddr0 = kmap(page0)
> *vaddr0 = val0 //It will cause tlb-miss, and hard-refill to MMU-tlb
> kunmap(page0)
> vaddr1 = kmap(page1) // Mostly vaddr1 = vaddr0
> val = vaddr1; //No tlb-miss and it will get page0's val not page1, because
> last expired vaddr0's entry is left in CPU-MMU-tlb.
>
Thanks.
I will add __nds32__tlbop_inv(vaddr); to invalidate this mapping
before retrun vaddr.
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* Re: [PATCH v4 16/36] nds32: System calls handling
From: Arnd Bergmann @ 2017-12-18 11:19 UTC (permalink / raw)
To: Greentime Hu
Cc: Greentime, Linux Kernel Mailing List, linux-arch, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Networking, Vincent Chen,
DTML, Al Viro, David Howells, Will Deacon, Daniel Lezcano,
linux-serial-u79uwXL29TY76Z2rM5mHXA, Geert Uytterhoeven,
Linus Walleij, Mark Rutland, Greg KH,
ren_guo-Y+KPrCd2zL4AvxtiuMwx3w, Philip
In-Reply-To: <9663cb7c21011cdb4f278c1fad081d1df296daa8.1513577007.git.green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Mon, Dec 18, 2017 at 7:46 AM, Greentime Hu <green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> new file mode 100644
> index 0000000..90da745
> --- /dev/null
> +++ b/arch/nds32/include/uapi/asm/unistd.h
> @@ -0,0 +1,12 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (C) 2005-2017 Andes Technology Corporation
> +
> +#define __ARCH_WANT_SYNC_FILE_RANGE2
> +
> +/* Use the standard ABI for syscalls */
> +#include <asm-generic/unistd.h>
> +
> +/* Additional NDS32 specific syscalls. */
> +#define __NR_cacheflush (__NR_arch_specific_syscall)
> +#define __NR__llseek __NR_llseek
> +__SYSCALL(__NR_cacheflush, sys_cacheflush)
I'm still confused by __NR__llseek here, why do you need that one?
> +SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len,
> + unsigned long, prot, unsigned long, flags,
> + unsigned long, fd, unsigned long, pgoff)
> +{
> + if (pgoff & (~PAGE_MASK >> 12))
> + return -EINVAL;
> +
> + return sys_mmap_pgoff(addr, len, prot, flags, fd,
> + pgoff >> (PAGE_SHIFT - 12));
> +}
> +
> +SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
> + unsigned long, prot, unsigned long, flags,
> + unsigned long, fd, unsigned long, pgoff)
> +{
> + if (unlikely(pgoff & ~PAGE_MASK))
> + return -EINVAL;
> +
> + return sys_mmap_pgoff(addr, len, prot, flags, fd,
> + pgoff >> PAGE_SHIFT);
> +}
And I don't see why you define sys_mmap() in addition to sys_mmap2().
The rest of the syscall handling looks good now.
Arnd
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* Re: [PATCH 2/3] ARM: dts: r8a7743: Add CMT SoC specific support
From: Simon Horman @ 2017-12-18 11:18 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Geert Uytterhoeven, Rob Herring, Mark Rutland, Russell King,
Magnus Damm, Chris Paterson, Biju Das,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <TY1PR06MB08954C04D41BDA8EFA04E1DFC0350@TY1PR06MB0895.apcprd06.prod.outlook.com>
On Wed, Dec 13, 2017 at 10:15:39AM +0000, Fabrizio Castro wrote:
> Hello Geert,
>
> thank you for your feedback.
>
> > Hi Fabrizio,
> >
> > On Wed, Dec 13, 2017 at 10:42 AM, Fabrizio Castro
> > <fabrizio.castro@bp.renesas.com> wrote:
> > >> On Tue, Dec 12, 2017 at 06:49:38PM +0000, Fabrizio Castro wrote:
> > >> > Add CMT[01] support to SoC DT.
> > >> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
> > >> > ---
> > >> > arch/arm/boot/dts/r8a7743.dtsi | 30 ++++++++++++++++++++++++++++++
> > >> > 1 file changed, 30 insertions(+)
> > >>
> > >> I was expecting the cmt nodes to be "disabled" in the SoC file
> > >> and then enabled selectively in board files. Am I missing something?
> > >
> > > Since this component is just a compare and match timer, I thought there was no harm in enabling it by default in the SoC specific DT.
> > > The system will park it and leave its clock disabled until actually needed for something.
> > > The user can still disable it in the board specific DT if he/she doesn't mean to even have the option to use it. Do you prefer I left it
> > disabled by default?
> >
> > It's debatable (thus up to Simon the maintainer ;-).
> > For I/O devices, we disable them in the SoC .dtsi file.
> > For core infrastructure like interrupt, DMA, and GPIO controllers, we keep
> > them enabled.
> >
> > Timers are core functionality, but who's actually using these timers?
>
> I don't have a use case in mind unfortunately, but it's still core
> functionality and pretty harmless as far as I can tell. Let's see what
> Simon thinks about this.
On Renesas SoCs we have a bit more flexibility with timers than might
be the case on other SoCs. Thus I'd like to keep with the scheme of
disabling them in .dtsi and enabling them when they are needed.
Please update the patches.
^ permalink raw reply
* Re: [PATCH v4 25/36] nds32: Miscellaneous header files
From: Arnd Bergmann @ 2017-12-18 11:13 UTC (permalink / raw)
To: Greentime Hu
Cc: Greentime, Linux Kernel Mailing List, linux-arch, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Networking, Vincent Chen,
DTML, Al Viro, David Howells, Will Deacon, Daniel Lezcano,
linux-serial-u79uwXL29TY76Z2rM5mHXA, Geert Uytterhoeven,
Linus Walleij, Mark Rutland, Greg KH,
ren_guo-Y+KPrCd2zL4AvxtiuMwx3w, Philip
In-Reply-To: <a5dc2090640500d88aa3af2f6fe9e4c73f0634f2.1513577007.git.green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Mon, Dec 18, 2017 at 7:46 AM, Greentime Hu <green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> From: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
>
> This patch introduces some miscellaneous header files.
> +static inline void __delay(unsigned long loops)
> +{
> + __asm__ __volatile__(".align 2\n"
> + "1:\n"
> + "\taddi\t%0, %0, -1\n"
> + "\tbgtz\t%0, 1b\n"
> + :"=r"(loops)
> + :"0"(loops));
> +}
> +
> +static inline void __udelay(unsigned long usecs, unsigned long lpj)
> +{
> + usecs *= (unsigned long)(((0x8000000000000000ULL / (500000 / HZ)) +
> + 0x80000000ULL) >> 32);
> + usecs = (unsigned long)(((unsigned long long)usecs * lpj) >> 32);
> + __delay(usecs);
> +}
Do you have a reliable clocksource that you can read here instead of doing the
loop? It's generally preferred to have an accurate delay if at all possible, the
delay loop calibration is only for those architectures that don't have any
way to observe how much time has passed accurately.
Arnd
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^ permalink raw reply
* Re: [PATCH 0/5] Add Sound support for iWave RZ/G1M board
From: Simon Horman @ 2017-12-18 11:12 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Russell King, Magnus Damm,
Chris Paterson, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <KL1PR06MB170226A1E9F3CA011EBF3E2DB8350@KL1PR06MB1702.apcprd06.prod.outlook.com>
On Wed, Dec 13, 2017 at 09:27:30AM +0000, Biju Das wrote:
> Hi Simon,
>
> Thanks.
>
> There is a typo in the documentation dependency link.
> The correct one is https://patchwork.kernel.org/patch/10108015/
Thanks, series applied.
^ permalink raw reply
* Re: [PATCH v3 05/11] thermal: armada: Add support for Armada AP806
From: Baruch Siach @ 2017-12-18 11:11 UTC (permalink / raw)
To: Miquel RAYNAL
Cc: Gregory CLEMENT, Zhang Rui, Eduardo Valentin, Rob Herring,
Mark Rutland, Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
Catalin Marinas, Will Deacon, Thomas Petazzoni, devicetree,
linux-pm, Antoine Tenart, Nadav Haklai, David Sniatkiwicz,
linux-arm-kernel
In-Reply-To: <20171218104127.65017555@xps13>
Hi Miquèl,
On Mon, Dec 18, 2017 at 10:41:27AM +0100, Miquel RAYNAL wrote:
> Hello Gregory & Baruch,
>
> On Thu, 14 Dec 2017 12:05:43 +0100
> Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
>
> > > @@ -184,9 +214,9 @@ static int armada_get_temp(struct
> > > thermal_zone_device *thermal, div = priv->data->coef_div;
> > >
> > > if (priv->data->inverted)
> > > - *temp = ((m * reg) - b) / div;
> > > + *temp = ((m * sample) - b) / div;
> > > else
> > > - *temp = (b - (m * reg)) / div;
> > > + *temp = (b - (m * sample)) / div;
> > > return 0;
> > > }
> > >
> > > @@ -237,6 +267,19 @@ static const struct armada_thermal_data
> > > armada380_data = { .inverted = true,
> > > };
> > >
> > > +static const struct armada_thermal_data armada_ap806_data = {
> > > + .is_valid = armada_is_valid,
> > > + .init_sensor = armada_ap806_init_sensor,
> > > + .is_valid_bit = BIT(16),
> > > + .temp_shift = 0,
> > > + .temp_mask = 0x3ff,
> > > + .coef_b = -150000,
> >
> > Don't you expect any side effect by storing a negative value in a
> > unsigned variable?
>
> That is a fair question, I did not spot that.
>
> As other values are really close to 2^32 I don't know what is the best
> option for us in this case. Should I:
> - don't care?
> - use signed values? (dangerous IMHO)
> - use a union with a signed and an unsigned value? (problem moved to
> ->get_temp())
Another option is to use s64 type.
baruch
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch@tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -
^ permalink raw reply
* Re: [PATCH v2 2/2] media: coda: Add i.MX51 (CodaHx4) support
From: Fabio Estevam @ 2017-12-18 11:03 UTC (permalink / raw)
To: Philipp Zabel
Cc: linux-media, Mauro Carvalho Chehab, Rob Herring, Mark Rutland,
Fabio Estevam, Chris Healy, devicetree-u79uwXL29TY76Z2rM5mHXA,
Sascha Hauer
In-Reply-To: <20171218101629.31395-2-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
On Mon, Dec 18, 2017 at 8:16 AM, Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> Add support for the CodaHx4 VPU used on i.MX51.
>
> Decoding h.264, MPEG-4, and MPEG-2 video works, as well as encoding
> h.264. MPEG-4 encoding is not enabled, it currently produces visual
> artifacts.
>
> Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
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* Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
From: Stefan Mavrodiev @ 2017-12-18 11:00 UTC (permalink / raw)
To: Maxime Ripard
Cc: Stefan Mavrodiev, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Rob Herring,
Mark Rutland, Russell King, Chen-Yu Tsai,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM PORT, open list
In-Reply-To: <20171218092814.n5ptd5mhvo4nkjgq-ZC1Zs529Oq4@public.gmane.org>
On 12/18/2017 11:28 AM, Maxime Ripard wrote:
> On Mon, Dec 18, 2017 at 08:24:21AM +0200, Stefan Mavrodiev wrote:
>> On 12/15/2017 05:08 PM, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Thu, Dec 14, 2017 at 08:24:54AM +0200, Stefan Mavrodiev wrote:
>>>> On 12/13/2017 05:40 PM, Maxime Ripard wrote:
>>>>> Hi,
>>>>>
>>>>> On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote:
>>>>>> Allwinner A10/A13/A20 SoCs have pinmux for spi0
>>>>>> on port C. The patch adds these pins in the respective
>>>>>> dts includes.
>>>>>>
>>>>>> Signed-off-by: Stefan Mavrodiev <stefan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org>
>>>>> Do you have any boards that are using these?
>>>>>
>>>>> We won't merge that patch if there's no users for it.
>>>> A20-OLinuXino-Lime/Lime2 and A10-OLinuXino-Lime with spi flash.
>>>> For A13 we still doesn't have that option.
>>> If this bus is exposed on the headers, you can add those to the DT but
>>> leave them disabled if you want. Buf if there's no users of those
>>> nodes, our policy is not to merge them.
>> So basically I should resend the patch, enabling the those pins only for
>> sun4i and sun7i platform?
> I'm not quite sure what you mean, but you should do something like
> 77df9d66b0b1ad01c685fd6341ce501493899658
>
> Maxime
>
I guess, since this patch actually supports optional component, it
shouldn't be applied.
(This is already commented here:
https://patchwork.kernel.org/patch/10076721/ )
Thanks,
Stefan Mavrodiev
^ permalink raw reply
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