* [PATCH v3 08/20] ARM: dts: aspeed: Add clock phandle to GPIO
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
This enables a feature where the driver can debounce inputs.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 1 +
arch/arm/boot/dts/aspeed-g5.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 36cb66d8cc10..d2a82850b05b 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -144,6 +144,7 @@
reg = <0x1e780000 0x1000>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 220>;
+ clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 156b345ff20d..3a25fa48d4f6 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -187,6 +187,7 @@
reg = <0x1e780000 0x1000>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 220>;
+ clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
};
--
2.15.1
^ permalink raw reply related
* [PATCH v3 07/20] ARM: dts: aspeed: Add flash controller clocks
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++
2 files changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 2b1bb31ce390..36cb66d8cc10 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -55,6 +55,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-fmc";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
interrupts = <19>;
flash@0 {
@@ -70,6 +71,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-spi";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 95bb04e4cee2..156b345ff20d 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -55,6 +55,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
interrupts = <19>;
flash@0 {
@@ -80,6 +81,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
@@ -99,6 +101,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
+ clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
--
2.15.1
^ permalink raw reply related
* [PATCH v3 06/20] ARM: dts: aspeed: Add watchdog clocks
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++
2 files changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 57194d804051..2b1bb31ce390 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -177,11 +177,13 @@
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2400-wdt";
reg = <0x1e785000 0x1c>;
+ clocks = <&syscon ASPEED_CLK_APB>;
};
wdt2: watchdog@1e785020 {
compatible = "aspeed,ast2400-wdt";
reg = <0x1e785020 0x1c>;
+ clocks = <&syscon ASPEED_CLK_APB>;
};
vuart: serial@1e787000 {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index b6faaef2b1a7..95bb04e4cee2 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -219,16 +219,19 @@
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785000 0x20>;
+ clocks = <&syscon ASPEED_CLK_APB>;
};
wdt2: watchdog@1e785020 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785020 0x20>;
+ clocks = <&syscon ASPEED_CLK_APB>;
};
wdt3: watchdog@1e785040 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785040 0x20>;
+ clocks = <&syscon ASPEED_CLK_APB>;
status = "disabled";
};
--
2.15.1
^ permalink raw reply related
* [PATCH v3 05/20] ARM: dts: aspeed: Add MAC clocks
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
arch/arm/boot/dts/aspeed-g5.dtsi | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b938759f799e..57194d804051 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -90,6 +90,7 @@
compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
interrupts = <2>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
status = "disabled";
};
@@ -97,6 +98,7 @@
compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
reg = <0x1e680000 0x180>;
interrupts = <3>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 1af600b48475..b6faaef2b1a7 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -124,6 +124,7 @@
compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
interrupts = <2>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
status = "disabled";
};
@@ -131,6 +132,7 @@
compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e680000 0x180>;
interrupts = <3>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
status = "disabled";
};
--
2.15.1
^ permalink raw reply related
* [PATCH v3 04/20] ARM: dts: aspeed: Add proper clock references
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20171220032328.30584-1-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
This device tree will break existing kernels that do not have the clk
patches applied (no clocksource, as we don't know the speed of the APB
clock. You can boot if you pass a lpj value on the command line, but
won't have a uart).
Older device trees running with the newer kernel will function as well
as pre-4.16 kernels. That is, that some IP blocks (i2c, pwm/tach, adc)
will not work as the kernel lacks reset controller and clock enabling.
This is being changed as existing device trees use fixed-clocks in order
to boot without a clk driver. The newly added clk driver provides proper
clock support, including gating, so we move the device trees over to
properly request clocks.
The SCU compatible string is updated as the g4-scu string made it into
the tree before we decided on aspeed,astX000-<ip> as the format for the
strings. The old string will be removed from the bindings in a future
patch.
Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
---
v3:
- Add reset phandle to ADC node
v2:
- Add more detail to the commit message
adc reset
Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 103 ++++++++++++++++----------------------
arch/arm/boot/dts/aspeed-g5.dtsi | 105 ++++++++++++++++-----------------------
2 files changed, 84 insertions(+), 124 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 9422f9cb1e11..b938759f799e 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
+#include <dt-bindings/clock/aspeed-clock.h>
/ {
model = "Aspeed BMC";
@@ -106,47 +107,12 @@
ranges;
syscon: syscon@1e6e2000 {
- compatible = "aspeed,g4-scu", "syscon", "simple-mfd";
+ compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
-
- clk_clkin: clk_clkin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <48000000>;
- };
-
- clk_hpll: clk_hpll@70 {
- #clock-cells = <0>;
- compatible = "aspeed,g4-hpll-clock", "fixed-clock";
- reg = <0x70>;
- clocks = <&clk_clkin>;
- clock-frequency = <384000000>;
- };
-
- clk_ahb: clk_ahb@70 {
- #clock-cells = <0>;
- compatible = "aspeed,g4-ahb-clock", "fixed-clock";
- reg = <0x70>;
- clocks = <&clk_hpll>;
- clock-frequency = <192000000>;
- };
-
- clk_apb: clk_apb@8 {
- #clock-cells = <0>;
- compatible = "aspeed,g4-apb-clock", "fixed-clock";
- reg = <0x08>;
- clocks = <&clk_hpll>;
- clock-frequency = <48000000>;
- };
-
- clk_uart: clk_uart@2c{
- #clock-cells = <0>;
- compatible = "aspeed,g4-uart-clock", "fixed-clock";
- reg = <0x2c>;
- clock-frequency = <24000000>;
- };
+ #clock-cells = <1>;
+ #reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,g4-pinctrl";
@@ -156,7 +122,8 @@
adc: adc@1e6e9000 {
compatible = "aspeed,ast2400-adc";
reg = <0x1e6e9000 0xb0>;
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_ADC>;
#io-channel-cells = <1>;
status = "disabled";
};
@@ -181,7 +148,7 @@
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
interrupts = <16 17 18 35 36 37 38 39>;
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
clock-names = "PCLK";
};
@@ -190,7 +157,7 @@
reg = <0x1e783000 0x20>;
reg-shift = <2>;
interrupts = <9>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
no-loopback-test;
status = "disabled";
};
@@ -200,7 +167,7 @@
reg = <0x1e784000 0x20>;
reg-shift = <2>;
interrupts = <10>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
no-loopback-test;
status = "disabled";
};
@@ -219,8 +186,8 @@
compatible = "aspeed,ast2400-vuart";
reg = <0x1e787000 0x40>;
reg-shift = <2>;
- interrupts = <10>;
- clocks = <&clk_uart>;
+ interrupts = <8>;
+ clocks = <&syscon ASPEED_CLK_APB>;
no-loopback-test;
status = "disabled";
};
@@ -265,7 +232,7 @@
reg = <0x1e78d000 0x20>;
reg-shift = <2>;
interrupts = <32>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
no-loopback-test;
status = "disabled";
};
@@ -275,7 +242,7 @@
reg = <0x1e78e000 0x20>;
reg-shift = <2>;
interrupts = <33>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
no-loopback-test;
status = "disabled";
};
@@ -285,7 +252,7 @@
reg = <0x1e78f000 0x20>;
reg-shift = <2>;
interrupts = <34>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
no-loopback-test;
status = "disabled";
};
@@ -316,7 +283,8 @@
reg = <0x40 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <0>;
interrupt-parent = <&i2c_ic>;
@@ -331,7 +299,8 @@
reg = <0x80 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <1>;
interrupt-parent = <&i2c_ic>;
@@ -346,7 +315,8 @@
reg = <0xc0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <2>;
interrupt-parent = <&i2c_ic>;
@@ -362,7 +332,8 @@
reg = <0x100 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <3>;
interrupt-parent = <&i2c_ic>;
@@ -378,7 +349,8 @@
reg = <0x140 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <4>;
interrupt-parent = <&i2c_ic>;
@@ -394,7 +366,8 @@
reg = <0x180 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <5>;
interrupt-parent = <&i2c_ic>;
@@ -410,7 +383,8 @@
reg = <0x1c0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <6>;
interrupt-parent = <&i2c_ic>;
@@ -426,7 +400,8 @@
reg = <0x300 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <7>;
interrupt-parent = <&i2c_ic>;
@@ -442,7 +417,8 @@
reg = <0x340 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <8>;
interrupt-parent = <&i2c_ic>;
@@ -458,7 +434,8 @@
reg = <0x380 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <9>;
interrupt-parent = <&i2c_ic>;
@@ -474,7 +451,8 @@
reg = <0x3c0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <10>;
interrupt-parent = <&i2c_ic>;
@@ -490,7 +468,8 @@
reg = <0x400 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <11>;
interrupt-parent = <&i2c_ic>;
@@ -506,7 +485,8 @@
reg = <0x440 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <12>;
interrupt-parent = <&i2c_ic>;
@@ -522,7 +502,8 @@
reg = <0x480 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <13>;
interrupt-parent = <&i2c_ic>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 069f13df19d1..1af600b48475 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
+#include <dt-bindings/clock/aspeed-clock.h>
/ {
model = "Aspeed BMC";
@@ -140,55 +141,18 @@
ranges;
syscon: syscon@1e6e2000 {
- compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
+ compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
-
- clk_clkin: clk_clkin@70 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-clkin-clock", "fixed-clock";
- reg = <0x70>;
- clock-frequency = <24000000>;
- };
-
- clk_hpll: clk_hpll@24 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-hpll-clock", "fixed-clock";
- reg = <0x24>;
- clocks = <&clk_clkin>;
- clock-frequency = <792000000>;
- };
-
- clk_ahb: clk_ahb@70 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-ahb-clock", "fixed-clock";
- reg = <0x70>;
- clocks = <&clk_hpll>;
- clock-frequency = <198000000>;
- };
-
- clk_apb: clk_apb@8 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-apb-clock", "fixed-clock";
- reg = <0x08>;
- clocks = <&clk_hpll>;
- clock-frequency = <24750000>;
- };
-
- clk_uart: clk_uart@2c {
- #clock-cells = <0>;
- compatible = "aspeed,uart-clock", "fixed-clock";
- reg = <0x2c>;
- clock-frequency = <24000000>;
- };
+ #clock-cells = <1>;
+ #reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,g5-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
};
-
};
gfx: display@1e6e6000 {
@@ -200,7 +164,8 @@
adc: adc@1e6e9000 {
compatible = "aspeed,ast2500-adc";
reg = <0x1e6e9000 0xb0>;
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_ADC>;
#io-channel-cells = <1>;
status = "disabled";
};
@@ -225,7 +190,7 @@
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
interrupts = <16 17 18 35 36 37 38 39>;
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
clock-names = "PCLK";
};
@@ -234,7 +199,7 @@
reg = <0x1e783000 0x20>;
reg-shift = <2>;
interrupts = <9>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
no-loopback-test;
status = "disabled";
};
@@ -244,7 +209,7 @@
reg = <0x1e784000 0x20>;
reg-shift = <2>;
interrupts = <10>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
no-loopback-test;
status = "disabled";
};
@@ -269,8 +234,8 @@
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787000 0x40>;
reg-shift = <2>;
- interrupts = <10>;
- clocks = <&clk_uart>;
+ interrupts = <8>;
+ clocks = <&syscon ASPEED_CLK_APB>;
no-loopback-test;
status = "disabled";
};
@@ -317,7 +282,7 @@
reg = <0x1e78d000 0x20>;
reg-shift = <2>;
interrupts = <32>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
no-loopback-test;
status = "disabled";
};
@@ -327,7 +292,7 @@
reg = <0x1e78e000 0x20>;
reg-shift = <2>;
interrupts = <33>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
no-loopback-test;
status = "disabled";
};
@@ -337,7 +302,7 @@
reg = <0x1e78f000 0x20>;
reg-shift = <2>;
interrupts = <34>;
- clocks = <&clk_uart>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
no-loopback-test;
status = "disabled";
};
@@ -368,7 +333,8 @@
reg = <0x40 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <0>;
interrupt-parent = <&i2c_ic>;
@@ -383,7 +349,8 @@
reg = <0x80 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <1>;
interrupt-parent = <&i2c_ic>;
@@ -398,7 +365,8 @@
reg = <0xc0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <2>;
interrupt-parent = <&i2c_ic>;
@@ -414,7 +382,8 @@
reg = <0x100 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <3>;
interrupt-parent = <&i2c_ic>;
@@ -430,7 +399,8 @@
reg = <0x140 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <4>;
interrupt-parent = <&i2c_ic>;
@@ -446,7 +416,8 @@
reg = <0x180 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <5>;
interrupt-parent = <&i2c_ic>;
@@ -462,7 +433,8 @@
reg = <0x1c0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <6>;
interrupt-parent = <&i2c_ic>;
@@ -478,7 +450,8 @@
reg = <0x300 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <7>;
interrupt-parent = <&i2c_ic>;
@@ -494,7 +467,8 @@
reg = <0x340 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <8>;
interrupt-parent = <&i2c_ic>;
@@ -510,7 +484,8 @@
reg = <0x380 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <9>;
interrupt-parent = <&i2c_ic>;
@@ -526,7 +501,8 @@
reg = <0x3c0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <10>;
interrupt-parent = <&i2c_ic>;
@@ -542,7 +518,8 @@
reg = <0x400 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <11>;
interrupt-parent = <&i2c_ic>;
@@ -558,7 +535,8 @@
reg = <0x440 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <12>;
interrupt-parent = <&i2c_ic>;
@@ -574,7 +552,8 @@
reg = <0x480 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <13>;
interrupt-parent = <&i2c_ic>;
--
2.15.1
--
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^ permalink raw reply related
* [PATCH v3 03/20] ARM: dts: aspeed: Add LPC and child devices
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20171220032328.30584-1-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
From: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
Ensure the ordering is correct and add all of the children in the SoC
device trees for the ast2400 and ast2500.
Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
Reviewed-by: Cédric Le Goater <clg-Bxea+6Xhats@public.gmane.org>
Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
---
v3:
- Fix ast2400 compatible string
---
arch/arm/boot/dts/aspeed-g4.dtsi | 35 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 27 +++++++++++++++++----------
2 files changed, 52 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 45d815a86d42..9422f9cb1e11 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -225,6 +225,41 @@
status = "disabled";
};
+ lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2400-lpc", "simple-mfd";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
+
+ lpc_bmc: lpc-bmc@0 {
+ compatible = "aspeed,ast2400-lpc-bmc";
+ reg = <0x0 0x80>;
+ };
+
+ lpc_host: lpc-host@80 {
+ compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
+ reg = <0x80 0x1e0>;
+ reg-io-width = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80 0x1e0>;
+
+ lpc_ctrl: lpc-ctrl@0 {
+ compatible = "aspeed,ast2400-lpc-ctrl";
+ reg = <0x0 0x80>;
+ status = "disabled";
+ };
+
+ lhc: lhc@20 {
+ compatible = "aspeed,ast2400-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
+ };
+ };
+ };
+
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 5c4ecdba3a6b..069f13df19d1 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -265,6 +265,16 @@
status = "disabled";
};
+ vuart: serial@1e787000 {
+ compatible = "aspeed,ast2500-vuart";
+ reg = <0x1e787000 0x40>;
+ reg-shift = <2>;
+ interrupts = <10>;
+ clocks = <&clk_uart>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
lpc: lpc@1e789000 {
compatible = "aspeed,ast2500-lpc", "simple-mfd";
reg = <0x1e789000 0x1000>;
@@ -288,6 +298,13 @@
reg-io-width = <4>;
+ lpc_ctrl: lpc-ctrl@0 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x0 0x80>;
+ status = "disabled";
+ };
+
+
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
@@ -295,16 +312,6 @@
};
};
- vuart: serial@1e787000 {
- compatible = "aspeed,ast2500-vuart";
- reg = <0x1e787000 0x40>;
- reg-shift = <2>;
- interrupts = <10>;
- clocks = <&clk_uart>;
- no-loopback-test;
- status = "disabled";
- };
-
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
--
2.15.1
--
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^ permalink raw reply related
* [PATCH v3 02/20] dt-bindings: gpio: Add ASPEED constants
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
These are used to by the device tree to map pin numbers to constants
required by the GPIO bindings.
Signed-off-by: Joel Stanley <joel@jms.id.au>
--
v3:
- Remove dtsi includes from this patch, they will come later
---
include/dt-bindings/gpio/aspeed-gpio.h | 49 ++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 include/dt-bindings/gpio/aspeed-gpio.h
diff --git a/include/dt-bindings/gpio/aspeed-gpio.h b/include/dt-bindings/gpio/aspeed-gpio.h
new file mode 100644
index 000000000000..56fc4889b2c4
--- /dev/null
+++ b/include/dt-bindings/gpio/aspeed-gpio.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header provides constants for binding aspeed,*-gpio.
+ *
+ * The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H
+#define _DT_BINDINGS_GPIO_ASPEED_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define ASPEED_GPIO_PORT_A 0
+#define ASPEED_GPIO_PORT_B 1
+#define ASPEED_GPIO_PORT_C 2
+#define ASPEED_GPIO_PORT_D 3
+#define ASPEED_GPIO_PORT_E 4
+#define ASPEED_GPIO_PORT_F 5
+#define ASPEED_GPIO_PORT_G 6
+#define ASPEED_GPIO_PORT_H 7
+#define ASPEED_GPIO_PORT_I 8
+#define ASPEED_GPIO_PORT_J 9
+#define ASPEED_GPIO_PORT_K 10
+#define ASPEED_GPIO_PORT_L 11
+#define ASPEED_GPIO_PORT_M 12
+#define ASPEED_GPIO_PORT_N 13
+#define ASPEED_GPIO_PORT_O 14
+#define ASPEED_GPIO_PORT_P 15
+#define ASPEED_GPIO_PORT_Q 16
+#define ASPEED_GPIO_PORT_R 17
+#define ASPEED_GPIO_PORT_S 18
+#define ASPEED_GPIO_PORT_T 19
+#define ASPEED_GPIO_PORT_U 20
+#define ASPEED_GPIO_PORT_V 21
+#define ASPEED_GPIO_PORT_W 22
+#define ASPEED_GPIO_PORT_X 23
+#define ASPEED_GPIO_PORT_Y 24
+#define ASPEED_GPIO_PORT_Z 25
+#define ASPEED_GPIO_PORT_AA 26
+#define ASPEED_GPIO_PORT_AB 27
+#define ASPEED_GPIO_PORT_AC 28
+
+#define ASPEED_GPIO(port, offset) \
+ ((ASPEED_GPIO_PORT_##port * 8) + offset)
+
+#endif
--
2.15.1
^ permalink raw reply related
* [PATCH v3 01/20] dt-bindings: clock: Add ASPEED constants
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20171220032328.30584-1-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
These will be used by the clock driver. This commit is included so
the tree will build without the clock series being applied.
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
---
v3:
- Clarify that the clock defines will be merged as part of the dt
changes, so that the device tree merge will not depend on the clock
tree
v2:
- remove NUM_CLKS define. There's no need for it to be part of ABI
---
include/dt-bindings/clock/aspeed-clock.h | 52 ++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 include/dt-bindings/clock/aspeed-clock.h
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
new file mode 100644
index 000000000000..d3558d897a4d
--- /dev/null
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+#ifndef DT_BINDINGS_ASPEED_CLOCK_H
+#define DT_BINDINGS_ASPEED_CLOCK_H
+
+#define ASPEED_CLK_GATE_ECLK 0
+#define ASPEED_CLK_GATE_GCLK 1
+#define ASPEED_CLK_GATE_MCLK 2
+#define ASPEED_CLK_GATE_VCLK 3
+#define ASPEED_CLK_GATE_BCLK 4
+#define ASPEED_CLK_GATE_DCLK 5
+#define ASPEED_CLK_GATE_REFCLK 6
+#define ASPEED_CLK_GATE_USBPORT2CLK 7
+#define ASPEED_CLK_GATE_LCLK 8
+#define ASPEED_CLK_GATE_USBUHCICLK 9
+#define ASPEED_CLK_GATE_D1CLK 10
+#define ASPEED_CLK_GATE_YCLK 11
+#define ASPEED_CLK_GATE_USBPORT1CLK 12
+#define ASPEED_CLK_GATE_UART1CLK 13
+#define ASPEED_CLK_GATE_UART2CLK 14
+#define ASPEED_CLK_GATE_UART5CLK 15
+#define ASPEED_CLK_GATE_ESPICLK 16
+#define ASPEED_CLK_GATE_MAC1CLK 17
+#define ASPEED_CLK_GATE_MAC2CLK 18
+#define ASPEED_CLK_GATE_RSACLK 19
+#define ASPEED_CLK_GATE_UART3CLK 20
+#define ASPEED_CLK_GATE_UART4CLK 21
+#define ASPEED_CLK_GATE_SDCLKCLK 22
+#define ASPEED_CLK_GATE_LHCCLK 23
+#define ASPEED_CLK_HPLL 24
+#define ASPEED_CLK_AHB 25
+#define ASPEED_CLK_APB 26
+#define ASPEED_CLK_UART 27
+#define ASPEED_CLK_SDIO 28
+#define ASPEED_CLK_ECLK 29
+#define ASPEED_CLK_ECLK_MUX 30
+#define ASPEED_CLK_LHCLK 31
+#define ASPEED_CLK_MAC 32
+#define ASPEED_CLK_BCLK 33
+#define ASPEED_CLK_MPLL 34
+
+#define ASPEED_RESET_XDMA 0
+#define ASPEED_RESET_MCTP 1
+#define ASPEED_RESET_ADC 2
+#define ASPEED_RESET_JTAG_MASTER 3
+#define ASPEED_RESET_MIC 4
+#define ASPEED_RESET_PWM 5
+#define ASPEED_RESET_PCIVGA 6
+#define ASPEED_RESET_I2C 7
+#define ASPEED_RESET_AHB 8
+
+#endif
--
2.15.1
--
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^ permalink raw reply related
* [PATCH v3 00/19] ARM: dts: aspeed: updates and new machines
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
This series of device tree patches for the ASPEED BMC machines
moves all systems to use the soon to be merged clk driver, and
updates machines to use all of the drivers we have upstream.
v3: Address review from Rob and Cedric
- Move aspeed-gpio.h usage out into the patches where use of the GPIO
is added
- Clarify that the aspeed-clock.h patch will be merged as part of
the device tree tree. This is to ensure we don't depend on the clk
tree for building.
- Fix duplicate flash controller nodes in Romulus
v2: Address review from Arnd
- Remove NUM_CLKS from dt header
- Send VUART patch as a fix, drop it from this series
- Add reasoning for breaking old kernel in the 'proper clock
references' patch
In addition it adds three new OpenBMC systems that have been developed
in the OpenBMC kernel tree over the past year: two Power9 OpenPower
systems, and a port by Google to a Quanta x86 server.
I have boot tested these on Romulus and Palmetto, as well as boot tested
all device trees in Qemu.
Please review the boards you are familiar with. I will merge these in to
the ASPEED ARM SoC tree for inclusion in 4.16.
Andrew Jeffery (1):
ARM: dts: aspeed: Add LPC and child devices
Joel Stanley (16):
dt-bindings: clock: Add ASPEED constants
dt-bindings: gpio: Add ASPEED constants
ARM: dts: aspeed: Add proper clock references
ARM: dts: aspeed: Add MAC clocks
ARM: dts: aspeed: Add watchdog clocks
ARM: dts: aspeed: Add flash controller clocks
ARM: dts: aspeed: Add clock phandle to GPIO
ARM: dts: aspeed: Add PWM and tachometer node
ARM: dts: aspeed: Add LPC Snoop device
ARM: dts: aspeed: Remove skeleton.dtsi
ARM: dts: aspeed: Update license headers
ARM: dts: Add OpenBMC flash layout
ARM: dts: aspeed: Sort ASPEED entries in makefile
ARM: dts: aspeed: Add Witherspoon BMC machine
ARM: dts: aspeed-romulus: Update Romulus system
ARM: dts: aspeed-plametto: Add flash layout
Rick Altherr (1):
ARM: dts: aspeed: Add Qanta Q71L BMC machine
Xo Wang (1):
ARM: dts: aspeed: Add Ingrasys Zaius BMC machine
arch/arm/boot/dts/Makefile | 8 +-
arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +-
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 3 +-
arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 157 ++++++-
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 548 +++++++++++++++++++++++
arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 426 ++++++++++++++++++
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 458 +++++++++++++++++++
arch/arm/boot/dts/aspeed-g4.dtsi | 163 ++++---
arch/arm/boot/dts/aspeed-g5.dtsi | 154 ++++---
arch/arm/boot/dts/openbmc-flash-layout.dtsi | 32 ++
include/dt-bindings/clock/aspeed-clock.h | 52 +++
include/dt-bindings/gpio/aspeed-gpio.h | 49 ++
12 files changed, 1905 insertions(+), 147 deletions(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
create mode 100644 arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
create mode 100644 arch/arm/boot/dts/openbmc-flash-layout.dtsi
create mode 100644 include/dt-bindings/clock/aspeed-clock.h
create mode 100644 include/dt-bindings/gpio/aspeed-gpio.h
--
2.15.1
^ permalink raw reply
* Re: [PATCH v2 18/19] ARM: dts: aspeed-romulus: Update Romulus system
From: Joel Stanley @ 2017-12-20 3:22 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU, Benjamin Herrenschmidt,
Jeremy Kerr, devicetree, Linux ARM, Linux Kernel Mailing List,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <b8e80861-88c4-da87-a201-ca2eefaa5a94-Bxea+6Xhats@public.gmane.org>
On Mon, Dec 18, 2017 at 8:02 PM, Cédric Le Goater <clg-Bxea+6Xhats@public.gmane.org> wrote:
>> +};
>> +
>> +&fmc {
>> + status = "okay";
>> +
>> + flash@0 {
>> + status = "okay";
>> + label = "pnor";
>> + m25p,fast-read;
>> +#include "openbmc-flash-layout.dtsi"
>> + };
>> +};
>> +
>> +&spi1 {
>> + status = "okay";
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_spi1_default>;
>> +
>> + flash@0 {
>> + status = "okay";
>> + label = "pnor";
>> + m25p,fast-read;
>> };
>> };
>
>
> hmm, the fmc and spi1 bindings were already added in commit 1142aea9ff9d.
>
>
>> @@ -38,6 +101,7 @@
>> status = "okay";
>> m25p,fast-read;
>> label = "bmc";
>> +#include "openbmc-flash-layout.dtsi"
>
>
> This looks like an extra "fmc" node ?
You're right. It still built and booted too. Good catch.
Cheers,
Joel
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^ permalink raw reply
* Re: [PATCH v2 03/19] ARM: dts: aspeed: Add LPC and child devices
From: Joel Stanley @ 2017-12-20 3:21 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU, Benjamin Herrenschmidt,
Jeremy Kerr, devicetree, Linux ARM, Linux Kernel Mailing List,
linux-aspeed
In-Reply-To: <f08188a0-a6dd-a445-340c-eee1ca335865@kaod.org>
j
On Mon, Dec 18, 2017 at 7:55 PM, Cédric Le Goater <clg@kaod.org> wrote:
> On 12/15/2017 07:24 AM, Joel Stanley wrote:
>> From: Andrew Jeffery <andrew@aj.id.au>
>>
>> Ensure the ordering is correct and add all of the children in the SoC
>> device trees for the ast2400 and ast2500.
>>
>> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>> ---
>> arch/arm/boot/dts/aspeed-g4.dtsi | 35 +++++++++++++++++++++++++++++++++++
>> arch/arm/boot/dts/aspeed-g5.dtsi | 27 +++++++++++++++++----------
>> 2 files changed, 52 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
>> index 100d092e6c07..a3bc5da7d42c 100644
>> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
>> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
>> @@ -226,6 +226,41 @@
>> status = "disabled";
>> };
>>
>> + lpc: lpc@1e789000 {
>> + compatible = "aspeed,ast2400-lpc", "simple-mfd";
>> + reg = <0x1e789000 0x1000>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x1e789000 0x1000>;
>> +
>> + lpc_bmc: lpc-bmc@0 {
>> + compatible = "aspeed,ast2400-lpc-bmc";
>> + reg = <0x0 0x80>;
>> + };
>> +
>> + lpc_host: lpc-host@80 {
>> + compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
>> + reg = <0x80 0x1e0>;
>> + reg-io-width = <4>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x80 0x1e0>;
>> +
>> + lpc_ctrl: lpc-ctrl@0 {
>> + compatible = "aspeed,ast2400-lpc-ctrl";
>> + reg = <0x0 0x80>;
>> + status = "disabled";
>> + };
>> +
>> + lhc: lhc@20 {
>> + compatible = "aspeed,ast2500-lhc";
>
> aspeed,ast2400-lhc
>
> The layout of the registers are the same but there a couple of differences
> in the bit definitions between the two SoCs.
>
> a part from that :
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
Good catch. Fixed in v3.
Cheers,
Joel
^ permalink raw reply
* Re: [PATCH v2 10/19] ARM: dts: aspeed: Add LPC Snoop device
From: Joel Stanley @ 2017-12-20 3:21 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU, Benjamin Herrenschmidt,
Jeremy Kerr, devicetree, Linux ARM, Linux Kernel Mailing List,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <c5ef27de-34c1-f5e9-e4ae-e2709b004677-Bxea+6Xhats@public.gmane.org>
On Mon, Dec 18, 2017 at 7:46 PM, Cédric Le Goater <clg-Bxea+6Xhats@public.gmane.org> wrote:
> On 12/15/2017 07:24 AM, Joel Stanley wrote:
>> LPC snoop hardware on the ASPEED BMC, used for monitoring
>> host I/O port activity.
>>
>> Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
>> ---
>> arch/arm/boot/dts/aspeed-g4.dtsi | 7 +++++++
>> arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++
>> 2 files changed, 13 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
>> index f6fee40c04c0..b3580f37f507 100644
>> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
>> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
>> @@ -236,6 +236,13 @@
>> status = "disabled";
>> };
>>
>> + lpc_snoop: lpc-snoop@0 {
>> + compatible = "aspeed,ast2500-lpc-snoop";
>
> it should be :
>
> aspeed,ast2400-lpc-snoop
>
> a part from that :
>
> Reviewed-by: Cédric Le Goater <clg-Bxea+6Xhats@public.gmane.org>
Fixed in v3.
Cheers,
Joel
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^ permalink raw reply
* Re: [PATCH] PCI: Mediatek: clear irq status after irq dispathed to avoid reentry
From: Ryder Lee @ 2017-12-20 3:08 UTC (permalink / raw)
To: honghui.zhang-NuS5LvNUpcJWk0Htik3J/w
Cc: bhelgaas-hpIqsD4AKlfQT0dZR+AlfA,
matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-pci-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w,
eddie.huang-NuS5LvNUpcJWk0Htik3J/w,
hongkun.cao-NuS5LvNUpcJWk0Htik3J/w,
youlin.pei-NuS5LvNUpcJWk0Htik3J/w, yong.wu-NuS5LvNUpcJWk0Htik3J/w,
yt.shen-NuS5LvNUpcJWk0Htik3J/w, sean.wang-NuS5LvNUpcJWk0Htik3J/w,
xinping.qian-NuS5LvNUpcJWk0Htik3J/w
In-Reply-To: <1513738334-26213-1-git-send-email-honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Wed, 2017-12-20 at 10:52 +0800, honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote:
> From: Honghui Zhang <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>
> There maybe a same irq reentry scenario after irq received in current
> irq handle flow:
> EP device PCIe host driver EP driver
> 1. issue an irq
> 2. received irq
> 3. clear irq status
> 4. dispatch irq
> 5. clear irq source
> The irq status was not successfully cleared at step 2 since the irq
> source was not cleared yet. So the PCIe host driver may receive the
> same irq after step 5. Then there's an irq reentry occurred.
> Even worse, if the reentry irq was not an irq that EP driver expected,
> it may not handle the irq. Then we may run into the dead loop from
> step 2 to step 4.
> Clear the irq status after irq have been dispatched to avoid the irq
> reentry.
>
> Signed-off-by: Honghui Zhang <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> drivers/pci/host/pcie-mediatek.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
> index db93efd..3248771 100644
> --- a/drivers/pci/host/pcie-mediatek.c
> +++ b/drivers/pci/host/pcie-mediatek.c
> @@ -605,11 +605,11 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
>
> while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) {
> for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
> - /* Clear the INTx */
> - writel(1 << bit, port->base + PCIE_INT_STATUS);
> virq = irq_find_mapping(port->irq_domain,
> bit - INTX_SHIFT);
> generic_handle_irq(virq);
> + /* Clear the INTx */
> + writel(1 << bit, port->base + PCIE_INT_STATUS);
> }
> }
>
> @@ -619,10 +619,10 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
>
> while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
> for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
> - /* Clear the MSI */
> - writel(1 << bit, port->base + PCIE_IMSI_STATUS);
> virq = irq_find_mapping(port->msi_domain, bit);
> generic_handle_irq(virq);
> + /* Clear the MSI */
> + writel(1 << bit, port->base + PCIE_IMSI_STATUS);
> }
> }
> /* Clear MSI interrupt status */
Acked-by: Ryder Lee <ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Thanks.
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^ permalink raw reply
* RE: [PATCH v5 1/2] dt-bindings: misc: Add DT bindings to xlnx_vcu driver
From: Dhaval Rajeshbhai Shah @ 2017-12-20 3:00 UTC (permalink / raw)
To: Rob Herring
Cc: arnd-r2nGTMty4D4@public.gmane.org,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org,
rdunlap-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org, Hyun Kwon
In-Reply-To: <20171219230953.bj5pbo535bzszant@rob-hp-laptop>
Hi Rob,
> -----Original Message-----
> From: Rob Herring [mailto:robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> Sent: Tuesday, December 19, 2017 3:10 PM
> To: Dhaval Rajeshbhai Shah <DSHAH-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> Cc: arnd-r2nGTMty4D4@public.gmane.org; gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org; rdunlap-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org;
> mark.rutland-5wv7dgnIgG8@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-
> kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org; Hyun Kwon
> <hyunk-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>; Dhaval Rajeshbhai Shah <DSHAH-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> Subject: Re: [PATCH v5 1/2] dt-bindings: misc: Add DT bindings to xlnx_vcu
> driver
>
> On Sun, Dec 17, 2017 at 10:15:31PM -0800, Dhaval Shah wrote:
> > Add Device Tree binding document for logicoreIP. This logicoreIP
> > provides the isolation between the processing system and programmable
> > logic. Also provides the clock related information.
> >
> > Signed-off-by: Dhaval Shah <dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> > ---
> > Chnages since v5:
> > No Changes.
> > Chnages since v4:
> > No Changes.
> > Chnages since v3:
> > * Use "dt-bindings: misc: ..." for the subject.
> > Changes since v2:
> > * Describe the h/w
> > * compatible string is updated to make it more specific
> > based on the logicoreIP version.
> > * Removed that encoder and decoder child nodes and relatd properties as
> that
> > will be a separate driver and dts nodes. other team is working on that.
> > * Updated to use as a single driver.
> >
> > .../devicetree/bindings/misc/xlnx,vcu.txt | 31 ++++++++++++++++++++++
> > 1 file changed, 31 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/misc/xlnx,vcu.txt
>
> Please add Reviewed-by tags when posting new versions.
>
> Rob
Sure. I will add this tag in the next version of patch.
Thanks & Regards,
Dhaval
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^ permalink raw reply
* Re: [PATCH v2] arm64: dts: ls1088a: Add USB support
From: Shawn Guo @ 2017-12-20 2:52 UTC (permalink / raw)
To: Yinbo Zhu
Cc: Rob Herring, Mark Rutland, Catalin Marinas ), Will Deacon ),
Harninder Rai, Raghav Dogra, Ashish Kumar, Andy Tang,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
open list
In-Reply-To: <VI1PR04MB1262C44016CE4ECB8902E7E7E9330-mr6QIVyDiCGbtYzA8xQqo89NdZoXdze2vxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
On Thu, Dec 07, 2017 at 07:33:28AM +0000, Yinbo Zhu wrote:
> Hi shawn guo,
>
> If my patch has no other issue,
> Can you help me push it to upstream.
Are you talking about v4 patch? First of all, I cannot find v4 in
my mailbox. That said, it seems you did not send the patch to me.
Secondly, by checking the patch on patchwork, the usb nodes in
fsl-ls1088a-rdb.dts do not sorted alphabetically in label name.
Shawn
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^ permalink raw reply
* [PATCH] PCI: Mediatek: clear irq status after irq dispathed to avoid reentry
From: honghui.zhang @ 2017-12-20 2:52 UTC (permalink / raw)
To: bhelgaas, matthias.bgg, linux-arm-kernel, linux-mediatek,
linux-pci, linux-kernel, devicetree, yingjoe.chen, eddie.huang,
ryder.lee
Cc: honghui.zhang, hongkun.cao, youlin.pei, yong.wu, yt.shen,
sean.wang, xinping.qian
From: Honghui Zhang <honghui.zhang@mediatek.com>
There maybe a same irq reentry scenario after irq received in current
irq handle flow:
EP device PCIe host driver EP driver
1. issue an irq
2. received irq
3. clear irq status
4. dispatch irq
5. clear irq source
The irq status was not successfully cleared at step 2 since the irq
source was not cleared yet. So the PCIe host driver may receive the
same irq after step 5. Then there's an irq reentry occurred.
Even worse, if the reentry irq was not an irq that EP driver expected,
it may not handle the irq. Then we may run into the dead loop from
step 2 to step 4.
Clear the irq status after irq have been dispatched to avoid the irq
reentry.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
---
drivers/pci/host/pcie-mediatek.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
index db93efd..3248771 100644
--- a/drivers/pci/host/pcie-mediatek.c
+++ b/drivers/pci/host/pcie-mediatek.c
@@ -605,11 +605,11 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) {
for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
- /* Clear the INTx */
- writel(1 << bit, port->base + PCIE_INT_STATUS);
virq = irq_find_mapping(port->irq_domain,
bit - INTX_SHIFT);
generic_handle_irq(virq);
+ /* Clear the INTx */
+ writel(1 << bit, port->base + PCIE_INT_STATUS);
}
}
@@ -619,10 +619,10 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
- /* Clear the MSI */
- writel(1 << bit, port->base + PCIE_IMSI_STATUS);
virq = irq_find_mapping(port->msi_domain, bit);
generic_handle_irq(virq);
+ /* Clear the MSI */
+ writel(1 << bit, port->base + PCIE_IMSI_STATUS);
}
}
/* Clear MSI interrupt status */
--
2.6.4
^ permalink raw reply related
* Re: [v7, 3/3] ARM: dts: imx6qdl.dtsi/imx6ul.dtsi: add "fsl, imx6q-snvs-lpgpr" node
From: Shawn Guo @ 2017-12-20 2:46 UTC (permalink / raw)
To: Maciej S. Szmigiero
Cc: Oleksij Rempel, devicetree-u79uwXL29TY76Z2rM5mHXA,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Mark Rutland, Maxime Ripard,
Rob Herring, Srinivas Kandagatla, Guy Shapiro, Stefan Wahren
In-Reply-To: <cfd53377-437a-98d3-1a0e-1123495a35ee-APzI5cXaD1zVlRWJc41N0YvC60bnQu0Y@public.gmane.org>
On Mon, Dec 11, 2017 at 11:31:52PM +0100, Maciej S. Szmigiero wrote:
> On 20.06.2017 09:09, Oleksij Rempel wrote:
> > This node is for Low Power General Purpose Register which can
> > be used as Non-Volatile Storage.
> >
> > Signed-off-by: Oleksij Rempel <o.rempel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> > ---
> > arch/arm/boot/dts/imx6qdl.dtsi | 4 ++++
> > arch/arm/boot/dts/imx6ul.dtsi | 4 ++++
> > 2 files changed, 8 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> > index e426faa9c243..94e992558238 100644
> (..)
>
> FYI: It looks to me that while the driver itself from this series was
> picked up and eventually reached Linus' tree this DT change was
> forgotten, since I can't find in any tree (or am I not looking at the
> right place?).
Thanks for reminding. I just updated the subject as below and applied
the patch.
ARM: dts: imx6: add snvs-lpgpr node
Shawn
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^ permalink raw reply
* Re: [PATCH v4 04/36] nds32: Kernel booting and initialization
From: Greentime Hu @ 2017-12-20 2:35 UTC (permalink / raw)
To: Randy Dunlap
Cc: Greentime, Linux Kernel Mailing List, Arnd Bergmann, linux-arch,
Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring, netdev,
Vincent Chen, DTML, Al Viro, David Howells, Will Deacon,
Daniel Lezcano, linux-serial, Geert Uytterhoeven, Linus Walleij,
Mark Rutland, Greg KH
In-Reply-To: <78afd442-4482-f104-746e-5984214658ee@infradead.org>
2017-12-20 6:01 GMT+08:00 Randy Dunlap <rdunlap@infradead.org>:
> On 12/17/2017 10:46 PM, Greentime Hu wrote:
>> From: Greentime Hu <greentime@andestech.com>
>>
>> This patch includes the kernel startup code. It can get dtb pointer
>> passed from bootloader. It will create a temp mapping by tlb
>> instructions at beginning and goto start_kernel.
>>
>> Signed-off-by: Vincent Chen <vincentc@andestech.com>
>> Signed-off-by: Greentime Hu <greentime@andestech.com>
>> ---
>> arch/nds32/kernel/head.S | 189 ++++++++++++++++++++++
>> arch/nds32/kernel/setup.c | 383 +++++++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 572 insertions(+)
>> create mode 100644 arch/nds32/kernel/head.S
>> create mode 100644 arch/nds32/kernel/setup.c
>>
>
>> diff --git a/arch/nds32/kernel/setup.c b/arch/nds32/kernel/setup.c
>> new file mode 100644
>> index 0000000..7718c58
>> --- /dev/null
>> +++ b/arch/nds32/kernel/setup.c
>> @@ -0,0 +1,383 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (C) 2005-2017 Andes Technology Corporation
>> +
>
> [snip]
>
>> +struct cache_info L1_cache_info[2];
>> +static void __init dump_cpu_info(int cpu)
>> +{
>> + int i, p = 0;
>> + char str[sizeof(hwcap_str) + 16];
>> +
>> + for (i = 0; hwcap_str[i]; i++) {
>> + if (elf_hwcap & (1 << i)) {
>> + sprintf(str + p, "%s ", hwcap_str[i]);
>> + p += strlen(hwcap_str[i]) + 1;
>> + }
>> + }
>> +
>> + pr_info("CPU%d Featuretures: %s\n", cpu, str);
>
> Features:
>
Thanks Randy. I will fix this typo.
^ permalink raw reply
* Re: [PATCH v4 25/36] nds32: Miscellaneous header files
From: Greentime Hu @ 2017-12-20 2:34 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Greentime, Linux Kernel Mailing List, linux-arch, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Networking, Vincent Chen,
DTML, Al Viro, David Howells, Will Deacon, Daniel Lezcano,
linux-serial-u79uwXL29TY76Z2rM5mHXA, Geert Uytterhoeven,
Linus Walleij, Mark Rutland, Greg KH, Guo Ren
In-Reply-To: <CAK8P3a3Ofczq1DrQEcEcP1fZrgyeOLpFDwgd7uMZ4H0NpHs+wg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-12-19 17:54 GMT+08:00 Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>:
> On Tue, Dec 19, 2017 at 6:34 AM, Greentime Hu <green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> Hi, Arnd:
>>
>> 2017-12-18 19:13 GMT+08:00 Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>:
>>> On Mon, Dec 18, 2017 at 7:46 AM, Greentime Hu <green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>>>> From: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
>>>>
>>>> This patch introduces some miscellaneous header files.
>>>
>>>> +static inline void __delay(unsigned long loops)
>>>> +{
>>>> + __asm__ __volatile__(".align 2\n"
>>>> + "1:\n"
>>>> + "\taddi\t%0, %0, -1\n"
>>>> + "\tbgtz\t%0, 1b\n"
>>>> + :"=r"(loops)
>>>> + :"0"(loops));
>>>> +}
>>>> +
>>>> +static inline void __udelay(unsigned long usecs, unsigned long lpj)
>>>> +{
>>>> + usecs *= (unsigned long)(((0x8000000000000000ULL / (500000 / HZ)) +
>>>> + 0x80000000ULL) >> 32);
>>>> + usecs = (unsigned long)(((unsigned long long)usecs * lpj) >> 32);
>>>> + __delay(usecs);
>>>> +}
>>>
>>> Do you have a reliable clocksource that you can read here instead of doing the
>>> loop? It's generally preferred to have an accurate delay if at all possible, the
>>> delay loop calibration is only for those architectures that don't have any
>>> way to observe how much time has passed accurately.
>>>
>>
>> We currently only have atcpit100 as clocksource but it is an IP of SoC.
>> These delay API will be unavailable if we changed to another SoC
>> unless all these timer driver provided the same APIs.
>> It may suffer our customers if they forget to port these APIs in their
>> timer drivers when they try to use nds32 in the first beginning.
>
> Ok, thanks for the clarification.
>
>> Or maybe I can use a CONFIG_USE_ACCURATE_DELAY to keep these 2
>> implementions for these purposes?
>
> I'd just add a one-line comment in delay.h to explain that there is no
> cycle counter in the CPU.
>
Thanks.
Got it. I will add a one-line comment in delay.h
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^ permalink raw reply
* RE: [PATCH v4 07/12] [media] cxd2880: Add top level of the driver
From: Takiguchi, Yasunari @ 2017-12-20 1:18 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-media@vger.kernel.org, tbird20d@gmail.com,
frowand.list@gmail.com, Yamamoto, Masayuki, Nozawa, Hideki (STWN),
Yonezawa, Kota, Matsumoto, Toshihiko, Watanabe, Satoshi (SSS),
Takiguchi, Yasunari
In-Reply-To: <20171213172509.1942e951@vento.lan>
Hi, Mauro
> > +
> > +#define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__
>
> Same comments as on other patches: use SPDX and dev_foo() for printing
> messages.
About printing messages pr_fmt, I also replied a comment to [PATCH v4 02/12] [media] cxd2880-spi: Add support for CXD2880 SPI interface.
Please refer to the comment.
Thanks,
Takiguchi
^ permalink raw reply
* RE: [PATCH v4 06/12] [media] cxd2880: Add integration layer for the driver
From: Takiguchi, Yasunari @ 2017-12-20 1:06 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
tbird20d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
Yamamoto, Masayuki, Nozawa, Hideki (STWN), Yonezawa, Kota,
Matsumoto, Toshihiko, Watanabe, Satoshi (SSS),
Takiguchi, Yasunari
In-Reply-To: <20171213171319.675b39a6-ch4gOOMV7nf/PtFMR13I2A@public.gmane.org>
Hi, Mauro.
> >
> > These functions monitor the driver and watch for task completion.
> > This is part of the Sony CXD2880 DVB-T2/T tuner + demodulator driver.
>
> If I understand well, the goal here is to have thread that would be waking
> up from time to time, right? Just use the infrastructure that the Kernel
> has for it, like a kthread, or timer_setup() & friends.
>
> Take a look at include/linux/timer.h, and just use what's already defined.
This code is initialize process.
Therefore, it is executed only once and it will not execute other processing at the same time.
We think that the current implementation is enough.
What do you think?
furthermore, we will modify this code by using ktime_foo().
Thanks,
Takiguchi
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^ permalink raw reply
* RE: [PATCH v4 05/12] [media] cxd2880: Add tuner part of the driver
From: Takiguchi, Yasunari @ 2017-12-20 1:01 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-media@vger.kernel.org, tbird20d@gmail.com,
frowand.list@gmail.com, Yamamoto, Masayuki, Nozawa, Hideki (STWN),
Yonezawa, Kota, Matsumoto, Toshihiko, Watanabe, Satoshi (SSS),
Takiguchi, Yasunari
In-Reply-To: <20171213164039.7eb5ad79@vento.lan>
Hi, Mauro
> > + ret = tnr_dmd->io->read_regs(tnr_dmd->io,
> > + CXD2880_IO_TGT_SYS,
> > + 0x10, data, 1);
> > + if (ret)
> > + return ret;
> > + if ((data[0] & 0x01) == 0x00)
> > + return -EBUSY;
>
> I don't know anything about this hardware, but it sounds weird to return
> -EBUSY here, except if the hardware reached a permanent busy condition,
> and would require some sort of reset to work again.
>
> As this is in the middle of lots of things, I *suspect* that this is
> not the case.
>
> If I'm right, and this is just a transitory solution that could happen
> for a limited amount of time, e. g. if what's there at data[0] is a flag
> saying that the device didn't finish the last operation yet, maybe the
> best would be to do something like:
>
> for (i = 0; i < 10; i++) {
> ret = tnr_dmd->io->read_regs(tnr_dmd->io,
> CXD2880_IO_TGT_SYS,
> 0x10, data, 1);
> if (ret)
> return ret;
> if (data[0] & 0x01)
> break;
> msleep(10);
> }
> if (!(data[0] & 0x01))
> return -EBUSY;
>
> > +
> > + ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
> > + CXD2880_IO_TGT_SYS,
> > + rf_init1_seq5,
> > + ARRAY_SIZE(rf_init1_seq5));
> > + if (ret)
> > + return ret;
> > +
> > + usleep_range(1000, 2000);
> > +
> > + ret = tnr_dmd->io->write_reg(tnr_dmd->io,
> > + CXD2880_IO_TGT_SYS,
> > + 0x00, 0x0a);
> > + if (ret)
> > + return ret;
> > + ret = tnr_dmd->io->read_regs(tnr_dmd->io,
> > + CXD2880_IO_TGT_SYS,
> > + 0x11, data, 1);
> > + if (ret)
> > + return ret;
> > + if ((data[0] & 0x01) == 0x00)
> > + return -EBUSY;
>
> Same here and on similar places.
As the hardware specification, It is abnormal if certain register doesn't become 1 even if sleep time passes.
Perhaps it should not be return EBUSY.
We will reconsider error code.
Thanks,
Takiguchi
^ permalink raw reply
* RE: [PATCH v4 02/12] [media] cxd2880-spi: Add support for CXD2880 SPI interface
From: Takiguchi, Yasunari @ 2017-12-20 0:54 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-media@vger.kernel.org, tbird20d@gmail.com,
frowand.list@gmail.com, Yamamoto, Masayuki, Nozawa, Hideki (STWN),
Yonezawa, Kota, Matsumoto, Toshihiko, Watanabe, Satoshi (SSS),
Takiguchi, Yasunari
In-Reply-To: <20171213155422.03621b5e@vento.lan>
Hi, Mauro.
> > +
> > +#define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__
>
> It would be better to use dev_foo() debug macros instead of
> pr_foo() ones.
I got comment for this previous version patch as below
--------------------------------------------------------------------------------------
The best would be to se dev_err() & friends for printing messages,
as they print the device's name as filled at struct device.
If you don't use, please add a define that will print the name at the logs, like:
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
either at the begining of the driver or at some header file.
Btw, I'm noticing that you're also using dev_err() on other places of the code.
Please standardize. OK, on a few places, you may still need to use pr_err(),
if you need to print a message before initializing struct device, but I suspect that you can init
--------------------------------------------------------------------------------------
You pointed out here before. Because dev_foo () and pr_foo () were mixed.
We standardize with pr_foo() because the logs is outputted before getting the device structure.
Is it better to use dev_foo() where we can use it?
> > +static int cxd2880_stop_feed(struct dvb_demux_feed *feed) {
> > + int i = 0;
> > + int ret;
> > + struct dvb_demux *demux = NULL;
> > + struct cxd2880_dvb_spi *dvb_spi = NULL;
> > +
> > + if (!feed) {
> > + pr_err("invalid arg\n");
> > + return -EINVAL;
> > + }
> > +
> > + demux = feed->demux;
> > + if (!demux) {
> > + pr_err("feed->demux is NULL\n");
> > + return -EINVAL;
> > + }
> > + dvb_spi = demux->priv;
> > +
> > + if (!dvb_spi->feed_count) {
> > + pr_err("no feed is started\n");
> > + return -EINVAL;
> > + }
> > +
> > + if (feed->pid == 0x2000) {
> > + /*
> > + * Special PID case.
> > + * Number of 0x2000 feed request was stored
> > + * in dvb_spi->all_pid_feed_count.
> > + */
> > + if (dvb_spi->all_pid_feed_count <= 0) {
> > + pr_err("PID %d not found.\n", feed->pid);
> > + return -EINVAL;
> > + }
> > + dvb_spi->all_pid_feed_count--;
> > + } else {
> > + struct cxd2880_pid_filter_config cfgtmp;
> > +
> > + cfgtmp = dvb_spi->filter_config;
> > +
> > + for (i = 0; i < CXD2880_MAX_FILTER_SIZE; i++) {
> > + if (feed->pid == cfgtmp.pid_config[i].pid &&
> > + cfgtmp.pid_config[i].is_enable != 0) {
> > + cfgtmp.pid_config[i].is_enable = 0;
> > + cfgtmp.pid_config[i].pid = 0;
> > + pr_debug("removed PID %d from #%d\n",
> > + feed->pid, i);
> > + break;
> > + }
> > + }
> > + dvb_spi->filter_config = cfgtmp;
> > +
> > + if (i == CXD2880_MAX_FILTER_SIZE) {
> > + pr_err("PID %d not found\n", feed->pid);
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + ret = cxd2880_update_pid_filter(dvb_spi,
> > + &dvb_spi->filter_config,
> > + dvb_spi->all_pid_feed_count >
> 0);
> > + dvb_spi->feed_count--;
> > +
> > + if (dvb_spi->feed_count == 0) {
> > + int ret_stop = 0;
> > +
> > + ret_stop =
> kthread_stop(dvb_spi->cxd2880_ts_read_thread);
> > + if (ret_stop) {
> > + pr_err("'kthread_stop failed. (%d)\n",
> ret_stop);
> > + ret = ret_stop;
> > + }
> > + kfree(dvb_spi->ts_buf);
> > + dvb_spi->ts_buf = NULL;
> > + }
> > +
> > + pr_debug("stop feed ok.(count %d)\n", dvb_spi->feed_count);
> > +
> > + return ret;
> > +}
>
> I have the feeling that I've seen the code above before at the dvb core.
> Any reason why don't use the already-existing code at dvb_demux.c &
> friends?
The CXD2880 HW PID filter is used to decrease the amount of TS data transferred via limited bit rate SPI interface.
Thanks,
Takiguchi
^ permalink raw reply
* Re: [PATCH v4 1/3] dt-bindings: mailbox: Introduce Hi3660 controller binding
From: Leo Yan @ 2017-12-20 0:27 UTC (permalink / raw)
To: Rob Herring
Cc: Kaihua Zhong, mark.rutland-5wv7dgnIgG8,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
guodong.xu-QSEj5FYQhm4dnm+yROfE0A,
haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
xuezhiliang-C8/M+/jPZTeaMJb+Lgu22Q,
kevin.wangtao-C8/M+/jPZTeaMJb+Lgu22Q
In-Reply-To: <20171219233038.mjkqakshn7ud7ise@rob-hp-laptop>
On Tue, Dec 19, 2017 at 05:30:38PM -0600, Rob Herring wrote:
> On Tue, Dec 19, 2017 at 07:15:43PM +0800, Kaihua Zhong wrote:
> > From: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> >
> > Introduce a binding for the Hi3660 mailbox controller, the mailbox is
> > used within application processor (AP), communication processor (CP),
> > HIFI and MCU, etc.
> >
> > Signed-off-by: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> > ---
> > .../bindings/mailbox/hisilicon,hi3660-mailbox.txt | 51 ++++++++++++++++++++++
> > 1 file changed, 51 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt
>
> Please add acks when posting new versions.
Thanks, Rob.
This is my bad :) and will add acks in later version.
Thanks,
Leo Yan
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^ permalink raw reply
* Re: [PATCH 0/3] irqchip: irq-bcm2836: add support for DT interrupt polarity
From: Eric Anholt @ 2017-12-20 0:12 UTC (permalink / raw)
To: Marc Zyngier, Stefan Wahren, Thomas Gleixner, Jason Cooper,
Florian Fainelli, Scott Branden, Rob Herring, Mark Rutland
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, phil-FnsA7b+Nu9XbIbC87yuRow,
Russell King, linux-rpi-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <97a68b71-2e62-13ba-72ac-575c3b68617a-5wv7dgnIgG8@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1299 bytes --]
Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> writes:
> On 19/12/17 18:41, Eric Anholt wrote:
>> Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> writes:
>>
>>> On 19/12/17 07:02, Stefan Wahren wrote:
>>>> Hi Marc,
>>>>
>>>> Am 11.12.2017 um 21:39 schrieb Stefan Wahren:
>>>>> This patch series implements DT polarity support for the 1st level interrupt
>>>>> controller.
>>>>>
>>>>> Stefan Wahren (3):
>>>>> dt-bindings: bcm2836-l1-intc: add interrupt polarity support
>>>>> irqchip: irq-bcm2836: add support for DT interrupt polarity
>>>>> ARM: dts: bcm283x: Define polarity of per-cpu interrupts
>>>>>
>>>>> .../interrupt-controller/brcm,bcm2836-l1-intc.txt | 4 +-
>>>>> arch/arm/boot/dts/bcm2836.dtsi | 14 +++----
>>>>> arch/arm/boot/dts/bcm2837.dtsi | 12 +++---
>>>>> arch/arm/boot/dts/bcm283x.dtsi | 1 +
>>>>> drivers/irqchip/irq-bcm2836.c | 46 +++++++++++++---------
>>>>> 5 files changed, 44 insertions(+), 33 deletions(-)
>>>>>
>>>>
>>>> is this series okay?
>>>
>>> Yes, it does look good. I'll queue that for 4.16.
>>
>> Are you grabbing all 3, or should I be grabbing the DT one?
>
> All 3, if that's OK with you.
Go for it.
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