* Re: [PATCH v2 1/5] ARM: dts: iwg20d-q7-common: Sound PIO support
From: Simon Horman @ 2017-12-20 9:49 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Kuninori Morimoto, Magnus Damm,
Chris Paterson, Fabrizio Castro, devicetree, linux-renesas-soc
In-Reply-To: <20171220094128.cffetpgij42m57kq@verge.net.au>
On Wed, Dec 20, 2017 at 10:41:28AM +0100, Simon Horman wrote:
> On Mon, Dec 18, 2017 at 06:22:37PM +0000, Biju Das wrote:
> > Enable sound PIO support on carrier board.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> > ---
> > v1-->v2
> > * Reworked sorting
> >
> > arch/arm/boot/dts/iwg20d-q7-common.dtsi | 46 +++++++++++++++++++++++++++++++++
> > 1 file changed, 46 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> > index 2070b14..ed67201 100644
> > --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> > +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> > @@ -34,6 +34,22 @@
> > regulator-always-on;
> > };
> >
> > + rsnd_sgtl5000: sound {
> > + compatible = "simple-audio-card";
> > +
> > + simple-audio-card,format = "i2s";
> > + simple-audio-card,bitclock-master = <&sndcodec>;
> > + simple-audio-card,frame-master = <&sndcodec>;
> > +
> > + sndcpu: simple-audio-card,cpu {
> > + sound-dai = <&rcar_sound>;
> > + };
> > +
> > + sndcodec: simple-audio-card,codec {
> > + sound-dai = <&sgtl5000>;
>
> I'm sorry for not noticing this earlier but with this patch applied
> (and none of the others in this series) I see the following error:
>
> arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: ERROR (phandle_references):
> Reference to non-existent node or label "sgtl5000"
>
> At the very least this will break bisection.
> Please find a way to avoid this.
Sorry for the false alarm!!!
It looks like "ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio codec"
was missing from my tree and all is well with that patch present.
^ permalink raw reply
* [PATCH net 2/2] net: mediatek: remove superfluous pin setup for MT7622 SoC
From: sean.wang @ 2017-12-20 9:47 UTC (permalink / raw)
To: robh+dt, davem, mark.rutland
Cc: matthias.bgg, john, nbd, nelson.chang, devicetree,
linux-arm-kernel, netdev, linux-kernel, linux-mediatek, Sean Wang
In-Reply-To: <e366efc29985d3292c8a1afb1389b5eac57c9037.1513762066.git.sean.wang@mediatek.com>
From: Sean Wang <sean.wang@mediatek.com>
Remove superfluous pin setup to get out of accessing invalid I/O pin
registers because the way for pin configuring tends to be different from
various SoCs and thus it should be better being managed and controlled by
the pinctrl driver which MT7622 already can support.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 +++++++++++++++++------------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +++
2 files changed, 24 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index fc67e35..29826dd 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1952,14 +1952,16 @@ static int mtk_hw_init(struct mtk_eth *eth)
}
regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
- /* Set GE2 driving and slew rate */
- regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
+ if (eth->pctl) {
+ /* Set GE2 driving and slew rate */
+ regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
- /* set GE2 TDSEL */
- regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
+ /* set GE2 TDSEL */
+ regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
- /* set GE2 TUNE */
- regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
+ /* set GE2 TUNE */
+ regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
+ }
/* Set linkdown as the default for each GMAC. Its own MCR would be set
* up with the more appropriate value when mtk_phy_link_adjust call is
@@ -2538,11 +2540,13 @@ static int mtk_probe(struct platform_device *pdev)
}
}
- eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
- "mediatek,pctl");
- if (IS_ERR(eth->pctl)) {
- dev_err(&pdev->dev, "no pctl regmap found\n");
- return PTR_ERR(eth->pctl);
+ if (eth->soc->required_pctl) {
+ eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "mediatek,pctl");
+ if (IS_ERR(eth->pctl)) {
+ dev_err(&pdev->dev, "no pctl regmap found\n");
+ return PTR_ERR(eth->pctl);
+ }
}
for (i = 0; i < 3; i++) {
@@ -2668,17 +2672,20 @@ static int mtk_remove(struct platform_device *pdev)
static const struct mtk_soc_data mt2701_data = {
.caps = MTK_GMAC1_TRGMII,
- .required_clks = MT7623_CLKS_BITMAP
+ .required_clks = MT7623_CLKS_BITMAP,
+ .required_pctl = true,
};
static const struct mtk_soc_data mt7622_data = {
.caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW,
- .required_clks = MT7622_CLKS_BITMAP
+ .required_clks = MT7622_CLKS_BITMAP,
+ .required_pctl = false,
};
static const struct mtk_soc_data mt7623_data = {
.caps = MTK_GMAC1_TRGMII,
- .required_clks = MT7623_CLKS_BITMAP
+ .required_clks = MT7623_CLKS_BITMAP,
+ .required_pctl = true,
};
const struct of_device_id of_mtk_match[] = {
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index a3af466..672b8c3 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -573,10 +573,13 @@ struct mtk_rx_ring {
* @caps Flags shown the extra capability for the SoC
* @required_clks Flags shown the bitmap for required clocks on
* the target SoC
+ * @required_pctl A bool value to show whether the SoC requires
+ * the extra setup for those pins used by GMAC.
*/
struct mtk_soc_data {
u32 caps;
u32 required_clks;
+ bool required_pctl;
};
/* currently no SoC has more than 2 macs */
--
2.7.4
^ permalink raw reply related
* [PATCH net 1/2] dt-bindings: net: mediatek: add condition to property mediatek,pctl
From: sean.wang @ 2017-12-20 9:47 UTC (permalink / raw)
To: robh+dt, davem, mark.rutland
Cc: matthias.bgg, john, nbd, nelson.chang, devicetree,
linux-arm-kernel, netdev, linux-kernel, linux-mediatek, Sean Wang
From: Sean Wang <sean.wang@mediatek.com>
The property "mediatek,pctl" is only required for SoCs such as MT2701 and
MT7623, so adding a few words for stating the condition.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
Documentation/devicetree/bindings/net/mediatek-net.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
index 214eaa9..53c13ee 100644
--- a/Documentation/devicetree/bindings/net/mediatek-net.txt
+++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
@@ -28,7 +28,7 @@ Required properties:
- mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup
which is required for those SoCs equipped with SGMII such as MT7622 SoC.
- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
- and driver current
+ and driver current: only for MT2701 and MT7623 SoC
Optional properties:
- interrupt-parent: Should be the phandle for the interrupt controller
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v2 1/5] ARM: dts: iwg20d-q7-common: Sound PIO support
From: Simon Horman @ 2017-12-20 9:41 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Kuninori Morimoto, Magnus Damm,
Chris Paterson, Fabrizio Castro,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1513621361-10944-2-git-send-email-biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
On Mon, Dec 18, 2017 at 06:22:37PM +0000, Biju Das wrote:
> Enable sound PIO support on carrier board.
>
> Signed-off-by: Biju Das <biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
> Reviewed-by: Fabrizio Castro <fabrizio.castro-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> ---
> v1-->v2
> * Reworked sorting
>
> arch/arm/boot/dts/iwg20d-q7-common.dtsi | 46 +++++++++++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
> diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> index 2070b14..ed67201 100644
> --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> @@ -34,6 +34,22 @@
> regulator-always-on;
> };
>
> + rsnd_sgtl5000: sound {
> + compatible = "simple-audio-card";
> +
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <&sndcodec>;
> + simple-audio-card,frame-master = <&sndcodec>;
> +
> + sndcpu: simple-audio-card,cpu {
> + sound-dai = <&rcar_sound>;
> + };
> +
> + sndcodec: simple-audio-card,codec {
> + sound-dai = <&sgtl5000>;
I'm sorry for not noticing this earlier but with this patch applied
(and none of the others in this series) I see the following error:
arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: ERROR (phandle_references):
Reference to non-existent node or label "sgtl5000"
At the very least this will break bisection.
Please find a way to avoid this.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2 2/2] can: rcar_canfd: document r8a77995 (R-Car D3) compatibility strings
From: Simon Horman @ 2017-12-20 9:38 UTC (permalink / raw)
To: Ulrich Hecht
Cc: linux-renesas-soc, linux-can, devicetree, wsa, geert, magnus.damm,
chris.paterson2, ramesh.shanmugasundaram, robh
In-Reply-To: <1513612297-10173-3-git-send-email-ulrich.hecht+renesas@gmail.com>
On Mon, Dec 18, 2017 at 04:51:37PM +0100, Ulrich Hecht wrote:
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply
* Re: [PATCH v2 1/2] can: rcar_can: document r8a77995 (R-Car D3) compatibility strings
From: Simon Horman @ 2017-12-20 9:38 UTC (permalink / raw)
To: Ulrich Hecht
Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-can-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, wsa-z923LK4zBo2bacvFa/9K2g,
geert-Td1EMuHUCqxL1ZNQvxDV9g, magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
chris.paterson2-zM6kxYcvzFBBDgjK7y7TUQ,
ramesh.shanmugasundaram-kTT6dE0pTRh9uiUsa/gSgQ,
robh-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <1513612297-10173-2-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Mon, Dec 18, 2017 at 04:51:36PM +0100, Ulrich Hecht wrote:
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Reviewed-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH v9 2/3] dt-bindings: iio: temperature: add MLX90632 device bindings
From: Crt Mori @ 2017-12-20 9:33 UTC (permalink / raw)
To: Jonathan Cameron
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Crt Mori
Add device tree bindings for MLX90632 IR temperature sensor.
Signed-off-by: Crt Mori <cmo-fc6wVz46lShBDgjK7y7TUQ@public.gmane.org>
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
.../bindings/iio/temperature/mlx90632.txt | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/temperature/mlx90632.txt
diff --git a/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt b/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt
new file mode 100644
index 000000000000..0b05812001f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt
@@ -0,0 +1,28 @@
+* Melexis MLX90632 contactless Infra Red temperature sensor
+
+Link to datasheet: https://www.melexis.com/en/documents/documentation/datasheets/datasheet-mlx90632
+
+There are various applications for the Infra Red contactless temperature sensor
+and MLX90632 is most suitable for consumer applications where measured object
+temperature is in range between -20 to 200 degrees Celsius with relative error
+of measurement below 1 degree Celsius in object temperature range for
+industrial applications. Since it can operate and measure ambient temperature
+in range of -20 to 85 degrees Celsius it is suitable also for outdoor use.
+
+Be aware that electronics surrounding the sensor can increase ambient
+temperature. MLX90632 can be calibrated to reduce the housing effect via
+already existing EEPROM parameters.
+
+Since measured object emissivity effects Infra Red energy emitted, emissivity
+should be set before requesting the object temperature.
+
+Required properties:
+ - compatible: should be "melexis,mlx90632"
+ - reg: the I2C address of the sensor (default 0x3a)
+
+Example:
+
+mlx90632@3a {
+ compatible = "melexis,mlx90632";
+ reg = <0x3a>;
+};
--
2.15.0
^ permalink raw reply related
* Re: [PATCH v2 3/3] ARM: dts: r8a7745: Add CMT SoC specific support
From: Simon Horman @ 2017-12-20 9:24 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Fabrizio Castro, Rob Herring, Mark Rutland, Russell King,
Magnus Damm, Linux-Renesas, devicetree, linux-arm-kernel,
Geert Uytterhoeven, Chris Paterson, Biju Das
In-Reply-To: <CAMuHMdV-sM833JqN-UD8sBYc-bVS-3zWanaQTL-OUgpvKh_uXA@mail.gmail.com>
On Tue, Dec 19, 2017 at 12:21:12PM +0100, Geert Uytterhoeven wrote:
> On Mon, Dec 18, 2017 at 6:39 PM, Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > Add CMT[01] support to SoC DT.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied.
^ permalink raw reply
* Re: [PATCH V2 9/9] ARM: dts: stm32: add initial support of stm32mp157c eval board
From: Alexandre Torgue @ 2017-12-20 9:19 UTC (permalink / raw)
To: Linus Walleij, Ludovic Barre
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Arnd Bergmann, Russell King, linux-kernel@vger.kernel.org,
Rob Herring, Maxime Coquelin, Gerald Baeza, Linux ARM
In-Reply-To: <CACRpkdZaEjdGB2k6HdPt1_E0jRXEimEUxT9NmMwMw7OiyeqGLA@mail.gmail.com>
Hi Linus
On 12/20/2017 08:44 AM, Linus Walleij wrote:
> On Mon, Dec 18, 2017 at 4:17 PM, Ludovic Barre <ludovic.Barre@st.com> wrote:
>
>> From: Ludovic Barre <ludovic.barre@st.com>
>>
>> Add support of stm32mp157c evaluation board (part number: STM32MP157C-EV1)
>> split in 2 elements:
>> -Daughter board (part number: STM32MP157C-ED1)
>> which includes CPU, memory and power supply
>> -Mother board (part number: STM32MP157C-EM1)
>> which includes external peripherals (like display, camera,...)
>> and extension connectors.
>>
>> The daughter board can run alone, this is why the device tree files
>> are split in two layers, for the complete evaluation board (ev1)
>> and for the daughter board alone (ed1).
>>
>> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
>> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
> (...)
>> diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
>
> Evaluation boards are important because they set a pattern that customers
> will use.
>
> Please consider to include nodes for all GPIO blocks used in this
> evaluation board, and add:
>
> gpio-line-names = "foo", "bar" ...;
>
> See for example
> arch/arm/boot/dts/bcm2835-rpi-a.dts
> arch/arm/boot/dts/ste-snowball.dts
>
> It's good to have because probably you guys have proper schematics and
> know rail names of the stuff connected to those GPIO lines and so on,
> so you can give the lines proper names.
It looks like useful for pins used as gpio line. Are you saying that we
also have to describe pins used as Alternate Function ? Currently for
stm32 MCU we add (for each pins in a group) a comment in
stm32xxx-pinctrl.dtsi file to describe the pinmux (to help developers).
On driver side for each stm32 pinctrl driver (ex:
drivers/pinctrl/stm32/pinctrl-stm32f429.c) we add for each possible
muxing a name:
STM32_PIN(
PINCTRL_PIN(0, "PA0"),
STM32_FUNCTION(0, "GPIOA0"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(8, "USART2_CTS"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(12, "ETH_MII_CRS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
To be honest, currently there is a an issue to printout the name :) but
I have a patch to send for that.
regards
Alex
>
> It will be helpful for people using the reference design, especially with the
> new character device, and also sets a pattern for people doing devices
> based on the reference design and we really want to do that.
>
> Yours,
> Linus Walleij
>
^ permalink raw reply
* [PATCH] RISC-V: Support built-in dtb
From: Zong Li @ 2017-12-20 9:14 UTC (permalink / raw)
To: palmer, albert, robh+dt, mark.rutland, wesley, patches,
linux-kernel, devicetree, zong
Cc: Zong Li
Build the dtb into the kernel image.
If the DTB is given via bootloader, the external DTB is adopted first.
Signed-off-by: Zong Li <zongbox@gmail.com>
---
arch/riscv/Kconfig | 4 ++++
arch/riscv/Makefile | 9 +++++++++
arch/riscv/boot/Makefile | 17 +++++++++++++++++
arch/riscv/boot/dts/Makefile | 11 +++++++++++
arch/riscv/kernel/setup.c | 2 +-
5 files changed, 42 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/boot/Makefile
create mode 100644 arch/riscv/boot/dts/Makefile
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 2e15e85..831cbb9 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -189,6 +189,10 @@ config RISCV_ISA_C
config RISCV_ISA_A
def_bool y
+config RISCV_BUILTIN_DTB
+ string "Builtin DTB"
+ default ""
+
endmenu
menu "Kernel type"
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 6719dd3..4c5c9f8 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -57,6 +57,12 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
KBUILD_CFLAGS += -mcmodel=medany
endif
+ifneq '$(CONFIG_RISCV_BUILTIN_DTB)' '""'
+BUILTIN_DTB := y
+else
+BUILTIN_DTB := n
+endif
+
# GCC versions that support the "-mstrict-align" option default to allowing
# unaligned accesses. While unaligned accesses are explicitly allowed in the
# RISC-V ISA, they're emulated by machine mode traps on all extant
@@ -69,4 +75,7 @@ core-y += arch/riscv/kernel/ arch/riscv/mm/
libs-y += arch/riscv/lib/
+boot := arch/riscv/boot
+core-$(BUILTIN_DTB) += $(boot)/dts/
+
all: vmlinux
diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile
new file mode 100644
index 0000000..003d697
--- /dev/null
+++ b/arch/riscv/boot/Makefile
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0
+
+targets := Image Image.gz
+
+$(obj)/Image: vmlinux FORCE
+ $(call if_changed,objcopy)
+
+$(obj)/Image.gz: $(obj)/Image FORCE
+ $(call if_changed,gzip)
+
+install: $(obj)/Image
+ $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+ $(obj)/Image System.map "$(INSTALL_PATH)"
+
+zinstall: $(obj)/Image.gz
+ $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+ $(obj)/Image.gz System.map "$(INSTALL_PATH)"
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
new file mode 100644
index 0000000..b65d070
--- /dev/null
+++ b/arch/riscv/boot/dts/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0
+
+ifneq '$(CONFIG_RISCV_BUILTIN_DTB)' '""'
+BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_RISCV_BUILTIN_DTB)).dtb.o
+else
+BUILTIN_DTB :=
+endif
+
+obj-$(CONFIG_OF) += $(BUILTIN_DTB)
+
+clean-files := *.dtb *.dtb.S
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index e59a28c..3c89f3d 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -149,7 +149,7 @@ asmlinkage void __init setup_vm(void)
void __init sbi_save(unsigned int hartid, void *dtb)
{
- early_init_dt_scan(__va(dtb));
+ early_init_dt_scan(dtb ? __va(dtb) : __dtb_start);
}
/*
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v2 2/3] ARM: dts: r8a7743: Add CMT SoC specific support
From: Simon Horman @ 2017-12-20 9:13 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Fabrizio Castro, Rob Herring, Mark Rutland, Russell King,
Magnus Damm, Linux-Renesas, devicetree, linux-arm-kernel,
Geert Uytterhoeven, Chris Paterson, Biju Das
In-Reply-To: <CAMuHMdWPufohN+g=gFwi2V6vsGvhO7kTh8kj9AKCkraGKWGZBg@mail.gmail.com>
On Tue, Dec 19, 2017 at 12:20:45PM +0100, Geert Uytterhoeven wrote:
> On Mon, Dec 18, 2017 at 6:39 PM, Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > Add CMT[01] support to SoC DT.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied.
^ permalink raw reply
* Re: [PATCH v2 4/4] ARM: dts: r8a7745: Add TPU support
From: Simon Horman @ 2017-12-20 9:12 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Rob Herring, Mark Rutland, Russell King, Magnus Damm,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven, Chris Paterson, Biju Das
In-Reply-To: <1513620411-17478-5-git-send-email-fabrizio.castro@bp.renesas.com>
On Mon, Dec 18, 2017 at 06:06:51PM +0000, Fabrizio Castro wrote:
> Add TPU support to SoC DT.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>
> ---
> v1->v2:
> * No change
Thanks, applied.
^ permalink raw reply
* Re: [PATCH v2 2/4] ARM: dts: r8a7745: Add PWM SoC support
From: Simon Horman @ 2017-12-20 9:10 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Fabrizio Castro, Mark Rutland, Chris Paterson, Geert Uytterhoeven,
devicetree, Magnus Damm, Russell King, Biju Das, Linux-Renesas,
Rob Herring, linux-arm-kernel
In-Reply-To: <CAMuHMdUi953N1J+vfJWJo0GMKO4tBZV9HnX7haG0fvyNHfOvOA@mail.gmail.com>
On Tue, Dec 19, 2017 at 12:25:54PM +0100, Geert Uytterhoeven wrote:
> On Mon, Dec 18, 2017 at 7:06 PM, Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > Add the definitions for pwm[0123456] to the SoC .dtsi.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > --- a/arch/arm/boot/dts/r8a7745.dtsi
> > +++ b/arch/arm/boot/dts/r8a7745.dtsi
> > @@ -968,6 +968,83 @@
> > status = "disabled";
> > };
> >
> > + pwm0: pwm@e6e30000 {
> > + compatible = "renesas,pwm-r8a7745",
> > + "renesas,pwm-rcar";
>
> I think this can fit on one line.
No need. I have fixed this when applying the patch.
^ permalink raw reply
* Re: [PATCH v2 2/2] ARM: dts: r8a7743: Add thermal device to DT
From: Simon Horman @ 2017-12-20 8:50 UTC (permalink / raw)
To: Biju Das
Cc: Zhang Rui, Eduardo Valentin, Rob Herring, Mark Rutland,
Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1513689449-2700-3-git-send-email-biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
On Tue, Dec 19, 2017 at 01:17:29PM +0000, Biju Das wrote:
> This patch instantiates the thermal sensor module with thermal-zone
> support.
>
> This patch is based on the commit cac68a56e34b
> ("ARM: dts: r8a7791: enable to use thermal-zone") by Kuninori Morimoto.
>
> Signed-off-by: Biju Das <biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
> Reviewed-by: Fabrizio Castro <fabrizio.castro-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
> ---
> v1->v2
> * Fixed the size.
Thanks, applied.
--
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^ permalink raw reply
* Re: [PATCH v3 5/5] ARM: dts: r8a7743: Add TPU support
From: Simon Horman @ 2017-12-20 8:47 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Rob Herring, Mark Rutland, Russell King, Magnus Damm,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven, Chris Paterson, Biju Das
In-Reply-To: <1513690500-12165-6-git-send-email-fabrizio.castro@bp.renesas.com>
On Tue, Dec 19, 2017 at 01:35:00PM +0000, Fabrizio Castro wrote:
> Add TPU support to SoC DT.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v2->v3:
> * No change
Thanks, applied.
^ permalink raw reply
* Re: [PATCH v3 4/5] dt-bindings: pwm: renesas-tpu: Document r8a774[35] support
From: Simon Horman @ 2017-12-20 8:46 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Thierry Reding, Rob Herring, Mark Rutland,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Geert Uytterhoeven,
Chris Paterson, Biju Das,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1513690500-12165-5-git-send-email-fabrizio.castro-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
On Tue, Dec 19, 2017 at 01:34:59PM +0000, Fabrizio Castro wrote:
> Document r8a774[35] specific compatible strings. No driver change is
> needed as the fallback compatible string "renesas,tpu" activates the
> right code in the driver.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
> Reviewed-by: Biju Das <biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
> Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
> ---
> v2->v3:
> * No change
Reviewed-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
--
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^ permalink raw reply
* Re: [PATCH v3 3/5] ARM: dts: r8a7743: Add PWM SoC support
From: Simon Horman @ 2017-12-20 8:45 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Rob Herring, Mark Rutland, Russell King, Magnus Damm,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven, Chris Paterson, Biju Das
In-Reply-To: <1513690500-12165-4-git-send-email-fabrizio.castro@bp.renesas.com>
On Tue, Dec 19, 2017 at 01:34:58PM +0000, Fabrizio Castro wrote:
> Add the definitions for pwm[0123456] to the SoC .dtsi.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v2->v3:
> * pwm[0123456] compatible definitions don't wrap anymore
Thanks, applied.
^ permalink raw reply
* Re: [PATCH v3 2/5] dt-bindings: pwm: rcar: Document r8a774[35] PWM bindings
From: Simon Horman @ 2017-12-20 8:31 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Thierry Reding, Rob Herring, Mark Rutland, linux-pwm, devicetree,
Geert Uytterhoeven, Chris Paterson, Biju Das, linux-renesas-soc
In-Reply-To: <1513690500-12165-3-git-send-email-fabrizio.castro@bp.renesas.com>
On Tue, Dec 19, 2017 at 01:34:57PM +0000, Fabrizio Castro wrote:
> This patch adds compatible strings specific to r8a774[35], no driver
> change is needed as the fallback compatible string will activate the
> right code. Also, this patch replaces the example with a DT snippet used
> for adding PWM0 support to an r8a7743 based platform.
What is the motivation for updating the example?
Could it be stated here?
^ permalink raw reply
* [PATCH v2 2/2] dt/bindings: Add bindings for Layerscape external irqs
From: Rasmus Villemoes @ 2017-12-20 8:30 UTC (permalink / raw)
To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
Mark Rutland
Cc: Andy Tang, Shawn Guo, Alexander Stein, Rasmus Villemoes,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1513758631-19909-1-git-send-email-rasmus.villemoes-rjjw5hvvQKZaa/9Udqfwiw@public.gmane.org>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes-rjjw5hvvQKZaa/9Udqfwiw@public.gmane.org>
---
.../interrupt-controller/fsl,ls-extirq.txt | 37 ++++++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
new file mode 100644
index 000000000000..7e4680866364
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
@@ -0,0 +1,37 @@
+* Freescale Layerscape external IRQs
+
+Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting
+the polarity of certain external interrupt lines.
+
+Required properties:
+- compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
+- interrupt-controller: Identifies the node as an interrupt controller
+- #interrupt-cells: Use the same format as specified by GIC in arm,gic.txt.
+- interrupt-parent: phandle of GIC.
+- syscon: phandle of Supplemental Configuration Unit (scfg) and offset
+ to the INTPCR register.
+- interrupts: Specifies the mapping to interrupt numbers in the parent
+ interrupt controller. Interrupts are mapped one-to-one to parent
+ interrupts.
+
+Optional properties:
+- bit-reverse: This boolean property should be set on the LS1021A if
+ the SCFGREVCR register has been set to all-ones (which is usually
+ the case), meaning that all reads and writes of SCFG registers are
+ implicitly bit-reversed. Other compatible platforms do not have such
+ a register.
+
+Example:
+ extirq: extirq {
+ compatible = "fsl,ls1021a-extirq";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ syscon = <&scfg 0x1ac>;
+ interrupts = <163 164 165 167 168 169>;
+ bit-reverse;
+ };
+
+
+ interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <&extirq GIC_SPI 1 IRQ_TYPE_LEVEL_LOW>;
--
2.7.4
--
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^ permalink raw reply related
* Re: [PATCH v2 1/2] dt-bindings: thermal: rcar: Add device tree support for r8a7743
From: Simon Horman @ 2017-12-20 8:27 UTC (permalink / raw)
To: Biju Das
Cc: Zhang Rui, Eduardo Valentin, Rob Herring, Mark Rutland,
Magnus Damm, Chris Paterson, Fabrizio Castro, devicetree,
linux-renesas-soc, linux-pm
In-Reply-To: <1513689449-2700-2-git-send-email-biju.das@bp.renesas.com>
On Tue, Dec 19, 2017 at 01:17:28PM +0000, Biju Das wrote:
> Add thermal sensor support for r8a7743 SoC. The Renesas RZ/G1M
> (r8a7743) thermal sensor module is identical to the R-Car Gen2 family.
>
> No driver change is needed due to the fallback compatible value
> "renesas,rcar-gen2-thermal".
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Simon Horman <simon.horman@netronome.com>
> ---
> v1->v2
> * No Change
>
> Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
> index a8e52c8..349e635 100644
> --- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
> @@ -6,6 +6,7 @@ Required properties:
> "renesas,rcar-thermal" (without thermal-zone) as fallback.
> Examples with soctypes are:
> - "renesas,thermal-r8a73a4" (R-Mobile APE6)
> + - "renesas,thermal-r8a7743" (RZ/G1M)
> - "renesas,thermal-r8a7779" (R-Car H1)
> - "renesas,thermal-r8a7790" (R-Car H2)
> - "renesas,thermal-r8a7791" (R-Car M2-W)
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH 0/2] eeprom: at24: write-protect pin support
From: Bartosz Golaszewski @ 2017-12-20 8:27 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Linus Walleij, Peter Rosin
Cc: linux-i2c, devicetree-u79uwXL29TY76Z2rM5mHXA,
Linux Kernel Mailing List, Bartosz Golaszewski
In-Reply-To: <20171219161432.29809-1-brgl-ARrdPY/1zhM@public.gmane.org>
2017-12-19 17:14 GMT+01:00 Bartosz Golaszewski <brgl-ARrdPY/1zhM@public.gmane.org>:
> AT24 EEPROMs have a write-protect pin, which - when pulled high -
> inhibits writes to the upper quadrant of memory (although it has been
> observed that on some chips it disables writing to the entire memory
> range).
>
> On some boards, this pin is connected to a GPIO and pulled high by
> default, which forces the user to manually change its state before
> writing. On linux this means that we either need to hog the line all
> the time, or set the GPIO value before writing from outside of the
> at24 driver.
>
> This series adds support for the write-protect pin split into two
> parts. The first patch extends the relevant binding document, while
> the second modifies the at24 code to pull the write-protect GPIO
> low (if present) during write operations.
>
> Bartosz Golaszewski (2):
> dt-bindings: at24: new optional property - write-protect-gpios
> eeprom: at24: add support for the write-protect pin
>
> Documentation/devicetree/bindings/eeprom/at24.txt | 4 ++++
> drivers/misc/eeprom/at24.c | 12 ++++++++++++
> 2 files changed, 16 insertions(+)
>
> --
> 2.15.1
>
Superseded by v2.
Thanks,
Bartosz
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^ permalink raw reply
* [PATCH v2 2/2] eeprom: at24: add support for the write-protect pin
From: Bartosz Golaszewski @ 2017-12-20 8:26 UTC (permalink / raw)
To: Andy Shevchenko, Rob Herring, Mark Rutland, Linus Walleij,
Peter Rosin
Cc: linux-i2c, devicetree, linux-kernel, Bartosz Golaszewski
In-Reply-To: <20171220082633.32237-1-brgl@bgdev.pl>
AT24 EEPROMs have a write-protect pin, which - when pulled high -
inhibits writes to the upper quadrant of memory (although it has been
observed that on some chips it disables writing to the entire memory
range).
On some boards, this pin is connected to a GPIO and pulled high by
default, which forces the user to manually change its state before
writing. On linux this means that we either need to hog the line all
the time, or set the GPIO value before writing from outside of the
at24 driver.
Make the driver check if the write-protect GPIO was defined in the
device tree and pull it low whenever writing to the EEPROM.
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
drivers/misc/eeprom/at24.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index b44a3d2b2b20..4456e192681c 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -27,6 +27,7 @@
#include <linux/regmap.h>
#include <linux/platform_data/at24.h>
#include <linux/pm_runtime.h>
+#include <linux/gpio/consumer.h>
/*
* I2C EEPROMs from most vendors are inexpensive and mostly interchangeable.
@@ -77,6 +78,8 @@ struct at24_data {
struct nvmem_config nvmem_config;
struct nvmem_device *nvmem;
+ struct gpio_desc *wp_gpio;
+
/*
* Some chips tie up multiple I2C addresses; dummy devices reserve
* them for us, and we'll use them with SMBus calls.
@@ -442,12 +445,14 @@ static int at24_write(void *priv, unsigned int off, void *val, size_t count)
* from this host, but not from other I2C masters.
*/
mutex_lock(&at24->lock);
+ gpiod_set_value_cansleep(at24->wp_gpio, 0);
while (count) {
int status;
status = at24_regmap_write(at24, buf, off, count);
if (status < 0) {
+ gpiod_set_value_cansleep(at24->wp_gpio, 1);
mutex_unlock(&at24->lock);
pm_runtime_put(dev);
return status;
@@ -457,6 +462,7 @@ static int at24_write(void *priv, unsigned int off, void *val, size_t count)
count -= status;
}
+ gpiod_set_value_cansleep(at24->wp_gpio, 1);
mutex_unlock(&at24->lock);
pm_runtime_put(dev);
@@ -604,6 +610,11 @@ static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id)
at24->num_addresses = num_addresses;
at24->offset_adj = at24_get_offset_adj(chip.flags, chip.byte_len);
+ at24->wp_gpio = devm_gpiod_get_optional(&client->dev,
+ "wp", GPIOD_OUT_HIGH);
+ if (IS_ERR(at24->wp_gpio))
+ return PTR_ERR(at24->wp_gpio);
+
at24->client[0].client = client;
at24->client[0].regmap = devm_regmap_init_i2c(client, ®map_config);
if (IS_ERR(at24->client[0].regmap))
--
2.15.1
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: at24: new optional property - wp-gpios
From: Bartosz Golaszewski @ 2017-12-20 8:26 UTC (permalink / raw)
To: Andy Shevchenko, Rob Herring, Mark Rutland, Linus Walleij,
Peter Rosin
Cc: linux-i2c, devicetree, linux-kernel, Bartosz Golaszewski
In-Reply-To: <20171220082633.32237-1-brgl@bgdev.pl>
AT24 EEPROMs have a write-protect pin, which - when pulled high -
inhibits writes to the upper quadrant of memory (although it has been
observed that on some chips it disables writing to the entire memory
range).
On some boards, this pin is connected to a GPIO and pulled high by
default, which forces the user to manually change its state before
writing. On linux this means that we either need to hog the line all
the time, or set the GPIO value before writing from outside of the
at24 driver.
Add a new optional property to the device tree binding document, which
allows to specify the GPIO line to which the write-protect pin is
connected.
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
Documentation/devicetree/bindings/eeprom/at24.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
index a0415b8471bb..cbc80e194ac6 100644
--- a/Documentation/devicetree/bindings/eeprom/at24.txt
+++ b/Documentation/devicetree/bindings/eeprom/at24.txt
@@ -43,10 +43,13 @@ Optional properties:
eeprom does not automatically roll over reads to the next
slave address. Please consult the manual of your device.
+ - wp-gpios: GPIO to which the write-protect pin of the chip is connected.
+
Example:
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
+ wp-gpios = <&gpio1 3 0>;
};
--
2.15.1
^ permalink raw reply related
* [PATCH v2 0/2] eeprom: at24: write-protect pin support
From: Bartosz Golaszewski @ 2017-12-20 8:26 UTC (permalink / raw)
To: Andy Shevchenko, Rob Herring, Mark Rutland, Linus Walleij,
Peter Rosin
Cc: linux-i2c, devicetree, linux-kernel, Bartosz Golaszewski
AT24 EEPROMs have a write-protect pin, which - when pulled high -
inhibits writes to the upper quadrant of memory (although it has been
observed that on some chips it disables writing to the entire memory
range).
On some boards, this pin is connected to a GPIO and pulled high by
default, which forces the user to manually change its state before
writing. On linux this means that we either need to hog the line all
the time, or set the GPIO value before writing from outside of the
at24 driver.
This series adds support for the write-protect pin split into two
parts. The first patch extends the relevant binding document, while
the second modifies the at24 code to pull the write-protect GPIO
low (if present) during write operations.
v1 -> v2:
- renamed the DT property to wp-gpios
Bartosz Golaszewski (2):
dt-bindings: at24: new optional property - wp-gpios
eeprom: at24: add support for the write-protect pin
Documentation/devicetree/bindings/eeprom/at24.txt | 3 +++
drivers/misc/eeprom/at24.c | 11 +++++++++++
2 files changed, 14 insertions(+)
--
2.15.1
^ permalink raw reply
* Re: [PATCH V8 2/3] OPP: Introduce "required-opp" property
From: Viresh Kumar @ 2017-12-20 8:26 UTC (permalink / raw)
To: Ulf Hansson
Cc: Kevin Hilman, Rob Herring, Viresh Kumar, Nishanth Menon,
Stephen Boyd, Rafael J. Wysocki, linux-pm@vger.kernel.org,
Vincent Guittot, Rajendra Nayak, Sudeep Holla,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <CAPDyKFoWo0bUMNbGFSgjdN-ZwS+o6_GUXt-sQK0Qpcndw5B8eA@mail.gmail.com>
On 20-12-17, 09:23, Ulf Hansson wrote:
> Nitpick: Could you please change "parent" to "power", to be consistent
> with earlier examples.
Sure. Thanks for the review.
--
viresh
^ permalink raw reply
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