* Re: [PATCH 2/4] dma: fsl-qdma: add devicetree documentation for qDMA driver.
From: Rob Herring @ 2017-12-20 18:43 UTC (permalink / raw)
To: Wen He; +Cc: devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171219064157.29586-1-wen.he_1-3arQi8VN3Tc@public.gmane.org>
On Tue, Dec 19, 2017 at 02:41:57PM +0800, Wen He wrote:
Need a commit message.
> Signed-off-by: Wen He <wen.he_1-3arQi8VN3Tc@public.gmane.org>
> ---
> Documentation/devicetree/bindings/dma/fsl-qdma.txt | 42 ++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
>
> diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
> new file mode 100644
> index 000000000000..b076177b4863
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
> @@ -0,0 +1,42 @@
> +* Freescale queue Direct Memory Access Controller(qDMA) Controller
> +
> + The qDMA controller transfers blocks of data between one source and one or more
Why the indentation?
> +destinations. The blocks of data transferred can be represented in memory as contiguous
> +or non-contiguous using scatter/gather table(s). Channel virtualization is supported
> +through enqueuing of DMA jobs to, or dequeuing DMA jobs from, different work
> +queues.
> +
> +* qDMA Controller
> +Required properties:
> +- compatible :
Add "Should be one of:"
> + - "fsl,ls1021a-qdma",
> + Or "fsl,ls1043a-qdma" followed by "fsl,ls1021a-qdma",
Then remove the "Or" and replace " followed by" with a comma (like dts
source).
> +- reg : Specifies base physical address(s) and size of the qDMA registers.
> + The region is qDMA control register's address and size.
> +- interrupts : A list of interrupt-specifiers, one for each entry in
> + interrupt-names.
> +- interrupt-names : Should contain:
> + "qdma-error" - the error interrupt
> + "qdma-queue" - the queue interrupt
> +- channels : Number of channels supported by the controller
dma-channels is the standard name.
> +- queues : Number of queues supported by driver
Needs a vendor prefix.
> +
> +Optional properties:
> +- big-endian: If present registers and hardware scatter/gather descriptors
> + of the qDMA are implemented in big endian mode, otherwise in little
> + mode.
> +
> +
> +Examples:
> +
> + qdma: qdma@8390000 {
Use standard node names:
dma-controller@...
> + compatible = "fsl,ls1021a-qdma";
> + reg = <0x0 0x8398000 0x0 0x2000 /* Controller registers */
> + 0x0 0x839a000 0x0 0x2000>; /* Block registers */
> + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "qdma-error", "qdma-queue";
> + channels = <8>;
> + queues = <2>;
> + big-endian;
> + };
> --
> 2.14.1
>
> --
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^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: i2c: Add MediaTek MT2712 i2c binding
From: Rob Herring @ 2017-12-20 18:43 UTC (permalink / raw)
To: Jun Gao
Cc: Wolfram Sang, Matthias Brugger, srv_heupstream, devicetree,
linux-i2c, linux-arm-kernel, linux-kernel, linux-mediatek
In-Reply-To: <1513666263-6443-2-git-send-email-jun.gao@mediatek.com>
On Tue, Dec 19, 2017 at 02:51:01PM +0800, Jun Gao wrote:
> From: Jun Gao <jun.gao@mediatek.com>
>
> Add MT2712 i2c binding to binding file. Compare to MT8173 i2c
> controller, MT2712 has timing adjust registers which can adjust
> the internal divider of i2c source clock, SCL duty cycle, SCL
> compare point, start(repeated start) and stop time, SDA change
> time.
>
> Signed-off-by: Jun Gao <jun.gao@mediatek.com>
> ---
> Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v3 2/6] media: dt: bindings: Update binding documentation for sunxi IR controller
From: Rob Herring @ 2017-12-20 18:44 UTC (permalink / raw)
To: Philipp Rossak
Cc: mchehab-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, sean-hENCXIMQXOg,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, andi.shyti-Sze3O3UU22JBDgjK7y7TUQ,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20171219080747.4507-3-embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Tue, Dec 19, 2017 at 09:07:43AM +0100, Philipp Rossak wrote:
> This patch updates documentation for Device-Tree bindings for sunxi IR
> controller and adds the new optional property for the base clock
> frequency.
>
> Signed-off-by: Philipp Rossak <embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
^ permalink raw reply
* Re: [PATCH v2 2/3] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7
From: Rob Herring @ 2017-12-20 18:57 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Lorenzo Pieralisi, Bjorn Helgaas, Mark Rutland,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pci-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0
In-Reply-To: <20171219085823.8695-3-kishon-l0cyMroinI0@public.gmane.org>
On Tue, Dec 19, 2017 at 02:28:22PM +0530, Kishon Vijay Abraham I wrote:
> Add syscon properties required for configuring PCIe in x2 lane mode.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
> Signed-off-by: Sekhar Nori <nsekhar-l0cyMroinI0@public.gmane.org>
> ---
> Documentation/devicetree/bindings/pci/ti-pci.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
> index 82cb875e4cec..bfbc77ac7355 100644
> --- a/Documentation/devicetree/bindings/pci/ti-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
> @@ -13,6 +13,12 @@ PCIe DesignWare Controller
> - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
> where <X> is the instance number of the pcie from the HW spec.
> - num-lanes as specified in ../designware-pcie.txt
> + - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system control
> + module and the register offset to specify 1 lane or
> + 2 lane.
> + - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
> + module and the register offset to specify lane
> + selection.
Adding a property for every syscon register doesn't really scale and
doesn't work if the register layout changes.
Rob
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* Re: [PATCH v5 3/4] ARM: dts: tegra20: Add device tree node to describe IRAM
From: Thierry Reding @ 2017-12-20 19:19 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Jonathan Hunter, Stephen Warren, Greg Kroah-Hartman,
Mauro Carvalho Chehab, Hans Verkuil, Vladimir Zapolskiy,
Rob Herring, Dan Carpenter, linux-media-u79uwXL29TY76Z2rM5mHXA,
devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <92563f9030ab413ff8f6d5a6b6a5680124ec4d98.1513038011.git.digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
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On Tue, Dec 12, 2017 at 03:26:09AM +0300, Dmitry Osipenko wrote:
> From: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
>
> All Tegra20 SoCs contain 256KiB IRAM, which is used to store
> resume code and by a video decoder engine.
>
> Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/boot/dts/tegra20.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
Applied, thanks.
Thierry
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* Re: [PATCH v5 4/4] ARM: dts: tegra20: Add video decoder node
From: Thierry Reding @ 2017-12-20 19:19 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Jonathan Hunter, Stephen Warren, Greg Kroah-Hartman,
Mauro Carvalho Chehab, Hans Verkuil, Vladimir Zapolskiy,
Rob Herring, Dan Carpenter, linux-media-u79uwXL29TY76Z2rM5mHXA,
devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <e80456489c7802e768883ded842e7818158168c4.1513038011.git.digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
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On Tue, Dec 12, 2017 at 03:26:10AM +0300, Dmitry Osipenko wrote:
> Add Video Decoder Engine device node.
>
> Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/boot/dts/tegra20.dtsi | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
Applied, thanks.
Thierry
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^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: ARM: Mediatek: Fix ethsys documentation
From: Michael Turquette @ 2017-12-20 19:26 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd
Cc: linux-I+IVW8TIWO2tmTQ+vhA3Yw, sean.wang-NuS5LvNUpcJWk0Htik3J/w,
chen.zhong-NuS5LvNUpcJWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <06b927e4-ed1b-9e1a-becf-e2818e7efe6d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Quoting Matthias Brugger (2017-12-20 09:13:12)
>
>
> On 12/19/2017 02:32 AM, Stephen Boyd wrote:
> > On 12/14, Matthias Brugger wrote:
> >> Hi Stephen, Michael,
> >>
> >> On 12/01/2017 01:07 PM, Matthias Brugger wrote:
> >>> The ethsys registers a reset controller, so we need to specify a
> >>> reset cell. This patch fixes the documentation.
> >>>
> >>> Signed-off-by: Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> >>> ---
> >>> Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
> >>> 1 file changed, 1 insertion(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> >>> index 7aa3fa167668..6cc7840ff37a 100644
> >>> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> >>> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> >>> @@ -20,4 +20,5 @@ ethsys: clock-controller@1b000000 {
> >>> compatible = "mediatek,mt2701-ethsys", "syscon";
> >>> reg = <0 0x1b000000 0 0x1000>;
> >>> #clock-cells = <1>;
> >>> + #reset-cells = <1>;
> >>> };
> >>>
> >>
> >> Will you take this patch through the clk tree, or shall I take it through my SoC
> >> tree?
> >>
> >
> > It's resets, we are clk maintainers. I'm clkfused.
> >
> > You can take it, along with my
> >
> > Acked-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> >
> > if you like/expect conflicts.
> >
>
> These are resets in the clock IP-block. I'll take it through my branch, I don't
> expect any conflicts.
Sounds good to me.
Best regards,
Mike
>
> Regards,
> Matthias
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* [PATCH 1/2] arm64: dts: exynos: Use lower case hex addresses in node unit addresses
From: Krzysztof Kozlowski @ 2017-12-20 19:27 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
Kukjin Kim, Krzysztof Kozlowski, Chanwoo Choi, Marek Szyprowski,
Andrzej Hajda, Alim Akhtar, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Convert all hex addresses in node unit addresses to lower case to
fix warnings like:
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dtb: Warning (simple_bus_reg):
Node /soc/video-scaler@13C00000 simple-bus unit address format error, expected "13c00000"
Conversion was done using sed:
$ sed -e 's/@\([a-zA-Z0-9_-]*\) {/@\L\1 {/' -i arch/arm64/boot/dts/exynos/*.dts*
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 8 ++++----
arch/arm64/boot/dts/exynos/exynos7.dtsi | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 1962b8074349..0ba5df825eff 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -994,7 +994,7 @@
reg = <0x145f0000 0x1038>;
};
- gsc_0: video-scaler@13C00000 {
+ gsc_0: video-scaler@13c00000 {
compatible = "samsung,exynos5433-gsc";
reg = <0x13c00000 0x1000>;
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
@@ -1008,7 +1008,7 @@
power-domains = <&pd_gscl>;
};
- gsc_1: video-scaler@13C10000 {
+ gsc_1: video-scaler@13c10000 {
compatible = "samsung,exynos5433-gsc";
reg = <0x13c10000 0x1000>;
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
@@ -1022,7 +1022,7 @@
power-domains = <&pd_gscl>;
};
- gsc_2: video-scaler@13C20000 {
+ gsc_2: video-scaler@13c20000 {
compatible = "samsung,exynos5433-gsc";
reg = <0x13c20000 0x1000>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
@@ -1049,7 +1049,7 @@
power-domains = <&pd_mscl>;
};
- mfc: codec@152E0000 {
+ mfc: codec@152e0000 {
compatible = "samsung,exynos5433-mfc";
reg = <0x152E0000 0x10000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 9a3fbed1765a..3504837b1d43 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -103,7 +103,7 @@
#size-cells = <1>;
ranges;
- pdma0: pdma@10E10000 {
+ pdma0: pdma@10e10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10E10000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
@@ -114,7 +114,7 @@
#dma-requests = <32>;
};
- pdma1: pdma@10EB0000 {
+ pdma1: pdma@10eb0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10EB0000 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
--
2.11.0
^ permalink raw reply related
* [PATCH 2/2] arm64: dts: exynos: Fix typo in MSCL clock controller unit address
From: Krzysztof Kozlowski @ 2017-12-20 19:27 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
Kukjin Kim, Krzysztof Kozlowski, Chanwoo Choi, Marek Szyprowski,
Andrzej Hajda, Alim Akhtar, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
In-Reply-To: <20171220192702.32515-1-krzk@kernel.org>
Fix typo in unit address of MSCL clock controller (the reg entry is
correct).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 0ba5df825eff..3e8311c60d1b 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -468,7 +468,7 @@
clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
};
- cmu_mscl: clock-controller@105d0000 {
+ cmu_mscl: clock-controller@150d0000 {
compatible = "samsung,exynos5433-cmu-mscl";
reg = <0x150d0000 0x1000>;
#clock-cells = <1>;
--
2.11.0
^ permalink raw reply related
* Re: [PATCH V4 3/7] PCI: tegra: Remove PCI_REASSIGN_ALL_BUS flag for Tegra PCIe
From: Thierry Reding @ 2017-12-20 19:30 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Manikanta Maddireddy, cyndis-/1wQRMveznE,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, jonathanh-DDmLM1+adcrQT0dZR+AlfA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, rjw-LthD3rsA81gm4RdzfppkhA,
tglx-hfZtesqFncYOwBW4kG4KsQ, vidyas-DDmLM1+adcrQT0dZR+AlfA,
kthota-DDmLM1+adcrQT0dZR+AlfA, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171215173643.GA1050@red-moon>
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On Fri, Dec 15, 2017 at 05:36:43PM +0000, Lorenzo Pieralisi wrote:
> On Fri, Dec 08, 2017 at 02:28:09PM +0530, Manikanta Maddireddy wrote:
> > Primary, secondary and subordinate default bus numbers are 0 in Tegra and
> > it is expecting SW to program these numbers in configration space.
> >
> > pci_scan_bridge_extend() function programs these numbers in configuration
> > space if secondary & subordinate bus numbers are 0 or PCI_REASSIGN_ALL_BUS
> > flag is set. Since secondary & subordinate default bus numbers are 0,
> > PCI_REASSIGN_ALL_BUS flag can be removed for Tegra PCIe.
> >
> > Signed-off-by: Manikanta Maddireddy <mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> > ---
> > V3:
> > * new patch in V3
> > V4:
> > * no change in this patch
> >
> > drivers/pci/host/pci-tegra.c | 1 -
> > 1 file changed, 1 deletion(-)
> >
> > diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> > index a549c5899e26..0d91f1a3a6b4 100644
> > --- a/drivers/pci/host/pci-tegra.c
> > +++ b/drivers/pci/host/pci-tegra.c
> > @@ -2604,7 +2604,6 @@ static int tegra_pcie_probe(struct platform_device *pdev)
> >
> > tegra_pcie_enable_ports(pcie);
> >
> > - pci_add_flags(PCI_REASSIGN_ALL_BUS);
>
> This looks obviously OK to me but I need Thierry's ACK to queue it.
Just as an additional note: I think the real reason why this is okay to
do is because we reset the PCI host controller in the kernel driver, so
any bus assignments done by the firmware are reset as well.
Acked-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support
From: Joao Pinto @ 2017-12-20 19:47 UTC (permalink / raw)
To: Lorenzo Pieralisi, Niklas Cassel, Jingoo Han, Joao Pinto
Cc: linux-arm-kernel-VrBV9hrLPhE, linux-pci-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA, Niklas Cassel,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171220173416.GD1709@red-moon>
Hello to all,
Às 5:34 PM de 12/20/2017, Lorenzo Pieralisi escreveu:
> On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas Cassel wrote:
>> This is a series that adds:
>> - PCI endpoint mode support in the ARTPEC-6 driver.
>> - ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar).
>> - Small fixes for MSI in designware-ep and designware-host,
>> needed to get endpoint mode support working for ARTPEC-6.
>> - Cleanups in pci-dra7xx to better prepare for endpoint mode in other
>> DWC based PCIe drivers.
>
> Joao, Jingoo,
>
> Gustavo tested the series and Kishon ACK'ed the relevant patches,
> I need your ACKs on designware patches to queue this series for
> v4.16.
>
> I am away from tomorrow (noon) till beginning of January which means
> that either I queue this series tomorrow or at -rc6, please do
> chime in if you can.
Sorry, I have been a bit tied up! Already checked each patch related to DWC.
Could anyone from artpec finish the revision, since there are some patches
related to that SoC?
Thanks,
Joao
>
> Thanks,
> Lorenzo
>
>> Changes since V5:
>> -Dropped GFP_DMA32 from "PCI: dwc: Use the DMA-API to get the MSI address"
>> so that we use the exact same GFP flags as before.
>> -Rewrote commit message for "PCI: dwc: Make cpu_addr_fixup take struct
>> dw_pcie as argument" to be more detailed.
>>
>> Niklas Cassel (18):
>> PCI: dwc: Use the DMA-API to get the MSI address
>> PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits
>> PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be
>> writable
>> PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init
>> PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar()
>> PCI: designware-ep: Add generic function for raising MSI irq
>> PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep
>> mode
>> PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than
>> in probe
>> PCI: dwc: dra7xx: Help compiler to remove unused code
>> PCI: dwc: artpec6: Remove unused defines
>> PCI: dwc: artpec6: Use BIT and GENMASK macros
>> PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller
>> functions
>> bindings: PCI: artpec: Add support for endpoint mode
>> PCI: dwc: artpec6: Add support for endpoint mode
>> PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument
>> PCI: dwc: artpec6: Deassert the core before waiting for PHY
>> bindings: PCI: artpec: Add support for the ARTPEC-7 SoC
>> PCI: dwc: artpec6: Add support for the ARTPEC-7 SoC
>>
>> .../devicetree/bindings/pci/axis,artpec6-pcie.txt | 5 +-
>> drivers/pci/dwc/Kconfig | 68 +--
>> drivers/pci/dwc/Makefile | 4 +-
>> drivers/pci/dwc/pci-dra7xx.c | 27 +-
>> drivers/pci/dwc/pcie-artpec6.c | 470 ++++++++++++++++++---
>> drivers/pci/dwc/pcie-designware-ep.c | 59 ++-
>> drivers/pci/dwc/pcie-designware-host.c | 15 +-
>> drivers/pci/dwc/pcie-designware.c | 2 +-
>> drivers/pci/dwc/pcie-designware.h | 22 +-
>> 9 files changed, 554 insertions(+), 118 deletions(-)
>>
>> --
>> 2.14.2
>>
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* [PATCH 0/9] Add sound support
From: Biju Das @ 2017-12-20 20:01 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree, linux-renesas-soc, Biju Das
This series aims to add sound support for iWave RZ/G1E board.
Biju Das (9):
ARM: dts: r8a7745: Add audio clocks
ARM: dts: r8a7745: Add audio DMAC support
ARM: dts: r8a7745: Add sound support
ARM: dts: iwg22d-sodimm: Enable SGTL5000 audio codec
ARM: dts: iwg22d-sodimm: Sound PIO support
ARM: dts: iwg22d-sodimm: Sound DMA support on DTS
ARM: dts: iwg22d-sodimm: Sound DMA support via BUSIF on DTS
ARM: dts: iwg22d-sodimm: Sound DMA support via SRC on DTS
ARM: dts: iwg22d-sodimm: Sound DMA support via DVC on DTS
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 92 +++++++++++
arch/arm/boot/dts/r8a7745.dtsi | 232 ++++++++++++++++++++++++++++
2 files changed, 324 insertions(+)
--
1.9.1
^ permalink raw reply
* [PATCH 1/9] ARM: dts: r8a7745: Add audio clocks
From: Biju Das @ 2017-12-20 20:01 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Biju Das
In-Reply-To: <1513800125-53213-1-git-send-email-biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
Describe the external audio clocks required by the sound driver.
Boards that provide audio clocks need to override the clock frequencies.
Signed-off-by: Biju Das <biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
Reviewed-by: Fabrizio Castro <fabrizio.castro-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
---
arch/arm/boot/dts/r8a7745.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 2be7485..6d085f0 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -35,6 +35,27 @@
vin1 = &vin1;
};
+ /*
+ * The external audio clocks are configured as 0 Hz fixed
+ * frequency clocks by default. Boards that provide audio
+ * clocks should override them.
+ */
+ audio_clka: audio_clka {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clkb: audio_clkb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clkc: audio_clkc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
/* External CAN clock */
can_clk: can {
compatible = "fixed-clock";
--
1.9.1
--
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* [PATCH 2/9] ARM: dts: r8a7745: Add audio DMAC support
From: Biju Das @ 2017-12-20 20:01 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree, linux-renesas-soc, Biju Das
In-Reply-To: <1513800125-53213-1-git-send-email-biju.das@bp.renesas.com>
Instantiate the audio DMA controller on the r8a7745 device tree.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm/boot/dts/r8a7745.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 6d085f0..d9488a1 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -397,6 +397,37 @@
dma-channels = <15>;
};
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7745",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,r8a7745-usb-dmac",
"renesas,usb-dmac";
--
1.9.1
^ permalink raw reply related
* [PATCH 3/9] ARM: dts: r8a7745: Add sound support
From: Biju Das @ 2017-12-20 20:01 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Biju Das
In-Reply-To: <1513800125-53213-1-git-send-email-biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
Define the generic r8a7745(RZ/G1E) part of the sound device node.
This patch is based on the r8a7794 sound work by Sergei Shtylyov.
Signed-off-by: Biju Das <biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
Reviewed-by: Fabrizio Castro <fabrizio.castro-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
---
arch/arm/boot/dts/r8a7745.dtsi | 180 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 180 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index d9488a1..835a282 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -1293,6 +1293,186 @@
resets = <&cpg 915>;
status = "disabled";
};
+
+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7745",
+ "renesas,rcar_sound-gen2";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
+ <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
+ <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
+ <&cpg CPG_CORE R8A7745_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.6", "src.5", "src.4", "src.3",
+ "src.2", "src.1",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>, <&cpg 1008>,
+ <&cpg 1009>, <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>, <&cpg 1014>,
+ <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma0 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma0 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src-0 {
+ status = "disabled";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma0 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma0 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma0 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma0 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma0 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma0 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma0 0x02>,
+ <&audma0 0x15>, <&audma0 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma0 0x04>,
+ <&audma0 0x49>, <&audma0 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma0 0x06>,
+ <&audma0 0x63>, <&audma0 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma0 0x08>,
+ <&audma0 0x6f>, <&audma0 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma0 0x0a>,
+ <&audma0 0x71>, <&audma0 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma0 0x0c>,
+ <&audma0 0x73>, <&audma0 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma0 0x0e>,
+ <&audma0 0x75>, <&audma0 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma0 0x10>,
+ <&audma0 0x79>, <&audma0 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma0 0x12>,
+ <&audma0 0x7b>, <&audma0 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma0 0x14>,
+ <&audma0 0x7d>, <&audma0 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ };
+ };
};
timer {
--
1.9.1
--
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^ permalink raw reply related
* [PATCH 4/9] ARM: dts: iwg22d-sodimm: Enable SGTL5000 audio codec
From: Biju Das @ 2017-12-20 20:02 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree, linux-renesas-soc, Biju Das
In-Reply-To: <1513800125-53213-1-git-send-email-biju.das@bp.renesas.com>
This patch enables SGTL5000 audio codec on the carrier board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index 39ce7e7..5d4b7d2 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -26,6 +26,12 @@
stdout-path = "serial3:115200n8";
};
+ audio_clock: audio_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
@@ -80,6 +86,23 @@
pinctrl-names = "default";
};
+&i2c5 {
+ pinctrl-0 = <&i2c5_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ #sound-dai-cells = <0>;
+ reg = <0x0a>;
+ clocks = <&audio_clock>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+};
+
&pci1 {
status = "okay";
pinctrl-0 = <&usb1_pins>;
@@ -102,6 +125,11 @@
function = "hscif1";
};
+ i2c5_pins: i2c5 {
+ groups = "i2c5_b";
+ function = "i2c5";
+ };
+
scif4_pins: scif4 {
groups = "scif4_data_b";
function = "scif4";
--
1.9.1
^ permalink raw reply related
* [PATCH 5/9] ARM: dts: iwg22d-sodimm: Sound PIO support
From: Biju Das @ 2017-12-20 20:02 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Biju Das
In-Reply-To: <1513800125-53213-1-git-send-email-biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
Enable sound PIO support on carrier board.
Signed-off-by: Biju Das <biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
Reviewed-by: Fabrizio Castro <fabrizio.castro-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 46 +++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index 5d4b7d2..b6521da 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -32,6 +32,21 @@
clock-frequency = <26000000>;
};
+ rsnd_sgtl5000: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&sndcodec>;
+ simple-audio-card,frame-master = <&sndcodec>;
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ };
+ };
+
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
@@ -141,6 +156,11 @@
power-source = <3300>;
};
+ sound_pins: sound {
+ groups = "ssi34_ctrl", "ssi3_data", "ssi4_data";
+ function = "ssi";
+ };
+
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
@@ -152,6 +172,23 @@
};
};
+&rcar_sound {
+ pinctrl-0 = <&sound_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* Single DAI */
+
+ #sound-dai-cells = <0>;
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi3>;
+ capture = <&ssi4>;
+ };
+ };
+};
+
&scif4 {
pinctrl-0 = <&scif4_pins>;
pinctrl-names = "default";
@@ -169,6 +206,15 @@
status = "okay";
};
+&ssi3 {
+ pio-transfer;
+};
+
+&ssi4 {
+ pio-transfer;
+ shared-pin;
+};
+
&usbphy {
status = "okay";
};
--
1.9.1
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^ permalink raw reply related
* [PATCH 6/9] ARM: dts: iwg22d-sodimm: Sound DMA support on DTS
From: Biju Das @ 2017-12-20 20:02 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree, linux-renesas-soc, Biju Das
In-Reply-To: <1513800125-53213-1-git-send-email-biju.das@bp.renesas.com>
DMA transfer to/from SSI
DMA
[MEM] -> [SSI]
DMA
[MEM] <- [SSI]
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index b6521da..a9ba46d 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -207,11 +207,11 @@
};
&ssi3 {
- pio-transfer;
+ no-busif;
};
&ssi4 {
- pio-transfer;
+ no-busif;
shared-pin;
};
--
1.9.1
^ permalink raw reply related
* [PATCH 7/9] ARM: dts: iwg22d-sodimm: Sound DMA support via BUSIF on DTS
From: Biju Das @ 2017-12-20 20:02 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Biju Das
In-Reply-To: <1513800125-53213-1-git-send-email-biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
DMA transfer to/from SSIU
DMA
[MEM] -> [SSIU] -> [SSI]
DMA
[MEM] <- [SSIU] <- [SSI]
Signed-off-by: Biju Das <biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
Reviewed-by: Fabrizio Castro <fabrizio.castro-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index a9ba46d..0f880c1 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -206,12 +206,7 @@
status = "okay";
};
-&ssi3 {
- no-busif;
-};
-
&ssi4 {
- no-busif;
shared-pin;
};
--
1.9.1
--
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^ permalink raw reply related
* [PATCH 8/9] ARM: dts: iwg22d-sodimm: Sound DMA support via SRC on DTS
From: Biju Das @ 2017-12-20 20:02 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree, linux-renesas-soc, Biju Das
In-Reply-To: <1513800125-53213-1-git-send-email-biju.das@bp.renesas.com>
DMA transfer to/from SRC
DMA DMApp
[MEM] -> [SRC] -> [SSIU] -> [SSI]
DMA DMApp
[MEM] <- [SRC] <- [SSIU] <- [SSI]
Current sound driver is supporting SSI/SRC random connection.
So, this patch is trying
SSI3 -> SRC3
SSI4 <- SRC4
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index 0f880c1..2cac57c 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -183,8 +183,8 @@
rcar_sound,dai {
dai0 {
- playback = <&ssi3>;
- capture = <&ssi4>;
+ playback = <&ssi3 &src3>;
+ capture = <&ssi4 &src4>;
};
};
};
--
1.9.1
^ permalink raw reply related
* [PATCH 9/9] ARM: dts: iwg22d-sodimm: Sound DMA support via DVC on DTS
From: Biju Das @ 2017-12-20 20:02 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree, linux-renesas-soc, Biju Das
In-Reply-To: <1513800125-53213-1-git-send-email-biju.das@bp.renesas.com>
DMA transfer uses DVC
DMA DMApp
[MEM] -> [SRC] -> [DVC] -> [SSIU] -> [SSI]
DMA DMApp
[MEM] <- [DVC] <- [SRC] <- [SSIU] <- [SSI]
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 27 +++++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index 2cac57c..a4058f4 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -8,6 +8,29 @@
* kind, whether express or implied.
*/
+/*
+ * SSI-SGTL5000
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer set "DVC Out" 100%
+ * amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ * amixer set "DVC Out Mute" on
+ * amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
+ * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ * amixer set "DVC Out Ramp" on
+ * aplay xxx.wav &
+ * amixer set "DVC Out" 80% // Volume Down
+ * amixer set "DVC Out" 100% // Volume Up
+ */
+
/dts-v1/;
#include "r8a7745-iwg22m.dtsi"
@@ -183,8 +206,8 @@
rcar_sound,dai {
dai0 {
- playback = <&ssi3 &src3>;
- capture = <&ssi4 &src4>;
+ playback = <&ssi3 &src3 &dvc0>;
+ capture = <&ssi4 &src4 &dvc1>;
};
};
};
--
1.9.1
^ permalink raw reply related
* [PATCH v16 0/5] ZII RAVE platform driver
From: Andrey Smirnov @ 2017-12-20 20:45 UTC (permalink / raw)
To: Lee Jones
Cc: Andrey Smirnov, Pavel Machek, Greg Kroah-Hartman,
cphealy-Re5JQEeQqe8AvxtiuMwx3w, Andy Shevchenko, Lucas Stach,
Nikita Yushchenko, Guenter Roeck, Rob Herring, Mark Rutland,
Johan Hovold, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Sebastian Reichel,
Philippe Ombredanne
Everyone:
This patch series is v16 of the driver for supervisory processor found
on RAVE series of devices from ZII. Supervisory processor is a PIC
microcontroller connected to various electrical subsystems on RAVE
devices whose firmware implements protocol to command/qery them.
NOTE:
* This driver dependends on crc_ccitt_false(), added by
2da9378d531f8cc6670c7497f20d936b706ab80b in 'linux-next', the patch
was pulled in by Andrew Morton and is currently avaiting users, so
this series might have to go in through Andrew's tree
Changes since [v15]:
- Adopted SPDX tags for licensing information per Philippe's
request
Changes since [v14]:
- Fixed a bug in deframer code where byte processing loop was not
being terminated early is it should've been. This would result,
among other things, in packets of maximum valid length being
incorrectly reported as tool long.
- Increased command timeout value in support other valid commands
that are outsied of scope for this patch set.
- Converted watchdog driver to differentiate between variants
based on its own compatiblity string as opposed to relying on
that of parent MFD device (as per request by Johan and Lee).
NOTE: This change didn't seem to change DT bingins enough to
warrant dropping any Acks for patches affected, so I kept
them. If anyone wants to rescind their Ack, please let me know.
- Collected Acked-by from Pavel
- Collected Acked-by from Lee (for patch 3/5)
Changes since [v13]:
- Fixed incorrect MFD driver menuconfig entry placement
Changes since [v12]:
- Minor comment inconsistencies fixes in rave-sp.c
Changes since [v11]:
- Fix incorrect include in rave-sp-wdt.c as uncovered by kernel
test robot
Changes since [v10]:
- Collected Acked-by from Rob and Reviewed-by from Guenter
- Incorporated watchdog driver feedback from Gunter and Johan
- Incorporated Johan's feedback for the rest of the code
Changes since [v9]:
- Converted watchdog driver to use watchdog_active() instead of
watchdog_hw_running() and replaced WARN_ON with a regular error
message as per feedback from Guenter
- Changed rave_sp_wdt_start() to set WDOG_HW_RUNNING only if
communicating with hardware was sucessful
- Collected Reviewd-by from Sebastian (for serdev related patches)
- Collected Acked-by from Rob (for watchdog DT bindings)
Changes since [v8]:
- Driver moved from drivers/platform to drivers/mfd
- Collected Reviewed-by from Guenter (for patches 1, 2 and 3)
- Incorporated feedback from Guenter into watchdog driver
- Incorporated feedback from Rob into watchdog DT bindings
- Removed struct rave_sp_rsp_status, which was a leftover from v5
-> v6 code removal.
- Fixed minor problems reported by checkpatch
Changes since [v7]:
- Added watchdog driver to the patchset, so it would be easier to
understand how parent/children drivers are tied together
- Added serdev patches to implement devm_serdev_device_open() and make .remove optional
- "Added" missing serdev_device_close() by converting the driver
to use devm_serdev_device_open()
- Converted the driver to use devm_of_platform_populate()
- Removed needless dependency on MFD_CORE
- Removed dependency on SERIAL_DEV_CTRL_TTYPORT
Changes since [v6]:
- Patch 2/2 has been applied by Lee so it is no longer a part of the series
- Removed all sysfs and debugfs attribute to reduce the scope of
the driver propsed for inclusion. This is not a critical to have
feature and can be added/discussed later.
Changes since [v5]:
- Fixed a build break, introduced by a last minute change in [v5]
- Moved majority of attributes that were exposed over sysfs to debugfs
- Document remaining sysfs attributes in Documentation/ABI/testing/sysfs-platform-rave-sp
Changes since [v4]:
- Replaced usage of DEVICE_ATTR with DEVICE_ATTR_RW
- Fixed a number of warnings produces by sparse tool
- Incorporated event more feedback from Andy Shevchenko
- Collected Reviewed-by from Andy
Changes since [v3]:
- Re-collected lost Acked-by from Rob
- Incorporated further feedback from Andy Shevchenko
- Dropped useless change (stray newline) to drivers/mfd/Makefile
Changes since [v2]:
- Fixed swapped command codes in rave_sp_common_get_boot_source()
and rave_sp_common_set_boot_source() revealed by further testing
of the code
- Incorporated feedback from Andy Shevchenko
Changes since [v1]:
- Updated wording in DT-bindings as per Rob's request.
- Collected Rob's Acked-by for patch 2/2
Feedback is greatly appreciated!
Thanks,
Andrey Smirnov
[v15] lkml.kernel.org/r/20171220040017.7605-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v14] lkml.kernel.org/r/20171207162735.25873-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v13] lkml.kernel.org/r/20171204161118.19558-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v12] lkml.kernel.org/r/20171109160556.17018-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v11] lkml.kernel.org/r/20171106152935.16920-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v10] lkml.kernel.org/r/20171031163656.24552-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v9] lkml.kernel.org/r/20171025190421.18415-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v8] lkml.kernel.org/r/20171018170136.12347-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v7] lkml.kernel.org/r/20171013061321.31252-2-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v6] lkml.kernel.org/r/20170828163131.24815-2-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v5] lkml.kernel.org/r/20170728142704.11156-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v4] lkml.kernel.org/r/20170725184450.13171-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v3] lkml.kernel.org/r/20170724150915.4824-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v2] lkml.kernel.org/r/20170718175604.11735-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v1] lkml.kernel.org/r/20170710170449.4544-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Andrey Smirnov (5):
serdev: Make .remove in struct serdev_device_driver optional
serdev: Introduce devm_serdev_device_open()
mfd: Add driver for RAVE Supervisory Processor
watchdog: Add RAVE SP watchdog driver
dt-bindings: watchdog: Add bindings for RAVE SP watchdog driver
.../bindings/watchdog/zii,rave-sp-wdt.txt | 39 ++
Documentation/driver-model/devres.txt | 3 +
drivers/mfd/Kconfig | 8 +
drivers/mfd/Makefile | 2 +
drivers/mfd/rave-sp.c | 710 +++++++++++++++++++++
drivers/tty/serdev/core.c | 31 +-
drivers/watchdog/Kconfig | 7 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/rave-sp-wdt.c | 337 ++++++++++
include/linux/mfd/rave-sp.h | 60 ++
include/linux/serdev.h | 1 +
11 files changed, 1197 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt
create mode 100644 drivers/mfd/rave-sp.c
create mode 100644 drivers/watchdog/rave-sp-wdt.c
create mode 100644 include/linux/mfd/rave-sp.h
--
2.14.3
--
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^ permalink raw reply
* [PATCH v16 5/5] dt-bindings: watchdog: Add bindings for RAVE SP watchdog driver
From: Andrey Smirnov @ 2017-12-20 20:45 UTC (permalink / raw)
To: Lee Jones
Cc: Andrey Smirnov, linux-kernel, devicetree, linux-watchdog, cphealy,
Lucas Stach, Nikita Yushchenko, Greg Kroah-Hartman, Pavel Machek,
Andy Shevchenko, Guenter Roeck, Rob Herring, Johan Hovold,
Mark Rutland, Sebastian Reichel, Philippe Ombredanne
In-Reply-To: <20171220204517.28313-1-andrew.smirnov@gmail.com>
Add Device Tree bindings for RAVE SP watchdog drvier - an MFD cell of
parent RAVE SP driver (documented in
Documentation/devicetree/bindings/mfd/zii,rave-sp.txt).
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-watchdog@vger.kernel.org
Cc: cphealy@gmail.com
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Rob Herring <robh@kernel.org>
Cc: Johan Hovold <johan@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Cc: Philippe Ombredanne <pombredanne@nexb.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
.../bindings/watchdog/zii,rave-sp-wdt.txt | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt b/Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt
new file mode 100644
index 000000000000..3de96186e92e
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt
@@ -0,0 +1,39 @@
+Zodiac Inflight Innovations RAVE Supervisory Processor Watchdog Bindings
+
+RAVE SP watchdog device is a "MFD cell" device corresponding to
+watchdog functionality of RAVE Supervisory Processor. It is expected
+that its Device Tree node is specified as a child of the node
+corresponding to the parent RAVE SP device (as documented in
+Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
+
+Required properties:
+
+- compatible: Depending on wire protocol implemented by RAVE SP
+ firmware, should be one of:
+ - "zii,rave-sp-watchdog"
+ - "zii,rave-sp-watchdog-legacy"
+
+Optional properties:
+
+- wdt-timeout: Two byte nvmem cell specified as per
+ Documentation/devicetree/bindings/nvmem/nvmem.txt
+
+Example:
+
+ rave-sp {
+ compatible = "zii,rave-sp-rdu1";
+ current-speed = <38400>;
+
+ eeprom {
+ wdt_timeout: wdt-timeout@8E {
+ reg = <0x8E 2>;
+ };
+ };
+
+ watchdog {
+ compatible = "zii,rave-sp-watchdog";
+ nvmem-cells = <&wdt_timeout>;
+ nvmem-cell-names = "wdt-timeout";
+ };
+ }
+
--
2.14.3
^ permalink raw reply related
* Re: [PATCH 1/2] dt-bindings: phy: ti-pipe3: Add dt binding to use USB3 PHY for PCIe
From: Rob Herring @ 2017-12-20 20:55 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Mark Rutland, devicetree, linux-pci, linux-kernel, nsekhar
In-Reply-To: <20171219094540.18432-2-kishon@ti.com>
On Tue, Dec 19, 2017 at 03:15:39PM +0530, Kishon Vijay Abraham I wrote:
> DRA72 uses USB3 PHY for the 2nd lane of PCIE. Add dt bindings property
> to indicate if the USB3 PHY should be used for 2nd lane of PCIe.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> Documentation/devicetree/bindings/phy/ti-phy.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
> index cd13e6157088..907a046e794b 100644
> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
> @@ -93,6 +93,8 @@ Optional properties:
> register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
> - syscon-pcs : phandle/offset pair. Phandle to the system control module and the
> register offset to write the PCS delay value.
> + - "ti,configure-as-pcie" : property to indicate if the PHY should be
> + configured as PCIE PHY.
This is not that uncommon as PCIe, 10Gb eth, USB3, SATA are all very
electrically similar and the same phy can drive all of them AIUI. The DT
already contains the necessary information too because you have a phys
property creating a link to PCI host. The problem is either the client
side would need to set the mode or you'd have to search all "phys"
properties to find the link. There's already a DT function to iterate
thru all named properties.
Rob
^ permalink raw reply
* Re: [PATCH v2 1/5] dt-bindings: mtd: add Marvell NAND controller documentation
From: Rob Herring @ 2017-12-20 21:05 UTC (permalink / raw)
To: Miquel Raynal
Cc: David Woodhouse, Brian Norris, Boris Brezillon, Marek Vasut,
Richard Weinberger, Cyrille Pitchen, Mark Rutland, Jason Cooper,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Russell King,
Daniel Mack, Haojian Zhuang, Robert Jarzmik, Eric Miao,
Catalin Marinas, Will Deacon, Ezequiel
In-Reply-To: <20171219132942.27433-2-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Tue, Dec 19, 2017 at 02:29:38PM +0100, Miquel Raynal wrote:
> Document the legacy and the new bindings for Marvell NAND controller.
>
> The pxa3xx_nand.c driver does only support legacy bindings, which are
> incomplete and inaccurate. A rework of this controller (called
> marvell_nand.c) does support both.
>
> Signed-off-by: Miquel Raynal <miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
> .../devicetree/bindings/mtd/marvell-nand.txt | 123 +++++++++++++++++++++
> 1 file changed, 123 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/marvell-nand.txt
>
> diff --git a/Documentation/devicetree/bindings/mtd/marvell-nand.txt b/Documentation/devicetree/bindings/mtd/marvell-nand.txt
> new file mode 100644
> index 000000000000..aa6a1ed045b2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/marvell-nand.txt
> @@ -0,0 +1,123 @@
> +Marvell NAND Flash Controller (NFC)
> +
> +Required properties:
> +- compatible: can be one of the following:
> + * "marvell,armada-8k-nand-controller"
> + * "marvell,armada370-nand-controller"
> + * "marvell,pxa3xx-nand-controller"
> + * "marvell,armada-8k-nand" (deprecated)
> + * "marvell,armada370-nand" (deprecated)
> + * "marvell,pxa3xx-nand" (deprecated)
> + Compatibles marked deprecated support only the old bindings described
> + at the bottom.
> +- reg: NAND flash controller memory area.
> +- #address-cells: shall be set to 1. Encode the NAND CS.
> +- #size-cells: shall be set to 0.
> +- interrupts: shall define the NAND controller interrupt.
> +- clocks: shall reference the NAND controller clock.
> +- marvell,system-controller: Set to retrieve the syscon node that handles
> + NAND controller related registers (only required with the
> + "marvell,armada-8k-nand[-controller]" compatibles).
> +
> +Optional properties:
> +- label: see partition.txt. New platforms shall omit this property.
> +- dmas: shall reference DMA channel associated to the NAND controller.
> + This property is only used with "marvell,pxa3xx-nand[-controller]"
> + compatible strings.
> +- dma-names: shall be "rxtx".
> + This property is only used with "marvell,pxa3xx-nand[-controller]"
> + compatible strings.
> +
> +Optional children nodes:
> +Children nodes represent the available NAND chips.
> +
> +Required properties:
> +- reg: shall contain the native Chip Select ids (0-3)
> +- marvell,rb: shall contain the native Ready/Busy ids (0-1)
We already have at least 2 other <vendor>,rb properties. Let's not add a
3rd and make a common one instead.
> +
> +Optional properties:
> +- marvell,nand-keep-config: orders the driver not to take the timings
> + from the core and leaving them completely untouched. Bootloader
> + timings will then be used.
> +- label: MTD name.
> +- nand-on-flash-bbt: see nand.txt.
> +- nand-ecc-mode: see nand.txt. Will use hardware ECC if not specified.
> +- nand-ecc-algo: see nand.txt. This property may be added when using
> + hardware ECC for clarification but will be ignored by the driver
> + because ECC mode is chosen depending on the page size and the strength
> + required by the NAND chip. This value may be overwritten with
> + nand-ecc-strength property.
If not used, then drop it.
> +- nand-ecc-strength: see nand.txt.
> +- nand-ecc-step-size: see nand.txt. This has no effect and will be
> + ignored by the driver when using hardware ECC because Marvell's NAND
> + flash controller does use fixed strength (1-bit for Hamming, 16-bit
> + for BCH), so the step size will shrink or grow in order to fit the
> + required strength. Step sizes are not completely random for all and
> + follow certain patterns described in AN-379, "Marvell SoC NFC ECC".
Same here.
> +
> +See Documentation/devicetree/bindings/mtd/nand.txt for more details on
> +generic bindings.
> +
> +
> +Example:
> +nand_controller: nand-controller@d0000 {
> + compatible = "marvell,armada370-nand-controller";
> + reg = <0xd0000 0x54>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&coredivclk 0>;
> +
> + nand@0 {
> + reg = <0>;
> + label = "main-storage";
> + marvell,rb = <0>;
> + nand-ecc-mode = "hw";
> + marvell,nand-keep-config;
> + nand-on-flash-bbt;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "Rootfs";
> + reg = <0x00000000 0x40000000>;
> + };
> + };
> + };
> +};
> +
> +
> +Note on legacy bindings: One can find, in not-updated device trees,
> +bindings slightly differents than described above with other properties
s/differents/different/
> +described below as well as the partitions node at the root of a so
> +called "nand" node (without clear controller/chip separation).
> +
> +Legacy properties:
> +- marvell,nand-enable-arbiter: To enable the arbiter, all boards blindly
> + used it, this bit was set by the bootloader for many boards and even if
> + it is marked reserved in several datasheets, it might be needed to set
> + it (otherwise it is harmless) so whether or not this property is set,
> + the bit is selected by the driver.
> +- num-cs: Number of chip-select lines to use, all boards blindly set 1
> + to this and for a reason, other values would have failed. The value of
> + this property is ignored.
> +
> +Example:
> +
> + nand0: nand@43100000 {
> + compatible = "marvell,pxa3xx-nand";
> + reg = <0x43100000 90>;
> + interrupts = <45>;
> + dmas = <&pdma 97 0>;
> + dma-names = "rxtx";
> + #address-cells = <1>;
> + marvell,nand-keep-config;
> + marvell,nand-enable-arbiter;
> + num-cs = <1>;
> + /* Partitions (optional) */
> + };
> --
> 2.11.0
>
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