* Re: [PATCH v3 3/3] drm/tinydrm: add driver for ST7735R panels
From: David Lechner @ 2017-12-21 19:35 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Noralf Trønnes, limor-6aDhHjTmHzzR7s880joybQ, Linus Walleij,
Rob Herring, Mark Rutland, linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1513884233-31540-4-git-send-email-david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
On 12/21/2017 01:23 PM, David Lechner wrote:
> This adds a new driver for Sitronix ST7735R display panels.
>
> This has been tested using an Adafruit 1.8" TFT.
>
> Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
> ---
<snip>
> + mipi_dbi_command(mipi, ST7735R_GAMCTRP1, 0x0f, 0x1a, 0x0f, 0x18, 0x2f,
> + 0x28, 0x20, 0x22, 0x1f, 0x1b, 0x23, 0x37, 0x00, 0x07,
> + 0x02, 0x10);
> + mipi_dbi_command(mipi, ST7735R_GAMCTRN1, 0x0f, 0x1b, 0x0f, 0x17, 0x33,
> + 0x2c, 0x29, 0x2e, 0x30, 0x30, 0x39, 0x3f, 0x00, 0x07,
> + 0x03, 0x10);
By the way, how do you know what is the "right" gamma curve? I think I
copied this from the generic st7735r driver in fbtft, but I noticed that
there is also a different curve for the Adafruit 1.8" display in fbtft.
I'm wondering if I should have used that one instead. I can't really
tell a difference looking at the display.
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^ permalink raw reply
* [PATCH v3 3/3] drm/tinydrm: add driver for ST7735R panels
From: David Lechner @ 2017-12-21 19:23 UTC (permalink / raw)
To: dri-devel, devicetree
Cc: Mark Rutland, limor, David Lechner, linux-kernel, Rob Herring
In-Reply-To: <1513884233-31540-1-git-send-email-david@lechnology.com>
This adds a new driver for Sitronix ST7735R display panels.
This has been tested using an Adafruit 1.8" TFT.
Signed-off-by: David Lechner <david@lechnology.com>
---
v3 changes:
* Changed compatible string
* use SPDX license header
* Renamed mode struct to use panel name instead of controller name
v2 changes:
* Change delay from 10ms to 20ms to avoid checkpatch warning
* Use mipi_dbi_pipe_enable()/mipi_dbi_pipe_disable() to reduce duplicated code
* Rebase on drm-misc-next (tinydrm_lastclose => drm_fb_helper_lastclose)
* Use mipi_dbi_debugfs_init
* Add mipi->read_commands = NULL; since this display is write-only
MAINTAINERS | 6 ++
drivers/gpu/drm/tinydrm/Kconfig | 10 ++
drivers/gpu/drm/tinydrm/Makefile | 1 +
drivers/gpu/drm/tinydrm/st7735r.c | 215 ++++++++++++++++++++++++++++++++++++++
4 files changed, 232 insertions(+)
create mode 100644 drivers/gpu/drm/tinydrm/st7735r.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 91268cb..95e98e2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4556,6 +4556,12 @@ S: Maintained
F: drivers/gpu/drm/tinydrm/st7586.c
F: Documentation/devicetree/bindings/display/st7586.txt
+DRM DRIVER FOR SITRONIX ST7735R PANELS
+M: David Lechner <david@lechnology.com>
+S: Maintained
+F: drivers/gpu/drm/tinydrm/st7735r.c
+F: Documentation/devicetree/bindings/display/st7735r.txt
+
DRM DRIVER FOR TDFX VIDEO CARDS
S: Orphan / Obsolete
F: drivers/gpu/drm/tdfx/
diff --git a/drivers/gpu/drm/tinydrm/Kconfig b/drivers/gpu/drm/tinydrm/Kconfig
index 90c5bd5..b0e567d 100644
--- a/drivers/gpu/drm/tinydrm/Kconfig
+++ b/drivers/gpu/drm/tinydrm/Kconfig
@@ -52,3 +52,13 @@ config TINYDRM_ST7586
* LEGO MINDSTORMS EV3
If M is selected the module will be called st7586.
+
+config TINYDRM_ST7735R
+ tristate "DRM support for Sitronix ST7735R display panels"
+ depends on DRM_TINYDRM && SPI
+ select TINYDRM_MIPI_DBI
+ help
+ DRM driver Sitronix ST7735R with one of the following LCDs:
+ * JD-T18003-T01 1.8" 128x160 TFT
+
+ If M is selected the module will be called st7735r.
diff --git a/drivers/gpu/drm/tinydrm/Makefile b/drivers/gpu/drm/tinydrm/Makefile
index 8aeee53..49a1119 100644
--- a/drivers/gpu/drm/tinydrm/Makefile
+++ b/drivers/gpu/drm/tinydrm/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_TINYDRM_ILI9225) += ili9225.o
obj-$(CONFIG_TINYDRM_MI0283QT) += mi0283qt.o
obj-$(CONFIG_TINYDRM_REPAPER) += repaper.o
obj-$(CONFIG_TINYDRM_ST7586) += st7586.o
+obj-$(CONFIG_TINYDRM_ST7735R) += st7735r.o
diff --git a/drivers/gpu/drm/tinydrm/st7735r.c b/drivers/gpu/drm/tinydrm/st7735r.c
new file mode 100644
index 0000000..0b05b2c
--- /dev/null
+++ b/drivers/gpu/drm/tinydrm/st7735r.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DRM driver for Sitronix ST7735R panels
+ *
+ * Copyright 2017 David Lechner <david@lechnology.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-buf.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/property.h>
+#include <linux/spi/spi.h>
+#include <video/mipi_display.h>
+
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/tinydrm/mipi-dbi.h>
+#include <drm/tinydrm/tinydrm-helpers.h>
+
+#define ST7735R_FRMCTR1 0xb1
+#define ST7735R_FRMCTR2 0xb2
+#define ST7735R_FRMCTR3 0xb3
+#define ST7735R_INVCTR 0xb4
+#define ST7735R_PWCTR1 0xc0
+#define ST7735R_PWCTR2 0xc1
+#define ST7735R_PWCTR3 0xc2
+#define ST7735R_PWCTR4 0xc3
+#define ST7735R_PWCTR5 0xc4
+#define ST7735R_VMCTR1 0xc5
+#define ST7735R_GAMCTRP1 0xe0
+#define ST7735R_GAMCTRN1 0xe1
+
+#define ST7735R_MY BIT(7)
+#define ST7735R_MX BIT(6)
+#define ST7735R_MV BIT(5)
+
+static void st7735r_pipe_enable(struct drm_simple_display_pipe *pipe,
+ struct drm_crtc_state *crtc_state)
+{
+ struct tinydrm_device *tdev = pipe_to_tinydrm(pipe);
+ struct mipi_dbi *mipi = mipi_dbi_from_tinydrm(tdev);
+ struct device *dev = tdev->drm->dev;
+ int ret;
+ u8 addr_mode;
+
+ DRM_DEBUG_KMS("\n");
+
+ mipi_dbi_hw_reset(mipi);
+
+ ret = mipi_dbi_command(mipi, MIPI_DCS_SOFT_RESET);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "Error sending command %d\n", ret);
+ return;
+ }
+
+ msleep(150);
+
+ mipi_dbi_command(mipi, MIPI_DCS_EXIT_SLEEP_MODE);
+ msleep(500);
+
+ mipi_dbi_command(mipi, ST7735R_FRMCTR1, 0x01, 0x2c, 0x2d);
+ mipi_dbi_command(mipi, ST7735R_FRMCTR2, 0x01, 0x2c, 0x2d);
+ mipi_dbi_command(mipi, ST7735R_FRMCTR3, 0x01, 0x2c, 0x2d, 0x01, 0x2c,
+ 0x2d);
+ mipi_dbi_command(mipi, ST7735R_INVCTR, 0x07);
+ mipi_dbi_command(mipi, ST7735R_PWCTR1, 0xa2, 0x02, 0x84);
+ mipi_dbi_command(mipi, ST7735R_PWCTR2, 0xc5);
+ mipi_dbi_command(mipi, ST7735R_PWCTR3, 0x0a, 0x00);
+ mipi_dbi_command(mipi, ST7735R_PWCTR4, 0x8a, 0x2a);
+ mipi_dbi_command(mipi, ST7735R_PWCTR5, 0x8a, 0xee);
+ mipi_dbi_command(mipi, ST7735R_VMCTR1, 0x0e);
+ mipi_dbi_command(mipi, MIPI_DCS_EXIT_INVERT_MODE);
+ switch (mipi->rotation) {
+ default:
+ addr_mode = ST7735R_MX | ST7735R_MY;
+ break;
+ case 90:
+ addr_mode = ST7735R_MX | ST7735R_MV;
+ break;
+ case 180:
+ addr_mode = 0;
+ break;
+ case 270:
+ addr_mode = ST7735R_MY | ST7735R_MV;
+ break;
+ }
+ mipi_dbi_command(mipi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
+ mipi_dbi_command(mipi, MIPI_DCS_SET_PIXEL_FORMAT,
+ MIPI_DCS_PIXEL_FMT_16BIT);
+ mipi_dbi_command(mipi, ST7735R_GAMCTRP1, 0x0f, 0x1a, 0x0f, 0x18, 0x2f,
+ 0x28, 0x20, 0x22, 0x1f, 0x1b, 0x23, 0x37, 0x00, 0x07,
+ 0x02, 0x10);
+ mipi_dbi_command(mipi, ST7735R_GAMCTRN1, 0x0f, 0x1b, 0x0f, 0x17, 0x33,
+ 0x2c, 0x29, 0x2e, 0x30, 0x30, 0x39, 0x3f, 0x00, 0x07,
+ 0x03, 0x10);
+ mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_ON);
+
+ msleep(100);
+
+ mipi_dbi_command(mipi, MIPI_DCS_ENTER_NORMAL_MODE);
+
+ msleep(20);
+
+ mipi_dbi_pipe_enable(pipe, crtc_state);
+}
+
+static const struct drm_simple_display_pipe_funcs st7735r_pipe_funcs = {
+ .enable = st7735r_pipe_enable,
+ .disable = mipi_dbi_pipe_disable,
+ .update = tinydrm_display_pipe_update,
+ .prepare_fb = tinydrm_display_pipe_prepare_fb,
+};
+
+static const struct drm_display_mode jd_t18003_t01_mode = {
+ TINYDRM_MODE(128, 160, 28, 35),
+};
+
+DEFINE_DRM_GEM_CMA_FOPS(st7735r_fops);
+
+static struct drm_driver st7735r_driver = {
+ .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
+ DRIVER_ATOMIC,
+ .fops = &st7735r_fops,
+ TINYDRM_GEM_DRIVER_OPS,
+ .lastclose = drm_fb_helper_lastclose,
+ .debugfs_init = mipi_dbi_debugfs_init,
+ .name = "st7735r",
+ .desc = "Sitronix ST7735R",
+ .date = "20171128",
+ .major = 1,
+ .minor = 0,
+};
+
+static const struct of_device_id st7735r_of_match[] = {
+ { .compatible = "jianda,jd-t18003-t01" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, st7735r_of_match);
+
+static const struct spi_device_id st7735r_id[] = {
+ { "jd-t18003-t01", 0 },
+ { },
+};
+MODULE_DEVICE_TABLE(spi, st7735r_id);
+
+static int st7735r_probe(struct spi_device *spi)
+{
+ struct device *dev = &spi->dev;
+ struct mipi_dbi *mipi;
+ struct gpio_desc *dc;
+ u32 rotation = 0;
+ int ret;
+
+ mipi = devm_kzalloc(dev, sizeof(*mipi), GFP_KERNEL);
+ if (!mipi)
+ return -ENOMEM;
+
+ mipi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(mipi->reset)) {
+ DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
+ return PTR_ERR(mipi->reset);
+ }
+
+ dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
+ if (IS_ERR(dc)) {
+ DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
+ return PTR_ERR(dc);
+ }
+
+ mipi->backlight = tinydrm_of_find_backlight(dev);
+ if (IS_ERR(mipi->backlight))
+ return PTR_ERR(mipi->backlight);
+
+ device_property_read_u32(dev, "rotation", &rotation);
+
+ ret = mipi_dbi_spi_init(spi, mipi, dc);
+ if (ret)
+ return ret;
+
+ /* Cannot read from Adafruit 1.8" display via SPI */
+ mipi->read_commands = NULL;
+
+ ret = mipi_dbi_init(&spi->dev, mipi, &st7735r_pipe_funcs,
+ &st7735r_driver, &jd_t18003_t01_mode, rotation);
+ if (ret)
+ return ret;
+
+ spi_set_drvdata(spi, mipi);
+
+ return devm_tinydrm_register(&mipi->tinydrm);
+}
+
+static void st7735r_shutdown(struct spi_device *spi)
+{
+ struct mipi_dbi *mipi = spi_get_drvdata(spi);
+
+ tinydrm_shutdown(&mipi->tinydrm);
+}
+
+static struct spi_driver st7735r_spi_driver = {
+ .driver = {
+ .name = "st7735r",
+ .owner = THIS_MODULE,
+ .of_match_table = st7735r_of_match,
+ },
+ .id_table = st7735r_id,
+ .probe = st7735r_probe,
+ .shutdown = st7735r_shutdown,
+};
+module_spi_driver(st7735r_spi_driver);
+
+MODULE_DESCRIPTION("Sitronix ST7735R DRM driver");
+MODULE_AUTHOR("David Lechner <david@lechnology.com>");
+MODULE_LICENSE("GPL");
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 2/3] dt-bindings: Add binding for Sitronix ST7735R display panels
From: David Lechner @ 2017-12-21 19:23 UTC (permalink / raw)
To: dri-devel, devicetree
Cc: Mark Rutland, limor, David Lechner, linux-kernel, Rob Herring
In-Reply-To: <1513884233-31540-1-git-send-email-david@lechnology.com>
This adds a new device tree binding for Sitronix ST7735R display panels,
such as the Adafruit 1.8" TFT.
Signed-off-by: David Lechner <david@lechnology.com>
---
v3 changes:
* compatible string is changed from "sitronix,st7735r-jd-t18003-t01" to
"jianda,jd-t18003-t01", "sitronix,st7735r"
v2 changes:
* none
.../bindings/display/sitronix,st7735r.txt | 35 ++++++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/sitronix,st7735r.txt
diff --git a/Documentation/devicetree/bindings/display/sitronix,st7735r.txt b/Documentation/devicetree/bindings/display/sitronix,st7735r.txt
new file mode 100644
index 0000000..f0a5090
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/sitronix,st7735r.txt
@@ -0,0 +1,35 @@
+Sitronix ST7735R display panels
+
+This binding is for display panels using a Sitronix ST7735R controller in SPI
+mode.
+
+Required properties:
+- compatible: "jianda,jd-t18003-t01", "sitronix,st7735r"
+- dc-gpios: Display data/command selection (D/CX)
+- reset-gpios: Reset signal (RSTX)
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in ../spi/spi-bus.txt must be specified.
+
+Optional properties:
+- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
+- backlight: phandle of the backlight device attached to the panel
+
+Example:
+
+ backlight: backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
+ }
+
+ ...
+
+ display@0{
+ compatible = "jianda,jd-t18003-t01", "sitronix,st7735r";
+ reg = <0>;
+ spi-max-frequency = <32000000>;
+ dc-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
+ rotation = <270>;
+ backlight = &backlight;
+ };
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 1/3] dt-bindings: add jianda vendor prefix
From: David Lechner @ 2017-12-21 19:23 UTC (permalink / raw)
To: dri-devel, devicetree
Cc: Mark Rutland, limor, David Lechner, linux-kernel, Rob Herring
In-Reply-To: <1513884233-31540-1-git-send-email-david@lechnology.com>
This adds a vendor prefix "jianda" for Jiandangjing Technology Co., Ltd.
Signed-off-by: David Lechner <david@lechnology.com>
---
v3 changes:
* new patch in v3
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 41cb1ff0..fea7903 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -172,6 +172,7 @@ issi Integrated Silicon Solutions Inc.
itead ITEAD Intelligent Systems Co.Ltd
iwave iWave Systems Technologies Pvt. Ltd.
jdi Japan Display Inc.
+jianda Jiandangjing Technology Co., Ltd.
jedec JEDEC Solid State Technology Association
karo Ka-Ro electronics GmbH
keithkoep Keith & Koep GmbH
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 0/3] DRM driver for Sitronix ST7735R display panels
From: David Lechner @ 2017-12-21 19:23 UTC (permalink / raw)
To: dri-devel, devicetree
Cc: Mark Rutland, limor, David Lechner, linux-kernel, Rob Herring
This series adds a new DRM/TinyDRM driver for Sitronix ST7735R, specifically
the Adafruit 1.8" TFT.
Nothing fancy here. Just mostly TinyDRM boilerplate with the init sequence
from the fbtft driver for the same panel.
v3 changes:
* New patch for jianda vendor prefix
* Change compatible string in DT bindings (dropped ACK because of this)
* Use SPDX license ID
David Lechner (3):
dt-bindings: add jianda vendor prefix
dt-bindings: Add binding for Sitronix ST7735R display panels
drm/tinydrm: add driver for ST7735R panels
.../bindings/display/sitronix,st7735r.txt | 35 ++++
.../devicetree/bindings/vendor-prefixes.txt | 1 +
MAINTAINERS | 6 +
drivers/gpu/drm/tinydrm/Kconfig | 10 +
drivers/gpu/drm/tinydrm/Makefile | 1 +
drivers/gpu/drm/tinydrm/st7735r.c | 215 +++++++++++++++++++++
6 files changed, 268 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/sitronix,st7735r.txt
create mode 100644 drivers/gpu/drm/tinydrm/st7735r.c
--
2.7.4
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^ permalink raw reply
* [PATCH] dt-bindings: Use lower case hex in unit-addresses
From: Rob Herring @ 2017-12-21 18:35 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
DT unit addresses should be lower case hex. Fix all the
binding examples.
Converted with the following command from Krzysztof Kozlowski:
sed -e 's/@\([a-fA-F0-9_-]*\) {/@\L\1 {/' -i $(find Documentation/devicetree/bindings -name '*.txt')
Signed-off-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt | 6 +++---
.../devicetree/bindings/arm/samsung/samsung-boards.txt | 2 +-
Documentation/devicetree/bindings/clock/exynos3250-clock.txt | 2 +-
Documentation/devicetree/bindings/clock/exynos5260-clock.txt | 2 +-
Documentation/devicetree/bindings/clock/exynos5410-clock.txt | 2 +-
Documentation/devicetree/bindings/clock/exynos5433-clock.txt | 2 +-
Documentation/devicetree/bindings/crypto/atmel-crypto.txt | 2 +-
.../devicetree/bindings/devfreq/event/exynos-nocp.txt | 2 +-
.../devicetree/bindings/display/exynos/exynos_dsim.txt | 2 +-
Documentation/devicetree/bindings/display/st,stih4xx.txt | 2 +-
Documentation/devicetree/bindings/dma/ste-dma40.txt | 2 +-
Documentation/devicetree/bindings/gpio/abilis,tb10x-gpio.txt | 2 +-
Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt | 2 +-
Documentation/devicetree/bindings/gpio/gpio.txt | 2 +-
.../devicetree/bindings/i2c/i2c-arb-gpio-challenge.txt | 2 +-
Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt | 2 +-
Documentation/devicetree/bindings/input/samsung-keypad.txt | 2 +-
.../bindings/input/touchscreen/brcm,iproc-touchscreen.txt | 2 +-
Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt | 2 +-
Documentation/devicetree/bindings/mailbox/omap-mailbox.txt | 2 +-
Documentation/devicetree/bindings/media/s5p-cec.txt | 2 +-
Documentation/devicetree/bindings/media/samsung-s5c73m3.txt | 2 +-
.../devicetree/bindings/memory-controllers/ti-aemif.txt | 2 +-
Documentation/devicetree/bindings/mfd/cros-ec.txt | 2 +-
Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt | 2 +-
Documentation/devicetree/bindings/net/cpsw.txt | 4 ++--
Documentation/devicetree/bindings/net/davinci-mdio.txt | 4 ++--
Documentation/devicetree/bindings/net/fsl-tsec-phy.txt | 2 +-
Documentation/devicetree/bindings/phy/ti-phy.txt | 2 +-
.../devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt | 6 +++---
.../devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt | 2 +-
.../devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt | 2 +-
Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 2 +-
.../devicetree/bindings/powerpc/fsl/interlaken-lac.txt | 12 ++++++------
.../devicetree/bindings/regulator/st,stm32-vrefbuf.txt | 2 +-
Documentation/devicetree/bindings/serial/lantiq_asc.txt | 2 +-
Documentation/devicetree/bindings/sound/img,i2s-out.txt | 2 +-
Documentation/devicetree/bindings/sound/img,parallel-out.txt | 2 +-
Documentation/devicetree/bindings/sound/img,spdif-in.txt | 2 +-
Documentation/devicetree/bindings/sound/img,spdif-out.txt | 2 +-
Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt | 8 ++++----
Documentation/devicetree/bindings/spi/spi-davinci.txt | 2 +-
Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt | 2 +-
Documentation/devicetree/bindings/thermal/exynos-thermal.txt | 2 +-
Documentation/devicetree/bindings/thermal/thermal.txt | 6 +++---
.../devicetree/bindings/timer/samsung,exynos4210-mct.txt | 2 +-
Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt | 2 +-
Documentation/devicetree/bindings/watchdog/samsung-wdt.txt | 2 +-
48 files changed, 64 insertions(+), 64 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index ccaaec6014bd..6c49db7f8ad2 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -55,7 +55,7 @@ Note: child nodes can be added for auto probing from device tree.
Example: adding device info in dtsi file
-adc: adc@12D10000 {
+adc: adc@12d10000 {
compatible = "samsung,exynos-adc-v1";
reg = <0x12D10000 0x100>;
interrupts = <0 106 0>;
@@ -71,7 +71,7 @@ adc: adc@12D10000 {
Example: adding device info in dtsi file for Exynos3250 with additional sclk
-adc: adc@126C0000 {
+adc: adc@126c0000 {
compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
reg = <0x126C0000 0x100>;
interrupts = <0 137 0>;
@@ -87,7 +87,7 @@ adc: adc@126C0000 {
Example: Adding child nodes in dts file
-adc@12D10000 {
+adc@12d10000 {
/* NTC thermistor is a hwmon device */
ncp15wb473@0 {
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index e13459618581..469ac98ecf8f 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -72,7 +72,7 @@ Optional nodes:
- compatible: only "samsung,secure-firmware" is currently supported
- reg: address of non-secure SYSRAM used for communication with firmware
- firmware@203F000 {
+ firmware@203f000 {
compatible = "samsung,secure-firmware";
reg = <0x0203F000 0x1000>;
};
diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
index f1738b88c225..7441ed519f02 100644
--- a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
@@ -32,7 +32,7 @@ Example 1: Examples of clock controller nodes are listed below.
#clock-cells = <1>;
};
- cmu_dmc: clock-controller@105C0000 {
+ cmu_dmc: clock-controller@105c0000 {
compatible = "samsung,exynos3250-cmu-dmc";
reg = <0x105C0000 0x2000>;
#clock-cells = <1>;
diff --git a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
index 5496b2fac483..c79d31f7f66e 100644
--- a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
@@ -180,7 +180,7 @@ Example 2: UART controller node that consumes the clock generated by the
peri clock controller. Refer to the standard clock bindings for
information about 'clocks' and 'clock-names' property.
- serial@12C00000 {
+ serial@12c00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 146 0>;
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
index c68b0d29b3d0..217beb27c30e 100644
--- a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -41,7 +41,7 @@ Example 2: UART controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
- serial@12C20000 {
+ serial@12c20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 51 0>;
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index c473dd38dd55..50d5897c9849 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -472,7 +472,7 @@ Example 2: Examples of clock controller nodes are listed below.
Example 3: UART controller node that consumes the clock generated by the clock
controller.
- serial_0: serial@14C10000 {
+ serial_0: serial@14c10000 {
compatible = "samsung,exynos5433-uart";
reg = <0x14C10000 0x100>;
interrupts = <0 421 0>;
diff --git a/Documentation/devicetree/bindings/crypto/atmel-crypto.txt b/Documentation/devicetree/bindings/crypto/atmel-crypto.txt
index 7de1a9674c70..6b458bb2440d 100644
--- a/Documentation/devicetree/bindings/crypto/atmel-crypto.txt
+++ b/Documentation/devicetree/bindings/crypto/atmel-crypto.txt
@@ -75,7 +75,7 @@ Required properties:
- clock-frequency: must be present in the i2c controller node.
Example:
-atecc508a@C0 {
+atecc508a@c0 {
compatible = "atmel,atecc508a";
reg = <0xC0>;
};
diff --git a/Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt b/Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt
index fd459f00aa5a..aeaebd425d1f 100644
--- a/Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt
+++ b/Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt
@@ -20,7 +20,7 @@ Optional properties:
Example : NoC Probe nodes in Device Tree are listed below.
- nocp_mem0_0: nocp@10CA1000 {
+ nocp_mem0_0: nocp@10ca1000 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1000 0x200>;
};
diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
index ca5204b3bc21..2fff8b406f4c 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
@@ -54,7 +54,7 @@ Video interfaces:
Example:
- dsi@11C80000 {
+ dsi@11c80000 {
compatible = "samsung,exynos4210-mipi-dsi";
reg = <0x11C80000 0x10000>;
interrupts = <0 79 0>;
diff --git a/Documentation/devicetree/bindings/display/st,stih4xx.txt b/Documentation/devicetree/bindings/display/st,stih4xx.txt
index a352ed30cd70..6778b3e7ad5b 100644
--- a/Documentation/devicetree/bindings/display/st,stih4xx.txt
+++ b/Documentation/devicetree/bindings/display/st,stih4xx.txt
@@ -119,7 +119,7 @@ Example:
/ {
...
- vtg_main_slave: sti-vtg-main-slave@fe85A800 {
+ vtg_main_slave: sti-vtg-main-slave@fe85a800 {
compatible = "st,vtg";
reg = <0xfe85A800 0x300>;
interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>;
diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index aa7dbd565ad0..99ab5c4d331e 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -15,7 +15,7 @@ Optional properties:
Example:
- dma: dma-controller@801C0000 {
+ dma: dma-controller@801c0000 {
compatible = "stericsson,db8500-dma40", "stericsson,dma40";
reg = <0x801C0000 0x1000 0x40010000 0x800>;
reg-names = "base", "lcpa";
diff --git a/Documentation/devicetree/bindings/gpio/abilis,tb10x-gpio.txt b/Documentation/devicetree/bindings/gpio/abilis,tb10x-gpio.txt
index 00611aceed3e..a25c87b650e5 100644
--- a/Documentation/devicetree/bindings/gpio/abilis,tb10x-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/abilis,tb10x-gpio.txt
@@ -21,7 +21,7 @@ Documentation/devicetree/bindings/gpio/gpio.txt
Example:
- gpioa: gpio@FF140000 {
+ gpioa: gpio@ff140000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt
index 854de130a971..78458adbf4b7 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt
@@ -27,7 +27,7 @@ Optional properties:
Example:
-gpio1: stp@E100BB0 {
+gpio1: stp@e100bb0 {
compatible = "lantiq,gpio-stp-xway";
reg = <0xE100BB0 0x40>;
#gpio-cells = <2>;
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
index 802402f6cc5d..b5de08e3b1a2 100644
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
@@ -290,7 +290,7 @@ pins 50..69.
Example 2:
- gpio_pio_i: gpio-controller@14B0 {
+ gpio_pio_i: gpio-controller@14b0 {
#gpio-cells = <2>;
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1480 0x18>;
diff --git a/Documentation/devicetree/bindings/i2c/i2c-arb-gpio-challenge.txt b/Documentation/devicetree/bindings/i2c/i2c-arb-gpio-challenge.txt
index 248a155414c2..548a73cde796 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-arb-gpio-challenge.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-arb-gpio-challenge.txt
@@ -54,7 +54,7 @@ Optional properties:
Example:
- i2c@12CA0000 {
+ i2c@12ca0000 {
compatible = "acme,some-i2c-device";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt
index 70c054a9a997..60fe90d69f4e 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt
@@ -11,7 +11,7 @@ Required properties:
Examples:
-lpi2c7: lpi2c7@40A50000 {
+lpi2c7: lpi2c7@40a50000 {
compatible = "fsl,imx8dv-lpi2c";
reg = <0x40A50000 0x10000>;
interrupt-parent = <&intc>;
diff --git a/Documentation/devicetree/bindings/input/samsung-keypad.txt b/Documentation/devicetree/bindings/input/samsung-keypad.txt
index 5305e74e5742..4c5c0a82586d 100644
--- a/Documentation/devicetree/bindings/input/samsung-keypad.txt
+++ b/Documentation/devicetree/bindings/input/samsung-keypad.txt
@@ -45,7 +45,7 @@ Optional Properties specific to linux:
Example:
- keypad@100A0000 {
+ keypad@100a0000 {
compatible = "samsung,s5pv210-keypad";
reg = <0x100A0000 0x100>;
interrupts = <173>;
diff --git a/Documentation/devicetree/bindings/input/touchscreen/brcm,iproc-touchscreen.txt b/Documentation/devicetree/bindings/input/touchscreen/brcm,iproc-touchscreen.txt
index ac5dff412e25..f127a2117072 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/brcm,iproc-touchscreen.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/brcm,iproc-touchscreen.txt
@@ -66,7 +66,7 @@ Example: An example of touchscreen node
reg = <0x180a6000 0xc30>;
};
- touchscreen: touchscreen@180A6000 {
+ touchscreen: touchscreen@180a6000 {
compatible = "brcm,iproc-touchscreen";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt
index 85f068805dd8..b1682c80b490 100644
--- a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt
+++ b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt
@@ -56,7 +56,7 @@ Examples:
iommus = <&sysmmu_gsc0>;
};
- sysmmu_gsc0: sysmmu@13E80000 {
+ sysmmu_gsc0: sysmmu@13e80000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13E80000 0x1000>;
interrupt-parent = <&combiner>;
diff --git a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
index 9b40c4925aa9..0ef372656a3e 100644
--- a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
+++ b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
@@ -124,7 +124,7 @@ dsp {
};
/* AM33xx */
-mailbox: mailbox@480C8000 {
+mailbox: mailbox@480c8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480C8000 0x200>;
interrupts = <77>;
diff --git a/Documentation/devicetree/bindings/media/s5p-cec.txt b/Documentation/devicetree/bindings/media/s5p-cec.txt
index 6f3756da900f..e847291d4aff 100644
--- a/Documentation/devicetree/bindings/media/s5p-cec.txt
+++ b/Documentation/devicetree/bindings/media/s5p-cec.txt
@@ -23,7 +23,7 @@ Optional:
Example:
-hdmicec: cec@100B0000 {
+hdmicec: cec@100b0000 {
compatible = "samsung,s5p-cec";
reg = <0x100B0000 0x200>;
interrupts = <0 114 0>;
diff --git a/Documentation/devicetree/bindings/media/samsung-s5c73m3.txt b/Documentation/devicetree/bindings/media/samsung-s5c73m3.txt
index 2c85c4538a6d..21f31fdf5543 100644
--- a/Documentation/devicetree/bindings/media/samsung-s5c73m3.txt
+++ b/Documentation/devicetree/bindings/media/samsung-s5c73m3.txt
@@ -62,7 +62,7 @@ For more details see description of the SPI busses bindings
Example:
-i2c@138A000000 {
+i2c@138a000000 {
...
s5c73m3@3c {
compatible = "samsung,s5c73m3";
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt
index 9592717f483f..190437a0c146 100644
--- a/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt
@@ -138,7 +138,7 @@ from the corresponding HW reg.
Example for aemif, davinci nand and nor flash chip select shown below.
-memory-controller@21000A00 {
+memory-controller@21000a00 {
compatible = "ti,davinci-aemif";
#address-cells = <2>;
#size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/mfd/cros-ec.txt b/Documentation/devicetree/bindings/mfd/cros-ec.txt
index 136e0c2da44d..6245c9b1a68b 100644
--- a/Documentation/devicetree/bindings/mfd/cros-ec.txt
+++ b/Documentation/devicetree/bindings/mfd/cros-ec.txt
@@ -41,7 +41,7 @@ Optional properties (all):
Example for I2C:
-i2c@12CA0000 {
+i2c@12ca0000 {
cros-ec@1e {
reg = <0x1e>;
compatible = "google,cros-ec-i2c";
diff --git a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt b/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
index d0a37252eb22..6d60bc3063f5 100644
--- a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
+++ b/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
@@ -23,7 +23,7 @@ Optional subnodes:
Example:
- mlc: flash@200A8000 {
+ mlc: flash@200a8000 {
compatible = "nxp,lpc3220-mlc";
reg = <0x200A8000 0x11000>;
interrupts = <11 0>;
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt
index 7cc15c96ea95..4cb4925a28ab 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -61,7 +61,7 @@ file.
Examples:
- mac: ethernet@4A100000 {
+ mac: ethernet@4a100000 {
compatible = "ti,cpsw";
reg = <0x4A100000 0x1000>;
interrupts = <55 0x4>;
@@ -91,7 +91,7 @@ Examples:
};
(or)
- mac: ethernet@4A100000 {
+ mac: ethernet@4a100000 {
compatible = "ti,cpsw";
ti,hwmods = "cpgmac0";
cpdma_channels = <8>;
diff --git a/Documentation/devicetree/bindings/net/davinci-mdio.txt b/Documentation/devicetree/bindings/net/davinci-mdio.txt
index 621156ca4ffd..e6527de80f10 100644
--- a/Documentation/devicetree/bindings/net/davinci-mdio.txt
+++ b/Documentation/devicetree/bindings/net/davinci-mdio.txt
@@ -21,7 +21,7 @@ file.
Examples:
- mdio: davinci_mdio@4A101000 {
+ mdio: davinci_mdio@4a101000 {
compatible = "ti,davinci_mdio";
reg = <0x4A101000 0x1000>;
bus_freq = <1000000>;
@@ -29,7 +29,7 @@ Examples:
(or)
- mdio: davinci_mdio@4A101000 {
+ mdio: davinci_mdio@4a101000 {
compatible = "ti,davinci_mdio";
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index db74f0dc290c..594982c6b9f9 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -136,7 +136,7 @@ Clock Properties:
Example:
- ptp_clock@24E00 {
+ ptp_clock@24e00 {
compatible = "fsl,etsec-ptp";
reg = <0x24E00 0xB0>;
interrupts = <12 0x8 13 0x8>;
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
index cd13e6157088..57dfda8a7a1d 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -120,7 +120,7 @@ usb3phy@4a084400 {
"refclk";
};
-sata_phy: phy@4A096000 {
+sata_phy: phy@4a096000 {
compatible = "ti,phy-pipe3-sata";
reg = <0x4A096000 0x80>, /* phy_rx */
<0x4A096400 0x64>, /* phy_tx */
diff --git a/Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt b/Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt
index 2c11866221c2..c591b9cb5ba0 100644
--- a/Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt
+++ b/Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt
@@ -49,7 +49,7 @@ explained in Documentation/devicetree/bindings/gpio/gpio.txt.
Example
-------
-iomux: iomux@FF10601c {
+iomux: iomux@ff10601c {
compatible = "abilis,tb10x-iomux";
reg = <0xFF10601c 0x4>;
pctl_gpio_a: pctl-gpio-a {
@@ -59,7 +59,7 @@ iomux: iomux@FF10601c {
abilis,function = "uart0";
};
};
-uart@FF100000 {
+uart@ff100000 {
compatible = "snps,dw-apb-uart";
reg = <0xFF100000 0x100>;
clock-frequency = <166666666>;
@@ -69,7 +69,7 @@ uart@FF100000 {
pinctrl-names = "default";
pinctrl-0 = <&pctl_uart0>;
};
-gpioa: gpio@FF140000 {
+gpioa: gpio@ff140000 {
compatible = "abilis,tb10x-gpio";
reg = <0xFF140000 0x1000>;
gpio-controller;
diff --git a/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt
index 0326154c7925..a72dc3178179 100644
--- a/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt
@@ -152,7 +152,7 @@ resetn
Example:
--------
-pinctrl@18101C00 {
+pinctrl@18101c00 {
compatible = "img,pistachio-system-pinctrl";
reg = <0x18101C00 0x400>;
diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt
index 8e5216bcd748..4658f105fa09 100644
--- a/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt
+++ b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt
@@ -163,7 +163,7 @@ Valid values for xRX300 pin names:
io42-io43,io48-io61.
Example:
- gpio: pinmux@E100B10 {
+ gpio: pinmux@e100b10 {
compatible = "lantiq,danube-pinctrl";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
index 231fa1db7c5e..afa8a18ea11a 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
@@ -81,7 +81,7 @@ Examples:
reg = <0 0x10005000 0 0x1000>;
};
- syscfg_pctl_b: syscfg_pctl_b@1020C020 {
+ syscfg_pctl_b: syscfg_pctl_b@1020c020 {
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
reg = <0 0x1020C020 0 0x1000>;
};
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt b/Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt
index 641bc13983e1..ed6a414b2e10 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt
@@ -223,37 +223,37 @@ lac-portals {
reg = <0x9000 0x1000>;
};
- lportal10: lac-portal@A000 {
+ lportal10: lac-portal@a000 {
compatible = "fsl,interlaken-lac-portal-v1.0";
fsl,liodn = <0x20E>;
reg = <0xA000 0x1000>;
};
- lportal11: lac-portal@B000 {
+ lportal11: lac-portal@b000 {
compatible = "fsl,interlaken-lac-portal-v1.0";
fsl,liodn = <0x20F>;
reg = <0xB000 0x1000>;
};
- lportal12: lac-portal@C000 {
+ lportal12: lac-portal@c000 {
compatible = "fsl,interlaken-lac-portal-v1.0";
fsl,liodn = <0x210>;
reg = <0xC000 0x1000>;
};
- lportal13: lac-portal@D000 {
+ lportal13: lac-portal@d000 {
compatible = "fsl,interlaken-lac-portal-v1.0";
fsl,liodn = <0x211>;
reg = <0xD000 0x1000>;
};
- lportal14: lac-portal@E000 {
+ lportal14: lac-portal@e000 {
compatible = "fsl,interlaken-lac-portal-v1.0";
fsl,liodn = <0x212>;
reg = <0xE000 0x1000>;
};
- lportal15: lac-portal@F000 {
+ lportal15: lac-portal@f000 {
compatible = "fsl,interlaken-lac-portal-v1.0";
fsl,liodn = <0x213>;
reg = <0xF000 0x1000>;
diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.txt b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.txt
index 3944ee3e731e..5ddb8500a929 100644
--- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.txt
+++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.txt
@@ -10,7 +10,7 @@ Required properties:
- clocks: Must contain an entry for peripheral clock.
Example:
- vrefbuf: regulator@58003C00 {
+ vrefbuf: regulator@58003c00 {
compatible = "st,stm32-vrefbuf";
reg = <0x58003C00 0x8>;
clocks = <&rcc VREF_CK>;
diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.txt b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
index 5b78591aaa46..3acbd309ab9d 100644
--- a/Documentation/devicetree/bindings/serial/lantiq_asc.txt
+++ b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
@@ -8,7 +8,7 @@ Required properties:
Example:
-asc1: serial@E100C00 {
+asc1: serial@e100c00 {
compatible = "lantiq,asc";
reg = <0xE100C00 0x400>;
interrupt-parent = <&icu0>;
diff --git a/Documentation/devicetree/bindings/sound/img,i2s-out.txt b/Documentation/devicetree/bindings/sound/img,i2s-out.txt
index 0159415b3338..6b0ee9b7e11b 100644
--- a/Documentation/devicetree/bindings/sound/img,i2s-out.txt
+++ b/Documentation/devicetree/bindings/sound/img,i2s-out.txt
@@ -35,7 +35,7 @@ Optional Properties:
Example:
-i2s_out: i2s-out@18100A00 {
+i2s_out: i2s-out@18100a00 {
compatible = "img,i2s-out";
reg = <0x18100A00 0x200>;
interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Documentation/devicetree/bindings/sound/img,parallel-out.txt b/Documentation/devicetree/bindings/sound/img,parallel-out.txt
index a3015d2a06e0..37a3f94cc126 100644
--- a/Documentation/devicetree/bindings/sound/img,parallel-out.txt
+++ b/Documentation/devicetree/bindings/sound/img,parallel-out.txt
@@ -29,7 +29,7 @@ Optional Properties:
Example:
-parallel_out: parallel-out@18100C00 {
+parallel_out: parallel-out@18100c00 {
compatible = "img,parallel-out";
reg = <0x18100C00 0x100>;
interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Documentation/devicetree/bindings/sound/img,spdif-in.txt b/Documentation/devicetree/bindings/sound/img,spdif-in.txt
index aab9a81f7e13..f7ea8c87bf34 100644
--- a/Documentation/devicetree/bindings/sound/img,spdif-in.txt
+++ b/Documentation/devicetree/bindings/sound/img,spdif-in.txt
@@ -29,7 +29,7 @@ Optional Properties:
Example:
-spdif_in: spdif-in@18100E00 {
+spdif_in: spdif-in@18100e00 {
compatible = "img,spdif-in";
reg = <0x18100E00 0x100>;
interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Documentation/devicetree/bindings/sound/img,spdif-out.txt b/Documentation/devicetree/bindings/sound/img,spdif-out.txt
index 470a5191e101..413ed8b01870 100644
--- a/Documentation/devicetree/bindings/sound/img,spdif-out.txt
+++ b/Documentation/devicetree/bindings/sound/img,spdif-out.txt
@@ -29,7 +29,7 @@ Optional Properties:
Example:
-spdif_out: spdif-out@18100D00 {
+spdif_out: spdif-out@18100d00 {
compatible = "img,spdif-out";
reg = <0x18100D00 0x100>;
interrupts = <GIC_SHARED 21 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
index 9c1ee52fed5b..4d51f3f5ea98 100644
--- a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
+++ b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
@@ -51,7 +51,7 @@ Optional properties:
Example:
- sti_uni_player1: sti-uni-player@8D81000 {
+ sti_uni_player1: sti-uni-player@8d81000 {
compatible = "st,stih407-uni-player-hdmi";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
@@ -63,7 +63,7 @@ Example:
st,tdm-mode = <1>;
};
- sti_uni_player2: sti-uni-player@8D82000 {
+ sti_uni_player2: sti-uni-player@8d82000 {
compatible = "st,stih407-uni-player-pcm-out";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
@@ -74,7 +74,7 @@ Example:
dma-names = "tx";
};
- sti_uni_player3: sti-uni-player@8D85000 {
+ sti_uni_player3: sti-uni-player@8d85000 {
compatible = "st,stih407-uni-player-spdif";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
@@ -85,7 +85,7 @@ Example:
dma-names = "tx";
};
- sti_uni_reader1: sti-uni-reader@8D84000 {
+ sti_uni_reader1: sti-uni-reader@8d84000 {
compatible = "st,stih407-uni-reader-hdmi";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt
index 1925277bfc1e..9f5b4c7c0c08 100644
--- a/Documentation/devicetree/bindings/spi/spi-davinci.txt
+++ b/Documentation/devicetree/bindings/spi/spi-davinci.txt
@@ -68,7 +68,7 @@ SPI_SOMI/SIMO+-----------------+ +-----------
Example of a NOR flash slave device (n25q032) connected to DaVinci
SPI controller device over the SPI bus.
-spi0:spi@20BF0000 {
+spi0:spi@20bf0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,dm6446-spi";
diff --git a/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
index 6069b95a883d..ce3230c8e28d 100644
--- a/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
+++ b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
@@ -16,7 +16,7 @@ Optional properties:
Example:
-spi: spi@E100800 {
+spi: spi@e100800 {
compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
reg = <0xE100800 0x100>;
interrupt-parent = <&icu0>;
diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 9b4c7b017495..1b596fd38dc4 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -70,7 +70,7 @@ Following properties are mandatory (depending on SoC):
Example 1):
- tmu@100C0000 {
+ tmu@100c0000 {
compatible = "samsung,exynos4412-tmu";
interrupt-parent = <&combiner>;
reg = <0x100C0000 0x100>;
diff --git a/Documentation/devicetree/bindings/thermal/thermal.txt b/Documentation/devicetree/bindings/thermal/thermal.txt
index 44d7cb2cb2c0..1719d47a5e2f 100644
--- a/Documentation/devicetree/bindings/thermal/thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/thermal.txt
@@ -252,7 +252,7 @@ ocp {
/*
* A simple IC with a single bandgap temperature sensor.
*/
- bandgap0: bandgap@0000ED00 {
+ bandgap0: bandgap@0000ed00 {
...
#thermal-sensor-cells = <0>;
};
@@ -330,7 +330,7 @@ ocp {
/*
* A simple IC with several bandgap temperature sensors.
*/
- bandgap0: bandgap@0000ED00 {
+ bandgap0: bandgap@0000ed00 {
...
#thermal-sensor-cells = <1>;
};
@@ -458,7 +458,7 @@ ocp {
/*
* A simple IC with a single bandgap temperature sensor.
*/
- bandgap0: bandgap@0000ED00 {
+ bandgap0: bandgap@0000ed00 {
...
#thermal-sensor-cells = <0>;
};
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
index 167d5dab9f64..8f78640ad64c 100644
--- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -51,7 +51,7 @@ Example 2: In this example, the timer interrupts are connected to two separate
interrupt controllers. Hence, an interrupt-map is created to map
the interrupts to the respective interrupt controllers.
- mct@101C0000 {
+ mct@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
interrupt-parent = <&mct_map>;
diff --git a/Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt b/Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt
index 556d06c17c92..4b76bec62af9 100644
--- a/Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt
@@ -10,7 +10,7 @@ Optional properties:
Example:
- watchdog@4003C000 {
+ watchdog@4003c000 {
compatible = "nxp,pnx4008-wdt";
reg = <0x4003C000 0x1000>;
timeout-sec = <10>;
diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
index 1f6e101e299a..46dcb48e75b4 100644
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
@@ -25,7 +25,7 @@ Optional properties:
Example:
-watchdog@101D0000 {
+watchdog@101d0000 {
compatible = "samsung,exynos5250-wdt";
reg = <0x101D0000 0x100>;
interrupts = <0 42 0>;
--
2.14.1
--
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^ permalink raw reply related
* [PATCH 3/3] drm/tinydrm: Update ILI9225 compatible string
From: David Lechner @ 2017-12-21 18:33 UTC (permalink / raw)
To: dri-devel, devicetree
Cc: Mark Rutland, limor, David Lechner, linux-kernel, Rob Herring
In-Reply-To: <1513881187-3197-1-git-send-email-david@lechnology.com>
This updates the compatible string for a no-name LCD panel to
"vot,v220hf01a-t", "ilitek,ili9225".
The original bindings were the generic "ilitek,ili9225-2.2in-176x220"
because I could not find a datasheet. However, after some more research,
I finally found one, so the actual vendor and model name are now known.
This previous bindings have not made it to the mainline kernel yet, so
this is not breaking backwards compatibility.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/gpu/drm/tinydrm/ili9225.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tinydrm/ili9225.c b/drivers/gpu/drm/tinydrm/ili9225.c
index e8f1b3a..c0cf498 100644
--- a/drivers/gpu/drm/tinydrm/ili9225.c
+++ b/drivers/gpu/drm/tinydrm/ili9225.c
@@ -391,13 +391,13 @@ static struct drm_driver ili9225_driver = {
};
static const struct of_device_id ili9225_of_match[] = {
- { .compatible = "ilitek,ili9225-2.2in-176x220" },
+ { .compatible = "vot,v220hf01a-t" },
{},
};
MODULE_DEVICE_TABLE(of, ili9225_of_match);
static const struct spi_device_id ili9225_id[] = {
- { "ili9225-2.2in-176x220", 0 },
+ { "v220hf01a-t", 0 },
{ },
};
MODULE_DEVICE_TABLE(spi, ili9225_id);
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v6 2/2] soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
From: Dhaval Shah @ 2017-12-21 18:33 UTC (permalink / raw)
To: arnd-r2nGTMty4D4, rdunlap-wEGCiKHe2LqWVfeAwA7xHQ,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, pombredanne-od1rfyK75/E,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
michal.simek-gjFFaj9aHVfQT0dZR+AlfA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, hyunk-gjFFaj9aHVfQT0dZR+AlfA,
Dhaval Shah
In-Reply-To: <1513881186-26020-1-git-send-email-dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
Xilinx ZYNQMP logicoreIP Init driver is based on the new
LogiCoreIP design created. This driver provides the processing system
and programmable logic isolation. Set the frequency based on the clock
information get from the logicoreIP register set.
Signed-off-by: Dhaval Shah <dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
---
Changes since v6:
* Path of the driver is updated to "drivers/soc/xilinx/" from "drivers/misc"
* Patch is rebase on top of the https://patchwork.kernel.org/patch/10123235/
Changes since v5:
* Changes made to include index 0 of the array.
Changes since v4:
* Indent the help text (below) by 2 additional spaces, as documented in coding-style.rst
* Spell check are resolved as per the review comment.
* inline the read() and write() functions..
* multi-line comment style
* Updated subject line prefix
Changes since v3:
No Changes.
Changes since v2:
* Removed the "default n" from the Kconfig
* More help text added to explain more about the logicoreIP driver
* SPDX id is relocated at top of the file with // style comment
* Removed the export API and header file and make it a single driver
which provides logocoreIP init.
* Provide the information in commit message as well for the why driver
in drivers/misc.
drivers/soc/xilinx/Kconfig | 15 +
drivers/soc/xilinx/Makefile | 1 +
drivers/soc/xilinx/xlnx_vcu.c | 630 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 646 insertions(+)
create mode 100644 drivers/soc/xilinx/xlnx_vcu.c
diff --git a/drivers/soc/xilinx/Kconfig b/drivers/soc/xilinx/Kconfig
index ffaaa2f..266b50f 100644
--- a/drivers/soc/xilinx/Kconfig
+++ b/drivers/soc/xilinx/Kconfig
@@ -1,4 +1,19 @@
# SPDX-License-Identifier: GPL-2.0
menu "Xilinx SoC drivers"
+config XILINX_VCU
+ tristate "Xilinx VCU logicoreIP Init"
+ help
+ Provides the driver to enable and disable the isolation between the
+ processing system and programmable logic part by using the logicoreIP
+ register set. This driver also configures the frequency based on the
+ clock information from the logicoreIP register set.
+
+ If you say yes here you get support for the logicoreIP.
+
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called xlnx_vcu.
+
endmenu
diff --git a/drivers/soc/xilinx/Makefile b/drivers/soc/xilinx/Makefile
index f66554c..dee8fd5 100644
--- a/drivers/soc/xilinx/Makefile
+++ b/drivers/soc/xilinx/Makefile
@@ -1 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_XILINX_VCU) += xlnx_vcu.o
diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c
new file mode 100644
index 0000000..46ec3fd
--- /dev/null
+++ b/drivers/soc/xilinx/xlnx_vcu.c
@@ -0,0 +1,630 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx VCU Init
+ *
+ * Copyright (C) 2016 - 2017 Xilinx, Inc.
+ *
+ * Contacts Dhaval Shah <dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ */
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+/* Address map for different registers implemented in the VCU LogiCORE IP. */
+#define VCU_ECODER_ENABLE 0x00
+#define VCU_DECODER_ENABLE 0x04
+#define VCU_MEMORY_DEPTH 0x08
+#define VCU_ENC_COLOR_DEPTH 0x0c
+#define VCU_ENC_VERTICAL_RANGE 0x10
+#define VCU_ENC_FRAME_SIZE_X 0x14
+#define VCU_ENC_FRAME_SIZE_Y 0x18
+#define VCU_ENC_COLOR_FORMAT 0x1c
+#define VCU_ENC_FPS 0x20
+#define VCU_MCU_CLK 0x24
+#define VCU_CORE_CLK 0x28
+#define VCU_PLL_BYPASS 0x2c
+#define VCU_ENC_CLK 0x30
+#define VCU_PLL_CLK 0x34
+#define VCU_ENC_VIDEO_STANDARD 0x38
+#define VCU_STATUS 0x3c
+#define VCU_AXI_ENC_CLK 0x40
+#define VCU_AXI_DEC_CLK 0x44
+#define VCU_AXI_MCU_CLK 0x48
+#define VCU_DEC_VIDEO_STANDARD 0x4c
+#define VCU_DEC_FRAME_SIZE_X 0x50
+#define VCU_DEC_FRAME_SIZE_Y 0x54
+#define VCU_DEC_FPS 0x58
+#define VCU_BUFFER_B_FRAME 0x5c
+#define VCU_WPP_EN 0x60
+#define VCU_PLL_CLK_DEC 0x64
+#define VCU_GASKET_INIT 0x74
+#define VCU_GASKET_VALUE 0x03
+
+/* vcu slcr registers, bitmask and shift */
+#define VCU_PLL_CTRL 0x24
+#define VCU_PLL_CTRL_RESET_MASK 0x01
+#define VCU_PLL_CTRL_RESET_SHIFT 0
+#define VCU_PLL_CTRL_BYPASS_MASK 0x01
+#define VCU_PLL_CTRL_BYPASS_SHIFT 3
+#define VCU_PLL_CTRL_FBDIV_MASK 0x7f
+#define VCU_PLL_CTRL_FBDIV_SHIFT 8
+#define VCU_PLL_CTRL_POR_IN_MASK 0x01
+#define VCU_PLL_CTRL_POR_IN_SHIFT 1
+#define VCU_PLL_CTRL_PWR_POR_MASK 0x01
+#define VCU_PLL_CTRL_PWR_POR_SHIFT 2
+#define VCU_PLL_CTRL_CLKOUTDIV_MASK 0x03
+#define VCU_PLL_CTRL_CLKOUTDIV_SHIFT 16
+#define VCU_PLL_CTRL_DEFAULT 0
+#define VCU_PLL_DIV2 2
+
+#define VCU_PLL_CFG 0x28
+#define VCU_PLL_CFG_RES_MASK 0x0f
+#define VCU_PLL_CFG_RES_SHIFT 0
+#define VCU_PLL_CFG_CP_MASK 0x0f
+#define VCU_PLL_CFG_CP_SHIFT 5
+#define VCU_PLL_CFG_LFHF_MASK 0x03
+#define VCU_PLL_CFG_LFHF_SHIFT 10
+#define VCU_PLL_CFG_LOCK_CNT_MASK 0x03ff
+#define VCU_PLL_CFG_LOCK_CNT_SHIFT 13
+#define VCU_PLL_CFG_LOCK_DLY_MASK 0x7f
+#define VCU_PLL_CFG_LOCK_DLY_SHIFT 25
+#define VCU_ENC_CORE_CTRL 0x30
+#define VCU_ENC_MCU_CTRL 0x34
+#define VCU_DEC_CORE_CTRL 0x38
+#define VCU_DEC_MCU_CTRL 0x3c
+#define VCU_PLL_DIVISOR_MASK 0x3f
+#define VCU_PLL_DIVISOR_SHIFT 4
+#define VCU_SRCSEL_MASK 0x01
+#define VCU_SRCSEL_SHIFT 0
+#define VCU_SRCSEL_PLL 1
+
+#define VCU_PLL_STATUS 0x60
+#define VCU_PLL_STATUS_LOCK_STATUS_MASK 0x01
+
+#define MHZ 1000000
+#define FVCO_MIN (1500U * MHZ)
+#define FVCO_MAX (3000U * MHZ)
+#define DIVISOR_MIN 0
+#define DIVISOR_MAX 63
+#define FRAC 100
+#define LIMIT (10 * MHZ)
+
+/**
+ * struct xvcu_device - Xilinx VCU init device structure
+ * @dev: Platform device
+ * @pll_ref: pll ref clock source
+ * @aclk: axi clock source
+ * @logicore_reg_ba: logicore reg base address
+ * @vcu_slcr_ba: vcu_slcr Register base address
+ * @coreclk: core clock frequency
+ */
+struct xvcu_device {
+ struct device *dev;
+ struct clk *pll_ref;
+ struct clk *aclk;
+ void __iomem *logicore_reg_ba;
+ void __iomem *vcu_slcr_ba;
+ u32 coreclk;
+};
+
+/**
+ * struct xvcu_pll_cfg - Helper data
+ * @fbdiv: The integer portion of the feedback divider to the PLL
+ * @cp: PLL charge pump control
+ * @res: PLL loop filter resistor control
+ * @lfhf: PLL loop filter high frequency capacitor control
+ * @lock_dly: Lock circuit configuration settings for lock windowsize
+ * @lock_cnt: Lock circuit counter setting
+ */
+struct xvcu_pll_cfg {
+ u32 fbdiv;
+ u32 cp;
+ u32 res;
+ u32 lfhf;
+ u32 lock_dly;
+ u32 lock_cnt;
+};
+
+static const struct xvcu_pll_cfg xvcu_pll_cfg[] = {
+ { 25, 3, 10, 3, 63, 1000 },
+ { 26, 3, 10, 3, 63, 1000 },
+ { 27, 4, 6, 3, 63, 1000 },
+ { 28, 4, 6, 3, 63, 1000 },
+ { 29, 4, 6, 3, 63, 1000 },
+ { 30, 4, 6, 3, 63, 1000 },
+ { 31, 6, 1, 3, 63, 1000 },
+ { 32, 6, 1, 3, 63, 1000 },
+ { 33, 4, 10, 3, 63, 1000 },
+ { 34, 5, 6, 3, 63, 1000 },
+ { 35, 5, 6, 3, 63, 1000 },
+ { 36, 5, 6, 3, 63, 1000 },
+ { 37, 5, 6, 3, 63, 1000 },
+ { 38, 5, 6, 3, 63, 975 },
+ { 39, 3, 12, 3, 63, 950 },
+ { 40, 3, 12, 3, 63, 925 },
+ { 41, 3, 12, 3, 63, 900 },
+ { 42, 3, 12, 3, 63, 875 },
+ { 43, 3, 12, 3, 63, 850 },
+ { 44, 3, 12, 3, 63, 850 },
+ { 45, 3, 12, 3, 63, 825 },
+ { 46, 3, 12, 3, 63, 800 },
+ { 47, 3, 12, 3, 63, 775 },
+ { 48, 3, 12, 3, 63, 775 },
+ { 49, 3, 12, 3, 63, 750 },
+ { 50, 3, 12, 3, 63, 750 },
+ { 51, 3, 2, 3, 63, 725 },
+ { 52, 3, 2, 3, 63, 700 },
+ { 53, 3, 2, 3, 63, 700 },
+ { 54, 3, 2, 3, 63, 675 },
+ { 55, 3, 2, 3, 63, 675 },
+ { 56, 3, 2, 3, 63, 650 },
+ { 57, 3, 2, 3, 63, 650 },
+ { 58, 3, 2, 3, 63, 625 },
+ { 59, 3, 2, 3, 63, 625 },
+ { 60, 3, 2, 3, 63, 625 },
+ { 61, 3, 2, 3, 63, 600 },
+ { 62, 3, 2, 3, 63, 600 },
+ { 63, 3, 2, 3, 63, 600 },
+ { 64, 3, 2, 3, 63, 600 },
+ { 65, 3, 2, 3, 63, 600 },
+ { 66, 3, 2, 3, 63, 600 },
+ { 67, 3, 2, 3, 63, 600 },
+ { 68, 3, 2, 3, 63, 600 },
+ { 69, 3, 2, 3, 63, 600 },
+ { 70, 3, 2, 3, 63, 600 },
+ { 71, 3, 2, 3, 63, 600 },
+ { 72, 3, 2, 3, 63, 600 },
+ { 73, 3, 2, 3, 63, 600 },
+ { 74, 3, 2, 3, 63, 600 },
+ { 75, 3, 2, 3, 63, 600 },
+ { 76, 3, 2, 3, 63, 600 },
+ { 77, 3, 2, 3, 63, 600 },
+ { 78, 3, 2, 3, 63, 600 },
+ { 79, 3, 2, 3, 63, 600 },
+ { 80, 3, 2, 3, 63, 600 },
+ { 81, 3, 2, 3, 63, 600 },
+ { 82, 3, 2, 3, 63, 600 },
+ { 83, 4, 2, 3, 63, 600 },
+ { 84, 4, 2, 3, 63, 600 },
+ { 85, 4, 2, 3, 63, 600 },
+ { 86, 4, 2, 3, 63, 600 },
+ { 87, 4, 2, 3, 63, 600 },
+ { 88, 4, 2, 3, 63, 600 },
+ { 89, 4, 2, 3, 63, 600 },
+ { 90, 4, 2, 3, 63, 600 },
+ { 91, 4, 2, 3, 63, 600 },
+ { 92, 4, 2, 3, 63, 600 },
+ { 93, 4, 2, 3, 63, 600 },
+ { 94, 4, 2, 3, 63, 600 },
+ { 95, 4, 2, 3, 63, 600 },
+ { 96, 4, 2, 3, 63, 600 },
+ { 97, 4, 2, 3, 63, 600 },
+ { 98, 4, 2, 3, 63, 600 },
+ { 99, 4, 2, 3, 63, 600 },
+ { 100, 4, 2, 3, 63, 600 },
+ { 101, 4, 2, 3, 63, 600 },
+ { 102, 4, 2, 3, 63, 600 },
+ { 103, 5, 2, 3, 63, 600 },
+ { 104, 5, 2, 3, 63, 600 },
+ { 105, 5, 2, 3, 63, 600 },
+ { 106, 5, 2, 3, 63, 600 },
+ { 107, 3, 4, 3, 63, 600 },
+ { 108, 3, 4, 3, 63, 600 },
+ { 109, 3, 4, 3, 63, 600 },
+ { 110, 3, 4, 3, 63, 600 },
+ { 111, 3, 4, 3, 63, 600 },
+ { 112, 3, 4, 3, 63, 600 },
+ { 113, 3, 4, 3, 63, 600 },
+ { 114, 3, 4, 3, 63, 600 },
+ { 115, 3, 4, 3, 63, 600 },
+ { 116, 3, 4, 3, 63, 600 },
+ { 117, 3, 4, 3, 63, 600 },
+ { 118, 3, 4, 3, 63, 600 },
+ { 119, 3, 4, 3, 63, 600 },
+ { 120, 3, 4, 3, 63, 600 },
+ { 121, 3, 4, 3, 63, 600 },
+ { 122, 3, 4, 3, 63, 600 },
+ { 123, 3, 4, 3, 63, 600 },
+ { 124, 3, 4, 3, 63, 600 },
+ { 125, 3, 4, 3, 63, 600 },
+};
+
+/**
+ * xvcu_read - Read from the VCU register space
+ * @iomem: vcu reg space base address
+ * @offset: vcu reg offset from base
+ *
+ * Return: Returns 32bit value from VCU register specified
+ *
+ */
+static inline u32 xvcu_read(void __iomem *iomem, u32 offset)
+{
+ return ioread32(iomem + offset);
+}
+
+/**
+ * xvcu_write - Write to the VCU register space
+ * @iomem: vcu reg space base address
+ * @offset: vcu reg offset from base
+ * @value: Value to write
+ */
+static inline void xvcu_write(void __iomem *iomem, u32 offset, u32 value)
+{
+ iowrite32(value, iomem + offset);
+}
+
+/**
+ * xvcu_write_field_reg - Write to the vcu reg field
+ * @iomem: vcu reg space base address
+ * @offset: vcu reg offset from base
+ * @field: vcu reg field to write to
+ * @mask: vcu reg mask
+ * @shift: vcu reg number of bits to shift the bitfield
+ */
+static void xvcu_write_field_reg(void __iomem *iomem, int offset,
+ u32 field, u32 mask, int shift)
+{
+ u32 val = xvcu_read(iomem, offset);
+
+ val &= ~(mask << shift);
+ val |= (field & mask) << shift;
+
+ xvcu_write(iomem, offset, val);
+}
+
+/**
+ * xvcu_set_vcu_pll_info - Set the VCU PLL info
+ * @xvcu: Pointer to the xvcu_device structure
+ *
+ * Programming the VCU PLL based on the user configuration
+ * (ref clock freq, core clock freq, mcu clock freq).
+ * Core clock frequency has higher priority than mcu clock frequency
+ * Errors in following cases
+ * - When mcu or clock clock get from logicoreIP is 0
+ * - When VCU PLL DIV related bits value other than 1
+ * - When proper data not found for given data
+ * - When sis570_1 clocksource related operation failed
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu)
+{
+ u32 refclk, coreclk, mcuclk, inte, deci;
+ u32 divisor_mcu, divisor_core, fvco;
+ u32 clkoutdiv, vcu_pll_ctrl, pll_clk;
+ u32 cfg_val, mod, ctrl;
+ int ret, i;
+ const struct xvcu_pll_cfg *found = NULL;
+
+ inte = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK);
+ deci = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK_DEC);
+ coreclk = xvcu_read(xvcu->logicore_reg_ba, VCU_CORE_CLK) * MHZ;
+ mcuclk = xvcu_read(xvcu->logicore_reg_ba, VCU_MCU_CLK) * MHZ;
+ if (!mcuclk || !coreclk) {
+ dev_err(xvcu->dev, "Invalid mcu and core clock data\n");
+ return -EINVAL;
+ }
+
+ refclk = (inte * MHZ) + (deci * (MHZ / FRAC));
+ dev_dbg(xvcu->dev, "Ref clock from logicoreIP is %uHz\n", refclk);
+ dev_dbg(xvcu->dev, "Core clock from logicoreIP is %uHz\n", coreclk);
+ dev_dbg(xvcu->dev, "Mcu clock from logicoreIP is %uHz\n", mcuclk);
+
+ clk_disable_unprepare(xvcu->pll_ref);
+ ret = clk_set_rate(xvcu->pll_ref, refclk);
+ if (ret)
+ dev_warn(xvcu->dev, "failed to set logicoreIP refclk rate\n");
+
+ ret = clk_prepare_enable(xvcu->pll_ref);
+ if (ret) {
+ dev_err(xvcu->dev, "failed to enable pll_ref clock source\n");
+ return ret;
+ }
+
+ refclk = clk_get_rate(xvcu->pll_ref);
+
+ /*
+ * The divide-by-2 should be always enabled (==1)
+ * to meet the timing in the design.
+ * Otherwise, it's an error
+ */
+ vcu_pll_ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_PLL_CTRL);
+ clkoutdiv = vcu_pll_ctrl >> VCU_PLL_CTRL_CLKOUTDIV_SHIFT;
+ clkoutdiv = clkoutdiv && VCU_PLL_CTRL_CLKOUTDIV_MASK;
+ if (clkoutdiv != 1) {
+ dev_err(xvcu->dev, "clkoutdiv value is invalid\n");
+ return -EINVAL;
+ }
+
+ for (i = ARRAY_SIZE(xvcu_pll_cfg) - 1; i >= 0; i--) {
+ const struct xvcu_pll_cfg *cfg = &xvcu_pll_cfg[i];
+
+ fvco = cfg->fbdiv * refclk;
+ if (fvco >= FVCO_MIN && fvco <= FVCO_MAX) {
+ pll_clk = fvco / VCU_PLL_DIV2;
+ if (fvco % VCU_PLL_DIV2 != 0)
+ pll_clk++;
+ mod = pll_clk % coreclk;
+ if (mod < LIMIT) {
+ divisor_core = pll_clk / coreclk;
+ } else if (coreclk - mod < LIMIT) {
+ divisor_core = pll_clk / coreclk;
+ divisor_core++;
+ } else {
+ continue;
+ }
+ if (divisor_core >= DIVISOR_MIN &&
+ divisor_core <= DIVISOR_MAX) {
+ found = cfg;
+ divisor_mcu = pll_clk / mcuclk;
+ mod = pll_clk % mcuclk;
+ if (mcuclk - mod < LIMIT)
+ divisor_mcu++;
+ break;
+ }
+ }
+ }
+
+ if (!found) {
+ dev_err(xvcu->dev, "Invalid clock combination.\n");
+ return -EINVAL;
+ }
+
+ xvcu->coreclk = pll_clk / divisor_core;
+ mcuclk = pll_clk / divisor_mcu;
+ dev_dbg(xvcu->dev, "Actual Ref clock freq is %uHz\n", refclk);
+ dev_dbg(xvcu->dev, "Actual Core clock freq is %uHz\n", xvcu->coreclk);
+ dev_dbg(xvcu->dev, "Actual Mcu clock freq is %uHz\n", mcuclk);
+
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_FBDIV_MASK << VCU_PLL_CTRL_FBDIV_SHIFT);
+ vcu_pll_ctrl |= (found->fbdiv & VCU_PLL_CTRL_FBDIV_MASK) <<
+ VCU_PLL_CTRL_FBDIV_SHIFT;
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_POR_IN_MASK <<
+ VCU_PLL_CTRL_POR_IN_SHIFT);
+ vcu_pll_ctrl |= (VCU_PLL_CTRL_DEFAULT & VCU_PLL_CTRL_POR_IN_MASK) <<
+ VCU_PLL_CTRL_POR_IN_SHIFT;
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_PWR_POR_MASK <<
+ VCU_PLL_CTRL_PWR_POR_SHIFT);
+ vcu_pll_ctrl |= (VCU_PLL_CTRL_DEFAULT & VCU_PLL_CTRL_PWR_POR_MASK) <<
+ VCU_PLL_CTRL_PWR_POR_SHIFT;
+ xvcu_write(xvcu->vcu_slcr_ba, VCU_PLL_CTRL, vcu_pll_ctrl);
+
+ /* Set divisor for the core and mcu clock */
+ ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_ENC_CORE_CTRL);
+ ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT);
+ ctrl |= (divisor_core & VCU_PLL_DIVISOR_MASK) <<
+ VCU_PLL_DIVISOR_SHIFT;
+ ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT);
+ ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT;
+ xvcu_write(xvcu->vcu_slcr_ba, VCU_ENC_CORE_CTRL, ctrl);
+
+ ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_DEC_CORE_CTRL);
+ ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT);
+ ctrl |= (divisor_core & VCU_PLL_DIVISOR_MASK) <<
+ VCU_PLL_DIVISOR_SHIFT;
+ ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT);
+ ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT;
+ xvcu_write(xvcu->vcu_slcr_ba, VCU_DEC_CORE_CTRL, ctrl);
+
+ ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_ENC_MCU_CTRL);
+ ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT);
+ ctrl |= (divisor_mcu & VCU_PLL_DIVISOR_MASK) << VCU_PLL_DIVISOR_SHIFT;
+ ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT);
+ ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT;
+ xvcu_write(xvcu->vcu_slcr_ba, VCU_ENC_MCU_CTRL, ctrl);
+
+ ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_DEC_MCU_CTRL);
+ ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT);
+ ctrl |= (divisor_mcu & VCU_PLL_DIVISOR_MASK) << VCU_PLL_DIVISOR_SHIFT;
+ ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT);
+ ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT;
+ xvcu_write(xvcu->vcu_slcr_ba, VCU_DEC_MCU_CTRL, ctrl);
+
+ /* Set RES, CP, LFHF, LOCK_CNT and LOCK_DLY cfg values */
+ cfg_val = (found->res << VCU_PLL_CFG_RES_SHIFT) |
+ (found->cp << VCU_PLL_CFG_CP_SHIFT) |
+ (found->lfhf << VCU_PLL_CFG_LFHF_SHIFT) |
+ (found->lock_cnt << VCU_PLL_CFG_LOCK_CNT_SHIFT) |
+ (found->lock_dly << VCU_PLL_CFG_LOCK_DLY_SHIFT);
+ xvcu_write(xvcu->vcu_slcr_ba, VCU_PLL_CFG, cfg_val);
+
+ return 0;
+}
+
+/**
+ * xvcu_set_pll - PLL init sequence
+ * @xvcu: Pointer to the xvcu_device structure
+ *
+ * Call the api to set the PLL info and once that is done then
+ * init the PLL sequence to make the PLL stable.
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int xvcu_set_pll(struct xvcu_device *xvcu)
+{
+ u32 lock_status;
+ unsigned long timeout;
+ int ret;
+
+ ret = xvcu_set_vcu_pll_info(xvcu);
+ if (ret) {
+ dev_err(xvcu->dev, "failed to set pll info\n");
+ return ret;
+ }
+
+ xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL,
+ 1, VCU_PLL_CTRL_BYPASS_MASK,
+ VCU_PLL_CTRL_BYPASS_SHIFT);
+ xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL,
+ 1, VCU_PLL_CTRL_RESET_MASK,
+ VCU_PLL_CTRL_RESET_SHIFT);
+ xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL,
+ 0, VCU_PLL_CTRL_RESET_MASK,
+ VCU_PLL_CTRL_RESET_SHIFT);
+ /*
+ * Defined the timeout for the max time to wait the
+ * PLL_STATUS to be locked.
+ */
+ timeout = jiffies + msecs_to_jiffies(2000);
+ do {
+ lock_status = xvcu_read(xvcu->vcu_slcr_ba, VCU_PLL_STATUS);
+ if (lock_status & VCU_PLL_STATUS_LOCK_STATUS_MASK) {
+ xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL,
+ 0, VCU_PLL_CTRL_BYPASS_MASK,
+ VCU_PLL_CTRL_BYPASS_SHIFT);
+ return 0;
+ }
+ } while (!time_after(jiffies, timeout));
+
+ /* PLL is not locked even after the timeout of the 2sec */
+ dev_err(xvcu->dev, "PLL is not locked\n");
+ return -ETIMEDOUT;
+}
+
+/**
+ * xvcu_probe - Probe existence of the logicoreIP
+ * and initialize PLL
+ *
+ * @pdev: Pointer to the platform_device structure
+ *
+ * Return: Returns 0 on success
+ * Negative error code otherwise
+ */
+static int xvcu_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct xvcu_device *xvcu;
+ int ret;
+
+ xvcu = devm_kzalloc(&pdev->dev, sizeof(*xvcu), GFP_KERNEL);
+ if (!xvcu)
+ return -ENOMEM;
+
+ xvcu->dev = &pdev->dev;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vcu_slcr");
+ if (!res) {
+ dev_err(&pdev->dev, "get vcu_slcr memory resource failed.\n");
+ return -ENODEV;
+ }
+
+ xvcu->vcu_slcr_ba = devm_ioremap_nocache(&pdev->dev,
+ res->start, resource_size(res));
+ if (!xvcu->vcu_slcr_ba) {
+ dev_err(&pdev->dev, "vcu_slcr register mapping failed.\n");
+ return -ENOMEM;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "logicore");
+ if (!res) {
+ dev_err(&pdev->dev, "get logicore memory resource failed.\n");
+ return -ENODEV;
+ }
+
+ xvcu->logicore_reg_ba = devm_ioremap_nocache(&pdev->dev,
+ res->start, resource_size(res));
+ if (!xvcu->logicore_reg_ba) {
+ dev_err(&pdev->dev, "logicore register mapping failed.\n");
+ return -ENOMEM;
+ }
+
+ xvcu->aclk = devm_clk_get(&pdev->dev, "aclk");
+ if (IS_ERR(xvcu->aclk)) {
+ dev_err(&pdev->dev, "Could not get aclk clock\n");
+ return PTR_ERR(xvcu->aclk);
+ }
+
+ xvcu->pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
+ if (IS_ERR(xvcu->pll_ref)) {
+ dev_err(&pdev->dev, "Could not get pll_ref clock\n");
+ return PTR_ERR(xvcu->pll_ref);
+ }
+
+ ret = clk_prepare_enable(xvcu->aclk);
+ if (ret) {
+ dev_err(&pdev->dev, "aclk clock enable failed\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(xvcu->pll_ref);
+ if (ret) {
+ dev_err(&pdev->dev, "pll_ref clock enable failed\n");
+ goto error_aclk;
+ }
+
+ /*
+ * Do the Gasket isolation and put the VCU out of reset
+ * Bit 0 : Gasket isolation
+ * Bit 1 : put VCU out of reset
+ */
+ xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, VCU_GASKET_VALUE);
+
+ /* Do the PLL Settings based on the ref clk,core and mcu clk freq */
+ ret = xvcu_set_pll(xvcu);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to set the pll\n");
+ goto error_pll_ref;
+ }
+
+ dev_set_drvdata(&pdev->dev, xvcu);
+
+ dev_info(&pdev->dev, "%s: Probed successfully\n", __func__);
+
+ return 0;
+
+error_pll_ref:
+ clk_disable_unprepare(xvcu->pll_ref);
+error_aclk:
+ clk_disable_unprepare(xvcu->aclk);
+ return ret;
+}
+
+/**
+ * xvcu_remove - Insert gasket isolation
+ * and disable the clock
+ * @pdev: Pointer to the platform_device structure
+ *
+ * Return: Returns 0 on success
+ * Negative error code otherwise
+ */
+static int xvcu_remove(struct platform_device *pdev)
+{
+ struct xvcu_device *xvcu;
+
+ xvcu = platform_get_drvdata(pdev);
+ if (!xvcu)
+ return -ENODEV;
+
+ /* Add the the Gasket isolation and put the VCU in reset. */
+ xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0);
+
+ clk_disable_unprepare(xvcu->pll_ref);
+ clk_disable_unprepare(xvcu->aclk);
+
+ return 0;
+}
+
+static const struct of_device_id xvcu_of_id_table[] = {
+ { .compatible = "xlnx,vcu" },
+ { .compatible = "xlnx,vcu-logicoreip-1.0" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, xvcu_of_id_table);
+
+static struct platform_driver xvcu_driver = {
+ .driver = {
+ .name = "xilinx-vcu",
+ .of_match_table = xvcu_of_id_table,
+ },
+ .probe = xvcu_probe,
+ .remove = xvcu_remove,
+};
+
+module_platform_driver(xvcu_driver);
+
+MODULE_AUTHOR("Dhaval Shah <dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>");
+MODULE_DESCRIPTION("Xilinx VCU init Driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
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^ permalink raw reply related
* [PATCH 2/3] dt-bindings: update compatible string for ILI9225
From: David Lechner @ 2017-12-21 18:33 UTC (permalink / raw)
To: dri-devel, devicetree
Cc: Mark Rutland, limor, David Lechner, linux-kernel, Rob Herring
In-Reply-To: <1513881187-3197-1-git-send-email-david@lechnology.com>
This updates the compatible string for a no-name LCD panel to
"vot,v220hf01a-t", "ilitek,ili9225".
The original bindings [1] were the generic "ilitek,ili9225-2.2in-176x220"
because I could not find a datasheet. However, after some more research,
I finally found one, so the actual vendor and model name are now known.
This previous bindings have not made it to the mainline kernel yet, so
this is not breaking backwards compatibility.
This is also following the precedence of the ILI9322 bindings [2] by using
the pattern "vendor,specific-system-config", "vendor,ip-part";
[1]: https://patchwork.ozlabs.org/patch/839352/
[2]: https://patchwork.ozlabs.org/patch/843576/
Signed-off-by: David Lechner <david@lechnology.com>
---
Documentation/devicetree/bindings/display/ilitek,ili9225.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9225.txt b/Documentation/devicetree/bindings/display/ilitek,ili9225.txt
index 21607a5..a59feb5 100644
--- a/Documentation/devicetree/bindings/display/ilitek,ili9225.txt
+++ b/Documentation/devicetree/bindings/display/ilitek,ili9225.txt
@@ -4,7 +4,7 @@ This binding is for display panels using an Ilitek ILI9225 controller in SPI
mode.
Required properties:
-- compatible: "ilitek,ili9225-2.2in-176x220"
+- compatible: "vot,v220hf01a-t", "ilitek,ili9225"
- rs-gpios: Register select signal
- reset-gpios: Reset pin
@@ -16,7 +16,7 @@ Optional properties:
Example:
display@0{
- compatible = "ilitek,ili9225-2.2in-176x220";
+ compatible = "vot,v220hf01a-t", "ilitek,ili9225";
reg = <0>;
spi-max-frequency = <12000000>;
rs-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
--
2.7.4
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^ permalink raw reply related
* [PATCH v6 1/2] dt-bindings: soc: xilinx: Add DT bindings to xlnx_vcu driver
From: Dhaval Shah @ 2017-12-21 18:33 UTC (permalink / raw)
To: arnd, rdunlap, gregkh, pombredanne, robh+dt, mark.rutland,
michal.simek
Cc: linux-arm-kernel, devicetree, linux-kernel, hyunk, Dhaval Shah
In-Reply-To: <1513881186-26020-1-git-send-email-dshah@xilinx.com>
Add Device Tree binding document for logicoreIP. This logicoreIP
provides the isolation between the processing system and
programmable logic. Also provides the clock related information.
Signed-off-by: Dhaval Shah <dshah@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since v6:
* Updated path of the dt-bindings doc as driver path is updated.
Chnages since v5:
No Changes.
Chnages since v4:
No Changes.
Chnages since v3:
* Use "dt-bindings: misc: ..." for the subject.
Changes since v2:
* Describe the h/w
* compatible string is updated to make it more specific
based on the logicoreIP version.
* Removed that encoder and decoder child nodes and relatd properties as that
will be a separate driver and dts nodes. other team is working on that.
* Updated to use as a single driver.
.../devicetree/bindings/soc/xilinx/xlnx,vcu.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt
diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt b/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt
new file mode 100644
index 0000000..6786d67
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt
@@ -0,0 +1,31 @@
+LogicoreIP designed compatible with Xilinx ZYNQ family.
+-------------------------------------------------------
+
+General concept
+---------------
+
+LogicoreIP design to provide the isolation between processing system
+and programmable logic. Also provides the list of register set to configure
+the frequency.
+
+Required properties:
+- compatible: shall be one of:
+ "xlnx,vcu"
+ "xlnx,vcu-logicoreip-1.0"
+- reg, reg-names: There are two sets of registers need to provide.
+ 1. vcu slcr
+ 2. Logicore
+ reg-names should contain name for the each register sequence.
+- clocks: phandle for aclk and pll_ref clocksource
+- clock-names: The identification string, "aclk", is always required for
+ the axi clock. "pll_ref" is required for pll.
+Example:
+
+ xlnx_vcu: vcu@a0040000 {
+ compatible = "xlnx,vcu-logicoreip-1.0";
+ reg = <0x0 0xa0040000 0x0 0x1000>,
+ <0x0 0xa0041000 0x0 0x1000>;
+ reg-names = "vcu_slcr", "logicore";
+ clocks = <&si570_1>, <&clkc 71>;
+ clock-names = "pll_ref", "aclk";
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH 1/3] dt-bindings: Add "vot" vendor prefix
From: David Lechner @ 2017-12-21 18:33 UTC (permalink / raw)
To: dri-devel, devicetree
Cc: Mark Rutland, limor, David Lechner, linux-kernel, Rob Herring
In-Reply-To: <1513881187-3197-1-git-send-email-david@lechnology.com>
This adds a vendor prefix "vot" for Vision Optical Technology Co., Ltd.
They make LCD displays.
Signed-off-by: David Lechner <david@lechnology.com>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 41cb1ff0..267d33b 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -380,6 +380,7 @@ virtio Virtual I/O Device Specification, developed by the OASIS consortium
vivante Vivante Corporation
vocore VoCore Studio
voipac Voipac Technologies s.r.o.
+vot Vision Optical Technology Co., Ltd.
wd Western Digital Corp.
wetek WeTek Electronics, limited.
wexler Wexler
--
2.7.4
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^ permalink raw reply related
* [PATCH v6 0/2] Documentation and driver of logicoreIP
From: Dhaval Shah @ 2017-12-21 18:33 UTC (permalink / raw)
To: arnd, rdunlap, gregkh, pombredanne, robh+dt, mark.rutland,
michal.simek
Cc: devicetree, hyunk, linux-kernel, linux-arm-kernel, Dhaval Shah
In-Reply-To: <CAK8P3a0z6HF8Rg08HUj7_T+7ZxxnHoReiu68bNzF6CnEooQSdA@mail.gmail.com>
1st patch provide Device Tree binding document for logicoreIP
2nd patch provide the xlnx_vcu logicoreIP driver, Kconfig changes
and Makefile changes for the driver.
Dhaval Shah (2):
dt-bindings: misc: Add DT bindings to xlnx_vcu driver
misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
.../devicetree/bindings/soc/xilinx/xlnx,vcu.txt | 31 +
drivers/soc/xilinx/Kconfig | 15 +
drivers/soc/xilinx/Makefile | 1 +
drivers/soc/xilinx/xlnx_vcu.c | 630 +++++++++++++++++++++
4 files changed, 677 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt
create mode 100644 drivers/soc/xilinx/xlnx_vcu.c
--
2.7.4
^ permalink raw reply
* [PATCH 0/3] update compatible string for ILI9225
From: David Lechner @ 2017-12-21 18:33 UTC (permalink / raw)
To: dri-devel, devicetree
Cc: Mark Rutland, limor, David Lechner, linux-kernel, Rob Herring
This updates the device tree compatible string for an ILI9225 display.
Detailed explanation is in the patches.
David Lechner (3):
dt-bindings: Add "vot" vendor prefix
dt-bindings: update compatible string for ILI9225
drm/tinydrm: Update ILI9225 compatible string
Documentation/devicetree/bindings/display/ilitek,ili9225.txt | 4 ++--
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
drivers/gpu/drm/tinydrm/ili9225.c | 4 ++--
3 files changed, 5 insertions(+), 4 deletions(-)
--
2.7.4
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^ permalink raw reply
* Re: [PATCH v2] ARM: dts: sunxi: Add sid for a83t
From: Emmanuel Vadot @ 2017-12-21 18:09 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, linux-kernel, Russell King, linux-sunxi,
Rob Herring, Srinivas Kandagatla, Kyle Evans, Chen-Yu Tsai,
linux-arm-kernel
In-Reply-To: <20171221152630.2vf57x5o2yi5sv3n@flea.lan>
Hi Maxime,
On Thu, 21 Dec 2017 16:26:30 +0100
Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Thu, Dec 21, 2017 at 09:19:24AM -0600, Kyle Evans wrote:
> > On Thu, Dec 21, 2017 at 8:55 AM, Maxime Ripard
> > <maxime.ripard@free-electrons.com> wrote:
> > > Hi Kyle,
> > >
> > > On Tue, Dec 19, 2017 at 03:05:23PM -0600, kevans91@ksu.edu wrote:
> > >> Allwinner a83t has a 1 KB sid block with efuse for security rootkey and
> > >> thermal calibration data, add node to describe it.
> > >>
> > >> a83t-sid is not currently supported by nvmem/sunxi-sid, but it is
> > >> supported in an external driver for FreeBSD.
> > >>
> > >> Signed-off-by: Kyle Evans <kevans91@ksu.edu>
> > >
> > > The patch looks fine in itself, but we've had a number of issues with
> > > the register layout (and access patterns) in the past, so I'd rather
> > > have something that works in Linux too if possible.
> >
> > I have a patch that I think should make it work fine on Linux [1], but
> > I'm afraid I have little to no capability to test it myself and so I
> > did not add it as well.
> >
> > I do know that the rootkey is offset 0x200 into the given space [2],
> > as is the case with the H3, and that the readout quirk is not needed.
> > I wasn't 100% sure that the a83t has 2Kbit worth of efuse space as the
> > H3, but I do know that thermal data can be found at 0x34 and 0x38 in
> > this space.
>
> Then maybe we should leave it aside until someone takes some time on
> the A83t.
Take some time on the Linux driver and do not apply this patch for
now you mean ?
Cheers,
> The good news is that the binding itself looks fine, so as
> far as FreeBSD goes, there shouldn't be anything preventing you from
> using it I guess.
>
> Chen-Yu, what do you think?
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
--
Emmanuel Vadot <manu@bidouilliste.com>
^ permalink raw reply
* Re: [PATCH 4/4] ARM: dts: vf610-zii-dev-rev-b: add interrupts for 88e1545 PHY
From: Russell King - ARM Linux @ 2017-12-21 17:32 UTC (permalink / raw)
To: Andrew Lunn
Cc: Linus Walleij, Mark Rutland, Rob Herring, Sascha Hauer, Shawn Guo,
Stefan Agner, Florian Fainelli,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM
In-Reply-To: <20171221134058.GA15416-g2DYL2Zd6BY@public.gmane.org>
On Thu, Dec 21, 2017 at 02:40:58PM +0100, Andrew Lunn wrote:
> On Thu, Dec 21, 2017 at 01:32:21PM +0100, Linus Walleij wrote:
> > On Thu, Dec 21, 2017 at 12:12 AM, Russell King
> > <rmk+kernel-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> wrote:
> >
> > > The 88e1545 PHY has its interrupts wired to the VF610, so we might as
> > > well use them.
> > >
> > > Signed-off-by: Russell King <rmk+kernel-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>
> > > ---
> > > This is certainly not correct, as all PHYs on this device share the
> > > same interrupt line, but we can't specify the pinmux settings
> > > individually on each PHY. How should this be handled?
> >
> > I do not know the details of the Marvell switch.
>
> Hi Linus
>
> The 88e1545 is a discreet quad PHY. It is connected to the switch, but
> not integrated into the switch. All its interrupt handling is done
> with a GPIO onto the Freescale processor, via a GPIO. There is nothing
> DSA related here at all with respect to the interrupt. It is just a
> normal GPIO interrupt. What is a bit odd is that it one shared
> interrupt for all four PHYs.
>
> What you described with an irqchip inside the switch is what we
> actually do for the internal PHYs on Marvell devices. And it is what i
> recommend for all DSA drivers. Expose standard IRQs, and let phylib
> use them in its normal way.
... and it has to be said that model doesn't work in this case,
because, although there is the possibility to demux the interrupt
any of the PHYs, you already need to be driving one of the PHYs.
It's not an interrupt controller itself (there's no possibility to
enable/disable individual interrupts from a PHY) so it doesn't make
sense.
What we have here is _really_ a shared interrupt between four
separate devices, and we need a way to sanely describe resources
shared between several device instances to pinmux. Unfortunately,
it seems pinmux is designed around one device having exclusive use
of a resource, which makes it hard to describe shared interrupts in
DT.
Given that DT should be a description of the hardware, and should be
independent of the OS implementation, I'd say this is a pinmux bug,
because pinmux gets in the way of describing the hardware correctly.
;)
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
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^ permalink raw reply
* Re: [PATCH v10 11/13] slimbus: qcom: Add Qualcomm Slimbus controller driver
From: Arnd Bergmann @ 2017-12-21 17:26 UTC (permalink / raw)
To: Srinivas Kandagatla
Cc: Mark Brown, Greg Kroah-Hartman, alsa-devel, sdharia, Rob Herring,
Mark Rutland, Jonathan Corbet, Philippe Ombredanne,
nathan=20Neusch=C3=A4fer?=, linux-arm-msm, DTML,
Linux Kernel Mailing List, linux-doc, Andy Gross, David Brown,
Bjorn Andersson
In-Reply-To: <20171211234307.14465-12-srinivas.kandagatla@linaro.org>
> +
> + ctrl->tx.base = dmam_alloc_coherent(&pdev->dev,
> + (ctrl->tx.sl_sz * ctrl->tx.n),
> + &ctrl->tx.phy, GFP_KERNEL);
> + if (!ctrl->tx.base) {
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + ctrl->rx.base = dmam_alloc_coherent(&pdev->dev,
> + (ctrl->rx.sl_sz * ctrl->rx.n),
> + &ctrl->rx.phy, GFP_KERNEL);
I got another one of
/git/arm-soc/drivers/slimbus/qcom-ctrl.c: In function 'qcom_slim_probe':
/git/arm-soc/drivers/slimbus/qcom-ctrl.c:584:9: error: passing
argument 3 of 'dmam_alloc_coherent' from incompatible pointer type
[-Werror=incompatible-pointer-types]
&ctrl->tx.phy, GFP_KERNEL);
^
In file included from /git/arm-soc/drivers/slimbus/qcom-ctrl.c:16:0:
/git/arm-soc/include/linux/dma-mapping.h:760:14: note: expected
'dma_addr_t * {aka unsigned int *}' but argument is of type
'phys_addr_t * {aka long long unsigned int *}'
extern void *dmam_alloc_coherent(struct device *dev, size_t size,
^~~~~~~~~~~~~~~~~~~
/git/arm-soc/drivers/slimbus/qcom-ctrl.c:592:9: error: passing
argument 3 of 'dmam_alloc_coherent' from incompatible pointer type
[-Werror=incompatible-pointer-types]
&ctrl->rx.phy, GFP_KERNEL);
^
In file included from /git/arm-soc/drivers/slimbus/qcom-ctrl.c:16:0:
/git/arm-soc/include/linux/dma-mapping.h:760:14: note: expected
'dma_addr_t * {aka unsigned int *}' but argument is of type
'phys_addr_t * {aka long long unsigned int *}'
extern void *dmam_alloc_coherent(struct device *dev, size_t size,
I don't have time to analyze this further, but I guess this is the
same confusion
that happened in a few other qualcomm drivers, which all used dma_alloc_*
to get a buffer that gets passed into firmware.This is always wrong.
Arnd
^ permalink raw reply
* Re: [PATCH v2 1/5] dt-bindings: at24: consistently document the compatible property
From: David Lechner @ 2017-12-21 17:25 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Peter Rosin, Andy Shevchenko, Rob Herring, Mark Rutland,
Javier Martinez Canillas, Divagar Mohandass,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <f5d14ee3-1f80-6709-c5e5-36f65c1a9b84-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
On 12/21/2017 11:24 AM, David Lechner wrote:
> Also, at,24c08 is listed in
> Documentation/devicetree/bindings/trivial-devices.txt. It should
> probably be removed.
And st,24c256
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^ permalink raw reply
* Re: [PATCH v2 1/5] dt-bindings: at24: consistently document the compatible property
From: David Lechner @ 2017-12-21 17:24 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Peter Rosin, Andy Shevchenko, Rob Herring, Mark Rutland,
Javier Martinez Canillas, Divagar Mohandass, linux-i2c,
devicetree, linux-kernel
In-Reply-To: <0c2455ae-2f68-5342-14c6-14706d6f0e66@axentia.se>
On 12/21/2017 10:20 AM, Peter Rosin wrote:
> On 2017-12-21 14:48, Bartosz Golaszewski wrote:
>> Current description of the compatible property for at24 is quite vague.
>>
>> Specify an exact list of accepted compatibles and document the - now
>> deprecated - strings which were previously used in device tree files.
>
> Why is it suddenly deprecated to correctly specify what hardware you
> have, e.g. "nxp,24c32". In this case the manufacturer is nxp, damnit.
> Sure, it happens to be compatible with "atmel,24c32", but that is
> supposed to be written with a fallback as
>
> "nxp,24c32", "atmel,24c32"
>
> if I understand correctly. So, why is that deprecated in this case?
>
> What if (a few years down the line) it is discovered that some weird
> quirk is needed that is only appropriate for nxp chips?
>
> nxp is of course just an example, pick any manufacturer of eeproms
> (supposedly) compatible with the atmel interface.
>
So now I am supposed to change my device tree from "microchip,24c128" to
"atmel,24c128"?
Also, at,24c08 is listed in
Documentation/devicetree/bindings/trivial-devices.txt. It should
probably be removed.
^ permalink raw reply
* Re: [PATCH V2 3/9] ARM: stm32: prepare stm32 family to welcome armv7 architecture
From: Ludovic BARRE @ 2017-12-21 16:39 UTC (permalink / raw)
To: Alexandre Torgue, Arnd Bergmann
Cc: Russell King, Rob Herring, Linus Walleij, Maxime Coquelin,
Gerald Baeza, Linux ARM, Linux Kernel Mailing List, DTML
In-Reply-To: <8092d8f9-c097-136f-4f6f-0b7ffea17c91-qxv4g6HH51o@public.gmane.org>
hi Arnd
just a ping, on Alex's proposal (below) about armv7m_restart
(Currently "restart" is not functional on stm32 MCU).
BR
Ludo
On 12/19/2017 03:38 PM, Alexandre Torgue wrote:
>
>
> On 12/18/2017 09:24 PM, Arnd Bergmann wrote:
>> On Mon, Dec 18, 2017 at 4:17 PM, Ludovic Barre <ludovic.Barre-qxv4g6HH51o@public.gmane.org>
>> wrote:
>>> From: Ludovic Barre <ludovic.barre-qxv4g6HH51o@public.gmane.org>
>>>
>>> This patch prepares the STM32 machine for the integration of Cortex-A
>>> based microprocessor (MPU), on top of the existing Cortex-M
>>> microcontroller family (MCU). Since both MCUs and MPUs are sharing
>>> common hardware blocks we can keep using ARCH_STM32 flag for most of
>>> them. If a hardware block is specific to one family we can use either
>>> ARM_SINGLE_ARMV7M or ARCH_MULTI_V7 flag.
>>>
>>> Signed-off-by: Ludovic Barre <ludovic.barre-qxv4g6HH51o@public.gmane.org>
>>
>> Looks good overall. Two more small comments:
>>
>>
>>>
>>> +if ARCH_STM32
>>> +
>>> config MACH_STM32F429
>>> - bool "STMicrolectronics STM32F429"
>>> - depends on ARCH_STM32
>>> + bool "STMicroelectronics STM32F429"
>>> + depends on ARM_SINGLE_ARMV7M
>>> default y
>>
>> Instead of the explicit dependency for each board, I'd leave the
>> surrounding
>> 'if ARM_SINGLE_ARMV7M'. I think you had in v1.
>>
>>> diff --git a/arch/arm/mach-stm32/Makefile b/arch/arm/mach-stm32/Makefile
>>> index bd0b7b5..5940af1 100644
>>> --- a/arch/arm/mach-stm32/Makefile
>>> +++ b/arch/arm/mach-stm32/Makefile
>>> @@ -1 +1 @@
>>> -obj-y += board-dt.o
>>> +obj-$(CONFIG_ARM_SINGLE_ARMV7M) += board-mcu-dt.o
>>> diff --git a/arch/arm/mach-stm32/board-dt.c
>>> b/arch/arm/mach-stm32/board-mcu-dt.c
>>> similarity index 100%
>>> rename from arch/arm/mach-stm32/board-dt.c
>>> rename to arch/arm/mach-stm32/board-mcu-dt.c
>>
>> Why the rename? I don't expect the new machines to have any notable
>> contents in a board file, if any at all, so just use one file for both.
>> I see the board-dt.c file refers to armv7m_restart, we can either put
>> that in an #ifdef, or find a way to make it the default for all armv7-m
>> platforms that don't provide any other restart method.
>>
> Currently "restart" is not functional on stm32 MCU (at least for
> stm32f746, I will check on others MCU). My fear is if Ludovic made some
> patches to make "armv7m_restart" the default ".restart" function for all
> armv7-m platform, he will not be able to test it on stm32 MCU (as it is
> not currently working). I propose to do it in 2 steps:
>
> 1-Keep as you suggest only one board-dt.c file for both (MCU and MPU)
> and remove ".restart" function.
>
> 2-Investigate and send patches around ".restart" for both in an other
> series.
I resend
>
> regards
> Alex
>
>
>> Arnd
>>
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^ permalink raw reply
* Re: [PATCH] devicetree: Add video bus switch
From: Ivaylo Dimitrov @ 2017-12-21 16:36 UTC (permalink / raw)
To: Laurent Pinchart, Pavel Machek
Cc: Sakari Ailus, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA, sre-DgEjT+Ai2ygdnm+yROfE0A,
pali.rohar-Re5JQEeQqe8AvxtiuMwx3w,
linux-media-u79uwXL29TY76Z2rM5mHXA, galak-sgV2jX0FEOL9JmXXK+q4OQ,
mchehab-JPH+aEBZ4P+UEJcrhfAQsw,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <75694885.3PuLWzx4qN@avalon>
Hi,
On 20.12.2017 19:54, Laurent Pinchart wrote:
> Hi Pavel,
>
> On Saturday, 4 February 2017 23:56:10 EET Pavel Machek wrote:
>> Hi!
>>
>>>>>> +Required properties
>>>>>> +===================
>>>>>> +
>>>>>> +compatible : must contain "video-bus-switch"
>>>>>
>>>>> How generic is this? Should we have e.g. nokia,video-bus-switch? And
>>>>> if so, change the file name accordingly.
>>>>
>>>> Generic for "single GPIO controls the switch", AFAICT. But that should
>>>> be common enough...
>>>
>>> Um, yes. Then... how about: video-bus-switch-gpio? No Nokia prefix.
>>
>> Ok, done. I also fixed the english a bit.
>>
>>>>>> +reg : The interface:
>>>>>> + 0 - port for image signal processor
>>>>>> + 1 - port for first camera sensor
>>>>>> + 2 - port for second camera sensor
>>>>>
>>>>> I'd say this must be pretty much specific to the one in N900. You
>>>>> could have more ports. Or you could say that ports beyond 0 are
>>>>> camera sensors. I guess this is good enough for now though, it can be
>>>>> changed later on with the source if a need arises.
>>>>
>>>> Well, I'd say that selecting between two sensors is going to be the
>>>> common case. If someone needs more than two, it will no longer be
>>>> simple GPIO, so we'll have some fixing to do.
>>>
>>> It could be two GPIOs --- that's how the GPIO I2C mux works.
>>>
>>> But I'd be surprised if someone ever uses something like that
>>> again. ;-)
>>
>> I'd say.. lets handle that when we see hardware like that.
>>
>>>>> Btw. was it still considered a problem that the endpoint properties
>>>>> for the sensors can be different? With the g_routing() pad op which is
>>>>> to be added, the ISP driver (should actually go to a framework
>>>>> somewhere) could parse the graph and find the proper endpoint there.
>>>>
>>>> I don't know about g_routing. I added g_endpoint_config method that
>>>> passes the configuration, and that seems to work for me.
>>>>
>>>> I don't see g_routing in next-20170201 . Is there place to look?
>>>
>>> I think there was a patch by Laurent to LMML quite some time ago. I
>>> suppose that set will be repicked soonish.
>>>
>>> I don't really object using g_endpoint_config() as a temporary solution;
>>> I'd like to have Laurent's opinion on that though. Another option is to
>>> wait, but we've already waited a looong time (as in total).
>>
>> Laurent, do you have some input here? We have simple "2 cameras
>> connected to one signal processor" situation here. We need some way of
>> passing endpoint configuration from the sensors through the switch. I
>> did this:
>
> Could you give me a bit more information about the platform you're targeting:
> how the switch is connected, what kind of switch it is, and what endpoint
http://plan9.stanleylieber.com/hardware/n900/n900.schematics.pdf, on
page 2, see N5801 and N5802.
> configuration data you need ?
>
>>>> @@ -415,6 +416,8 @@ struct v4l2_subdev_video_ops {
>>>> const struct v4l2_mbus_config *cfg);
>>>> int (*s_rx_buffer)(struct v4l2_subdev *sd, void *buf,
>>>> unsigned int *size);
>>>> + int (*g_endpoint_config)(struct v4l2_subdev *sd,
>>>> + struct v4l2_of_endpoint *cfg);
>>
>> Google of g_routing tells me:
>>
>> 9) Highly reconfigurable hardware - Julien Beraud
>>
>> - 44 sub-devices connected with an interconnect.
>> - As long as formats match, any sub-device could be connected to any
>> - other sub-device through a link.
>> - The result is 44 * 44 links at worst.
>> - A switch sub-device proposed as the solution to model the
>> - interconnect. The sub-devices are connected to the switch
>> - sub-devices through the hardware links that connect to the
>> - interconnect.
>> - The switch would be controlled through new IOCTLs S_ROUTING and
>> - G_ROUTING.
>> - Patches available:
>> http://git.linuxtv.org/cgit.cgi/pinchartl/media.git/log/?h=xilinx-wip
>>
>> but the patches are from 2005. So I guess I'll need some guidance here...
>
> You made me feel very old for a moment. The patches are from 2015 :-)
>
>>> I'll reply to the other patch containing the code.
>
Regards,
Ivo
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* Re: [RFC 2/2] pci: dwc: pci-exynos: add the codes to support the exynos5433
From: Jingoo Han @ 2017-12-21 16:27 UTC (permalink / raw)
To: 'Jaehoon Chung', linux-pci-u79uwXL29TY76Z2rM5mHXA
Cc: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, krzk-DgEjT+Ai2ygdnm+yROfE0A,
kgene-DgEjT+Ai2ygdnm+yROfE0A, lorenzo.pieralisi-5wv7dgnIgG8
In-Reply-To: <000401d37a76$899613c0$9cc23b40$@gmail.com>
On Thursday, December 21, 2017 11:13 AM, Jingoo Han wrote:
> On Thursday, December 21, 2017 7:14 AM, Jaehoon Chung wrote:
> >
> > Exynos5433 has the PCIe for WiFi.
> > Added the codes relevant to PCIe for supporting the exynos5433.
> > Also changed the binding documentation name to
> > 'samsung,exynos-pcie.txt'.
> > (It's not only exynos5440 anymore.)
> >
>
> I have no objection.
> However, I added some comments about Exynos5440.
>
> > Signed-off-by: Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> > ---
> > ...exynos5440-pcie.txt => samsung,exynos-pcie.txt} | 2 +-
> > drivers/pci/dwc/pci-exynos.c | 183
> ++++++++++++++++-----
> > 2 files changed, 144 insertions(+), 41 deletions(-)
> > rename Documentation/devicetree/bindings/pci/{samsung,exynos5440-
> pcie.txt
> > => samsung,exynos-pcie.txt} (97%)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> > pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.txt
> > similarity index 97%
> > rename from Documentation/devicetree/bindings/pci/samsung,exynos5440-
> > pcie.txt
> > rename to Documentation/devicetree/bindings/pci/samsung,exynos-pcie.txt
> > index 34a11bfbfb60..958dcc150505 100644
> > --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> > +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.txt
> > @@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsys
> > DesignWare PCIe IP
> > and thus inherits all the common properties defined in designware-
> > pcie.txt.
> >
> > Required properties:
> > -- compatible: "samsung,exynos5440-pcie"
> > +- compatible: "samsung,exynos5440-pcie" or "samsung,exynos5433-pcie"
> > - reg: base addresses and lengths of the PCIe controller,
> > the PHY controller, additional register for the PHY controller.
> > (Registers for the PHY controller are DEPRECATED.
> > diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
> > index 5596fdedbb94..8dee2e90347e 100644
> > --- a/drivers/pci/dwc/pci-exynos.c
> > +++ b/drivers/pci/dwc/pci-exynos.c
> > @@ -40,6 +40,8 @@
> > #define PCIE_IRQ_SPECIAL 0x008
> > #define PCIE_IRQ_EN_PULSE 0x00c
> > #define PCIE_IRQ_EN_LEVEL 0x010
> > +#define PCIE_SW_WAKE 0x018
> > +#define PCIE_BUS_EN BIT(1)
> > #define IRQ_MSI_ENABLE BIT(2)
> > #define PCIE_IRQ_EN_SPECIAL 0x014
> > #define PCIE_PWR_RESET 0x018
> > @@ -49,7 +51,8 @@
> > #define PCIE_NONSTICKY_RESET 0x024
> > #define PCIE_APP_INIT_RESET 0x028
> > #define PCIE_APP_LTSSM_ENABLE 0x02c
> > -#define PCIE_ELBI_RDLH_LINKUP 0x064
> > +#define PCIE_ELBI_RDLH_LINKUP 0x074
>
> The address of this register should be 0x064 for exynos5440.
> Howe about the following?
>
> +#define EXYNOS5440_PCIE_ELBI_RDLH_LINKUP 0x064
> +#define PCIE_ELBI_RDLH_LINKUP 0x074
>
> Or you can add the following.
>
> /* Exynos5440 PCIe ELBI registers */
> #define EXYNOS5440_PCIE_ELBI_RDLH_LINKUP 0x064
>
> > +#define PCIE_ELBI_XMLH_LINKUP BIT(4)
> > #define PCIE_ELBI_LTSSM_ENABLE 0x1
> > #define PCIE_ELBI_SLV_AWMISC 0x11c
> > #define PCIE_ELBI_SLV_ARMISC 0x120
> > @@ -94,6 +97,10 @@
> > #define PCIE_PHY_TRSV3_PD_TSV BIT(7)
> > #define PCIE_PHY_TRSV3_LVCC 0x31c
> >
> > +/* DBI register */
> > +#define PCIE_MISC_CONTROL_1_OFF 0x8BC
> > +#define DBI_RO_WR_EN BIT(0)
> > +
> > struct exynos_pcie_mem_res {
> > void __iomem *elbi_base; /* DT 0th resource: PCIe CTRL */
> > void __iomem *phy_base; /* DT 1st resource: PHY CTRL */
> > @@ -221,6 +228,96 @@ static const struct exynos_pcie_ops
> > exynos5440_pcie_ops = {
> > .deinit_clk_resources = exynos5440_pcie_deinit_clk_resources,
> > };
> >
> > +static int exynos5433_pcie_get_mem_resources(struct platform_device
> *pdev,
> > + struct exynos_pcie *ep)
> > +{
> > + struct dw_pcie *pci = ep->pci;
> > + struct device *dev = pci->dev;
> > + struct resource *res;
> > +
> > + ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
> > + if (!ep->mem_res)
> > + return -ENOMEM;
> > +
> > + /* External Local Bus interface(ELBI) Register */
> > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
> > + ep->mem_res->elbi_base = devm_ioremap_resource(&pdev->dev, res);
> > + if (IS_ERR(ep->mem_res->elbi_base))
> > + return PTR_ERR(ep->mem_res->elbi_base);
> > +
> > + /* Data Bus Interface(DBI) Register */
> > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> > + pci->dbi_base = devm_ioremap_resource(&pdev->dev, res);
> > + if (IS_ERR(pci->dbi_base))
> > + return PTR_ERR(pci->dbi_base);
> > +
> > + return 0;
> > +}
> > +
> > +static int exynos5433_pcie_get_clk_resources(struct exynos_pcie *ep)
> > +{
> > + struct dw_pcie *pci = ep->pci;
> > + struct device *dev = pci->dev;
> > +
> > + ep->clk_res = devm_kzalloc(dev, sizeof(*ep->clk_res), GFP_KERNEL);
> > + if (!ep->clk_res)
> > + return -ENOMEM;
> > +
> > + ep->clk_res->clk = devm_clk_get(dev, "pcie");
> > + if (IS_ERR(ep->clk_res->clk)) {
> > + dev_err(dev, "Failed to get pcie rc clock\n");
> > + return PTR_ERR(ep->clk_res->clk);
> > + }
> > +
> > + ep->clk_res->bus_clk = devm_clk_get(dev, "pcie_bus");
> > + if (IS_ERR(ep->clk_res->bus_clk)) {
> > + dev_err(dev, "Failed to get pcie bus clock\n");
> > + return PTR_ERR(ep->clk_res->bus_clk);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void exynos5433_pcie_deinit_clk_resources(struct exynos_pcie
*ep)
> > +{
> > + clk_disable_unprepare(ep->clk_res->bus_clk);
> > + clk_disable_unprepare(ep->clk_res->clk);
> > +}
> > +
> > +
> > +static int exynos5433_pcie_init_clk_resources(struct exynos_pcie *ep)
> > +{
> > + struct dw_pcie *pci = ep->pci;
> > + struct device *dev = pci->dev;
> > + int ret;
> > +
> > + ret = clk_prepare_enable(ep->clk_res->clk);
> > + if (ret) {
> > + dev_err(dev, "cannot enable pcie rc clock");
> > + return ret;
> > + }
> > +
> > + ret = clk_prepare_enable(ep->clk_res->bus_clk);
> > + if (ret) {
> > + dev_err(dev, "cannot enable pcie bus clock");
> > + goto err_bus_clk;
> > + }
> > +
> > + return 0;
> > +
> > +err_bus_clk:
> > + clk_disable_unprepare(ep->clk_res->clk);
> > +
> > + return ret;
> > +}
> > +
> > +static const struct exynos_pcie_ops exynos5433_pcie_ops = {
> > + .get_mem_resources = exynos5433_pcie_get_mem_resources,
> > + .get_clk_resources = exynos5433_pcie_get_clk_resources,
> > + .init_clk_resources = exynos5433_pcie_init_clk_resources,
> > + .deinit_clk_resources = exynos5433_pcie_deinit_clk_resources,
> > +};
> > +
> > static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
> > {
> > writel(val, base + reg);
> > @@ -279,7 +376,9 @@ static void exynos_pcie_deassert_core_reset(struct
> > exynos_pcie *ep)
> > exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET);
> > exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET);
> > exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET);
> > - exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_MAC_RESET);
> > + if (ep->mem_res->block_base)
> > + exynos_pcie_writel(ep->mem_res->block_base, 1,
> > + PCIE_PHY_MAC_RESET);
>
> Good.
>
> > }
> >
> > static void exynos_pcie_assert_phy_reset(struct exynos_pcie *ep)
> > @@ -413,9 +512,6 @@ static int exynos_pcie_establish_link(struct
> > exynos_pcie *ep)
> > if (ep->using_phy) {
> > phy_reset(ep->phy);
> >
> > - exynos_pcie_writel(ep->mem_res->elbi_base, 1,
> > - PCIE_PWR_RESET);
> > -
> > phy_power_on(ep->phy);
> > phy_init(ep->phy);
> > } else {
> > @@ -430,14 +526,16 @@ static int exynos_pcie_establish_link(struct
> > exynos_pcie *ep)
> > udelay(500);
> > exynos_pcie_writel(ep->mem_res->block_base, 0,
> > PCIE_PHY_COMMON_RESET);
> > + exynos_pcie_deassert_core_reset(ep);
> > }
> >
> > - /* pulse for common reset */
> > - exynos_pcie_writel(ep->mem_res->block_base, 1,
> > PCIE_PHY_COMMON_RESET);
> > - udelay(500);
> > - exynos_pcie_writel(ep->mem_res->block_base, 0,
> > PCIE_PHY_COMMON_RESET);
>
> These codes are also necessary for Exyno5440.
> How about moving these codes instead of removing them?
>
> @@ -430,14 +526,16 @@ static int exynos_pcie_establish_link(struct
> exynos_pcie *ep)
> udelay(500);
> exynos_pcie_writel(ep->mem_res->block_base, 0,
> PCIE_PHY_COMMON_RESET);
> + /* pulse for common reset */
> + exynos_pcie_writel(ep->mem_res->block_base, 1,
> + PCIE_PHY_COMMON_RESET);
> + udelay(500);
> + exynos_pcie_writel(ep->mem_res->block_base, 0,
> + PCIE_PHY_COMMON_RESET);
> + exynos_pcie_deassert_core_reset(ep);
> }
I checked that this code is duplicated.
So, you can remove this one.
Sorry for making you confused.
Best regards,
Jingoo Han
>
>
> > + /*
> > + * Enable DBI_RO_WR_EN bit.
> > + * - When set to 1, some RO and HWinit bits are wriatble from
> > + * the local application through the DBI.
> > + */
> > + dw_pcie_writel_dbi(pci, PCIE_MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
> >
> > - exynos_pcie_deassert_core_reset(ep);
> > dw_pcie_setup_rc(pp);
> > exynos_pcie_assert_reset(ep);
> >
> > @@ -472,16 +570,6 @@ static void exynos_pcie_clear_irq_pulse(struct
> > exynos_pcie *ep)
> > exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_PULSE);
> > }
> >
> > -static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
> > -{
> > - u32 val;
> > -
> > - /* enable INTX interrupt */
> > - val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
> > - IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
> > - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE);
> > -}
> > -
> > static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
> > {
> > struct exynos_pcie *ep = arg;
> > @@ -513,9 +601,16 @@ static void exynos_pcie_msi_init(struct exynos_pcie
> > *ep)
> > exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_LEVEL);
> > }
> >
> > -static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
> > +static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
> > {
> > - exynos_pcie_enable_irq_pulse(ep);
> > + u32 val;
> > +
> > + val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
> > + IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
> > + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE);
> > +
> > + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_IRQ_EN_LEVEL);
> > + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_IRQ_EN_SPECIAL);
>
> Good.
>
> >
> > if (IS_ENABLED(CONFIG_PCI_MSI))
> > exynos_pcie_msi_init(ep);
> > @@ -575,10 +670,8 @@ static int exynos_pcie_link_up(struct dw_pcie *pci)
> > u32 val;
> >
> > val = exynos_pcie_readl(ep->mem_res->elbi_base,
> > PCIE_ELBI_RDLH_LINKUP);
> > - if (val == PCIE_ELBI_LTSSM_ENABLE)
> > - return 1;
>
> Exynos5440 uses 'PCIE_ELBI_LTSSM_ENABLE'.
> Can you keep this code for Exyno5440?
>
> This register can be added as below.
>
> /* Exynos5440 PCIe ELBI registers */
> #define EXYNOS5440_PCIE_ELBI_RDLH_LINKUP 0x064
> #define EXYNOS5440_PCIE_ELBI_LTSSM_ENABLE BIT(0)
>
> Best regards,
> Jingoo Han
>
> >
> > - return 0;
> > + return (val & PCIE_ELBI_XMLH_LINKUP);
> > }
> >
> > static int exynos_pcie_host_init(struct pcie_port *pp)
> > @@ -587,7 +680,7 @@ static int exynos_pcie_host_init(struct pcie_port
> *pp)
> > struct exynos_pcie *ep = to_exynos_pcie(pci);
> >
> > exynos_pcie_establish_link(ep);
> > - exynos_pcie_enable_interrupts(ep);
> > + exynos_pcie_enable_irq_pulse(ep);
> >
> > return 0;
> > }
> > @@ -608,8 +701,11 @@ static int __init exynos_add_pcie_port(struct
> > exynos_pcie *ep,
> >
> > pp->irq = platform_get_irq(pdev, 1);
> > if (pp->irq < 0) {
> > - dev_err(dev, "failed to get irq\n");
> > - return pp->irq;
> > + pp->irq = platform_get_irq_byname(pdev, "intr");
> > + if (pp->irq < 0) {
> > + dev_err(dev, "failed to get irq\n");
> > + return pp->irq;
> > + }
> > }
> > ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler,
> > IRQF_SHARED, "exynos-pcie", ep);
> > @@ -678,13 +774,23 @@ static int __init exynos_pcie_probe(struct
> > platform_device *pdev)
> >
> > ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
> >
> > - /* Assume that controller doesn't use the PHY framework */
> > - ep->using_phy = false;
> > + /*
> > + * In case of Exynos5440,
> > + * Assume that controller doesn't use the PHY frameork.
> > + * Other SoCs might be used the PHY framework.
> > + */
> > +
> > + if (of_device_is_compatible(np, "samsung,exynos5440-pcie"))
> > + ep->using_phy = false;
> >
> > - ep->phy = devm_of_phy_get(dev, np, NULL);
> > + ep->phy = devm_of_phy_get(dev, np, "pcie-phy");
> > if (IS_ERR(ep->phy)) {
> > if (PTR_ERR(ep->phy) == -EPROBE_DEFER)
> > return PTR_ERR(ep->phy);
> > + if (!of_device_is_compatible(np, "samsung,exynos5440-pcie"))
> > {
> > + dev_err(dev, "Can't find the pcie-phy\n");
> > + return PTR_ERR(ep->phy);
> > + }
> > dev_warn(dev, "Use the 'phy' property. Current DT of pci-
> > exynos was deprecated!!\n");
> > } else
> > ep->using_phy = true;
> > @@ -734,23 +840,20 @@ static int __exit exynos_pcie_remove(struct
> > platform_device *pdev)
> > static const struct of_device_id exynos_pcie_of_match[] = {
> > {
> > .compatible = "samsung,exynos5440-pcie",
> > - .data = &exynos5440_pcie_ops
> > + .data = &exynos5440_pcie_ops,
> > + }, {
> > + .compatible = "samsung,exynos5433-pcie",
> > + .data = &exynos5433_pcie_ops,
> > },
> > {},
> > };
> >
> > static struct platform_driver exynos_pcie_driver = {
> > + .probe = exynos_pcie_probe,
> > .remove = __exit_p(exynos_pcie_remove),
> > .driver = {
> > .name = "exynos-pcie",
> > .of_match_table = exynos_pcie_of_match,
> > },
> > };
> > -
> > -/* Exynos PCIe driver does not allow module unload */
> > -
> > -static int __init exynos_pcie_init(void)
> > -{
> > - return platform_driver_probe(&exynos_pcie_driver,
> > exynos_pcie_probe);
> > -}
> > -subsys_initcall(exynos_pcie_init);
> > +builtin_platform_driver(exynos_pcie_driver);
> > --
> > 2.15.1
>
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* Re: [PATCH v2 1/5] dt-bindings: at24: consistently document the compatible property
From: Peter Rosin @ 2017-12-21 16:20 UTC (permalink / raw)
To: Bartosz Golaszewski, Andy Shevchenko, Rob Herring, Mark Rutland,
Javier Martinez Canillas, David Lechner, Divagar Mohandass
Cc: linux-i2c, devicetree, linux-kernel
In-Reply-To: <20171221134842.31287-2-brgl@bgdev.pl>
On 2017-12-21 14:48, Bartosz Golaszewski wrote:
> Current description of the compatible property for at24 is quite vague.
>
> Specify an exact list of accepted compatibles and document the - now
> deprecated - strings which were previously used in device tree files.
Why is it suddenly deprecated to correctly specify what hardware you
have, e.g. "nxp,24c32". In this case the manufacturer is nxp, damnit.
Sure, it happens to be compatible with "atmel,24c32", but that is
supposed to be written with a fallback as
"nxp,24c32", "atmel,24c32"
if I understand correctly. So, why is that deprecated in this case?
What if (a few years down the line) it is discovered that some weird
quirk is needed that is only appropriate for nxp chips?
nxp is of course just an example, pick any manufacturer of eeproms
(supposedly) compatible with the atmel interface.
Cheers,
Peter
^ permalink raw reply
* Re: [RFC 2/2] pci: dwc: pci-exynos: add the codes to support the exynos5433
From: Jingoo Han @ 2017-12-21 16:12 UTC (permalink / raw)
To: 'Jaehoon Chung', linux-pci
Cc: linux-samsung-soc, devicetree, linux-kernel, robh+dt, krzk, kgene,
lorenzo.pieralisi
In-Reply-To: <20171221121408.22636-2-jh80.chung@samsung.com>
On Thursday, December 21, 2017 7:14 AM, Jaehoon Chung wrote:
>
> Exynos5433 has the PCIe for WiFi.
> Added the codes relevant to PCIe for supporting the exynos5433.
> Also changed the binding documentation name to
> 'samsung,exynos-pcie.txt'.
> (It's not only exynos5440 anymore.)
>
I have no objection.
However, I added some comments about Exynos5440.
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> ---
> ...exynos5440-pcie.txt => samsung,exynos-pcie.txt} | 2 +-
> drivers/pci/dwc/pci-exynos.c | 183
++++++++++++++++-----
> 2 files changed, 144 insertions(+), 41 deletions(-)
> rename Documentation/devicetree/bindings/pci/{samsung,exynos5440-pcie.txt
> => samsung,exynos-pcie.txt} (97%)
>
> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.txt
> similarity index 97%
> rename from Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt
> rename to Documentation/devicetree/bindings/pci/samsung,exynos-pcie.txt
> index 34a11bfbfb60..958dcc150505 100644
> --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.txt
> @@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsys
> DesignWare PCIe IP
> and thus inherits all the common properties defined in designware-
> pcie.txt.
>
> Required properties:
> -- compatible: "samsung,exynos5440-pcie"
> +- compatible: "samsung,exynos5440-pcie" or "samsung,exynos5433-pcie"
> - reg: base addresses and lengths of the PCIe controller,
> the PHY controller, additional register for the PHY controller.
> (Registers for the PHY controller are DEPRECATED.
> diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
> index 5596fdedbb94..8dee2e90347e 100644
> --- a/drivers/pci/dwc/pci-exynos.c
> +++ b/drivers/pci/dwc/pci-exynos.c
> @@ -40,6 +40,8 @@
> #define PCIE_IRQ_SPECIAL 0x008
> #define PCIE_IRQ_EN_PULSE 0x00c
> #define PCIE_IRQ_EN_LEVEL 0x010
> +#define PCIE_SW_WAKE 0x018
> +#define PCIE_BUS_EN BIT(1)
> #define IRQ_MSI_ENABLE BIT(2)
> #define PCIE_IRQ_EN_SPECIAL 0x014
> #define PCIE_PWR_RESET 0x018
> @@ -49,7 +51,8 @@
> #define PCIE_NONSTICKY_RESET 0x024
> #define PCIE_APP_INIT_RESET 0x028
> #define PCIE_APP_LTSSM_ENABLE 0x02c
> -#define PCIE_ELBI_RDLH_LINKUP 0x064
> +#define PCIE_ELBI_RDLH_LINKUP 0x074
The address of this register should be 0x064 for exynos5440.
Howe about the following?
+#define EXYNOS5440_PCIE_ELBI_RDLH_LINKUP 0x064
+#define PCIE_ELBI_RDLH_LINKUP 0x074
Or you can add the following.
/* Exynos5440 PCIe ELBI registers */
#define EXYNOS5440_PCIE_ELBI_RDLH_LINKUP 0x064
> +#define PCIE_ELBI_XMLH_LINKUP BIT(4)
> #define PCIE_ELBI_LTSSM_ENABLE 0x1
> #define PCIE_ELBI_SLV_AWMISC 0x11c
> #define PCIE_ELBI_SLV_ARMISC 0x120
> @@ -94,6 +97,10 @@
> #define PCIE_PHY_TRSV3_PD_TSV BIT(7)
> #define PCIE_PHY_TRSV3_LVCC 0x31c
>
> +/* DBI register */
> +#define PCIE_MISC_CONTROL_1_OFF 0x8BC
> +#define DBI_RO_WR_EN BIT(0)
> +
> struct exynos_pcie_mem_res {
> void __iomem *elbi_base; /* DT 0th resource: PCIe CTRL */
> void __iomem *phy_base; /* DT 1st resource: PHY CTRL */
> @@ -221,6 +228,96 @@ static const struct exynos_pcie_ops
> exynos5440_pcie_ops = {
> .deinit_clk_resources = exynos5440_pcie_deinit_clk_resources,
> };
>
> +static int exynos5433_pcie_get_mem_resources(struct platform_device
*pdev,
> + struct exynos_pcie *ep)
> +{
> + struct dw_pcie *pci = ep->pci;
> + struct device *dev = pci->dev;
> + struct resource *res;
> +
> + ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
> + if (!ep->mem_res)
> + return -ENOMEM;
> +
> + /* External Local Bus interface(ELBI) Register */
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
> + ep->mem_res->elbi_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(ep->mem_res->elbi_base))
> + return PTR_ERR(ep->mem_res->elbi_base);
> +
> + /* Data Bus Interface(DBI) Register */
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> + pci->dbi_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(pci->dbi_base))
> + return PTR_ERR(pci->dbi_base);
> +
> + return 0;
> +}
> +
> +static int exynos5433_pcie_get_clk_resources(struct exynos_pcie *ep)
> +{
> + struct dw_pcie *pci = ep->pci;
> + struct device *dev = pci->dev;
> +
> + ep->clk_res = devm_kzalloc(dev, sizeof(*ep->clk_res), GFP_KERNEL);
> + if (!ep->clk_res)
> + return -ENOMEM;
> +
> + ep->clk_res->clk = devm_clk_get(dev, "pcie");
> + if (IS_ERR(ep->clk_res->clk)) {
> + dev_err(dev, "Failed to get pcie rc clock\n");
> + return PTR_ERR(ep->clk_res->clk);
> + }
> +
> + ep->clk_res->bus_clk = devm_clk_get(dev, "pcie_bus");
> + if (IS_ERR(ep->clk_res->bus_clk)) {
> + dev_err(dev, "Failed to get pcie bus clock\n");
> + return PTR_ERR(ep->clk_res->bus_clk);
> + }
> +
> + return 0;
> +}
> +
> +static void exynos5433_pcie_deinit_clk_resources(struct exynos_pcie *ep)
> +{
> + clk_disable_unprepare(ep->clk_res->bus_clk);
> + clk_disable_unprepare(ep->clk_res->clk);
> +}
> +
> +
> +static int exynos5433_pcie_init_clk_resources(struct exynos_pcie *ep)
> +{
> + struct dw_pcie *pci = ep->pci;
> + struct device *dev = pci->dev;
> + int ret;
> +
> + ret = clk_prepare_enable(ep->clk_res->clk);
> + if (ret) {
> + dev_err(dev, "cannot enable pcie rc clock");
> + return ret;
> + }
> +
> + ret = clk_prepare_enable(ep->clk_res->bus_clk);
> + if (ret) {
> + dev_err(dev, "cannot enable pcie bus clock");
> + goto err_bus_clk;
> + }
> +
> + return 0;
> +
> +err_bus_clk:
> + clk_disable_unprepare(ep->clk_res->clk);
> +
> + return ret;
> +}
> +
> +static const struct exynos_pcie_ops exynos5433_pcie_ops = {
> + .get_mem_resources = exynos5433_pcie_get_mem_resources,
> + .get_clk_resources = exynos5433_pcie_get_clk_resources,
> + .init_clk_resources = exynos5433_pcie_init_clk_resources,
> + .deinit_clk_resources = exynos5433_pcie_deinit_clk_resources,
> +};
> +
> static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
> {
> writel(val, base + reg);
> @@ -279,7 +376,9 @@ static void exynos_pcie_deassert_core_reset(struct
> exynos_pcie *ep)
> exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET);
> exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET);
> exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET);
> - exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_MAC_RESET);
> + if (ep->mem_res->block_base)
> + exynos_pcie_writel(ep->mem_res->block_base, 1,
> + PCIE_PHY_MAC_RESET);
Good.
> }
>
> static void exynos_pcie_assert_phy_reset(struct exynos_pcie *ep)
> @@ -413,9 +512,6 @@ static int exynos_pcie_establish_link(struct
> exynos_pcie *ep)
> if (ep->using_phy) {
> phy_reset(ep->phy);
>
> - exynos_pcie_writel(ep->mem_res->elbi_base, 1,
> - PCIE_PWR_RESET);
> -
> phy_power_on(ep->phy);
> phy_init(ep->phy);
> } else {
> @@ -430,14 +526,16 @@ static int exynos_pcie_establish_link(struct
> exynos_pcie *ep)
> udelay(500);
> exynos_pcie_writel(ep->mem_res->block_base, 0,
> PCIE_PHY_COMMON_RESET);
> + exynos_pcie_deassert_core_reset(ep);
> }
>
> - /* pulse for common reset */
> - exynos_pcie_writel(ep->mem_res->block_base, 1,
> PCIE_PHY_COMMON_RESET);
> - udelay(500);
> - exynos_pcie_writel(ep->mem_res->block_base, 0,
> PCIE_PHY_COMMON_RESET);
These codes are also necessary for Exyno5440.
How about moving these codes instead of removing them?
@@ -430,14 +526,16 @@ static int exynos_pcie_establish_link(struct
exynos_pcie *ep)
udelay(500);
exynos_pcie_writel(ep->mem_res->block_base, 0,
PCIE_PHY_COMMON_RESET);
+ /* pulse for common reset */
+ exynos_pcie_writel(ep->mem_res->block_base, 1,
+ PCIE_PHY_COMMON_RESET);
+ udelay(500);
+ exynos_pcie_writel(ep->mem_res->block_base, 0,
+ PCIE_PHY_COMMON_RESET);
+ exynos_pcie_deassert_core_reset(ep);
}
> + /*
> + * Enable DBI_RO_WR_EN bit.
> + * - When set to 1, some RO and HWinit bits are wriatble from
> + * the local application through the DBI.
> + */
> + dw_pcie_writel_dbi(pci, PCIE_MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
>
> - exynos_pcie_deassert_core_reset(ep);
> dw_pcie_setup_rc(pp);
> exynos_pcie_assert_reset(ep);
>
> @@ -472,16 +570,6 @@ static void exynos_pcie_clear_irq_pulse(struct
> exynos_pcie *ep)
> exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_PULSE);
> }
>
> -static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
> -{
> - u32 val;
> -
> - /* enable INTX interrupt */
> - val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
> - IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
> - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE);
> -}
> -
> static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
> {
> struct exynos_pcie *ep = arg;
> @@ -513,9 +601,16 @@ static void exynos_pcie_msi_init(struct exynos_pcie
> *ep)
> exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_LEVEL);
> }
>
> -static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
> +static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
> {
> - exynos_pcie_enable_irq_pulse(ep);
> + u32 val;
> +
> + val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
> + IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
> + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE);
> +
> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_IRQ_EN_LEVEL);
> + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_IRQ_EN_SPECIAL);
Good.
>
> if (IS_ENABLED(CONFIG_PCI_MSI))
> exynos_pcie_msi_init(ep);
> @@ -575,10 +670,8 @@ static int exynos_pcie_link_up(struct dw_pcie *pci)
> u32 val;
>
> val = exynos_pcie_readl(ep->mem_res->elbi_base,
> PCIE_ELBI_RDLH_LINKUP);
> - if (val == PCIE_ELBI_LTSSM_ENABLE)
> - return 1;
Exynos5440 uses 'PCIE_ELBI_LTSSM_ENABLE'.
Can you keep this code for Exyno5440?
This register can be added as below.
/* Exynos5440 PCIe ELBI registers */
#define EXYNOS5440_PCIE_ELBI_RDLH_LINKUP 0x064
#define EXYNOS5440_PCIE_ELBI_LTSSM_ENABLE BIT(0)
Best regards,
Jingoo Han
>
> - return 0;
> + return (val & PCIE_ELBI_XMLH_LINKUP);
> }
>
> static int exynos_pcie_host_init(struct pcie_port *pp)
> @@ -587,7 +680,7 @@ static int exynos_pcie_host_init(struct pcie_port *pp)
> struct exynos_pcie *ep = to_exynos_pcie(pci);
>
> exynos_pcie_establish_link(ep);
> - exynos_pcie_enable_interrupts(ep);
> + exynos_pcie_enable_irq_pulse(ep);
>
> return 0;
> }
> @@ -608,8 +701,11 @@ static int __init exynos_add_pcie_port(struct
> exynos_pcie *ep,
>
> pp->irq = platform_get_irq(pdev, 1);
> if (pp->irq < 0) {
> - dev_err(dev, "failed to get irq\n");
> - return pp->irq;
> + pp->irq = platform_get_irq_byname(pdev, "intr");
> + if (pp->irq < 0) {
> + dev_err(dev, "failed to get irq\n");
> + return pp->irq;
> + }
> }
> ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler,
> IRQF_SHARED, "exynos-pcie", ep);
> @@ -678,13 +774,23 @@ static int __init exynos_pcie_probe(struct
> platform_device *pdev)
>
> ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>
> - /* Assume that controller doesn't use the PHY framework */
> - ep->using_phy = false;
> + /*
> + * In case of Exynos5440,
> + * Assume that controller doesn't use the PHY frameork.
> + * Other SoCs might be used the PHY framework.
> + */
> +
> + if (of_device_is_compatible(np, "samsung,exynos5440-pcie"))
> + ep->using_phy = false;
>
> - ep->phy = devm_of_phy_get(dev, np, NULL);
> + ep->phy = devm_of_phy_get(dev, np, "pcie-phy");
> if (IS_ERR(ep->phy)) {
> if (PTR_ERR(ep->phy) == -EPROBE_DEFER)
> return PTR_ERR(ep->phy);
> + if (!of_device_is_compatible(np, "samsung,exynos5440-pcie"))
> {
> + dev_err(dev, "Can't find the pcie-phy\n");
> + return PTR_ERR(ep->phy);
> + }
> dev_warn(dev, "Use the 'phy' property. Current DT of pci-
> exynos was deprecated!!\n");
> } else
> ep->using_phy = true;
> @@ -734,23 +840,20 @@ static int __exit exynos_pcie_remove(struct
> platform_device *pdev)
> static const struct of_device_id exynos_pcie_of_match[] = {
> {
> .compatible = "samsung,exynos5440-pcie",
> - .data = &exynos5440_pcie_ops
> + .data = &exynos5440_pcie_ops,
> + }, {
> + .compatible = "samsung,exynos5433-pcie",
> + .data = &exynos5433_pcie_ops,
> },
> {},
> };
>
> static struct platform_driver exynos_pcie_driver = {
> + .probe = exynos_pcie_probe,
> .remove = __exit_p(exynos_pcie_remove),
> .driver = {
> .name = "exynos-pcie",
> .of_match_table = exynos_pcie_of_match,
> },
> };
> -
> -/* Exynos PCIe driver does not allow module unload */
> -
> -static int __init exynos_pcie_init(void)
> -{
> - return platform_driver_probe(&exynos_pcie_driver,
> exynos_pcie_probe);
> -}
> -subsys_initcall(exynos_pcie_init);
> +builtin_platform_driver(exynos_pcie_driver);
> --
> 2.15.1
^ permalink raw reply
* Re: [PATCH 1/8] ARM: dts: dra7: Add vbb-supply to cpu and additional voltages
From: Tony Lindgren @ 2017-12-21 15:51 UTC (permalink / raw)
To: Dave Gerlach
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Nishanth Menon
In-Reply-To: <82512a74-023d-5000-7c8d-e3a681503032-l0cyMroinI0@public.gmane.org>
* Dave Gerlach <d-gerlach-l0cyMroinI0@public.gmane.org> [171221 15:42]:
> On 12/21/2017 09:15 AM, Tony Lindgren wrote:
> > * Dave Gerlach <d-gerlach-l0cyMroinI0@public.gmane.org> [171219 15:27]:
> >> Add a vbb-supply phandle to the cpus node and also add an additional
> >> triplet of voltages for each OPP in the operating-points-v2 table to
> >> make use of the multi regulator support in the OPP core and provide the
> >> vbb regulator for use by the ti-opp-supply driver.
> >
> > Sounds like these depend on the ti-opp-supply being available first?
> >
>
> Yes that would be best, but the ti-opp-supply patches are already in linux-next.
OK applying into omap-for-v4.16/dt then thanks.
Regards,
Tony
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^ permalink raw reply
* Re: [PATCH 1/8] ARM: dts: dra7: Add vbb-supply to cpu and additional voltages
From: Dave Gerlach @ 2017-12-21 15:40 UTC (permalink / raw)
To: Tony Lindgren
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Nishanth Menon
In-Reply-To: <20171221151536.GR3875-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
On 12/21/2017 09:15 AM, Tony Lindgren wrote:
> * Dave Gerlach <d-gerlach-l0cyMroinI0@public.gmane.org> [171219 15:27]:
>> Add a vbb-supply phandle to the cpus node and also add an additional
>> triplet of voltages for each OPP in the operating-points-v2 table to
>> make use of the multi regulator support in the OPP core and provide the
>> vbb regulator for use by the ti-opp-supply driver.
>
> Sounds like these depend on the ti-opp-supply being available first?
>
Yes that would be best, but the ti-opp-supply patches are already in linux-next.
Regards,
Dave
> Regards,
>
> Tony
>
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