* Re: [PATCH 3/7] watchdog: JZ4740: Register a restart handler
From: Guenter Roeck @ 2017-12-28 18:40 UTC (permalink / raw)
To: Paul Cercueil, Ralf Baechle, Rob Herring, Mark Rutland,
Wim Van Sebroeck
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171228162939.3928-4-paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
On 12/28/2017 08:29 AM, Paul Cercueil wrote:
> The watchdog driver can restart the system by simply configuring the
> hardware for a timeout of 0 seconds.
>
> Signed-off-by: Paul Cercueil <paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
Reviewed-by: Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
> ---
> drivers/watchdog/jz4740_wdt.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/watchdog/jz4740_wdt.c b/drivers/watchdog/jz4740_wdt.c
> index 92d6ca8ceb49..fa7f49a3212c 100644
> --- a/drivers/watchdog/jz4740_wdt.c
> +++ b/drivers/watchdog/jz4740_wdt.c
> @@ -130,6 +130,14 @@ static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
> return 0;
> }
>
> +static int jz4740_wdt_restart(struct watchdog_device *wdt_dev,
> + unsigned long action, void *data)
> +{
> + wdt_dev->timeout = 0;
> + jz4740_wdt_start(wdt_dev);
> + return 0;
> +}
> +
> static const struct watchdog_info jz4740_wdt_info = {
> .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
> .identity = "jz4740 Watchdog",
> @@ -141,6 +149,7 @@ static const struct watchdog_ops jz4740_wdt_ops = {
> .stop = jz4740_wdt_stop,
> .ping = jz4740_wdt_ping,
> .set_timeout = jz4740_wdt_set_timeout,
> + .restart = jz4740_wdt_restart,
> };
>
> #ifdef CONFIG_OF
>
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^ permalink raw reply
* Re: [PATCH 1/3] mtd: spi-nor: add optional DMA-safe bounce buffer for data transfer
From: Trent Piepho @ 2017-12-28 18:54 UTC (permalink / raw)
To: linux-mtd@lists.infradead.org, linux@armlinux.org.uk,
broonie@kernel.org, cyrille.pitchen@wedev4u.fr,
dwmw2@infradead.org, computersforpeace@gmail.com, vigneshr@ti.com,
boris.brezillon@free-electrons.com, richard@nod.at,
marek.vasut@gmail.com
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
nicolas.ferre@microchip.com, radu.pirea@microchip.com,
robh@kernel.org, devicetree@vger.kernel.org
In-Reply-To: <1a7dc424-1ce0-6c64-fc52-bb88ec7db8fa@wedev4u.fr>
On Thu, 2017-12-28 at 11:39 +0100, Cyrille Pitchen wrote:
> Le 26/12/2017 à 20:43, Trent Piepho a écrit :
> > On Sun, 2017-12-24 at 05:36 +0100, Cyrille Pitchen wrote:
> > >
> > > Then the patch adds two hardware capabilities for SPI flash controllers,
> > > SNOR_HWCAPS_WR_BOUNCE and SNOR_HWCAPS_RD_BOUNCE.
> >
> > Are there any drivers for which a bounce buffer is NOT needed when the
> > tx/rx buffer is not in DMA safe memory? Maybe it would make more sense
> > to invert the sense of these flags, so that they indicate the driver
> > does not need DMA safe buffers, if that is the uncommon/non-existent
> > case, so that fewer drivers need to be modified to to be fixed?
> >
>
> It doesn't sound safe for a first step. I don't know if some of the
> spi-flash controllers are embedded inside systems with small memory and
> don't care about DMA transfers. Maybe they don't plan to use anything else
> but PIO transfers. Then why taking the risk to exhaust the memory on systems
> that would not use the bounce buffer anyway?
This would certainly be the case when the driver does not even support
DMA in the first place.
This also makes me wonder, how inefficient does this become when it
uses a bounce buffer for small transfer that would not use DMA anyway?
In the spi_flash_read() interface for spi masters, there is a master
method spi_flash_can_dma() callback used by the spi core to tell if
each transfer can be DMAed.
Should something like that be used here, to ask the master if it would
use dma on the buffer?
This might also prevent allocation of the bounce buffer if the only DMA
unsafe transfers are tiny control ops with stack variables that
wouldn't use DMA, e.g. the stuff spi_nor_read_sfdp_dma_unsafe() does.
> About the memory loss when forcing the SNOR_HWCAPS_*_BOUNCE in m25p80.c, I
> justify it because the m25p80 has to be compliant with the SPI sub-system
> requirements but currently is not. However I've taken care not to allocate
> the bounce buffer as long as we use only DMA-safe buffers.
Another possibility to reduce memory usage: make the buffer smaller
when first allocated by being just enough for the needed space. Grow
it (by powers of two?) until it reaches the max allowed size. No
reason to use a 256 kB buffer if DMA unsafe operations never get that
big.
> Here at the MTD side, the main (only ?) source of DMA-unsafe buffers is
> the UBIFS (JFFS2 too ?) layer. Then I've assumed that systems using such a
> file-system should already have enough system memory.
I saw a note in one of the existing DMA fixes that JFFS2 was the source
of the unsafe buffers, so probably there too.
>
> Vignesh has suggested to call virt_addr_valid() instead.
> I think Boris has also told me about this function.
> So it might be the right solution. What do you think about their proposal?
Not sure what exactly the differences are between these methods. The
fact that each of the many existing DMA fixes uses slightly different
code to detect what is unsafe speaks to the difficulty of this problem!
virt_addr_valid() is already used by spi-ti-qspi. spi core uses for
the buffer map helper, but that code path is for buffers which are NOT
vmalloc or highmem, but are still not virt_addr_valid() for some other
reason.
> > > +static int spi_nor_get_bounce_buffer(struct spi_nor *nor,
> > > + u_char **buffer,
> > > + size_t *buffer_size)
> > > +{
> > > +
> > > + *buffer = nor->bounce_buffer;
> > > + *buffer_size = size;
> >
> > So the buffer is returned via the parameter, and also via a field
> > inside nor. Seems redundant. Consider address could be returned via
> > the function return value coupled with PTR_ERR() for the error cases.
> > Or not return address at all since it's available via nor-
> > > bounce_buffer.
>
> Why not. It would require more lines though. I guess it's purely a matter of taste.
Well, also consider that you don't need to even return the buffer
pointer at all, since it's available as nor->bounce_buffer. Which it
is used as in spi_nor_write() and spi_nor_read().
> > This pattern, check if bounce is enabled, check if address is dma-
> > unsafe, get bounce buffer, seems to be very common. Could it be
> > refactored into one helper?
> >
> > u_char *buffer = spi_nor_check_bounce(nor, buf, len, &buffer_size);
>
> The conditions that define the value of 'use_bounce' also depend on the type
> of operation, read or write, hence on the two different flags
> SNOR_F_USE_RD_BOUNCE and SNOR_F_USE_WR_BOUNCE.
Just pass one of those flags as an argument to tell what direction it
is in. Though I wonder if using a bounce buffer for only one direction
will ever be used.
>
> Besides, 'use_bounce' is also tested later in spi_nor_read(), sst_write()
> and sst_write().
>
> So I don't really see how the spi_nor_check_bounce() function you propose
> could be that different from spi_nor_get_bounce_buffer().
>
> > if (IS_ERR(buffer))
> > return PTR_ERR(buffer);
> > // buffer = nor->bounce_buffer or buf, whichever is correct
> > // buffer_size = len or bounce buffer size, whichever is correct
> >
> > Could spi_nor_read_sfdp_dma_unsafe() also use this buffer?
> >
>
> I didn't use the bounce buffer in spi_nor_read_sfdp_dma_unsafe() on
> purpose: the bounce buffer, when needed, is allocated once for all to limit
> performance loss. However, to avoid increasing the memory footprint, if not
> absolutely needed the bounce buffer is not allocated at all.
spi-nor tries to provide a common implementation of DMA bounce buffers,
yet spi-nor itself has two different DMA bounce buffer
implementations.
I think the real answer for spi_nor_read_sfdp_dma_unsafe() is that it
shouldn't be written that way and the function should go away. The two
call sites should just kmalloc the struct they read into instead of
placing it on the stack. The dma_unsafe wrapper kmallocs a buffer
anyway, so it's not like there is any more allocation going on.
^ permalink raw reply
* Re: [PATCH 2/7] watchdog: jz4740: Use devm_* functions
From: Paul Cercueil @ 2017-12-28 19:59 UTC (permalink / raw)
To: Guenter Roeck
Cc: Ralf Baechle, Rob Herring, Mark Rutland, Wim Van Sebroeck,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <9778afd4-5841-0d48-cde3-c02872623a5f-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
Hi Guenter,
Le jeu. 28 déc. 2017 à 18:48, Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org> a
écrit :
> On 12/28/2017 08:29 AM, Paul Cercueil wrote:
>> - Use devm_clk_get instead of clk_get
>> - Use devm_watchdog_register_device instead of
>> watchdog_register_device
>>
>> Signed-off-by: Paul Cercueil <paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
>> ---
>> drivers/watchdog/jz4740_wdt.c | 27 ++++++++-------------------
>> 1 file changed, 8 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/watchdog/jz4740_wdt.c
>> b/drivers/watchdog/jz4740_wdt.c
>> index 6955deb100ef..92d6ca8ceb49 100644
>> --- a/drivers/watchdog/jz4740_wdt.c
>> +++ b/drivers/watchdog/jz4740_wdt.c
>> @@ -178,40 +178,29 @@ static int jz4740_wdt_probe(struct
>> platform_device *pdev)
>> \x7f res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> drvdata->base = devm_ioremap_resource(&pdev->dev, res);
>> - if (IS_ERR(drvdata->base)) {
>> - ret = PTR_ERR(drvdata->base);
>> - goto err_out;
>> - }
>> + if (IS_ERR(drvdata->base))
>> + return PTR_ERR(drvdata->base);
>> \x7f- drvdata->rtc_clk = clk_get(&pdev->dev, "rtc");
>> + drvdata->rtc_clk = devm_clk_get(&pdev->dev, "rtc");
>> if (IS_ERR(drvdata->rtc_clk)) {
>> dev_err(&pdev->dev, "cannot find RTC clock\n");
>> - ret = PTR_ERR(drvdata->rtc_clk);
>> - goto err_out;
>> + return PTR_ERR(drvdata->rtc_clk);
>> }
>> \x7f- ret = watchdog_register_device(&drvdata->wdt);
>> + ret = devm_watchdog_register_device(&pdev->dev, &drvdata->wdt);
>> if (ret < 0)
>> - goto err_disable_clk;
>> + return ret;
>> \x7f platform_set_drvdata(pdev, drvdata);
>> - return 0;
>> \x7f-err_disable_clk:
>> - clk_put(drvdata->rtc_clk);
>> -err_out:
>> - return ret;
>> + return 0;
>> }
>> \x7f static int jz4740_wdt_remove(struct platform_device *pdev)
>> {
>> struct jz4740_wdt_drvdata *drvdata = platform_get_drvdata(pdev);
>> \x7f- jz4740_wdt_stop(&drvdata->wdt);
>> - watchdog_unregister_device(&drvdata->wdt);
>> - clk_put(drvdata->rtc_clk);
>> -
>> - return 0;
>> + return jz4740_wdt_stop(&drvdata->wdt);
>
> If the watchdog is running, the module can not be unloaded. Even if
> that wasn't
> the case, this defeats both WDIOF_MAGICCLOSE and
> watchdog_set_nowayout().
> Are you sure this is what you want ? If so, please call
> watchdog_stop_on_unregister() before registration; this clarifies
> that this
> is what you want, and you can drop the remove function.
>
> Thanks,
> Guenter
This patch does not change the behaviour. We always used that driver
built-in; what
should the behaviour be when unloading the module? Keep the watchdog
hardware running
if configured for 'nowayout'?
Thanks,
-Paul
>
>> }
>> \x7f static struct platform_driver jz4740_wdt_driver = {
>>
>
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^ permalink raw reply
* [PATCH v6 0/6] TDA1997x HDMI video receiver
From: Tim Harvey @ 2017-12-28 20:09 UTC (permalink / raw)
To: linux-media, alsa-devel
Cc: devicetree, linux-kernel, shawnguo, Steve Longerbeam,
Philipp Zabel, Hans Verkuil, Mauro Carvalho Chehab
This is a v4l2 subdev driver supporting the TDA1997x HDMI video receiver.
I've tested this on a Gateworks GW54xx/GW551x with an IMX6Q/IMX6DL which
uses the TDA19971 with 16bits connected to the IMX6 CSI and single-lane
I2S audio providing 2-channel audio.
For this configuration I've tested both 16bit YUV422 and 8bit
BT656 parallel video bus modes.
While the driver should support the TDA1993 I do not have one for testing.
Further potential development efforts include:
- CEC support
- HDCP support
- mbus format selection support for bus widths that support multiple
formats
- TDA19972 support (2 inputs)
Media graphs can be found at http://dev.gateworks.com/docs/linux/media
History:
v6:
- tda1997x: fix return on regulator enablei in tda1997x_set_power() (Fabio)
- tda1997x: fix colorspace handling (Hans)
- bindings: added Robs's ack (Rob)
- replace copyright with SPDX tag (Philippe)
v5:
- added v4l2_hdmi_colorimetry() patch from Hans to series
- bindings: added Sakari's ack
- tda1997x: uppercase string constants
- tda1997x: use v4l2_hdmi_rx_coloriemtry to fill format
- tda1997x: fix V4L2_CID_DV_RX_RGB_RANGE
- tda1997x: fix interlaced mode format
- dts: remove leading 0 from unit address
- dts: add newline between property list and child node
- dts: added missing audmux in GW551x dts
v4:
- move include/dt-bindings/media/tda1997x.h to bindings patch
- clarify port node details in bindings
- fix typos
- fix default quant range for VGA
- fix quant range handling and conv matrix
- add additional standards and capabilities to timings_cap
v3:
- fix typo in dt bindings
- added dt bindings for GW551x
- use V4L2_DV_BT_FRAME_WIDTH/HEIGHT macros
- fixed missing break
- use only hdmi_infoframe_log for infoframe logging
- simplify tda1997x_s_stream error handling
- add delayed work proc to handle hotplug enable/disable
- fix set_edid (disable HPD before writing, enable after)
- remove enabling edid by default
- initialize timings
- take quant range into account in colorspace conversion
- remove vendor/product tracking (we provide this in log_status via
infoframes)
- add v4l_controls
- add more detail to log_status
- calculate vhref generator timings
- timing detection fixes (rounding errors, hswidth errors)
- rename configure_input/configure_conv functions
v2:
- encorporate feedback into dt bindings
- change audio dt bindings
- implement dv timings enum/cap
- remove deprecated g_mbus_config op
- fix dv_query_timings
- add EDID get/set handling
- remove max-pixel-rate support
- add audio codec DAI support
- added media-ctl and v4l2-compliance details
v1:
- initial RFC
Media device topology:
# media-ctl -d /dev/media0 -p
Media controller API version 4.13.0
Media device information
------------------------
driver imx-media
model imx-media
serial
bus info
hw revision 0x0
driver version 4.13.0
Device topology
- entity 1: adv7180 2-0020 (1 pad, 1 link)
type V4L2 subdev subtype Unknown flags 20004
device node name /dev/v4l-subdev0
pad0: Source
[fmt:UYVY8_2X8/720x480 field:interlaced colorspace:smpte170m]
-> "ipu2_csi1_mux":1 []
- entity 3: tda19971 2-0048 (1 pad, 1 link)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev1
pad0: Source
[fmt:UYVY8_1X16/640x480 field:none colorspace:srgb]
[dv.caps:BT.656/1120 min:640x480@13000000 max:1920x1080@165000000 stds:CEA-861,DMT caps:progressive]
[dv.detect:BT.656/1120 640x480p59 (800x525) stds:CEA-861,DMT flags:has-cea861-vic]
[dv.current:BT.656/1120 1920x1080p60 (2200x1125) stds:CEA-861,DMT flags:can-reduce-fps,CE-video,has-cea861-vic]
-> "ipu1_csi0_mux":1 []
- entity 5: ipu1_vdic (3 pads, 3 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev2
pad0: Sink
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
<- "ipu1_csi0":1 []
<- "ipu1_csi1":1 []
pad1: Sink
[fmt:UYVY8_2X8/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
pad2: Source
[fmt:AYUV8_1X32/640x480@1/60 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu1_ic_prp":0 []
- entity 9: ipu2_vdic (3 pads, 3 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev3
pad0: Sink
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
<- "ipu2_csi0":1 []
<- "ipu2_csi1":1 []
pad1: Sink
[fmt:UYVY8_2X8/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
pad2: Source
[fmt:AYUV8_1X32/640x480@1/60 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu2_ic_prp":0 []
- entity 13: ipu1_ic_prp (3 pads, 5 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev4
pad0: Sink
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
<- "ipu1_vdic":2 []
<- "ipu1_csi0":1 []
<- "ipu1_csi1":1 []
pad1: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu1_ic_prpenc":0 []
pad2: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu1_ic_prpvf":0 []
- entity 17: ipu1_ic_prpenc (2 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev5
pad0: Sink
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
<- "ipu1_ic_prp":1 []
pad1: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu1_ic_prpenc capture":0 []
- entity 20: ipu1_ic_prpenc capture (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video0
pad0: Sink
<- "ipu1_ic_prpenc":1 []
- entity 26: ipu1_ic_prpvf (2 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev6
pad0: Sink
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
<- "ipu1_ic_prp":2 []
pad1: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu1_ic_prpvf capture":0 []
- entity 29: ipu1_ic_prpvf capture (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video1
pad0: Sink
<- "ipu1_ic_prpvf":1 []
- entity 35: ipu2_ic_prp (3 pads, 5 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev7
pad0: Sink
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
<- "ipu2_vdic":2 []
<- "ipu2_csi0":1 []
<- "ipu2_csi1":1 []
pad1: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu2_ic_prpenc":0 []
pad2: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu2_ic_prpvf":0 []
- entity 39: ipu2_ic_prpenc (2 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev8
pad0: Sink
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
<- "ipu2_ic_prp":1 []
pad1: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu2_ic_prpenc capture":0 []
- entity 42: ipu2_ic_prpenc capture (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video2
pad0: Sink
<- "ipu2_ic_prpenc":1 []
- entity 48: ipu2_ic_prpvf (2 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev9
pad0: Sink
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
<- "ipu2_ic_prp":2 []
pad1: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu2_ic_prpvf capture":0 []
- entity 51: ipu2_ic_prpvf capture (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video3
pad0: Sink
<- "ipu2_ic_prpvf":1 []
- entity 57: ipu1_csi0 (3 pads, 4 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev10
pad0: Sink
[fmt:UYVY8_2X8/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range
crop.bounds:(0,0)/640x480
crop:(0,0)/640x480
compose.bounds:(0,0)/640x480
compose:(0,0)/640x480]
<- "ipu1_csi0_mux":2 []
pad1: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu1_ic_prp":0 []
-> "ipu1_vdic":0 []
pad2: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu1_csi0 capture":0 []
- entity 61: ipu1_csi0 capture (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video4
pad0: Sink
<- "ipu1_csi0":2 []
- entity 67: ipu1_csi1 (3 pads, 3 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev11
pad0: Sink
[fmt:UYVY8_2X8/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range
crop.bounds:(0,0)/640x480
crop:(0,0)/640x480
compose.bounds:(0,0)/640x480
compose:(0,0)/640x480]
pad1: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu1_ic_prp":0 []
-> "ipu1_vdic":0 []
pad2: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu1_csi1 capture":0 []
- entity 71: ipu1_csi1 capture (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video5
pad0: Sink
<- "ipu1_csi1":2 []
- entity 77: ipu2_csi0 (3 pads, 3 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev12
pad0: Sink
[fmt:UYVY8_2X8/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range
crop.bounds:(0,0)/640x480
crop:(0,0)/640x480
compose.bounds:(0,0)/640x480
compose:(0,0)/640x480]
pad1: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu2_ic_prp":0 []
-> "ipu2_vdic":0 []
pad2: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu2_csi0 capture":0 []
- entity 81: ipu2_csi0 capture (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video6
pad0: Sink
<- "ipu2_csi0":2 []
- entity 87: ipu2_csi1 (3 pads, 4 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev13
pad0: Sink
[fmt:UYVY8_2X8/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range
crop.bounds:(0,0)/640x480
crop:(0,0)/640x480
compose.bounds:(0,0)/640x480
compose:(0,0)/640x480]
<- "ipu2_csi1_mux":2 []
pad1: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu2_ic_prp":0 []
-> "ipu2_vdic":0 []
pad2: Source
[fmt:AYUV8_1X32/640x480@1/30 field:none colorspace:smpte170m xfer:709 ycbcr:601 quantization:lim-range]
-> "ipu2_csi1 capture":0 []
- entity 91: ipu2_csi1 capture (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video7
pad0: Sink
<- "ipu2_csi1":2 []
- entity 97: ipu1_csi0_mux (3 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev14
pad0: Sink
[fmt:unknown/0x0]
pad1: Sink
[fmt:unknown/0x0]
<- "tda19971 2-0048":0 []
pad2: Source
[fmt:unknown/0x0]
-> "ipu1_csi0":0 []
- entity 101: ipu2_csi1_mux (3 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev15
pad0: Sink
[fmt:unknown/0x0]
pad1: Sink
[fmt:unknown/0x0]
<- "adv7180 2-0020":0 []
pad2: Source
[fmt:unknown/0x0]
-> "ipu2_csi1":0 []
v4l2-compliance test results:
(on /dev/video6 as v4l2-compliance doesn't yet support subdevs)
Driver Info:
Driver name : imx-media-captu
Card type : imx-media-capture
Bus info : platform:ipu2_csi0
Driver version: 4.13.0
Capabilities : 0x84200001
Video Capture
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04200001
Video Capture
Streaming
Extended Pix Format
Compliance test for device /dev/video6 (not using libv4l2):
Required ioctls:
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second video open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
fail: v4l2-test-input-output.cpp(418): G_INPUT not supported for a capture device
test VIDIOC_G/S/ENUMINPUT: FAIL
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
fail: v4l2-test-controls.cpp(574): g_ext_ctrls does not support count == 0
test VIDIOC_G/S/TRY_EXT_CTRLS: FAIL
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK (Not Supported)
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 0 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
Test input 0:
Total: 42, Succeeded: 40, Failed: 2, Warnings: 0
Hans Verkuil (1):
v4l2-dv-timings: add v4l2_hdmi_colorimetry()
Tim Harvey (5):
MAINTAINERS: add entry for NXP TDA1997x driver
media: dt-bindings: Add bindings for TDA1997X
media: i2c: Add TDA1997x HDMI receiver driver
ARM: dts: imx: Add TDA19971 HDMI Receiver to GW54xx
ARM: dts: imx: Add TDA19971 HDMI Receiver to GW551x
.../devicetree/bindings/media/i2c/tda1997x.txt | 179 +
MAINTAINERS | 8 +
arch/arm/boot/dts/imx6q-gw54xx.dts | 105 +
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 29 +-
arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 138 +
drivers/media/i2c/Kconfig | 9 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/tda1997x.c | 3476 ++++++++++++++++++++
drivers/media/v4l2-core/v4l2-dv-timings.c | 141 +
include/dt-bindings/media/tda1997x.h | 74 +
include/media/i2c/tda1997x.h | 41 +
include/media/v4l2-dv-timings.h | 21 +
12 files changed, 4219 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/i2c/tda1997x.txt
create mode 100644 drivers/media/i2c/tda1997x.c
create mode 100644 include/dt-bindings/media/tda1997x.h
create mode 100644 include/media/i2c/tda1997x.h
--
2.7.4
^ permalink raw reply
* [PATCH v6 1/6] v4l2-dv-timings: add v4l2_hdmi_colorimetry()
From: Tim Harvey @ 2017-12-28 20:09 UTC (permalink / raw)
To: linux-media, alsa-devel
Cc: devicetree, linux-kernel, Hans Verkuil, Mauro Carvalho Chehab,
Hans Verkuil, Philipp Zabel, Steve Longerbeam, Hans Verkuil,
shawnguo
In-Reply-To: <1514491789-8697-1-git-send-email-tharvey@gateworks.com>
From: Hans Verkuil <hverkuil@xs4all.nl>
Add the v4l2_hdmi_colorimetry() function so we have a single function
that determines the colorspace, YCbCr encoding, quantization range and
transfer function from the InfoFrame data.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
drivers/media/v4l2-core/v4l2-dv-timings.c | 141 ++++++++++++++++++++++++++++++
include/media/v4l2-dv-timings.h | 21 +++++
2 files changed, 162 insertions(+)
diff --git a/drivers/media/v4l2-core/v4l2-dv-timings.c b/drivers/media/v4l2-core/v4l2-dv-timings.c
index 5c8c49d..4d01d52 100644
--- a/drivers/media/v4l2-core/v4l2-dv-timings.c
+++ b/drivers/media/v4l2-core/v4l2-dv-timings.c
@@ -27,6 +27,7 @@
#include <linux/v4l2-dv-timings.h>
#include <media/v4l2-dv-timings.h>
#include <linux/math64.h>
+#include <linux/hdmi.h>
MODULE_AUTHOR("Hans Verkuil");
MODULE_DESCRIPTION("V4L2 DV Timings Helper Functions");
@@ -814,3 +815,143 @@ struct v4l2_fract v4l2_calc_aspect_ratio(u8 hor_landscape, u8 vert_portrait)
return aspect;
}
EXPORT_SYMBOL_GPL(v4l2_calc_aspect_ratio);
+
+/** v4l2_hdmi_rx_colorimetry - determine HDMI colorimetry information
+ * based on various InfoFrames.
+ * @avi - the AVI InfoFrame
+ * @hdmi - the HDMI Vendor InfoFrame, may be NULL
+ * @height - the frame height
+ *
+ * Determines the HDMI colorimetry information, i.e. how the HDMI
+ * pixel color data should be interpreted.
+ *
+ * Note that some of the newer features (DCI-P3, HDR) are not yet
+ * implemented: the hdmi.h header needs to be updated to the HDMI 2.0
+ * and CTA-861-G standards.
+ */
+struct v4l2_hdmi_colorimetry
+v4l2_hdmi_rx_colorimetry(const struct hdmi_avi_infoframe *avi,
+ const struct hdmi_vendor_infoframe *hdmi,
+ unsigned int height)
+{
+ struct v4l2_hdmi_colorimetry c = {
+ V4L2_COLORSPACE_SRGB,
+ V4L2_YCBCR_ENC_DEFAULT,
+ V4L2_QUANTIZATION_FULL_RANGE,
+ V4L2_XFER_FUNC_SRGB
+ };
+ bool is_ce = avi->video_code || (hdmi && hdmi->vic);
+ bool is_sdtv = height <= 576;
+ bool default_is_lim_range_rgb = avi->video_code > 1;
+
+ switch (avi->colorspace) {
+ case HDMI_COLORSPACE_RGB:
+ /* RGB pixel encoding */
+ switch (avi->colorimetry) {
+ case HDMI_COLORIMETRY_EXTENDED:
+ switch (avi->extended_colorimetry) {
+ case HDMI_EXTENDED_COLORIMETRY_ADOBE_RGB:
+ c.colorspace = V4L2_COLORSPACE_ADOBERGB;
+ c.xfer_func = V4L2_XFER_FUNC_ADOBERGB;
+ break;
+ case HDMI_EXTENDED_COLORIMETRY_BT2020:
+ c.colorspace = V4L2_COLORSPACE_BT2020;
+ c.xfer_func = V4L2_XFER_FUNC_709;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ switch (avi->quantization_range) {
+ case HDMI_QUANTIZATION_RANGE_LIMITED:
+ c.quantization = V4L2_QUANTIZATION_LIM_RANGE;
+ break;
+ case HDMI_QUANTIZATION_RANGE_FULL:
+ break;
+ default:
+ if (default_is_lim_range_rgb)
+ c.quantization = V4L2_QUANTIZATION_LIM_RANGE;
+ break;
+ }
+ break;
+
+ default:
+ /* YCbCr pixel encoding */
+ c.quantization = V4L2_QUANTIZATION_LIM_RANGE;
+ switch (avi->colorimetry) {
+ case HDMI_COLORIMETRY_NONE:
+ if (!is_ce)
+ break;
+ if (is_sdtv) {
+ c.colorspace = V4L2_COLORSPACE_SMPTE170M;
+ c.ycbcr_enc = V4L2_YCBCR_ENC_601;
+ } else {
+ c.colorspace = V4L2_COLORSPACE_REC709;
+ c.ycbcr_enc = V4L2_YCBCR_ENC_709;
+ }
+ c.xfer_func = V4L2_XFER_FUNC_709;
+ break;
+ case HDMI_COLORIMETRY_ITU_601:
+ c.colorspace = V4L2_COLORSPACE_SMPTE170M;
+ c.ycbcr_enc = V4L2_YCBCR_ENC_601;
+ c.xfer_func = V4L2_XFER_FUNC_709;
+ break;
+ case HDMI_COLORIMETRY_ITU_709:
+ c.colorspace = V4L2_COLORSPACE_REC709;
+ c.ycbcr_enc = V4L2_YCBCR_ENC_709;
+ c.xfer_func = V4L2_XFER_FUNC_709;
+ break;
+ case HDMI_COLORIMETRY_EXTENDED:
+ switch (avi->extended_colorimetry) {
+ case HDMI_EXTENDED_COLORIMETRY_XV_YCC_601:
+ c.colorspace = V4L2_COLORSPACE_REC709;
+ c.ycbcr_enc = V4L2_YCBCR_ENC_XV709;
+ c.xfer_func = V4L2_XFER_FUNC_709;
+ break;
+ case HDMI_EXTENDED_COLORIMETRY_XV_YCC_709:
+ c.colorspace = V4L2_COLORSPACE_REC709;
+ c.ycbcr_enc = V4L2_YCBCR_ENC_XV601;
+ c.xfer_func = V4L2_XFER_FUNC_709;
+ break;
+ case HDMI_EXTENDED_COLORIMETRY_S_YCC_601:
+ c.colorspace = V4L2_COLORSPACE_SRGB;
+ c.ycbcr_enc = V4L2_YCBCR_ENC_601;
+ c.xfer_func = V4L2_XFER_FUNC_SRGB;
+ break;
+ case HDMI_EXTENDED_COLORIMETRY_ADOBE_YCC_601:
+ c.colorspace = V4L2_COLORSPACE_ADOBERGB;
+ c.ycbcr_enc = V4L2_YCBCR_ENC_601;
+ c.xfer_func = V4L2_XFER_FUNC_ADOBERGB;
+ break;
+ case HDMI_EXTENDED_COLORIMETRY_BT2020:
+ c.colorspace = V4L2_COLORSPACE_BT2020;
+ c.ycbcr_enc = V4L2_YCBCR_ENC_BT2020;
+ c.xfer_func = V4L2_XFER_FUNC_709;
+ break;
+ case HDMI_EXTENDED_COLORIMETRY_BT2020_CONST_LUM:
+ c.colorspace = V4L2_COLORSPACE_BT2020;
+ c.ycbcr_enc = V4L2_YCBCR_ENC_BT2020_CONST_LUM;
+ c.xfer_func = V4L2_XFER_FUNC_709;
+ break;
+ default: /* fall back to ITU_709 */
+ c.colorspace = V4L2_COLORSPACE_REC709;
+ c.ycbcr_enc = V4L2_YCBCR_ENC_709;
+ c.xfer_func = V4L2_XFER_FUNC_709;
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ /*
+ * YCC Quantization Range signaling is more-or-less broken,
+ * let's just ignore this.
+ */
+ break;
+ }
+ return c;
+}
+EXPORT_SYMBOL_GPL(v4l2_hdmi_rx_colorimetry);
diff --git a/include/media/v4l2-dv-timings.h b/include/media/v4l2-dv-timings.h
index 61a1889..835aef7 100644
--- a/include/media/v4l2-dv-timings.h
+++ b/include/media/v4l2-dv-timings.h
@@ -223,5 +223,26 @@ static inline bool can_reduce_fps(struct v4l2_bt_timings *bt)
return false;
}
+/**
+ * struct v4l2_hdmi_rx_colorimetry - describes the HDMI colorimetry information
+ * @colorspace: enum v4l2_colorspace, the colorspace
+ * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding
+ * @quantization: enum v4l2_quantization, colorspace quantization
+ * @xfer_func: enum v4l2_xfer_func, colorspace transfer function
+ */
+struct v4l2_hdmi_colorimetry {
+ enum v4l2_colorspace colorspace;
+ enum v4l2_ycbcr_encoding ycbcr_enc;
+ enum v4l2_quantization quantization;
+ enum v4l2_xfer_func xfer_func;
+};
+
+struct hdmi_avi_infoframe;
+struct hdmi_vendor_infoframe;
+
+struct v4l2_hdmi_colorimetry
+v4l2_hdmi_rx_colorimetry(const struct hdmi_avi_infoframe *avi,
+ const struct hdmi_vendor_infoframe *hdmi,
+ unsigned int height);
#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v6 2/6] MAINTAINERS: add entry for NXP TDA1997x driver
From: Tim Harvey @ 2017-12-28 20:09 UTC (permalink / raw)
To: linux-media, alsa-devel
Cc: devicetree, linux-kernel, shawnguo, Steve Longerbeam,
Philipp Zabel, Hans Verkuil, Mauro Carvalho Chehab
In-Reply-To: <1514491789-8697-1-git-send-email-tharvey@gateworks.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aa71ab52f..502bc97 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13244,6 +13244,14 @@ T: git git://linuxtv.org/mkrufky/tuners.git
S: Maintained
F: drivers/media/tuners/tda18271*
+TDA1997x MEDIA DRIVER
+M: Tim Harvey <tharvey@gateworks.com>
+L: linux-media@vger.kernel.org
+W: https://linuxtv.org
+Q: http://patchwork.linuxtv.org/project/linux-media/list/
+S: Maintained
+F: drivers/media/i2c/tda1997x.*
+
TDA827x MEDIA DRIVER
M: Michael Krufky <mkrufky@linuxtv.org>
L: linux-media@vger.kernel.org
--
2.7.4
^ permalink raw reply related
* [PATCH v6 3/6] media: dt-bindings: Add bindings for TDA1997X
From: Tim Harvey @ 2017-12-28 20:09 UTC (permalink / raw)
To: linux-media, alsa-devel
Cc: devicetree, linux-kernel, shawnguo, Steve Longerbeam,
Philipp Zabel, Hans Verkuil, Mauro Carvalho Chehab
In-Reply-To: <1514491789-8697-1-git-send-email-tharvey@gateworks.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Sakari Ailus <sakari.ailus@iki.fi>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
v6:
- replace copyright with SPDX tag (Philippe)
- added Rob's ack (Rob)
v5:
- added Sakari's ack
v4:
- move include/dt-bindings/media/tda1997x.h to bindings patch
- clarify port node details
v3:
- fix typo
v2:
- add vendor prefix and remove _ from vidout-portcfg
- remove _ from labels
- remove max-pixel-rate property
- describe and provide example for single output port
- update to new audio port bindings
---
.../devicetree/bindings/media/i2c/tda1997x.txt | 179 +++++++++++++++++++++
include/dt-bindings/media/tda1997x.h | 74 +++++++++
2 files changed, 253 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/tda1997x.txt
create mode 100644 include/dt-bindings/media/tda1997x.h
diff --git a/Documentation/devicetree/bindings/media/i2c/tda1997x.txt b/Documentation/devicetree/bindings/media/i2c/tda1997x.txt
new file mode 100644
index 0000000..9ab53c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/tda1997x.txt
@@ -0,0 +1,179 @@
+Device-Tree bindings for the NXP TDA1997x HDMI receiver
+
+The TDA19971/73 are HDMI video receivers.
+
+The TDA19971 Video port output pins can be used as follows:
+ - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
+ - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
+ - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
+ - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
+ - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
+ - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
+ - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
+ - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
+
+The TDA19973 Video port output pins can be used as follows:
+ - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
+ - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
+ - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]
+ - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
+
+The Video port output pins are mapped via 4-bit 'pin groups' allowing
+for a variety of connection possibilities including swapping pin order within
+pin groups. The video_portcfg device-tree property consists of register mapping
+pairs which map a chip-specific VP output register to a 4-bit pin group. If
+the pin group needs to be bit-swapped you can use the *_S pin-group defines.
+
+Required Properties:
+ - compatible :
+ - "nxp,tda19971" for the TDA19971
+ - "nxp,tda19973" for the TDA19973
+ - reg : I2C slave address
+ - interrupts : The interrupt number
+ - DOVDD-supply : Digital I/O supply
+ - DVDD-supply : Digital Core supply
+ - AVDD-supply : Analog supply
+ - nxp,vidout-portcfg : array of pairs mapping VP output pins to pin groups.
+
+Optional Properties:
+ - nxp,audout-format : DAI bus format: "i2s" or "spdif".
+ - nxp,audout-width : width of audio output data bus (1-4).
+ - nxp,audout-layout : data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used).
+ - nxp,audout-mclk-fs : Multiplication factor between stream rate and codec
+ mclk.
+
+The port node shall contain one endpoint child node for its digital
+output video port, in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Optional Endpoint Properties:
+ The following three properties are defined in video-interfaces.txt and
+ are valid for the output parallel bus endpoint:
+ - hsync-active: Horizontal synchronization polarity. Defaults to active high.
+ - vsync-active: Vertical synchronization polarity. Defaults to active high.
+ - data-active: Data polarity. Defaults to active high.
+
+Examples:
+ - VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422
+ 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
+ hdmi-receiver@48 {
+ compatible = "nxp,tda19971";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tda1997x>;
+ reg = <0x48>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ DOVDD-supply = <®_3p3v>;
+ AVDD-supply = <®_1p8v>;
+ DVDD-supply = <®_1p8v>;
+ /* audio */
+ #sound-dai-cells = <0>;
+ nxp,audout-format = "i2s";
+ nxp,audout-layout = <0>;
+ nxp,audout-width = <16>;
+ nxp,audout-mclk-fs = <128>;
+ /*
+ * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
+ * and Y[11:4] across 16bits in the same pixclk cycle.
+ */
+ nxp,vidout-portcfg =
+ /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
+ < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
+ /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
+ < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
+ /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
+ < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
+ /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
+ < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
+
+ port {
+ tda1997x_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <16>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ data-active = <1>;
+ };
+ };
+ };
+ - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
+ 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
+ hdmi-receiver@48 {
+ compatible = "nxp,tda19971";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tda1997x>;
+ reg = <0x48>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ DOVDD-supply = <®_3p3v>;
+ AVDD-supply = <®_1p8v>;
+ DVDD-supply = <®_1p8v>;
+ /* audio */
+ #sound-dai-cells = <0>;
+ nxp,audout-format = "i2s";
+ nxp,audout-layout = <0>;
+ nxp,audout-width = <16>;
+ nxp,audout-mclk-fs = <128>;
+ /*
+ * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
+ * and Y[11:4] across 16bits in the same pixclk cycle.
+ */
+ nxp,vidout-portcfg =
+ /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
+ < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
+ /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
+ < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
+ /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
+ < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
+ /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
+ < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
+
+ port {
+ tda1997x_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <16>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ data-active = <1>;
+ };
+ };
+ };
+ - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
+ 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
+ hdmi-receiver@48 {
+ compatible = "nxp,tda19971";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tda1997x>;
+ reg = <0x48>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ DOVDD-supply = <®_3p3v>;
+ AVDD-supply = <®_1p8v>;
+ DVDD-supply = <®_1p8v>;
+ /* audio */
+ #sound-dai-cells = <0>;
+ nxp,audout-format = "i2s";
+ nxp,audout-layout = <0>;
+ nxp,audout-width = <16>;
+ nxp,audout-mclk-fs = <128>;
+ /*
+ * The 8bpp BT656 mode outputs YCbCr[11:4] across 8bits over
+ * 2 pixclk cycles.
+ */
+ nxp,vidout-portcfg =
+ /* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
+ < TDA1997X_VP24_V15_12 TDA1997X_R_CR_CBCR_11_8 >,
+ /* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
+ < TDA1997X_VP24_V11_08 TDA1997X_R_CR_CBCR_7_4 >,
+
+ port {
+ tda1997x_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <16>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ data-active = <1>;
+ };
+ };
+ };
+
diff --git a/include/dt-bindings/media/tda1997x.h b/include/dt-bindings/media/tda1997x.h
new file mode 100644
index 0000000..bd9fbd7
--- /dev/null
+++ b/include/dt-bindings/media/tda1997x.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Gateworks Corporation
+ */
+#ifndef _DT_BINDINGS_MEDIA_TDA1997X_H
+#define _DT_BINDINGS_MEDIA_TDA1997X_H
+
+/* TDA19973 36bit Video Port control registers */
+#define TDA1997X_VP36_35_32 0
+#define TDA1997X_VP36_31_28 1
+#define TDA1997X_VP36_27_24 2
+#define TDA1997X_VP36_23_20 3
+#define TDA1997X_VP36_19_16 4
+#define TDA1997X_VP36_15_12 5
+#define TDA1997X_VP36_11_08 6
+#define TDA1997X_VP36_07_04 7
+#define TDA1997X_VP36_03_00 8
+
+/* TDA19971 24bit Video Port control registers */
+#define TDA1997X_VP24_V23_20 0
+#define TDA1997X_VP24_V19_16 1
+#define TDA1997X_VP24_V15_12 3
+#define TDA1997X_VP24_V11_08 4
+#define TDA1997X_VP24_V07_04 6
+#define TDA1997X_VP24_V03_00 7
+
+/* Pin groups */
+#define TDA1997X_VP_OUT_EN 0x80 /* enable output group */
+#define TDA1997X_VP_HIZ 0x40 /* hi-Z output group when not used */
+#define TDA1997X_VP_SWP 0x10 /* pin-swap output group */
+#define TDA1997X_R_CR_CBCR_3_0 (0 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
+#define TDA1997X_R_CR_CBCR_7_4 (1 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
+#define TDA1997X_R_CR_CBCR_11_8 (2 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
+#define TDA1997X_B_CB_3_0 (3 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
+#define TDA1997X_B_CB_7_4 (4 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
+#define TDA1997X_B_CB_11_8 (5 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
+#define TDA1997X_G_Y_3_0 (6 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
+#define TDA1997X_G_Y_7_4 (7 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
+#define TDA1997X_G_Y_11_8 (8 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
+/* pinswapped groups */
+#define TDA1997X_R_CR_CBCR_3_0_S (TDA1997X_R_CR_CBCR_3_0 | TDA1997X_VP_SWAP)
+#define TDA1997X_R_CR_CBCR_7_4_S (TDA1997X_R_CR_CBCR_7_4 | TDA1997X_VP_SWAP)
+#define TDA1997X_R_CR_CBCR_11_8_S (TDA1997X_R_CR_CBCR_11_8 | TDA1997X_VP_SWAP)
+#define TDA1997X_B_CB_3_0_S (TDA1997X_B_CB_3_0 | TDA1997X_VP_SWAP)
+#define TDA1997X_B_CB_7_4_S (TDA1997X_B_CB_7_4 | TDA1997X_VP_SWAP)
+#define TDA1997X_B_CB_11_8_S (TDA1997X_B_CB_11_8 | TDA1997X_VP_SWAP)
+#define TDA1997X_G_Y_3_0_S (TDA1997X_G_Y_3_0 | TDA1997X_VP_SWAP)
+#define TDA1997X_G_Y_7_4_S (TDA1997X_G_Y_7_4 | TDA1997X_VP_SWAP)
+#define TDA1997X_G_Y_11_8_S (TDA1997X_G_Y_11_8 | TDA1997X_VP_SWAP)
+
+/* Audio bus DAI format */
+#define TDA1997X_I2S16 1 /* I2S 16bit */
+#define TDA1997X_I2S32 2 /* I2S 32bit */
+#define TDA1997X_SPDIF 3 /* SPDIF */
+#define TDA1997X_OBA 4 /* One Bit Audio */
+#define TDA1997X_DST 5 /* Direct Stream Transfer */
+#define TDA1997X_I2S16_HBR 6 /* HBR straight in I2S 16bit mode */
+#define TDA1997X_I2S16_HBR_DEMUX 7 /* HBR demux in I2S 16bit mode */
+#define TDA1997X_I2S32_HBR_DEMUX 8 /* HBR demux in I2S 32bit mode */
+#define TDA1997X_SPDIF_HBR_DEMUX 9 /* HBR demux in SPDIF mode */
+
+/* Audio bus channel layout */
+#define TDA1997X_LAYOUT0 0 /* 2-channel */
+#define TDA1997X_LAYOUT1 1 /* 8-channel */
+
+/* Audio bus clock */
+#define TDA1997X_ACLK_16FS 0
+#define TDA1997X_ACLK_32FS 1
+#define TDA1997X_ACLK_64FS 2
+#define TDA1997X_ACLK_128FS 3
+#define TDA1997X_ACLK_256FS 4
+#define TDA1997X_ACLK_512FS 5
+
+#endif /* _DT_BINDINGS_MEDIA_TDA1997X_H */
--
2.7.4
^ permalink raw reply related
* [PATCH v6 4/6] media: i2c: Add TDA1997x HDMI receiver driver
From: Tim Harvey @ 2017-12-28 20:09 UTC (permalink / raw)
To: linux-media, alsa-devel
Cc: devicetree, linux-kernel, shawnguo, Steve Longerbeam,
Philipp Zabel, Hans Verkuil, Mauro Carvalho Chehab, Hans Verkuil
In-Reply-To: <1514491789-8697-1-git-send-email-tharvey@gateworks.com>
Add support for the TDA1997x HDMI receivers.
Cc: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
v6:
- fix return on regulator enablei in tda1997x_set_power() (Fabio)
- replace copyright with SPDX tag (Philippe)
- fix colorspace handling (Hans)
v5:
- uppercase string constants
- use v4l2_hdmi_rx_coloriemtry to fill format
- fix V4L2_CID_DV_RX_RGB_RANGE
- fix interlaced mode format
v4:
- move include/dt-bindings/media/tda1997x.h to bindings patch
- fix typos
- fix default quant range for VGA
- fix quant range handling and conv matrix
- add additional standards and capabilities to timings_cap
v3:
- use V4L2_DV_BT_FRAME_WIDTH/HEIGHT macros
- fixed missing break
- use only hdmi_infoframe_log for infoframe logging
- simplify tda1997x_s_stream error handling
- add delayed work proc to handle hotplug enable/disable
- fix set_edid (disable HPD before writing, enable after)
- remove enabling edid by default
- initialize timings
- take quant range into account in colorspace conversion
- remove vendor/product tracking (we provide this in log_status via infoframes)
- add v4l_controls
- add more detail to log_status
- calculate vhref generator timings
- timing detection fixes (rounding errors, hswidth errors)
- rename configure_input/configure_conv functions
v2:
- implement dv timings enum/cap
- remove deprecated g_mbus_config op
- fix dv_query_timings
- add EDID get/set handling
- remove max-pixel-rate support
- add audio codec DAI support
- change audio bindings
---
drivers/media/i2c/Kconfig | 9 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/tda1997x.c | 3476 ++++++++++++++++++++++++++++++++++++++++++
include/media/i2c/tda1997x.h | 41 +
4 files changed, 3527 insertions(+)
create mode 100644 drivers/media/i2c/tda1997x.c
create mode 100644 include/media/i2c/tda1997x.h
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index 3c6d642..abf24b9 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -56,6 +56,15 @@ config VIDEO_TDA9840
To compile this driver as a module, choose M here: the
module will be called tda9840.
+config VIDEO_TDA1997X
+ tristate "NXP TDA1997x HDMI receiver"
+ depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API
+ ---help---
+ V4L2 subdevice driver for the NXP TDA1997x HDMI receivers.
+
+ To compile this driver as a module, choose M here: the
+ module will be called tda1997x.
+
config VIDEO_TEA6415C
tristate "Philips TEA6415C audio processor"
depends on I2C
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index 548a9ef..adfcae9 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_VIDEO_TVAUDIO) += tvaudio.o
obj-$(CONFIG_VIDEO_TDA7432) += tda7432.o
obj-$(CONFIG_VIDEO_SAA6588) += saa6588.o
obj-$(CONFIG_VIDEO_TDA9840) += tda9840.o
+obj-$(CONFIG_VIDEO_TDA1997X) += tda1997x.o
obj-$(CONFIG_VIDEO_TEA6415C) += tea6415c.o
obj-$(CONFIG_VIDEO_TEA6420) += tea6420.o
obj-$(CONFIG_VIDEO_SAA7110) += saa7110.o
diff --git a/drivers/media/i2c/tda1997x.c b/drivers/media/i2c/tda1997x.c
new file mode 100644
index 0000000..0993c13
--- /dev/null
+++ b/drivers/media/i2c/tda1997x.c
@@ -0,0 +1,3476 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Gateworks Corporation
+ */
+#include <linux/delay.h>
+#include <linux/hdmi.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/types.h>
+#include <linux/v4l2-dv-timings.h>
+#include <linux/videodev2.h>
+
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-dv-timings.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-fwnode.h>
+#include <media/i2c/tda1997x.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <dt-bindings/media/tda1997x.h>
+
+/* debug level */
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "debug level (0-2)");
+
+/* Page 0x00 - General Control */
+#define REG_VERSION 0x0000
+#define REG_INPUT_SEL 0x0001
+#define REG_SVC_MODE 0x0002
+#define REG_HPD_MAN_CTRL 0x0003
+#define REG_RT_MAN_CTRL 0x0004
+#define REG_STANDBY_SOFT_RST 0x000A
+#define REG_HDMI_SOFT_RST 0x000B
+#define REG_HDMI_INFO_RST 0x000C
+#define REG_INT_FLG_CLR_TOP 0x000E
+#define REG_INT_FLG_CLR_SUS 0x000F
+#define REG_INT_FLG_CLR_DDC 0x0010
+#define REG_INT_FLG_CLR_RATE 0x0011
+#define REG_INT_FLG_CLR_MODE 0x0012
+#define REG_INT_FLG_CLR_INFO 0x0013
+#define REG_INT_FLG_CLR_AUDIO 0x0014
+#define REG_INT_FLG_CLR_HDCP 0x0015
+#define REG_INT_FLG_CLR_AFE 0x0016
+#define REG_INT_MASK_TOP 0x0017
+#define REG_INT_MASK_SUS 0x0018
+#define REG_INT_MASK_DDC 0x0019
+#define REG_INT_MASK_RATE 0x001A
+#define REG_INT_MASK_MODE 0x001B
+#define REG_INT_MASK_INFO 0x001C
+#define REG_INT_MASK_AUDIO 0x001D
+#define REG_INT_MASK_HDCP 0x001E
+#define REG_INT_MASK_AFE 0x001F
+#define REG_DETECT_5V 0x0020
+#define REG_SUS_STATUS 0x0021
+#define REG_V_PER 0x0022
+#define REG_H_PER 0x0025
+#define REG_HS_WIDTH 0x0027
+#define REG_FMT_H_TOT 0x0029
+#define REG_FMT_H_ACT 0x002b
+#define REG_FMT_H_FRONT 0x002d
+#define REG_FMT_H_SYNC 0x002f
+#define REG_FMT_H_BACK 0x0031
+#define REG_FMT_V_TOT 0x0033
+#define REG_FMT_V_ACT 0x0035
+#define REG_FMT_V_FRONT_F1 0x0037
+#define REG_FMT_V_FRONT_F2 0x0038
+#define REG_FMT_V_SYNC 0x0039
+#define REG_FMT_V_BACK_F1 0x003a
+#define REG_FMT_V_BACK_F2 0x003b
+#define REG_FMT_DE_ACT 0x003c
+#define REG_RATE_CTRL 0x0040
+#define REG_CLK_MIN_RATE 0x0043
+#define REG_CLK_MAX_RATE 0x0046
+#define REG_CLK_A_STATUS 0x0049
+#define REG_CLK_A_RATE 0x004A
+#define REG_DRIFT_CLK_A_REG 0x004D
+#define REG_CLK_B_STATUS 0x004E
+#define REG_CLK_B_RATE 0x004F
+#define REG_DRIFT_CLK_B_REG 0x0052
+#define REG_HDCP_CTRL 0x0060
+#define REG_HDCP_KDS 0x0061
+#define REG_HDCP_BCAPS 0x0063
+#define REG_HDCP_KEY_CTRL 0x0064
+#define REG_INFO_CTRL 0x0076
+#define REG_INFO_EXCEED 0x0077
+#define REG_PIX_REPEAT 0x007B
+#define REG_AUDIO_PATH 0x007C
+#define REG_AUDCFG 0x007D
+#define REG_AUDIO_OUT_ENABLE 0x007E
+#define REG_AUDIO_OUT_HIZ 0x007F
+#define REG_VDP_CTRL 0x0080
+#define REG_VDP_MATRIX 0x0081
+#define REG_VHREF_CTRL 0x00A0
+#define REG_PXCNT_PR 0x00A2
+#define REG_PXCNT_NPIX 0x00A4
+#define REG_LCNT_PR 0x00A6
+#define REG_LCNT_NLIN 0x00A8
+#define REG_HREF_S 0x00AA
+#define REG_HREF_E 0x00AC
+#define REG_HS_S 0x00AE
+#define REG_HS_E 0x00B0
+#define REG_VREF_F1_S 0x00B2
+#define REG_VREF_F1_WIDTH 0x00B4
+#define REG_VREF_F2_S 0x00B5
+#define REG_VREF_F2_WIDTH 0x00B7
+#define REG_VS_F1_LINE_S 0x00B8
+#define REG_VS_F1_LINE_WIDTH 0x00BA
+#define REG_VS_F2_LINE_S 0x00BB
+#define REG_VS_F2_LINE_WIDTH 0x00BD
+#define REG_VS_F1_PIX_S 0x00BE
+#define REG_VS_F1_PIX_E 0x00C0
+#define REG_VS_F2_PIX_S 0x00C2
+#define REG_VS_F2_PIX_E 0x00C4
+#define REG_FREF_F1_S 0x00C6
+#define REG_FREF_F2_S 0x00C8
+#define REG_FDW_S 0x00ca
+#define REG_FDW_E 0x00cc
+#define REG_BLK_GY 0x00da
+#define REG_BLK_BU 0x00dc
+#define REG_BLK_RV 0x00de
+#define REG_FILTERS_CTRL 0x00e0
+#define REG_DITHERING_CTRL 0x00E9
+#define REG_OF 0x00EA
+#define REG_PCLK 0x00EB
+#define REG_HS_HREF 0x00EC
+#define REG_VS_VREF 0x00ED
+#define REG_DE_FREF 0x00EE
+#define REG_VP35_32_CTRL 0x00EF
+#define REG_VP31_28_CTRL 0x00F0
+#define REG_VP27_24_CTRL 0x00F1
+#define REG_VP23_20_CTRL 0x00F2
+#define REG_VP19_16_CTRL 0x00F3
+#define REG_VP15_12_CTRL 0x00F4
+#define REG_VP11_08_CTRL 0x00F5
+#define REG_VP07_04_CTRL 0x00F6
+#define REG_VP03_00_CTRL 0x00F7
+#define REG_CURPAGE_00H 0xFF
+
+#define MASK_VPER 0x3fffff
+#define MASK_VHREF 0x3fff
+#define MASK_HPER 0x0fff
+#define MASK_HSWIDTH 0x03ff
+
+/* HPD Detection */
+#define DETECT_UTIL BIT(7) /* utility of HDMI level */
+#define DETECT_HPD BIT(6) /* HPD of HDMI level */
+#define DETECT_5V_SEL BIT(2) /* 5V present on selected input */
+#define DETECT_5V_B BIT(1) /* 5V present on input B */
+#define DETECT_5V_A BIT(0) /* 5V present on input A */
+
+/* Input Select */
+#define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */
+#define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */
+#define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */
+#define INPUT_SEL_B BIT(0) /* 0=inputA 1=inputB */
+
+/* Service Mode */
+#define SVC_MODE_CLK2_MASK 0xc0
+#define SVC_MODE_CLK2_SHIFT 6
+#define SVC_MODE_CLK2_XTL 0L
+#define SVC_MODE_CLK2_XTLDIV2 1L
+#define SVC_MODE_CLK2_HDMIX2 3L
+#define SVC_MODE_CLK1_MASK 0x30
+#define SVC_MODE_CLK1_SHIFT 4
+#define SVC_MODE_CLK1_XTAL 0L
+#define SVC_MODE_CLK1_XTLDIV2 1L
+#define SVC_MODE_CLK1_HDMI 3L
+#define SVC_MODE_RAMP BIT(3) /* 0=colorbar 1=ramp */
+#define SVC_MODE_PAL BIT(2) /* 0=NTSC(480i/p) 1=PAL(576i/p) */
+#define SVC_MODE_INT_PROG BIT(1) /* 0=interlaced 1=progressive */
+#define SVC_MODE_SM_ON BIT(0) /* Enable color bars and tone gen */
+
+/* HDP Manual Control */
+#define HPD_MAN_CTRL_HPD_PULSE BIT(7) /* HPD Pulse low 110ms */
+#define HPD_MAN_CTRL_5VEN BIT(2) /* Output 5V */
+#define HPD_MAN_CTRL_HPD_B BIT(1) /* Assert HPD High for Input A */
+#define HPD_MAN_CTRL_HPD_A BIT(0) /* Assert HPD High for Input A */
+
+/* RT_MAN_CTRL */
+#define RT_MAN_CTRL_RT_AUTO BIT(7)
+#define RT_MAN_CTRL_RT BIT(6)
+#define RT_MAN_CTRL_RT_B BIT(1) /* enable TMDS pull-up on Input B */
+#define RT_MAN_CTRL_RT_A BIT(0) /* enable TMDS pull-up on Input A */
+
+/* VDP_CTRL */
+#define VDP_CTRL_COMPDEL_BP BIT(5) /* bypass compdel */
+#define VDP_CTRL_FORMATTER_BP BIT(4) /* bypass formatter */
+#define VDP_CTRL_PREFILTER_BP BIT(1) /* bypass prefilter */
+#define VDP_CTRL_MATRIX_BP BIT(0) /* bypass matrix conversion */
+
+/* REG_VHREF_CTRL */
+#define VHREF_INT_DET BIT(7) /* interlace detect: 1=alt 0=frame */
+#define VHREF_VSYNC_MASK 0x60
+#define VHREF_VSYNC_SHIFT 6
+#define VHREF_VSYNC_AUTO 0L
+#define VHREF_VSYNC_FDW 1L
+#define VHREF_VSYNC_EVEN 2L
+#define VHREF_VSYNC_ODD 3L
+#define VHREF_STD_DET_MASK 0x18
+#define VHREF_STD_DET_SHIFT 3
+#define VHREF_STD_DET_PAL 0L
+#define VHREF_STD_DET_NTSC 1L
+#define VHREF_STD_DET_AUTO 2L
+#define VHREF_STD_DET_OFF 3L
+#define VHREF_VREF_SRC_STD BIT(2) /* 1=from standard 0=manual */
+#define VHREF_HREF_SRC_STD BIT(1) /* 1=from standard 0=manual */
+#define VHREF_HSYNC_SEL_HS BIT(0) /* 1=HS 0=VS */
+
+/* AUDIO_OUT_ENABLE */
+#define AUDIO_OUT_ENABLE_ACLK BIT(5)
+#define AUDIO_OUT_ENABLE_WS BIT(4)
+#define AUDIO_OUT_ENABLE_AP3 BIT(3)
+#define AUDIO_OUT_ENABLE_AP2 BIT(2)
+#define AUDIO_OUT_ENABLE_AP1 BIT(1)
+#define AUDIO_OUT_ENABLE_AP0 BIT(0)
+
+/* Prefilter Control */
+#define FILTERS_CTRL_BU_MASK 0x0c
+#define FILTERS_CTRL_BU_SHIFT 2
+#define FILTERS_CTRL_RV_MASK 0x03
+#define FILTERS_CTRL_RV_SHIFT 0
+#define FILTERS_CTRL_OFF 0L /* off */
+#define FILTERS_CTRL_2TAP 1L /* 2 Taps */
+#define FILTERS_CTRL_7TAP 2L /* 7 Taps */
+#define FILTERS_CTRL_2_7TAP 3L /* 2/7 Taps */
+
+/* PCLK Configuration */
+#define PCLK_DELAY_MASK 0x70
+#define PCLK_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
+#define PCLK_INV_SHIFT 2
+#define PCLK_SEL_MASK 0x03 /* clock scaler */
+#define PCLK_SEL_SHIFT 0
+#define PCLK_SEL_X1 0L
+#define PCLK_SEL_X2 1L
+#define PCLK_SEL_DIV2 2L
+#define PCLK_SEL_DIV4 3L
+
+/* Pixel Repeater */
+#define PIX_REPEAT_MASK_UP_SEL 0x30
+#define PIX_REPEAT_MASK_REP 0x0f
+#define PIX_REPEAT_SHIFT 4
+#define PIX_REPEAT_CHROMA 1
+
+/* Page 0x01 - HDMI info and packets */
+#define REG_HDMI_FLAGS 0x0100
+#define REG_DEEP_COLOR_MODE 0x0101
+#define REG_AUDIO_FLAGS 0x0108
+#define REG_AUDIO_FREQ 0x0109
+#define REG_ACP_PACKET_TYPE 0x0141
+#define REG_ISRC1_PACKET_TYPE 0x0161
+#define REG_ISRC2_PACKET_TYPE 0x0181
+#define REG_GBD_PACKET_TYPE 0x01a1
+
+/* HDMI_FLAGS */
+#define HDMI_FLAGS_AUDIO BIT(7) /* Audio packet in last videoframe */
+#define HDMI_FLAGS_HDMI BIT(6) /* HDMI detected */
+#define HDMI_FLAGS_EESS BIT(5) /* EESS detected */
+#define HDMI_FLAGS_HDCP BIT(4) /* HDCP detected */
+#define HDMI_FLAGS_AVMUTE BIT(3) /* AVMUTE */
+#define HDMI_FLAGS_AUD_LAYOUT BIT(2) /* Layout status Audio sample packet */
+#define HDMI_FLAGS_AUD_FIFO_OF BIT(1) /* FIFO read/write pointers crossed */
+#define HDMI_FLAGS_AUD_FIFO_LOW BIT(0) /* FIFO read ptr within 2 of write */
+
+/* Page 0x12 - HDMI Extra control and debug */
+#define REG_CLK_CFG 0x1200
+#define REG_CLK_OUT_CFG 0x1201
+#define REG_CFG1 0x1202
+#define REG_CFG2 0x1203
+#define REG_WDL_CFG 0x1210
+#define REG_DELOCK_DELAY 0x1212
+#define REG_PON_OVR_EN 0x12A0
+#define REG_PON_CBIAS 0x12A1
+#define REG_PON_RESCAL 0x12A2
+#define REG_PON_RES 0x12A3
+#define REG_PON_CLK 0x12A4
+#define REG_PON_PLL 0x12A5
+#define REG_PON_EQ 0x12A6
+#define REG_PON_DES 0x12A7
+#define REG_PON_OUT 0x12A8
+#define REG_PON_MUX 0x12A9
+#define REG_MODE_REC_CFG1 0x12F8
+#define REG_MODE_REC_CFG2 0x12F9
+#define REG_MODE_REC_STS 0x12FA
+#define REG_AUDIO_LAYOUT 0x12D0
+
+#define PON_EN 1
+#define PON_DIS 0
+
+/* CLK CFG */
+#define CLK_CFG_INV_OUT_CLK BIT(7)
+#define CLK_CFG_INV_BUS_CLK BIT(6)
+#define CLK_CFG_SEL_ACLK_EN BIT(1)
+#define CLK_CFG_SEL_ACLK BIT(0)
+#define CLK_CFG_DIS 0
+
+/* Page 0x13 - HDMI Extra control and debug */
+#define REG_DEEP_COLOR_CTRL 0x1300
+#define REG_CGU_DBG_SEL 0x1305
+#define REG_HDCP_DDC_ADDR 0x1310
+#define REG_HDCP_KIDX 0x1316
+#define REG_DEEP_PLL7_BYP 0x1347
+#define REG_HDCP_DE_CTRL 0x1370
+#define REG_HDCP_EP_FILT_CTRL 0x1371
+#define REG_HDMI_CTRL 0x1377
+#define REG_HMTP_CTRL 0x137a
+#define REG_TIMER_D 0x13CF
+#define REG_SUS_SET_RGB0 0x13E1
+#define REG_SUS_SET_RGB1 0x13E2
+#define REG_SUS_SET_RGB2 0x13E3
+#define REG_SUS_SET_RGB3 0x13E4
+#define REG_SUS_SET_RGB4 0x13E5
+#define REG_MAN_SUS_HDMI_SEL 0x13E8
+#define REG_MAN_HDMI_SET 0x13E9
+#define REG_SUS_CLOCK_GOOD 0x13EF
+
+/* HDCP DE Control */
+#define HDCP_DE_MODE_MASK 0xc0 /* DE Measurement mode */
+#define HDCP_DE_MODE_SHIFT 6
+#define HDCP_DE_REGEN_EN BIT(5) /* enable regen mode */
+#define HDCP_DE_FILTER_MASK 0x18 /* DE filter sensitivity */
+#define HDCP_DE_FILTER_SHIFT 3
+#define HDCP_DE_COMP_MASK 0x07 /* DE Composition mode */
+#define HDCP_DE_COMP_MIXED 6L
+#define HDCP_DE_COMP_OR 5L
+#define HDCP_DE_COMP_AND 4L
+#define HDCP_DE_COMP_CH3 3L
+#define HDCP_DE_COMP_CH2 2L
+#define HDCP_DE_COMP_CH1 1L
+#define HDCP_DE_COMP_CH0 0L
+
+/* HDCP EP Filter Control */
+#define HDCP_EP_FIL_CTL_MASK 0x30
+#define HDCP_EP_FIL_CTL_SHIFT 4
+#define HDCP_EP_FIL_VS_MASK 0x0c
+#define HDCP_EP_FIL_VS_SHIFT 2
+#define HDCP_EP_FIL_HS_MASK 0x03
+#define HDCP_EP_FIL_HS_SHIFT 0
+
+/* HDMI_CTRL */
+#define HDMI_CTRL_MUTE_MASK 0x0c
+#define HDMI_CTRL_MUTE_SHIFT 2
+#define HDMI_CTRL_MUTE_AUTO 0L
+#define HDMI_CTRL_MUTE_OFF 1L
+#define HDMI_CTRL_MUTE_ON 2L
+#define HDMI_CTRL_HDCP_MASK 0x03
+#define HDMI_CTRL_HDCP_SHIFT 0
+#define HDMI_CTRL_HDCP_EESS 2L
+#define HDMI_CTRL_HDCP_OESS 1L
+#define HDMI_CTRL_HDCP_AUTO 0L
+
+/* CGU_DBG_SEL bits */
+#define CGU_DBG_CLK_SEL_MASK 0x18
+#define CGU_DBG_CLK_SEL_SHIFT 3
+#define CGU_DBG_XO_FRO_SEL BIT(2)
+#define CGU_DBG_VDP_CLK_SEL BIT(1)
+#define CGU_DBG_PIX_CLK_SEL BIT(0)
+
+/* REG_MAN_SUS_HDMI_SEL / REG_MAN_HDMI_SET bits */
+#define MAN_DIS_OUT_BUF BIT(7)
+#define MAN_DIS_ANA_PATH BIT(6)
+#define MAN_DIS_HDCP BIT(5)
+#define MAN_DIS_TMDS_ENC BIT(4)
+#define MAN_DIS_TMDS_FLOW BIT(3)
+#define MAN_RST_HDCP BIT(2)
+#define MAN_RST_TMDS_ENC BIT(1)
+#define MAN_RST_TMDS_FLOW BIT(0)
+
+/* Page 0x14 - Audio Extra control and debug */
+#define REG_FIFO_LATENCY_VAL 0x1403
+#define REG_AUDIO_CLOCK 0x1411
+#define REG_TEST_NCTS_CTRL 0x1415
+#define REG_TEST_AUDIO_FREQ 0x1426
+#define REG_TEST_MODE 0x1437
+
+/* Audio Clock Configuration */
+#define AUDIO_CLOCK_PLL_PD BIT(7) /* powerdown PLL */
+#define AUDIO_CLOCK_SEL_MASK 0x7f
+#define AUDIO_CLOCK_SEL_16FS 0L /* 16*fs */
+#define AUDIO_CLOCK_SEL_32FS 1L /* 32*fs */
+#define AUDIO_CLOCK_SEL_64FS 2L /* 64*fs */
+#define AUDIO_CLOCK_SEL_128FS 3L /* 128*fs */
+#define AUDIO_CLOCK_SEL_256FS 4L /* 256*fs */
+#define AUDIO_CLOCK_SEL_512FS 5L /* 512*fs */
+
+/* Page 0x20: EDID and Hotplug Detect */
+#define REG_EDID_IN_BYTE0 0x2000 /* EDID base */
+#define REG_EDID_IN_VERSION 0x2080
+#define REG_EDID_ENABLE 0x2081
+#define REG_HPD_POWER 0x2084
+#define REG_HPD_AUTO_CTRL 0x2085
+#define REG_HPD_DURATION 0x2086
+#define REG_RX_HPD_HEAC 0x2087
+
+/* EDID_ENABLE */
+#define EDID_ENABLE_NACK_OFF BIT(7)
+#define EDID_ENABLE_EDID_ONLY BIT(6)
+#define EDID_ENABLE_B_EN BIT(1)
+#define EDID_ENABLE_A_EN BIT(0)
+
+/* HPD Power */
+#define HPD_POWER_BP_MASK 0x0c
+#define HPD_POWER_BP_SHIFT 2
+#define HPD_POWER_BP_LOW 0L
+#define HPD_POWER_BP_HIGH 1L
+#define HPD_POWER_EDID_ONLY BIT(1)
+
+/* HPD Auto control */
+#define HPD_AUTO_READ_EDID BIT(7)
+#define HPD_AUTO_HPD_F3TECH BIT(5)
+#define HPD_AUTO_HP_OTHER BIT(4)
+#define HPD_AUTO_HPD_UNSEL BIT(3)
+#define HPD_AUTO_HPD_ALL_CH BIT(2)
+#define HPD_AUTO_HPD_PRV_CH BIT(1)
+#define HPD_AUTO_HPD_NEW_CH BIT(0)
+
+/* Page 0x21 - EDID content */
+#define REG_EDID_IN_BYTE128 0x2100 /* CEA Extension block */
+#define REG_EDID_IN_SPA_SUB 0x2180
+#define REG_EDID_IN_SPA_AB_A 0x2181
+#define REG_EDID_IN_SPA_CD_A 0x2182
+#define REG_EDID_IN_CKSUM_A 0x2183
+#define REG_EDID_IN_SPA_AB_B 0x2184
+#define REG_EDID_IN_SPA_CD_B 0x2185
+#define REG_EDID_IN_CKSUM_B 0x2186
+
+/* Page 0x30 - NV Configuration */
+#define REG_RT_AUTO_CTRL 0x3000
+#define REG_EQ_MAN_CTRL0 0x3001
+#define REG_EQ_MAN_CTRL1 0x3002
+#define REG_OUTPUT_CFG 0x3003
+#define REG_MUTE_CTRL 0x3004
+#define REG_SLAVE_ADDR 0x3005
+#define REG_CMTP_REG6 0x3006
+#define REG_CMTP_REG7 0x3007
+#define REG_CMTP_REG8 0x3008
+#define REG_CMTP_REG9 0x3009
+#define REG_CMTP_REGA 0x300A
+#define REG_CMTP_REGB 0x300B
+#define REG_CMTP_REGC 0x300C
+#define REG_CMTP_REGD 0x300D
+#define REG_CMTP_REGE 0x300E
+#define REG_CMTP_REGF 0x300F
+#define REG_CMTP_REG10 0x3010
+#define REG_CMTP_REG11 0x3011
+
+/* Page 0x80 - CEC */
+#define REG_PWR_CONTROL 0x80F4
+#define REG_OSC_DIVIDER 0x80F5
+#define REG_EN_OSC_PERIOD_LSB 0x80F8
+#define REG_CONTROL 0x80FF
+
+/* global interrupt flags (INT_FLG_CRL_TOP) */
+#define INTERRUPT_AFE BIT(7) /* AFE module */
+#define INTERRUPT_HDCP BIT(6) /* HDCP module */
+#define INTERRUPT_AUDIO BIT(5) /* Audio module */
+#define INTERRUPT_INFO BIT(4) /* Infoframe module */
+#define INTERRUPT_MODE BIT(3) /* HDMI mode module */
+#define INTERRUPT_RATE BIT(2) /* rate module */
+#define INTERRUPT_DDC BIT(1) /* DDC module */
+#define INTERRUPT_SUS BIT(0) /* SUS module */
+
+/* INT_FLG_CLR_HDCP bits */
+#define MASK_HDCP_MTP BIT(7) /* HDCP MTP busy */
+#define MASK_HDCP_DLMTP BIT(4) /* HDCP end download MTP to SRAM */
+#define MASK_HDCP_DLRAM BIT(3) /* HDCP end download keys from SRAM */
+#define MASK_HDCP_ENC BIT(2) /* HDCP ENC */
+#define MASK_STATE_C5 BIT(1) /* HDCP State C5 reached */
+#define MASK_AKSV BIT(0) /* AKSV received (start of auth) */
+
+/* INT_FLG_CLR_RATE bits */
+#define MASK_RATE_B_DRIFT BIT(7) /* Rate measurement drifted */
+#define MASK_RATE_B_ST BIT(6) /* Rate measurement stability change */
+#define MASK_RATE_B_ACT BIT(5) /* Rate measurement activity change */
+#define MASK_RATE_B_PST BIT(4) /* Rate measreument presence change */
+#define MASK_RATE_A_DRIFT BIT(3) /* Rate measurement drifted */
+#define MASK_RATE_A_ST BIT(2) /* Rate measurement stability change */
+#define MASK_RATE_A_ACT BIT(1) /* Rate measurement presence change */
+#define MASK_RATE_A_PST BIT(0) /* Rate measreument presence change */
+
+/* INT_FLG_CLR_SUS (Start Up Sequencer) bits */
+#define MASK_MPT BIT(7) /* Config MTP end of process */
+#define MASK_FMT BIT(5) /* Video format changed */
+#define MASK_RT_PULSE BIT(4) /* End of termination resistance pulse */
+#define MASK_SUS_END BIT(3) /* SUS last state reached */
+#define MASK_SUS_ACT BIT(2) /* Activity of selected input changed */
+#define MASK_SUS_CH BIT(1) /* Selected input changed */
+#define MASK_SUS_ST BIT(0) /* SUS state changed */
+
+/* INT_FLG_CLR_DDC bits */
+#define MASK_EDID_MTP BIT(7) /* EDID MTP end of process */
+#define MASK_DDC_ERR BIT(6) /* master DDC error */
+#define MASK_DDC_CMD_DONE BIT(5) /* master DDC cmd send correct */
+#define MASK_READ_DONE BIT(4) /* End of down EDID read */
+#define MASK_RX_DDC_SW BIT(3) /* Output DDC switching finished */
+#define MASK_HDCP_DDC_SW BIT(2) /* HDCP DDC switching finished */
+#define MASK_HDP_PULSE_END BIT(1) /* End of Hot Plug Detect pulse */
+#define MASK_DET_5V BIT(0) /* Detection of +5V */
+
+/* INT_FLG_CLR_MODE bits */
+#define MASK_HDMI_FLG BIT(7) /* HDMI mode/avmute/encrypt/FIFO fail */
+#define MASK_GAMUT BIT(6) /* Gamut packet */
+#define MASK_ISRC2 BIT(5) /* ISRC2 packet */
+#define MASK_ISRC1 BIT(4) /* ISRC1 packet */
+#define MASK_ACP BIT(3) /* Audio Content Protection packet */
+#define MASK_DC_NO_GCP BIT(2) /* GCP not received in 5 frames */
+#define MASK_DC_PHASE BIT(1) /* deepcolor pixel phase needs update */
+#define MASK_DC_MODE BIT(0) /* deepcolor color depth changed */
+
+/* INT_FLG_CLR_INFO bits (Infoframe Change Status) */
+#define MASK_MPS_IF BIT(6) /* MPEG Source Product */
+#define MASK_AUD_IF BIT(5) /* Audio */
+#define MASK_SPD_IF BIT(4) /* Source Product Descriptor */
+#define MASK_AVI_IF BIT(3) /* Auxiliary Video IF */
+#define MASK_VS_IF_OTHER_BK2 BIT(2) /* Vendor Specific (bank2) */
+#define MASK_VS_IF_OTHER_BK1 BIT(1) /* Vendor Specific (bank1) */
+#define MASK_VS_IF_HDMI BIT(0) /* Vendor Specific (w/ HDMI LLC code) */
+
+/* INT_FLG_CLR_AUDIO bits */
+#define MASK_AUDIO_FREQ_FLG BIT(5) /* Audio freq change */
+#define MASK_AUDIO_FLG BIT(4) /* DST, OBA, HBR, ASP change */
+#define MASK_MUTE_FLG BIT(3) /* Audio Mute */
+#define MASK_CH_STATE BIT(2) /* Channel status */
+#define MASK_UNMUTE_FIFO BIT(1) /* Audio Unmute */
+#define MASK_ERROR_FIFO_PT BIT(0) /* Audio FIFO pointer error */
+
+/* INT_FLG_CLR_AFE bits */
+#define MASK_AFE_WDL_UNLOCKED BIT(7) /* Wordlocker was unlocked */
+#define MASK_AFE_GAIN_DONE BIT(6) /* Gain calibration done */
+#define MASK_AFE_OFFSET_DONE BIT(5) /* Offset calibration done */
+#define MASK_AFE_ACTIVITY_DET BIT(4) /* Activity detected on data */
+#define MASK_AFE_PLL_LOCK BIT(3) /* TMDS PLL is locked */
+#define MASK_AFE_TRMCAL_DONE BIT(2) /* Termination calibration done */
+#define MASK_AFE_ASU_STATE BIT(1) /* ASU state is reached */
+#define MASK_AFE_ASU_READY BIT(0) /* AFE calibration done: TMDS ready */
+
+/* Audio Output */
+#define AUDCFG_CLK_INVERT BIT(7) /* invert A_CLK polarity */
+#define AUDCFG_TEST_TONE BIT(6) /* enable test tone generator */
+#define AUDCFG_BUS_SHIFT 5
+#define AUDCFG_BUS_I2S 0L
+#define AUDCFG_BUS_SPDIF 1L
+#define AUDCFG_I2SW_SHIFT 4
+#define AUDCFG_I2SW_16 0L
+#define AUDCFG_I2SW_32 1L
+#define AUDCFG_AUTO_MUTE_EN BIT(3) /* Enable Automatic audio mute */
+#define AUDCFG_HBR_SHIFT 2
+#define AUDCFG_HBR_STRAIGHT 0L /* straight via AP0 */
+#define AUDCFG_HBR_DEMUX 1L /* demuxed via AP0:AP3 */
+#define AUDCFG_TYPE_MASK 0x03
+#define AUDCFG_TYPE_SHIFT 0
+#define AUDCFG_TYPE_DST 3L /* Direct Stream Transfer (DST) */
+#define AUDCFG_TYPE_OBA 2L /* One Bit Audio (OBA) */
+#define AUDCFG_TYPE_HBR 1L /* High Bit Rate (HBR) */
+#define AUDCFG_TYPE_PCM 0L /* Audio samples */
+
+/* Video Formatter */
+#define OF_VP_ENABLE BIT(7) /* VP[35:0]/HS/VS/DE/CLK */
+#define OF_BLK BIT(4) /* blanking codes */
+#define OF_TRC BIT(3) /* timing codes (SAV/EAV) */
+#define OF_FMT_MASK 0x3
+#define OF_FMT_444 0L /* RGB444/YUV444 */
+#define OF_FMT_422_SMPT 1L /* YUV422 semi-planar */
+#define OF_FMT_422_CCIR 2L /* YUV422 CCIR656 */
+
+/* HS/HREF output control */
+#define HS_HREF_DELAY_MASK 0xf0
+#define HS_HREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
+#define HS_HREF_PXQ_SHIFT 3 /* Timing codes from HREF */
+#define HS_HREF_INV_SHIFT 2 /* polarity (1=invert) */
+#define HS_HREF_SEL_MASK 0x03
+#define HS_HREF_SEL_SHIFT 0
+#define HS_HREF_SEL_HS_VHREF 0L /* HS from VHREF */
+#define HS_HREF_SEL_HREF_VHREF 1L /* HREF from VHREF */
+#define HS_HREF_SEL_HREF_HDMI 2L /* HREF from HDMI */
+#define HS_HREF_SEL_NONE 3L /* not generated */
+
+/* VS output control */
+#define VS_VREF_DELAY_MASK 0xf0
+#define VS_VREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
+#define VS_VREF_INV_SHIFT 2 /* polarity (1=invert) */
+#define VS_VREF_SEL_MASK 0x03
+#define VS_VREF_SEL_SHIFT 0
+#define VS_VREF_SEL_VS_VHREF 0L /* VS from VHREF */
+#define VS_VREF_SEL_VREF_VHREF 1L /* VREF from VHREF */
+#define VS_VREF_SEL_VREF_HDMI 2L /* VREF from HDMI */
+#define VS_VREF_SEL_NONE 3L /* not generated */
+
+/* DE/FREF output control */
+#define DE_FREF_DELAY_MASK 0xf0
+#define DE_FREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
+#define DE_FREF_DE_PXQ_SHIFT 3 /* Timing codes from DE */
+#define DE_FREF_INV_SHIFT 2 /* polarity (1=invert) */
+#define DE_FREF_SEL_MASK 0x03
+#define DE_FREF_SEL_SHIFT 0
+#define DE_FREF_SEL_DE_VHREF 0L /* DE from VHREF (HREF and not(VREF) */
+#define DE_FREF_SEL_FREF_VHREF 1L /* FREF from VHREF */
+#define DE_FREF_SEL_FREF_HDMI 2L /* FREF from HDMI */
+#define DE_FREF_SEL_NONE 3L /* not generated */
+
+/* HDMI_SOFT_RST bits */
+#define RESET_DC BIT(7) /* Reset deep color module */
+#define RESET_HDCP BIT(6) /* Reset HDCP module */
+#define RESET_KSV BIT(5) /* Reset KSV-FIFO */
+#define RESET_SCFG BIT(4) /* Reset HDCP and repeater function */
+#define RESET_HCFG BIT(3) /* Reset HDCP DDC part */
+#define RESET_PA BIT(2) /* Reset polarity adjust */
+#define RESET_EP BIT(1) /* Reset Error protection */
+#define RESET_TMDS BIT(0) /* Reset TMDS (calib, encoding, flow) */
+
+/* HDMI_INFO_RST bits */
+#define NACK_HDCP BIT(7) /* No ACK on HDCP request */
+#define RESET_FIFO BIT(4) /* Reset Audio FIFO control */
+#define RESET_GAMUT BIT(3) /* Clear Gamut packet */
+#define RESET_AI BIT(2) /* Clear ACP and ISRC packets */
+#define RESET_IF BIT(1) /* Clear all Audio infoframe packets */
+#define RESET_AUDIO BIT(0) /* Reset Audio FIFO control */
+
+/* HDCP_BCAPS bits */
+#define HDCP_HDMI BIT(7) /* HDCP suports HDMI (vs DVI only) */
+#define HDCP_REPEATER BIT(6) /* HDCP supports repeater function */
+#define HDCP_READY BIT(5) /* set by repeater function */
+#define HDCP_FAST BIT(4) /* Up to 400kHz */
+#define HDCP_11 BIT(1) /* HDCP 1.1 supported */
+#define HDCP_FAST_REAUTH BIT(0) /* fast reauthentication supported */
+
+/* Audio output formatter */
+#define AUDIO_LAYOUT_SP_FLAG BIT(2) /* sp flag used by FIFO */
+#define AUDIO_LAYOUT_MANUAL BIT(1) /* manual layout (vs per pkt) */
+#define AUDIO_LAYOUT_LAYOUT1 BIT(0) /* Layout1: AP0-3 vs Layout0:AP0 */
+
+/* masks for interrupt status registers */
+#define MASK_SUS_STATUS 0x1F
+#define LAST_STATE_REACHED 0x1B
+#define MASK_CLK_STABLE 0x04
+#define MASK_CLK_ACTIVE 0x02
+#define MASK_SUS_STATE 0x10
+#define MASK_SR_FIFO_FIFO_CTRL 0x30
+#define MASK_AUDIO_FLAG 0x10
+
+/* Rate measurement */
+#define RATE_REFTIM_ENABLE 0x01
+#define CLK_MIN_RATE 0x0057e4
+#define CLK_MAX_RATE 0x0395f8
+#define WDL_CFG_VAL 0x82
+#define DC_FILTER_VAL 0x31
+
+/* Infoframe */
+#define VS_HDMI_IF_UPDATE 0x0200
+#define VS_HDMI_IF 0x0201
+#define VS_BK1_IF_UPDATE 0x0220
+#define VS_BK1_IF 0x0221
+#define VS_BK2_IF_UPDATE 0x0240
+#define VS_BK2_IF 0x0241
+#define AVI_IF_UPDATE 0x0260
+#define AVI_IF 0x0261
+#define SPD_IF_UPDATE 0x0280
+#define SPD_IF 0x0281
+#define AUD_IF_UPDATE 0x02a0
+#define AUD_IF 0x02a1
+#define MPS_IF_UPDATE 0x02c0
+#define MPS_IF 0x02c1
+
+/* Audio formats */
+static const char * const audtype_names[] = {
+ "PCM", /* PCM Samples */
+ "HBR", /* High Bit Rate Audio */
+ "OBA", /* One-Bit Audio */
+ "DST" /* Direct Stream Transfer */
+};
+
+/* Audio output port formats */
+enum audfmt_types {
+ AUDFMT_TYPE_DISABLED = 0,
+ AUDFMT_TYPE_I2S,
+ AUDFMT_TYPE_SPDIF,
+};
+static const char * const audfmt_names[] = {
+ "Disabled",
+ "I2S",
+ "SPDIF",
+};
+
+/* Video input formats */
+static const char * const hdmi_colorspace_names[] = {
+ "RGB", "YUV422", "YUV444", "YUV420", "", "", "", "",
+};
+static const char * const hdmi_colorimetry_names[] = {
+ "", "ITU601", "ITU709", "Extended",
+};
+static const char * const v4l2_quantization_names[] = {
+ "Default",
+ "Rull Range (0-255)",
+ "Limited Range (16-235)",
+};
+
+/* Video output port formats */
+static const char * const vidfmt_names[] = {
+ "RGB444/YUV444", /* RGB/YUV444 16bit data bus, 8bpp */
+ "YUV422 semi-planar", /* YUV422 16bit data base, 8bpp */
+ "YUV422 CCIR656", /* BT656 (YUV 8bpp 2 clock per pixel) */
+ "Invalid",
+};
+
+/*
+ * Video Output formats
+ * There are 24 video output pins on TDA19971 and 36 on TDA19973 supporting
+ * the following output formats:
+ * - RGB444
+ * - YUV444
+ * - YUV422 semi-planar based on ITU-R BT.601
+ * - YUV422 ITU-R BT.656
+ *
+ * TDA19971 can output 3x8bits per pixel
+ * TDA19973 can output 3x8, 3x10, or 3x12bit per pixel
+ *
+ * Deep color modes (3x10 or 3x12 bits) are possible in any case.
+ *
+ * Reference: NXP AN1206 - TDA19971_TDA19973 receiver HW recommendation: 3.3.4
+ */
+static u32 tda19971_video_formats[] = {
+ /* 24bit RGB444: 1 pixel in 1x24bit sample: VP[23:0] */
+ MEDIA_BUS_FMT_RGB888_1X24,
+ /* 24bit YUV444: 1 pixel in 1x24bit sample: VP[23:0] */
+ MEDIA_BUS_FMT_YUV8_1X24,
+ /* 24bit YUV422: 1 pixel in 1x24bit sample: VP[23:12]/VP[11:0] */
+ MEDIA_BUS_FMT_UYVY12_1X24,
+ /* 20bit YUV422: 1 pixel in 1x20bit sample: VP[23:14]/VP[11:2] */
+ MEDIA_BUS_FMT_UYVY10_1X20,
+ /* 16bit YUV422: 1 pixel in 1x16bit sample: VP[23:16]/VP[15:8] */
+ MEDIA_BUS_FMT_UYVY8_1X16,
+ /* 12bit CCIR656: 1 pixel in 2x12bit samples: VP[23:12] */
+ MEDIA_BUS_FMT_UYVY12_2X12,
+ /* 10bit CCIR656: 1 pixel in 2x10bit samples: VP[23:14] */
+ MEDIA_BUS_FMT_UYVY10_2X10,
+ /* 8bit CCIR656: 1 pixel in 2x8bit samples: VP[23:16] */
+ MEDIA_BUS_FMT_UYVY8_2X8,
+};
+static u32 tda19973_video_formats[] = {
+ /* 36bit RGB444: 1 pixel in 1x36bit sample on VP[35:0] */
+ MEDIA_BUS_FMT_RGB121212_1X36,
+ /* 36bit YUV444 1 pixel in 1x36bit sample on VP[35:0] */
+ MEDIA_BUS_FMT_YUV12_1X36,
+ /* 24bit YUV422: 1 pixel in 1x24bit sample on VP[35:24]/VP[11:0] */
+ MEDIA_BUS_FMT_UYVY12_1X24,
+ /* 12bit CCIR656: 1 pixel in 2x12bit samples on VP[11:0] */
+ MEDIA_BUS_FMT_UYVY12_2X12,
+};
+
+/*
+ * Colorspace conversion matrices
+ */
+struct color_matrix_coefs {
+ const char *name;
+ /* Input offsets */
+ s16 offint1;
+ s16 offint2;
+ s16 offint3;
+ /* Coeficients */
+ s16 p11coef;
+ s16 p12coef;
+ s16 p13coef;
+ s16 p21coef;
+ s16 p22coef;
+ s16 p23coef;
+ s16 p31coef;
+ s16 p32coef;
+ s16 p33coef;
+ /* Output offsets */
+ s16 offout1;
+ s16 offout2;
+ s16 offout3;
+};
+
+enum {
+ ITU709_RGBFULL,
+ ITU601_RGBFULL,
+ RGBLIMITED_RGBFULL,
+ RGBLIMITED_ITU601,
+ RGBLIMITED_ITU709,
+ RGBFULL_ITU601,
+ RGBFULL_ITU709,
+};
+
+/* NB: 4096 is 1.0 using fixed point numbers */
+static const struct color_matrix_coefs conv_matrix[] = {
+ {
+ "YUV709 -> RGB full",
+ -256, -2048, -2048,
+ 4769, -2183, -873,
+ 4769, 7343, 0,
+ 4769, 0, 8652,
+ 0, 0, 0,
+ },
+ {
+ "YUV601 -> RGB full",
+ -256, -2048, -2048,
+ 4769, -3330, -1602,
+ 4769, 6538, 0,
+ 4769, 0, 8264,
+ 256, 256, 256,
+ },
+ {
+ "RGB limited -> RGB full",
+ -256, -256, -256,
+ 0, 4769, 0,
+ 0, 0, 4769,
+ 4769, 0, 0,
+ 0, 0, 0,
+ },
+ {
+ "RGB limited -> ITU601",
+ -256, -256, -256,
+ 2404, 1225, 467,
+ -1754, 2095, -341,
+ -1388, -707, 2095,
+ 256, 2048, 2048,
+ },
+ {
+ "RGB limited -> ITU709",
+ -256, -256, -256,
+ 2918, 867, 295,
+ -1894, 2087, -190,
+ -1607, -477, 2087,
+ 256, 2048, 2048,
+ },
+ {
+ "RGB full -> ITU601",
+ 0, 0, 0,
+ 2065, 1052, 401,
+ -1506, 1799, -293,
+ -1192, -607, 1799,
+ 256, 2048, 2048,
+ },
+ {
+ "RGB full -> ITU709",
+ 0, 0, 0,
+ 2506, 745, 253,
+ -1627, 1792, -163,
+ -1380, -410, 1792,
+ 256, 2048, 2048,
+ },
+};
+
+static const struct v4l2_dv_timings_cap tda1997x_dv_timings_cap = {
+ .type = V4L2_DV_BT_656_1120,
+ /* keep this initialization for compatibility with GCC < 4.4.6 */
+ .reserved = { 0 },
+
+ V4L2_INIT_BT_TIMINGS(
+ 640, 1920, /* min/max width */
+ 480, 1080, /* min/max height */
+ 13000000, 165000000, /* min/max pixelclock */
+ /* standards */
+ V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
+ V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
+ /* capabilities */
+ V4L2_DV_BT_CAP_INTERLACED | V4L2_DV_BT_CAP_PROGRESSIVE |
+ V4L2_DV_BT_CAP_REDUCED_BLANKING |
+ V4L2_DV_BT_CAP_CUSTOM
+ )
+};
+
+/*
+ * Video Input formats
+ */
+static const struct v4l2_dv_timings tda1997x_hdmi_modes[] = {
+ V4L2_DV_BT_DMT_640X350P85,
+ V4L2_DV_BT_DMT_640X400P85,
+ V4L2_DV_BT_DMT_640X480P60,
+ V4L2_DV_BT_DMT_640X480P72,
+ V4L2_DV_BT_DMT_640X480P75,
+ V4L2_DV_BT_DMT_720X400P85,
+ V4L2_DV_BT_CEA_720X480I59_94,
+ V4L2_DV_BT_CEA_720X480P59_94,
+ V4L2_DV_BT_CEA_720X576I50,
+ V4L2_DV_BT_CEA_720X576P50,
+ V4L2_DV_BT_DMT_800X600P60,
+ V4L2_DV_BT_DMT_800X600P72,
+ V4L2_DV_BT_DMT_800X600P75,
+ V4L2_DV_BT_DMT_800X600P85,
+ V4L2_DV_BT_DMT_1024X768P60,
+ V4L2_DV_BT_DMT_1024X768P70,
+ V4L2_DV_BT_DMT_1024X768P75,
+ V4L2_DV_BT_DMT_1024X768P85,
+ V4L2_DV_BT_CEA_1280X720P24,
+ V4L2_DV_BT_CEA_1280X720P25,
+ V4L2_DV_BT_CEA_1280X720P30,
+ V4L2_DV_BT_CEA_1280X720P50,
+ V4L2_DV_BT_CEA_1280X720P60,
+ V4L2_DV_BT_DMT_1280X768P60_RB,
+ V4L2_DV_BT_DMT_1280X768P75,
+ V4L2_DV_BT_DMT_1280X768P85,
+ V4L2_DV_BT_DMT_1280X960P60,
+ V4L2_DV_BT_DMT_1280X1024P60,
+ V4L2_DV_BT_DMT_1280X1024P85,
+ V4L2_DV_BT_DMT_1280X1024P75,
+ V4L2_DV_BT_DMT_1360X768P60,
+ V4L2_DV_BT_DMT_1440X900P60,
+ V4L2_DV_BT_DMT_1400X1050P60_RB,
+ V4L2_DV_BT_DMT_1400X1050P60,
+ V4L2_DV_BT_DMT_1600X1200P60,
+ V4L2_DV_BT_DMT_1680X1050P60_RB,
+ V4L2_DV_BT_CEA_1920X1080P24,
+ V4L2_DV_BT_CEA_1920X1080P25,
+ V4L2_DV_BT_CEA_1920X1080P30,
+ V4L2_DV_BT_CEA_1920X1080I50,
+ V4L2_DV_BT_CEA_1920X1080P50,
+ V4L2_DV_BT_CEA_1920X1080I60,
+ V4L2_DV_BT_CEA_1920X1080P60,
+ V4L2_DV_BT_DMT_1920X1200P60_RB,
+};
+
+/* regulator supplies */
+static const char * const tda1997x_supply_name[] = {
+ "DOVDD", /* Digital I/O supply */
+ "DVDD", /* Digital Core supply */
+ "AVDD", /* Analog supply */
+};
+
+#define TDA1997X_NUM_SUPPLIES ARRAY_SIZE(tda1997x_supply_name)
+
+enum tda1997x_type {
+ TDA19971,
+ TDA19973,
+};
+
+enum tda1997x_hdmi_pads {
+ TDA1997X_PAD_SOURCE,
+ TDA1997X_NUM_PADS,
+};
+
+struct tda1997x_chip_info {
+ enum tda1997x_type type;
+ const char *name;
+ const u32 *formats;
+ unsigned int nformats;
+};
+
+struct tda1997x_state {
+ const struct tda1997x_chip_info *info;
+ struct tda1997x_platform_data pdata;
+ struct i2c_client *client;
+ struct i2c_client *client_cec;
+ struct v4l2_subdev sd;
+ struct regulator_bulk_data supplies[TDA1997X_NUM_SUPPLIES];
+ struct media_pad pads[TDA1997X_NUM_PADS];
+ struct mutex lock;
+ struct mutex page_lock;
+ char page;
+
+ /* detected info from chip */
+ int chip_revision;
+ char port_30bit;
+ char output_2p5;
+ char tmdsb_clk;
+ char tmdsb_soc;
+
+ /* status info */
+ char hdmi_status;
+ char mptrw_in_progress;
+ char state_c5_reached;
+ char activity_status;
+ char input_detect[2];
+
+ /* video */
+ struct hdmi_avi_infoframe avi_infoframe;
+ struct v4l2_hdmi_colorimetry colorimetry;
+ u32 rgb_quantization_range;
+ struct v4l2_dv_timings timings;
+ const struct v4l2_dv_timings *detected_timings;
+ int fps;
+ const struct color_matrix_coefs *conv;
+ u32 code;
+ enum v4l2_mbus_type bus_type;
+ u8 vid_fmt;
+
+ /* controls */
+ struct v4l2_ctrl_handler hdl;
+ struct v4l2_ctrl *detect_tx_5v_ctrl;
+ struct v4l2_ctrl *rgb_quantization_range_ctrl;
+
+ /* audio */
+ u8 audio_ch_alloc;
+ int audio_samplerate;
+ int audio_channels;
+ int audio_samplesize;
+ int audio_type;
+ struct mutex audio_lock;
+ struct snd_pcm_substream *audio_stream;
+
+ /* EDID */
+ struct {
+ u8 edid[256];
+ u32 present;
+ unsigned int blocks;
+ } edid;
+ struct delayed_work delayed_work_enable_hpd;
+};
+
+static const struct v4l2_event tda1997x_ev_fmt = {
+ .type = V4L2_EVENT_SOURCE_CHANGE,
+ .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
+};
+
+static const struct tda1997x_chip_info tda1997x_chip_info[] = {
+ [TDA19971] = {
+ .type = TDA19971,
+ .name = "tda19971",
+ .formats = tda19971_video_formats,
+ .nformats = ARRAY_SIZE(tda19971_video_formats),
+ },
+ [TDA19973] = {
+ .type = TDA19973,
+ .name = "tda19973",
+ .formats = tda19973_video_formats,
+ .nformats = ARRAY_SIZE(tda19973_video_formats),
+ },
+};
+
+static inline struct tda1997x_state *to_state(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct tda1997x_state, sd);
+}
+
+static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
+{
+ return &container_of(ctrl->handler, struct tda1997x_state, hdl)->sd;
+}
+
+static int tda1997x_cec_read(struct v4l2_subdev *sd, u8 reg)
+{
+ struct tda1997x_state *state = to_state(sd);
+ int val;
+
+ val = i2c_smbus_read_byte_data(state->client_cec, reg);
+ if (val < 0) {
+ v4l_err(state->client, "read reg error: reg=%2x\n", reg);
+ val = -1;
+ }
+
+ return val;
+}
+
+static int tda1997x_cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
+{
+ struct tda1997x_state *state = to_state(sd);
+ int ret = 0;
+
+ ret = i2c_smbus_write_byte_data(state->client_cec, reg, val);
+ if (ret < 0) {
+ v4l_err(state->client, "write reg error:reg=%2x,val=%2x\n",
+ reg, val);
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/* -----------------------------------------------------------------------------
+ * I2C transfer
+ */
+
+static int tda1997x_setpage(struct v4l2_subdev *sd, u8 page)
+{
+ struct tda1997x_state *state = to_state(sd);
+ int ret;
+
+ if (state->page != page) {
+ ret = i2c_smbus_write_byte_data(state->client,
+ REG_CURPAGE_00H, page);
+ if (ret < 0) {
+ v4l_err(state->client,
+ "write reg error:reg=%2x,val=%2x\n",
+ REG_CURPAGE_00H, page);
+ return ret;
+ }
+ state->page = page;
+ }
+ return 0;
+}
+
+static inline int io_read(struct v4l2_subdev *sd, u16 reg)
+{
+ struct tda1997x_state *state = to_state(sd);
+ int val;
+
+ mutex_lock(&state->page_lock);
+ if (tda1997x_setpage(sd, reg >> 8)) {
+ val = -1;
+ goto out;
+ }
+
+ val = i2c_smbus_read_byte_data(state->client, reg&0xff);
+ if (val < 0) {
+ v4l_err(state->client, "read reg error: reg=%2x\n", reg & 0xff);
+ val = -1;
+ goto out;
+ }
+
+out:
+ mutex_unlock(&state->page_lock);
+ return val;
+}
+
+static inline long io_read16(struct v4l2_subdev *sd, u16 reg)
+{
+ u8 val;
+ long lval = 0;
+
+ val = io_read(sd, reg);
+ if (val < 0)
+ return val;
+ lval |= (val << 8);
+ val = io_read(sd, reg + 1);
+ if (val < 0)
+ return val;
+ lval |= val;
+
+ return lval;
+}
+
+static inline long io_read24(struct v4l2_subdev *sd, u16 reg)
+{
+ u8 val;
+ long lval = 0;
+
+ val = io_read(sd, reg);
+ if (val < 0)
+ return val;
+ lval |= (val << 16);
+ val = io_read(sd, reg + 1);
+ if (val < 0)
+ return val;
+ lval |= (val << 8);
+ val = io_read(sd, reg + 2);
+ if (val < 0)
+ return val;
+ lval |= val;
+
+ return lval;
+}
+
+static unsigned int io_readn(struct v4l2_subdev *sd, u16 reg, u8 len, u8 *data)
+{
+ int i;
+ int sz = 0;
+ u8 val;
+
+ for (i = 0; i < len; i++) {
+ val = io_read(sd, reg + i);
+ if (val < 0)
+ break;
+ data[i] = val;
+ sz++;
+ }
+
+ return sz;
+}
+
+static int io_write(struct v4l2_subdev *sd, u16 reg, u8 val)
+{
+ struct tda1997x_state *state = to_state(sd);
+ s32 ret = 0;
+
+ mutex_lock(&state->page_lock);
+ if (tda1997x_setpage(sd, reg >> 8)) {
+ ret = -1;
+ goto out;
+ }
+
+ ret = i2c_smbus_write_byte_data(state->client, reg & 0xff, val);
+ if (ret < 0) {
+ v4l_err(state->client, "write reg error:reg=%2x,val=%2x\n",
+ reg&0xff, val);
+ ret = -1;
+ goto out;
+ }
+
+out:
+ mutex_unlock(&state->page_lock);
+ return ret;
+}
+
+static int io_write16(struct v4l2_subdev *sd, u16 reg, u16 val)
+{
+ int ret;
+
+ ret = io_write(sd, reg, (val >> 8) & 0xff);
+ if (ret < 0)
+ return ret;
+ ret = io_write(sd, reg + 1, val & 0xff);
+ if (ret < 0)
+ return ret;
+ return 0;
+}
+
+static int io_write24(struct v4l2_subdev *sd, u16 reg, u32 val)
+{
+ int ret;
+
+ ret = io_write(sd, reg, (val >> 16) & 0xff);
+ if (ret < 0)
+ return ret;
+ ret = io_write(sd, reg + 1, (val >> 8) & 0xff);
+ if (ret < 0)
+ return ret;
+ ret = io_write(sd, reg + 2, val & 0xff);
+ if (ret < 0)
+ return ret;
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * Hotplug
+ */
+
+enum hpd_mode {
+ HPD_LOW_BP, /* HPD low and pulse of at least 100ms */
+ HPD_LOW_OTHER, /* HPD low and pulse of at least 100ms */
+ HPD_HIGH_BP, /* HIGH */
+ HPD_HIGH_OTHER,
+ HPD_PULSE, /* HPD low pulse */
+};
+
+/* manual HPD (Hot Plug Detect) control */
+static int tda1997x_manual_hpd(struct v4l2_subdev *sd, enum hpd_mode mode)
+{
+ u8 hpd_auto, hpd_pwr, hpd_man;
+
+ hpd_auto = io_read(sd, REG_HPD_AUTO_CTRL);
+ hpd_pwr = io_read(sd, REG_HPD_POWER);
+ hpd_man = io_read(sd, REG_HPD_MAN_CTRL);
+
+ /* mask out unused bits */
+ hpd_man &= (HPD_MAN_CTRL_HPD_PULSE |
+ HPD_MAN_CTRL_5VEN |
+ HPD_MAN_CTRL_HPD_B |
+ HPD_MAN_CTRL_HPD_A);
+
+ switch (mode) {
+ /* HPD low and pulse of at least 100ms */
+ case HPD_LOW_BP:
+ /* hpd_bp=0 */
+ hpd_pwr &= ~HPD_POWER_BP_MASK;
+ /* disable HPD_A and HPD_B */
+ hpd_man &= ~(HPD_MAN_CTRL_HPD_A | HPD_MAN_CTRL_HPD_B);
+ io_write(sd, REG_HPD_POWER, hpd_pwr);
+ io_write(sd, REG_HPD_MAN_CTRL, hpd_man);
+ break;
+ /* HPD high */
+ case HPD_HIGH_BP:
+ /* hpd_bp=1 */
+ hpd_pwr &= ~HPD_POWER_BP_MASK;
+ hpd_pwr |= 1 << HPD_POWER_BP_SHIFT;
+ io_write(sd, REG_HPD_POWER, hpd_pwr);
+ break;
+ /* HPD low and pulse of at least 100ms */
+ case HPD_LOW_OTHER:
+ /* disable HPD_A and HPD_B */
+ hpd_man &= ~(HPD_MAN_CTRL_HPD_A | HPD_MAN_CTRL_HPD_B);
+ /* hp_other=0 */
+ hpd_auto &= ~HPD_AUTO_HP_OTHER;
+ io_write(sd, REG_HPD_AUTO_CTRL, hpd_auto);
+ io_write(sd, REG_HPD_MAN_CTRL, hpd_man);
+ break;
+ /* HPD high */
+ case HPD_HIGH_OTHER:
+ hpd_auto |= HPD_AUTO_HP_OTHER;
+ io_write(sd, REG_HPD_AUTO_CTRL, hpd_auto);
+ break;
+ /* HPD low pulse */
+ case HPD_PULSE:
+ /* disable HPD_A and HPD_B */
+ hpd_man &= ~(HPD_MAN_CTRL_HPD_A | HPD_MAN_CTRL_HPD_B);
+ io_write(sd, REG_HPD_MAN_CTRL, hpd_man);
+ break;
+ }
+
+ return 0;
+}
+
+static void tda1997x_delayed_work_enable_hpd(struct work_struct *work)
+{
+ struct delayed_work *dwork = to_delayed_work(work);
+ struct tda1997x_state *state = container_of(dwork,
+ struct tda1997x_state,
+ delayed_work_enable_hpd);
+ struct v4l2_subdev *sd = &state->sd;
+
+ v4l2_dbg(2, debug, sd, "%s:\n", __func__);
+
+ /* Set HPD high */
+ tda1997x_manual_hpd(sd, HPD_HIGH_OTHER);
+ tda1997x_manual_hpd(sd, HPD_HIGH_BP);
+
+ state->edid.present = 1;
+}
+
+static void tda1997x_disable_edid(struct v4l2_subdev *sd)
+{
+ struct tda1997x_state *state = to_state(sd);
+
+ v4l2_dbg(1, debug, sd, "%s\n", __func__);
+ cancel_delayed_work_sync(&state->delayed_work_enable_hpd);
+
+ /* Set HPD low */
+ tda1997x_manual_hpd(sd, HPD_LOW_BP);
+}
+
+static void tda1997x_enable_edid(struct v4l2_subdev *sd)
+{
+ struct tda1997x_state *state = to_state(sd);
+
+ v4l2_dbg(1, debug, sd, "%s\n", __func__);
+
+ /* Enable hotplug after 100ms */
+ schedule_delayed_work(&state->delayed_work_enable_hpd, HZ / 10);
+}
+
+/* -----------------------------------------------------------------------------
+ * Signal Control
+ */
+
+/*
+ * The color conversion matrix will convert between the colorimetry of the
+ * HDMI input to the desired output format RGB|YUV. RGB output is to be
+ * full-range and YUV is to be limited range.
+ *
+ * RGB full-range uses values from 0 to 255 which is recommended on a monitor
+ * and RGB Limited uses values from 16 to 236 (16=black, 235=white) which is
+ * typically recommended on a TV.
+ */
+static int
+tda1997x_configure_csc(struct v4l2_subdev *sd)
+{
+ struct tda1997x_state *state = to_state(sd);
+ struct hdmi_avi_infoframe *avi = &state->avi_infoframe;
+ struct v4l2_hdmi_colorimetry *c = &state->colorimetry;
+ /* Blanking code values depend on output colorspace (RGB or YUV) */
+ struct blanking_codes {
+ s16 code_gy;
+ s16 code_bu;
+ s16 code_rv;
+ };
+ static const struct blanking_codes rgb_blanking = { 64, 64, 64 };
+ static const struct blanking_codes yuv_blanking = { 64, 512, 512 };
+ const struct blanking_codes *blanking_codes = NULL;
+ u8 reg;
+
+ v4l_dbg(1, debug, state->client, "input:%s quant:%s output:%s\n",
+ hdmi_colorspace_names[avi->colorspace],
+ v4l2_quantization_names[c->quantization],
+ vidfmt_names[state->vid_fmt]);
+ state->conv = NULL;
+ switch (state->vid_fmt) {
+ /* RGB output */
+ case OF_FMT_444:
+ blanking_codes = &rgb_blanking;
+ if (c->colorspace == V4L2_COLORSPACE_SRGB) {
+ if (c->quantization == V4L2_QUANTIZATION_LIM_RANGE)
+ state->conv = &conv_matrix[RGBLIMITED_RGBFULL];
+ } else {
+ if (c->colorspace == V4L2_COLORSPACE_REC709)
+ state->conv = &conv_matrix[ITU709_RGBFULL];
+ else if (c->colorspace == V4L2_COLORSPACE_SMPTE170M)
+ state->conv = &conv_matrix[ITU601_RGBFULL];
+ }
+ break;
+
+ /* YUV output */
+ case OF_FMT_422_SMPT: /* semi-planar */
+ case OF_FMT_422_CCIR: /* CCIR656 */
+ blanking_codes = &yuv_blanking;
+ if ((c->colorspace == V4L2_COLORSPACE_SRGB) &&
+ (c->quantization == V4L2_QUANTIZATION_FULL_RANGE)) {
+ if (state->timings.bt.height <= 576)
+ state->conv = &conv_matrix[RGBFULL_ITU601];
+ else
+ state->conv = &conv_matrix[RGBFULL_ITU709];
+ } else if ((c->colorspace == V4L2_COLORSPACE_SRGB) &&
+ (c->quantization == V4L2_QUANTIZATION_LIM_RANGE)) {
+ if (state->timings.bt.height <= 576)
+ state->conv = &conv_matrix[RGBLIMITED_ITU601];
+ else
+ state->conv = &conv_matrix[RGBLIMITED_ITU709];
+ }
+ break;
+ }
+
+ if (state->conv) {
+ v4l_dbg(1, debug, state->client, "%s\n",
+ state->conv->name);
+ /* enable matrix conversion */
+ reg = io_read(sd, REG_VDP_CTRL);
+ reg &= ~VDP_CTRL_MATRIX_BP;
+ io_write(sd, REG_VDP_CTRL, reg);
+ /* offset inputs */
+ io_write16(sd, REG_VDP_MATRIX + 0, state->conv->offint1);
+ io_write16(sd, REG_VDP_MATRIX + 2, state->conv->offint2);
+ io_write16(sd, REG_VDP_MATRIX + 4, state->conv->offint3);
+ /* coefficients */
+ io_write16(sd, REG_VDP_MATRIX + 6, state->conv->p11coef);
+ io_write16(sd, REG_VDP_MATRIX + 8, state->conv->p12coef);
+ io_write16(sd, REG_VDP_MATRIX + 10, state->conv->p13coef);
+ io_write16(sd, REG_VDP_MATRIX + 12, state->conv->p21coef);
+ io_write16(sd, REG_VDP_MATRIX + 14, state->conv->p22coef);
+ io_write16(sd, REG_VDP_MATRIX + 16, state->conv->p23coef);
+ io_write16(sd, REG_VDP_MATRIX + 18, state->conv->p31coef);
+ io_write16(sd, REG_VDP_MATRIX + 20, state->conv->p32coef);
+ io_write16(sd, REG_VDP_MATRIX + 22, state->conv->p33coef);
+ /* offset outputs */
+ io_write16(sd, REG_VDP_MATRIX + 24, state->conv->offout1);
+ io_write16(sd, REG_VDP_MATRIX + 26, state->conv->offout2);
+ io_write16(sd, REG_VDP_MATRIX + 28, state->conv->offout3);
+ } else {
+ /* disable matrix conversion */
+ reg = io_read(sd, REG_VDP_CTRL);
+ reg |= VDP_CTRL_MATRIX_BP;
+ io_write(sd, REG_VDP_CTRL, reg);
+ }
+
+ /* SetBlankingCodes */
+ if (blanking_codes) {
+ io_write16(sd, REG_BLK_GY, blanking_codes->code_gy);
+ io_write16(sd, REG_BLK_BU, blanking_codes->code_bu);
+ io_write16(sd, REG_BLK_RV, blanking_codes->code_rv);
+ }
+
+ return 0;
+}
+
+/* Configure frame detection window and VHREF timing generator */
+static int
+tda1997x_configure_vhref(struct v4l2_subdev *sd)
+{
+ struct tda1997x_state *state = to_state(sd);
+ const struct v4l2_bt_timings *bt;
+ int width, lines;
+ u16 href_start, href_end;
+ u16 vref_f1_start, vref_f2_start;
+ u8 vref_f1_width, vref_f2_width;
+ u8 field_polarity;
+ u16 fieldref_f1_start, fieldref_f2_start;
+ u8 reg;
+
+ if (!state->detected_timings)
+ return -EINVAL;
+ bt = &state->detected_timings->bt;
+ href_start = bt->hbackporch + bt->hsync + 1;
+ href_end = href_start + bt->width;
+ vref_f1_start = bt->height + bt->vbackporch + bt->vsync +
+ bt->il_vbackporch + bt->il_vsync +
+ bt->il_vfrontporch;
+ vref_f1_width = bt->vbackporch + bt->vsync + bt->vfrontporch;
+ vref_f2_start = 0;
+ vref_f2_width = 0;
+ fieldref_f1_start = 0;
+ fieldref_f2_start = 0;
+ if (bt->interlaced) {
+ vref_f2_start = (bt->height / 2) +
+ (bt->il_vbackporch + bt->il_vsync - 1);
+ vref_f2_width = bt->il_vbackporch + bt->il_vsync +
+ bt->il_vfrontporch;
+ fieldref_f2_start = vref_f2_start + bt->il_vfrontporch +
+ fieldref_f1_start;
+ }
+ field_polarity = 0;
+
+ width = V4L2_DV_BT_FRAME_WIDTH(bt);
+ lines = V4L2_DV_BT_FRAME_HEIGHT(bt);
+
+ /*
+ * Configure Frame Detection Window:
+ * horiz area where the VHREF module consider a VSYNC a new frame
+ */
+ io_write16(sd, REG_FDW_S, 0x2ef); /* start position */
+ io_write16(sd, REG_FDW_E, 0x141); /* end position */
+
+ /* Set Pixel And Line Counters */
+ if (state->chip_revision == 0)
+ io_write16(sd, REG_PXCNT_PR, 4);
+ else
+ io_write16(sd, REG_PXCNT_PR, 1);
+ io_write16(sd, REG_PXCNT_NPIX, width & MASK_VHREF);
+ io_write16(sd, REG_LCNT_PR, 1);
+ io_write16(sd, REG_LCNT_NLIN, lines & MASK_VHREF);
+
+ /*
+ * Configure the VHRef timing generator responsible for rebuilding all
+ * horiz and vert synch and ref signals from its input allowing auto
+ * detection algorithms and forcing predefined modes (480i & 576i)
+ */
+ reg = VHREF_STD_DET_OFF << VHREF_STD_DET_SHIFT;
+ io_write(sd, REG_VHREF_CTRL, reg);
+
+ /*
+ * Configure the VHRef timing values. In case the VHREF generator has
+ * been configured in manual mode, this will allow to manually set all
+ * horiz and vert ref values (non-active pixel areas) of the generator
+ * and allows setting the frame reference params.
+ */
+ /* horizontal reference start/end */
+ io_write16(sd, REG_HREF_S, href_start & MASK_VHREF);
+ io_write16(sd, REG_HREF_E, href_end & MASK_VHREF);
+ /* vertical reference f1 start/end */
+ io_write16(sd, REG_VREF_F1_S, vref_f1_start & MASK_VHREF);
+ io_write(sd, REG_VREF_F1_WIDTH, vref_f1_width);
+ /* vertical reference f2 start/end */
+ io_write16(sd, REG_VREF_F2_S, vref_f2_start & MASK_VHREF);
+ io_write(sd, REG_VREF_F2_WIDTH, vref_f2_width);
+
+ /* F1/F2 FREF, field polarity */
+ reg = fieldref_f1_start & MASK_VHREF;
+ reg |= field_polarity << 8;
+ io_write16(sd, REG_FREF_F1_S, reg);
+ reg = fieldref_f2_start & MASK_VHREF;
+ io_write16(sd, REG_FREF_F2_S, reg);
+
+ return 0;
+}
+
+/* Configure Video Output port signals */
+static int
+tda1997x_configure_vidout(struct tda1997x_state *state)
+{
+ struct v4l2_subdev *sd = &state->sd;
+ struct tda1997x_platform_data *pdata = &state->pdata;
+ u8 prefilter;
+ u8 reg;
+
+ /* Configure pixel clock generator: delay, polarity, rate */
+ reg = (state->vid_fmt == OF_FMT_422_CCIR) ?
+ PCLK_SEL_X2 : PCLK_SEL_X1;
+ reg |= pdata->vidout_delay_pclk << PCLK_DELAY_SHIFT;
+ reg |= pdata->vidout_inv_pclk << PCLK_INV_SHIFT;
+ io_write(sd, REG_PCLK, reg);
+
+ /* Configure pre-filter */
+ prefilter = 0; /* filters off */
+ /* YUV422 mode requires conversion */
+ if ((state->vid_fmt == OF_FMT_422_SMPT)
+ || (state->vid_fmt == OF_FMT_422_CCIR)) {
+ /* 2/7taps for Rv and Bu */
+ prefilter = FILTERS_CTRL_2_7TAP << FILTERS_CTRL_BU_SHIFT |
+ FILTERS_CTRL_2_7TAP << FILTERS_CTRL_RV_SHIFT;
+ }
+ io_write(sd, REG_FILTERS_CTRL, prefilter);
+
+ /* Configure video port */
+ reg = state->vid_fmt & OF_FMT_MASK;
+ if (state->vid_fmt == OF_FMT_422_CCIR)
+ reg |= (OF_BLK | OF_TRC);
+ reg |= OF_VP_ENABLE;
+ io_write(sd, REG_OF, reg);
+
+ /* Configure formatter and conversions */
+ reg = io_read(sd, REG_VDP_CTRL);
+ /* pre-filter is needed unless (REG_FILTERS_CTRL == 0) */
+ if (!prefilter)
+ reg |= VDP_CTRL_PREFILTER_BP;
+ else
+ reg &= ~VDP_CTRL_PREFILTER_BP;
+ /* formatter is needed for YUV422 and for trc/blc codes */
+ if (state->vid_fmt == OF_FMT_444)
+ reg |= VDP_CTRL_FORMATTER_BP;
+ /* formatter and compdel needed for timing/blanking codes */
+ else
+ reg &= ~(VDP_CTRL_FORMATTER_BP | VDP_CTRL_COMPDEL_BP);
+ /* activate compdel for small sync delays */
+ if ((pdata->vidout_delay_vs < 4) || (pdata->vidout_delay_hs < 4))
+ reg &= ~VDP_CTRL_COMPDEL_BP;
+ io_write(sd, REG_VDP_CTRL, reg);
+
+ /* Configure DE output signal: delay, polarity, and source */
+ reg = pdata->vidout_delay_de << DE_FREF_DELAY_SHIFT |
+ pdata->vidout_inv_de << DE_FREF_INV_SHIFT |
+ pdata->vidout_sel_de << DE_FREF_SEL_SHIFT;
+ io_write(sd, REG_DE_FREF, reg);
+
+ /* Configure HS/HREF output signal: delay, polarity, and source */
+ if (state->vid_fmt != OF_FMT_422_CCIR) {
+ reg = pdata->vidout_delay_hs << HS_HREF_DELAY_SHIFT |
+ pdata->vidout_inv_hs << HS_HREF_INV_SHIFT |
+ pdata->vidout_sel_hs << HS_HREF_SEL_SHIFT;
+ } else
+ reg = HS_HREF_SEL_NONE << HS_HREF_SEL_SHIFT;
+ io_write(sd, REG_HS_HREF, reg);
+
+ /* Configure VS/VREF output signal: delay, polarity, and source */
+ if (state->vid_fmt != OF_FMT_422_CCIR) {
+ reg = pdata->vidout_delay_vs << VS_VREF_DELAY_SHIFT |
+ pdata->vidout_inv_vs << VS_VREF_INV_SHIFT |
+ pdata->vidout_sel_vs << VS_VREF_SEL_SHIFT;
+ } else
+ reg = VS_VREF_SEL_NONE << VS_VREF_SEL_SHIFT;
+ io_write(sd, REG_VS_VREF, reg);
+
+ return 0;
+}
+
+/* Configure Audio output port signals */
+static int
+tda1997x_configure_audout(struct v4l2_subdev *sd, u8 channel_assignment)
+{
+ struct tda1997x_state *state = to_state(sd);
+ struct tda1997x_platform_data *pdata = &state->pdata;
+ bool sp_used_by_fifo = 1;
+ u8 reg;
+
+ if (!pdata->audout_format)
+ return 0;
+
+ /* channel assignment (CEA-861-D Table 20) */
+ io_write(sd, REG_AUDIO_PATH, channel_assignment);
+
+ /* Audio output configuration */
+ reg = 0;
+ switch (pdata->audout_format) {
+ case AUDFMT_TYPE_I2S:
+ reg |= AUDCFG_BUS_I2S << AUDCFG_BUS_SHIFT;
+ break;
+ case AUDFMT_TYPE_SPDIF:
+ reg |= AUDCFG_BUS_SPDIF << AUDCFG_BUS_SHIFT;
+ break;
+ }
+ switch (state->audio_type) {
+ case AUDCFG_TYPE_PCM:
+ reg |= AUDCFG_TYPE_PCM << AUDCFG_TYPE_SHIFT;
+ break;
+ case AUDCFG_TYPE_OBA:
+ reg |= AUDCFG_TYPE_OBA << AUDCFG_TYPE_SHIFT;
+ break;
+ case AUDCFG_TYPE_DST:
+ reg |= AUDCFG_TYPE_DST << AUDCFG_TYPE_SHIFT;
+ sp_used_by_fifo = 0;
+ break;
+ case AUDCFG_TYPE_HBR:
+ reg |= AUDCFG_TYPE_HBR << AUDCFG_TYPE_SHIFT;
+ if (pdata->audout_layout == 1) {
+ /* demuxed via AP0:AP3 */
+ reg |= AUDCFG_HBR_DEMUX << AUDCFG_HBR_SHIFT;
+ if (pdata->audout_format == AUDFMT_TYPE_SPDIF)
+ sp_used_by_fifo = 0;
+ } else {
+ /* straight via AP0 */
+ reg |= AUDCFG_HBR_STRAIGHT << AUDCFG_HBR_SHIFT;
+ }
+ break;
+ }
+ if (pdata->audout_width == 32)
+ reg |= AUDCFG_I2SW_32 << AUDCFG_I2SW_SHIFT;
+ else
+ reg |= AUDCFG_I2SW_16 << AUDCFG_I2SW_SHIFT;
+
+ /* automatic hardware mute */
+ if (pdata->audio_auto_mute)
+ reg |= AUDCFG_AUTO_MUTE_EN;
+ /* clock polarity */
+ if (pdata->audout_invert_clk)
+ reg |= AUDCFG_CLK_INVERT;
+ io_write(sd, REG_AUDCFG, reg);
+
+ /* audio layout */
+ reg = (pdata->audout_layout) ? AUDIO_LAYOUT_LAYOUT1 : 0;
+ if (!pdata->audout_layoutauto)
+ reg |= AUDIO_LAYOUT_MANUAL;
+ if (sp_used_by_fifo)
+ reg |= AUDIO_LAYOUT_SP_FLAG;
+ io_write(sd, REG_AUDIO_LAYOUT, reg);
+
+ /* FIFO Latency value */
+ io_write(sd, REG_FIFO_LATENCY_VAL, 0x80);
+
+ /* Audio output port config */
+ if (sp_used_by_fifo) {
+ reg = AUDIO_OUT_ENABLE_AP0;
+ if (channel_assignment >= 0x01)
+ reg |= AUDIO_OUT_ENABLE_AP1;
+ if (channel_assignment >= 0x04)
+ reg |= AUDIO_OUT_ENABLE_AP2;
+ if (channel_assignment >= 0x0c)
+ reg |= AUDIO_OUT_ENABLE_AP3;
+ /* specific cases where AP1 is not used */
+ if ((channel_assignment == 0x04)
+ || (channel_assignment == 0x08)
+ || (channel_assignment == 0x0c)
+ || (channel_assignment == 0x10)
+ || (channel_assignment == 0x14)
+ || (channel_assignment == 0x18)
+ || (channel_assignment == 0x1c))
+ reg &= ~AUDIO_OUT_ENABLE_AP1;
+ /* specific cases where AP2 is not used */
+ if ((channel_assignment >= 0x14)
+ && (channel_assignment <= 0x17))
+ reg &= ~AUDIO_OUT_ENABLE_AP2;
+ } else {
+ reg = AUDIO_OUT_ENABLE_AP3 |
+ AUDIO_OUT_ENABLE_AP2 |
+ AUDIO_OUT_ENABLE_AP1 |
+ AUDIO_OUT_ENABLE_AP0;
+ }
+ if (pdata->audout_format == AUDFMT_TYPE_I2S)
+ reg |= (AUDIO_OUT_ENABLE_ACLK | AUDIO_OUT_ENABLE_WS);
+ io_write(sd, REG_AUDIO_OUT_ENABLE, reg);
+
+ /* reset test mode to normal audio freq auto selection */
+ io_write(sd, REG_TEST_MODE, 0x00);
+
+ return 0;
+}
+
+/* Soft Reset of specific hdmi info */
+static int
+tda1997x_hdmi_info_reset(struct v4l2_subdev *sd, u8 info_rst, bool reset_sus)
+{
+ u8 reg;
+
+ /* reset infoframe engine packets */
+ reg = io_read(sd, REG_HDMI_INFO_RST);
+ io_write(sd, REG_HDMI_INFO_RST, info_rst);
+
+ /* if infoframe engine has been reset clear INT_FLG_MODE */
+ if (reg & RESET_IF) {
+ reg = io_read(sd, REG_INT_FLG_CLR_MODE);
+ io_write(sd, REG_INT_FLG_CLR_MODE, reg);
+ }
+
+ /* Disable REFTIM to restart start-up-sequencer (SUS) */
+ reg = io_read(sd, REG_RATE_CTRL);
+ reg &= ~RATE_REFTIM_ENABLE;
+ if (!reset_sus)
+ reg |= RATE_REFTIM_ENABLE;
+ reg = io_write(sd, REG_RATE_CTRL, reg);
+
+ return 0;
+}
+
+static void
+tda1997x_power_mode(struct tda1997x_state *state, bool enable)
+{
+ struct v4l2_subdev *sd = &state->sd;
+ u8 reg;
+
+ if (enable) {
+ /* Automatic control of TMDS */
+ io_write(sd, REG_PON_OVR_EN, PON_DIS);
+ /* Enable current bias unit */
+ io_write(sd, REG_CFG1, PON_EN);
+ /* Enable deep color PLL */
+ io_write(sd, REG_DEEP_PLL7_BYP, PON_DIS);
+ /* Output buffers active */
+ reg = io_read(sd, REG_OF);
+ reg &= ~OF_VP_ENABLE;
+ io_write(sd, REG_OF, reg);
+ } else {
+ /* Power down EDID mode sequence */
+ /* Output buffers in HiZ */
+ reg = io_read(sd, REG_OF);
+ reg |= OF_VP_ENABLE;
+ io_write(sd, REG_OF, reg);
+ /* Disable deep color PLL */
+ io_write(sd, REG_DEEP_PLL7_BYP, PON_EN);
+ /* Disable current bias unit */
+ io_write(sd, REG_CFG1, PON_DIS);
+ /* Manual control of TMDS */
+ io_write(sd, REG_PON_OVR_EN, PON_EN);
+ }
+}
+
+static bool
+tda1997x_detect_tx_5v(struct v4l2_subdev *sd)
+{
+ u8 reg = io_read(sd, REG_DETECT_5V);
+
+ return ((reg & DETECT_5V_SEL) ? 1 : 0);
+}
+
+static bool
+tda1997x_detect_tx_hpd(struct v4l2_subdev *sd)
+{
+ u8 reg = io_read(sd, REG_DETECT_5V);
+
+ return ((reg & DETECT_HPD) ? 1 : 0);
+}
+
+static int
+tda1997x_detect_std(struct tda1997x_state *state)
+{
+ struct v4l2_subdev *sd = &state->sd;
+ u32 vper;
+ u16 hper;
+ u16 hsper;
+ int i;
+
+ /*
+ * Read the FMT registers
+ * REG_V_PER: Period of a frame (or two fields) in MCLK(27MHz) cycles
+ * REG_H_PER: Period of a line in MCLK(27MHz) cycles
+ * REG_HS_WIDTH: Period of horiz sync pulse in MCLK(27MHz) cycles
+ */
+ vper = io_read24(sd, REG_V_PER) & MASK_VPER;
+ hper = io_read16(sd, REG_H_PER) & MASK_HPER;
+ hsper = io_read16(sd, REG_HS_WIDTH) & MASK_HSWIDTH;
+ if (!vper || !hper || !hsper)
+ return -ENOLINK;
+ v4l2_dbg(1, debug, sd, "Signal Timings: %u/%u/%u\n", vper, hper, hsper);
+
+ /* look for matching timings */
+ for (i = 0; i < ARRAY_SIZE(tda1997x_hdmi_modes); i++) {
+ const struct v4l2_bt_timings *bt = &tda1997x_hdmi_modes[i].bt;
+ u32 lines, width, _hper, _hsper;
+ u32 vmin, vmax, hmin, hmax, hsmin, hsmax;
+ bool vmatch, hmatch, hsmatch;
+
+ width = V4L2_DV_BT_FRAME_WIDTH(bt);
+ lines = V4L2_DV_BT_FRAME_HEIGHT(bt);
+ _hper = (u32)bt->pixelclock / width;
+ if (bt->interlaced)
+ lines /= 2;
+ /* vper +/- 0.7% */
+ vmin = ((27000000 / 1000) * 993) / _hper * lines;
+ vmax = ((27000000 / 1000) * 1007) / _hper * lines;
+ /* hper +/- 1.0% */
+ hmin = ((27000000 / 100) * 99) / _hper;
+ hmax = ((27000000 / 100) * 101) / _hper;
+ /* hsper +/- 2 (take care to avoid 32bit overflow) */
+ _hsper = 27000 * bt->hsync / ((u32)bt->pixelclock/1000);
+ hsmin = _hsper - 2;
+ hsmax = _hsper + 2;
+
+ /* vmatch matches the framerate */
+ vmatch = ((vper <= vmax) && (vper >= vmin)) ? 1 : 0;
+ /* hmatch matches the width */
+ hmatch = ((hper <= hmax) && (hper >= hmin)) ? 1 : 0;
+ /* hsmatch matches the hswidth */
+ hsmatch = ((hsper <= hsmax) && (hsper >= hsmin)) ? 1 : 0;
+ if (hmatch && vmatch && hsmatch) {
+ state->detected_timings = &tda1997x_hdmi_modes[i];
+ v4l2_print_dv_timings(sd->name, "Detected format: ",
+ state->detected_timings, false);
+ return 0;
+ }
+ }
+
+ v4l_err(state->client, "no resolution match for timings: %d/%d/%d\n",
+ vper, hper, hsper);
+ return -EINVAL;
+}
+
+/* some sort of errata workaround for chip revision 0 (N1) */
+static void tda1997x_reset_n1(struct tda1997x_state *state)
+{
+ struct v4l2_subdev *sd = &state->sd;
+ u8 reg;
+
+ /* clear HDMI mode flag in BCAPS */
+ io_write(sd, REG_CLK_CFG, CLK_CFG_SEL_ACLK_EN | CLK_CFG_SEL_ACLK);
+ io_write(sd, REG_PON_OVR_EN, PON_EN);
+ io_write(sd, REG_PON_CBIAS, PON_EN);
+ io_write(sd, REG_PON_PLL, PON_EN);
+
+ reg = io_read(sd, REG_MODE_REC_CFG1);
+ reg &= ~0x06;
+ reg |= 0x02;
+ io_write(sd, REG_MODE_REC_CFG1, reg);
+ io_write(sd, REG_CLK_CFG, CLK_CFG_DIS);
+ io_write(sd, REG_PON_OVR_EN, PON_DIS);
+ reg = io_read(sd, REG_MODE_REC_CFG1);
+ reg &= ~0x06;
+ io_write(sd, REG_MODE_REC_CFG1, reg);
+}
+
+/*
+ * Activity detection must only be notified when stable_clk_x AND active_x
+ * bits are set to 1. If only stable_clk_x bit is set to 1 but not
+ * active_x, it means that the TMDS clock is not in the defined range
+ * and activity detection must not be notified.
+ */
+static u8
+tda1997x_read_activity_status_regs(struct v4l2_subdev *sd)
+{
+ u8 reg, status = 0;
+
+ /* Read CLK_A_STATUS register */
+ reg = io_read(sd, REG_CLK_A_STATUS);
+ /* when stable_clk_x is set to 1, check active_x bit */
+ if ((reg & MASK_CLK_STABLE) && !(reg & MASK_CLK_ACTIVE))
+ reg &= ~MASK_CLK_STABLE;
+ status |= ((reg & MASK_CLK_STABLE) >> 2);
+
+ /* Read CLK_B_STATUS register */
+ reg = io_read(sd, REG_CLK_B_STATUS);
+ /* when stable_clk_x is set to 1, check active_x bit */
+ if ((reg & MASK_CLK_STABLE) && !(reg & MASK_CLK_ACTIVE))
+ reg &= ~MASK_CLK_STABLE;
+ status |= ((reg & MASK_CLK_STABLE) >> 1);
+
+ /* Read the SUS_STATUS register */
+ reg = io_read(sd, REG_SUS_STATUS);
+
+ /* If state = 5 => TMDS is locked */
+ if ((reg & MASK_SUS_STATUS) == LAST_STATE_REACHED)
+ status |= MASK_SUS_STATE;
+ else
+ status &= ~MASK_SUS_STATE;
+
+ return status;
+}
+
+/* parse an infoframe and do some sanity checks on it */
+static unsigned int
+tda1997x_parse_infoframe(struct tda1997x_state *state, u16 addr)
+{
+ struct v4l2_subdev *sd = &state->sd;
+ struct v4l2_hdmi_colorimetry *c = &state->colorimetry;
+ union hdmi_infoframe frame;
+ u8 buffer[40];
+ u8 reg;
+ int len, err;
+
+ /* read data */
+ len = io_readn(sd, addr, sizeof(buffer), buffer);
+ err = hdmi_infoframe_unpack(&frame, buffer);
+ if (err) {
+ v4l_err(state->client,
+ "failed parsing %d byte infoframe: 0x%04x/0x%02x\n",
+ len, addr, buffer[0]);
+ return err;
+ }
+ hdmi_infoframe_log(KERN_INFO, &state->client->dev, &frame);
+ switch (frame.any.type) {
+ /* Audio InfoFrame: see HDMI spec 8.2.2 */
+ case HDMI_INFOFRAME_TYPE_AUDIO:
+ /* sample rate */
+ switch (frame.audio.sample_frequency) {
+ case HDMI_AUDIO_SAMPLE_FREQUENCY_32000:
+ state->audio_samplerate = 32000;
+ break;
+ case HDMI_AUDIO_SAMPLE_FREQUENCY_44100:
+ state->audio_samplerate = 44100;
+ break;
+ case HDMI_AUDIO_SAMPLE_FREQUENCY_48000:
+ state->audio_samplerate = 48000;
+ break;
+ case HDMI_AUDIO_SAMPLE_FREQUENCY_88200:
+ state->audio_samplerate = 88200;
+ break;
+ case HDMI_AUDIO_SAMPLE_FREQUENCY_96000:
+ state->audio_samplerate = 96000;
+ break;
+ case HDMI_AUDIO_SAMPLE_FREQUENCY_176400:
+ state->audio_samplerate = 176400;
+ break;
+ case HDMI_AUDIO_SAMPLE_FREQUENCY_192000:
+ state->audio_samplerate = 192000;
+ break;
+ default:
+ case HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM:
+ break;
+ }
+
+ /* sample size */
+ switch (frame.audio.sample_size) {
+ case HDMI_AUDIO_SAMPLE_SIZE_16:
+ state->audio_samplesize = 16;
+ break;
+ case HDMI_AUDIO_SAMPLE_SIZE_20:
+ state->audio_samplesize = 20;
+ break;
+ case HDMI_AUDIO_SAMPLE_SIZE_24:
+ state->audio_samplesize = 24;
+ break;
+ case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
+ default:
+ break;
+ }
+
+ /* Channel Count */
+ state->audio_channels = frame.audio.channels;
+ if (frame.audio.channel_allocation &&
+ frame.audio.channel_allocation != state->audio_ch_alloc) {
+ /* use the channel assignment from the infoframe */
+ state->audio_ch_alloc = frame.audio.channel_allocation;
+ tda1997x_configure_audout(sd, state->audio_ch_alloc);
+ /* reset the audio FIFO */
+ tda1997x_hdmi_info_reset(sd, RESET_AUDIO, false);
+ }
+ break;
+
+ /* Auxiliary Video information (AVI) InfoFrame: see HDMI spec 8.2.1 */
+ case HDMI_INFOFRAME_TYPE_AVI:
+ state->avi_infoframe = frame.avi;
+ state->colorimetry = v4l2_hdmi_rx_colorimetry(&frame.avi, NULL,
+ state->timings.bt.height);
+ /* If ycbcr_enc is V4L2_YCBCR_ENC_DEFAULT, we receive RGB */
+ if (c->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) {
+ switch (state->rgb_quantization_range) {
+ case V4L2_DV_RGB_RANGE_LIMITED:
+ c->quantization = V4L2_QUANTIZATION_FULL_RANGE;
+ break;
+ case V4L2_DV_RGB_RANGE_FULL:
+ c->quantization = V4L2_QUANTIZATION_LIM_RANGE;
+ break;
+ }
+ }
+ v4l_dbg(1, debug, state->client,
+ "colorspace=%d/%d colorimetry=%d range=%s content=%d\n",
+ frame.avi.colorspace, c->colorspace,
+ frame.avi.colorimetry,
+ v4l2_quantization_names[c->quantization],
+ frame.avi.content_type);
+
+ /* configure upsampler: 0=bypass 1=repeatchroma 2=interpolate */
+ reg = io_read(sd, REG_PIX_REPEAT);
+ reg &= ~PIX_REPEAT_MASK_UP_SEL;
+ if (frame.avi.colorspace == HDMI_COLORSPACE_YUV422)
+ reg |= (PIX_REPEAT_CHROMA << PIX_REPEAT_SHIFT);
+ io_write(sd, REG_PIX_REPEAT, reg);
+
+ /* ConfigurePixelRepeater: repeat n-times each pixel */
+ reg = io_read(sd, REG_PIX_REPEAT);
+ reg &= ~PIX_REPEAT_MASK_REP;
+ reg |= frame.avi.pixel_repeat;
+ io_write(sd, REG_PIX_REPEAT, reg);
+
+ /* configure the receiver with the new colorspace */
+ tda1997x_configure_csc(sd);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void tda1997x_irq_sus(struct tda1997x_state *state, u8 *flags)
+{
+ struct v4l2_subdev *sd = &state->sd;
+ u8 reg, source;
+
+ source = io_read(sd, REG_INT_FLG_CLR_SUS);
+ io_write(sd, REG_INT_FLG_CLR_SUS, source);
+
+ if (source & MASK_MPT) {
+ /* reset MTP in use flag if set */
+ if (state->mptrw_in_progress)
+ state->mptrw_in_progress = 0;
+ }
+
+ if (source & MASK_SUS_END) {
+ /* reset audio FIFO */
+ reg = io_read(sd, REG_HDMI_INFO_RST);
+ reg |= MASK_SR_FIFO_FIFO_CTRL;
+ io_write(sd, REG_HDMI_INFO_RST, reg);
+ reg &= ~MASK_SR_FIFO_FIFO_CTRL;
+ io_write(sd, REG_HDMI_INFO_RST, reg);
+
+ /* reset HDMI flags */
+ state->hdmi_status = 0;
+ }
+
+ /* filter FMT interrupt based on SUS state */
+ reg = io_read(sd, REG_SUS_STATUS);
+ if (((reg & MASK_SUS_STATUS) != LAST_STATE_REACHED)
+ || (source & MASK_MPT)) {
+ source &= ~MASK_FMT;
+ }
+
+ if (source & (MASK_FMT | MASK_SUS_END)) {
+ reg = io_read(sd, REG_SUS_STATUS);
+ if ((reg & MASK_SUS_STATUS) != LAST_STATE_REACHED) {
+ v4l_err(state->client, "BAD SUS STATUS\n");
+ return;
+ }
+
+ /* There is new activity, the status for HDCP repeater state */
+ state->state_c5_reached = 0;
+
+ /* Detect the new resolution */
+ if (!tda1997x_detect_std(state))
+ v4l2_subdev_notify_event(&state->sd, &tda1997x_ev_fmt);
+ }
+}
+
+static void tda1997x_irq_ddc(struct tda1997x_state *state, u8 *flags)
+{
+ struct v4l2_subdev *sd = &state->sd;
+ u8 source;
+
+ source = io_read(sd, REG_INT_FLG_CLR_DDC);
+ io_write(sd, REG_INT_FLG_CLR_DDC, source);
+ if (source & MASK_EDID_MTP) {
+ /* reset MTP in use flag if set */
+ if (state->mptrw_in_progress)
+ state->mptrw_in_progress = 0;
+ }
+
+ /* Detection of +5V */
+ if (source & MASK_DET_5V) {
+ v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
+ tda1997x_detect_tx_5v(sd));
+ }
+}
+
+static void tda1997x_irq_rate(struct tda1997x_state *state, u8 *flags)
+{
+ struct v4l2_subdev *sd = &state->sd;
+ u8 reg, source;
+
+ u8 irq_status, last_irq_status;
+
+ source = io_read(sd, REG_INT_FLG_CLR_RATE);
+ io_write(sd, REG_INT_FLG_CLR_RATE, source);
+
+ /* read status regs */
+ last_irq_status = irq_status = tda1997x_read_activity_status_regs(sd);
+
+ /*
+ * read clock status reg until INT_FLG_CLR_RATE is still 0
+ * after the read to make sure its the last one
+ */
+ reg = source;
+ while (reg != 0) {
+ irq_status = tda1997x_read_activity_status_regs(sd);
+ reg = io_read(sd, REG_INT_FLG_CLR_RATE);
+ io_write(sd, REG_INT_FLG_CLR_RATE, reg);
+ source |= reg;
+ }
+
+ /* we only pay attention to stability change events */
+ if (source & (MASK_RATE_A_ST | MASK_RATE_B_ST)) {
+ int input = (source & MASK_RATE_A_ST)?0:1;
+ u8 mask = 1<<input;
+
+ /* state change */
+ if ((irq_status & mask) != (state->activity_status & mask)) {
+ /* activity lost */
+ if ((irq_status & mask) == 0) {
+ v4l_info(state->client,
+ "HDMI-%c: Digital Activity Lost\n",
+ input+'A');
+
+ /* bypass up/down sampler and pixel repeater */
+ reg = io_read(sd, REG_PIX_REPEAT);
+ reg &= ~PIX_REPEAT_MASK_UP_SEL;
+ reg &= ~PIX_REPEAT_MASK_REP;
+ io_write(sd, REG_PIX_REPEAT, reg);
+
+ if (state->chip_revision == 0)
+ tda1997x_reset_n1(state);
+
+ state->detected_timings = NULL;
+ state->input_detect[input] = 0;
+ v4l2_subdev_notify_event(sd, &tda1997x_ev_fmt);
+ }
+
+ /* activity detected */
+ else {
+ v4l_info(state->client,
+ "HDMI-%c: Digital Activity Detected\n",
+ input+'A');
+ state->input_detect[input] = 1;
+ }
+
+ /* hold onto current state */
+ state->activity_status = (irq_status & mask);
+ }
+ }
+}
+
+static void tda1997x_irq_info(struct tda1997x_state *state, u8 *flags)
+{
+ struct v4l2_subdev *sd = &state->sd;
+ u8 source;
+
+ source = io_read(sd, REG_INT_FLG_CLR_INFO);
+ io_write(sd, REG_INT_FLG_CLR_INFO, source);
+
+ /* Audio infoframe */
+ if (source & MASK_AUD_IF) {
+ tda1997x_parse_infoframe(state, AUD_IF);
+ source &= ~MASK_AUD_IF;
+ }
+
+ /* Source Product Descriptor infoframe change */
+ if (source & MASK_SPD_IF) {
+ tda1997x_parse_infoframe(state, SPD_IF);
+ source &= ~MASK_SPD_IF;
+ }
+
+ /* Auxiliary Video Information infoframe */
+ if (source & MASK_AVI_IF) {
+ tda1997x_parse_infoframe(state, AVI_IF);
+ source &= ~MASK_AVI_IF;
+ }
+}
+
+static void tda1997x_irq_audio(struct tda1997x_state *state, u8 *flags)
+{
+ struct v4l2_subdev *sd = &state->sd;
+ u8 reg, source;
+
+ source = io_read(sd, REG_INT_FLG_CLR_AUDIO);
+ io_write(sd, REG_INT_FLG_CLR_AUDIO, source);
+
+ /* reset audio FIFO on FIFO pointer error or audio mute */
+ if (source & MASK_ERROR_FIFO_PT ||
+ source & MASK_MUTE_FLG) {
+ /* audio reset audio FIFO */
+ reg = io_read(sd, REG_SUS_STATUS);
+ if ((reg & MASK_SUS_STATUS) == LAST_STATE_REACHED) {
+ reg = io_read(sd, REG_HDMI_INFO_RST);
+ reg |= MASK_SR_FIFO_FIFO_CTRL;
+ io_write(sd, REG_HDMI_INFO_RST, reg);
+ reg &= ~MASK_SR_FIFO_FIFO_CTRL;
+ io_write(sd, REG_HDMI_INFO_RST, reg);
+ /* reset channel status IT if present */
+ source &= ~(MASK_CH_STATE);
+ }
+ }
+ if (source & MASK_AUDIO_FREQ_FLG) {
+ static const int freq[] = {
+ 0, 32000, 44100, 48000, 88200, 96000, 176400, 192000
+ };
+
+ reg = io_read(sd, REG_AUDIO_FREQ);
+ state->audio_samplerate = freq[reg & 7];
+ v4l_info(state->client, "Audio Frequency Change: %dHz\n",
+ state->audio_samplerate);
+ }
+ if (source & MASK_AUDIO_FLG) {
+ reg = io_read(sd, REG_AUDIO_FLAGS);
+ if (reg & BIT(AUDCFG_TYPE_DST))
+ state->audio_type = AUDCFG_TYPE_DST;
+ if (reg & BIT(AUDCFG_TYPE_OBA))
+ state->audio_type = AUDCFG_TYPE_OBA;
+ if (reg & BIT(AUDCFG_TYPE_HBR))
+ state->audio_type = AUDCFG_TYPE_HBR;
+ if (reg & BIT(AUDCFG_TYPE_PCM))
+ state->audio_type = AUDCFG_TYPE_PCM;
+ v4l_info(state->client, "Audio Type: %s\n",
+ audtype_names[state->audio_type]);
+ }
+}
+
+static void tda1997x_irq_hdcp(struct tda1997x_state *state, u8 *flags)
+{
+ struct v4l2_subdev *sd = &state->sd;
+ u8 reg, source;
+
+ source = io_read(sd, REG_INT_FLG_CLR_HDCP);
+ io_write(sd, REG_INT_FLG_CLR_HDCP, source);
+
+ /* reset MTP in use flag if set */
+ if (source & MASK_HDCP_MTP)
+ state->mptrw_in_progress = 0;
+ if (source & MASK_STATE_C5) {
+ /* REPEATER: mask AUDIO and IF irqs to avoid IF during auth */
+ reg = io_read(sd, REG_INT_MASK_TOP);
+ reg &= ~(INTERRUPT_AUDIO | INTERRUPT_INFO);
+ io_write(sd, REG_INT_MASK_TOP, reg);
+ *flags &= (INTERRUPT_AUDIO | INTERRUPT_INFO);
+ }
+}
+
+static irqreturn_t tda1997x_isr_thread(int irq, void *d)
+{
+ struct tda1997x_state *state = d;
+ struct v4l2_subdev *sd = &state->sd;
+ u8 flags;
+
+ mutex_lock(&state->lock);
+ do {
+ /* read interrupt flags */
+ flags = io_read(sd, REG_INT_FLG_CLR_TOP);
+ if (flags == 0)
+ break;
+
+ /* SUS interrupt source (Input activity events) */
+ if (flags & INTERRUPT_SUS)
+ tda1997x_irq_sus(state, &flags);
+ /* DDC interrupt source (Display Data Channel) */
+ else if (flags & INTERRUPT_DDC)
+ tda1997x_irq_ddc(state, &flags);
+ /* RATE interrupt source (Digital Input activity) */
+ else if (flags & INTERRUPT_RATE)
+ tda1997x_irq_rate(state, &flags);
+ /* Infoframe change interrupt */
+ else if (flags & INTERRUPT_INFO)
+ tda1997x_irq_info(state, &flags);
+ /* Audio interrupt source:
+ * freq change, DST,OBA,HBR,ASP flags, mute, FIFO err
+ */
+ else if (flags & INTERRUPT_AUDIO)
+ tda1997x_irq_audio(state, &flags);
+ /* HDCP interrupt source (content protection) */
+ if (flags & INTERRUPT_HDCP)
+ tda1997x_irq_hdcp(state, &flags);
+ } while (flags != 0);
+ mutex_unlock(&state->lock);
+
+ return IRQ_HANDLED;
+}
+
+static bool tda1997x_check_dv_timings(const struct v4l2_dv_timings *timings,
+ void *hdl)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(tda1997x_hdmi_modes); i++) {
+ if (v4l2_match_dv_timings(timings, &tda1997x_hdmi_modes[i],
+ 0, false))
+ return true;
+ }
+
+ return false;
+}
+
+/* -----------------------------------------------------------------------------
+ * v4l2_subdev_video_ops
+ */
+
+static int
+tda1997x_g_input_status(struct v4l2_subdev *sd, u32 *status)
+{
+ struct tda1997x_state *state = to_state(sd);
+
+ mutex_lock(&state->lock);
+ if (state->detected_timings)
+ *status = 0;
+ else
+ *status |= V4L2_IN_ST_NO_SIGNAL;
+ mutex_unlock(&state->lock);
+
+ return 0;
+};
+
+static int tda1997x_s_dv_timings(struct v4l2_subdev *sd,
+ struct v4l2_dv_timings *timings)
+{
+ struct tda1997x_state *state = to_state(sd);
+ int ret;
+
+ v4l_dbg(1, debug, state->client, "%s\n", __func__);
+ if (!timings)
+ return -EINVAL;
+
+ if (v4l2_match_dv_timings(&state->timings, timings, 0, false))
+ return 0; /* no changes */
+
+ if (!v4l2_valid_dv_timings(timings, &tda1997x_dv_timings_cap,
+ tda1997x_check_dv_timings, state))
+ return -ERANGE;
+
+ mutex_lock(&state->lock);
+ state->timings = *timings;
+ /* setup frame detection window and VHREF timing generator */
+ ret = tda1997x_configure_vhref(sd);
+ if (ret)
+ goto error;
+ /* configure colorspace conversion */
+ ret = tda1997x_configure_csc(sd);
+ if (ret)
+ goto error;
+ mutex_unlock(&state->lock);
+
+ return 0;
+
+error:
+ mutex_unlock(&state->lock);
+ return ret;
+}
+
+static int tda1997x_g_dv_timings(struct v4l2_subdev *sd,
+ struct v4l2_dv_timings *timings)
+{
+ struct tda1997x_state *state = to_state(sd);
+
+ v4l_dbg(1, debug, state->client, "%s\n", __func__);
+ if (!timings)
+ return -EINVAL;
+
+ mutex_lock(&state->lock);
+ *timings = state->timings;
+ mutex_unlock(&state->lock);
+
+ return 0;
+}
+
+static int tda1997x_query_dv_timings(struct v4l2_subdev *sd,
+ struct v4l2_dv_timings *timings)
+{
+ struct tda1997x_state *state = to_state(sd);
+ int ret;
+
+ v4l_dbg(1, debug, state->client, "%s\n", __func__);
+ if (!timings)
+ return -EINVAL;
+
+ memset(timings, 0, sizeof(struct v4l2_dv_timings));
+ mutex_lock(&state->lock);
+ ret = tda1997x_detect_std(state);
+ if (!ret)
+ *timings = *state->detected_timings;
+ mutex_unlock(&state->lock);
+
+ return ret;
+}
+
+static int tda1997x_s_stream(struct v4l2_subdev *sd, int enable)
+{
+ struct tda1997x_state *state = to_state(sd);
+
+ v4l_dbg(1, debug, state->client, "%s %d\n", __func__, enable);
+ mutex_lock(&state->lock);
+ if (!state->detected_timings)
+ v4l_dbg(1, debug, state->client, "Invalid HDMI signal\n");
+ mutex_unlock(&state->lock);
+
+ return 0;
+}
+
+static const struct v4l2_subdev_video_ops tda1997x_video_ops = {
+ .g_input_status = tda1997x_g_input_status,
+ .s_dv_timings = tda1997x_s_dv_timings,
+ .g_dv_timings = tda1997x_g_dv_timings,
+ .query_dv_timings = tda1997x_query_dv_timings,
+ .s_stream = tda1997x_s_stream,
+};
+
+
+/* -----------------------------------------------------------------------------
+ * v4l2_subdev_pad_ops
+ */
+
+static int tda1997x_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ struct tda1997x_state *state = to_state(sd);
+
+ if (code->index > 0)
+ return -EINVAL;
+
+ code->code = state->code;
+
+ return 0;
+}
+
+static int tda1997x_fill_format(struct tda1997x_state *state,
+ struct v4l2_mbus_framefmt *format)
+{
+ const struct v4l2_bt_timings *bt;
+
+ v4l_dbg(1, debug, state->client, "%s\n", __func__);
+
+ if (!state->detected_timings)
+ return -EINVAL;
+
+ memset(format, 0, sizeof(*format));
+ bt = &state->detected_timings->bt;
+ format->width = bt->width;
+ format->height = bt->height;
+ format->colorspace = state->colorimetry.colorspace;
+
+ return 0;
+}
+
+static int tda1997x_get_pad_format(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *format)
+{
+ struct tda1997x_state *state = to_state(sd);
+
+ v4l_dbg(1, debug, state->client, "%s\n", __func__);
+ if (format->pad != TDA1997X_PAD_SOURCE)
+ return -EINVAL;
+
+ tda1997x_fill_format(state, &format->format);
+
+ if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
+ struct v4l2_mbus_framefmt *fmt;
+
+ fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
+ format->format.code = format->format.code;
+ } else
+ format->format.code = state->code;
+
+ return 0;
+}
+
+static int tda1997x_set_pad_format(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *format)
+{
+ struct v4l2_mbus_framefmt *fmt;
+
+ if (format->pad != TDA1997X_PAD_SOURCE)
+ return -EINVAL;
+
+ if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
+ return tda1997x_get_pad_format(sd, cfg, format);
+
+ fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
+ *fmt = format->format;
+
+ return 0;
+}
+
+static int tda1997x_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
+{
+ struct tda1997x_state *state = to_state(sd);
+
+ v4l_dbg(1, debug, state->client, "%s pad=%d\n", __func__, edid->pad);
+ memset(edid->reserved, 0, sizeof(edid->reserved));
+
+ if (!state->edid.present)
+ return -ENODATA;
+
+ if (edid->start_block == 0 && edid->blocks == 0) {
+ edid->blocks = state->edid.blocks;
+ return 0;
+ }
+
+ if (edid->start_block >= state->edid.blocks)
+ return -EINVAL;
+
+ if (edid->start_block + edid->blocks > state->edid.blocks)
+ edid->blocks = state->edid.blocks - edid->start_block;
+
+ memcpy(edid->edid, state->edid.edid + edid->start_block * 128,
+ edid->blocks * 128);
+
+ return 0;
+}
+
+static int tda1997x_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
+{
+ struct tda1997x_state *state = to_state(sd);
+ int i;
+
+ v4l_dbg(1, debug, state->client, "%s pad=%d\n", __func__, edid->pad);
+ memset(edid->reserved, 0, sizeof(edid->reserved));
+
+ if (edid->start_block != 0)
+ return -EINVAL;
+
+ if (edid->blocks == 0) {
+ state->edid.blocks = 0;
+ state->edid.present = 0;
+ tda1997x_disable_edid(sd);
+ return 0;
+ }
+
+ if (edid->blocks > 2) {
+ edid->blocks = 2;
+ return -E2BIG;
+ }
+
+ tda1997x_disable_edid(sd);
+
+ /* write base EDID */
+ for (i = 0; i < 128; i++)
+ io_write(sd, REG_EDID_IN_BYTE0 + i, edid->edid[i]);
+
+ /* write CEA Extension */
+ for (i = 0; i < 128; i++)
+ io_write(sd, REG_EDID_IN_BYTE128 + i, edid->edid[i+128]);
+
+ tda1997x_enable_edid(sd);
+
+ return 0;
+}
+
+static int tda1997x_get_dv_timings_cap(struct v4l2_subdev *sd,
+ struct v4l2_dv_timings_cap *cap)
+{
+ *cap = tda1997x_dv_timings_cap;
+ return 0;
+}
+
+static int tda1997x_enum_dv_timings(struct v4l2_subdev *sd,
+ struct v4l2_enum_dv_timings *timings)
+{
+ struct tda1997x_state *state = to_state(sd);
+
+ return v4l2_enum_dv_timings_cap(timings, &tda1997x_dv_timings_cap,
+ tda1997x_check_dv_timings, state);
+}
+
+static const struct v4l2_subdev_pad_ops tda1997x_pad_ops = {
+ .enum_mbus_code = tda1997x_enum_mbus_code,
+ .get_fmt = tda1997x_get_pad_format,
+ .set_fmt = tda1997x_set_pad_format,
+ .get_edid = tda1997x_get_edid,
+ .set_edid = tda1997x_set_edid,
+ .dv_timings_cap = tda1997x_get_dv_timings_cap,
+ .enum_dv_timings = tda1997x_enum_dv_timings,
+};
+
+/* -----------------------------------------------------------------------------
+ * v4l2_subdev_core_ops
+ */
+
+static int tda1997x_log_infoframe(struct v4l2_subdev *sd, int addr)
+{
+ struct tda1997x_state *state = to_state(sd);
+ union hdmi_infoframe frame;
+ u8 buffer[40];
+ int len, err;
+
+ /* read data */
+ len = io_readn(sd, addr, sizeof(buffer), buffer);
+ v4l2_dbg(1, debug, sd, "infoframe: addr=%d len=%d\n", addr, len);
+ err = hdmi_infoframe_unpack(&frame, buffer);
+ if (err) {
+ v4l_err(state->client,
+ "failed parsing %d byte infoframe: 0x%04x/0x%02x\n",
+ len, addr, buffer[0]);
+ return err;
+ }
+ hdmi_infoframe_log(KERN_INFO, &state->client->dev, &frame);
+
+ return 0;
+}
+
+static int tda1997x_log_status(struct v4l2_subdev *sd)
+{
+ struct tda1997x_state *state = to_state(sd);
+ struct v4l2_dv_timings timings;
+ struct hdmi_avi_infoframe *avi = &state->avi_infoframe;
+
+ v4l2_info(sd, "-----Chip status-----\n");
+ v4l2_info(sd, "Chip: %s N%d\n", state->info->name,
+ state->chip_revision + 1);
+ v4l2_info(sd, "EDID Enabled: %s\n", state->edid.present ? "yes" : "no");
+
+ v4l2_info(sd, "-----Signal status-----\n");
+ v4l2_info(sd, "Cable detected (+5V power): %s\n",
+ tda1997x_detect_tx_5v(sd) ? "yes" : "no");
+ v4l2_info(sd, "HPD detected: %s\n",
+ tda1997x_detect_tx_hpd(sd) ? "yes" : "no");
+
+ v4l2_info(sd, "-----Video Timings-----\n");
+ if (tda1997x_query_dv_timings(sd, &timings))
+ v4l2_info(sd, "No video detected\n");
+ else
+ v4l2_print_dv_timings(sd->name, "Detected format: ",
+ &timings, true);
+ v4l2_print_dv_timings(sd->name, "Configured format: ",
+ &state->timings, true);
+
+ v4l2_info(sd, "-----Color space-----\n");
+ v4l2_info(sd, "Input color space: %s %s %s",
+ hdmi_colorspace_names[avi->colorspace],
+ (avi->colorspace == HDMI_COLORSPACE_RGB) ? "" :
+ hdmi_colorimetry_names[avi->colorimetry],
+ v4l2_quantization_names[state->colorimetry.quantization]);
+ v4l2_info(sd, "Output color space: %s",
+ vidfmt_names[state->vid_fmt]);
+ v4l2_info(sd, "Color space conversion: %s", state->conv ?
+ state->conv->name : "None");
+
+ v4l2_info(sd, "-----Audio-----\n");
+ if (state->audio_channels) {
+ v4l2_info(sd, "audio: %dch %dHz\n", state->audio_channels,
+ state->audio_samplerate);
+ } else {
+ v4l2_info(sd, "audio: none\n");
+ }
+
+ v4l2_info(sd, "-----Infoframes-----\n");
+ tda1997x_log_infoframe(sd, AUD_IF);
+ tda1997x_log_infoframe(sd, SPD_IF);
+ tda1997x_log_infoframe(sd, AVI_IF);
+
+ return 0;
+}
+
+static int tda1997x_subscribe_event(struct v4l2_subdev *sd,
+ struct v4l2_fh *fh,
+ struct v4l2_event_subscription *sub)
+{
+ switch (sub->type) {
+ case V4L2_EVENT_SOURCE_CHANGE:
+ return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
+ case V4L2_EVENT_CTRL:
+ return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct v4l2_subdev_core_ops tda1997x_core_ops = {
+ .log_status = tda1997x_log_status,
+ .subscribe_event = tda1997x_subscribe_event,
+ .unsubscribe_event = v4l2_event_subdev_unsubscribe,
+};
+
+/* -----------------------------------------------------------------------------
+ * v4l2_subdev_ops
+ */
+
+static const struct v4l2_subdev_ops tda1997x_subdev_ops = {
+ .core = &tda1997x_core_ops,
+ .video = &tda1997x_video_ops,
+ .pad = &tda1997x_pad_ops,
+};
+
+/* -----------------------------------------------------------------------------
+ * v4l2_controls
+ */
+
+static int tda1997x_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct v4l2_subdev *sd = to_sd(ctrl);
+ struct tda1997x_state *state = to_state(sd);
+
+ switch (ctrl->id) {
+ /* allow overriding the default RGB quantization range */
+ case V4L2_CID_DV_RX_RGB_RANGE:
+ state->rgb_quantization_range = ctrl->val;
+ tda1997x_configure_csc(sd);
+ return 0;
+ }
+
+ return -EINVAL;
+};
+
+static int tda1997x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct v4l2_subdev *sd = to_sd(ctrl);
+ struct tda1997x_state *state = to_state(sd);
+
+ if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
+ ctrl->val = state->avi_infoframe.content_type;
+ return 0;
+ }
+ return -EINVAL;
+};
+
+static const struct v4l2_ctrl_ops tda1997x_ctrl_ops = {
+ .s_ctrl = tda1997x_s_ctrl,
+ .g_volatile_ctrl = tda1997x_g_volatile_ctrl,
+};
+
+static int tda1997x_core_init(struct v4l2_subdev *sd)
+{
+ struct tda1997x_state *state = to_state(sd);
+ struct tda1997x_platform_data *pdata = &state->pdata;
+ u8 reg;
+ int i;
+
+ /* disable HPD */
+ io_write(sd, REG_HPD_AUTO_CTRL, HPD_AUTO_HPD_UNSEL);
+ if (state->chip_revision == 0) {
+ io_write(sd, REG_MAN_SUS_HDMI_SEL, MAN_DIS_HDCP | MAN_RST_HDCP);
+ io_write(sd, REG_CGU_DBG_SEL, 1 << CGU_DBG_CLK_SEL_SHIFT);
+ }
+
+ /* reset infoframe at end of start-up-sequencer */
+ io_write(sd, REG_SUS_SET_RGB2, 0x06);
+ io_write(sd, REG_SUS_SET_RGB3, 0x06);
+
+ /* Enable TMDS pull-ups */
+ io_write(sd, REG_RT_MAN_CTRL, RT_MAN_CTRL_RT |
+ RT_MAN_CTRL_RT_B | RT_MAN_CTRL_RT_A);
+
+ /* enable sync measurement timing */
+ tda1997x_cec_write(sd, REG_PWR_CONTROL & 0xff, 0x04);
+ /* adjust CEC clock divider */
+ tda1997x_cec_write(sd, REG_OSC_DIVIDER & 0xff, 0x03);
+ tda1997x_cec_write(sd, REG_EN_OSC_PERIOD_LSB & 0xff, 0xa0);
+ io_write(sd, REG_TIMER_D, 0x54);
+ /* enable power switch */
+ reg = tda1997x_cec_read(sd, REG_CONTROL & 0xff);
+ reg |= 0x20;
+ tda1997x_cec_write(sd, REG_CONTROL & 0xff, reg);
+ mdelay(50);
+
+ /* read the chip version */
+ reg = io_read(sd, REG_VERSION);
+ /* get the chip configuration */
+ reg = io_read(sd, REG_CMTP_REG10);
+
+ /* enable interrupts we care about */
+ io_write(sd, REG_INT_MASK_TOP,
+ INTERRUPT_HDCP | INTERRUPT_AUDIO | INTERRUPT_INFO |
+ INTERRUPT_RATE | INTERRUPT_SUS);
+ /* config_mtp,fmt,sus_end,sus_st */
+ io_write(sd, REG_INT_MASK_SUS, MASK_MPT | MASK_FMT | MASK_SUS_END);
+ /* rate stability change for inputs A/B */
+ io_write(sd, REG_INT_MASK_RATE, MASK_RATE_B_ST | MASK_RATE_A_ST);
+ /* aud,spd,avi*/
+ io_write(sd, REG_INT_MASK_INFO,
+ MASK_AUD_IF | MASK_SPD_IF | MASK_AVI_IF);
+ /* audio_freq,audio_flg,mute_flg,fifo_err */
+ io_write(sd, REG_INT_MASK_AUDIO,
+ MASK_AUDIO_FREQ_FLG | MASK_AUDIO_FLG | MASK_MUTE_FLG |
+ MASK_ERROR_FIFO_PT);
+ /* HDCP C5 state reached */
+ io_write(sd, REG_INT_MASK_HDCP, MASK_STATE_C5);
+ /* 5V detect and HDP pulse end */
+ io_write(sd, REG_INT_MASK_DDC, MASK_DET_5V);
+ /* don't care about AFE/MODE */
+ io_write(sd, REG_INT_MASK_AFE, 0);
+ io_write(sd, REG_INT_MASK_MODE, 0);
+
+ /* clear all interrupts */
+ io_write(sd, REG_INT_FLG_CLR_TOP, 0xff);
+ io_write(sd, REG_INT_FLG_CLR_SUS, 0xff);
+ io_write(sd, REG_INT_FLG_CLR_DDC, 0xff);
+ io_write(sd, REG_INT_FLG_CLR_RATE, 0xff);
+ io_write(sd, REG_INT_FLG_CLR_MODE, 0xff);
+ io_write(sd, REG_INT_FLG_CLR_INFO, 0xff);
+ io_write(sd, REG_INT_FLG_CLR_AUDIO, 0xff);
+ io_write(sd, REG_INT_FLG_CLR_HDCP, 0xff);
+ io_write(sd, REG_INT_FLG_CLR_AFE, 0xff);
+
+ /* init TMDS equalizer */
+ if (state->chip_revision == 0)
+ io_write(sd, REG_CGU_DBG_SEL, 1 << CGU_DBG_CLK_SEL_SHIFT);
+ io_write24(sd, REG_CLK_MIN_RATE, CLK_MIN_RATE);
+ io_write24(sd, REG_CLK_MAX_RATE, CLK_MAX_RATE);
+ if (state->chip_revision == 0)
+ io_write(sd, REG_WDL_CFG, WDL_CFG_VAL);
+ /* DC filter */
+ io_write(sd, REG_DEEP_COLOR_CTRL, DC_FILTER_VAL);
+ /* disable test pattern */
+ io_write(sd, REG_SVC_MODE, 0x00);
+ /* update HDMI INFO CTRL */
+ io_write(sd, REG_INFO_CTRL, 0xff);
+ /* write HDMI INFO EXCEED value */
+ io_write(sd, REG_INFO_EXCEED, 3);
+
+ if (state->chip_revision == 0)
+ tda1997x_reset_n1(state);
+
+ /*
+ * No HDCP acknowledge when HDCP is disabled
+ * and reset SUS to force format detection
+ */
+ tda1997x_hdmi_info_reset(sd, NACK_HDCP, true);
+
+ /* Set HPD low */
+ tda1997x_manual_hpd(sd, HPD_LOW_BP);
+
+ /* Configure receiver capabilities */
+ io_write(sd, REG_HDCP_BCAPS, HDCP_HDMI | HDCP_FAST_REAUTH);
+
+ /* Configure HDMI: Auto HDCP mode, packet controlled mute */
+ reg = HDMI_CTRL_MUTE_AUTO << HDMI_CTRL_MUTE_SHIFT;
+ reg |= HDMI_CTRL_HDCP_AUTO << HDMI_CTRL_HDCP_SHIFT;
+ io_write(sd, REG_HDMI_CTRL, reg);
+
+ /* reset start-up-sequencer to force format detection */
+ tda1997x_hdmi_info_reset(sd, 0, true);
+
+ /* disable matrix conversion */
+ reg = io_read(sd, REG_VDP_CTRL);
+ reg |= VDP_CTRL_MATRIX_BP;
+ io_write(sd, REG_VDP_CTRL, reg);
+
+ /* set video output mode */
+ tda1997x_configure_vidout(state);
+
+ /* configure video output port */
+ for (i = 0; i < 9; i++) {
+ v4l_dbg(1, debug, state->client, "vidout_cfg[%d]=0x%02x\n", i,
+ pdata->vidout_port_cfg[i]);
+ io_write(sd, REG_VP35_32_CTRL + i, pdata->vidout_port_cfg[i]);
+ }
+
+ /* configure audio output port */
+ tda1997x_configure_audout(sd, 0);
+
+ /* configure audio clock freq */
+ switch (pdata->audout_mclk_fs) {
+ case 512:
+ reg = AUDIO_CLOCK_SEL_512FS;
+ break;
+ case 256:
+ reg = AUDIO_CLOCK_SEL_256FS;
+ break;
+ case 128:
+ reg = AUDIO_CLOCK_SEL_128FS;
+ break;
+ case 64:
+ reg = AUDIO_CLOCK_SEL_64FS;
+ break;
+ case 32:
+ reg = AUDIO_CLOCK_SEL_32FS;
+ break;
+ default:
+ reg = AUDIO_CLOCK_SEL_16FS;
+ break;
+ }
+ io_write(sd, REG_AUDIO_CLOCK, reg);
+
+ /* reset advanced infoframes (ISRC1/ISRC2/ACP) */
+ tda1997x_hdmi_info_reset(sd, RESET_AI, false);
+ /* reset infoframe */
+ tda1997x_hdmi_info_reset(sd, RESET_IF, false);
+ /* reset audio infoframes */
+ tda1997x_hdmi_info_reset(sd, RESET_AUDIO, false);
+ /* reset gamut */
+ tda1997x_hdmi_info_reset(sd, RESET_GAMUT, false);
+
+ /* get initial HDMI status */
+ state->hdmi_status = io_read(sd, REG_HDMI_FLAGS);
+
+ return 0;
+}
+
+static int tda1997x_set_power(struct tda1997x_state *state, bool on)
+{
+ int ret = 0;
+
+ if (on) {
+ ret = regulator_bulk_enable(TDA1997X_NUM_SUPPLIES,
+ state->supplies);
+ msleep(300);
+ } else {
+ ret = regulator_bulk_disable(TDA1997X_NUM_SUPPLIES,
+ state->supplies);
+ }
+
+ return ret;
+}
+
+static const struct i2c_device_id tda1997x_i2c_id[] = {
+ {"tda19971", (kernel_ulong_t)&tda1997x_chip_info[TDA19971]},
+ {"tda19973", (kernel_ulong_t)&tda1997x_chip_info[TDA19973]},
+ { },
+};
+MODULE_DEVICE_TABLE(i2c, tda1997x_i2c_id);
+
+static const struct of_device_id tda1997x_of_id[] __maybe_unused = {
+ { .compatible = "nxp,tda19971", .data = &tda1997x_chip_info[TDA19971] },
+ { .compatible = "nxp,tda19973", .data = &tda1997x_chip_info[TDA19973] },
+ { },
+};
+MODULE_DEVICE_TABLE(of, tda1997x_of_id);
+
+static int tda1997x_parse_dt(struct tda1997x_state *state)
+{
+ struct tda1997x_platform_data *pdata = &state->pdata;
+ struct v4l2_fwnode_endpoint bus_cfg;
+ struct device_node *ep;
+ struct device_node *np;
+ unsigned int flags;
+ const char *str;
+ int ret;
+ u32 v;
+
+ /*
+ * setup default values:
+ * - HREF: active high from start to end of row
+ * - VS: Vertical Sync active high at beginning of frame
+ * - DE: Active high when data valid
+ * - A_CLK: 128*Fs
+ */
+ pdata->vidout_sel_hs = HS_HREF_SEL_HREF_VHREF;
+ pdata->vidout_sel_vs = VS_VREF_SEL_VREF_HDMI;
+ pdata->vidout_sel_de = DE_FREF_SEL_DE_VHREF;
+
+ np = state->client->dev.of_node;
+ ep = of_graph_get_next_endpoint(np, NULL);
+ if (!ep)
+ return -EINVAL;
+
+ ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &bus_cfg);
+ if (ret) {
+ of_node_put(ep);
+ return ret;
+ }
+ of_node_put(ep);
+
+ /* polarity of HS/VS/DE */
+ flags = bus_cfg.bus.parallel.flags;
+ if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
+ pdata->vidout_inv_hs = 1;
+ if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
+ pdata->vidout_inv_vs = 1;
+ if (flags & V4L2_MBUS_DATA_ACTIVE_LOW)
+ pdata->vidout_inv_de = 1;
+ pdata->vidout_bus_width = bus_cfg.bus.parallel.bus_width;
+
+ /* video output port config */
+ ret = of_property_count_u32_elems(np, "nxp,vidout-portcfg");
+ if (ret > 0) {
+ u32 reg, val, i;
+
+ for (i = 0; i < ret / 2 && i < 9; i++) {
+ of_property_read_u32_index(np, "nxp,vidout-portcfg",
+ i * 2, ®);
+ of_property_read_u32_index(np, "nxp,vidout-portcfg",
+ i * 2 + 1, &val);
+ if (reg < 9)
+ pdata->vidout_port_cfg[reg] = val;
+ }
+ } else {
+ v4l_err(state->client, "nxp,vidout-portcfg missing\n");
+ return -EINVAL;
+ }
+
+ /* default to channel layout dictated by packet header */
+ pdata->audout_layoutauto = true;
+
+ pdata->audout_format = AUDFMT_TYPE_DISABLED;
+ if (!of_property_read_string(np, "nxp,audout-format", &str)) {
+ if (strcmp(str, "i2s") == 0)
+ pdata->audout_format = AUDFMT_TYPE_I2S;
+ else if (strcmp(str, "spdif") == 0)
+ pdata->audout_format = AUDFMT_TYPE_SPDIF;
+ else {
+ v4l_err(state->client, "nxp,audout-format invalid\n");
+ return -EINVAL;
+ }
+ if (!of_property_read_u32(np, "nxp,audout-layout", &v)) {
+ switch (v) {
+ case 0:
+ case 1:
+ break;
+ default:
+ v4l_err(state->client,
+ "nxp,audout-layout invalid\n");
+ return -EINVAL;
+ }
+ pdata->audout_layout = v;
+ }
+ if (!of_property_read_u32(np, "nxp,audout-width", &v)) {
+ switch (v) {
+ case 16:
+ case 32:
+ break;
+ default:
+ v4l_err(state->client,
+ "nxp,audout-width invalid\n");
+ return -EINVAL;
+ }
+ pdata->audout_width = v;
+ }
+ if (!of_property_read_u32(np, "nxp,audout-mclk-fs", &v)) {
+ switch (v) {
+ case 512:
+ case 256:
+ case 128:
+ case 64:
+ case 32:
+ case 16:
+ break;
+ default:
+ v4l_err(state->client,
+ "nxp,audout-mclk-fs invalid\n");
+ return -EINVAL;
+ }
+ pdata->audout_mclk_fs = v;
+ }
+ }
+
+ return 0;
+}
+
+static int tda1997x_get_regulators(struct tda1997x_state *state)
+{
+ int i;
+
+ for (i = 0; i < TDA1997X_NUM_SUPPLIES; i++)
+ state->supplies[i].supply = tda1997x_supply_name[i];
+
+ return devm_regulator_bulk_get(&state->client->dev,
+ TDA1997X_NUM_SUPPLIES,
+ state->supplies);
+}
+
+static int tda1997x_identify_module(struct tda1997x_state *state)
+{
+ struct v4l2_subdev *sd = &state->sd;
+ enum tda1997x_type type;
+ u8 reg;
+
+ /* Read chip configuration*/
+ reg = io_read(sd, REG_CMTP_REG10);
+ state->tmdsb_clk = (reg >> 6) & 0x01; /* use tmds clock B_inv for B */
+ state->tmdsb_soc = (reg >> 5) & 0x01; /* tmds of input B */
+ state->port_30bit = (reg >> 2) & 0x03; /* 30bit vs 24bit */
+ state->output_2p5 = (reg >> 1) & 0x01; /* output supply 2.5v */
+ switch ((reg >> 4) & 0x03) {
+ case 0x00:
+ type = TDA19971;
+ break;
+ case 0x02:
+ case 0x03:
+ type = TDA19973;
+ break;
+ default:
+ dev_err(&state->client->dev, "unsupported chip ID\n");
+ return -EIO;
+ }
+ if (state->info->type != type) {
+ dev_err(&state->client->dev, "chip id mismatch\n");
+ return -EIO;
+ }
+
+ /* read chip revision */
+ state->chip_revision = io_read(sd, REG_CMTP_REG11);
+
+ return 0;
+}
+
+static const struct media_entity_operations tda1997x_media_ops = {
+ .link_validate = v4l2_subdev_link_validate,
+};
+
+
+/* -----------------------------------------------------------------------------
+ * HDMI Audio Codec
+ */
+
+/* refine sample-rate based on HDMI source */
+static int tda1997x_pcm_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct tda1997x_state *state = snd_soc_dai_get_drvdata(dai);
+ struct snd_soc_codec *codec = dai->codec;
+ struct snd_pcm_runtime *rtd = substream->runtime;
+ int rate, err;
+
+ rate = state->audio_samplerate;
+ err = snd_pcm_hw_constraint_minmax(rtd, SNDRV_PCM_HW_PARAM_RATE,
+ rate, rate);
+ if (err < 0) {
+ dev_err(codec->dev, "failed to constrain samplerate to %dHz\n",
+ rate);
+ return err;
+ }
+ dev_info(codec->dev, "set samplerate constraint to %dHz\n", rate);
+
+ return 0;
+}
+
+static const struct snd_soc_dai_ops tda1997x_dai_ops = {
+ .startup = tda1997x_pcm_startup,
+};
+
+static struct snd_soc_dai_driver tda1997x_audio_dai = {
+ .name = "tda1997x",
+ .capture = {
+ .stream_name = "Capture",
+ .channels_min = 2,
+ .channels_max = 8,
+ .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
+ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
+ SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
+ SNDRV_PCM_RATE_192000,
+ },
+ .ops = &tda1997x_dai_ops,
+};
+
+static int tda1997x_codec_probe(struct snd_soc_codec *codec)
+{
+ return 0;
+}
+
+static int tda1997x_codec_remove(struct snd_soc_codec *codec)
+{
+ return 0;
+}
+
+static struct snd_soc_codec_driver tda1997x_codec_driver = {
+ .probe = tda1997x_codec_probe,
+ .remove = tda1997x_codec_remove,
+ .reg_word_size = sizeof(u16),
+};
+
+static int tda1997x_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct tda1997x_state *state;
+ struct tda1997x_platform_data *pdata;
+ struct v4l2_subdev *sd;
+ struct v4l2_ctrl_handler *hdl;
+ struct v4l2_ctrl *ctrl;
+ static const struct v4l2_dv_timings cea1920x1080 =
+ V4L2_DV_BT_CEA_1920X1080P60;
+ int ret;
+
+ /* Check if the adapter supports the needed features */
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+ return -EIO;
+
+ state = kzalloc(sizeof(struct tda1997x_state), GFP_KERNEL);
+ if (!state)
+ return -ENOMEM;
+
+ state->client = client;
+ pdata = &state->pdata;
+ if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
+ const struct of_device_id *oid;
+
+ oid = of_match_node(tda1997x_of_id, client->dev.of_node);
+ state->info = oid->data;
+
+ ret = tda1997x_parse_dt(state);
+ if (ret < 0) {
+ v4l_err(client, "DT parsing error\n");
+ goto err_free_state;
+ }
+ } else if (client->dev.platform_data) {
+ struct tda1997x_platform_data *pdata =
+ client->dev.platform_data;
+ state->info =
+ (const struct tda1997x_chip_info *)id->driver_data;
+ state->pdata = *pdata;
+ } else {
+ v4l_err(client, "No platform data\n");
+ ret = -ENODEV;
+ goto err_free_state;
+ }
+
+ ret = tda1997x_get_regulators(state);
+ if (ret)
+ goto err_free_state;
+
+ ret = tda1997x_set_power(state, 1);
+ if (ret)
+ goto err_free_state;
+
+ mutex_init(&state->page_lock);
+ mutex_init(&state->lock);
+ state->page = 0xff;
+
+ INIT_DELAYED_WORK(&state->delayed_work_enable_hpd,
+ tda1997x_delayed_work_enable_hpd);
+
+ /* set video format based on chip and bus width */
+ ret = tda1997x_identify_module(state);
+ if (ret)
+ goto err_free_mutex;
+
+ /* initialize subdev */
+ sd = &state->sd;
+ v4l2_i2c_subdev_init(sd, client, &tda1997x_subdev_ops);
+ snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
+ id->name, i2c_adapter_id(client->adapter),
+ client->addr);
+ sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
+ sd->entity.ops = &tda1997x_media_ops;
+
+ switch (state->info->type) {
+ case TDA19973:
+ switch (pdata->vidout_bus_width) {
+ case 36: /* 36bit RGB (could also be 36bit YUV) */
+ state->code = MEDIA_BUS_FMT_YUV12_1X36;
+ break;
+ case 24: /* 24bit BT656 (YUV422 semi-planar: 1-cycle) */
+ state->code = MEDIA_BUS_FMT_UYVY12_1X24;
+ break;
+ case 12: /* 12bit BT656 (2-cycle) */
+ state->code = MEDIA_BUS_FMT_UYVY12_2X12;
+ break;
+ }
+ break;
+ case TDA19971:
+ switch (pdata->vidout_bus_width) {
+ case 24: /* 24bit YUV (could also be RGB or YUV422) */
+ state->code = MEDIA_BUS_FMT_YUV8_1X24;
+ break;
+ case 20: /* 20bit YUV422 */
+ state->code = MEDIA_BUS_FMT_UYVY10_1X20;
+ break;
+ case 16: /* 16bit BT656 (YUV422 semi-planar: 1-cycle) */
+ state->code = MEDIA_BUS_FMT_UYVY8_1X16;
+ break;
+ case 12: /* 12bit BT656 (2-cycle) */
+ state->code = MEDIA_BUS_FMT_UYVY12_2X12;
+ break;
+ case 10: /* 10bit BT656 (2-cycle) */
+ state->code = MEDIA_BUS_FMT_UYVY10_2X10;
+ break;
+ case 8: /* 8bit BT656 (2-cycle) */
+ state->code = MEDIA_BUS_FMT_UYVY8_2X8;
+ break;
+ }
+ }
+ switch (state->code) {
+ case MEDIA_BUS_FMT_RGB121212_1X36:
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ case MEDIA_BUS_FMT_YUV12_1X36:
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ state->bus_type = V4L2_MBUS_PARALLEL;
+ state->vid_fmt = OF_FMT_444;
+ break;
+ case MEDIA_BUS_FMT_UYVY12_1X24:
+ case MEDIA_BUS_FMT_UYVY8_1X16:
+ state->bus_type = V4L2_MBUS_BT656;
+ state->vid_fmt = OF_FMT_422_SMPT;
+ break;
+ case MEDIA_BUS_FMT_UYVY12_2X12:
+ case MEDIA_BUS_FMT_UYVY10_2X10:
+ case MEDIA_BUS_FMT_UYVY8_2X8:
+ state->bus_type = V4L2_MBUS_BT656;
+ state->vid_fmt = OF_FMT_422_CCIR;
+ break;
+ default:
+ v4l_err(state->client, "incompatible code (%x)\n", state->code);
+ ret = -EINVAL;
+ goto err_free_mutex;
+ }
+ state->timings = cea1920x1080;
+
+ /* disable/reset HDCP to get correct I2C access to Rx HDMI */
+ io_write(sd, REG_MAN_SUS_HDMI_SEL, MAN_RST_HDCP | MAN_DIS_HDCP);
+
+ /*
+ * if N2 version, reset compdel_bp as it may generate some small pixel
+ * shifts in case of embedded sync/or delay lower than 4
+ */
+ if (state->chip_revision != 0) {
+ io_write(sd, REG_MAN_SUS_HDMI_SEL, 0x00);
+ io_write(sd, REG_VDP_CTRL, 0x1f);
+ }
+
+ v4l_info(client, "NXP %s N%d detected\n", state->info->name,
+ state->chip_revision + 1);
+ v4l_info(client, "video: %dbit %s %s MBUS_FMT=0x%x\n",
+ pdata->vidout_bus_width,
+ (state->bus_type == V4L2_MBUS_PARALLEL) ? "parallel" : "BT656",
+ vidfmt_names[state->vid_fmt],
+ state->code);
+ if (pdata->audout_format) {
+ v4l_info(client, "audio: %dch %s layout%d sysclk=%d*fs\n",
+ pdata->audout_layout ? 2 : 8,
+ audfmt_names[pdata->audout_format],
+ pdata->audout_layout,
+ pdata->audout_mclk_fs);
+ }
+
+ ret = 0x34 + ((io_read(sd, REG_SLAVE_ADDR)>>4) & 0x03);
+ state->client_cec = i2c_new_dummy(client->adapter, ret);
+ v4l_info(client, "CEC slave address 0x%02x\n", ret);
+
+ ret = tda1997x_core_init(sd);
+ if (ret)
+ goto err_free_mutex;
+
+ /* control handlers */
+ hdl = &state->hdl;
+ v4l2_ctrl_handler_init(hdl, 5);
+ ctrl = v4l2_ctrl_new_std_menu(hdl, &tda1997x_ctrl_ops,
+ V4L2_CID_DV_RX_IT_CONTENT_TYPE,
+ V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 0,
+ V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
+ if (ctrl)
+ ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
+ /* custom controls */
+ state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
+ V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
+ state->rgb_quantization_range_ctrl = v4l2_ctrl_new_std_menu(hdl,
+ &tda1997x_ctrl_ops,
+ V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 0,
+ V4L2_DV_RGB_RANGE_AUTO);
+
+ /* initialize source pads */
+ state->pads[TDA1997X_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
+ ret = media_entity_pads_init(&sd->entity, TDA1997X_NUM_PADS,
+ state->pads);
+ if (ret) {
+ v4l_err(client, "failed entity_init: %d", ret);
+ goto err_free_mutex;
+ }
+
+ ret = v4l2_async_register_subdev(sd);
+ if (ret)
+ goto err_free_media;
+
+ /* register audio DAI */
+ if (pdata->audout_format) {
+ u64 formats;
+
+ if (pdata->audout_width == 32)
+ formats = SNDRV_PCM_FMTBIT_S32_LE;
+ else
+ formats = SNDRV_PCM_FMTBIT_S16_LE;
+ tda1997x_audio_dai.capture.formats = formats;
+ ret = snd_soc_register_codec(&state->client->dev,
+ &tda1997x_codec_driver,
+ &tda1997x_audio_dai, 1);
+ if (ret) {
+ dev_err(&client->dev, "register audio codec failed\n");
+ goto err_free_media;
+ }
+ dev_set_drvdata(&state->client->dev, state);
+ v4l_info(state->client, "registered audio codec\n");
+ }
+
+ /* request irq */
+ ret = devm_request_threaded_irq(&client->dev, client->irq,
+ NULL, tda1997x_isr_thread,
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
+ KBUILD_MODNAME, state);
+ if (ret) {
+ v4l_err(client, "irq%d reg failed: %d\n", client->irq, ret);
+ goto err_free_media;
+ }
+
+ return 0;
+
+err_free_media:
+ media_entity_cleanup(&sd->entity);
+err_free_mutex:
+ cancel_delayed_work(&state->delayed_work_enable_hpd);
+ mutex_destroy(&state->page_lock);
+ mutex_destroy(&state->lock);
+err_free_state:
+ kfree(state);
+ dev_err(&client->dev, "%s failed: %d\n", __func__, ret);
+
+ return ret;
+}
+
+static int tda1997x_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct tda1997x_state *state = to_state(sd);
+ struct tda1997x_platform_data *pdata = &state->pdata;
+
+ if (pdata->audout_format) {
+ snd_soc_unregister_codec(&client->dev);
+ mutex_destroy(&state->audio_lock);
+ }
+
+ disable_irq(state->client->irq);
+ tda1997x_power_mode(state, 0);
+
+ v4l2_async_unregister_subdev(sd);
+ media_entity_cleanup(&sd->entity);
+ regulator_bulk_disable(TDA1997X_NUM_SUPPLIES, state->supplies);
+ i2c_unregister_device(state->client_cec);
+ cancel_delayed_work(&state->delayed_work_enable_hpd);
+ mutex_destroy(&state->page_lock);
+ mutex_destroy(&state->lock);
+
+ kfree(state);
+
+ return 0;
+}
+
+static struct i2c_driver tda1997x_i2c_driver = {
+ .driver = {
+ .name = "tda1997x",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(tda1997x_of_id),
+ },
+ .probe = tda1997x_probe,
+ .remove = tda1997x_remove,
+ .id_table = tda1997x_i2c_id,
+};
+
+module_i2c_driver(tda1997x_i2c_driver);
+
+MODULE_AUTHOR("Tim Harvey <tharvey@gateworks.com>");
+MODULE_DESCRIPTION("TDA1997X HDMI Receiver driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/media/i2c/tda1997x.h b/include/media/i2c/tda1997x.h
new file mode 100644
index 0000000..0ed3cc2
--- /dev/null
+++ b/include/media/i2c/tda1997x.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * tda1997x - NXP HDMI receiver
+ *
+ * Copyright 2017 Tim Harvey <tharvey@gateworks.com>
+ *
+ */
+
+#ifndef _TDA1997X_
+#define _TDA1997X_
+
+/* Platform Data */
+struct tda1997x_platform_data {
+ u32 vidout_bus_width;
+ u8 vidout_port_cfg[9];
+ /* pin polarity (1=invert) */
+ bool vidout_inv_de;
+ bool vidout_inv_hs;
+ bool vidout_inv_vs;
+ bool vidout_inv_pclk;
+ /* clock delays (0=-8, 1=-7 ... 15=+7 pixels) */
+ u8 vidout_delay_hs;
+ u8 vidout_delay_vs;
+ u8 vidout_delay_de;
+ u8 vidout_delay_pclk;
+ /* sync selections (controls how sync pins are derived) */
+ u8 vidout_sel_hs;
+ u8 vidout_sel_vs;
+ u8 vidout_sel_de;
+
+ /* Audio Port Output */
+ int audout_format;
+ u32 audout_mclk_fs; /* clock multiplier */
+ u32 audout_width; /* 13 or 32 bit */
+ u32 audout_layout; /* layout0=AP0 layout1=AP0,AP1,AP2,AP3 */
+ bool audout_layoutauto; /* audio layout dictated by pkt header */
+ bool audout_invert_clk; /* data valid on rising edge of BCLK */
+ bool audio_auto_mute; /* enable hardware audio auto-mute */
+};
+
+#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v6 5/6] ARM: dts: imx: Add TDA19971 HDMI Receiver to GW54xx
From: Tim Harvey @ 2017-12-28 20:09 UTC (permalink / raw)
To: linux-media-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A, Steve Longerbeam, Philipp Zabel,
Hans Verkuil, Mauro Carvalho Chehab
In-Reply-To: <1514491789-8697-1-git-send-email-tharvey-UMMOYl/HMS+akBO8gow8eQ@public.gmane.org>
The GW54xx has a front-panel microHDMI connector routed to a TDA19971
which is connected the the IPU CSI when using IMX6Q.
Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Tim Harvey <tharvey-UMMOYl/HMS+akBO8gow8eQ@public.gmane.org>
---
v6: no changes
v5:
- remove leading 0 from unit address (Shawn)
- add newline between property list and child node (Shawn)
v4: no changes
v3: no changes
v2:
- add HDMI audio input support
---
arch/arm/boot/dts/imx6q-gw54xx.dts | 105 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 29 +++++++++-
2 files changed, 131 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/imx6q-gw54xx.dts
index 56e5b50..0477120 100644
--- a/arch/arm/boot/dts/imx6q-gw54xx.dts
+++ b/arch/arm/boot/dts/imx6q-gw54xx.dts
@@ -12,10 +12,30 @@
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw54xx.dtsi"
+#include <dt-bindings/media/tda1997x.h>
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
+
+ sound-digital {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "tda1997x-audio";
+
+ simple-audio-card,dai-link@0 {
+ format = "i2s";
+
+ cpu {
+ sound-dai = <&ssi2>;
+ };
+
+ codec {
+ bitclock-master;
+ frame-master;
+ sound-dai = <&tda1997x>;
+ };
+ };
+ };
};
&i2c3 {
@@ -35,6 +55,61 @@
};
};
};
+
+ tda1997x: codec@48 {
+ compatible = "nxp,tda19971";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tda1997x>;
+ reg = <0x48>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ DOVDD-supply = <®_3p3v>;
+ AVDD-supply = <&sw4_reg>;
+ DVDD-supply = <&sw4_reg>;
+ #sound-dai-cells = <0>;
+ nxp,audout-format = "i2s";
+ nxp,audout-layout = <0>;
+ nxp,audout-width = <16>;
+ nxp,audout-mclk-fs = <128>;
+ /*
+ * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
+ * and Y[11:4] across 16bits in the same cycle
+ * which we map to VP[15:08]<->CSI_DATA[19:12]
+ */
+ nxp,vidout-portcfg =
+ /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
+ < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
+ /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
+ < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
+ /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
+ < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
+ /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
+ < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
+
+ port {
+ tda1997x_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <16>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ data-active = <1>;
+ };
+ };
+ };
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <16>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
+ bus-width = <16>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&ipu2_csi1_from_ipu2_csi1_mux {
@@ -63,6 +138,30 @@
>;
};
+ pinctrl_ipu1_csi0: ipu1_csi0grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
+ >;
+ };
+
pinctrl_ipu2_csi1: ipu2_csi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
@@ -78,4 +177,10 @@
MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
>;
};
+
+ pinctrl_tda1997x: tda1997xgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
+ >;
+ };
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index eab75f3..f9e1fb9 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -10,6 +10,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
/* these are used by bootloader for disabling nodes */
@@ -114,12 +115,12 @@
};
};
- sound {
+ sound-analog {
compatible = "fsl,imx6q-ventana-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "sgtl5000-audio";
ssi-controller = <&ssi1>;
- audio-codec = <&codec>;
+ audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
@@ -133,6 +134,25 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
status = "okay";
+
+ ssi2 {
+ fsl,audmux-port = <1>;
+ fsl,port-config = <
+ (IMX_AUDMUX_V2_PTCR_TFSDIR |
+ IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
+ IMX_AUDMUX_V2_PTCR_TCLKDIR |
+ IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
+ IMX_AUDMUX_V2_PTCR_SYN)
+ IMX_AUDMUX_V2_PDCR_RXDSEL(4)
+ >;
+ };
+
+ aud5 {
+ fsl,audmux-port = <4>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN
+ IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
+ };
};
&can1 {
@@ -331,7 +351,7 @@
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
- codec: sgtl5000@a {
+ sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
@@ -475,6 +495,9 @@
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
+ MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
+ MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0
>;
};
--
2.7.4
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^ permalink raw reply related
* [PATCH v6 6/6] ARM: dts: imx: Add TDA19971 HDMI Receiver to GW551x
From: Tim Harvey @ 2017-12-28 20:09 UTC (permalink / raw)
To: linux-media, alsa-devel
Cc: devicetree, linux-kernel, shawnguo, Steve Longerbeam,
Philipp Zabel, Hans Verkuil, Mauro Carvalho Chehab
In-Reply-To: <1514491789-8697-1-git-send-email-tharvey@gateworks.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
v6: no changes
v5:
- add missing audmux config
---
arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 138 ++++++++++++++++++++++++++++++++++
1 file changed, 138 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
index 30d4662..749548a 100644
--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
@@ -46,6 +46,8 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/tda1997x.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
/* these are used by bootloader for disabling nodes */
@@ -98,6 +100,50 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ sound-digital {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "tda1997x-audio";
+
+ simple-audio-card,dai-link@0 {
+ format = "i2s";
+
+ cpu {
+ sound-dai = <&ssi2>;
+ };
+
+ codec {
+ bitclock-master;
+ frame-master;
+ sound-dai = <&tda1997x>;
+ };
+ };
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */
+ status = "okay";
+
+ ssi1 {
+ fsl,audmux-port = <0>;
+ fsl,port-config = <
+ (IMX_AUDMUX_V2_PTCR_TFSDIR |
+ IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
+ IMX_AUDMUX_V2_PTCR_TCLKDIR |
+ IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
+ IMX_AUDMUX_V2_PTCR_SYN)
+ IMX_AUDMUX_V2_PDCR_RXDSEL(4)
+ >;
+ };
+
+ aud5 {
+ fsl,audmux-port = <4>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN
+ IMX_AUDMUX_V2_PDCR_RXDSEL(0)>;
+ };
};
&can1 {
@@ -263,6 +309,60 @@
#gpio-cells = <2>;
};
+ tda1997x: tda1997x@48 {
+ compatible = "nxp,tda19971";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tda1997x>;
+ reg = <0x48>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ DOVDD-supply = <®_3p3>;
+ AVDD-supply = <®_1p8b>;
+ DVDD-supply = <®_1p8a>;
+ #sound-dai-cells = <0>;
+ nxp,audout-format = "i2s";
+ nxp,audout-layout = <0>;
+ nxp,audout-width = <16>;
+ nxp,audout-mclk-fs = <128>;
+ /*
+ * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
+ * and Y[11:4] across 16bits in the same cycle
+ * which we map to VP[15:08]<->CSI_DATA[19:12]
+ */
+ nxp,vidout-portcfg =
+ /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
+ < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
+ /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
+ < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
+ /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
+ < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
+ /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
+ < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
+
+ port {
+ tda1997x_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <16>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ data-active = <1>;
+ };
+ };
+ };
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <16>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
+ bus-width = <16>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&pcie {
@@ -320,6 +420,14 @@
};
&iomuxc {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
+ MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0
+ >;
+ };
+
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
@@ -375,6 +483,30 @@
>;
};
+ pinctrl_ipu1_csi0: ipu1_csi0grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
@@ -399,6 +531,12 @@
>;
};
+ pinctrl_tda1997x: tda1997xgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
--
2.7.4
^ permalink raw reply related
* Re: [PATCH 2/7] watchdog: jz4740: Use devm_* functions
From: Guenter Roeck @ 2017-12-28 20:19 UTC (permalink / raw)
To: Paul Cercueil
Cc: Ralf Baechle, Rob Herring, Mark Rutland, Wim Van Sebroeck,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1514491167.6093.0-nb6JAIIttxhEPksTRSfcJOTW4wlIGRCZ@public.gmane.org>
On 12/28/2017 11:59 AM, Paul Cercueil wrote:
> Hi Guenter,
>
> Le jeu. 28 déc. 2017 à 18:48, Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org> a écrit :
>> On 12/28/2017 08:29 AM, Paul Cercueil wrote:
>>> - Use devm_clk_get instead of clk_get
>>> - Use devm_watchdog_register_device instead of watchdog_register_device
>>>
>>> Signed-off-by: Paul Cercueil <paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
>>> ---
>>> drivers/watchdog/jz4740_wdt.c | 27 ++++++++-------------------
>>> 1 file changed, 8 insertions(+), 19 deletions(-)
>>>
>>> diff --git a/drivers/watchdog/jz4740_wdt.c b/drivers/watchdog/jz4740_wdt.c
>>> index 6955deb100ef..92d6ca8ceb49 100644
>>> --- a/drivers/watchdog/jz4740_wdt.c
>>> +++ b/drivers/watchdog/jz4740_wdt.c
>>> @@ -178,40 +178,29 @@ static int jz4740_wdt_probe(struct platform_device *pdev)
>>> \x7f res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> drvdata->base = devm_ioremap_resource(&pdev->dev, res);
>>> - if (IS_ERR(drvdata->base)) {
>>> - ret = PTR_ERR(drvdata->base);
>>> - goto err_out;
>>> - }
>>> + if (IS_ERR(drvdata->base))
>>> + return PTR_ERR(drvdata->base);
>>> \x7f- drvdata->rtc_clk = clk_get(&pdev->dev, "rtc");
>>> + drvdata->rtc_clk = devm_clk_get(&pdev->dev, "rtc");
>>> if (IS_ERR(drvdata->rtc_clk)) {
>>> dev_err(&pdev->dev, "cannot find RTC clock\n");
>>> - ret = PTR_ERR(drvdata->rtc_clk);
>>> - goto err_out;
>>> + return PTR_ERR(drvdata->rtc_clk);
>>> }
>>> \x7f- ret = watchdog_register_device(&drvdata->wdt);
>>> + ret = devm_watchdog_register_device(&pdev->dev, &drvdata->wdt);
>>> if (ret < 0)
>>> - goto err_disable_clk;
>>> + return ret;
>>> \x7f platform_set_drvdata(pdev, drvdata);
>>> - return 0;
>>> \x7f-err_disable_clk:
>>> - clk_put(drvdata->rtc_clk);
>>> -err_out:
>>> - return ret;
>>> + return 0;
>>> }
>>> \x7f static int jz4740_wdt_remove(struct platform_device *pdev)
>>> {
>>> struct jz4740_wdt_drvdata *drvdata = platform_get_drvdata(pdev);
>>> \x7f- jz4740_wdt_stop(&drvdata->wdt);
>>> - watchdog_unregister_device(&drvdata->wdt);
>>> - clk_put(drvdata->rtc_clk);
>>> -
>>> - return 0;
>>> + return jz4740_wdt_stop(&drvdata->wdt);
>>
>> If the watchdog is running, the module can not be unloaded. Even if that wasn't
>> the case, this defeats both WDIOF_MAGICCLOSE and watchdog_set_nowayout().
>> Are you sure this is what you want ? If so, please call
>> watchdog_stop_on_unregister() before registration; this clarifies that this
>> is what you want, and you can drop the remove function.
>>
>> Thanks,
>> Guenter
>
> This patch does not change the behaviour. We always used that driver built-in; what
> should the behaviour be when unloading the module? Keep the watchdog hardware running
> if configured for 'nowayout'?
>
One can still unload the driver. If you are fine with bypassing/dfeating nowayout
and WDIOF_MAGICCLOSE, may I ask why those are enabled in the first place ?
Thanks,
Guenter
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^ permalink raw reply
* Re: [PATCH 2/7] watchdog: jz4740: Use devm_* functions
From: Paul Cercueil @ 2017-12-28 20:22 UTC (permalink / raw)
To: Guenter Roeck
Cc: Ralf Baechle, Rob Herring, Mark Rutland, Wim Van Sebroeck,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <994187b3-113c-88ef-8ebd-cd57d0c833a0-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
Le jeu. 28 déc. 2017 à 21:19, Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org> a
écrit :
> On 12/28/2017 11:59 AM, Paul Cercueil wrote:
>> Hi Guenter,
>>
>> Le jeu. 28 déc. 2017 à 18:48, Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org> a
>> écrit :
>>> On 12/28/2017 08:29 AM, Paul Cercueil wrote:
>>>> - Use devm_clk_get instead of clk_get
>>>> - Use devm_watchdog_register_device instead of
>>>> watchdog_register_device
>>>>
>>>> Signed-off-by: Paul Cercueil <paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
>>>> ---
>>>> drivers/watchdog/jz4740_wdt.c | 27 ++++++++-------------------
>>>> 1 file changed, 8 insertions(+), 19 deletions(-)
>>>>
>>>> diff --git a/drivers/watchdog/jz4740_wdt.c
>>>> b/drivers/watchdog/jz4740_wdt.c
>>>> index 6955deb100ef..92d6ca8ceb49 100644
>>>> --- a/drivers/watchdog/jz4740_wdt.c
>>>> +++ b/drivers/watchdog/jz4740_wdt.c
>>>> @@ -178,40 +178,29 @@ static int jz4740_wdt_probe(struct
>>>> platform_device *pdev)
>>>> \x7f res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>> drvdata->base = devm_ioremap_resource(&pdev->dev, res);
>>>> - if (IS_ERR(drvdata->base)) {
>>>> - ret = PTR_ERR(drvdata->base);
>>>> - goto err_out;
>>>> - }
>>>> + if (IS_ERR(drvdata->base))
>>>> + return PTR_ERR(drvdata->base);
>>>> \x7f- drvdata->rtc_clk = clk_get(&pdev->dev, "rtc");
>>>> + drvdata->rtc_clk = devm_clk_get(&pdev->dev, "rtc");
>>>> if (IS_ERR(drvdata->rtc_clk)) {
>>>> dev_err(&pdev->dev, "cannot find RTC clock\n");
>>>> - ret = PTR_ERR(drvdata->rtc_clk);
>>>> - goto err_out;
>>>> + return PTR_ERR(drvdata->rtc_clk);
>>>> }
>>>> \x7f- ret = watchdog_register_device(&drvdata->wdt);
>>>> + ret = devm_watchdog_register_device(&pdev->dev,
>>>> &drvdata->wdt);
>>>> if (ret < 0)
>>>> - goto err_disable_clk;
>>>> + return ret;
>>>> \x7f platform_set_drvdata(pdev, drvdata);
>>>> - return 0;
>>>> \x7f-err_disable_clk:
>>>> - clk_put(drvdata->rtc_clk);
>>>> -err_out:
>>>> - return ret;
>>>> + return 0;
>>>> }
>>>> \x7f static int jz4740_wdt_remove(struct platform_device *pdev)
>>>> {
>>>> struct jz4740_wdt_drvdata *drvdata =
>>>> platform_get_drvdata(pdev);
>>>> \x7f- jz4740_wdt_stop(&drvdata->wdt);
>>>> - watchdog_unregister_device(&drvdata->wdt);
>>>> - clk_put(drvdata->rtc_clk);
>>>> -
>>>> - return 0;
>>>> + return jz4740_wdt_stop(&drvdata->wdt);
>>>
>>> If the watchdog is running, the module can not be unloaded. Even if
>>> that wasn't
>>> the case, this defeats both WDIOF_MAGICCLOSE and
>>> watchdog_set_nowayout().
>>> Are you sure this is what you want ? If so, please call
>>> watchdog_stop_on_unregister() before registration; this clarifies
>>> that this
>>> is what you want, and you can drop the remove function.
>>>
>>> Thanks,
>>> Guenter
>>
>> This patch does not change the behaviour. We always used that driver
>> built-in; what
>> should the behaviour be when unloading the module? Keep the watchdog
>> hardware running
>> if configured for 'nowayout'?
>>
>
> One can still unload the driver. If you are fine with
> bypassing/dfeating nowayout
> and WDIOF_MAGICCLOSE, may I ask why those are enabled in the first
> place ?
>
Who knows? That code is very old :)
I'm fine with removing the remove() function completely, if you think
it makes more sense.
Thanks,
-Paul
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^ permalink raw reply
* Re: [PATCH 0/4] Sunxi: Add SMP support on A83T
From: Corentin Labbe @ 2017-12-28 20:31 UTC (permalink / raw)
To: Mylene JOSSERAND
Cc: Maxime Ripard, wens-jdAy2FN1RRM, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20171227160729.4509bec5-K8i4uRanGBt8XcdJbWeDu7NAH6kLmebB@public.gmane.org>
On Wed, Dec 27, 2017 at 04:07:29PM +0100, Mylene JOSSERAND wrote:
> Hello Corentin,
>
> Le Fri, 15 Dec 2017 07:10:46 +0100,
> Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> a écrit :
> > On Tue, Dec 12, 2017 at 09:24:25AM +0100, Maxime Ripard wrote:
> > > Hi,
> > >
> > > On Mon, Dec 11, 2017 at 08:35:34PM +0100, Corentin Labbe wrote:
> > > > On Mon, Dec 11, 2017 at 08:49:57AM +0100, Mylène Josserand wrote:
> > > > > This series adds SMP support for Allwinner Sun8i-a83t
> > > > > with MCPM (Multi-Cluster Power Management).
> > > > > Series information:
> > > > > - Based on last linux-next (next-20171211)
> > > > > - Had dependencies on Chen Yu's patch that add MCPM
> > > > > support:
> > > > > https://patchwork.kernel.org/patch/6402801/
> > > > >
> > > > > Patch 01: Convert the mcpm driver (initially for A80) to be able
> > > > > to use it for A83T. This SoC has a bit flip that needs to be handled.
> > > > > Patch 02: Add registers nodes (prcm, cpucfg and r_cpucfg) needed
> > > > > for MCPM.
> > > > > Patch 03: Add CCI-400 node for a83t.
> > > > > Patch 04: Fix the use of virtual timers that hangs the kernel in
> > > > > case of SMP support.
> > > >
> > > > As we discussed in private, Chen Yu's patch should be added in your series.
> > >
> > > Not really, she mentionned the dependency in the cover letter, and
> > > it's a good way to do things too. Sure, you can do it your way, but
> > > there's no preference.
> > >
> >
> > If the goal of this series is to be applied, the dependency must be applied also.
> > And since the dependency is 2 years old (and part of a serie which does not apply now), I think cherry picking the patch and send it for review is better.
> >
> > > > Furthermore, MCPM is not automaticaly selected via imply.
> > >
> > > Well, yes, is that an issue?
> > >
> >
> > After reading the imply documentation, no.
> >
> > > > With all patchs I hit a bug:
> > > > [ 0.898668] BUG: sleeping function called from invalid context at kernel/locking/mutex.c:238
> > >
> > > I guess this is with CONFIG_PROVE_LOCKING enabled?
> > >
> >
> > No, the BUG() printed is enabled by default
> >
> > > > [ 0.911162] in_atomic(): 1, irqs_disabled(): 0, pid: 1, name: swapper/0
> > > > [ 0.917776] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.15.0-rc2-next-20171211+ #73
> > >
> > > What are the changes you've made?
> > >
> >
> > Just adding wens's patch and this series.
>
> I tried to reproduce your issue without success (even with
> CONFIG_PROVE_LOCKING enabled, just in case).
> Can you give me more details about your tests? which defconfig and
> additional configurations?
>
> >
> > > > [ 0.925418] Hardware name: Allwinner sun8i Family
> > > > [ 0.930118] Backtrace:
> > > > [ 0.932596] [<c010cc50>] (dump_backtrace) from [<c010cf0c>] (show_stack+0x18/0x1c)
> > > > [ 0.940158] r7:c0b261e4 r6:60000013 r5:00000000 r4:c0b51958
> > > > [ 0.945820] [<c010cef4>] (show_stack) from [<c06baccc>] (dump_stack+0x8c/0xa0)
> > > > [ 0.953045] [<c06bac40>] (dump_stack) from [<c0149d40>] (___might_sleep+0x150/0x170)
> > > > [ 0.960779] r7:c0b261e4 r6:00000000 r5:000000ee r4:ee844000
> > > > [ 0.966437] [<c0149bf0>] (___might_sleep) from [<c0149dc8>] (__might_sleep+0x68/0xa0)
> > > > [ 0.974253] r4:c0861690
> > > > [ 0.976796] [<c0149d60>] (__might_sleep) from [<c06d2918>] (mutex_lock+0x24/0x68)
> > > > [ 0.984269] r6:c0892f6c r5:ffffffff r4:c0b1bb24
> > > > [ 0.988891] [<c06d28f4>] (mutex_lock) from [<c01ccb6c>] (perf_pmu_register+0x24/0x3e4)
> > > > [ 0.996795] r5:ffffffff r4:ee98b014
> > > > [ 1.000375] [<c01ccb48>] (perf_pmu_register) from [<c03efabc>] (cci_pmu_probe+0x340/0x484)
> > > > [ 1.008631] r10:c0892f6c r9:c0bfd5f0 r8:eea19010 r7:c0b261e4 r6:c0b26240 r5:eea19000
> > > > [ 1.016447] r4:ee98b010
> > > > [ 1.018989] [<c03ef77c>] (cci_pmu_probe) from [<c045e21c>] (platform_drv_probe+0x58/0xb8)
> > > > [ 1.027158] r10:00000000 r9:c0b2610c r8:00000000 r7:fffffdfb r6:c0b2610c r5:ffffffed
> > > > [ 1.034974] r4:eea19010
> > > > [ 1.037511] [<c045e1c4>] (platform_drv_probe) from [<c045c984>] (driver_probe_device+0x254/0x330)
> > > > [ 1.046371] r7:00000000 r6:c0bff498 r5:c0bff494 r4:eea19010
> > > > [ 1.052026] [<c045c730>] (driver_probe_device) from [<c045cbc4>] (__device_attach_driver+0xa0/0xd4)
> > > > [ 1.061062] r10:00000000 r9:c0bff470 r8:00000000 r7:00000001 r6:eea19010 r5:ee845ac0
> > > > [ 1.068879] r4:c0b2610c r3:00000000
> > > > [ 1.072454] [<c045cb24>] (__device_attach_driver) from [<c045ad68>] (bus_for_each_drv+0x68/0x9c)
> > > > [ 1.081228] r7:00000001 r6:c045cb24 r5:ee845ac0 r4:00000000
> > > > [ 1.086883] [<c045ad00>] (bus_for_each_drv) from [<c045c60c>] (__device_attach+0xb8/0x11c)
> > > > [ 1.095135] r6:c0b3e848 r5:eea19044 r4:eea19010
> > > > [ 1.099750] [<c045c554>] (__device_attach) from [<c045cc44>] (device_initial_probe+0x14/0x18)
> > > > [ 1.108263] r7:c0b0a4c8 r6:c0b3e848 r5:eea19010 r4:eea19018
> > > > [ 1.113919] [<c045cc30>] (device_initial_probe) from [<c045bb58>] (bus_probe_device+0x8c/0x94)
> > > > [ 1.122523] [<c045bacc>] (bus_probe_device) from [<c0459db8>] (device_add+0x40c/0x5a0)
> > > > [ 1.130429] r7:c0b0a4c8 r6:eea19010 r5:eea18a10 r4:eea19018
> > > > [ 1.136089] [<c04599ac>] (device_add) from [<c0582a58>] (of_device_add+0x3c/0x44)
> > > > [ 1.143564] r10:00000000 r9:00000000 r8:00000000 r7:eedf21a4 r6:eea18a10 r5:00000000
> > > > [ 1.151380] r4:eea19000
> > > > [ 1.153915] [<c0582a1c>] (of_device_add) from [<c0582f80>] (of_platform_device_create_pdata+0x7c/0xac)
> > > > [ 1.163210] [<c0582f04>] (of_platform_device_create_pdata) from [<c0583100>] (of_platform_bus_create+0xf4/0x1f0)
> > > > [ 1.173372] r9:00000000 r8:00000000 r7:00000001 r6:00000000 r5:eedf2154 r4:00000000
> > > > [ 1.181107] [<c058300c>] (of_platform_bus_create) from [<c0583374>] (of_platform_populate+0x74/0xd4)
> > > > [ 1.190229] r10:00000001 r9:eea18a10 r8:00000000 r7:00000000 r6:00000000 r5:eedf1d04
> > > > [ 1.198045] r4:eedf2154
> > > > [ 1.200580] [<c0583300>] (of_platform_populate) from [<c03ef2a8>] (cci_platform_probe+0x3c/0x54)
> > > > [ 1.209356] r10:00000000 r9:c0b26168 r8:00000000 r7:fffffdfb r6:c0b26168 r5:ffffffed
> > > > [ 1.217172] r4:eea18a00
> > > > [ 1.219708] [<c03ef26c>] (cci_platform_probe) from [<c045e21c>] (platform_drv_probe+0x58/0xb8)
> > > > [ 1.228306] r5:ffffffed r4:eea18a10
> > > > [ 1.231881] [<c045e1c4>] (platform_drv_probe) from [<c045c984>] (driver_probe_device+0x254/0x330)
> > > > [ 1.240742] r7:00000000 r6:c0bff498 r5:c0bff494 r4:eea18a10
> > > > [ 1.246397] [<c045c730>] (driver_probe_device) from [<c045cbc4>] (__device_attach_driver+0xa0/0xd4)
> > > > [ 1.255433] r10:00000000 r9:c0bff470 r8:00000000 r7:00000001 r6:eea18a10 r5:ee845ce8
> > > > [ 1.263250] r4:c0b26168 r3:00000000
> > > > [ 1.266825] [<c045cb24>] (__device_attach_driver) from [<c045ad68>] (bus_for_each_drv+0x68/0x9c)
> > > > [ 1.275598] r7:00000001 r6:c045cb24 r5:ee845ce8 r4:00000000
> > > > [ 1.281253] [<c045ad00>] (bus_for_each_drv) from [<c045c60c>] (__device_attach+0xb8/0x11c)
> > > > [ 1.289506] r6:c0b3e848 r5:eea18a44 r4:eea18a10
> > > > [ 1.294120] [<c045c554>] (__device_attach) from [<c045cc44>] (device_initial_probe+0x14/0x18)
> > > > [ 1.302633] r7:c0b0a4c8 r6:c0b3e848 r5:eea18a10 r4:eea18a18
> > > > [ 1.308288] [<c045cc30>] (device_initial_probe) from [<c045bb58>] (bus_probe_device+0x8c/0x94)
> > > > [ 1.316890] [<c045bacc>] (bus_probe_device) from [<c0459db8>] (device_add+0x40c/0x5a0)
> > > > [ 1.324796] r7:c0b0a4c8 r6:eea18a10 r5:ee993810 r4:eea18a18
> > > > [ 1.330450] [<c04599ac>] (device_add) from [<c0582a58>] (of_device_add+0x3c/0x44)
> > > > [ 1.337926] r10:00000000 r9:c07759d8 r8:00000000 r7:eedf1d54 r6:ee993810 r5:00000000
> > > > [ 1.345743] r4:eea18a00
> > > > [ 1.348277] [<c0582a1c>] (of_device_add) from [<c0582f80>] (of_platform_device_create_pdata+0x7c/0xac)
> > > > [ 1.357572] [<c0582f04>] (of_platform_device_create_pdata) from [<c0583100>] (of_platform_bus_create+0xf4/0x1f0)
> > > > [ 1.367734] r9:c07759d8 r8:00000000 r7:00000001 r6:00000000 r5:eedf1d04 r4:00000000
> > > > [ 1.375469] [<c058300c>] (of_platform_bus_create) from [<c058315c>] (of_platform_bus_create+0x150/0x1f0)
> > > > [ 1.384938] r10:ee993810 r9:c07759d8 r8:00000000 r7:00000001 r6:00000000 r5:eedefe1c
> > > > [ 1.392754] r4:eedf1d04
> > > > [ 1.395289] [<c058300c>] (of_platform_bus_create) from [<c0583374>] (of_platform_populate+0x74/0xd4)
> > > > [ 1.404411] r10:00000001 r9:00000000 r8:00000000 r7:c07759d8 r6:00000000 r5:eedee844
> > > > [ 1.412228] r4:eedefe1c
> > > > [ 1.414769] [<c0583300>] (of_platform_populate) from [<c0a25ee8>] (of_platform_default_populate_init+0x80/0x94)
> > > > [ 1.424844] r10:c0a37848 r9:00000000 r8:c0b59680 r7:c0a37834 r6:ffffe000 r5:c0775ce8
> > > > [ 1.432661] r4:00000000
> > > > [ 1.435200] [<c0a25e68>] (of_platform_default_populate_init) from [<c0102794>] (do_one_initcall+0x5c/0x194)
> > > > [ 1.444925] r5:c0a25e68 r4:c0b0a4c8
> > > > [ 1.448506] [<c0102738>] (do_one_initcall) from [<c0a00f88>] (kernel_init_freeable+0x1d4/0x268)
> > > > [ 1.457195] r9:00000004 r8:c0b59680 r7:c0a37834 r6:c0b59680 r5:c0a47308 r4:c090cfb8
> > > > [ 1.464932] [<c0a00db4>] (kernel_init_freeable) from [<c06cf3b0>] (kernel_init+0x10/0x118)
> > > > [ 1.473187] r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c06cf3a0
> > > > [ 1.481004] r4:00000000
> > > > [ 1.483540] [<c06cf3a0>] (kernel_init) from [<c01010e8>] (ret_from_fork+0x14/0x2c)
> > > > [ 1.491098] Exception stack(0xee845fb0 to 0xee845ff8)
> > > > [ 1.496146] 5fa0: 00000000 00000000 00000000 00000000
> > > > [ 1.504313] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> > > > [ 1.512480] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000
> > > > [ 1.519084] r5:c06cf3a0 r4:00000000
> > > > [ 1.522737] ARM CCI_400_r1 PMU driver probed
> > > >
> > > > And only CPU 0 show up.
> > >
> > > This looks more like a bug in the CCI code, and not in this serie
> > > itself. Can you share your whole boot logs?
> > >
> >
> > This week end I will retry and send it.
>
> By any chance, did you try it again? Can you reproduce it on your side?
>
Hello
With the .config that you give me in private, everything seems to work.
But with mine, the stacktrace still happen.
After some research, this is due to the following code:
cpumask_set_cpu(get_cpu(), &cci_pmu->cpus);
which disable preemption (via get_cpu())
So it is unrelated with your patch, I will send a bug report tomorow.
Furthermore, you can add:
Tested-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Thanks
Regards
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* Re: [PATCH 2/7] watchdog: jz4740: Use devm_* functions
From: Guenter Roeck @ 2017-12-28 21:03 UTC (permalink / raw)
To: Paul Cercueil
Cc: Ralf Baechle, Rob Herring, Mark Rutland, Wim Van Sebroeck,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1514492538.6093.1-nb6JAIIttxhEPksTRSfcJOTW4wlIGRCZ@public.gmane.org>
On 12/28/2017 12:22 PM, Paul Cercueil wrote:
>
>
> Le jeu. 28 déc. 2017 à 21:19, Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org> a écrit :
>> On 12/28/2017 11:59 AM, Paul Cercueil wrote:
>>> Hi Guenter,
>>>
>>> Le jeu. 28 déc. 2017 à 18:48, Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org> a écrit :
>>>> On 12/28/2017 08:29 AM, Paul Cercueil wrote:
>>>>> - Use devm_clk_get instead of clk_get
>>>>> - Use devm_watchdog_register_device instead of watchdog_register_device
>>>>>
>>>>> Signed-off-by: Paul Cercueil <paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
>>>>> ---
>>>>> drivers/watchdog/jz4740_wdt.c | 27 ++++++++-------------------
>>>>> 1 file changed, 8 insertions(+), 19 deletions(-)
>>>>>
>>>>> diff --git a/drivers/watchdog/jz4740_wdt.c b/drivers/watchdog/jz4740_wdt.c
>>>>> index 6955deb100ef..92d6ca8ceb49 100644
>>>>> --- a/drivers/watchdog/jz4740_wdt.c
>>>>> +++ b/drivers/watchdog/jz4740_wdt.c
>>>>> @@ -178,40 +178,29 @@ static int jz4740_wdt_probe(struct platform_device *pdev)
>>>>> \x7f res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>>> drvdata->base = devm_ioremap_resource(&pdev->dev, res);
>>>>> - if (IS_ERR(drvdata->base)) {
>>>>> - ret = PTR_ERR(drvdata->base);
>>>>> - goto err_out;
>>>>> - }
>>>>> + if (IS_ERR(drvdata->base))
>>>>> + return PTR_ERR(drvdata->base);
>>>>> \x7f- drvdata->rtc_clk = clk_get(&pdev->dev, "rtc");
>>>>> + drvdata->rtc_clk = devm_clk_get(&pdev->dev, "rtc");
>>>>> if (IS_ERR(drvdata->rtc_clk)) {
>>>>> dev_err(&pdev->dev, "cannot find RTC clock\n");
>>>>> - ret = PTR_ERR(drvdata->rtc_clk);
>>>>> - goto err_out;
>>>>> + return PTR_ERR(drvdata->rtc_clk);
>>>>> }
>>>>> \x7f- ret = watchdog_register_device(&drvdata->wdt);
>>>>> + ret = devm_watchdog_register_device(&pdev->dev, &drvdata->wdt);
>>>>> if (ret < 0)
>>>>> - goto err_disable_clk;
>>>>> + return ret;
>>>>> \x7f platform_set_drvdata(pdev, drvdata);
>>>>> - return 0;
>>>>> \x7f-err_disable_clk:
>>>>> - clk_put(drvdata->rtc_clk);
>>>>> -err_out:
>>>>> - return ret;
>>>>> + return 0;
>>>>> }
>>>>> \x7f static int jz4740_wdt_remove(struct platform_device *pdev)
>>>>> {
>>>>> struct jz4740_wdt_drvdata *drvdata = platform_get_drvdata(pdev);
>>>>> \x7f- jz4740_wdt_stop(&drvdata->wdt);
>>>>> - watchdog_unregister_device(&drvdata->wdt);
>>>>> - clk_put(drvdata->rtc_clk);
>>>>> -
>>>>> - return 0;
>>>>> + return jz4740_wdt_stop(&drvdata->wdt);
>>>>
>>>> If the watchdog is running, the module can not be unloaded. Even if that wasn't
>>>> the case, this defeats both WDIOF_MAGICCLOSE and watchdog_set_nowayout().
>>>> Are you sure this is what you want ? If so, please call
>>>> watchdog_stop_on_unregister() before registration; this clarifies that this
>>>> is what you want, and you can drop the remove function.
>>>>
>>>> Thanks,
>>>> Guenter
>>>
>>> This patch does not change the behaviour. We always used that driver built-in; what
>>> should the behaviour be when unloading the module? Keep the watchdog hardware running
>>> if configured for 'nowayout'?
>>>
>>
>> One can still unload the driver. If you are fine with bypassing/dfeating nowayout
>> and WDIOF_MAGICCLOSE, may I ask why those are enabled in the first place ?
>>
>
> Who knows? That code is very old :)
Probably copied from some other driver w/o thinking much about it.
> I'm fine with removing the remove() function completely, if you think it makes more sense.
>
Yes, I do, but I won't insist on it either.
Thanks,
Guenter
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* Re: [PATCH v2] arm64: dts: Hi3660: Fix up psci state id
From: Wei Xu @ 2017-12-28 21:14 UTC (permalink / raw)
To: Leo Yan, Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: Vincent Guittot, Daniel Lezcano, Sudeep Holla, Soby Mathew
In-Reply-To: <5A3CD23C.3080307-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Hi Leo,
On 2017/12/22 9:37, Wei Xu wrote:
> Hi Leo,
>
> On 2017/12/12 9:12, Leo Yan wrote:
>> Thanks a lot for Vincent Guittot careful work to find bug for 'CPU_NAP'
>> idle state. From ftrace log we can observe CA73 CPUs can be easily
>> waken up from 'CPU_NAP' state but the 'waken up' CPUs doesn't handle
>> anything and sleep again; so there have tons of trace events for CA73
>> CPUs entering and exiting idle state.
>>
>> On Hi3660 CA73 has retention state 'CPU_NAP' for CPU idle, this state we
>> set its psci parameter as '0x0000001' and from this parameter it can
>> calculate state id is 1. Unfortunately ARM trusted firmware (ARM-TF)
>> takes 1 as a invalid value for state id, so the CPU cannot enter idle
>> state and directly bail out to kernel.
>>
>> We want to create good practice for psci parameters platform definition,
>> so review the psci specification. The spec "ARM Power State Coordination
>> Interface - Platform Design Document (ARM DEN 0022D)" recommends state
>> ID in chapter "6.5 Recommended StateID Encoding". The recommended power
>> state IDs can be presented by below listed values; and it divides into
>> three fields, every field can use 4 bits to present power states
>> corresponding to core level, cluster level and system level:
>> 0: Run
>> 1: Standby
>> 2: Retention
>> 3: Powerdown
>>
>> This commit changes psci parameter to compliance with the suggested
>> state ID in the doc. Except we change 'CPU_NAP' state psci parameter
>> to '0x0000002', this commit also changes 'CPU_SLEEP' and 'CLUSTER_SLEEP'
>> state parameters to '0x0010003' and '0x1010033' respectively.
>>
>> Credits to Daniel, Sudeep and Soby for suggestion and consolidation.
>>
>> Cc: Vincent Guittot <vincent.guittot-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> Cc: Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> Cc: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
>> Cc: Soby Mathew <Soby.Mathew-5wv7dgnIgG8@public.gmane.org>
>> Signed-off-by: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> ---
>
> Applied into hisilicon dt tree.
> Thanks!
Sorry, since this patch is still under discussion,
I will drop it firstly.
Thanks!
Best Regards,
Wei
>
> Best Regards,
> Wei
>
>> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> index ab0b95b..99d5a46 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> @@ -147,7 +147,7 @@
>>
>> CPU_NAP: cpu-nap {
>> compatible = "arm,idle-state";
>> - arm,psci-suspend-param = <0x0000001>;
>> + arm,psci-suspend-param = <0x0000002>;
>> entry-latency-us = <7>;
>> exit-latency-us = <2>;
>> min-residency-us = <15>;
>> @@ -156,7 +156,7 @@
>> CPU_SLEEP: cpu-sleep {
>> compatible = "arm,idle-state";
>> local-timer-stop;
>> - arm,psci-suspend-param = <0x0010000>;
>> + arm,psci-suspend-param = <0x0010003>;
>> entry-latency-us = <40>;
>> exit-latency-us = <70>;
>> min-residency-us = <3000>;
>> @@ -165,7 +165,7 @@
>> CLUSTER_SLEEP_0: cluster-sleep-0 {
>> compatible = "arm,idle-state";
>> local-timer-stop;
>> - arm,psci-suspend-param = <0x1010000>;
>> + arm,psci-suspend-param = <0x1010033>;
>> entry-latency-us = <500>;
>> exit-latency-us = <5000>;
>> min-residency-us = <20000>;
>> @@ -174,7 +174,7 @@
>> CLUSTER_SLEEP_1: cluster-sleep-1 {
>> compatible = "arm,idle-state";
>> local-timer-stop;
>> - arm,psci-suspend-param = <0x1010000>;
>> + arm,psci-suspend-param = <0x1010033>;
>> entry-latency-us = <1000>;
>> exit-latency-us = <5000>;
>> min-residency-us = <20000>;
>>
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* [PATCH v2 0/2] Add efuse driver for Ingenic JZ4780 SoC
From: Mathieu Malaterre @ 2017-12-28 21:29 UTC (permalink / raw)
To: Marcin Nowakowski
Cc: Greg Kroah-Hartman, Zubair.Kakakhel-8NJIiSa5LzA,
Mathieu Malaterre, Srinivas Kandagatla, Rob Herring, Mark Rutland,
Ralf Baechle, PrasannaKumar Muralidharan,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA
This patchset bring support for read-only access to the JZ4780 efuse as found
on MIPS Creator CI20.
To keep the driver as simple as possible, it was not possible to re-use most of
the nvmem core functionalities. This driver is not compatible with the original
efuse driver as found in the custom linux kernel from upstream (1), in
particular it does not expose to the users neither:
`/sys/devices/platform/*/chip_id` nor `/sys/devices/platform/*/user_id`.
The goal of this driver is to provide access to the MAC address to the dm9000
driver.
(1) https://github.com/ZubairLK/CI20_linux/commit/6efd4ffca7dcfaff0794ab60cd6922ce96c60419
Changes in v2:
Properly handle offset and byte value from the main entry point.
Also add a commit message in patch #2.
Mathieu Malaterre (1):
dts: Probe efuse for CI20
PrasannaKumar Muralidharan (1):
nvmem: add driver for JZ4780 efuse
.../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++
.../bindings/nvmem/ingenic,jz4780-efuse.txt | 17 ++
MAINTAINERS | 5 +
arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++-
arch/mips/configs/ci20_defconfig | 2 +
drivers/nvmem/Kconfig | 10 +
drivers/nvmem/Makefile | 2 +
drivers/nvmem/jz4780-efuse.c | 305 +++++++++++++++++++++
8 files changed, 385 insertions(+), 12 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse
create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt
create mode 100644 drivers/nvmem/jz4780-efuse.c
--
2.11.0
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* [PATCH v2 1/2] nvmem: add driver for JZ4780 efuse
From: Mathieu Malaterre @ 2017-12-28 21:29 UTC (permalink / raw)
To: Marcin Nowakowski
Cc: Greg Kroah-Hartman, Zubair.Kakakhel, PrasannaKumar Muralidharan,
Mathieu Malaterre, Srinivas Kandagatla, Rob Herring, Mark Rutland,
Ralf Baechle, linux-kernel, devicetree, linux-mips
In-Reply-To: <20171228212954.2922-1-malat@debian.org>
From: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
This patch brings support for the JZ4780 efuse. Currently it only expose
a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
Signed-off-by: Mathieu Malaterre <malat@debian.org>
---
.../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++
.../bindings/nvmem/ingenic,jz4780-efuse.txt | 17 ++
MAINTAINERS | 5 +
arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++-
drivers/nvmem/Kconfig | 10 +
drivers/nvmem/Makefile | 2 +
drivers/nvmem/jz4780-efuse.c | 305 +++++++++++++++++++++
7 files changed, 383 insertions(+), 12 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse
create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt
create mode 100644 drivers/nvmem/jz4780-efuse.c
diff --git a/Documentation/ABI/testing/sysfs-driver-jz4780-efuse b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse
new file mode 100644
index 000000000000..bb6f5d6ceea0
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse
@@ -0,0 +1,16 @@
+What: /sys/devices/*/<our-device>/nvmem
+Date: December 2017
+Contact: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+Description: read-only access to the efuse on the Ingenic JZ4780 SoC
+ The SoC has a one time programmable 8K efuse that is
+ split into segments. The driver supports read only.
+ The segments are
+ 0x000 64 bit Random Number
+ 0x008 128 bit Ingenic Chip ID
+ 0x018 128 bit Customer ID
+ 0x028 3520 bit Reserved
+ 0x1E0 8 bit Protect Segment
+ 0x1E1 2296 bit HDMI Key
+ 0x300 2048 bit Security boot key
+Users: any user space application which wants to read the Chip
+ and Customer ID
diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt
new file mode 100644
index 000000000000..cd6d67ec22fc
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt
@@ -0,0 +1,17 @@
+Ingenic JZ EFUSE driver bindings
+
+Required properties:
+- "compatible" Must be set to "ingenic,jz4780-efuse"
+- "reg" Register location and length
+- "clocks" Handle for the ahb clock for the efuse.
+- "clock-names" Must be "bus_clk"
+
+Example:
+
+efuse: efuse@134100d0 {
+ compatible = "ingenic,jz4780-efuse";
+ reg = <0x134100D0 0xFF>;
+
+ clocks = <&cgu JZ4780_CLK_AHB2>;
+ clock-names = "bus_clk";
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index a6e86e20761e..7a050c20c533 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6902,6 +6902,11 @@ M: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
S: Maintained
F: drivers/dma/dma-jz4780.c
+INGENIC JZ4780 EFUSE Driver
+M: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+S: Maintained
+F: drivers/nvmem/jz4780-efuse.c
+
INGENIC JZ4780 NAND DRIVER
M: Harvey Hunt <harveyhuntnexus@gmail.com>
L: linux-mtd@lists.infradead.org
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index 9b5794667aee..3fb9d916a2ea 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -224,21 +224,37 @@
reg = <0x10002000 0x100>;
};
- nemc: nemc@13410000 {
- compatible = "ingenic,jz4780-nemc";
- reg = <0x13410000 0x10000>;
- #address-cells = <2>;
+
+ ahb2: ahb2 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
#size-cells = <1>;
- ranges = <1 0 0x1b000000 0x1000000
- 2 0 0x1a000000 0x1000000
- 3 0 0x19000000 0x1000000
- 4 0 0x18000000 0x1000000
- 5 0 0x17000000 0x1000000
- 6 0 0x16000000 0x1000000>;
+ ranges = <>;
+
+ nemc: nemc@13410000 {
+ compatible = "ingenic,jz4780-nemc";
+ reg = <0x13410000 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0x1b000000 0x1000000
+ 2 0 0x1a000000 0x1000000
+ 3 0 0x19000000 0x1000000
+ 4 0 0x18000000 0x1000000
+ 5 0 0x17000000 0x1000000
+ 6 0 0x16000000 0x1000000>;
+
+ clocks = <&cgu JZ4780_CLK_NEMC>;
+
+ status = "disabled";
+ };
- clocks = <&cgu JZ4780_CLK_NEMC>;
+ efuse: efuse@134100d0 {
+ compatible = "ingenic,jz4780-efuse";
+ reg = <0x134100d0 0xff>;
- status = "disabled";
+ clocks = <&cgu JZ4780_CLK_AHB2>;
+ clock-names = "bus_clk";
+ };
};
bch: bch@134d0000 {
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index ff505af064ba..75400982abac 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -36,6 +36,16 @@ config NVMEM_IMX_OCOTP
This driver can also be built as a module. If so, the module
will be called nvmem-imx-ocotp.
+config JZ4780_EFUSE
+ tristate "JZ4780 EFUSE Memory Support"
+ depends on MACH_JZ4780 || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ Say Y here to include support for JZ4780 efuse memory found on
+ all JZ4780 SoC based devices.
+ To compile this driver as a module, choose M here: the module
+ will be called nvmem_jz4780_efuse.
+
config NVMEM_LPC18XX_EEPROM
tristate "NXP LPC18XX EEPROM Memory Support"
depends on ARCH_LPC18XX || COMPILE_TEST
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index e54dcfa6565a..3b7c18df6771 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -13,6 +13,8 @@ obj-$(CONFIG_NVMEM_IMX_IIM) += nvmem-imx-iim.o
nvmem-imx-iim-y := imx-iim.o
obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o
nvmem-imx-ocotp-y := imx-ocotp.o
+obj-$(CONFIG_JZ4780_EFUSE) += nvmem_jz4780_efuse.o
+nvmem_jz4780_efuse-y := jz4780-efuse.o
obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o
nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o
obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o
diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c
new file mode 100644
index 000000000000..2490e5fc1a88
--- /dev/null
+++ b/drivers/nvmem/jz4780-efuse.c
@@ -0,0 +1,305 @@
+/*
+ * JZ4780 EFUSE Memory Support driver
+ *
+ * Copyright (c) 2017 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+/*
+ * Currently supports JZ4780 efuse which has 8K programmable bit.
+ * Efuse is separated into seven segments as below:
+ *
+ * -----------------------------------------------------------------------
+ * | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit |
+ * -----------------------------------------------------------------------
+ *
+ * The rom itself is accessed using a 9 bit address line and an 8 word wide bus
+ * which reads/writes based on strobes. The strobe is configured in the config
+ * register and is based on number of cycles of the bus clock.
+ *
+ * Driver supports read only as the writes are done in the Factory.
+ */
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/timer.h>
+
+#define JZ_EFUCTRL (0x0) /* Control Register */
+#define JZ_EFUCFG (0x4) /* Configure Register*/
+#define JZ_EFUSTATE (0x8) /* Status Register */
+#define JZ_EFUDATA(n) (0xC + (n)*4)
+
+#define JZ_EFUSE_START_ADDR 0x200
+#define JZ_EFUSE_SEG1_OFF 0x00 /* 64 bit Random Number */
+#define JZ_EFUSE_SEG2_OFF 0x08 /* 128 bit Ingenic Chip ID */
+#define JZ_EFUSE_SEG3_OFF 0x18 /* 128 bit Customer ID */
+#define JZ_EFUSE_SEG4_OFF 0x28 /* 3520 bit Reserved */
+#define JZ_EFUSE_SEG5_OFF 0x1E0 /* 8 bit Protect Segment */
+#define JZ_EFUSE_SEG6_OFF 0x1E1 /* 2296 bit HDMI Key */
+#define JZ_EFUSE_SEG7_OFF 0x300 /* 2048 bit Security boot key */
+#define JZ_EFUSE_END_ADDR 0x5FF
+
+#define JZ_EFUSE_EFUCTRL_CS BIT(30)
+#define JZ_EFUSE_EFUCTRL_ADDR_MASK 0x1FF
+#define JZ_EFUSE_EFUCTRL_ADDR_SHIFT 21
+#define JZ_EFUSE_EFUCTRL_LEN_MASK 0x1F
+#define JZ_EFUSE_EFUCTRL_LEN_SHIFT 16
+#define JZ_EFUSE_EFUCTRL_PG_EN BIT(15)
+#define JZ_EFUSE_EFUCTRL_WR_EN BIT(1)
+#define JZ_EFUSE_EFUCTRL_RD_EN BIT(0)
+
+#define JZ_EFUSE_EFUCFG_INT_EN BIT(31)
+#define JZ_EFUSE_EFUCFG_RD_ADJ_MASK 0xF
+#define JZ_EFUSE_EFUCFG_RD_ADJ_SHIFT 20
+#define JZ_EFUSE_EFUCFG_RD_STR_MASK 0xF
+#define JZ_EFUSE_EFUCFG_RD_STR_SHIFT 16
+#define JZ_EFUSE_EFUCFG_WR_ADJ_MASK 0xF
+#define JZ_EFUSE_EFUCFG_WR_ADJ_SHIFT 12
+#define JZ_EFUSE_EFUCFG_WR_STR_MASK 0xFFF
+#define JZ_EFUSE_EFUCFG_WR_STR_SHIFT 0
+
+#define JZ_EFUSE_EFUSTATE_WR_DONE BIT(1)
+#define JZ_EFUSE_EFUSTATE_RD_DONE BIT(0)
+
+#define JZ_EFUSE_WORD_SIZE 16
+#define JZ_EFUSE_STRIDE 8
+
+struct jz4780_efuse {
+ struct device *dev;
+ void __iomem *iomem;
+ struct clk *clk;
+ unsigned int rd_adj;
+ unsigned int rd_strobe;
+};
+
+/* We read 32 byte chunks to avoid complexity in the driver. */
+static int jz4780_efuse_read_32bytes(struct jz4780_efuse *efuse, char *buf,
+ unsigned int addr)
+{
+ unsigned int tmp = 0;
+ int i = 0;
+ int timeout = 1000;
+ int size = 32;
+
+ /* 1. Set config register */
+ tmp = readl(efuse->iomem + JZ_EFUCFG);
+ tmp &= ~((JZ_EFUSE_EFUCFG_RD_ADJ_MASK << JZ_EFUSE_EFUCFG_RD_ADJ_SHIFT)
+ | (JZ_EFUSE_EFUCFG_RD_STR_MASK << JZ_EFUSE_EFUCFG_RD_STR_SHIFT));
+ tmp |= (efuse->rd_adj << JZ_EFUSE_EFUCFG_RD_ADJ_SHIFT)
+ | (efuse->rd_strobe << JZ_EFUSE_EFUCFG_RD_STR_SHIFT);
+ writel(tmp, efuse->iomem + JZ_EFUCFG);
+
+ /*
+ * 2. Set control register to indicate what to read data address,
+ * read data numbers and read enable.
+ */
+ tmp = readl(efuse->iomem + JZ_EFUCTRL);
+ tmp &= ~(JZ_EFUSE_EFUCFG_RD_STR_SHIFT
+ | (JZ_EFUSE_EFUCTRL_ADDR_MASK << JZ_EFUSE_EFUCTRL_ADDR_SHIFT)
+ | JZ_EFUSE_EFUCTRL_PG_EN | JZ_EFUSE_EFUCTRL_WR_EN
+ | JZ_EFUSE_EFUCTRL_WR_EN);
+
+ /* Need to select CS bit if address accesses upper 4Kbits memory */
+ if (addr >= (JZ_EFUSE_START_ADDR + 512))
+ tmp |= JZ_EFUSE_EFUCTRL_CS;
+
+ tmp |= (addr << JZ_EFUSE_EFUCTRL_ADDR_SHIFT)
+ | ((size - 1) << JZ_EFUSE_EFUCTRL_LEN_SHIFT)
+ | JZ_EFUSE_EFUCTRL_RD_EN;
+ writel(tmp, efuse->iomem + JZ_EFUCTRL);
+
+ /*
+ * 3. Wait status register RD_DONE set to 1 or EFUSE interrupted,
+ * software can read EFUSE data buffer 0 - 8 registers.
+ */
+ do {
+ tmp = readl(efuse->iomem + JZ_EFUSTATE);
+ usleep_range(1000, 2000);
+ if (timeout--)
+ break;
+ } while (!(tmp & JZ_EFUSE_EFUSTATE_RD_DONE));
+
+ if (timeout <= 0) {
+ dev_err(efuse->dev, "Timed out while reading\n");
+ return -EAGAIN;
+ }
+
+ for (i = 0; i < (size / 4); i++)
+ *((unsigned int *)(buf + i * 4))
+ = readl(efuse->iomem + JZ_EFUDATA(i));
+
+ return 0;
+}
+
+static unsigned int segments[][2] = {
+ /* offset , size in bytes */
+ { JZ_EFUSE_SEG1_OFF, 64 >> 3 }, /* bit Random Number */
+ { JZ_EFUSE_SEG2_OFF, 128 >> 3 }, /* bit Ingenic Chip ID */
+ { JZ_EFUSE_SEG3_OFF, 128 >> 3 }, /* bit Customer ID */
+ { JZ_EFUSE_SEG4_OFF, 3520 >> 3 }, /* bit Reserved */
+ { JZ_EFUSE_SEG5_OFF, 8 >> 3 }, /* bit Protect Segment */
+ { JZ_EFUSE_SEG6_OFF, 2296 >> 3 }, /* bit HDMI Key */
+ { JZ_EFUSE_SEG7_OFF, 2048 >> 3 } /* bit Security boot key */
+};
+
+#define MAX(x, y) (((x) > (y)) ? (x) : (y))
+#define MIN(x, y) (((x) < (y)) ? (x) : (y))
+
+/* PM recommends read/write each segment separately */
+static int jz4780_efuse_read_segment(struct jz4780_efuse *efuse, int segid,
+ unsigned int *offset, char *out, size_t *bytes)
+{
+ char buf[32];
+ unsigned int lpos, buflen, ncount, remain;
+ unsigned int *segment = segments[segid];
+ int j;
+ char *cur = out;
+ int ret;
+
+ if (*bytes == 0 ||
+ (*offset < segment[0] || *offset >= segment[0] + segment[1])) {
+ // nothing to see, move along
+ return 0;
+ }
+ lpos = MAX(segment[0], *offset);
+ buflen = MIN(segment[1], *bytes);
+ ncount = buflen / 32;
+ remain = buflen % 32;
+
+ for (j = 0; j < ncount ; ++j) {
+ ret = jz4780_efuse_read_32bytes(efuse, buf, lpos);
+ if (ret < 0)
+ return ret;
+
+ memcpy(cur, buf, sizeof(buf));
+ cur += sizeof(buf);
+ lpos += sizeof(buf);
+ }
+ if (remain) {
+ ret = jz4780_efuse_read_32bytes(efuse, buf, lpos);
+ if (ret < 0)
+ return ret;
+
+ memcpy(cur, buf, remain);
+ cur += remain;
+ }
+ *offset += buflen;
+ *bytes -= buflen;
+ return buflen;
+}
+
+/* main entry point */
+static int jz4780_efuse_read(void *context, unsigned int offset,
+ void *val, size_t bytes)
+{
+ static const int nsegments = sizeof(segments) / sizeof(*segments);
+ struct jz4780_efuse *efuse = context;
+ char *cur = val;
+ int i, ret;
+
+ for (i = 0; i < nsegments; ++i) {
+ ret = jz4780_efuse_read_segment(efuse, i, &offset, cur, &bytes);
+ if (ret < 0)
+ return ret;
+ cur += ret;
+ }
+
+ return 0;
+}
+
+static struct nvmem_config jz4780_efuse_nvmem_config = {
+ .name = "jz4780-efuse",
+ .read_only = true,
+ .word_size = JZ_EFUSE_WORD_SIZE,
+ .stride = JZ_EFUSE_STRIDE,
+ .owner = THIS_MODULE,
+ .reg_read = jz4780_efuse_read,
+};
+
+static int jz4780_efuse_probe(struct platform_device *pdev)
+{
+ struct nvmem_device *nvmem;
+ struct jz4780_efuse *efuse;
+ struct resource *res;
+ unsigned long clk_rate;
+ struct device *dev = &pdev->dev;
+
+ efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
+ if (!efuse)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ efuse->iomem = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (IS_ERR(efuse->iomem))
+ return PTR_ERR(efuse->iomem);
+
+ efuse->clk = devm_clk_get(&pdev->dev, "bus_clk");
+ if (IS_ERR(efuse->clk))
+ return PTR_ERR(efuse->clk);
+
+ clk_rate = clk_get_rate(efuse->clk);
+ /*
+ * rd_adj and rd_strobe are 4 bit values
+ * bus clk period * (rd_adj + 1) > 6.5ns
+ * bus clk period * (rd_adj + 5 + rd_strobe) > 35ns
+ */
+ efuse->rd_adj = (((6500 * (clk_rate / 1000000)) / 1000000) + 1) - 1;
+ efuse->rd_strobe = ((((35000 * (clk_rate / 1000000)) / 1000000) + 1)
+ - 5 - efuse->rd_adj);
+
+ if ((efuse->rd_adj > 0x1F) || (efuse->rd_strobe > 0x1F)) {
+ dev_err(&pdev->dev, "Cannot set clock configuration\n");
+ return -EINVAL;
+ }
+ efuse->dev = dev;
+
+ jz4780_efuse_nvmem_config.size = 1024;
+ jz4780_efuse_nvmem_config.dev = &pdev->dev;
+ jz4780_efuse_nvmem_config.priv = efuse;
+
+ nvmem = nvmem_register(&jz4780_efuse_nvmem_config);
+ if (IS_ERR(nvmem))
+ return PTR_ERR(nvmem);
+
+ platform_set_drvdata(pdev, nvmem);
+
+ return 0;
+}
+
+static int jz4780_efuse_remove(struct platform_device *pdev)
+{
+ struct nvmem_device *nvmem = platform_get_drvdata(pdev);
+
+ return nvmem_unregister(nvmem);
+}
+
+static const struct of_device_id jz4780_efuse_match[] = {
+ { .compatible = "ingenic,jz4780-efuse" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
+
+static struct platform_driver jz4780_efuse_driver = {
+ .probe = jz4780_efuse_probe,
+ .remove = jz4780_efuse_remove,
+ .driver = {
+ .name = "jz4780-efuse",
+ .of_match_table = jz4780_efuse_match,
+ },
+};
+module_platform_driver(jz4780_efuse_driver);
+
+MODULE_AUTHOR("PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>");
+MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related
* [PATCH v2 2/2] dts: Probe efuse for CI20
From: Mathieu Malaterre @ 2017-12-28 21:29 UTC (permalink / raw)
To: Marcin Nowakowski
Cc: Greg Kroah-Hartman, Zubair.Kakakhel-8NJIiSa5LzA,
Mathieu Malaterre, Srinivas Kandagatla, Rob Herring, Mark Rutland,
Ralf Baechle, PrasannaKumar Muralidharan,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA
In-Reply-To: <20171228212954.2922-1-malat-8fiUuRrzOP0dnm+yROfE0A@public.gmane.org>
MIPS Creator CI20 comes with JZ4780 SoC. Provides access to the efuse block
using jz4780 efuse driver.
Signed-off-by: Mathieu Malaterre <malat-8fiUuRrzOP0dnm+yROfE0A@public.gmane.org>
---
arch/mips/configs/ci20_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig
index b5f4ad8f2c45..62c63617e97a 100644
--- a/arch/mips/configs/ci20_defconfig
+++ b/arch/mips/configs/ci20_defconfig
@@ -171,3 +171,5 @@ CONFIG_STACKTRACE=y
# CONFIG_FTRACE is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="earlycon console=ttyS4,115200 clk_ignore_unused"
+CONFIG_NVMEM=y
+CONFIG_JZ4780_EFUSE=y
--
2.11.0
--
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH v2 1/9] PCI: Regroup all PCI related entries into drivers/pci/Makefile
From: Bjorn Helgaas @ 2017-12-28 22:47 UTC (permalink / raw)
To: Cyrille Pitchen
Cc: bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, kishon-l0cyMroinI0,
lorenzo.pieralisi-5wv7dgnIgG8, linux-pci-u79uwXL29TY76Z2rM5mHXA,
adouglas-vna1KIf7WgpBDgjK7y7TUQ, stelford-vna1KIf7WgpBDgjK7y7TUQ,
dgary-vna1KIf7WgpBDgjK7y7TUQ, kgopi-vna1KIf7WgpBDgjK7y7TUQ,
eandrews-vna1KIf7WgpBDgjK7y7TUQ,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
sureshp-vna1KIf7WgpBDgjK7y7TUQ, nsekhar-l0cyMroinI0,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <49f5a733e05a46521340e913876332f3804e2042.1513620412.git.cyrille.pitchen-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Mon, Dec 18, 2017 at 07:16:01PM +0100, Cyrille Pitchen wrote:
> This patch cleans drivers/Makefile up by moving the pci/endpoint and
> pci/dwc entries from drivers/Makefile into drivers/pci/Makefile.
Thanks a lot for doing this!
s/This patch cleans/Clean up/
Speaking of cleanup, this Makefile has useless comments and blank
lines. Maybe you could add a new patch to remove them and reorder it
into a sensible order, with the Intel MID special case at the end and
the host/dwc/cadence stuff together?
> Since we don't want to introduce any dependency between CONFIG_PCI and
> CONFIG_PCI_ENDPOINT, we now always execute drivers/pci/Makefile.
>
> Hence all Makefiles in drivers/pci/ were updated accordingly so no file is
> compiled when CONFIG_PCI is not defined.
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitchen-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
> drivers/Makefile | 5 +----
> drivers/pci/Kconfig | 1 +
> drivers/pci/Makefile | 11 ++++++++---
> drivers/pci/host/Makefile | 2 ++
> 4 files changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 1d034b680431..9757199b9a65 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -16,10 +16,7 @@ obj-$(CONFIG_PINCTRL) += pinctrl/
> obj-$(CONFIG_GPIOLIB) += gpio/
> obj-y += pwm/
>
> -obj-$(CONFIG_PCI) += pci/
> -obj-$(CONFIG_PCI_ENDPOINT) += pci/endpoint/
> -# PCI dwc controller drivers
> -obj-y += pci/dwc/
> +obj-y += pci/
>
> obj-$(CONFIG_PARISC) += parisc/
> obj-$(CONFIG_RAPIDIO) += rapidio/
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index bda151788f3f..7eeb969ab86a 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -125,6 +125,7 @@ config PCI_PASID
>
> config PCI_LABEL
> def_bool y if (DMI || ACPI)
> + depends on PCI
> select NLS
>
> config PCI_HYPERV
> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> index c7819b973df7..7284a7f6ad1e 100644
> --- a/drivers/pci/Makefile
> +++ b/drivers/pci/Makefile
> @@ -3,12 +3,15 @@
> # Makefile for the PCI bus specific drivers.
> #
>
> -obj-y += access.o bus.o probe.o host-bridge.o remove.o pci.o \
> +obj-$(CONFIG_PCI) += access.o bus.o probe.o host-bridge.o remove.o pci.o \
> pci-driver.o search.o pci-sysfs.o rom.o setup-res.o \
> irq.o vpd.o setup-bus.o vc.o mmap.o setup-irq.o
>
> +ifdef CONFIG_PCI
> obj-$(CONFIG_PROC_FS) += proc.o
> obj-$(CONFIG_SYSFS) += slot.o
> +obj-$(CONFIG_OF) += of.o
> +endif
>
> obj-$(CONFIG_PCI_QUIRKS) += quirks.o
>
> @@ -44,10 +47,12 @@ obj-$(CONFIG_PCI_ECAM) += ecam.o
>
> obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o
>
> -obj-$(CONFIG_OF) += of.o
> -
> ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
>
> # PCI host controller drivers
> obj-y += host/
> obj-y += switch/
> +
> +obj-$(CONFIG_PCI_ENDPOINT) += endpoint/
> +# PCI dwc controller drivers
> +obj-y += dwc/
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index 34ec1d88f961..3b1059190867 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -34,6 +34,8 @@ obj-$(CONFIG_VMD) += vmd.o
> # ARM64 and use internal ifdefs to only build the pieces we need
> # depending on whether ACPI, the DT driver, or both are enabled.
>
> +ifdef CONFIG_PCI
> obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
> obj-$(CONFIG_ARM64) += pci-thunder-pem.o
> obj-$(CONFIG_ARM64) += pci-xgene.o
> +endif
> --
> 2.11.0
>
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* Re: [PATCH v2 6/9] PCI: cadence: Add host driver for Cadence PCIe controller
From: Bjorn Helgaas @ 2017-12-28 23:01 UTC (permalink / raw)
To: Cyrille Pitchen
Cc: bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, kishon-l0cyMroinI0,
lorenzo.pieralisi-5wv7dgnIgG8, linux-pci-u79uwXL29TY76Z2rM5mHXA,
adouglas-vna1KIf7WgpBDgjK7y7TUQ, stelford-vna1KIf7WgpBDgjK7y7TUQ,
dgary-vna1KIf7WgpBDgjK7y7TUQ, kgopi-vna1KIf7WgpBDgjK7y7TUQ,
eandrews-vna1KIf7WgpBDgjK7y7TUQ,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
sureshp-vna1KIf7WgpBDgjK7y7TUQ, nsekhar-l0cyMroinI0,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <4b2b67ad54e14ee5e1f83af65e9932ce408e82ec.1513620412.git.cyrille.pitchen-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Mon, Dec 18, 2017 at 07:16:06PM +0100, Cyrille Pitchen wrote:
> This patch adds support to the Cadence PCIe controller in host mode.
>
> The "cadence/" entry in drivers/pci/Makefile is placed after the
> "endpoint/" entry so when the next patch introduces a EPC driver for the
> Cadence PCIe controller, drivers/pci/cadence/pcie-cadence-ep.o will be
> linked after drivers/pci/endpoint/*.o objects, otherwise the built-in
> pci-cadence-ep driver would be probed before the PCI endpoint libraries
> would have been initialized, which would result in a kernel crash.
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitchen-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> index 7284a7f6ad1e..a66ddb347798 100644
> --- a/drivers/pci/Makefile
> +++ b/drivers/pci/Makefile
> @@ -54,5 +54,6 @@ obj-y += host/
> obj-y += switch/
>
> obj-$(CONFIG_PCI_ENDPOINT) += endpoint/
> +obj-$(CONFIG_PCI_CADENCE) += cadence/
> # PCI dwc controller drivers
> obj-y += dwc/
I don't like the fact that the cadence/ rule looks different than the
dwc/ rule for no obvious reason. With some work, the dwc/ rule could
maybe be made to look like:
obj-$(CONFIG_PCIE_DW) += dwc/
I *think* that should actually be pretty easy. Everything in
drivers/pci/dwc/Kconfig selects PCIE_DW if set, either via
PCIE_DW_HOST or PCIE_DW_EP.
> diff --git a/drivers/pci/cadence/Kconfig b/drivers/pci/cadence/Kconfig
> new file mode 100644
> index 000000000000..0d15b40861e9
> --- /dev/null
> +++ b/drivers/pci/cadence/Kconfig
> @@ -0,0 +1,24 @@
> +menuconfig PCI_CADENCE
> + bool "Cadence PCI controllers support"
> + depends on PCI && HAS_IOMEM
> + help
> + Say Y here if you want to support some Cadence PCI controller.
> +
> + When in doubt, say N.
> +
> +if PCI_CADENCE
> +
> +config PCIE_CADENCE
> + bool
> +
> +config PCIE_CADENCE_HOST
> + bool "Cadence PCIe host controller"
> + depends on OF
> + select IRQ_DOMAIN
> + select PCIE_CADENCE
> + help
> + Say Y here if you want to support the Cadence PCIe controller in host
> + mode. This PCIe controller may be embedded into many different vendors
> + SoCs.
> +
> +endif # PCI_CADENCE
Can you just use the same strategy as pci/dwc/Kconfig does, i.e., omit
the top-level PCI_CADENCE symbol? If we don't need it for dwc, with
its dozen drivers, we probably don't need it for the one or two
Cadence drivers.
Bjorn
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^ permalink raw reply
* Re: [PATCH v2] arm64: dts: Hi3660: Fix up psci state id
From: Leo Yan @ 2017-12-28 23:13 UTC (permalink / raw)
To: Wei Xu
Cc: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Vincent Guittot,
Daniel Lezcano, Sudeep Holla, Soby Mathew
In-Reply-To: <5A455E9B.9010703-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
On Thu, Dec 28, 2017 at 09:14:03PM +0000, Wei Xu wrote:
> Hi Leo,
[...]
> Sorry, since this patch is still under discussion,
> I will drop it firstly.
> Thanks!
Thanks, Wei.
> Best Regards,
> Wei
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^ permalink raw reply
* Re: [PATCH v7] i2c: Add support for NXP PCA984x family.
From: Peter Rosin @ 2017-12-28 23:31 UTC (permalink / raw)
To: Adrian Fiergolski, linux-i2c-u79uwXL29TY76Z2rM5mHXA
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, robh-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <20171225212646.8062-1-adrian.fiergolski-vJEk5272eHo@public.gmane.org>
On 2017-12-25 22:26, Adrian Fiergolski wrote:
> This patch extends the current i2c-mux-pca954x driver and adds support for
> a newer PCA984x family of the I2C switches and multiplexers from NXP.
>
> Signed-off-by: Adrian Fiergolski <adrian.fiergolski-vJEk5272eHo@public.gmane.org>
> ---
> Following Rob's and Peter's remarks, bindings contain now one valid
> combination of compatibles per line.
Patch applied, thanks!
Any idea if you are going to tackle that device-id functionality for the
i2c core?
Cheers,
Peter
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* Re: [PATCH v11 0/6] Add support for Qualcomm A53 CPU clock
From: Stephen Boyd @ 2017-12-28 23:53 UTC (permalink / raw)
To: Georgi Djakov
Cc: jassisinghbrar, bjorn.andersson, mturquette, robh, linux-clk,
linux-kernel, linux-arm-msm, devicetree
In-Reply-To: <1ea1fa92-de78-c4df-469c-3f36f5f62497@linaro.org>
On 12/22, Georgi Djakov wrote:
> On 22.12.17 г. 2:49, Stephen Boyd wrote:
> > On 12/05, Georgi Djakov wrote:
> >> This patchset adds support for the A53 CPU clock on MSM8916 platforms
> >> and allows scaling of the CPU frequency on msm8916 based platforms.
> >
> > Ok. I will apply just the clk ones? Patches 3,4, and 6?
> >
>
> Yes, i think this would be best. The rest should go through the mailbox tree.
>
Ok. I made some changes. I'll comment one patch too. But I
applied them to clk-next.
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Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH v11 6/6] clk: qcom: Add APCS clock controller support
From: Stephen Boyd @ 2017-12-29 0:00 UTC (permalink / raw)
To: Georgi Djakov
Cc: jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w,
bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A,
mturquette-rdvid1DuHRBWk0Htik3J/w, robh-DgEjT+Ai2ygdnm+yROfE0A,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171205154701.27730-7-georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On 12/05, Georgi Djakov wrote:
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include "clk-regmap.h"
> +#include "clk-regmap-mux-div.h"
> +
> +enum {
> + P_GPLL0,
> + P_A53PLL,
> +};
This is always 0, 1.
> +
> +static const struct parent_map gpll0_a53cc_map[] = {
> + { P_GPLL0, 4 },
> + { P_A53PLL, 5 },
And then this is not really doing much. So I wonder why we really
even need a parent_map? More like we need a map from parent_names
to mux number. We don't need to map some random enum into another
number space like we do for RCGs. I think we may have the same
problem with another qcom clk patch (see commit df964016490b in
clk-next). We really don't need the rcg version of parent_map in
either case, more like we just need a u8 *table (or u32
whatever), and then we're done. I'm going to make that change now
because otherwise we get into a mess with the parent_map stuff in
the other branch. I'll go clean up that too so we don't move
parent_map around.
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a Linux Foundation Collaborative Project
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^ permalink raw reply
* Re: [PATCH v11 4/6] clk: qcom: Add regmap mux-div clocks support
From: Stephen Boyd @ 2017-12-29 0:01 UTC (permalink / raw)
To: Georgi Djakov
Cc: jassisinghbrar, bjorn.andersson, mturquette, robh, linux-clk,
linux-kernel, linux-arm-msm, devicetree
In-Reply-To: <20171205154701.27730-5-georgi.djakov@linaro.org>
On 12/05, Georgi Djakov wrote:
> Add support for hardware that can switch both parent clock and divider
> at the same time. This avoids generating intermediate frequencies from
> either the old parent clock and new divider or new parent clock and
> old divider combinations.
>
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> ---
Applied to clk-next
--
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