* [PATCH] ARM: dts: berlin2q: add "cache-unified" to l2 node
From: Jisheng Zhang @ 2018-05-15 6:05 UTC (permalink / raw)
To: Sebastian Hesselbarth, Rob Herring, Mark Rutland
Cc: linux-arm-kernel, devicetree, linux-kernel
Without this property, we get this boot warning:
"L2C: device tree omits to specify unified cache"
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
---
arch/arm/boot/dts/berlin2q.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index e23c49ae3ec2..7cba798152b9 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -149,6 +149,7 @@
l2: l2-cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
+ cache-unified;
cache-level = <2>;
arm,data-latency = <2 2 2>;
arm,tag-latency = <2 2 2>;
--
2.17.0
^ permalink raw reply related
* Re: [PATCH] ARM: dts: chromecast: override bad bootloader memory info
From: Tom Hebb @ 2018-05-15 6:04 UTC (permalink / raw)
To: Jisheng Zhang
Cc: linux-kernel, Sebastian Hesselbarth, Rob Herring, Mark Rutland,
moderated list:ARM/Synaptics Berlin SoC support,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <20180515102939.3ab8797c@xhacker.debian>
Hi,
On 05/14/2018 10:29 PM, Jisheng Zhang wrote:
> Hi,
>
> On Mon, 14 May 2018 17:56:45 -0400 Thomas Hebb wrote:
>
>> On the Chromecast, the bootloader provides us with an ATAG_MEM of
>> start=0x01000000 and size=0x3eff8000. This is clearly incorrect, as the
>> range given encompasses nearly a GiB but the Chromecast only has 512MiB
>> of RAM! Additionally, this causes the kernel to be decompressed at
>> 0x00008000, below the claimed beginning of RAM, and so the boot fails.
>>
>> Since the existing ATAG parsing code runs before the kernel is even
>> decompressed and irrevocably patches the device tree, don't even try
>
> This means you enabled ARM_ATAG_DTB_COMPAT. could we disable it instead?
> The ATAG is useless when we provide dtb. And IIRC, the ATAG is provided due
> to legacy history code.
>
> Thanks
Thanks for the quick review! It's true that compiling without
ARM_ATAG_DTB_COMPAT will prevent ATAG_MEM from getting parsed at all.
However, it will also prevent ATAG_CMDLINE from getting parsed, and the
command line from the Chromecast's bootloader does actually contain some
useful information--notably the mode in which the system was booted
(normal or recovery).
Userspace could conceivably want this information, so it's preferable
for the kernel to boot regardless of whether ARM_ATAG_DTB_COMPAT is
enabled. That's the intent of this patch.
I do agree in principle that ARM_ATAG_DTB_COMPAT should be disabled
whenever possible.
>> to bypass it. Instead, use the "linux,usable-memory" property instead
>> of the "reg" property to define the real range. The ATAG code only
>> overwrites reg, but linux,usable-memory is checked first in the OF
>> driver, so the fact that reg gets changed makes no difference.
>>
>> Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
>> ---
>> arch/arm/boot/dts/berlin2cd-google-chromecast.dts | 12 +++++++++++-
>> 1 file changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
>> index 20f31cdeaf38..54221f55bfa2 100644
>> --- a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
>> +++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
>> @@ -52,7 +52,17 @@
>>
>> memory@0 {
>> device_type = "memory";
>> - reg = <0x00000000 0x20000000>; /* 512 MB */
>> +
>> + /*
>> + * We're using "linux,usable-memory" instead of "reg" here
>> + * because the (signed and encrypted) bootloader that shipped
>> + * with this device provides an incorrect memory range in
>> + * ATAG_MEM. Linux helpfully overrides the "reg" property with
>> + * data from the ATAG, so we can't specify the proper range
>> + * normally. Fortunately, this alternate property is checked
>> + * first by the OF driver, so we can (ab)use it instead.
>> + */
>> + linux,usable-memory = <0x00000000 0x20000000>; /* 512 MB */
>> };
>>
>> leds {
>
^ permalink raw reply
* Re: [PATCH 1/3] ARM: dra762: hwmod: Add MCAN support
From: Faiz Abbas @ 2018-05-15 6:04 UTC (permalink / raw)
To: Tony Lindgren
Cc: linux-kernel, linux-omap, devicetree, bcousson, robh+dt,
mark.rutland, paul, lokeshvutla, linux
In-Reply-To: <20180501152615.GB98604@atomide.com>
Hi Tony,
On Tuesday 01 May 2018 08:56 PM, Tony Lindgren wrote:
> Hi,
>
> * Faiz Abbas <faiz_abbas@ti.com> [180408 09:59]:
>> From: Lokesh Vutla <lokeshvutla@ti.com>
>>
>> Add MCAN hwmod data and register it for dra762 silicons.
>>
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
>> ---
>> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 32 +++++++++++++++++++++++++++++++
>> 1 file changed, 32 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> index 62352d1..a2cd7f8 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> @@ -1356,6 +1356,29 @@ static struct omap_hwmod dra7xx_mailbox13_hwmod = {
>> };
>>
>> /*
>> + * 'mcan' class
>> + *
>> + */
>> +static struct omap_hwmod_class dra76x_mcan_hwmod_class = {
>> + .name = "mcan",
>> +};
>
> Looks like you're missing the related struct omap_hwmod_class_sysconfig
> entry for this with the rev and sysconfig registers.
>
Sorry, I missed this email earlier. The MCAN module doesn't have
sysconfig registers.
Thanks,
Faiz
^ permalink raw reply
* [PATCH v6 4/4] dt-bindings: drm/panel: Document Innolux TV123WAM panel bindings
From: Sandeep Panda @ 2018-05-15 5:52 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: ryadav-sgV2jX0FEOL9JmXXK+q4OQ, Sandeep Panda,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, seanpaul-F7+t8E8rja9g9hUCZPvPmw,
hoegsberg-F7+t8E8rja9g9hUCZPvPmw, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ
In-Reply-To: <1526363564-13823-1-git-send-email-spanda-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Innolux TV123WAM is a 12.3" eDP display panel with
2160x1440 resolution, which can be supported by simple
panel driver.
Changes in v1:
- Make use of simple panel driver instead of creating
a new driver for this panel (Sean Paul).
- Combine dt-binding and driver changes into one patch
as done by other existing panel support changes.
Changes in v2:
- Separate driver change from dt-binding documentation (Rob Herring).
- Add the properties from simple-panel binding that are applicable to
this panel (Rob Herring).
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/display/panel/innolux,tv123wam.txt | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt
diff --git a/Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt b/Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt
new file mode 100644
index 0000000..a9b3526
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt
@@ -0,0 +1,20 @@
+Innolux TV123WAM 12.3 inch eDP 2K display panel
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
+
+Required properties:
+- compatible: should be "innolux,tv123wam"
+- power-supply: regulator to provide the supply voltage
+
+Optional properties:
+- enable-gpios: GPIO pin to enable or disable the panel
+- backlight: phandle of the backlight device attached to the panel
+
+Example:
+ panel_edp: panel-edp {
+ compatible = "innolux,tv123wam";
+ enable-gpios = <&msmgpio 31 GPIO_ACTIVE_LOW>;
+ power-supply = <&pm8916_l2>;
+ backlight = <&backlight>;
+ };
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related
* [PATCH v6 3/4] drm/panel: add Innolux TV123WAM panel driver support
From: Sandeep Panda @ 2018-05-15 5:52 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: ryadav-sgV2jX0FEOL9JmXXK+q4OQ, Sandeep Panda,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, seanpaul-F7+t8E8rja9g9hUCZPvPmw,
hoegsberg-F7+t8E8rja9g9hUCZPvPmw, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ
In-Reply-To: <1526363564-13823-1-git-send-email-spanda-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Add support for Innolux TV123WAM, which is a 12.3" eDP
display panel with 2160x1440 resolution.
Changes in v1:
- Add the compatibility string, display_mode and panel_desc
structures in alphabetical order (Sean Paul).
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
---
drivers/gpu/drm/panel/panel-simple.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 234af81..8c72270 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1190,6 +1190,30 @@ static void panel_simple_shutdown(struct device *dev)
},
};
+static const struct drm_display_mode innolux_tv123wam_mode = {
+ .clock = 206016,
+ .hdisplay = 2160,
+ .hsync_start = 2160 + 48,
+ .hsync_end = 2160 + 48 + 32,
+ .htotal = 2160 + 48 + 32 + 80,
+ .vdisplay = 1440,
+ .vsync_start = 1440 + 3,
+ .vsync_end = 1440 + 3 + 10,
+ .vtotal = 1440 + 3 + 10 + 27,
+ .vrefresh = 60,
+ .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+};
+
+static const struct panel_desc innolux_tv123wam = {
+ .modes = &innolux_tv123wam_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 259,
+ .height = 173,
+ },
+};
+
static const struct drm_display_mode innolux_zj070na_01p_mode = {
.clock = 51501,
.hdisplay = 1024,
@@ -2037,6 +2061,9 @@ static void panel_simple_shutdown(struct device *dev)
.compatible = "innolux,n156bge-l21",
.data = &innolux_n156bge_l21,
}, {
+ .compatible = "innolux,tv123wam",
+ .data = &innolux_tv123wam,
+ }, {
.compatible = "innolux,zj070na-01p",
.data = &innolux_zj070na_01p,
}, {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related
* [PATCH v6 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings
From: Sandeep Panda @ 2018-05-15 5:52 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: ryadav-sgV2jX0FEOL9JmXXK+q4OQ, Sandeep Panda,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, seanpaul-F7+t8E8rja9g9hUCZPvPmw,
hoegsberg-F7+t8E8rja9g9hUCZPvPmw, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ
In-Reply-To: <1526363564-13823-1-git-send-email-spanda-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Document the bindings used for the sn65dsi86 DSI to eDP bridge.
Changes in v1:
- Rephrase the dt-binding descriptions to be more inline with existing
bindings (Andrzej Hajda).
- Add missing dt-binding that are parsed by corresponding driver
(Andrzej Hajda).
Changes in v2:
- Remove edp panel specific dt-binding entries. Only keep bridge
specific entries (Sean Paul).
- Remove custom-modes dt entry since its usage is removed from driver also (Sean Paul).
- Remove is-pluggable dt entry since this will not be needed anymore (Sean Paul).
Changes in v3:
- Remove irq-gpio dt entry and instead populate is an interrupt
property (Rob Herring).
Changes in v4:
- Add link to bridge chip datasheet (Stephen Boyd)
- Add vpll and vcc regulator supply bindings (Stephen Boyd)
- Add ref clk optional dt binding (Stephen Boyd)
- Add gpio-controller optional dt binding (Stephen Boyd)
Changes in v5:
- Use clock property to specify the input refclk (Stephen Boyd).
- Update gpio cell and pwm cell numbers (Stephen Boyd).
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
---
.../bindings/display/bridge/ti,sn65dsi86.txt | 81 ++++++++++++++++++++++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
new file mode 100644
index 0000000..b82bb56
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
@@ -0,0 +1,81 @@
+SN65DSI86 DSI to eDP bridge chip
+--------------------------------
+
+This is the binding for Texas Instruments SN65DSI86 bridge.
+http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf
+
+Required properties:
+- compatible: Must be "ti,sn65dsi86"
+- reg: i2c address of the chip, 0x2d as per datasheet
+- enable-gpios: OF device-tree gpio specification for bridge_en pin
+
+- vccio-supply: A 1.8V supply that powers up the digital IOs.
+- vpll-supply: A 1.8V supply that powers up the displayport PLL.
+- vcca-supply: A 1.2V supply that powers up the analog circuits.
+- vcc-supply: A 1.2V supply that powers up the digital core.
+
+Optional properties:
+- interrupts: Specifier for the SN65DSI86 interrupt line.
+- hpd-gpios: OF device-tree gpio specifications for HPD pin.
+
+- gpio-controller: Marks the device has a GPIO controller.
+- #gpio-cells : Should be two. The first cell is the pin number and
+ the second cell is used to specify flags.
+ See ../../gpio/gpio.txt for more information.
+- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description of
+ the cell formats.
+
+- clock-names: should be "refclk"
+- clocks: OF device-tree clock specification for refclk input. The reference
+ clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
+
+Required nodes:
+
+This device has two video ports. Their connections are modelled using the
+OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+
+- Video port 0 for DSI input
+- Video port 1 for eDP output
+
+Example
+-------
+
+edp-bridge@2d {
+ compatible = "ti,sn65dsi86";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2d>;
+
+ enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+
+ vccio-supply = <&pm8916_l17>;
+ vcca-supply = <&pm8916_l6>;
+ vpll-supply = <&pm8916_l17>;
+ vcc-supply = <&pm8916_l6>;
+
+ clock-names = "refclk";
+ clocks = <&input_refclk>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ edp_bridge_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ edp_bridge_out: endpoint {
+ remote-endpoint = <&edp_panel_in>;
+ };
+ };
+ };
+}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related
* [PATCH v6 1/4] drm/bridge: add support for sn65dsi86 bridge driver
From: Sandeep Panda @ 2018-05-15 5:52 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: ryadav-sgV2jX0FEOL9JmXXK+q4OQ, Sandeep Panda,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, seanpaul-F7+t8E8rja9g9hUCZPvPmw,
hoegsberg-F7+t8E8rja9g9hUCZPvPmw, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ
In-Reply-To: <1526363564-13823-1-git-send-email-spanda-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Add support for TI's sn65dsi86 dsi2edp bridge chip.
The chip converts DSI transmitted signal to eDP signal,
which is fed to the connected eDP panel.
This chip can be controlled via either i2c interface or
dsi interface. Currently in driver all the control registers
are being accessed through i2c interface only.
Also as of now HPD support has not been added to bridge
chip driver.
Changes in v1:
- Split the dt-bindings and the driver support into separate patches
(Andrzej Hajda).
- Use of gpiod APIs to parse and configure gpios instead of obsolete ones
(Andrzej Hajda).
- Use macros to define the register offsets (Andrzej Hajda).
Changes in v2:
- Separate out edp panel specific HW resource handling from bridge
driver and create a separate edp panel drivers to handle panel
specific mode information and HW resources (Sean Paul).
- Replace pr_* APIs to DRM_* APIs to log error or debug information
(Sean Paul).
- Remove some of the unnecessary structure/variable from driver (Sean
Paul).
- Rename the function and structure prefix "sn65dsi86" to "ti_sn_bridge"
(Sean Paul / Rob Herring).
- Remove most of the hard-coding and modified the bridge init sequence
based on current mode (Sean Paul).
- Remove the existing function to retrieve the EDID data and
implemented this as an i2c_adapter and use drm_get_edid() (Sean Paul).
- Remove the dummy irq handler implementation, will add back the
proper irq handling later (Sean Paul).
- Capture the required enable gpios in a single array based on dt entry
instead of having individual descriptor for each gpio (Sean Paul).
Changes in v3:
- Remove usage of irq_gpio and replace it as "interrupts" property (Rob
Herring).
- Remove the unnecessary header file inclusions (Sean Paul).
- Rearrange the header files in alphabetical order (Sean Paul).
- Use regmap interface to perform i2c transactions.
- Update Copyright/License field and address other review comments
(Jordan Crouse).
Changes in v4:
- Update License/Copyright (Sean Paul).
- Add Kconfig and Makefile changes (Sean Paul).
- Drop i2c gpio handling from this bridge driver, since i2c sda/scl gpios
will be handled by i2c master.
- Update required supplies names.
- Remove unnecessary goto statements (Sean Paul).
- Add mutex lock to power_ctrl API to avoid race conditions (Sean
Paul).
- Add support to parse reference clk frequency from dt(optional).
- Update the bridge chip enable/disable sequence.
Changes in v5:
- Fixed Kbuild test service reported warnings.
Changes in v6:
- Use PM runtime based ref-counting instead of local ref_count mechanism
(Stephen Boyd).
- Clean up some debug logs and indentations (Sean Paul).
- Simplify dp rate calculation (Sean Paul).
- Add support to configure refclk based on input REFCLK pin or DACP/N
pin (Stephen Boyd).
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
---
drivers/gpu/drm/bridge/Kconfig | 9 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 766 ++++++++++++++++++++++++++++++++++
3 files changed, 776 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi86.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 3b99d5a..8153150 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -108,6 +108,15 @@ config DRM_TI_TFP410
---help---
Texas Instruments TFP410 DVI/HDMI Transmitter driver
+config DRM_TI_SN65DSI86
+ tristate "TI SN65DSI86 DSI to eDP bridge"
+ depends on OF
+ select DRM_KMS_HELPER
+ select REGMAP_I2C
+ select DRM_PANEL
+ ---help---
+ Texas Instruments SN65DSI86 DSI to eDP Bridge driver
+
source "drivers/gpu/drm/bridge/analogix/Kconfig"
source "drivers/gpu/drm/bridge/adv7511/Kconfig"
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 373eb28..3711be8 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
+obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
obj-y += synopsys/
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
new file mode 100644
index 0000000..1d3e549
--- /dev/null
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -0,0 +1,766 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/of_graph.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define SN_BRIDGE_REVISION_ID 0x2
+
+/* Link Training specific registers */
+#define SN_DEVICE_REV_REG 0x08
+#define SN_HPD_DISABLE_REG 0x5C
+#define SN_REFCLK_FREQ_REG 0x0A
+#define SN_DSI_LANES_REG 0x10
+#define SN_DSIA_CLK_FREQ_REG 0x12
+#define SN_ENH_FRAME_REG 0x5A
+#define SN_SSC_CONFIG_REG 0x93
+#define SN_DATARATE_CONFIG_REG 0x94
+#define SN_PLL_ENABLE_REG 0x0D
+#define SN_SCRAMBLE_CONFIG_REG 0x95
+#define SN_AUX_WDATA0_REG 0x64
+#define SN_AUX_ADDR_19_16_REG 0x74
+#define SN_AUX_ADDR_15_8_REG 0x75
+#define SN_AUX_ADDR_7_0_REG 0x76
+#define SN_AUX_LENGTH_REG 0x77
+#define SN_AUX_CMD_REG 0x78
+#define SN_ML_TX_MODE_REG 0x96
+/* video config specific registers */
+#define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
+#define SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG 0x21
+#define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
+#define SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG 0x25
+#define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
+#define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
+#define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
+#define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
+#define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
+#define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
+#define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
+#define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
+#define SN_DATA_FORMAT_REG 0x5B
+
+#define MIN_DSI_CLK_FREQ_MHZ 40
+
+/* fudge factor required to account for 8b/10b encoding */
+#define DP_CLK_FUDGE_NUM 10
+#define DP_CLK_FUDGE_DEN 8
+
+#define DPPLL_CLK_SRC_REFCLK 0
+#define DPPLL_CLK_SRC_DSICLK 1
+
+#define SN_DSIA_REFCLK_OFFSET 1
+#define SN_DSIA_LANE_OFFSET 3
+#define SN_DP_LANE_OFFSET 4
+#define SN_DP_DATA_RATE_OFFSET 5
+#define SN_TIMING_HIGH_OFFSET 8
+
+#define SN_ENABLE_VID_STREAM_BIT BIT(3)
+#define SN_DSIA_NUM_LANES_BITS (BIT(4) | BIT(3))
+#define SN_DP_NUM_LANES_BITS (BIT(5) | BIT(4))
+#define SN_DP_DATA_RATE_BITS (BIT(7) | BIT(6) | BIT(5))
+#define SN_HPD_DISABLE_BIT BIT(0)
+
+struct ti_sn_bridge {
+ struct device *dev;
+ struct regmap *regmap;
+ struct drm_bridge bridge;
+ struct drm_connector connector;
+ struct device_node *host_node;
+ struct mipi_dsi_device *dsi;
+ struct clk *refclk;
+ struct drm_panel *panel;
+ struct gpio_desc *enable_gpio;
+ unsigned int num_supplies;
+ struct regulator_bulk_data *supplies;
+ struct i2c_adapter *ddc;
+ struct drm_display_mode curr_mode;
+};
+
+static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
+ { .range_min = 0, .range_max = 0xff },
+};
+
+static const struct regmap_access_table ti_sn_bridge_volatile_table = {
+ .yes_ranges = ti_sn_bridge_volatile_ranges,
+ .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges),
+};
+
+static const struct regmap_config ti_sn_bridge_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .volatile_table = &ti_sn_bridge_volatile_table,
+ .cache_type = REGCACHE_NONE,
+};
+
+#ifdef CONFIG_PM
+static int ti_sn_bridge_resume(struct device *dev)
+{
+ struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
+ int ret = 0;
+
+ ret = regulator_bulk_enable(pdata->num_supplies, pdata->supplies);
+ if (ret) {
+ DRM_ERROR("failed to enable supplies %d\n", ret);
+ return ret;
+ }
+
+ gpiod_set_value(pdata->enable_gpio, 1);
+
+ return ret;
+}
+
+static int ti_sn_bridge_suspend(struct device *dev)
+{
+ struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
+ int ret = 0;
+
+ gpiod_set_value(pdata->enable_gpio, 0);
+
+ ret = regulator_bulk_disable(pdata->num_supplies, pdata->supplies);
+ if (ret)
+ DRM_ERROR("failed to disable supplies %d\n", ret);
+
+ return ret;
+}
+#endif
+
+static const struct dev_pm_ops ti_sn_bridge_pm_ops = {
+ SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL)
+};
+
+/* Connector funcs */
+static struct ti_sn_bridge *
+connector_to_ti_sn_bridge(struct drm_connector *connector)
+{
+ return container_of(connector, struct ti_sn_bridge, connector);
+}
+
+static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
+{
+ struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
+ struct drm_panel *panel = pdata->panel;
+ struct edid *edid;
+ u32 num_modes;
+
+ if (panel) {
+ DRM_DEBUG_KMS("get mode from connected drm_panel\n");
+ return drm_panel_get_modes(panel);
+ }
+
+ if (!pdata->ddc)
+ return 0;
+
+ pm_runtime_get_sync(pdata->dev);
+ edid = drm_get_edid(connector, pdata->ddc);
+ pm_runtime_put_sync(pdata->dev);
+ if (!edid)
+ return 0;
+
+ drm_mode_connector_update_edid_property(connector, edid);
+ num_modes = drm_add_edid_modes(connector, edid);
+ kfree(edid);
+
+ return num_modes;
+}
+
+static enum drm_mode_status
+ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ /* maximum supported resolution is 4K at 60 fps */
+ if (mode->clock > 594000)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
+ .get_modes = ti_sn_bridge_connector_get_modes,
+ .mode_valid = ti_sn_bridge_connector_mode_valid,
+};
+
+static enum drm_connector_status
+ti_sn_bridge_connector_detect(struct drm_connector *connector, bool force)
+{
+ struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
+
+ /**
+ * TODO: Currently if drm_panel is present, then always
+ * return the status as connected. Need to add support to detect
+ * device state for no panel(hot pluggable) scenarios.
+ */
+ if (pdata->panel)
+ return connector_status_connected;
+ else
+ return connector_status_unknown;
+}
+
+static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .detect = ti_sn_bridge_connector_detect,
+ .destroy = drm_connector_cleanup,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge *bridge)
+{
+ return container_of(bridge, struct ti_sn_bridge, bridge);
+}
+
+static int ti_sn_bridge_read_device_rev(struct ti_sn_bridge *pdata)
+{
+ unsigned int rev = 0;
+ int ret = 0;
+
+ ret = regmap_read(pdata->regmap, SN_DEVICE_REV_REG, &rev);
+ if (ret) {
+ DRM_ERROR("Revision read failed %d\n", ret);
+ return ret;
+ }
+
+ if (rev != SN_BRIDGE_REVISION_ID) {
+ DRM_ERROR("ti_sn_bridge revision id: 0x%x mismatch\n", rev);
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static const char * const ti_sn_bridge_supply_names[] = {
+ "vcca",
+ "vcc",
+ "vccio",
+ "vpll",
+};
+
+static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata)
+{
+ unsigned int i;
+
+ pdata->num_supplies = ARRAY_SIZE(ti_sn_bridge_supply_names);
+
+ pdata->supplies = devm_kcalloc(pdata->dev, pdata->num_supplies,
+ sizeof(*pdata->supplies), GFP_KERNEL);
+ if (!pdata->supplies)
+ return -ENOMEM;
+
+ for (i = 0; i < pdata->num_supplies; i++)
+ pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
+
+ return devm_regulator_bulk_get(pdata->dev,
+ pdata->num_supplies, pdata->supplies);
+}
+
+static int ti_sn_bridge_attach_panel(struct ti_sn_bridge *pdata)
+{
+ struct device_node *panel_node, *port, *endpoint;
+
+ pdata->panel = NULL;
+ port = of_graph_get_port_by_id(pdata->dev->of_node, 1);
+ if (!port)
+ return 0;
+
+ endpoint = of_get_child_by_name(port, "endpoint");
+ of_node_put(port);
+ if (!endpoint) {
+ DRM_ERROR("no output endpoint found\n");
+ return -EINVAL;
+ }
+
+ panel_node = of_graph_get_remote_port_parent(endpoint);
+ of_node_put(endpoint);
+ if (!panel_node) {
+ DRM_ERROR("no output node found\n");
+ return -EINVAL;
+ }
+
+ pdata->panel = of_drm_find_panel(panel_node);
+ of_node_put(panel_node);
+ if (!pdata->panel) {
+ DRM_ERROR("no panel node found\n");
+ return -EINVAL;
+ }
+ drm_panel_attach(pdata->panel, &pdata->connector);
+ DRM_DEBUG_KMS("drm panel attached to ti_sn_bridge\n");
+
+ return 0;
+}
+
+static int ti_sn_bridge_attach(struct drm_bridge *bridge)
+{
+ struct mipi_dsi_host *host;
+ struct mipi_dsi_device *dsi;
+ struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
+ int ret;
+ const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
+ .channel = 0,
+ .node = NULL,
+ };
+
+ if (!bridge->encoder) {
+ DRM_ERROR("Parent encoder object not found\n");
+ return -ENODEV;
+ }
+
+ /* HPD not supported */
+ pdata->connector.polled = 0;
+
+ ret = drm_connector_init(bridge->dev, &pdata->connector,
+ &ti_sn_bridge_connector_funcs,
+ DRM_MODE_CONNECTOR_eDP);
+ if (ret) {
+ DRM_ERROR("Failed to initialize connector with drm\n");
+ return ret;
+ }
+
+ drm_connector_helper_add(&pdata->connector,
+ &ti_sn_bridge_connector_helper_funcs);
+ drm_mode_connector_attach_encoder(&pdata->connector, bridge->encoder);
+
+ host = of_find_mipi_dsi_host_by_node(pdata->host_node);
+ if (!host) {
+ DRM_ERROR("failed to find dsi host\n");
+ return -ENODEV;
+ }
+
+ dsi = mipi_dsi_device_register_full(host, &info);
+ if (IS_ERR(dsi)) {
+ DRM_ERROR("failed to create dsi device\n");
+ ret = PTR_ERR(dsi);
+ return ret;
+ }
+
+ /* TODO: setting to 4 lanes always for now */
+ dsi->lanes = 4;
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
+
+ ret = mipi_dsi_attach(dsi);
+ if (ret < 0) {
+ DRM_ERROR("failed to attach dsi to host\n");
+ mipi_dsi_device_unregister(dsi);
+ return ret;
+ }
+
+ pdata->dsi = dsi;
+
+ DRM_DEBUG_KMS("ti_sn_bridge attached to dsi\n");
+ /* attach panel to bridge */
+ ti_sn_bridge_attach_panel(pdata);
+
+ return 0;
+}
+
+static void ti_sn_bridge_mode_set(struct drm_bridge *bridge,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adj_mode)
+{
+ struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
+
+ DRM_DEBUG("mode_set: hdisplay=%d, vdisplay=%d, vrefresh=%d, clock=%d\n",
+ adj_mode->hdisplay, adj_mode->vdisplay,
+ adj_mode->vrefresh, adj_mode->clock);
+
+ drm_mode_copy(&pdata->curr_mode, adj_mode);
+}
+
+static void ti_sn_bridge_disable(struct drm_bridge *bridge)
+{
+ struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
+ struct drm_panel *panel = pdata->panel;
+
+ if (panel) {
+ drm_panel_disable(panel);
+ drm_panel_unprepare(panel);
+ }
+
+ /* disable video stream */
+ regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG,
+ SN_ENABLE_VID_STREAM_BIT, 0);
+ /* semi auto link training mode OFF */
+ regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
+ /* disable DP PLL */
+ regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
+}
+
+static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge *pdata)
+{
+ u32 bit_rate_khz, clk_freq_khz;
+ struct drm_display_mode *mode = &pdata->curr_mode;
+
+ bit_rate_khz = mode->clock *
+ mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
+ clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
+
+ return clk_freq_khz;
+}
+
+#define REFCLK_LUT_SIZE 5
+
+/* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
+static const u32 ti_sn_bridge_refclk_lut[] = {
+ 12000000,
+ 19200000,
+ 26000000,
+ 27000000,
+ 38400000,
+};
+
+/* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
+static const u32 ti_sn_bridge_dsiclk_lut[] = {
+ 468000000,
+ 384000000,
+ 416000000,
+ 486000000,
+ 460800000,
+};
+
+static void ti_sn_bridge_set_refclk(struct ti_sn_bridge *pdata)
+{
+ int i = 0;
+ u8 refclk_src;
+ u32 refclk_rate;
+ const u32 *refclk_lut;
+
+ if (pdata->refclk) {
+ refclk_src = DPPLL_CLK_SRC_REFCLK;
+ refclk_rate = clk_get_rate(pdata->refclk);
+ refclk_lut = ti_sn_bridge_refclk_lut;
+ clk_prepare_enable(pdata->refclk);
+ } else {
+ refclk_src = DPPLL_CLK_SRC_DSICLK;
+ refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
+ refclk_lut = ti_sn_bridge_dsiclk_lut;
+ }
+
+ /* for i equals to REFCLK_LUT_SIZE means default frequency */
+ for (i = 0; i < REFCLK_LUT_SIZE; i++)
+ if (refclk_lut[i] == refclk_rate)
+ break;
+
+ regmap_write(pdata->regmap, SN_REFCLK_FREQ_REG,
+ (refclk_src | (i << SN_DSIA_REFCLK_OFFSET)));
+}
+
+/**
+ * LUT index corresponds to register value and
+ * LUT values corresponds to dp data rate supported
+ * by the bridge in Mbps unit.
+ */
+static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
+ 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
+};
+
+static void ti_sn_bridge_set_dsi_dp_rate(struct ti_sn_bridge *pdata)
+{
+ unsigned int bit_rate_mhz, clk_freq_mhz, dp_rate_mhz;
+ unsigned int val = 0, i = 0;
+ struct drm_display_mode *mode = &pdata->curr_mode;
+
+ /* set DSIA clk frequency */
+ bit_rate_mhz = (mode->clock / 1000) *
+ mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
+ clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
+
+ /* for each increment in val, frequency increases by 5MHz */
+ val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
+ (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
+ regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
+
+ /* set DP data rate */
+ dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) /
+ DP_CLK_FUDGE_DEN;
+ for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++)
+ if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz)
+ break;
+ if (i == ARRAY_SIZE(ti_sn_bridge_dp_rate_lut))
+ i--; /* set to maximum possible */
+
+ regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
+ SN_DP_DATA_RATE_BITS, i << SN_DP_DATA_RATE_OFFSET);
+}
+
+static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
+{
+ struct drm_display_mode *mode = &pdata->curr_mode;
+
+ regmap_write(pdata->regmap, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
+ mode->hdisplay & 0xFF);
+ regmap_write(pdata->regmap, SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG,
+ (mode->hdisplay >> SN_TIMING_HIGH_OFFSET) & 0xFF);
+ regmap_write(pdata->regmap, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
+ mode->vdisplay & 0xFF);
+ regmap_write(pdata->regmap, SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG,
+ (mode->vdisplay >> SN_TIMING_HIGH_OFFSET) & 0xFF);
+ regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
+ (mode->hsync_end - mode->hsync_start) & 0xFF);
+ regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
+ ((mode->hsync_end - mode->hsync_start) >>
+ SN_TIMING_HIGH_OFFSET) & 0xFF);
+ regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
+ (mode->vsync_end - mode->vsync_start) & 0xFF);
+ regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
+ ((mode->vsync_end - mode->vsync_start) >>
+ SN_TIMING_HIGH_OFFSET) & 0xFF);
+ regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
+ (mode->htotal - mode->hsync_end) & 0xFF);
+ regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
+ (mode->vtotal - mode->vsync_end) & 0xFF);
+ regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
+ (mode->hsync_start - mode->hdisplay) & 0xFF);
+ regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
+ (mode->vsync_start - mode->vdisplay) & 0xFF);
+ usleep_range(10000, 10500); /* 10ms delay recommended by spec */
+}
+
+static void ti_sn_bridge_enable(struct drm_bridge *bridge)
+{
+ struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
+ struct drm_panel *panel = pdata->panel;
+ unsigned int val = 0;
+
+ if (panel) {
+ drm_panel_prepare(panel);
+ /* in case drm_panel is connected then HPD is not supported */
+ regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG,
+ SN_HPD_DISABLE_BIT, SN_HPD_DISABLE_BIT);
+ }
+
+ /* DSI_A lane config */
+ val = (4 - pdata->dsi->lanes) << SN_DSIA_LANE_OFFSET;
+ regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
+ SN_DSIA_NUM_LANES_BITS, val);
+
+ /* DP lane config */
+ val = (pdata->dsi->lanes - 1) << SN_DP_LANE_OFFSET;
+ regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG,
+ SN_DP_NUM_LANES_BITS, val);
+
+ /* set dsi/dp clk frequency value */
+ ti_sn_bridge_set_dsi_dp_rate(pdata);
+
+ /* enable DP PLL */
+ regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
+ usleep_range(10000, 10500); /* 10ms delay recommended by spec */
+
+ /**
+ * The SN65DSI86 only supports ASSR Display Authentication method and
+ * this method is enabled by default. An eDP panel must support this
+ * authentication method. We need to enable this method in the eDP panel
+ * at DisplayPort address 0x0010A prior to link training.
+ */
+ regmap_write(pdata->regmap, SN_AUX_WDATA0_REG, 0x01);
+ regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, 0x00);
+ regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG, 0x01);
+ regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, 0x0A);
+ regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, 0x01);
+ regmap_write(pdata->regmap, SN_AUX_CMD_REG, 0x81);
+ usleep_range(10000, 10500); /* 10ms delay recommended by spec */
+
+ /* Semi auto link training mode */
+ regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
+ msleep(20); /* 20ms delay recommended by spec */
+
+ /* config video parameters */
+ ti_sn_bridge_set_video_timings(pdata);
+
+ /* enable video stream */
+ regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG,
+ SN_ENABLE_VID_STREAM_BIT, SN_ENABLE_VID_STREAM_BIT);
+
+ if (panel)
+ drm_panel_enable(panel);
+}
+
+static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
+{
+ struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
+
+ pm_runtime_get_sync(pdata->dev);
+
+ /* configure bridge CLK_SRC and ref_clk */
+ ti_sn_bridge_set_refclk(pdata);
+}
+
+static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
+{
+ struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
+
+ if (pdata->refclk)
+ clk_disable_unprepare(pdata->refclk);
+
+ pm_runtime_put_sync(pdata->dev);
+}
+
+static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
+ .attach = ti_sn_bridge_attach,
+ .pre_enable = ti_sn_bridge_pre_enable,
+ .enable = ti_sn_bridge_enable,
+ .disable = ti_sn_bridge_disable,
+ .post_disable = ti_sn_bridge_post_disable,
+ .mode_set = ti_sn_bridge_mode_set,
+};
+
+static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata)
+{
+ struct device_node *np = pdata->dev->of_node;
+ struct device_node *end_node;
+
+ end_node = of_graph_get_endpoint_by_regs(np, 0, 0);
+ if (!end_node) {
+ DRM_ERROR("remote endpoint not found\n");
+ return -ENODEV;
+ }
+
+ pdata->host_node = of_graph_get_remote_port_parent(end_node);
+ of_node_put(end_node);
+ if (!pdata->host_node) {
+ DRM_ERROR("remote node not found\n");
+ return -ENODEV;
+ }
+ of_node_put(pdata->host_node);
+
+ return 0;
+}
+
+static int ti_sn_bridge_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct ti_sn_bridge *pdata;
+ struct device_node *ddc_node;
+ int ret = 0;
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+ DRM_ERROR("device doesn't support I2C\n");
+ return -ENODEV;
+ }
+
+ pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge),
+ GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ pdata->dev = &client->dev;
+ dev_set_drvdata(&client->dev, pdata);
+
+ pdata->regmap = devm_regmap_init_i2c(client,
+ &ti_sn_bridge_regmap_config);
+ if (IS_ERR(pdata->regmap)) {
+ DRM_ERROR("regmap i2c init failed\n");
+ return PTR_ERR(pdata->regmap);
+ }
+
+ pdata->enable_gpio = devm_gpiod_get(pdata->dev,
+ "enable", GPIOD_OUT_LOW);
+ if (IS_ERR(pdata->enable_gpio)) {
+ DRM_ERROR("failed to get enable gpio from DT\n");
+ ret = PTR_ERR(pdata->enable_gpio);
+ return ret;
+ }
+
+ ret = ti_sn_bridge_parse_regulators(pdata);
+ if (ret) {
+ DRM_ERROR("failed to parse regulators\n");
+ return ret;
+ }
+
+ ret = ti_sn_bridge_parse_dsi_host(pdata);
+ if (ret)
+ return ret;
+
+ pm_runtime_enable(pdata->dev);
+ pm_runtime_get_sync(pdata->dev);
+ ret = ti_sn_bridge_read_device_rev(pdata);
+ pm_runtime_put_sync(pdata->dev);
+ if (ret)
+ goto err_rev_read;
+
+ pdata->refclk = devm_clk_get(pdata->dev, "refclk");
+
+ ddc_node = of_parse_phandle(pdata->dev->of_node, "ddc-i2c-bus", 0);
+ if (ddc_node) {
+ pdata->ddc = of_find_i2c_adapter_by_node(ddc_node);
+ of_node_put(ddc_node);
+ if (!pdata->ddc) {
+ DRM_DEBUG_KMS("failed to read ddc node\n");
+ ret = -EPROBE_DEFER;
+ goto err_rev_read;
+ }
+ } else {
+ DRM_DEBUG_KMS("no ddc property found\n");
+ }
+
+ i2c_set_clientdata(client, pdata);
+
+ pdata->bridge.funcs = &ti_sn_bridge_funcs;
+ pdata->bridge.of_node = client->dev.of_node;
+
+ drm_bridge_add(&pdata->bridge);
+
+ return 0;
+
+err_rev_read:
+ pm_runtime_disable(pdata->dev);
+ return ret;
+}
+
+static int ti_sn_bridge_remove(struct i2c_client *client)
+{
+ struct ti_sn_bridge *pdata = i2c_get_clientdata(client);
+
+ if (!pdata)
+ return -EINVAL;
+
+ mipi_dsi_detach(pdata->dsi);
+ mipi_dsi_device_unregister(pdata->dsi);
+
+ drm_bridge_remove(&pdata->bridge);
+ pm_runtime_disable(pdata->dev);
+ i2c_put_adapter(pdata->ddc);
+
+ return 0;
+}
+
+static struct i2c_device_id ti_sn_bridge_id[] = {
+ { "ti,sn65dsi86", 0},
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id);
+
+static const struct of_device_id ti_sn_bridge_match_table[] = {
+ {.compatible = "ti,sn65dsi86"},
+ {},
+};
+MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table);
+
+static struct i2c_driver ti_sn_bridge_driver = {
+ .driver = {
+ .name = "ti_sn65dsi86",
+ .of_match_table = ti_sn_bridge_match_table,
+ .pm = &ti_sn_bridge_pm_ops,
+ },
+ .probe = ti_sn_bridge_probe,
+ .remove = ti_sn_bridge_remove,
+ .id_table = ti_sn_bridge_id,
+};
+
+module_i2c_driver(ti_sn_bridge_driver);
+MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
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Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related
* [PATCH v6 0/4] Add suppport for sn65dsi86 bridge chip and Innolux 2k edp panel
From: Sandeep Panda @ 2018-05-15 5:52 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: ryadav-sgV2jX0FEOL9JmXXK+q4OQ, Sandeep Panda,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, robdclark-Re5JQEeQqe8AvxtiuMwx3w,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, seanpaul-F7+t8E8rja9g9hUCZPvPmw,
hoegsberg-F7+t8E8rja9g9hUCZPvPmw, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ
Changes in current patchset:
- Use PM runtime based ref-counting instead of local ref_count mechanism.
- Simplify dp rate calculation.
- Add support to configure refclk based on input REFCLK pin or DACP/N pin.
- Add compatibility string and display_mode structure to simple panel driver
in alphabetical order.
Sandeep Panda (4):
drm/bridge: add support for sn65dsi86 bridge driver
dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings
drm/panel: add Innolux TV123WAM panel driver support
dt-bindings: drm/panel: Document Innolux TV123WAM panel bindings
.../bindings/display/bridge/ti,sn65dsi86.txt | 81 +++
.../bindings/display/panel/innolux,tv123wam.txt | 20 +
drivers/gpu/drm/bridge/Kconfig | 9 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 766 +++++++++++++++++++++
drivers/gpu/drm/panel/panel-simple.c | 27 +
6 files changed, 904 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
create mode 100644 Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt
create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi86.c
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
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Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply
* Re: [PATCH v5 3/4] drm/panel: add Innolux TV123WAM panel driver support
From: spanda-sgV2jX0FEOL9JmXXK+q4OQ @ 2018-05-15 5:50 UTC (permalink / raw)
To: Sean Paul
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, nganji-sgV2jX0FEOL9JmXXK+q4OQ,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
jsanka-sgV2jX0FEOL9JmXXK+q4OQ, chandanu-sgV2jX0FEOL9JmXXK+q4OQ
In-Reply-To: <20180502190556.GS73214@art_vandelay>
On 2018-05-03 00:35, Sean Paul wrote:
> On Wed, May 02, 2018 at 10:02:01AM +0530, Sandeep Panda wrote:
>> Add support for Innolux TV123WAM, which is a 12.3" eDP
>> display panel with 2160x1440 resolution.
>>
>> Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
>> ---
>> drivers/gpu/drm/panel/panel-simple.c | 27 +++++++++++++++++++++++++++
>> 1 file changed, 27 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/panel/panel-simple.c
>> b/drivers/gpu/drm/panel/panel-simple.c
>> index 234af81..52bbcfb 100644
>> --- a/drivers/gpu/drm/panel/panel-simple.c
>> +++ b/drivers/gpu/drm/panel/panel-simple.c
>> @@ -1939,6 +1939,30 @@ static void panel_simple_shutdown(struct device
>> *dev)
>> .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
>> };
>>
>> +static const struct drm_display_mode innolux_tv123wam_mode = {
>> + .clock = 206016,
>> + .hdisplay = 2160,
>> + .hsync_start = 2160 + 48,
>> + .hsync_end = 2160 + 48 + 32,
>> + .htotal = 2160 + 48 + 32 + 80,
>> + .vdisplay = 1440,
>> + .vsync_start = 1440 + 3,
>> + .vsync_end = 1440 + 3 + 10,
>> + .vtotal = 1440 + 3 + 10 + 27,
>> + .vrefresh = 60,
>> + .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
>> +};
>> +
>> +static const struct panel_desc innolux_tv123wam = {
>> + .modes = &innolux_tv123wam_mode,
>> + .num_modes = 1,
>> + .bpc = 8,
>> + .size = {
>> + .width = 259,
>> + .height = 173,
>> + },
>> +};
>> +
>> static const struct of_device_id platform_of_match[] = {
>> {
>> .compatible = "ampire,am-480272h3tmqw-t01h",
>> @@ -2142,6 +2166,9 @@ static void panel_simple_shutdown(struct device
>> *dev)
>> .compatible = "winstar,wf35ltiacd",
>> .data = &winstar_wf35ltiacd,
>> }, {
>> + .compatible = "innolux,tv123wam",
>> + .data = &innolux_tv123wam,
>> + }, {
>
> These are alphabetically ordered, as are the
> drm_display_mode/panel_desc
> structs.
>
> Sean
>
Done.
>> /* sentinel */
>> }
>> };
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>> Forum,
>> a Linux Foundation Collaborative Project
>>
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply
* Re: [PATCH v5 1/4] drm/bridge: add support for sn65dsi86 bridge driver
From: spanda-sgV2jX0FEOL9JmXXK+q4OQ @ 2018-05-15 5:50 UTC (permalink / raw)
To: Sean Paul
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, nganji-sgV2jX0FEOL9JmXXK+q4OQ,
abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
jsanka-sgV2jX0FEOL9JmXXK+q4OQ, chandanu-sgV2jX0FEOL9JmXXK+q4OQ
In-Reply-To: <20180502190316.GR73214@art_vandelay>
On 2018-05-03 00:33, Sean Paul wrote:
> On Wed, May 02, 2018 at 10:01:59AM +0530, Sandeep Panda wrote:
>> Add support for TI's sn65dsi86 dsi2edp bridge chip.
>> The chip converts DSI transmitted signal to eDP signal,
>> which is fed to the connected eDP panel.
>>
>> This chip can be controlled via either i2c interface or
>> dsi interface. Currently in driver all the control registers
>> are being accessed through i2c interface only.
>> Also as of now HPD support has not been added to bridge
>> chip driver.
>>
>> Changes in v1:
>> - Split the dt-bindings and the driver support into separate patches
>> (Andrzej Hajda).
>> - Use of gpiod APIs to parse and configure gpios instead of obsolete
>> ones
>> (Andrzej Hajda).
>> - Use macros to define the register offsets (Andrzej Hajda).
>>
>> Changes in v2:
>> - Separate out edp panel specific HW resource handling from bridge
>> driver and create a separate edp panel drivers to handle panel
>> specific mode information and HW resources (Sean Paul).
>> - Replace pr_* APIs to DRM_* APIs to log error or debug information
>> (Sean Paul).
>> - Remove some of the unnecessary structure/variable from driver (Sean
>> Paul).
>> - Rename the function and structure prefix "sn65dsi86" to
>> "ti_sn_bridge"
>> (Sean Paul / Rob Herring).
>> - Remove most of the hard-coding and modified the bridge init
>> sequence
>> based on current mode (Sean Paul).
>> - Remove the existing function to retrieve the EDID data and
>> implemented this as an i2c_adapter and use drm_get_edid() (Sean
>> Paul).
>> - Remove the dummy irq handler implementation, will add back the
>> proper irq handling later (Sean Paul).
>> - Capture the required enable gpios in a single array based on dt
>> entry
>> instead of having individual descriptor for each gpio (Sean Paul).
>>
>> Changes in v3:
>> - Remove usage of irq_gpio and replace it as "interrupts" property
>> (Rob
>> Herring).
>> - Remove the unnecessary header file inclusions (Sean Paul).
>> - Rearrange the header files in alphabetical order (Sean Paul).
>> - Use regmap interface to perform i2c transactions.
>> - Update Copyright/License field and address other review comments
>> (Jordan Crouse).
>>
>> Changes in v4:
>> - Update License/Copyright (Sean Paul).
>> - Add Kconfig and Makefile changes (Sean Paul).
>> - Drop i2c gpio handling from this bridge driver, since i2c sda/scl
>> gpios
>> will be handled by i2c master.
>> - Remove unnecessary goto statements (Sean Paul).
>> - Add mutex lock to power_ctrl API to avoid race conditions (Sean
>> Paul).
>> - Add support to parse reference clk frequency from dt(optional).
>> - Update the bridge chip enable/disable sequence.
>
> It seems like you also added 2 new supply names, as well as remove the
> configurable gpios?
>
>>
>> Changes in v5:
>> - Fixed Kbuild test service reported warnings.
>>
>> Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
>> ---
>> drivers/gpu/drm/bridge/Kconfig | 9 +
>> drivers/gpu/drm/bridge/Makefile | 1 +
>> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 725
>> ++++++++++++++++++++++++++++++++++
>> 3 files changed, 735 insertions(+)
>> create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi86.c
>>
>> diff --git a/drivers/gpu/drm/bridge/Kconfig
>> b/drivers/gpu/drm/bridge/Kconfig
>> index 3b99d5a..8153150 100644
>> --- a/drivers/gpu/drm/bridge/Kconfig
>> +++ b/drivers/gpu/drm/bridge/Kconfig
>> @@ -108,6 +108,15 @@ config DRM_TI_TFP410
>> ---help---
>> Texas Instruments TFP410 DVI/HDMI Transmitter driver
>>
>> +config DRM_TI_SN65DSI86
>> + tristate "TI SN65DSI86 DSI to eDP bridge"
>> + depends on OF
>> + select DRM_KMS_HELPER
>> + select REGMAP_I2C
>> + select DRM_PANEL
>> + ---help---
>> + Texas Instruments SN65DSI86 DSI to eDP Bridge driver
>> +
>> source "drivers/gpu/drm/bridge/analogix/Kconfig"
>>
>> source "drivers/gpu/drm/bridge/adv7511/Kconfig"
>> diff --git a/drivers/gpu/drm/bridge/Makefile
>> b/drivers/gpu/drm/bridge/Makefile
>> index 373eb28..3711be8 100644
>> --- a/drivers/gpu/drm/bridge/Makefile
>> +++ b/drivers/gpu/drm/bridge/Makefile
>> @@ -12,4 +12,5 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
>> obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
>> obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
>> obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
>> +obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
>> obj-y += synopsys/
>> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
>> b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
>> new file mode 100644
>> index 0000000..019c7cd
>> --- /dev/null
>> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
>> @@ -0,0 +1,725 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <drm/drmP.h>
>> +#include <drm/drm_atomic.h>
>> +#include <drm/drm_atomic_helper.h>
>> +#include <drm/drm_crtc_helper.h>
>> +#include <drm/drm_mipi_dsi.h>
>> +#include <drm/drm_panel.h>
>> +#include <linux/gpio.h>
>> +#include <linux/i2c.h>
>> +#include <linux/of_gpio.h>
>> +#include <linux/of_graph.h>
>> +#include <linux/regmap.h>
>> +#include <linux/regulator/consumer.h>
>> +
>> +#define SN_BRIDGE_REVISION_ID 0x2
>> +
>> +/* Link Training specific registers */
>> +#define SN_DEVICE_REV_REG 0x08
>> +#define SN_HPD_DISABLE_REG 0x5C
>> +#define SN_REFCLK_FREQ_REG 0x0A
>> +#define SN_DSI_LANES_REG 0x10
>> +#define SN_DSIA_CLK_FREQ_REG 0x12
>> +#define SN_ENH_FRAME_REG 0x5A
>> +#define SN_SSC_CONFIG_REG 0x93
>> +#define SN_DATARATE_CONFIG_REG 0x94
>> +#define SN_PLL_ENABLE_REG 0x0D
>> +#define SN_SCRAMBLE_CONFIG_REG 0x95
>> +#define SN_AUX_WDATA0_REG 0x64
>> +#define SN_AUX_ADDR_19_16_REG 0x74
>> +#define SN_AUX_ADDR_15_8_REG 0x75
>> +#define SN_AUX_ADDR_7_0_REG 0x76
>> +#define SN_AUX_LENGTH_REG 0x77
>> +#define SN_AUX_CMD_REG 0x78
>> +#define SN_ML_TX_MODE_REG 0x96
>> +/* video config specific registers */
>> +#define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
>> +#define SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG 0x21
>> +#define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
>> +#define SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG 0x25
>> +#define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
>> +#define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
>> +#define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
>> +#define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
>> +#define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
>> +#define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
>> +#define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
>> +#define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
>> +#define SN_DATA_FORMAT_REG 0x5B
>> +
>> +#define MIN_DSI_CLK_FREQ_MHZ 40
>> +#define SN_DEFAULT_REF_CLK_KHZ 19200
>> +
>> +/* fudge factor required to account for 8b/10b encoding */
>> +#define DP_CLK_FUDGE_NUM 10
>> +#define DP_CLK_FUDGE_DEN 8
>> +
>> +#define DPPLL_CLK_SRC_REFCLK 0
>> +#define DPPLL_CLK_SRC_DSICLK 1
>> +
>> +#define SN_DSIA_REFCLK_OFFSET 1
>> +#define SN_DSIA_LANE_OFFSET 3
>> +#define SN_DP_LANE_OFFSET 4
>> +#define SN_DP_DATA_RATE_OFFSET 5
>> +#define SN_TIMING_HIGH_OFFSET 8
>> +
>> +#define SN_ENABLE_VID_STREAM_BIT BIT(3)
>> +#define SN_DSIA_NUM_LANES_BITS (BIT(4) | BIT(3))
>> +#define SN_DP_NUM_LANES_BITS (BIT(5) | BIT(4))
>> +#define SN_DP_DATA_RATE_BITS (BIT(7) | BIT(6) | BIT(5))
>> +#define SN_HPD_DISABLE_BIT BIT(0)
>> +
>> +struct ti_sn_bridge {
>> + struct device *dev;
>> + struct regmap *regmap;
>> + struct drm_bridge bridge;
>> + struct drm_connector connector;
>> + struct device_node *host_node;
>> + struct mipi_dsi_device *dsi;
>> + unsigned int refclk_khz;
>> + struct drm_panel *panel;
>> + struct gpio_desc *enable_gpio;
>> + unsigned int num_supplies;
>> + struct regulator_bulk_data *supplies;
>> + struct i2c_adapter *ddc;
>> + unsigned int num_modes;
>
> You only use this in one function, it should be a local.
>
Removed.
>> + struct drm_display_mode curr_mode;
>> + struct mutex lock;
>> + unsigned int ctrl_ref_count;
>> +};
>> +
>> +static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
>> + { .range_min = 0, .range_max = 0xff },
>> +};
>> +
>> +static const struct regmap_access_table ti_sn_bridge_volatile_table =
>> {
>> + .yes_ranges = ti_sn_bridge_volatile_ranges,
>> + .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges),
>> +};
>> +
>> +static const struct regmap_config ti_sn_bridge_regmap_config = {
>> + .reg_bits = 8,
>> + .val_bits = 8,
>> + .volatile_table = &ti_sn_bridge_volatile_table,
>> + .cache_type = REGCACHE_NONE,
>> +};
>> +
>> +static int ti_sn_bridge_power_ctrl(struct ti_sn_bridge *pdata, bool
>> enable)
>> +{
>> + int ret = 0;
>> +
>> + mutex_lock(&pdata->lock);
>> + if (enable)
>> + pdata->ctrl_ref_count++;
>> + else
>> + pdata->ctrl_ref_count--;
>
> I think you should use a kref instead of rolling your own ref_count.
> You can
> handle release by calling kref_put_mutex(), which will handle the
> reference and
> the lock. On the acquire side, you can use kref_get_unless_zero which
> will be
> fast if the reference is already active.
>
As per comment from Stephen Boyd used PM runtime instead of our own
ref_count.
>> +
>> + if (enable && (pdata->ctrl_ref_count == 1)) {
>> + ret = regulator_bulk_enable(pdata->num_supplies,
>> + pdata->supplies);
>> + if (ret) {
>> + DRM_ERROR("bridge regulator enable failed\n");
>
> print ret on failure
>
Done.
>> + goto exit;
>> + }
>> +
>> + gpiod_set_value(pdata->enable_gpio, 1);
>> + } else if (!enable && !pdata->ctrl_ref_count) {
>> + gpiod_set_value(pdata->enable_gpio, 0);
>> +
>> + regulator_bulk_disable(pdata->num_supplies, pdata->supplies);
>> + } else {
>> + DRM_DEBUG("ti_sn_bridge power ctrl: %d refcount: %d\n",
>> + enable, pdata->ctrl_ref_count);
>
> No need for this.
>
Removed.
>> + }
>> +
>> +exit:
>> + mutex_unlock(&pdata->lock);
>> + return ret;
>> +}
>> +
>> +/* Connector funcs */
>> +static struct ti_sn_bridge *
>> +connector_to_ti_sn_bridge(struct drm_connector *connector)
>> +{
>> + return container_of(connector, struct ti_sn_bridge, connector);
>> +}
>> +
>> +static int ti_sn_bridge_connector_get_modes(struct drm_connector
>> *connector)
>> +{
>> + struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
>> + struct drm_panel *panel = pdata->panel;
>> + struct edid *edid;
>> +
>> + if (panel) {
>> + DRM_DEBUG("get mode from connected drm_panel\n");
>> + pdata->num_modes = drm_panel_get_modes(panel);
>> + return pdata->num_modes;
>> + }
>> +
>> + /* get from EDID */
>
> This comment isn't useful.
>
Removed.
>> + if (!pdata->ddc)
>> + return 0;
>> +
>> + ti_sn_bridge_power_ctrl(pdata, true);
>> + edid = drm_get_edid(connector, pdata->ddc);
>> + ti_sn_bridge_power_ctrl(pdata, false);
>> + if (!edid)
>> + return 0;
>> +
>> + drm_mode_connector_update_edid_property(connector, edid);
>> + pdata->num_modes = drm_add_edid_modes(connector, edid);
>> + kfree(edid);
>> +
>> + return pdata->num_modes;
>> +}
>> +
>> +static enum drm_mode_status
>> +ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
>> + struct drm_display_mode *mode)
>> +{
>> + /* maximum supported resolution is 4K at 60 fps */
>> + if (mode->clock > 594000)
>> + return MODE_CLOCK_HIGH;
>> +
>> + return MODE_OK;
>> +}
>> +
>> +static struct drm_connector_helper_funcs
>> ti_sn_bridge_connector_helper_funcs = {
>> + .get_modes = ti_sn_bridge_connector_get_modes,
>> + .mode_valid = ti_sn_bridge_connector_mode_valid,
>> +};
>> +
>> +static enum drm_connector_status
>> +ti_sn_bridge_connector_detect(struct drm_connector *connector, bool
>> force)
>> +{
>> + struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
>> +
>> + /**
>> + * TODO: Currently if drm_panel is present, then always
>> + * return the status as connected. Need to add support to detect
>> + * device state for no panel(hot pluggable) scenarios.
>> + */
>> + if (pdata->panel)
>> + return connector_status_connected;
>> + else
>> + return connector_status_unknown;
>> +}
>> +
>> +static const struct drm_connector_funcs ti_sn_bridge_connector_funcs
>> = {
>> + .fill_modes = drm_helper_probe_single_connector_modes,
>> + .detect = ti_sn_bridge_connector_detect,
>> + .destroy = drm_connector_cleanup,
>> + .reset = drm_atomic_helper_connector_reset,
>> + .atomic_duplicate_state =
>> drm_atomic_helper_connector_duplicate_state,
>> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
>> +};
>> +
>> +static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge
>> *bridge)
>> +{
>> + return container_of(bridge, struct ti_sn_bridge, bridge);
>> +}
>> +
>> +static int ti_sn_bridge_read_device_rev(struct ti_sn_bridge *pdata)
>> +{
>> + unsigned int rev = 0;
>> + int ret = 0;
>> +
>> + ret = regmap_read(pdata->regmap, SN_DEVICE_REV_REG, &rev);
>> + if (ret)
>> + return ret;
>> +
>> + if (rev != SN_BRIDGE_REVISION_ID) {
>> + DRM_ERROR("ti_sn_bridge revision id: 0x%x mismatch\n", rev);
>> + ret = -EINVAL;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static const char * const ti_sn_bridge_supply_names[] = {
>> + "vcca",
>> + "vcc",
>> + "vccio",
>> + "vpll",
>> +};
>> +
>> +static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata)
>> +{
>> + unsigned int i;
>> +
>> + pdata->num_supplies = ARRAY_SIZE(ti_sn_bridge_supply_names);
>> +
>> + pdata->supplies = devm_kcalloc(pdata->dev, pdata->num_supplies,
>> + sizeof(*pdata->supplies), GFP_KERNEL);
>> + if (!pdata->supplies)
>> + return -ENOMEM;
>> +
>> + for (i = 0; i < pdata->num_supplies; i++)
>> + pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
>> +
>> + return devm_regulator_bulk_get(pdata->dev,
>> + pdata->num_supplies, pdata->supplies);
>> +}
>> +
>> +static int ti_sn_bridge_attach_panel(struct ti_sn_bridge *pdata)
>> +{
>> + struct device_node *panel_node, *port, *endpoint;
>> +
>> + pdata->panel = NULL;
>> + port = of_graph_get_port_by_id(pdata->dev->of_node, 1);
>> + if (port) {
>
> Flip this to avoid indenting the whole function. ie:
>
> if (!port)
> return 0;
>
Done.
>> + endpoint = of_get_child_by_name(port, "endpoint");
>> + of_node_put(port);
>> + if (!endpoint) {
>> + DRM_ERROR("no output endpoint found\n");
>> + return -EINVAL;
>> + }
>> +
>> + panel_node = of_graph_get_remote_port_parent(endpoint);
>> + of_node_put(endpoint);
>> + if (!panel_node) {
>> + DRM_ERROR("no output node found\n");
>> + return -EINVAL;
>> + }
>> +
>> + pdata->panel = of_drm_find_panel(panel_node);
>> + of_node_put(panel_node);
>> + if (!pdata->panel) {
>> + DRM_ERROR("no panel node found\n");
>> + return -EINVAL;
>> + }
>> + drm_panel_attach(pdata->panel, &pdata->connector);
>> + DRM_DEBUG("panel attached\n");
>
> This log should be DRM_DEBUG_KMS and you should be more descriptive in
> your
> message (ie: "Attached sn65dsi86 panel").
>
Updated the debug log.
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int ti_sn_bridge_attach(struct drm_bridge *bridge)
>> +{
>> + struct mipi_dsi_host *host;
>> + struct mipi_dsi_device *dsi;
>> + struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
>> + int ret;
>> + const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
>> + .channel = 0,
>> + .node = NULL,
>> + };
>> +
>> + if (!bridge->encoder) {
>> + DRM_ERROR("Parent encoder object not found\n");
>> + return -ENODEV;
>> + }
>> +
>> + /* HPD not supported */
>> + pdata->connector.polled = 0;
>> +
>> + ret = drm_connector_init(bridge->dev, &pdata->connector,
>> + &ti_sn_bridge_connector_funcs,
>> + DRM_MODE_CONNECTOR_eDP);
>> + if (ret) {
>> + DRM_ERROR("Failed to initialize connector with drm\n");
>> + return ret;
>> + }
>> +
>> + drm_connector_helper_add(&pdata->connector,
>> + &ti_sn_bridge_connector_helper_funcs);
>> + drm_mode_connector_attach_encoder(&pdata->connector,
>> bridge->encoder);
>> +
>> + host = of_find_mipi_dsi_host_by_node(pdata->host_node);
>> + if (!host) {
>> + DRM_ERROR("failed to find dsi host\n");
>> + return -ENODEV;
>> + }
>> +
>> + dsi = mipi_dsi_device_register_full(host, &info);
>> + if (IS_ERR(dsi)) {
>> + DRM_ERROR("failed to create dsi device\n");
>> + ret = PTR_ERR(dsi);
>> + return ret;
>> + }
>> +
>> + /* TODO: setting to 4 lanes always for now */
>> + dsi->lanes = 4;
>> + dsi->format = MIPI_DSI_FMT_RGB888;
>> + dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
>> MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
>> + MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
>> +
>> + ret = mipi_dsi_attach(dsi);
>> + if (ret < 0) {
>> + DRM_ERROR("failed to attach dsi to host\n");
>> + mipi_dsi_device_unregister(dsi);
>> + return ret;
>> + }
>> +
>> + pdata->dsi = dsi;
>> +
>> + DRM_DEBUG("bridge attached\n");
>
> Same comment here regarding being more descriptive.
>
>> + /* attach panel to bridge */
>> + ti_sn_bridge_attach_panel(pdata);
>> +
>> + return 0;
>> +}
>> +
>> +static void ti_sn_bridge_mode_set(struct drm_bridge *bridge,
>> + struct drm_display_mode *mode,
>> + struct drm_display_mode *adj_mode)
>> +{
>> + struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
>> +
>> + DRM_DEBUG("mode_set: hdisplay=%d, vdisplay=%d, vrefresh=%d,
>> clock=%d\n",
>> + adj_mode->hdisplay, adj_mode->vdisplay,
>> + adj_mode->vrefresh, adj_mode->clock);
>> +
>> + drm_mode_copy(&pdata->curr_mode, adj_mode);
>> +}
>> +
>> +static void ti_sn_bridge_disable(struct drm_bridge *bridge)
>> +{
>> + struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
>> + struct drm_panel *panel = pdata->panel;
>> +
>> + if (panel) {
>> + drm_panel_disable(panel);
>> + drm_panel_unprepare(panel);
>> + }
>> +
>> + /* disable video stream */
>> + regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG,
>> + SN_ENABLE_VID_STREAM_BIT, 0);
>> + /* semi auto link training mode OFF */
>> + regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
>> + /* disable DP PLL */
>> + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
>> +}
>> +
>> +/* reference clk frequencies supported by the bridge in KHz */
>> +static u32 ti_sn_bridge_ref_clk_table[] = {
>> + 12000,
>> + 19200,
>> + 26000,
>> + 27000,
>> + 38400,
>> +};
>> +
>> +static void ti_sn_bridge_set_refclk(struct ti_sn_bridge *pdata)
>> +{
>> + int i = 0;
>> +
>> + for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_ref_clk_table); i++)
>> + if (ti_sn_bridge_ref_clk_table[i] == pdata->refclk_khz)
>> + break;
>> + regmap_write(pdata->regmap, SN_REFCLK_FREQ_REG,
>> + (DPPLL_CLK_SRC_REFCLK | (i << SN_DSIA_REFCLK_OFFSET)));
>
> What if the refclk frequency isn't found?
>
If refclk frequency is not found then we will program i=5, which is also
valid as per datasheet, this means 19.2MHz.
>> +}
>> +
>> +struct dp_data_rate {
>> + unsigned int bit_val;
>> + unsigned int dp_rate;
>> +};
>> +
>> +/* dp data rate supported by the bridge Mbps */
>> +static struct dp_data_rate ti_sn_bridge_dp_rate_table[] = {
>> + {1, 1620},
>> + {2, 2160},
>> + {3, 2430},
>> + {4, 2700},
>> + {5, 3240},
>> + {6, 4320},
>> + {7, 5400},
>> +};
>> +
>> +static void ti_sn_bridge_set_dsi_dp_rate(struct ti_sn_bridge *pdata)
>> +{
>> + unsigned int bit_rate_mhz, clk_freq_mhz, dp_rate_mhz;
>> + unsigned int val = 0, i = 0;
>> + struct drm_display_mode *mode = &pdata->curr_mode;
>> +
>> + /* set DSIA clk frequency */
>> + bit_rate_mhz = (mode->clock / 1000) *
>> + mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
>> + clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
>> +
>> + /* for each increment in val, frequency increases by 5MHz */
>> + val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
>> + (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
>> + regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
>> +
>> + /* set DP data rate */
>> + dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) *
>> DP_CLK_FUDGE_NUM) /
>> + DP_CLK_FUDGE_DEN;
>> + for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_table); i++)
>> + if (ti_sn_bridge_dp_rate_table[i].dp_rate > dp_rate_mhz)
>> + break;
>> + if (i == ARRAY_SIZE(ti_sn_bridge_dp_rate_table))
>> + i--; /* set to maximum possible */
>> +
>> + val = ti_sn_bridge_dp_rate_table[i].bit_val <<
>> SN_DP_DATA_RATE_OFFSET;
>> + regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
>> + SN_DP_DATA_RATE_BITS, val);
>
> I think this can be simplified.
>
> /* Array index corresponds to register value */
> static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
> 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
> };
>
> static void ti_sn_bridge_set_dsi_dp_rate(struct ti_sn_bridge *pdata)
> {
> ...
> for (i = ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i >= 0; i--)
> {
> if (ti_sn_bridge_dp_rate_lut[i] <= dp_rate_mhz)
> break;
> }
> regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
> SN_DP_DATA_RATE_BITS, i <<
> SN_DP_DATA_RATE_OFFSET);
> }
>
As per datasheet we have to program the dp data rate greater than stream
rate.
In order to support the panel stream bit rate, the SN65DSI86 eDP
interface must be programmed so that the total
eDP data rate is greater than the stream bit rate.
>> +}
>> +
>> +static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge
>> *pdata)
>> +{
>> + struct drm_display_mode *mode = &pdata->curr_mode;
>> +
>> + regmap_write(pdata->regmap, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
>> + mode->hdisplay & 0xFF);
>> + regmap_write(pdata->regmap, SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG,
>> + (mode->hdisplay >> SN_TIMING_HIGH_OFFSET) & 0xFF);
>> + regmap_write(pdata->regmap, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
>> + mode->vdisplay & 0xFF);
>> + regmap_write(pdata->regmap, SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG,
>> + (mode->vdisplay >> SN_TIMING_HIGH_OFFSET) & 0xFF);
>> + regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
>> + (mode->hsync_end - mode->hsync_start) & 0xFF);
>> + regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
>> + ((mode->hsync_end - mode->hsync_start) >>
>> + SN_TIMING_HIGH_OFFSET) & 0xFF);
>> + regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
>> + (mode->vsync_end - mode->vsync_start) & 0xFF);
>> + regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
>> + ((mode->vsync_end - mode->vsync_start) >>
>> + SN_TIMING_HIGH_OFFSET) & 0xFF);
>> + regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
>> + (mode->htotal - mode->hsync_end) & 0xFF);
>> + regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
>> + (mode->vtotal - mode->vsync_end) & 0xFF);
>> + regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
>> + (mode->hsync_start - mode->hdisplay) & 0xFF);
>> + regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
>> + (mode->vsync_start - mode->vdisplay) & 0xFF);
>> + usleep_range(10000, 10050); /* 10ms delay recommended by spec */
>
> You would probably be fine to set the upper bound to 10500 so we don't
> trigger
> an unnecessary interrupt.
>
Done.
>> +}
>> +
>> +static void ti_sn_bridge_enable(struct drm_bridge *bridge)
>> +{
>> + struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
>> + struct drm_panel *panel = pdata->panel;
>> + unsigned int val = 0;
>> +
>> + if (panel) {
>> + drm_panel_prepare(panel);
>> + /* in case drm_panel is connected then HPD is not supported */
>> + regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG,
>> + SN_HPD_DISABLE_BIT, SN_HPD_DISABLE_BIT);
>> + }
>> +
>> + /* DSI_A lane config */
>> + val = (4 - pdata->dsi->lanes) << SN_DSIA_LANE_OFFSET;
>> + regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
>> + SN_DSIA_NUM_LANES_BITS, val);
>> +
>> + /* DP lane config */
>> + val = (pdata->dsi->lanes - 1) << SN_DP_LANE_OFFSET;
>> + regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG,
>> + SN_DP_NUM_LANES_BITS, val);
>> +
>> + /* set dsi/dp clk frequency value */
>> + ti_sn_bridge_set_dsi_dp_rate(pdata);
>> +
>> + /* enable DP PLL */
>> + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
>> + usleep_range(10000, 10050); /* 10ms delay recommended by spec */
>> +
>> + /**
>> + * The SN65DSI86 only supports ASSR Display Authentication method
>> and
>> + * this method is enabled by default. An eDP panel must support this
>> + * authentication method. We need to enable this method in the eDP
>> panel
>> + * at DisplayPort address 0x0010A prior to link training.
>> + */
>> + regmap_write(pdata->regmap, SN_AUX_WDATA0_REG, 0x01);
>> + regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, 0x00);
>> + regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG, 0x01);
>> + regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, 0x0A);
>> + regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, 0x01);
>> + regmap_write(pdata->regmap, SN_AUX_CMD_REG, 0x81);
>> + usleep_range(10000, 10050); /* 10ms delay recommended by spec */
>> +
>> + /* Semi auto link training mode */
>> + regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
>> + msleep(20); /* 20ms delay recommended by spec */
>> +
>> + /* config video parameters */
>> + ti_sn_bridge_set_video_timings(pdata);
>> +
>> + /* enable video stream */
>> + regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG,
>> + SN_ENABLE_VID_STREAM_BIT, SN_ENABLE_VID_STREAM_BIT);
>> +
>> + if (panel)
>> + drm_panel_enable(panel);
>> +}
>> +
>> +static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
>> +{
>> + struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
>> +
>> + ti_sn_bridge_power_ctrl(pdata, true);
>> +
>> + /* configure bridge CLK_SRC and ref_clk */
>> + ti_sn_bridge_set_refclk(pdata);
>> +}
>> +
>> +static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
>> +{
>> + struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
>> +
>> + ti_sn_bridge_power_ctrl(pdata, false);
>> +}
>> +
>> +static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
>> + .attach = ti_sn_bridge_attach,
>> + .pre_enable = ti_sn_bridge_pre_enable,
>> + .enable = ti_sn_bridge_enable,
>> + .disable = ti_sn_bridge_disable,
>> + .post_disable = ti_sn_bridge_post_disable,
>> + .mode_set = ti_sn_bridge_mode_set,
>> +};
>> +
>> +static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata)
>> +{
>> + struct device_node *np = pdata->dev->of_node;
>> + struct device_node *end_node;
>> +
>> + end_node = of_graph_get_endpoint_by_regs(np, 0, 0);
>> + if (!end_node) {
>> + DRM_ERROR("remote endpoint not found\n");
>> + return -ENODEV;
>> + }
>> +
>> + pdata->host_node = of_graph_get_remote_port_parent(end_node);
>> + of_node_put(end_node);
>> + if (!pdata->host_node) {
>> + DRM_ERROR("remote node not found\n");
>> + return -ENODEV;
>> + }
>> + of_node_put(pdata->host_node);
>> +
>> + return 0;
>> +}
>> +
>> +static int ti_sn_bridge_probe(struct i2c_client *client,
>> + const struct i2c_device_id *id)
>> +{
>> + struct ti_sn_bridge *pdata;
>> + struct device_node *ddc_node;
>> + int ret = 0;
>> +
>> + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
>> + DRM_ERROR("device doesn't support I2C\n");
>> + return -ENODEV;
>> + }
>> +
>> + pdata = devm_kzalloc(&client->dev,
>> + sizeof(struct ti_sn_bridge), GFP_KERNEL);
>
> pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge),
> GFP_KERNEL);
>
>> + if (!pdata)
>> + return -ENOMEM;
>> +
>> + pdata->dev = &client->dev;
>> + DRM_DEBUG("I2C address is %x\n", client->addr);
>
> unnecessary
>
Removed
>> +
>> + pdata->regmap = devm_regmap_init_i2c(client,
>> + &ti_sn_bridge_regmap_config);
>
> indentation is wrong here, should be:
>
> pdata->regmap = devm_regmap_init_i2c(client,
>
> &ti_sn_bridge_regmap_config);
>
>> + if (IS_ERR(pdata->regmap))
>
> Print an error?
>
>> + return PTR_ERR(pdata->regmap);
>> +
>> + pdata->enable_gpio = devm_gpiod_get(pdata->dev,
>> + "enable", GPIOD_OUT_LOW);
>> + if (IS_ERR(pdata->enable_gpio)) {
>> + DRM_ERROR("failed to get enable gpio from DT\n");
>> + ret = PTR_ERR(pdata->enable_gpio);
>> + return ret;
>> + }
>> +
>> + ret = ti_sn_bridge_parse_regulators(pdata);
>> + if (ret) {
>> + DRM_ERROR("failed to parse regulators\n");
>> + return ret;
>> + }
>> +
>> + ret = of_property_read_u32(pdata->dev->of_node,
>> + "refclk-freq-khz", &pdata->refclk_khz);
>> + if (ret)
>> + pdata->refclk_khz = SN_DEFAULT_REF_CLK_KHZ;
>> +
>> + ret = ti_sn_bridge_parse_dsi_host(pdata);
>> + if (ret)
>
> DRM_ERROR?
>
I am already printing error in ti_sn_bridge_parse_dsi_host() so removed
from here as per comment from Jordan Crouse.
>> + return ret;
>> +
>> + ddc_node = of_parse_phandle(pdata->dev->of_node, "ddc-i2c-bus", 0);
>> + if (ddc_node) {
>> + pdata->ddc = of_find_i2c_adapter_by_node(ddc_node);
>> + of_node_put(ddc_node);
>> + if (!pdata->ddc) {
>> + dev_dbg(pdata->dev, "failed to read ddc node\n");
>> + return -EPROBE_DEFER;
>> + }
>> + } else {
>> + dev_dbg(pdata->dev, "no ddc property found\n");
>
> You've copied dev_dbg() logs, they should be DRM_DEBUG_KMS().
>
Done.
>> + }
>> +
>> + ti_sn_bridge_power_ctrl(pdata, true);
>> + ret = ti_sn_bridge_read_device_rev(pdata);
>> + ti_sn_bridge_power_ctrl(pdata, false);
>
> This could be done before handling refclk or ddc.
>
Moved before refclk and ddc handing.
>> + if (ret)
>> + return ret;
>> +
>> + i2c_set_clientdata(client, pdata);
>> + mutex_init(&pdata->lock);
>> +
>> + pdata->bridge.funcs = &ti_sn_bridge_funcs;
>> + pdata->bridge.of_node = client->dev.of_node;
>> +
>> + drm_bridge_add(&pdata->bridge);
>> +
>> + DRM_DEBUG("bridge device registered successfully\n");
>
> unnecessary
>
Removed
>> +
>> + return 0;
>> +}
>> +
>> +static int ti_sn_bridge_remove(struct i2c_client *client)
>> +{
>> + struct ti_sn_bridge *pdata = i2c_get_clientdata(client);
>> +
>> + if (!pdata)
>> + return -EINVAL;
>> +
>> + mipi_dsi_detach(pdata->dsi);
>> + mipi_dsi_device_unregister(pdata->dsi);
>> +
>> + drm_bridge_remove(&pdata->bridge);
>> + i2c_put_adapter(pdata->ddc);
>> +
>> + return 0;
>> +}
>> +
>> +static struct i2c_device_id ti_sn_bridge_id[] = {
>> + { "ti,sn65dsi86", 0},
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id);
>> +
>> +static const struct of_device_id ti_sn_bridge_match_table[] = {
>> + {.compatible = "ti,sn65dsi86"},
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table);
>> +
>> +static struct i2c_driver ti_sn_bridge_driver = {
>> + .driver = {
>> + .name = "ti_sn65dsi86",
>> + .of_match_table = ti_sn_bridge_match_table,
>> + },
>> + .probe = ti_sn_bridge_probe,
>> + .remove = ti_sn_bridge_remove,
>> + .id_table = ti_sn_bridge_id,
>> +};
>> +
>> +module_i2c_driver(ti_sn_bridge_driver);
>> +MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
>> +MODULE_LICENSE("GPL v2");
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>> Forum,
>> a Linux Foundation Collaborative Project
>>
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply
* Re: [PATCH 1/2] ARM64: dts: meson-gxbb: odroidc2: enable sdcard UHS modes
From: Anand Moon @ 2018-05-15 5:34 UTC (permalink / raw)
To: Jerome Brunet
Cc: Neil Armstrong, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Carlo Caione, Kevin Hilman, devicetree,
linux-arm-kernel, linux-amlogic, Linux Kernel
In-Reply-To: <1526305693.2897.16.camel@baylibre.com>
Hi Jerome
On 14 May 2018 at 19:18, Jerome Brunet <jbrunet@baylibre.com> wrote:
> On Wed, 2018-05-02 at 00:29 +0530, Anand Moon wrote:
>> Enable UHS modes for sdcard, on odroidc2.
>>
>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
>> index 54954b314a45..c90f8b46c60c 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
>> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
>> @@ -258,6 +258,11 @@
>> cap-sd-highspeed;
>> max-frequency = <100000000>;
>> disable-wp;
>> + sd-uhs-sdr12;
>> + sd-uhs-sdr25;
>> + sd-uhs-sdr50;
>> + sd-uhs-sdr104;
>> + sd-uhs-ddr50;
>>
>> cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
>> cd-inverted;
>
> Hi Anand,
>
> I tried a few sdcards on the OC2 with your 2 patches.
> Like with the libretech-cc, sdr104@200Mhz works "mostly", but, with some
> sdcards, it does not - please see below. The same sdcards appear to be working
> fine on my laptop.
>
> This is something I have not been able to crack yet on the libretech-cc.
>
> I'd suggest dropping sdr104 and keeping the max frequency at 100Mhz until we can
> figure out the problem here.
>
> With this changed:
>
> Tested-by: Jerome Brunet <jbrunet@baylibre.com>
>
> dd if=/dev/mmcblk1 of=/dev/zero bs=4M
> [ 446.925817] mmc1: tuning execution failed: -5
> [ 446.956597] mmc1: tuning execution failed: -5
> [ 489.957810] print_req_error: I/O error, dev mmcblk1, sector 6654424
> [ 490.141975] print_req_error: I/O error, dev mmcblk1, sector 6656440
> [ 490.148304] print_req_error: I/O error, dev mmcblk1, sector 6656944
> [ 490.349650] print_req_error: I/O error, dev mmcblk1, sector 6658456
> [ 491.804382] print_req_error: I/O error, dev mmcblk1, sector 6747688
> [ 492.281246] print_req_error: I/O error, dev mmcblk1, sector 6784992
> [ 492.419034] print_req_error: I/O error, dev mmcblk1, sector 6785496
> [ 492.865878] print_req_error: I/O error, dev mmcblk1, sector 6791800
> [ 493.023809] print_req_error: I/O error, dev mmcblk1, sector 6792192
> [ 493.024435] Buffer I/O error on dev mmcblk1, logical block 849024, async page
> read
> [ 493.217751] print_req_error: I/O error, dev mmcblk1, sector 6792808
> [ 494.891779] mmc1: tuning execution failed: -5
> [ 495.374186] print_req_error: 3 callbacks suppressed
> [ 495.374193] print_req_error: I/O error, dev mmcblk1, sector 6854576
> [ 495.767498] print_req_error: I/O error, dev mmcblk1, sector 6860000
> [ 496.013104] print_req_error: I/O error, dev mmcblk1, sector 6863024
> [ 496.223042] print_req_error: I/O error, dev mmcblk1, sector 6864032
> [ 496.227003] print_req_error: I/O error, dev mmcblk1, sector 6864536
> [ 496.375175] print_req_error: I/O error, dev mmcblk1, sector 6864176
> [ 496.375806] Buffer I/O error on dev mmcblk1, logical block 858022, async page
> read
> [ 496.521229] print_req_error: I/O error, dev mmcblk1, sector 6864184
> [ 496.521852] Buffer I/O error on dev mmcblk1, logical block 858023, async page
> read
> [ 503.596978] print_req_error: I/O error, dev mmcblk1, sector 6983312
> [ 503.597606] Buffer I/O error on dev mmcblk1, logical block 872914, async page
> read
> [ 505.280621] print_req_error: I/O error, dev mmcblk1, sector 7004536
> [ 505.281249] Buffer I/O error on dev mmcblk1, logical block 875567, async page
> read
> [ 507.372560] print_req_error: I/O error, dev mmcblk1, sector 7048696
> [ 507.373192] Buffer I/O error on dev mmcblk1, logical block 881087, async page
> read
> [ 511.355248] print_req_error: I/O error, dev mmcblk1, sector 7131352
> [ 511.355883] Buffer I/O error on dev mmcblk1, logical block 891419, async page
> read
> [ 511.369076] print_req_error: I/O error, dev mmcblk1, sector 7131352
> [ 511.369694] Buffer I/O error on dev mmcblk1, logical block 891419, async page
> read
> dd: error reading '/dev/mmcblk1': Input/output error
> 868+7 records in
> 868+7 records out
> 3651252224 bytes (3.7 GB, 3.4 GiB) copied, 66.7736 s, 54.7 MB/s
Thank for your testing, I will also do some more testing on all the
sdcard and share you the result..
Mean while Sandisk Ultra microSDHC UHS-I card @A1 32GB shows.
On my Odroid C2:
[ 1.165784] meson-gx-mmc d0074000.mmc: allocated mmc-pwrseq
[ 1.403756] meson-gx-mmc d0072000.mmc: Got CD GPIO
[ 1.456160] Waiting for root device /dev/mmcblk1p2...
[ 1.608180] mmc1: new ultra high speed SDR104 SDHC card at address aaaa
[ 1.610002] mmcblk1: mmc1:aaaa JULIE 29.7 GiB
[ 1.617811] mmcblk1: p1 p2
Also I did not encounter and read/write failure on the sdcard but I
will re-test them.
root@odroid64:~# dd if=/dev/mmcblk1 of=/dev/zero bs=4M
7609+1 records in
7609+1 records out
31914983424 bytes (32 GB, 30 GiB) copied, 368.637 s, 86.6 MB/s
root@odroid64:~#
Best Regards
-Anand
^ permalink raw reply
* Re: [PATCH V3] ARM: dts: da850-evm: Enable LCD and Backlight
From: Laurent Pinchart @ 2018-05-15 5:25 UTC (permalink / raw)
To: Adam Ford
Cc: devicetree, Kevin Hilman, Sekhar Nori, Rob Herring,
Tomi Valkeinen, jsarha, arm-soc
In-Reply-To: <CAHCN7xKgop-SMZpQm4jca3NB0rrc_CCcMG8JL6mayLx4u+zW9w@mail.gmail.com>
Hi Adam,
On Monday, 14 May 2018 21:04:07 EEST Adam Ford wrote:
> On Mon, May 14, 2018 at 7:35 AM, Sekhar Nori <nsekhar@ti.com> wrote:
> > On Monday 14 May 2018 04:22 PM, Adam Ford wrote:
> >> On Mon, May 14, 2018 at 12:29 AM, Sekhar Nori <nsekhar@ti.com> wrote:
> >>> Hi Adam,
>
> Added Tomi, Laurent, and Jyri for feedback.
>
> >>> On Monday 14 May 2018 04:50 AM, Adam Ford wrote:
> >>>> When using the board files the LCD works, but not with the DT.
> >>>> This adds enables the original da850-evm to work with the same
> >>>> LCD in device tree mode.
> >>>>
> >>>> The EVM has a gpio for the regulator and a gpio enable. The LCD and
> >>>> the vpif display pins are mutually exclusive, so if using the LCD,
> >>>> do not load the vpif driver.
> >>>
> >>> Its not sufficient just note this in patch description.
> >>>
> >>> a) Disable (status = "disabled") the VPIF node which clashes for pins
> >>> with LCD.
> >>> b) Add a comment on top of the status = "disabled" giving information on
> >>> how user can enable it (disable lcdc node and then change to status =
> >>> "okay").
> >>>
> >>>> Signed-off-by: Adam Ford <aford173@gmail.com>
> >>>> ---
> >>>> V3: Fix errant GPIO, label GPIO pins, and rename the regulator to be
> >>>> more explict to backlight which better matches the schematic.
> >>>> Updated the description to explain that it cannot be used at the
> >>>> same time as the vpif driver.
> >>>>
> >>>> V2: Add regulator and GPIO enable pins. Remove PWM backlight and
> >>>> replace with GPIO
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/da850-evm.dts
> >>>> b/arch/arm/boot/dts/da850-evm.dts index 2e817da37fdb..3f1c8be07efe
> >>>> 100644
> >>>> --- a/arch/arm/boot/dts/da850-evm.dts
> >>>> +++ b/arch/arm/boot/dts/da850-evm.dts
> >>>> @@ -27,6 +27,50 @@
> >>>> spi0 = &spi1;
> >>>> };
> >>>>
> >>>> + backlight {
> >>>> + compatible = "gpio-backlight";
> >>>> + enable-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; /* GP0[7] */
> >>>
> >>> The gpio-backlight binding does not describe a property called
> >>> enable-gpios. It should just be gpios.
> >>
> >> I will fix that.
> >>
> >>> a) Are you using gpio-backlight because you are not able to get the PWM
> >>> to work?
> >>
> >> Yes, You told me not to worry about doing a PWM backlight because the
> >> legacy board does not PWM either.
> >
> > Yeah, I meant not to add backlight control till the time we are able to
> > get it working using PWM. Is this needed for the basic LCD functionality
> > to work? I would like to avoid the churn of adding it using GPIO now and
> > changing to PWM later, if possible.
> >
> >>> b) What is GP0[7] connected to in the schematic you have? In the
> >>> schematic I have I see LCD_PWM0 is connected to
> >>> SPI1_SCS[0]/EPWM1B/GP2[14]/TM64P3_IN12.
> >>
> >> I have schematic 1016572 dated Wednesday, August 18, 2010. According
> >> to it, AXR15 / EPWMN0_TZ[0] / ECAP2_APWM2 / GPIO0[7] connects to U25,
> >> Pin 46 to generate M_LCD_PWM0. You might have one of the early,
> >> pre-release versions.
> >
> > Ah, okay. In your schematic, is GP2[14] connected to anything?
> >
> >>> c) The /* GP0[7] */ comment is not really useful on its own as it can be
> >>> computed. What I wanted to see is the schematic symbol like "LCD_PWM0".
> >>> Same for other places like this below.
> >>
> >> I can do that.
> >>
> >>>> @@ -35,6 +79,16 @@
> >>>> regulator-boot-on;
> >>>> };
> >>>>
> >>>> + backlight_reg: backlight-regulator {
> >>>> + compatible = "regulator-fixed";
> >>>> + regulator-name = "lcd_backlight_pwr";
> >>>> + regulator-min-microvolt = <3300000>;
> >>>> + regulator-max-microvolt = <3300000>;
> >>>> + gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* GP2[15] */
> >>>> + regulator-always-on;
> >>>
> >>> Why should this regulator never be disabled?
> >>
> >> The gpio-backlight does not have a way that I can see to associate the
> >> regulator to it. I read through the bindings, but I didn't see an
> >> option to associate a regulator it. I use this regulator to drive
> >> lcd_backlight_pwr and the backlight driver to write lcd_pwm0. Without
> >> this option, the system disables lcd_backlight_pwr and the screen is
> >> blank
> >
> > It sounds like this is a hack to enable backlight on this board. I think
> > either the backlight driver needs to gain functionality to enable the
> > GPIO. Or backlight could be treated as part of the panel and enabled
> > using enable-gpios property in the panel. TBH, I will be okay either
> > way. Can you check with Jyri, Tomi and rest of the DRM folks on what
> > should be right way of dealing with this?
>
> Per your request I added them into this thread. I added Tomi, Jyri,
> and Laurent to this as Laurent's name is associated with the gpio
> backlight driver.
>
> I am not sure why you think it's a hack. I pulled up the schematic
> for the LCD to see what it's doing, and the lcd_backlight_pwr pin
> controls the power-on sequence of the back-light controller. Without
> this, there is no power, so it seems to me that the 'regulator-fixed'
> device is the correct way to do it.
It's a hack because keeping the backlight power on when the display is off
will consume power unnecessarily. The backlight power should be turned off in
that case.
> The separate pin associated to the gpio is used to tell the backlight
> IC to actually turn on/off the back-light. Ideally it seems like it
> would nice to have the gpio-backlight driver be able to specify the
> regulator, so when the backlight is in use, it would power the
> regulator, but until that's available, the it seems like
> 'regulator-always-on' is the way to make it stay on.
>
> Laurent, Jyri, Tomi, do you have any thoughts on this matter?
This has been attempted 6 years ago, and got rejected. See https://lwn.net/
Articles/525422/.
The problem is that the number of power supplies, the order in which they need
to be sequenced, and the related timings (as in delays required between
turning power supplies on/off) is highly hardware-specific. We can't hardcode
a specific sequence and specific timings in the gpio-backlight (or pwm-
backlight) driver, and specifying the sequence in DT was considered to be
over-engineered.
You thus have two options, either creating a custom backlight driver that will
handle the power supplies specific to your backlight controller, or
integrating backlight power supply control in your panel driver. If the power
supplies also power the panel and not just the backlight, or if their
sequencing depends in any way on the panel model in which the backlight
controller is integrated, I'd go for the latter, otherwise you can pick any of
the two methods.
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH V3] ARM: dts: da850-evm: Enable LCD and Backlight
From: Sekhar Nori @ 2018-05-15 5:19 UTC (permalink / raw)
To: Adam Ford
Cc: devicetree, Kevin Hilman, jsarha, Rob Herring, Tomi Valkeinen,
Laurent Pinchart, arm-soc
In-Reply-To: <CAHCN7xKgop-SMZpQm4jca3NB0rrc_CCcMG8JL6mayLx4u+zW9w@mail.gmail.com>
On Monday 14 May 2018 11:34 PM, Adam Ford wrote:
> On Mon, May 14, 2018 at 7:35 AM, Sekhar Nori <nsekhar@ti.com> wrote:
>> On Monday 14 May 2018 04:22 PM, Adam Ford wrote:
>>> On Mon, May 14, 2018 at 12:29 AM, Sekhar Nori <nsekhar@ti.com> wrote:
>>>> Hi Adam,
>
> Added Tomi, Laurent, and Jyri for feedback.
>
>>>>
>>>> On Monday 14 May 2018 04:50 AM, Adam Ford wrote:
>>>>> When using the board files the LCD works, but not with the DT.
>>>>> This adds enables the original da850-evm to work with the same
>>>>> LCD in device tree mode.
>>>>>
>>>>> The EVM has a gpio for the regulator and a gpio enable. The LCD and
>>>>> the vpif display pins are mutually exclusive, so if using the LCD,
>>>>> do not load the vpif driver.
>>>>
>>>> Its not sufficient just note this in patch description.
>>>>
>>>> a) Disable (status = "disabled") the VPIF node which clashes for pins
>>>> with LCD.
>>>> b) Add a comment on top of the status = "disabled" giving information on
>>>> how user can enable it (disable lcdc node and then change to status =
>>>> "okay").
>>>>
>>>>>
>>>>> Signed-off-by: Adam Ford <aford173@gmail.com>
>>>>> ---
>>>>> V3: Fix errant GPIO, label GPIO pins, and rename the regulator to be more explict to
>>>>> backlight which better matches the schematic. Updated the description to explain
>>>>> that it cannot be used at the same time as the vpif driver.
>>>>>
>>>>> V2: Add regulator and GPIO enable pins. Remove PWM backlight and replace with GPIO
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
>>>>> index 2e817da37fdb..3f1c8be07efe 100644
>>>>> --- a/arch/arm/boot/dts/da850-evm.dts
>>>>> +++ b/arch/arm/boot/dts/da850-evm.dts
>>>>> @@ -27,6 +27,50 @@
>>>>> spi0 = &spi1;
>>>>> };
>>>>>
>>>>> + backlight {
>>>>> + compatible = "gpio-backlight";
>>>>> + enable-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; /* GP0[7] */
>>>>
>>>> The gpio-backlight binding does not describe a property called
>>>> enable-gpios. It should just be gpios.
>>>
>>> I will fix that.
>>>
>>>>
>>>> a) Are you using gpio-backlight because you are not able to get the PWM
>>>> to work?
>>>>
>>> Yes, You told me not to worry about doing a PWM backlight because the
>>> legacy board does not PWM either.
>>
>> Yeah, I meant not to add backlight control till the time we are able to
>> get it working using PWM. Is this needed for the basic LCD functionality
>> to work? I would like to avoid the churn of adding it using GPIO now and
>> changing to PWM later, if possible.
>>
>>>
>>>> b) What is GP0[7] connected to in the schematic you have? In the
>>>> schematic I have I see LCD_PWM0 is connected to
>>>> SPI1_SCS[0]/EPWM1B/GP2[14]/TM64P3_IN12.
>>>
>>> I have schematic 1016572 dated Wednesday, August 18, 2010. According
>>> to it, AXR15 / EPWMN0_TZ[0] / ECAP2_APWM2 / GPIO0[7] connects to U25,
>>> Pin 46 to generate M_LCD_PWM0. You might have one of the early,
>>> pre-release versions.
>>
>> Ah, okay. In your schematic, is GP2[14] connected to anything?
>>
>>>
>>>>
>>>> c) The /* GP0[7] */ comment is not really useful on its own as it can be
>>>> computed. What I wanted to see is the schematic symbol like "LCD_PWM0".
>>>> Same for other places like this below.
>>>
>>> I can do that.
>>>>
>>>>> @@ -35,6 +79,16 @@
>>>>> regulator-boot-on;
>>>>> };
>>>>>
>>>>> + backlight_reg: backlight-regulator {
>>>>> + compatible = "regulator-fixed";
>>>>> + regulator-name = "lcd_backlight_pwr";
>>>>> + regulator-min-microvolt = <3300000>;
>>>>> + regulator-max-microvolt = <3300000>;
>>>>> + gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* GP2[15] */
>>>>> + regulator-always-on;
>>>>
>>>> Why should this regulator never be disabled?
>>>
>>> The gpio-backlight does not have a way that I can see to associate the
>>> regulator to it. I read through the bindings, but I didn't see an
>>> option to associate a regulator it. I use this regulator to drive
>>> lcd_backlight_pwr and the backlight driver to write lcd_pwm0. Without
>>> this option, the system disables lcd_backlight_pwr and the screen is
>>> blank
>>
>> It sounds like this is a hack to enable backlight on this board. I think
>> either the backlight driver needs to gain functionality to enable the
>> GPIO. Or backlight could be treated as part of the panel and enabled
>> using enable-gpios property in the panel. TBH, I will be okay either
>> way. Can you check with Jyri, Tomi and rest of the DRM folks on what
>> should be right way of dealing with this?
>
> Per your request I added them into this thread. I added Tomi, Jyri,
> and Laurent to this as Laurent's name is associated with the gpio
> backlight driver.
Okay. The reason I did not loop them in myself is because I thought a
fresh thread with background will be better. But okay.
> I am not sure why you think it's a hack. I pulled up the schematic
> for the LCD to see what it's doing, and the lcd_backlight_pwr pin
> controls the power-on sequence of the back-light controller. Without
> this, there is no power, so it seems to me that the 'regulator-fixed'
> device is the correct way to do it.
Not questioning modeling the GPIO as a regulator.
>
> The separate pin associated to the gpio is used to tell the backlight
> IC to actually turn on/off the back-light. Ideally it seems like it
> would nice to have the gpio-backlight driver be able to specify the
> regulator, so when the backlight is in use, it would power the
> regulator, but until that's available, the it seems like
> 'regulator-always-on' is the way to make it stay on.
We need to add support for this in backlight driver. Using
regulator-always-on to paper over this lack of support in backlight
driver is what I am calling a hack. 'regulator-always-on' means the
regulator cannot be turned off. Thats certainly not the case as you have
pointed out.
Thanks,
Sekhar
^ permalink raw reply
* Re: [PATCH V1 2/5] backlight: qcom-wled: Add support for WLED4 peripheral
From: kgunda @ 2018-05-15 4:55 UTC (permalink / raw)
To: Pavel Machek
Cc: bjorn.andersson, Lee Jones, Daniel Thompson, Jingoo Han,
Jacek Anaszewski, Rob Herring, Mark Rutland,
Bartlomiej Zolnierkiewicz, linux-leds, devicetree, linux-kernel,
dri-devel, linux-fbdev, linux-arm-msm, linux-arm-msm-owner
In-Reply-To: <20180514165755.GB27984@xo-6d-61-c0.localdomain>
On 2018-05-14 22:27, Pavel Machek wrote:
> Hi!
>
>> WLED4 peripheral is present on some PMICs like pmi8998
>> and pm660l. It has a different register map and also
>> configurations are different. Add support for it.
>>
>> Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
>> ---
>> .../bindings/leds/backlight/qcom-wled.txt | 172 ++++-
>> drivers/video/backlight/qcom-wled.c | 749
>> +++++++++++++++------
>> 2 files changed, 696 insertions(+), 225 deletions(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/leds/backlight/qcom-wled.txt
>> b/Documentation/devicetree/bindings/leds/backlight/qcom-wled.txt
>> index fb39e32..0ceffa1 100644
>> --- a/Documentation/devicetree/bindings/leds/backlight/qcom-wled.txt
>> +++ b/Documentation/devicetree/bindings/leds/backlight/qcom-wled.txt
>> @@ -1,30 +1,129 @@
>> Binding for Qualcomm Technologies, Inc. WLED driver
>>
>> -Required properties:
>> -- compatible: should be "qcom,pm8941-wled"
>> -- reg: slave address
>> -
>> -Optional properties:
>> -- default-brightness: brightness value on boot, value from: 0-4095
>> - default: 2048
>> +- compatible
>> + Usage: required
>> + Value type: <string>
>> + Definition: should be "qcom,pm8941-wled" or "qcom,pmi8998-wled".
>> + or "qcom,pm660l-wled".
>> +
>> +- reg
>> + Usage: required
>> + Value type: <prop encoded array>
>> + Definition: Base address of the WLED modules.
>
> I'm not sure if this change of format is good idea here...
>
> Pavel
> --
This format is clean and easily readable. That's why I have moved to
this format.
To avoid confusion, I will move out the existing properties
(pm8941-wled.c) to other
patch. So that it will be easy to review.
> To unsubscribe from this list: send the line "unsubscribe
> linux-arm-msm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH v2] arm64: dts: qcom: sdm845: Sort nodes in the reserved mem by address
From: Douglas Anderson @ 2018-05-15 4:43 UTC (permalink / raw)
To: andy.gross
Cc: Bjorn Andersson, Douglas Anderson, devicetree, linux-arm-msm,
linux-kernel, Rob Herring, David Brown, Will Deacon, Mark Rutland,
linux-soc, Catalin Marinas, linux-arm-kernel
Let's keep the reserved-memory node tidy and neat and keep it sorted
by address. This should have no functional change.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
Changes in v2:
- Oops! v1 accidentally changed the node name. Fixed.
arch/arm64/boot/dts/qcom/sdm845.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 7c85e7c596db..73f71061fef8 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -31,6 +31,12 @@
no-map;
};
+ memory@85fe0000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x85fe0000 0x0 0x20000>;
+ no-map;
+ };
+
smem_mem: memory@86000000 {
reg = <0x0 0x86000000 0x0 0x200000>;
no-map;
@@ -40,12 +46,6 @@
reg = <0 0x86200000 0 0x2d00000>;
no-map;
};
-
- memory@85fe0000 {
- compatible = "qcom,cmd-db";
- reg = <0x0 0x85fe0000 0x0 0x20000>;
- no-map;
- };
};
cpus {
--
2.17.0.441.gb46fe60e1d-goog
^ permalink raw reply related
* [PATCH] arm64: dts: qcom: sdm845: Sort nodes in the reserved mem by address
From: Douglas Anderson @ 2018-05-15 4:37 UTC (permalink / raw)
To: andy.gross
Cc: Bjorn Andersson, Douglas Anderson, devicetree, linux-arm-msm,
linux-kernel, Rob Herring, David Brown, Will Deacon, Mark Rutland,
linux-soc, Catalin Marinas, linux-arm-kernel
Let's keep the reserved-memory node tidy and neat and keep it sorted
by address. This should have no functional change.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 7c85e7c596db..63026133feab 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -31,6 +31,12 @@
no-map;
};
+ reserved-memory@85fe0000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x85fe0000 0x0 0x20000>;
+ no-map;
+ };
+
smem_mem: memory@86000000 {
reg = <0x0 0x86000000 0x0 0x200000>;
no-map;
@@ -40,12 +46,6 @@
reg = <0 0x86200000 0 0x2d00000>;
no-map;
};
-
- memory@85fe0000 {
- compatible = "qcom,cmd-db";
- reg = <0x0 0x85fe0000 0x0 0x20000>;
- no-map;
- };
};
cpus {
--
2.17.0.441.gb46fe60e1d-goog
^ permalink raw reply related
* Re: [PATCH v6 14/14] dt: qcom: Add qcom-cpufreq-kryo driver configuration
From: Viresh Kumar @ 2018-05-15 4:11 UTC (permalink / raw)
To: Ilia Lin
Cc: mturquette, sboyd, robh, mark.rutland, nm, lgirdwood, broonie,
andy.gross, david.brown, catalin.marinas, will.deacon, rjw,
linux-clk, devicetree, linux-kernel, linux-pm, linux-arm-msm,
linux-soc, linux-arm-kernel, rnayak, amit.kucheria,
nicolas.dechesne, celster, tfinkel
In-Reply-To: <1526303520-5843-15-git-send-email-ilialin@codeaurora.org>
On 14-05-18, 16:12, Ilia Lin wrote:
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +-
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 310 +++++++++++++++++++++++++++-
> 2 files changed, 309 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
> index 230e9c8..da23bda 100644
> --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
> +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
> @@ -17,5 +17,5 @@
>
> / {
> model = "Qualcomm Technologies, Inc. DB820c";
> - compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
> + compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
> };
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index d7adef9..fbf92f6 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -174,218 +174,519 @@
> };
>
> cluster0_opp: opp_table0 {
> - compatible = "operating-points-v2";
> + compatible = "operating-points-v2-kryo-cpu";
I think you need to mention both the above compatible strings here
with the kyro one mentioned first.
--
viresh
^ permalink raw reply
* Re: [PATCH v6 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu
From: Viresh Kumar @ 2018-05-15 4:09 UTC (permalink / raw)
To: Ilia Lin
Cc: mturquette, sboyd, robh, mark.rutland, nm, lgirdwood, broonie,
andy.gross, david.brown, catalin.marinas, will.deacon, rjw,
linux-clk, devicetree, linux-kernel, linux-pm, linux-arm-msm,
linux-soc, linux-arm-kernel, rnayak, amit.kucheria,
nicolas.dechesne, celster, tfinkel
In-Reply-To: <1526303520-5843-14-git-send-email-ilialin@codeaurora.org>
On 14-05-18, 16:11, Ilia Lin wrote:
> In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
> that have KRYO processors, the CPU ferequencies subset and voltage value
> of each OPP varies based on the silicon variant in use.
> Qualcomm Technologies, Inc. Process Voltage Scaling Tables
> defines the voltage and frequency value based on the msm-id in SMEM
> and speedbin blown in the efuse combination.
> The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
> to provide the OPP framework with required information.
> This is used to determine the voltage and frequency value for each OPP of
> operating-points-v2 table when it is parsed by the OPP framework.
>
> This change adds documentation.
>
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> .../devicetree/bindings/opp/kryo-cpufreq.txt | 680 +++++++++++++++++++++
> 1 file changed, 680 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply
* Re: [PATCH v6 12/14] cpufreq: Add Kryo CPU scaling driver
From: Viresh Kumar @ 2018-05-15 4:09 UTC (permalink / raw)
To: Ilia Lin
Cc: mturquette, sboyd, robh, mark.rutland, nm, lgirdwood, broonie,
andy.gross, david.brown, catalin.marinas, will.deacon, rjw,
linux-clk, devicetree, linux-kernel, linux-pm, linux-arm-msm,
linux-soc, linux-arm-kernel, rnayak, amit.kucheria,
nicolas.dechesne, celster, tfinkel
In-Reply-To: <1526303520-5843-13-git-send-email-ilialin@codeaurora.org>
On 14-05-18, 16:11, Ilia Lin wrote:
> +static int __init qcom_cpufreq_kryo_driver_init(void)
> +{
> + size_t len;
> + int ret;
> + u32 versions;
> + enum _msm8996_version msm8996_version;
> + u8 *speedbin;
> + struct device *cpu_dev;
> + struct device_node *np;
> + struct nvmem_cell *speedbin_nvmem;
> + struct opp_table *opp_temp = NULL;
> +
> + cpu_dev = get_cpu_device(SILVER_LEAD);
> + if (IS_ERR_OR_NULL(cpu_dev))
> + return PTR_ERR(cpu_dev);
> +
> + msm8996_version = qcom_cpufreq_kryo_get_msm_id();
> + if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
> + dev_err(cpu_dev, "Not Snapdragon 820/821!");
> + return -ENODEV;
> + }
> +
> + np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
> + if (IS_ERR_OR_NULL(np))
> + return PTR_ERR(np);
> +
> + if (!of_device_is_compatible(np, "operating-points-v2-kryo-cpu")) {
> + ret = -ENOENT;
> + goto free_np;
> + }
> +
> + speedbin_nvmem = of_nvmem_cell_get(np, NULL);
> + if (IS_ERR(speedbin_nvmem)) {
> + ret = PTR_ERR(speedbin_nvmem);
> + dev_err(cpu_dev, "Could not get nvmem cell: %d\n", ret);
> + goto free_np;
> + }
> +
> + speedbin = nvmem_cell_read(speedbin_nvmem, &len);
> +
> + switch (msm8996_version) {
> + case MSM8996_V3:
> + versions = 1 << (unsigned int)(*speedbin);
> + break;
> + case MSM8996_SG:
> + versions = 1 << ((unsigned int)(*speedbin) + 4);
> + break;
> + default:
> + BUG();
> + break;
> + }
> +
> + ret = PTR_ERR_OR_ZERO(opp_temp = \
Why back slash here ?
> + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1));
> + if (0 > ret)
> + goto free_np;
> +
> + dev_pm_opp_put_supported_hw(opp_temp);
> +
> + cpu_dev = get_cpu_device(GOLD_LEAD);
> + ret = PTR_ERR_OR_ZERO(opp_temp = \
And here.
> + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1));
> + if (0 > ret)
> + goto free_np;
> +
> + ret = PTR_ERR_OR_ZERO(platform_device_register_simple("cpufreq-dt", \
and here.
> + -1, NULL, 0));
> +
> + dev_pm_opp_put_supported_hw(opp_temp);
And this is wrong. You don't need to call this in success case here.
It may have worked for you as cpufreq-dt driver would have already
been initialized, but that's not the case always. For example try
inserting cpufreq-dt module after kernel boots and it will fail.
> +
> +free_np:
> + of_node_put(np);
> +
> + return ret;
> +}
> +late_initcall(qcom_cpufreq_kryo_driver_init);
> +
> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver");
> +MODULE_LICENSE("GPL v2");
> --
> 1.9.1
--
viresh
^ permalink raw reply
* Re: [PATCH v6 11/14] dt: qcom: Add SAW regulator for 8x96 CPUs
From: Viresh Kumar @ 2018-05-15 4:04 UTC (permalink / raw)
To: Ilia Lin
Cc: mturquette, sboyd, robh, mark.rutland, nm, lgirdwood, broonie,
andy.gross, david.brown, catalin.marinas, will.deacon, rjw,
linux-clk, devicetree, linux-kernel, linux-pm, linux-arm-msm,
linux-soc, linux-arm-kernel, rnayak, amit.kucheria,
nicolas.dechesne, celster, tfinkel
In-Reply-To: <1526303520-5843-12-git-send-email-ilialin@codeaurora.org>
On 14-05-18, 16:11, Ilia Lin wrote:
> 1. Add syscon node for the SAW CPU registers
> 2. Add SAW regulators gang definition for s8-s11
> 3. Add voltages to the OPP tables
> 4. Add the s11 SAW regulator as CPU regulator
>
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 75 +++++++++++++++++++++++++++++++++++
> 1 file changed, 75 insertions(+)
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply
* Re: [PATCH v6 08/14] dt: qcom: Add opp and thermal to the msm8996
From: Viresh Kumar @ 2018-05-15 4:04 UTC (permalink / raw)
To: Ilia Lin
Cc: mturquette, sboyd, robh, mark.rutland, nm, lgirdwood, broonie,
andy.gross, david.brown, catalin.marinas, will.deacon, rjw,
linux-clk, devicetree, linux-kernel, linux-pm, linux-arm-msm,
linux-soc, linux-arm-kernel, rnayak, amit.kucheria,
nicolas.dechesne, celster, tfinkel
In-Reply-To: <1526303520-5843-9-git-send-email-ilialin@codeaurora.org>
On 14-05-18, 16:11, Ilia Lin wrote:
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 269 ++++++++++++++++++++++++++++++++--
> 1 file changed, 260 insertions(+), 9 deletions(-)
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply
* [PATCH v2] arm64: dts: qcom: sdm845: Sort nodes in the soc by address
From: Douglas Anderson @ 2018-05-15 3:59 UTC (permalink / raw)
To: Andy Gross
Cc: Bjorn Andersson, swboyd, Douglas Anderson, devicetree,
linux-arm-msm, linux-kernel, Rob Herring, David Brown,
Will Deacon, Mark Rutland, linux-soc, Catalin Marinas,
linux-arm-kernel
This is pure-churn and should be a no-op. I'm doing it in the hopes
of reducing merge conflicts. When things are sorted in a sane way
(and by base address seems sane) then it's less likely that future
patches will cause merge conflicts.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes in v2:
- rebase atop tree today
arch/arm64/boot/dts/qcom/sdm845.dtsi | 96 ++++++++++++++--------------
1 file changed, 48 insertions(+), 48 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 7c85e7c596db..96dd4b2a41d6 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -198,6 +198,54 @@
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sdm845";
+ reg = <0x100000 0x1f0000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ tcsr_mutex_regs: syscon@1f40000 {
+ compatible = "syscon";
+ reg = <0x1f40000 0x40000>;
+ };
+
+ tlmm: pinctrl@3400000 {
+ compatible = "qcom,sdm845-pinctrl";
+ reg = <0x03400000 0xc00000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ spmi_bus: spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0xc440000 0x1100>,
+ <0xc600000 0x2000000>,
+ <0xe600000 0x100000>,
+ <0xe700000 0xa0000>,
+ <0xc40a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
+ apss_shared: mailbox@17990000 {
+ compatible = "qcom,sdm845-apss-shared";
+ reg = <0x17990000 0x1000>;
+ #mbox-cells = <1>;
+ };
+
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#address-cells = <1>;
@@ -218,24 +266,6 @@
};
};
- gcc: clock-controller@100000 {
- compatible = "qcom,gcc-sdm845";
- reg = <0x100000 0x1f0000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-
- tlmm: pinctrl@3400000 {
- compatible = "qcom,sdm845-pinctrl";
- reg = <0x03400000 0xc00000>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
timer@17c90000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -293,35 +323,5 @@
status = "disabled";
};
};
-
- spmi_bus: spmi@c440000 {
- compatible = "qcom,spmi-pmic-arb";
- reg = <0xc440000 0x1100>,
- <0xc600000 0x2000000>,
- <0xe600000 0x100000>,
- <0xe700000 0xa0000>,
- <0xc40a000 0x26000>;
- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
- interrupt-names = "periph_irq";
- interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
- qcom,ee = <0>;
- qcom,channel = <0>;
- #address-cells = <2>;
- #size-cells = <0>;
- interrupt-controller;
- #interrupt-cells = <4>;
- cell-index = <0>;
- };
-
- tcsr_mutex_regs: syscon@1f40000 {
- compatible = "syscon";
- reg = <0x1f40000 0x40000>;
- };
-
- apss_shared: mailbox@17990000 {
- compatible = "qcom,sdm845-apss-shared";
- reg = <0x17990000 0x1000>;
- #mbox-cells = <1>;
- };
};
};
--
2.17.0.441.gb46fe60e1d-goog
^ permalink raw reply related
* [PATCH v4 4/4] drm/rockchip: support dp training outside dp firmware
From: Lin Huang @ 2018-05-15 3:22 UTC (permalink / raw)
To: seanpaul, airlied, zyw
Cc: dianders, briannorris, linux-rockchip, heiko, daniel.vetter,
jani.nikula, dri-devel, linux-arm-kernel, linux-kernel, eballetbo,
robh+dt, devicetree, Lin Huang
In-Reply-To: <1526354560-23135-1-git-send-email-hl@rock-chips.com>
DP firmware uses fixed phy config values to do training, but some
boards need to adjust these values to fit for their unique hardware
design. So get phy config values from dts and use software link training
instead of relying on firmware, if software training fail, keep firmware
training as a fallback if sw training fails.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
---
Changes in v2:
- update patch following Enric suggest
Changes in v3:
- use variable fw_training instead sw_training_success
- base on DP SPCE, if training fail use lower link rate to retry training
Changes in v4:
- improve cdn_dp_get_lower_link_rate() and cdn_dp_software_train_link() follow Sean suggest
drivers/gpu/drm/rockchip/Makefile | 3 +-
drivers/gpu/drm/rockchip/cdn-dp-core.c | 24 +-
drivers/gpu/drm/rockchip/cdn-dp-core.h | 2 +
drivers/gpu/drm/rockchip/cdn-dp-link-training.c | 420 ++++++++++++++++++++++++
drivers/gpu/drm/rockchip/cdn-dp-reg.c | 31 +-
drivers/gpu/drm/rockchip/cdn-dp-reg.h | 38 ++-
6 files changed, 505 insertions(+), 13 deletions(-)
create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-link-training.c
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index a314e21..b932f62 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -9,7 +9,8 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
-rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
+rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o \
+ cdn-dp-link-training.o
rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c
index cce64c1..d9d0d4d 100644
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
@@ -629,11 +629,13 @@ static void cdn_dp_encoder_enable(struct drm_encoder *encoder)
goto out;
}
}
-
- ret = cdn_dp_set_video_status(dp, CONTROL_VIDEO_IDLE);
- if (ret) {
- DRM_DEV_ERROR(dp->dev, "Failed to idle video %d\n", ret);
- goto out;
+ if (dp->use_fw_training == true) {
+ ret = cdn_dp_set_video_status(dp, CONTROL_VIDEO_IDLE);
+ if (ret) {
+ DRM_DEV_ERROR(dp->dev,
+ "Failed to idle video %d\n", ret);
+ goto out;
+ }
}
ret = cdn_dp_config_video(dp);
@@ -642,11 +644,15 @@ static void cdn_dp_encoder_enable(struct drm_encoder *encoder)
goto out;
}
- ret = cdn_dp_set_video_status(dp, CONTROL_VIDEO_VALID);
- if (ret) {
- DRM_DEV_ERROR(dp->dev, "Failed to valid video %d\n", ret);
- goto out;
+ if (dp->use_fw_training == true) {
+ ret = cdn_dp_set_video_status(dp, CONTROL_VIDEO_VALID);
+ if (ret) {
+ DRM_DEV_ERROR(dp->dev,
+ "Failed to valid video %d\n", ret);
+ goto out;
+ }
}
+
out:
mutex_unlock(&dp->lock);
}
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.h b/drivers/gpu/drm/rockchip/cdn-dp-core.h
index 46159b2..77a9793 100644
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.h
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h
@@ -84,6 +84,7 @@ struct cdn_dp_device {
bool connected;
bool active;
bool suspended;
+ bool use_fw_training;
const struct firmware *fw; /* cdn dp firmware */
unsigned int fw_version; /* cdn fw version */
@@ -106,6 +107,7 @@ struct cdn_dp_device {
u8 ports;
u8 lanes;
int active_port;
+ u8 train_set[4];
u8 dpcd[DP_RECEIVER_CAP_SIZE];
bool sink_has_audio;
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-link-training.c b/drivers/gpu/drm/rockchip/cdn-dp-link-training.c
new file mode 100644
index 0000000..7efd070
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/cdn-dp-link-training.c
@@ -0,0 +1,420 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author: Chris Zhong <zyw@rock-chips.com>
+ */
+
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/phy/phy.h>
+#include <soc/rockchip/rockchip_phy_typec.h>
+
+#include "cdn-dp-core.h"
+#include "cdn-dp-reg.h"
+
+static void cdn_dp_set_signal_levels(struct cdn_dp_device *dp)
+{
+ struct cdn_dp_port *port = dp->port[dp->active_port];
+ struct rockchip_typec_phy *tcphy = phy_get_drvdata(port->phy);
+
+ int rate = drm_dp_bw_code_to_link_rate(dp->link.rate);
+ u8 swing = (dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) >>
+ DP_TRAIN_VOLTAGE_SWING_SHIFT;
+ u8 pre_emphasis = (dp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
+ >> DP_TRAIN_PRE_EMPHASIS_SHIFT;
+
+ tcphy->typec_phy_config(port->phy, rate, dp->link.num_lanes,
+ swing, pre_emphasis);
+}
+
+static int cdn_dp_set_pattern(struct cdn_dp_device *dp, uint8_t dp_train_pat)
+{
+ u32 phy_config, global_config;
+ int ret;
+ uint8_t pattern = dp_train_pat & DP_TRAINING_PATTERN_MASK;
+
+ global_config = NUM_LANES(dp->link.num_lanes - 1) | SST_MODE |
+ GLOBAL_EN | RG_EN | ENC_RST_DIS | WR_VHSYNC_FALL;
+
+ phy_config = DP_TX_PHY_ENCODER_BYPASS(0) |
+ DP_TX_PHY_SKEW_BYPASS(0) |
+ DP_TX_PHY_DISPARITY_RST(0) |
+ DP_TX_PHY_LANE0_SKEW(0) |
+ DP_TX_PHY_LANE1_SKEW(1) |
+ DP_TX_PHY_LANE2_SKEW(2) |
+ DP_TX_PHY_LANE3_SKEW(3) |
+ DP_TX_PHY_10BIT_ENABLE(0);
+
+ if (pattern != DP_TRAINING_PATTERN_DISABLE) {
+ global_config |= NO_VIDEO;
+ phy_config |= DP_TX_PHY_TRAINING_ENABLE(1) |
+ DP_TX_PHY_SCRAMBLER_BYPASS(1) |
+ DP_TX_PHY_TRAINING_PATTERN(pattern);
+ }
+
+ ret = cdn_dp_reg_write(dp, DP_FRAMER_GLOBAL_CONFIG, global_config);
+ if (ret) {
+ DRM_ERROR("fail to set DP_FRAMER_GLOBAL_CONFIG, error: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = cdn_dp_reg_write(dp, DP_TX_PHY_CONFIG_REG, phy_config);
+ if (ret) {
+ DRM_ERROR("fail to set DP_TX_PHY_CONFIG_REG, error: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = cdn_dp_reg_write(dp, DPTX_LANE_EN, BIT(dp->link.num_lanes) - 1);
+ if (ret) {
+ DRM_ERROR("fail to set DPTX_LANE_EN, error: %d\n", ret);
+ return ret;
+ }
+
+ if (drm_dp_enhanced_frame_cap(dp->dpcd))
+ ret = cdn_dp_reg_write(dp, DPTX_ENHNCD, 1);
+ else
+ ret = cdn_dp_reg_write(dp, DPTX_ENHNCD, 0);
+ if (ret)
+ DRM_ERROR("failed to set DPTX_ENHNCD, error: %x\n", ret);
+
+ return ret;
+}
+
+static u8 cdn_dp_pre_emphasis_max(u8 voltage_swing)
+{
+ switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+ case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
+ return DP_TRAIN_PRE_EMPH_LEVEL_3;
+ case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
+ return DP_TRAIN_PRE_EMPH_LEVEL_2;
+ case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
+ return DP_TRAIN_PRE_EMPH_LEVEL_1;
+ default:
+ return DP_TRAIN_PRE_EMPH_LEVEL_0;
+ }
+}
+
+static void cdn_dp_get_adjust_train(struct cdn_dp_device *dp,
+ uint8_t link_status[DP_LINK_STATUS_SIZE])
+{
+ int i;
+ uint8_t v = 0, p = 0;
+ uint8_t preemph_max;
+
+ for (i = 0; i < dp->link.num_lanes; i++) {
+ v = max(v, drm_dp_get_adjust_request_voltage(link_status, i));
+ p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status,
+ i));
+ }
+
+ if (v >= VOLTAGE_LEVEL_2)
+ v = VOLTAGE_LEVEL_2 | DP_TRAIN_MAX_SWING_REACHED;
+
+ preemph_max = cdn_dp_pre_emphasis_max(v);
+ if (p >= preemph_max)
+ p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+ for (i = 0; i < dp->link.num_lanes; i++)
+ dp->train_set[i] = v | p;
+}
+
+/*
+ * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
+ * or 1.2 devices that support it, Training Pattern 2 otherwise.
+ */
+static u32 cdn_dp_select_chaneq_pattern(struct cdn_dp_device *dp)
+{
+ u32 training_pattern = DP_TRAINING_PATTERN_2;
+
+ /*
+ * cdn dp support HBR2 also support TPS3. TPS3 support is also mandatory
+ * for downstream devices that support HBR2. However, not all sinks
+ * follow the spec.
+ */
+ if (drm_dp_tps3_supported(dp->dpcd))
+ training_pattern = DP_TRAINING_PATTERN_3;
+ else
+ DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
+
+ return training_pattern;
+}
+
+
+static bool cdn_dp_link_max_vswing_reached(struct cdn_dp_device *dp)
+{
+ int lane;
+
+ for (lane = 0; lane < dp->link.num_lanes; lane++)
+ if ((dp->train_set[lane] & DP_TRAIN_MAX_SWING_REACHED) == 0)
+ return false;
+
+ return true;
+}
+
+static int cdn_dp_update_link_train(struct cdn_dp_device *dp)
+{
+ int ret;
+
+ cdn_dp_set_signal_levels(dp);
+
+ ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
+ dp->train_set, dp->link.num_lanes);
+ if (ret != dp->link.num_lanes)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int cdn_dp_set_link_train(struct cdn_dp_device *dp,
+ uint8_t dp_train_pat)
+{
+ uint8_t buf[sizeof(dp->train_set) + 1];
+ int ret, len;
+
+ buf[0] = dp_train_pat;
+ if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
+ DP_TRAINING_PATTERN_DISABLE) {
+ /* don't write DP_TRAINING_LANEx_SET on disable */
+ len = 1;
+ } else {
+ /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
+ memcpy(buf + 1, dp->train_set, dp->link.num_lanes);
+ len = dp->link.num_lanes + 1;
+ }
+
+ ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_PATTERN_SET,
+ buf, len);
+ if (ret != len)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int cdn_dp_reset_link_train(struct cdn_dp_device *dp,
+ uint8_t dp_train_pat)
+{
+ int ret;
+
+ memset(dp->train_set, 0, sizeof(dp->train_set));
+
+ cdn_dp_set_signal_levels(dp);
+
+ ret = cdn_dp_set_pattern(dp, dp_train_pat);
+ if (ret)
+ return ret;
+
+ return cdn_dp_set_link_train(dp, dp_train_pat);
+}
+
+/* Enable corresponding port and start training pattern 1 */
+static int cdn_dp_link_training_clock_recovery(struct cdn_dp_device *dp)
+{
+ u8 voltage;
+ u8 link_status[DP_LINK_STATUS_SIZE];
+ u32 voltage_tries, max_vswing_tries;
+ int ret;
+
+ /* clock recovery */
+ ret = cdn_dp_reset_link_train(dp, DP_TRAINING_PATTERN_1 |
+ DP_LINK_SCRAMBLING_DISABLE);
+ if (ret) {
+ DRM_ERROR("failed to start link train\n");
+ return ret;
+ }
+
+ voltage_tries = 1;
+ max_vswing_tries = 0;
+ for (;;) {
+ drm_dp_link_train_clock_recovery_delay(dp->dpcd);
+ if (drm_dp_dpcd_read_link_status(&dp->aux, link_status) !=
+ DP_LINK_STATUS_SIZE) {
+ DRM_ERROR("failed to get link status\n");
+ return -EINVAL;
+ }
+
+ if (drm_dp_clock_recovery_ok(link_status, dp->link.num_lanes)) {
+ DRM_DEBUG_KMS("clock recovery OK\n");
+ return 0;
+ }
+
+ if (voltage_tries >= 5) {
+ DRM_DEBUG_KMS("Same voltage tried 5 times\n");
+ return -EINVAL;
+ }
+
+ if (max_vswing_tries >= 1) {
+ DRM_DEBUG_KMS("Max Voltage Swing reached\n");
+ return -EINVAL;
+ }
+
+ voltage = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
+
+ /* Update training set as requested by target */
+ cdn_dp_get_adjust_train(dp, link_status);
+ if (cdn_dp_update_link_train(dp)) {
+ DRM_ERROR("failed to update link training\n");
+ return -EINVAL;
+ }
+
+ if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
+ voltage)
+ ++voltage_tries;
+ else
+ voltage_tries = 1;
+
+ if (cdn_dp_link_max_vswing_reached(dp))
+ ++max_vswing_tries;
+ }
+}
+
+static int cdn_dp_link_training_channel_equalization(struct cdn_dp_device *dp)
+{
+ int tries, ret;
+ u32 training_pattern;
+ uint8_t link_status[DP_LINK_STATUS_SIZE];
+
+ training_pattern = cdn_dp_select_chaneq_pattern(dp);
+ training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
+
+ ret = cdn_dp_set_pattern(dp, training_pattern);
+ if (ret)
+ return ret;
+
+ ret = cdn_dp_set_link_train(dp, training_pattern);
+ if (ret) {
+ DRM_ERROR("failed to start channel equalization\n");
+ return ret;
+ }
+
+ for (tries = 0; tries < 5; tries++) {
+ drm_dp_link_train_channel_eq_delay(dp->dpcd);
+ if (drm_dp_dpcd_read_link_status(&dp->aux, link_status) !=
+ DP_LINK_STATUS_SIZE) {
+ DRM_ERROR("failed to get link status\n");
+ break;
+ }
+
+ /* Make sure clock is still ok */
+ if (!drm_dp_clock_recovery_ok(link_status,
+ dp->link.num_lanes)) {
+ DRM_DEBUG_KMS("Clock recovery check failed\n");
+ break;
+ }
+
+ if (drm_dp_channel_eq_ok(link_status, dp->link.num_lanes)) {
+ DRM_DEBUG_KMS("Channel EQ done\n");
+ return 0;
+ }
+
+ /* Update training set as requested by target */
+ cdn_dp_get_adjust_train(dp, link_status);
+ if (cdn_dp_update_link_train(dp)) {
+ DRM_ERROR("failed to update link training\n");
+ break;
+ }
+ }
+
+ /* Try 5 times, else fail and try at lower BW */
+ if (tries == 5)
+ DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
+
+ return -EINVAL;
+}
+
+static int cdn_dp_stop_link_train(struct cdn_dp_device *dp)
+{
+ int ret = cdn_dp_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);
+
+ if (ret)
+ return ret;
+
+ return cdn_dp_set_link_train(dp, DP_TRAINING_PATTERN_DISABLE);
+}
+
+static int cdn_dp_get_lower_link_rate(struct cdn_dp_device *dp)
+{
+ switch (dp->link.rate) {
+ case DP_LINK_BW_1_62:
+ return -EINVAL;
+ case DP_LINK_BW_2_7:
+ dp->link.rate = DP_LINK_BW_1_62;
+ break;
+ case DP_LINK_BW_5_4:
+ dp->link.rate = DP_LINK_BW_2_7;
+ break;
+ default:
+ dp->link.rate = DP_LINK_BW_5_4;
+ break;
+ }
+
+ return 0;
+}
+
+int cdn_dp_software_train_link(struct cdn_dp_device *dp)
+{
+ int ret, stop_err;
+ u8 link_config[2];
+ u32 rate, sink_max, source_max;
+
+ ret = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, dp->dpcd,
+ sizeof(dp->dpcd));
+ if (ret < 0) {
+ DRM_DEV_ERROR(dp->dev, "Failed to get caps %d\n", ret);
+ return ret;
+ }
+
+ source_max = dp->lanes;
+ sink_max = drm_dp_max_lane_count(dp->dpcd);
+ dp->link.num_lanes = min(source_max, sink_max);
+
+ source_max = drm_dp_bw_code_to_link_rate(CDN_DP_MAX_LINK_RATE);
+ sink_max = drm_dp_max_link_rate(dp->dpcd);
+ rate = min(source_max, sink_max);
+ dp->link.rate = drm_dp_link_rate_to_bw_code(rate);
+
+ link_config[0] = 0;
+ link_config[1] = 0;
+ if (dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & 0x01)
+ link_config[1] = DP_SET_ANSI_8B10B;
+ drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+
+ while (true) {
+
+ /* Write the link configuration data */
+ link_config[0] = dp->link.rate;
+ link_config[1] = dp->link.num_lanes;
+ if (drm_dp_enhanced_frame_cap(dp->dpcd))
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, link_config, 2);
+
+ ret = cdn_dp_link_training_clock_recovery(dp);
+ if (ret) {
+ if (!cdn_dp_get_lower_link_rate(dp))
+ continue;
+
+ DRM_ERROR("training clock recovery failed: %d\n", ret);
+ break;
+ }
+
+ ret = cdn_dp_link_training_channel_equalization(dp);
+ if (ret) {
+ if (!cdn_dp_get_lower_link_rate(dp))
+ continue;
+
+ DRM_ERROR("training channel eq failed: %d\n", ret);
+ break;
+ }
+
+ break;
+ }
+
+ stop_err = cdn_dp_stop_link_train(dp);
+ if (stop_err) {
+ DRM_ERROR("stop training fail, error: %d\n", stop_err);
+ return stop_err;
+ }
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.c b/drivers/gpu/drm/rockchip/cdn-dp-reg.c
index 979355d..e1273e6 100644
--- a/drivers/gpu/drm/rockchip/cdn-dp-reg.c
+++ b/drivers/gpu/drm/rockchip/cdn-dp-reg.c
@@ -17,7 +17,9 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
+#include <linux/phy/phy.h>
#include <linux/reset.h>
+#include <soc/rockchip/rockchip_phy_typec.h>
#include "cdn-dp-core.h"
#include "cdn-dp-reg.h"
@@ -189,7 +191,7 @@ static int cdn_dp_mailbox_send(struct cdn_dp_device *dp, u8 module_id,
return 0;
}
-static int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val)
+int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val)
{
u8 msg[6];
@@ -609,6 +611,31 @@ int cdn_dp_train_link(struct cdn_dp_device *dp)
{
int ret;
+ /*
+ * DP firmware uses fixed phy config values to do training, but some
+ * boards need to adjust these values to fit for their unique hardware
+ * design. So if the phy is using custom config values, do software
+ * link training instead of relying on firmware, if software training
+ * fail, keep firmware training as a fallback if sw training fails.
+ */
+ ret = cdn_dp_software_train_link(dp);
+ if (ret) {
+ DRM_DEV_ERROR(dp->dev,
+ "Failed to do software training %d\n", ret);
+ goto do_fw_training;
+ }
+ ret = cdn_dp_reg_write(dp, SOURCE_HDTX_CAR, 0xf);
+ if (ret) {
+ DRM_DEV_ERROR(dp->dev,
+ "Failed to write SOURCE_HDTX_CAR register %d\n", ret);
+ goto do_fw_training;
+ }
+ dp->use_fw_training = false;
+ return 0;
+
+do_fw_training:
+ dp->use_fw_training = true;
+ DRM_DEV_DEBUG_KMS(dp->dev, "use fw training\n");
ret = cdn_dp_training_start(dp);
if (ret) {
DRM_DEV_ERROR(dp->dev, "Failed to start training %d\n", ret);
@@ -623,7 +650,7 @@ int cdn_dp_train_link(struct cdn_dp_device *dp)
DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n", dp->link.rate,
dp->link.num_lanes);
- return ret;
+ return 0;
}
int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active)
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.h b/drivers/gpu/drm/rockchip/cdn-dp-reg.h
index 6580b11..3420771 100644
--- a/drivers/gpu/drm/rockchip/cdn-dp-reg.h
+++ b/drivers/gpu/drm/rockchip/cdn-dp-reg.h
@@ -137,7 +137,7 @@
#define HPD_EVENT_MASK 0x211c
#define HPD_EVENT_DET 0x2120
-/* dpyx framer addr */
+/* dptx framer addr */
#define DP_FRAMER_GLOBAL_CONFIG 0x2200
#define DP_SW_RESET 0x2204
#define DP_FRAMER_TU 0x2208
@@ -431,6 +431,40 @@
/* Reference cycles when using lane clock as reference */
#define LANE_REF_CYC 0x8000
+/* register CM_VID_CTRL */
+#define LANE_VID_REF_CYC(x) (((x) & (BIT(24) - 1)) << 0)
+#define NMVID_MEAS_TOLERANCE(x) (((x) & 0xf) << 24)
+
+/* register DP_TX_PHY_CONFIG_REG */
+#define DP_TX_PHY_TRAINING_ENABLE(x) ((x) & 1)
+#define DP_TX_PHY_TRAINING_TYPE_PRBS7 (0 << 1)
+#define DP_TX_PHY_TRAINING_TYPE_TPS1 (1 << 1)
+#define DP_TX_PHY_TRAINING_TYPE_TPS2 (2 << 1)
+#define DP_TX_PHY_TRAINING_TYPE_TPS3 (3 << 1)
+#define DP_TX_PHY_TRAINING_TYPE_TPS4 (4 << 1)
+#define DP_TX_PHY_TRAINING_TYPE_PLTPAT (5 << 1)
+#define DP_TX_PHY_TRAINING_TYPE_D10_2 (6 << 1)
+#define DP_TX_PHY_TRAINING_TYPE_HBR2CPAT (8 << 1)
+#define DP_TX_PHY_TRAINING_PATTERN(x) ((x) << 1)
+#define DP_TX_PHY_SCRAMBLER_BYPASS(x) (((x) & 1) << 5)
+#define DP_TX_PHY_ENCODER_BYPASS(x) (((x) & 1) << 6)
+#define DP_TX_PHY_SKEW_BYPASS(x) (((x) & 1) << 7)
+#define DP_TX_PHY_DISPARITY_RST(x) (((x) & 1) << 8)
+#define DP_TX_PHY_LANE0_SKEW(x) (((x) & 7) << 9)
+#define DP_TX_PHY_LANE1_SKEW(x) (((x) & 7) << 12)
+#define DP_TX_PHY_LANE2_SKEW(x) (((x) & 7) << 15)
+#define DP_TX_PHY_LANE3_SKEW(x) (((x) & 7) << 18)
+#define DP_TX_PHY_10BIT_ENABLE(x) (((x) & 1) << 21)
+
+/* register DP_FRAMER_GLOBAL_CONFIG */
+#define NUM_LANES(x) ((x) & 3)
+#define SST_MODE (0 << 2)
+#define RG_EN (0 << 4)
+#define GLOBAL_EN BIT(3)
+#define NO_VIDEO BIT(5)
+#define ENC_RST_DIS BIT(6)
+#define WR_VHSYNC_FALL BIT(7)
+
enum voltage_swing_level {
VOLTAGE_LEVEL_0,
VOLTAGE_LEVEL_1,
@@ -476,6 +510,7 @@ int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip);
int cdn_dp_event_config(struct cdn_dp_device *dp);
u32 cdn_dp_get_event(struct cdn_dp_device *dp);
int cdn_dp_get_hpd_status(struct cdn_dp_device *dp);
+int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val);
ssize_t cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr,
u8 *data, u16 len);
ssize_t cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr,
@@ -489,4 +524,5 @@ int cdn_dp_config_video(struct cdn_dp_device *dp);
int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio);
int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable);
int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio);
+int cdn_dp_software_train_link(struct cdn_dp_device *dp);
#endif /* _CDN_DP_REG_H */
--
2.7.4
^ permalink raw reply related
* [PATCH v4 3/4] phy: rockchip-typec: support variable phy config value
From: Lin Huang @ 2018-05-15 3:22 UTC (permalink / raw)
To: seanpaul, airlied, zyw
Cc: dianders, briannorris, linux-rockchip, heiko, daniel.vetter,
jani.nikula, dri-devel, linux-arm-kernel, linux-kernel, eballetbo,
robh+dt, devicetree, Lin Huang
In-Reply-To: <1526354560-23135-1-git-send-email-hl@rock-chips.com>
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
---
Changes in v2:
- update patch following Enric suggest
Changes in v3:
- delete need_software_training variable
- add default phy config value, if dts do not define phy config value, use these value
Changes in v4:
- rename variable config to tcphy_default_config
drivers/phy/rockchip/phy-rockchip-typec.c | 306 ++++++++++++++++++++----------
include/soc/rockchip/rockchip_phy_typec.h | 63 ++++++
2 files changed, 271 insertions(+), 98 deletions(-)
create mode 100644 include/soc/rockchip/rockchip_phy_typec.h
diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
index 76a4b58..5d8692d 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -63,6 +63,7 @@
#include <linux/mfd/syscon.h>
#include <linux/phy/phy.h>
+#include <soc/rockchip/rockchip_phy_typec.h>
#define CMN_SSM_BANDGAP (0x21 << 2)
#define CMN_SSM_BIAS (0x22 << 2)
@@ -323,21 +324,29 @@
* clock 0: PLL 0 div 1
* clock 1: PLL 1 div 2
*/
-#define CLK_PLL_CONFIG 0X30
+#define CLK_PLL1_DIV1 0x20
+#define CLK_PLL1_DIV2 0x30
#define CLK_PLL_MASK 0x33
#define CMN_READY BIT(0)
+#define DP_PLL_CLOCK_ENABLE_ACK BIT(3)
#define DP_PLL_CLOCK_ENABLE BIT(2)
+#define DP_PLL_ENABLE_ACK BIT(1)
#define DP_PLL_ENABLE BIT(0)
#define DP_PLL_DATA_RATE_RBR ((2 << 12) | (4 << 8))
#define DP_PLL_DATA_RATE_HBR ((2 << 12) | (4 << 8))
#define DP_PLL_DATA_RATE_HBR2 ((1 << 12) | (2 << 8))
+#define DP_PLL_DATA_RATE_MASK 0xff00
-#define DP_MODE_A0 BIT(4)
-#define DP_MODE_A2 BIT(6)
-#define DP_MODE_ENTER_A0 0xc101
-#define DP_MODE_ENTER_A2 0xc104
+#define DP_MODE_MASK 0xf
+#define DP_MODE_ENTER_A0 BIT(0)
+#define DP_MODE_ENTER_A2 BIT(2)
+#define DP_MODE_ENTER_A3 BIT(3)
+#define DP_MODE_A0_ACK BIT(4)
+#define DP_MODE_A2_ACK BIT(6)
+#define DP_MODE_A3_ACK BIT(7)
+#define DP_LINK_RESET_DEASSERTED BIT(8)
#define PHY_MODE_SET_TIMEOUT 100000
@@ -349,51 +358,7 @@
#define MODE_DFP_USB BIT(1)
#define MODE_DFP_DP BIT(2)
-struct usb3phy_reg {
- u32 offset;
- u32 enable_bit;
- u32 write_enable;
-};
-
-/**
- * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
- * @reg: the base address for usb3-phy config.
- * @typec_conn_dir: the register of type-c connector direction.
- * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
- * @external_psm: the register of type-c phy external psm clock.
- * @pipe_status: the register of type-c phy pipe status.
- * @usb3_host_disable: the register of type-c usb3 host disable.
- * @usb3_host_port: the register of type-c usb3 host port.
- * @uphy_dp_sel: the register of type-c phy DP select control.
- */
-struct rockchip_usb3phy_port_cfg {
- unsigned int reg;
- struct usb3phy_reg typec_conn_dir;
- struct usb3phy_reg usb3tousb2_en;
- struct usb3phy_reg external_psm;
- struct usb3phy_reg pipe_status;
- struct usb3phy_reg usb3_host_disable;
- struct usb3phy_reg usb3_host_port;
- struct usb3phy_reg uphy_dp_sel;
-};
-
-struct rockchip_typec_phy {
- struct device *dev;
- void __iomem *base;
- struct extcon_dev *extcon;
- struct regmap *grf_regs;
- struct clk *clk_core;
- struct clk *clk_ref;
- struct reset_control *uphy_rst;
- struct reset_control *pipe_rst;
- struct reset_control *tcphy_rst;
- const struct rockchip_usb3phy_port_cfg *port_cfgs;
- /* mutex to protect access to individual PHYs */
- struct mutex lock;
-
- bool flip;
- u8 mode;
-};
+#define DP_DEFAULT_RATE 162000
struct phy_reg {
u16 value;
@@ -417,15 +382,15 @@ struct phy_reg usb3_pll_cfg[] = {
{ 0x8, CMN_DIAG_PLL0_LF_PROG },
};
-struct phy_reg dp_pll_cfg[] = {
+struct phy_reg dp_pll_rbr_cfg[] = {
{ 0xf0, CMN_PLL1_VCOCAL_INIT },
{ 0x18, CMN_PLL1_VCOCAL_ITER },
{ 0x30b9, CMN_PLL1_VCOCAL_START },
- { 0x21c, CMN_PLL1_INTDIV },
+ { 0x87, CMN_PLL1_INTDIV },
{ 0, CMN_PLL1_FRACDIV },
- { 0x5, CMN_PLL1_HIGH_THR },
- { 0x35, CMN_PLL1_SS_CTRL1 },
- { 0x7f1e, CMN_PLL1_SS_CTRL2 },
+ { 0x22, CMN_PLL1_HIGH_THR },
+ { 0x8000, CMN_PLL1_SS_CTRL1 },
+ { 0, CMN_PLL1_SS_CTRL2 },
{ 0x20, CMN_PLL1_DSM_DIAG },
{ 0, CMN_PLLSM1_USER_DEF_CTRL },
{ 0, CMN_DIAG_PLL1_OVRD },
@@ -436,9 +401,52 @@ struct phy_reg dp_pll_cfg[] = {
{ 0x8, CMN_DIAG_PLL1_LF_PROG },
{ 0x100, CMN_DIAG_PLL1_PTATIS_TUNE1 },
{ 0x7, CMN_DIAG_PLL1_PTATIS_TUNE2 },
- { 0x4, CMN_DIAG_PLL1_INCLK_CTRL },
+ { 0x1, CMN_DIAG_PLL1_INCLK_CTRL },
+};
+
+struct phy_reg dp_pll_hbr_cfg[] = {
+ { 0xf0, CMN_PLL1_VCOCAL_INIT },
+ { 0x18, CMN_PLL1_VCOCAL_ITER },
+ { 0x30b4, CMN_PLL1_VCOCAL_START },
+ { 0xe1, CMN_PLL1_INTDIV },
+ { 0, CMN_PLL1_FRACDIV },
+ { 0x5, CMN_PLL1_HIGH_THR },
+ { 0x8000, CMN_PLL1_SS_CTRL1 },
+ { 0, CMN_PLL1_SS_CTRL2 },
+ { 0x20, CMN_PLL1_DSM_DIAG },
+ { 0x1000, CMN_PLLSM1_USER_DEF_CTRL },
+ { 0, CMN_DIAG_PLL1_OVRD },
+ { 0, CMN_DIAG_PLL1_FBH_OVRD },
+ { 0, CMN_DIAG_PLL1_FBL_OVRD },
+ { 0x7, CMN_DIAG_PLL1_V2I_TUNE },
+ { 0x45, CMN_DIAG_PLL1_CP_TUNE },
+ { 0x8, CMN_DIAG_PLL1_LF_PROG },
+ { 0x1, CMN_DIAG_PLL1_PTATIS_TUNE1 },
+ { 0x1, CMN_DIAG_PLL1_PTATIS_TUNE2 },
+ { 0x1, CMN_DIAG_PLL1_INCLK_CTRL },
};
+struct phy_reg dp_pll_hbr2_cfg[] = {
+ { 0xf0, CMN_PLL1_VCOCAL_INIT },
+ { 0x18, CMN_PLL1_VCOCAL_ITER },
+ { 0x30b4, CMN_PLL1_VCOCAL_START },
+ { 0xe1, CMN_PLL1_INTDIV },
+ { 0, CMN_PLL1_FRACDIV },
+ { 0x5, CMN_PLL1_HIGH_THR },
+ { 0x8000, CMN_PLL1_SS_CTRL1 },
+ { 0, CMN_PLL1_SS_CTRL2 },
+ { 0x20, CMN_PLL1_DSM_DIAG },
+ { 0x1000, CMN_PLLSM1_USER_DEF_CTRL },
+ { 0, CMN_DIAG_PLL1_OVRD },
+ { 0, CMN_DIAG_PLL1_FBH_OVRD },
+ { 0, CMN_DIAG_PLL1_FBL_OVRD },
+ { 0x7, CMN_DIAG_PLL1_V2I_TUNE },
+ { 0x45, CMN_DIAG_PLL1_CP_TUNE },
+ { 0x8, CMN_DIAG_PLL1_LF_PROG },
+ { 0x1, CMN_DIAG_PLL1_PTATIS_TUNE1 },
+ { 0x1, CMN_DIAG_PLL1_PTATIS_TUNE2 },
+ { 0x1, CMN_DIAG_PLL1_INCLK_CTRL },
+};
static const struct rockchip_usb3phy_port_cfg rk3399_usb3phy_port_cfgs[] = {
{
.reg = 0xff7c0000,
@@ -463,6 +471,24 @@ static const struct rockchip_usb3phy_port_cfg rk3399_usb3phy_port_cfgs[] = {
{ /* sentinel */ }
};
+/* default phy config */
+static const struct phy_config tcphy_default_config[3][4] = {
+ {{ .swing = 0x2a, .pe = 0x00 },
+ { .swing = 0x1f, .pe = 0x15 },
+ { .swing = 0x14, .pe = 0x22 },
+ { .swing = 0x02, .pe = 0x2b } },
+
+ {{ .swing = 0x21, .pe = 0x00 },
+ { .swing = 0x12, .pe = 0x15 },
+ { .swing = 0x02, .pe = 0x22 },
+ { .swing = 0, .pe = 0 } },
+
+ {{ .swing = 0x15, .pe = 0x00 },
+ { .swing = 0x00, .pe = 0x15 },
+ { .swing = 0, .pe = 0 },
+ { .swing = 0, .pe = 0 } },
+};
+
static void tcphy_cfg_24m(struct rockchip_typec_phy *tcphy)
{
u32 i, rdata;
@@ -484,7 +510,7 @@ static void tcphy_cfg_24m(struct rockchip_typec_phy *tcphy)
rdata = readl(tcphy->base + CMN_DIAG_HSCLK_SEL);
rdata &= ~CLK_PLL_MASK;
- rdata |= CLK_PLL_CONFIG;
+ rdata |= CLK_PLL1_DIV2;
writel(rdata, tcphy->base + CMN_DIAG_HSCLK_SEL);
}
@@ -498,17 +524,44 @@ static void tcphy_cfg_usb3_pll(struct rockchip_typec_phy *tcphy)
tcphy->base + usb3_pll_cfg[i].addr);
}
-static void tcphy_cfg_dp_pll(struct rockchip_typec_phy *tcphy)
+static void tcphy_cfg_dp_pll(struct rockchip_typec_phy *tcphy, int link_rate)
{
- u32 i;
+ struct phy_reg *phy_cfg;
+ u32 clk_ctrl;
+ u32 i, cfg_size, hsclk_sel;
+
+ hsclk_sel = readl(tcphy->base + CMN_DIAG_HSCLK_SEL);
+ hsclk_sel &= ~CLK_PLL_MASK;
+
+ switch (link_rate) {
+ case 162000:
+ clk_ctrl = DP_PLL_DATA_RATE_RBR;
+ hsclk_sel |= CLK_PLL1_DIV2;
+ phy_cfg = dp_pll_rbr_cfg;
+ cfg_size = ARRAY_SIZE(dp_pll_rbr_cfg);
+ break;
+ case 270000:
+ clk_ctrl = DP_PLL_DATA_RATE_HBR;
+ hsclk_sel |= CLK_PLL1_DIV2;
+ phy_cfg = dp_pll_hbr_cfg;
+ cfg_size = ARRAY_SIZE(dp_pll_hbr_cfg);
+ break;
+ case 540000:
+ clk_ctrl = DP_PLL_DATA_RATE_HBR2;
+ hsclk_sel |= CLK_PLL1_DIV1;
+ phy_cfg = dp_pll_hbr2_cfg;
+ cfg_size = ARRAY_SIZE(dp_pll_hbr2_cfg);
+ break;
+ }
+
+ clk_ctrl |= DP_PLL_CLOCK_ENABLE | DP_PLL_ENABLE;
+ writel(clk_ctrl, tcphy->base + DP_CLK_CTL);
- /* set the default mode to RBR */
- writel(DP_PLL_CLOCK_ENABLE | DP_PLL_ENABLE | DP_PLL_DATA_RATE_RBR,
- tcphy->base + DP_CLK_CTL);
+ writel(hsclk_sel, tcphy->base + CMN_DIAG_HSCLK_SEL);
/* load the configuration of PLL1 */
- for (i = 0; i < ARRAY_SIZE(dp_pll_cfg); i++)
- writel(dp_pll_cfg[i].value, tcphy->base + dp_pll_cfg[i].addr);
+ for (i = 0; i < cfg_size; i++)
+ writel(phy_cfg[i].value, tcphy->base + phy_cfg[i].addr);
}
static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
@@ -535,9 +588,10 @@ static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
writel(0xfb, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane));
}
-static void tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
+static void tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy, int link_rate,
+ u8 swing, u8 pre_emp, u32 lane)
{
- u16 rdata;
+ u16 val;
writel(0xbefc, tcphy->base + XCVR_PSM_RCTRL(lane));
writel(0x6799, tcphy->base + TX_PSC_A0(lane));
@@ -545,25 +599,31 @@ static void tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
writel(0x98, tcphy->base + TX_PSC_A2(lane));
writel(0x98, tcphy->base + TX_PSC_A3(lane));
- writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane));
- writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_001(lane));
- writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_010(lane));
- writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_011(lane));
- writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_100(lane));
- writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_101(lane));
- writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_110(lane));
- writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_111(lane));
- writel(0, tcphy->base + TX_TXCC_CPOST_MULT_10(lane));
- writel(0, tcphy->base + TX_TXCC_CPOST_MULT_01(lane));
- writel(0, tcphy->base + TX_TXCC_CPOST_MULT_00(lane));
- writel(0, tcphy->base + TX_TXCC_CPOST_MULT_11(lane));
-
- writel(0x128, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane));
- writel(0x400, tcphy->base + TX_DIAG_TX_DRV(lane));
-
- rdata = readl(tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane));
- rdata = (rdata & 0x8fff) | 0x6000;
- writel(rdata, tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane));
+ writel(tcphy->config[swing][pre_emp].swing,
+ tcphy->base + TX_TXCC_MGNFS_MULT_000(lane));
+ writel(tcphy->config[swing][pre_emp].pe,
+ tcphy->base + TX_TXCC_CPOST_MULT_00(lane));
+
+ if (swing == 2 && pre_emp == 0 && link_rate != 540000) {
+ writel(0x700, tcphy->base + TX_DIAG_TX_DRV(lane));
+ writel(0x13c, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane));
+ } else {
+ writel(0x128, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane));
+ writel(0x0400, tcphy->base + TX_DIAG_TX_DRV(lane));
+ }
+
+ val = readl(tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane));
+ val = val & 0x8fff;
+ switch (link_rate) {
+ case 162000:
+ case 270000:
+ val |= (6 << 12);
+ break;
+ case 540000:
+ val |= (4 << 12);
+ break;
+ }
+ writel(val, tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane));
}
static inline int property_enable(struct rockchip_typec_phy *tcphy,
@@ -754,30 +814,33 @@ static int tcphy_phy_init(struct rockchip_typec_phy *tcphy, u8 mode)
tcphy_cfg_24m(tcphy);
if (mode == MODE_DFP_DP) {
- tcphy_cfg_dp_pll(tcphy);
+ tcphy_cfg_dp_pll(tcphy, DP_DEFAULT_RATE);
for (i = 0; i < 4; i++)
- tcphy_dp_cfg_lane(tcphy, i);
+ tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, i);
writel(PIN_ASSIGN_C_E, tcphy->base + PMA_LANE_CFG);
} else {
tcphy_cfg_usb3_pll(tcphy);
- tcphy_cfg_dp_pll(tcphy);
+ tcphy_cfg_dp_pll(tcphy, DP_DEFAULT_RATE);
if (tcphy->flip) {
tcphy_tx_usb3_cfg_lane(tcphy, 3);
tcphy_rx_usb3_cfg_lane(tcphy, 2);
- tcphy_dp_cfg_lane(tcphy, 0);
- tcphy_dp_cfg_lane(tcphy, 1);
+ tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 0);
+ tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 1);
} else {
tcphy_tx_usb3_cfg_lane(tcphy, 0);
tcphy_rx_usb3_cfg_lane(tcphy, 1);
- tcphy_dp_cfg_lane(tcphy, 2);
- tcphy_dp_cfg_lane(tcphy, 3);
+ tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 2);
+ tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 3);
}
writel(PIN_ASSIGN_D_F, tcphy->base + PMA_LANE_CFG);
}
- writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL);
+ val = readl(tcphy->base + DP_MODE_CTL);
+ val &= ~DP_MODE_MASK;
+ val |= DP_MODE_ENTER_A2 | DP_LINK_RESET_DEASSERTED;
+ writel(val, tcphy->base + DP_MODE_CTL);
reset_control_deassert(tcphy->uphy_rst);
@@ -990,7 +1053,7 @@ static int rockchip_dp_phy_power_on(struct phy *phy)
property_enable(tcphy, &cfg->uphy_dp_sel, 1);
ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL,
- val, val & DP_MODE_A2, 1000,
+ val, val & DP_MODE_A2_ACK, 1000,
PHY_MODE_SET_TIMEOUT);
if (ret < 0) {
dev_err(tcphy->dev, "failed to wait TCPHY enter A2\n");
@@ -999,13 +1062,19 @@ static int rockchip_dp_phy_power_on(struct phy *phy)
tcphy_dp_aux_calibration(tcphy);
- writel(DP_MODE_ENTER_A0, tcphy->base + DP_MODE_CTL);
+ /* enter A0 mode */
+ val = readl(tcphy->base + DP_MODE_CTL);
+ val &= ~DP_MODE_MASK;
+ val |= DP_MODE_ENTER_A0;
+ writel(val, tcphy->base + DP_MODE_CTL);
ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL,
- val, val & DP_MODE_A0, 1000,
+ val, val & DP_MODE_A0_ACK, 1000,
PHY_MODE_SET_TIMEOUT);
if (ret < 0) {
- writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL);
+ val &= ~DP_MODE_MASK;
+ val |= DP_MODE_ENTER_A2;
+ writel(val, tcphy->base + DP_MODE_CTL);
dev_err(tcphy->dev, "failed to wait TCPHY enter A0\n");
goto power_on_finish;
}
@@ -1023,6 +1092,7 @@ static int rockchip_dp_phy_power_on(struct phy *phy)
static int rockchip_dp_phy_power_off(struct phy *phy)
{
struct rockchip_typec_phy *tcphy = phy_get_drvdata(phy);
+ u32 val;
mutex_lock(&tcphy->lock);
@@ -1031,7 +1101,10 @@ static int rockchip_dp_phy_power_off(struct phy *phy)
tcphy->mode &= ~MODE_DFP_DP;
- writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL);
+ val = readl(tcphy->base + DP_MODE_CTL);
+ val &= ~DP_MODE_MASK;
+ val |= DP_MODE_ENTER_A2;
+ writel(val, tcphy->base + DP_MODE_CTL);
if (tcphy->mode == MODE_DISCONNECT)
tcphy_phy_deinit(tcphy);
@@ -1047,9 +1120,35 @@ static const struct phy_ops rockchip_dp_phy_ops = {
.owner = THIS_MODULE,
};
+static int typec_dp_phy_config(struct phy *phy, int link_rate,
+ int lanes, u8 swing, u8 pre_emp)
+{
+ struct rockchip_typec_phy *tcphy = phy_get_drvdata(phy);
+ u8 i;
+
+ tcphy_cfg_dp_pll(tcphy, link_rate);
+
+ if (tcphy->mode == MODE_DFP_DP) {
+ for (i = 0; i < 4; i++)
+ tcphy_dp_cfg_lane(tcphy, link_rate, swing, pre_emp, i);
+ } else {
+ if (tcphy->flip) {
+ tcphy_dp_cfg_lane(tcphy, link_rate, swing, pre_emp, 0);
+ tcphy_dp_cfg_lane(tcphy, link_rate, swing, pre_emp, 1);
+ } else {
+ tcphy_dp_cfg_lane(tcphy, link_rate, swing, pre_emp, 2);
+ tcphy_dp_cfg_lane(tcphy, link_rate, swing, pre_emp, 3);
+ }
+ }
+
+ return 0;
+}
+
static int tcphy_parse_dt(struct rockchip_typec_phy *tcphy,
struct device *dev)
{
+ int ret;
+
tcphy->grf_regs = syscon_regmap_lookup_by_phandle(dev->of_node,
"rockchip,grf");
if (IS_ERR(tcphy->grf_regs)) {
@@ -1087,6 +1186,16 @@ static int tcphy_parse_dt(struct rockchip_typec_phy *tcphy,
return PTR_ERR(tcphy->tcphy_rst);
}
+ /*
+ * check if phy_config pass from dts, if no,
+ * use default phy config value.
+ */
+ ret = of_property_read_u32_array(dev->of_node, "rockchip,phy_config",
+ (u32 *)tcphy->config, sizeof(tcphy->config) / sizeof(u32));
+ if (ret)
+ memcpy(tcphy->config, tcphy_default_config,
+ sizeof(tcphy->config));
+
return 0;
}
@@ -1171,6 +1280,7 @@ static int rockchip_typec_phy_probe(struct platform_device *pdev)
}
}
+ tcphy->typec_phy_config = typec_dp_phy_config;
pm_runtime_enable(dev);
for_each_available_child_of_node(np, child_np) {
diff --git a/include/soc/rockchip/rockchip_phy_typec.h b/include/soc/rockchip/rockchip_phy_typec.h
new file mode 100644
index 0000000..be6af0e
--- /dev/null
+++ b/include/soc/rockchip/rockchip_phy_typec.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author: Lin Huang <hl@rock-chips.com>
+ */
+
+#ifndef __SOC_ROCKCHIP_PHY_TYPEC_H
+#define __SOC_ROCKCHIP_PHY_TYPEC_H
+
+struct usb3phy_reg {
+ u32 offset;
+ u32 enable_bit;
+ u32 write_enable;
+};
+
+/**
+ * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
+ * @reg: the base address for usb3-phy config.
+ * @typec_conn_dir: the register of type-c connector direction.
+ * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
+ * @external_psm: the register of type-c phy external psm clock.
+ * @pipe_status: the register of type-c phy pipe status.
+ * @usb3_host_disable: the register of type-c usb3 host disable.
+ * @usb3_host_port: the register of type-c usb3 host port.
+ * @uphy_dp_sel: the register of type-c phy DP select control.
+ */
+struct rockchip_usb3phy_port_cfg {
+ unsigned int reg;
+ struct usb3phy_reg typec_conn_dir;
+ struct usb3phy_reg usb3tousb2_en;
+ struct usb3phy_reg external_psm;
+ struct usb3phy_reg pipe_status;
+ struct usb3phy_reg usb3_host_disable;
+ struct usb3phy_reg usb3_host_port;
+ struct usb3phy_reg uphy_dp_sel;
+};
+
+struct phy_config {
+ int swing;
+ int pe;
+};
+
+struct rockchip_typec_phy {
+ struct device *dev;
+ void __iomem *base;
+ struct extcon_dev *extcon;
+ struct regmap *grf_regs;
+ struct clk *clk_core;
+ struct clk *clk_ref;
+ struct reset_control *uphy_rst;
+ struct reset_control *pipe_rst;
+ struct reset_control *tcphy_rst;
+ const struct rockchip_usb3phy_port_cfg *port_cfgs;
+ /* mutex to protect access to individual PHYs */
+ struct mutex lock;
+ struct phy_config config[3][4];
+ bool flip;
+ u8 mode;
+ int (*typec_phy_config)(struct phy *phy, int link_rate,
+ int lanes, u8 swing, u8 pre_emp);
+};
+
+#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v4 2/4] Documentation: bindings: add phy_config for Rockchip USB Type-C PHY
From: Lin Huang @ 2018-05-15 3:22 UTC (permalink / raw)
To: seanpaul, airlied, zyw
Cc: dianders, briannorris, linux-rockchip, heiko, daniel.vetter,
jani.nikula, dri-devel, linux-arm-kernel, linux-kernel, eballetbo,
robh+dt, devicetree, Lin Huang
In-Reply-To: <1526354560-23135-1-git-send-email-hl@rock-chips.com>
If want to do training outside DP Firmware, need phy voltage swing
and pre_emphasis value.
Signed-off-by: Lin Huang <hl@rock-chips.com>
---
Changes in v2:
- None
Changes in v3:
- modify property description and add this property to Example
Change in v4:
- None
.../devicetree/bindings/phy/phy-rockchip-typec.txt | 29 +++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
index 960da7f..af298f2 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
@@ -17,7 +17,8 @@ Required properties:
Optional properties:
- extcon : extcon specifier for the Power Delivery
-
+ - rockchip,phy_config : A list of voltage swing(mv) and pre-emphasis
+ (dB) pairs.
Required nodes : a sub-node is required for each port the phy provides.
The sub-node name is used to identify dp or usb3 port,
and shall be the following entries:
@@ -50,6 +51,19 @@ Example:
<&cru SRST_P_UPHY0_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
+ rockchip,phy_config =<0x2a 0x00
+ 0x1f 0x15
+ 0x14 0x22
+ 0x02 0x2b
+ 0x21 0x00
+ 0x12 0x15
+ 0x02 0x22
+ 0 0
+ 0x15 0x00
+ 0x00 0x15
+ 0 0
+ 0 0>;
+
tcphy0_dp: dp-port {
#phy-cells = <0>;
};
@@ -74,6 +88,19 @@ Example:
<&cru SRST_P_UPHY1_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
+ rockchip,phy_config =<0x2a 0x00
+ 0x1f 0x15
+ 0x14 0x22
+ 0x02 0x2b
+ 0x21 0x00
+ 0x12 0x15
+ 0x02 0x22
+ 0 0
+ 0x15 0x00
+ 0x00 0x15
+ 0 0
+ 0 0>;
+
tcphy1_dp: dp-port {
#phy-cells = <0>;
};
--
2.7.4
^ permalink raw reply related
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