* [PATCH v2 0/4] Add DesignWare EP support
From: Gustavo Pimentel @ 2018-05-15 14:41 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, Joao.Pinto, jingoohan1, kishon,
robh+dt, mark.rutland
Cc: linux-pci, linux-kernel, devicetree, Gustavo Pimentel
Patch set was made against the Lorenzo's pci/dwc branch.
The PCIe controller dual mode is capable of operating in RC mode as well
as EP mode by configuration option. Till now only RC mode was supported,
with this patch is add EP support to the DesignWare driver.
Gustavo Pimentel (4):
bindings: PCI: designware: Example update
PCI: dwc: Add support for EP mode
bindings: PCI: designware: Add support for EP in DesignWare driver
misc: pci_endpoint_test: Add DesignWare EP entry
.../devicetree/bindings/pci/designware-pcie.txt | 24 +++-
drivers/misc/pci_endpoint_test.c | 1 +
drivers/pci/dwc/Kconfig | 37 +++--
drivers/pci/dwc/pcie-designware-ep.c | 3 +
drivers/pci/dwc/pcie-designware-plat.c | 149 +++++++++++++++++++--
drivers/pci/endpoint/functions/pci-epf-test.c | 7 +
include/linux/pci-epc.h | 8 ++
7 files changed, 205 insertions(+), 24 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH v4 3/3] ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules
From: Krzysztof Kozlowski @ 2018-05-15 14:41 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Thierry Reding, Jonathan Hunter,
devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Stefan Agner, Lucas Stach, Krzysztof Kozlowski
In-Reply-To: <1526395285-19006-1-git-send-email-krzk@kernel.org>
Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM
(with 1024 MB NAND) flavors. Both of them will use the same DTSI
expecting the bootloader to do the fixup of /memory node. However in
case it does not happen, let's stay on safe side by limiting the memory
to 256 MB for both versions of Colibri-T20.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
RFT:
Not tested on 512 MB module as I have only the 256 MB one.
Changes since v3:
1. Reduce the memory in existing DTSI instead of creating a new one
(suggested by Marcel).
Changes since v2:
1. Do not add new compatible but use everywhere existing
"toradex,colibri_t20-512" (suggested by Rob).
Changes since v1:
1. Fix memory size in tegra20-colibri-256.dtsi (was working fine because
my bootloader uses mem= argument).
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 9 +++++++--
arch/arm/boot/dts/tegra20-iris-512.dts | 2 +-
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 305efb275b48..b9387c540450 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -2,7 +2,7 @@
#include "tegra20.dtsi"
/ {
- model = "Toradex Colibri T20 512MB";
+ model = "Toradex Colibri T20 256/512 MB";
compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
aliases {
@@ -12,7 +12,12 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x20000000>;
+ /*
+ * Set memory to 256 MB to be safe as this could be used on
+ * 256 or 512 MB module. It is expected from bootloader
+ * to fix this up for 512 MB version.
+ */
+ reg = <0x00000000 0x10000000>;
};
host1x@50000000 {
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index 40126388946d..efaa96228722 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -4,7 +4,7 @@
#include "tegra20-colibri-512.dtsi"
/ {
- model = "Toradex Colibri T20 512MB on Iris";
+ model = "Toradex Colibri T20 256/512 MB on Iris";
compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
aliases {
--
2.7.4
^ permalink raw reply related
* [PATCH v4 2/3] ARM: dts: tegra: Fix unit_address_vs_reg and avoid_unnecessary_addr_size DTC warnings
From: Krzysztof Kozlowski @ 2018-05-15 14:41 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Thierry Reding, Jonathan Hunter,
devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Stefan Agner, Lucas Stach, Krzysztof Kozlowski
In-Reply-To: <1526395285-19006-1-git-send-email-krzk@kernel.org>
Remove unneeded address/size cells properties and unit addresses to fix
DTC warnings like:
arch/arm/boot/dts/tegra30-apalis-eval.dtb: Warning (unit_address_vs_reg):
/i2c@7000d000/stmpe811@41/stmpe_touchscreen@0: node has a unit name, but no reg property
arch/arm/boot/dts/tegra30-apalis-eval.dtb: Warning (avoid_unnecessary_addr_size):
/i2c@7000d000/stmpe811@41: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 4 +---
arch/arm/boot/dts/tegra30-beaver.dts | 3 ---
arch/arm/boot/dts/tegra30-colibri.dtsi | 2 --
3 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 184f60c720fa..5038ca7b68af 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -590,8 +590,6 @@
/* STMPE811 touch screen controller */
stmpe811@41 {
compatible = "st,stmpe811";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0x41>;
interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio>;
@@ -600,7 +598,7 @@
blocks = <0x5>;
irq-trigger = <0x1>;
- stmpe_touchscreen@0 {
+ stmpe_touchscreen {
compatible = "st,stmpe-ts";
/* 3.25 MHz ADC clock speed */
st,adc-freq = <1>;
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 72369877d284..961934f70639 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1791,9 +1791,6 @@
vccio-supply = <&vdd_5v_in_reg>;
regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
vdd1_reg: vdd1 {
regulator-name = "vddio_ddr_1v2";
regulator-min-microvolt = <1200000>;
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index cc46cedf80b9..a593dc8be47f 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -352,8 +352,6 @@
/* STMPE811 touch screen controller */
stmpe811@41 {
compatible = "st,stmpe811";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0x41>;
interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio>;
--
2.7.4
^ permalink raw reply related
* [PATCH v4 1/3] ARM: dts: tegra: Remove skeleton.dtsi and fix DTC warnings for /memory
From: Krzysztof Kozlowski @ 2018-05-15 14:41 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Thierry Reding, Jonathan Hunter,
devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Stefan Agner, Lucas Stach, Krzysztof Kozlowski
In-Reply-To: <1526395285-19006-1-git-send-email-krzk@kernel.org>
Remove the usage of skeleton.dtsi and add necessary properties to /memory
node to fix the DTC warnings:
arch/arm/boot/dts/tegra20-harmony.dtb: Warning (unit_address_vs_reg):
/memory: node has a reg or ranges property, but no unit name
The DTB after the change is the same as before except adding
unit-address to /memory node.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/tegra114-dalmore.dts | 3 ++-
arch/arm/boot/dts/tegra114-roth.dts | 3 ++-
arch/arm/boot/dts/tegra114-tn7.dts | 3 ++-
arch/arm/boot/dts/tegra114.dtsi | 4 ++--
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 3 ++-
arch/arm/boot/dts/tegra124-apalis.dtsi | 3 ++-
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 3 ++-
arch/arm/boot/dts/tegra124-nyan.dtsi | 3 ++-
arch/arm/boot/dts/tegra124-venice2.dts | 3 ++-
arch/arm/boot/dts/tegra124.dtsi | 2 --
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 3 ++-
arch/arm/boot/dts/tegra20-harmony.dts | 3 ++-
arch/arm/boot/dts/tegra20-paz00.dts | 3 ++-
arch/arm/boot/dts/tegra20-seaboard.dts | 3 ++-
arch/arm/boot/dts/tegra20-tamonten.dtsi | 3 ++-
arch/arm/boot/dts/tegra20-trimslice.dts | 3 ++-
arch/arm/boot/dts/tegra20-ventana.dts | 3 ++-
arch/arm/boot/dts/tegra20.dtsi | 7 +++++--
arch/arm/boot/dts/tegra30-apalis.dtsi | 5 +++++
arch/arm/boot/dts/tegra30-beaver.dts | 3 ++-
arch/arm/boot/dts/tegra30-cardhu.dtsi | 3 ++-
arch/arm/boot/dts/tegra30-colibri.dtsi | 3 ++-
arch/arm/boot/dts/tegra30.dtsi | 7 +++++--
23 files changed, 53 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index eafff16765b4..5cdcedfc19cb 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -23,7 +23,8 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@80000000 {
+ device_type = "memory";
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts
index 7ed7370ee67a..b4f329a07c60 100644
--- a/arch/arm/boot/dts/tegra114-roth.dts
+++ b/arch/arm/boot/dts/tegra114-roth.dts
@@ -28,7 +28,8 @@
};
};
- memory {
+ memory@80000000 {
+ device_type = "memory";
/* memory >= 0x79600000 is reserved for firmware usage */
reg = <0x80000000 0x79600000>;
};
diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts
index 7fc4a8b31e45..12092d344ce8 100644
--- a/arch/arm/boot/dts/tegra114-tn7.dts
+++ b/arch/arm/boot/dts/tegra114-tn7.dts
@@ -28,7 +28,8 @@
};
};
- memory {
+ memory@80000000 {
+ device_type = "memory";
/* memory >= 0x37e00000 is reserved for firmware usage */
reg = <0x80000000 0x37e00000>;
};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 0e4a13295d8a..b917784d3f97 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -5,11 +5,11 @@
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
-
/ {
compatible = "nvidia,tegra114";
interrupt-parent = <&lic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
host1x@50000000 {
compatible = "nvidia,tegra114-host1x", "simple-bus";
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
index bb67edb016c5..80b52c612891 100644
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -15,7 +15,8 @@
compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
"nvidia,tegra124";
- memory {
+ memory@0 {
+ device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 65a2161b9b8e..3ca7601cafe9 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -50,7 +50,8 @@
model = "Toradex Apalis TK1";
compatible = "toradex,apalis-tk1", "nvidia,tegra124";
- memory {
+ memory@0 {
+ device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 6dbcf84dafbc..8d9e6ee6c6a7 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -24,7 +24,8 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
+ device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index 3609367037a6..15a2b0e3237e 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -13,7 +13,8 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
+ device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 89bcc178994d..241cdc4b6600 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -18,7 +18,8 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
+ device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 174092bfac90..df1642876a4c 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -7,8 +7,6 @@
#include <dt-bindings/reset/tegra124-car.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
-#include "skeleton.dtsi"
-
/ {
compatible = "nvidia,tegra124";
interrupt-parent = <&lic>;
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 5c202b3e3bb1..305efb275b48 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -10,7 +10,8 @@
rtc1 = "/rtc@7000e000";
};
- memory {
+ memory@0 {
+ device_type = "memory";
reg = <0x00000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 628a55a9318b..5009a55ae15c 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -18,7 +18,8 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
+ device_type = "memory";
reg = <0x00000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 30436969adc0..e794ac5442ef 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -19,7 +19,8 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
+ device_type = "memory";
reg = <0x00000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 284aae351ff2..6cb832cfa4f3 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -18,7 +18,8 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
+ device_type = "memory";
reg = <0x00000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 872046d48709..6ceb1228fed3 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -15,7 +15,8 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
+ device_type = "memory";
reg = <0x00000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index d55c6b240a30..3f94be3da9e5 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -18,7 +18,8 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
+ device_type = "memory";
reg = <0x00000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index ee3fbf941e79..c897a90289bc 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -18,7 +18,8 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
+ device_type = "memory";
reg = <0x00000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 0a7136462a1a..290ebbeb210f 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,11 +4,14 @@
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
-
/ {
compatible = "nvidia,tegra20";
interrupt-parent = <&lic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen { };
+ aliases { };
iram@40000000 {
compatible = "mmio-sram";
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index d1d21ec2a844..184f60c720fa 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -10,6 +10,11 @@
model = "Toradex Apalis T30";
compatible = "toradex,apalis_t30", "nvidia,tegra30";
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0>;
+ };
+
pcie@3000 {
avdd-pexa-supply = <&vdd2_reg>;
vdd-pexa-supply = <&vdd2_reg>;
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index ae52a5039506..72369877d284 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -17,7 +17,8 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@80000000 {
+ device_type = "memory";
reg = <0x80000000 0x7ff00000>;
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 92a9740c533f..24c04d4c335d 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -40,7 +40,8 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@80000000 {
+ device_type = "memory";
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index c44d8c40c410..cc46cedf80b9 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -10,7 +10,8 @@
model = "Toradex Colibri T30";
compatible = "toradex,colibri_t30", "nvidia,tegra30";
- memory {
+ memory@80000000 {
+ device_type = "memory";
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index a110cf84d85f..4383f0fd789d 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -5,11 +5,14 @@
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
-
/ {
compatible = "nvidia,tegra30";
interrupt-parent = <&lic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen { };
+ aliases { };
pcie@3000 {
compatible = "nvidia,tegra30-pcie";
--
2.7.4
^ permalink raw reply related
* [PATCH v4 0/3] ARM: dts: tegra: Add 256 MB Colibri-T20 and cleanups
From: Krzysztof Kozlowski @ 2018-05-15 14:41 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Thierry Reding, Jonathan Hunter,
devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Stefan Agner, Lucas Stach, Krzysztof Kozlowski
Hi,
Changes since v3:
1. Patch 3/3: Just reduce the memory of existing DTSI
(suggested by Marcel).
Best regards,
Krzysztof
Krzysztof Kozlowski (3):
ARM: dts: tegra: Remove skeleton.dtsi and fix DTC warnings for /memory
ARM: dts: tegra: Fix unit_address_vs_reg and
avoid_unnecessary_addr_size DTC warnings
ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules
arch/arm/boot/dts/tegra114-dalmore.dts | 3 ++-
arch/arm/boot/dts/tegra114-roth.dts | 3 ++-
arch/arm/boot/dts/tegra114-tn7.dts | 3 ++-
arch/arm/boot/dts/tegra114.dtsi | 4 ++--
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 3 ++-
arch/arm/boot/dts/tegra124-apalis.dtsi | 3 ++-
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 3 ++-
arch/arm/boot/dts/tegra124-nyan.dtsi | 3 ++-
arch/arm/boot/dts/tegra124-venice2.dts | 3 ++-
arch/arm/boot/dts/tegra124.dtsi | 2 --
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 12 +++++++++---
arch/arm/boot/dts/tegra20-harmony.dts | 3 ++-
arch/arm/boot/dts/tegra20-iris-512.dts | 2 +-
arch/arm/boot/dts/tegra20-paz00.dts | 3 ++-
arch/arm/boot/dts/tegra20-seaboard.dts | 3 ++-
arch/arm/boot/dts/tegra20-tamonten.dtsi | 3 ++-
arch/arm/boot/dts/tegra20-trimslice.dts | 3 ++-
arch/arm/boot/dts/tegra20-ventana.dts | 3 ++-
arch/arm/boot/dts/tegra20.dtsi | 7 +++++--
arch/arm/boot/dts/tegra30-apalis.dtsi | 9 ++++++---
arch/arm/boot/dts/tegra30-beaver.dts | 6 ++----
arch/arm/boot/dts/tegra30-cardhu.dtsi | 3 ++-
arch/arm/boot/dts/tegra30-colibri.dtsi | 5 ++---
arch/arm/boot/dts/tegra30.dtsi | 7 +++++--
24 files changed, 62 insertions(+), 37 deletions(-)
--
2.7.4
^ permalink raw reply
* Re: [PATCH v8 0/5] clk: meson-axg: Add AO Cloclk and Reset driver
From: Jerome Brunet @ 2018-05-15 14:40 UTC (permalink / raw)
To: Yixun Lan, Neil Armstrong, Kevin Hilman, Carlo Caione
Cc: Rob Herring, Michael Turquette, Stephen Boyd, Philipp Zabel,
Qiufang Dai, linux-amlogic, linux-clk, linux-arm-kernel,
linux-kernel, devicetree
In-Reply-To: <20180503132624.78453-1-yixun.lan@amlogic.com>
On Thu, 2018-05-03 at 21:26 +0800, Yixun Lan wrote:
> This patch try to add AO clock and Reset driver for Amlogic's
> Meson-AXG SoC.
>
> patch 1: factor the common code into a dedicated file
> patch 2-4: add the aoclk driver for AXG SoC
> patch 5: drop unnecessary clock flags
>
> changes since v7 at [8]:
> - drop the 'drop CLK_IGNORE_UNUSED flag' patch
> to avoid circle dependencies
> - fix Philip's Ack on patch 3
>
> changes since v6 at [7]:
> - fix over 80 chars chechpatch error
> - add Philip's Ack on patch 5
> - drop extra end of newline
>
> changes since v5 at [6]:
> - drop unnecessary header files
> - add 'axg_aoclk' prefix to clk driver, make them more consistent
> - add missing end new line..
>
> changes since v4 at [5]:
> - fix return err
> - introduce CONFIG_COMMON_CLK_MESON_AO
> - format/style minor fix
>
> changes since v3 at [4]:
> - add 'const' contraint to the read-only data
> - switch to devm_of_clk_add_hw_provider API
> - check return value of devm_reset_controller_register
>
> changes since v2 at [2]:
> - rework meson_aoclkc_probe() which leverage the of_match_data
> - merge patch 5-6 into this series
> - seperate DTS patch, will send to Kevin Hilman independently
>
> changes since v1 at [0]:
> - rebase to clk-meson's branch 'next/drivers' [1]
> - fix license, update to BSD-3-Clause
> - drop un-used include header file
>
> [0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan@amlogic.com
> [1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
> [2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan@amlogic.com
> [3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan@amlogic.com
> [4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan@amlogic.com
> [5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan@amlogic.com
> [6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan@amlogic.com
> [7] https://lkml.kernel.org/r/20180419135426.155794-1-yixun.lan@amlogic.com
> [8] https://lkml.kernel.org/r/20180426084437.192394-1-yixun.lan@amlogic.com
>
>
> Qiufang Dai (1):
> clk: meson-axg: Add AO Clock and Reset controller driver
>
> Yixun Lan (4):
> clk: meson: aoclk: refactor common code into dedicated file
> dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
> dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
> clk: meson: drop CLK_SET_RATE_PARENT flag
Applied
>
> .../bindings/clock/amlogic,gxbb-aoclkc.txt | 1 +
> drivers/clk/meson/Kconfig | 8 +
> drivers/clk/meson/Makefile | 3 +-
> drivers/clk/meson/axg-aoclk.c | 164 ++++++++++++++++++
> drivers/clk/meson/axg-aoclk.h | 29 ++++
> drivers/clk/meson/gxbb-aoclk.c | 96 ++++------
> drivers/clk/meson/gxbb-aoclk.h | 5 +
> drivers/clk/meson/meson-aoclk.c | 81 +++++++++
> drivers/clk/meson/meson-aoclk.h | 34 ++++
> include/dt-bindings/clock/axg-aoclkc.h | 26 +++
> include/dt-bindings/reset/axg-aoclkc.h | 20 +++
> 11 files changed, 403 insertions(+), 64 deletions(-)
> create mode 100644 drivers/clk/meson/axg-aoclk.c
> create mode 100644 drivers/clk/meson/axg-aoclk.h
> create mode 100644 drivers/clk/meson/meson-aoclk.c
> create mode 100644 drivers/clk/meson/meson-aoclk.h
> create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
> create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
>
^ permalink raw reply
* Re: [PATCH 0/4] Add DesignWare EP support
From: Joao Pinto @ 2018-05-15 14:32 UTC (permalink / raw)
To: Gustavo Pimentel, bhelgaas, lorenzo.pieralisi, Joao.Pinto,
jingoohan1, kishon, robh+dt, mark.rutland
Cc: linux-pci, linux-kernel, devicetree
In-Reply-To: <cover.1526368368.git.gustavo.pimentel@synopsys.com>
Hi Gustavo,
Às 8:13 AM de 5/15/2018, Gustavo Pimentel escreveu:
> The PCIe controller dual mode is capable of operating in RC mode as well
> as EP mode by configuration option. Till now only RC mode was supported,
> with this patch is add EP support to the DesignWare driver.
>
> Gustavo Pimentel (4):
> bindings: PCI: designware: Example update
> PCI: dwc: Add support for EP mode
> bindings: PCI: designware: Add support for EP in DesignWare driver
> misc: pci_endpoint_test: Add DesignWare EP entry
>
> .../devicetree/bindings/pci/designware-pcie.txt | 24 +++-
> drivers/misc/pci_endpoint_test.c | 1 +
> drivers/pci/dwc/Kconfig | 41 ++++--
> drivers/pci/dwc/pcie-designware-ep.c | 3 +
> drivers/pci/dwc/pcie-designware-plat.c | 149 +++++++++++++++++++--
> drivers/pci/endpoint/functions/pci-epf-test.c | 7 +
> include/linux/pci-epc.h | 8 ++
> 7 files changed, 206 insertions(+), 27 deletions(-)
>
Thanks for this patch-set.
Reviewed-by: Joao Pinto <jpinto@synopsys.com>
^ permalink raw reply
* Re: [PATCH] Input: ili251x - add support for Ilitek ILI251x touchscreens
From: Philipp Puschmann @ 2018-05-15 14:31 UTC (permalink / raw)
To: Dmitry Torokhov
Cc: robh, mark.rutland, rydberg, andi, linux-input, devicetree,
linux-kernel
In-Reply-To: <20180509224152.GB91762@dtor-ws>
Hi Dmitry,
hi Rob,
hi Andi,
thank you for your replies and your helpful hints. I will take care of them and
send a V2 of this driver + dt-bindings soon. As i have a working version of this
driver working on it has not a very priority so it may need some time.
Most of your points are correct and don't need further discussion. For the pressure
data i'm unsure, see below.
Am 10.05.2018 um 00:41 schrieb Dmitry Torokhov:
>> The usage of pressure is optional. Touchscreens may deliver constant
>> and so useless pressure data.
>
> Is it dependent on model or what? I would much rather we did not have DT
> property for this.
I don't know. My touchscreen here delivers a constant (useless) pressure of
10. So my chip delivers "something". I'm not sure if the chip always delivers
no real pressure data or if this is dependent from the wiring.
This was the reason i put it in the dt.
Thanks
Philipp
--
Bitte beachten Sie unsere neue Adresse am Göttinger Standort:
emlix GmbH, Gothaer Platz 3, 37083 Göttingen
Philipp Puschmann, emlix GmbH, http://www.emlix.com
Fon +49 551 30664-0, Fax +49 551 30664-11
Gothaer Platz 3, 37083 Göttingen, Germany
Sitz der Gesellschaft: Göttingen, Amtsgericht Goettingen HR B 3160
Geschaeftsführung: Heike Jordan, Dr. Uwe Kracke
Ust-IdNr.: DE 205 198 055
emlix - smart embedded open source
^ permalink raw reply
* [patch v21 4/4] Documentation: jtag: Add ABI documentation
From: Oleksandr Shamray @ 2018-05-15 14:21 UTC (permalink / raw)
To: gregkh, arnd
Cc: linux-kernel, linux-arm-kernel, devicetree, openbmc, joel, jiri,
tklauser, linux-serial, vadimp, system-sw-low-level, robh+dt,
openocd-devel-owner, linux-api, davem, mchehab, Oleksandr Shamray
In-Reply-To: <1526394095-5069-1-git-send-email-oleksandrs@mellanox.com>
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
v19->v20
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- Fix JTAG doccumentation
v18->v19
Pavel Machek <pavel@ucw.cz>
- Added JTAG doccumentation to Documentation/jtag
v17->v18
v16->v17
v15->v16
v14->v15
v13->v14
v12->v13
v11->v12
Tobias Klauser <tklauser@distanz.ch>
- rename /Documentation/ABI/testing/jatg-dev -> jtag-dev
- Typo: s/interfase/interface
v10->v11
v9->v10
Fixes added by Oleksandr:
- change jtag-cdev to jtag-dev in documentation
- update Kernel Version and Date in jtag-dev documentation;
v8->v9
v7->v8
v6->v7
Comments pointed by Pavel Machek <pavel@ucw.cz>
- Added jtag-cdev documentation to Documentation/ABI/testing folder
---
Documentation/ABI/testing/jtag-dev | 27 +++++++++
Documentation/jtag/overview | 28 +++++++++
Documentation/jtag/transactions | 109 ++++++++++++++++++++++++++++++++++++
3 files changed, 164 insertions(+), 0 deletions(-)
create mode 100644 Documentation/ABI/testing/jtag-dev
create mode 100644 Documentation/jtag/overview
create mode 100644 Documentation/jtag/transactions
diff --git a/Documentation/ABI/testing/jtag-dev b/Documentation/ABI/testing/jtag-dev
new file mode 100644
index 0000000..4325316
--- /dev/null
+++ b/Documentation/ABI/testing/jtag-dev
@@ -0,0 +1,27 @@
+What: /dev/jtag[0-9]+
+Date: May 2018
+KernelVersion: 4.18
+Contact: oleksandrs@mellanox.com
+Description:
+ The misc device files /dev/jtag* are the interface
+ between JTAG master interface and userspace.
+
+ The ioctl(2)-based ABI is defined and documented in
+ [include/uapi]<linux/jtag.h>.
+
+ The following file operations are supported:
+
+ open(2)
+ The argument flag currently support only one access
+ mode O_RDWR.
+
+ ioctl(2)
+ Initiate various actions.
+ See the inline documentation in [include/uapi]<linux/jtag.h>
+ for descriptions of all ioctls.
+
+ close(2)
+ Stops and free up the I/O contexts that was associated
+ with the file descriptor.
+
+Users: TBD
diff --git a/Documentation/jtag/overview b/Documentation/jtag/overview
new file mode 100644
index 0000000..a86f188
--- /dev/null
+++ b/Documentation/jtag/overview
@@ -0,0 +1,28 @@
+Linux kernel JTAG support
+=========================
+
+The JTAG is an industry standard for verifying hardware
+JTAG provides access to many logic signals of a complex integrated circuit,
+including the device pins.
+
+A JTAG interface is a special interface added to a chip.
+Depending on the version of JTAG, two, four, or five pins are added.
+
+The connector pins are:
+ TDI (Test Data In)
+ TDO (Test Data Out)
+ TCK (Test Clock)
+ TMS (Test Mode Select)
+ TRST (Test Reset) optional.
+
+JTAG interface is designed to have two parts - basic core driver and
+hardware specific driver. The basic driver introduces a general interface
+which is not dependent of specific hardware. It provides communication
+between user space and hardware specific driver.
+Each JTAG device is represented as a char device from (jtag0, jtag1, ...).
+Access to a JTAG device is performed through IOCTL calls.
+
+Call flow example:
+User: open -> /dev/jatgX
+User: ioctl -> /dev/jtagX -> JTAG core driver -> JTAG hw specific driver
+User: close -> /dev/jatgX
diff --git a/Documentation/jtag/transactions b/Documentation/jtag/transactions
new file mode 100644
index 0000000..6a857c8
--- /dev/null
+++ b/Documentation/jtag/transactions
@@ -0,0 +1,109 @@
+The JTAG API
+=============
+
+JTAG master devices can be accessed through a character misc-device.
+Each JTAG master interface can be accessed by using /dev/jtagN
+
+JTAG system calls set:
+- SIR (Scan Instruction Register, IEEE 1149.1 Instruction Register scan);
+- SDR (Scan Data Register, IEEE 1149.1 Data Register scan);
+- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
+number of clocks.
+
+open(), close()
+-------
+open() opens JTAG device. Only one open operation per JTAG device
+can be performed. Two or more open for one device will return error
+
+Open/Close device:
+- open("/dev/jtag0", O_RDWR);
+- close(jtag_fd');
+
+ioctl()
+-------
+All access operations to JTAG devices performed through ioctl interface.
+The IOCTL interface supports this requests:
+ JTAG_IOCRUNTEST - Force JTAG state machine to RUN_TEST/IDLE state
+ JTAG_SIOCFREQ - Set JTAG TCK frequency
+ JTAG_GIOCFREQ - Get JTAG TCK frequency
+ JTAG_IOCXFER - send JTAG data Xfer
+ JTAG_GIOCSTATUS - get current JTAG TAP status
+ JTAG_SIOCMODE - set JTAG mode flags.
+
+JTAG_SIOCFREQ, JTAG_GIOCFREQ
+------
+Set/Get JTAG clock speed:
+
+ unsigned int jtag_fd;
+ ioctl(jtag_fd, JTAG_SIOCFREQ, &frq);
+ ioctl(jtag_fd, JTAG_GIOCFREQ, &frq);
+
+JTAG_IOCRUNTEST
+------
+Force JTAG state machine to RUN_TEST/IDLE state
+
+struct jtag_run_test_idle {
+ __u8 reset;
+ __u8 endstate;
+ __u8 tck;
+};
+
+reset: 0 - run IDLE/PAUSE from current state
+ 1 - go through TEST_LOGIC/RESET state before IDLE/PAUSE
+endstate: completion flag
+tck: clock counter
+
+Example:
+ struct jtag_run_test_idle runtest;
+
+ runtest.endstate = JTAG_STATE_IDLE;
+ runtest.reset = 0;
+ runtest.tck = data_p->tck;
+ usleep(25 * 1000);
+ ioctl(jtag_fd, JTAG_IOCRUNTEST, &runtest);
+
+JTAG_IOCXFER
+------
+Send SDR/SIR transaction
+
+struct jtag_xfer {
+ __u8 type;
+ __u8 direction;
+ __u8 endstate;
+ __u8 padding;
+ __u32 length;
+ __u64 tdio;
+};
+
+type: transfer type - JTAG_SIR_XFER/JTAG_SDR_XFER
+direction: xfer direction - JTAG_SIR_XFER/JTAG_SDR_XFER,
+length: xfer data len in bits
+tdio : xfer data array
+endstate: xfer end state after transaction finish
+ can be: JTAG_STATE_IDLE/JTAG_STATE_PAUSEIR/JTAG_STATE_PAUSEDR
+
+Example:
+ struct jtag_xfer xfer;
+ static char buf[64];
+ static unsigned int buf_len = 0;
+ [...]
+ xfer.type = JTAG_SDR_XFER;
+ xfer.tdio = (__u64)buf;
+ xfer.length = buf_len;
+ xfer.endstate = JTAG_STATE_IDLE;
+
+ if (is_read)
+ xfer.direction = JTAG_READ_XFER;
+ else
+ xfer.direction = JTAG_WRITE_XFER;
+
+ ioctl(jtag_fd, JTAG_IOCXFER, &xfer);
+
+JTAG_SIOCMODE
+------
+If hw driver can support different running modes you can change it.
+
+Example:
+ unsigned int mode;
+ mode = JTAG_XFER_HW_MODE;
+ ioctl(jtag_fd, JTAG_SIOCMODE, &mode);
--
1.7.1
^ permalink raw reply related
* [patch v21 3/4] Documentation: jtag: Add bindings for Aspeed SoC 24xx and 25xx families JTAG master driver
From: Oleksandr Shamray @ 2018-05-15 14:21 UTC (permalink / raw)
To: gregkh, arnd
Cc: linux-kernel, linux-arm-kernel, devicetree, openbmc, joel, jiri,
tklauser, linux-serial, vadimp, system-sw-low-level, robh+dt,
openocd-devel-owner, linux-api, davem, mchehab, Oleksandr Shamray,
Jiri Pirko
In-Reply-To: <1526394095-5069-1-git-send-email-oleksandrs@mellanox.com>
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v19->v20
v18->v19
v17->v18
v16->v17
v15->v16
Comments pointed by Joel Stanley <joel.stan@gmail.com>
- change clocks = <&clk_apb> to proper clocks = <&syscon ASPEED_CLK_APB>
- add reset descriptions in bndings file
v14->v15
v13->v14
v12->v13
v11->v12
v10->v11
v9->v10
v8->v9
v7->v8
Comments pointed by pointed by Joel Stanley <joel.stan@gmail.com>
- Change compatible string to ast2400 and ast2000
V6->v7
Comments pointed by Tobias Klauser <tklauser@distanz.ch>
- Fix spell "Doccumentation" -> "Documentation"
v5->v6
Comments pointed by Tobias Klauser <tklauser@distanz.ch>
- Small nit: s/documentation/Documentation/
v4->v5
V3->v4
Comments pointed by Rob Herring <robh@kernel.org>
- delete unnecessary "status" and "reg-shift" descriptions in
bndings file
v2->v3
Comments pointed by Rob Herring <robh@kernel.org>
- split Aspeed jtag driver and binding to sepatrate patches
- delete unnecessary "status" and "reg-shift" descriptions in
bndings file
---
.../devicetree/bindings/jtag/aspeed-jtag.txt | 22 ++++++++++++++++++++
1 files changed, 22 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/jtag/aspeed-jtag.txt
diff --git a/Documentation/devicetree/bindings/jtag/aspeed-jtag.txt b/Documentation/devicetree/bindings/jtag/aspeed-jtag.txt
new file mode 100644
index 0000000..7c36eb6
--- /dev/null
+++ b/Documentation/devicetree/bindings/jtag/aspeed-jtag.txt
@@ -0,0 +1,22 @@
+Aspeed JTAG driver for ast2400 and ast2500 SoC
+
+Required properties:
+- compatible: Should be one of
+ - "aspeed,ast2400-jtag"
+ - "aspeed,ast2500-jtag"
+- reg contains the offset and length of the JTAG memory
+ region
+- clocks root clock of bus, should reference the APB
+ clock in the second cell
+- resets phandle to reset controller with the reset number in
+ the second cell
+- interrupts should contain JTAG controller interrupt
+
+Example:
+jtag: jtag@1e6e4000 {
+ compatible = "aspeed,ast2500-jtag";
+ reg = <0x1e6e4000 0x1c>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_JTAG_MASTER>;
+ interrupts = <43>;
+};
--
1.7.1
^ permalink raw reply related
* [patch v21 2/4] drivers: jtag: Add Aspeed SoC 24xx and 25xx families JTAG master driver
From: Oleksandr Shamray @ 2018-05-15 14:21 UTC (permalink / raw)
To: gregkh, arnd
Cc: linux-kernel, linux-arm-kernel, devicetree, openbmc, joel, jiri,
tklauser, linux-serial, vadimp, system-sw-low-level, robh+dt,
openocd-devel-owner, linux-api, davem, mchehab, Oleksandr Shamray,
Jiri Pirko
In-Reply-To: <1526394095-5069-1-git-send-email-oleksandrs@mellanox.com>
Driver adds support of Aspeed 2500/2400 series SOC JTAG master controller.
Driver implements the following jtag ops:
- freq_get;
- freq_set;
- status_get;
- idle;
- xfer;
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
Acked-by: Joel Stanley <joel@jms.id.au>
---
v19->v20
Notifications from kbuild test robot <lkp@intel.com>
- add static declaration to 'aspeed_jtag_init' and
'aspeed_jtag_deinit' functions
v18->v19
v17->v18
v16->v17
v15->v16
Comments pointed by Joel Stanley <joel.stan@gmail.com>
- Add reset_control on Jtag init/deinit
v14->v15
Comments pointed by Joel Stanley <joel.stan@gmail.com>
- Add ARCH_ASPEED || COMPILE_TEST to Kconfig
- remove unused offset variable
- remove "aspeed_jtag" from dev_err and dev_dbg messages
- change clk_prepare_enable initialisation order
v13->v14
Comments pointed by Philippe Ombredanne <pombredanne@nexb.com>
- Change style of head block comment from /**/ to //
v12->v13
Comments pointed by Philippe Ombredanne <pombredanne@nexb.com>
- Change jtag-aspeed.c licence type to
SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
and reorder line with license in description
Comments pointed by Kun Yi <kunyi@google.com>
- Changed capability check for aspeed,ast2400-jtag/ast200-jtag
v11->v12
Comments pointed by Chip Bilbrey <chip@bilbrey.org>
- Remove access mode from xfer and idle transactions
- Add new ioctl JTAG_SIOCMODE for set hw mode
v10->v11
v9->v10
V8->v9
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- add *data parameter to xfer function prototype
v7->v8
Comments pointed by Joel Stanley <joel.stan@gmail.com>
- aspeed_jtag_init replace goto to return;
- change input variables type from __u32 to u32
in functios freq_get, freq_set, status_get
- change sm_ variables type from char to u8
- in jatg_init add disable clocks on error case
- remove release_mem_region on error case
- remove devm_free_irq on jtag_deinit
- Fix misspelling Disabe/Disable
- Change compatible string to ast2400 and ast2000
v6->v7
Notifications from kbuild test robot <lkp@intel.com>
- Add include <linux/types.h> to jtag-asapeed.c
v5->v6
v4->v5
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- Added HAS_IOMEM dependence in Kconfig to avoid
"undefined reference to `devm_ioremap_resource'" error,
because in some arch this not supported
v3->v4
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- change transaction pointer tdio type to __u64
- change internal status type from enum to __u32
v2->v3
v1->v2
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- change license type from GPLv2/BSD to GPLv2
Comments pointed by Neil Armstrong <narmstrong@baylibre.com>
- Add clk_prepare_enable/clk_disable_unprepare in clock init/deinit
- Change .compatible to soc-specific compatible names
aspeed,aspeed4000-jtag/aspeed5000-jtag
- Added dt-bindings
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- Reorder functions and removed the forward declarations
- Add static const qualifier to state machine states transitions
- Change .compatible to soc-specific compatible names
aspeed,aspeed4000-jtag/aspeed5000-jtag
- Add dt-bindings
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- Change module name jtag-aspeed in description in Kconfig
Comments pointed by kbuild test robot <lkp@intel.com>
- Remove invalid include <asm/mach-types.h>
- add resource_size instead of calculation
---
drivers/jtag/Kconfig | 14 +
drivers/jtag/Makefile | 1 +
drivers/jtag/jtag-aspeed.c | 786 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 801 insertions(+), 0 deletions(-)
create mode 100644 drivers/jtag/jtag-aspeed.c
diff --git a/drivers/jtag/Kconfig b/drivers/jtag/Kconfig
index 43eb9a4..6b43ac8 100644
--- a/drivers/jtag/Kconfig
+++ b/drivers/jtag/Kconfig
@@ -16,3 +16,17 @@ menuconfig JTAG
To compile this driver as a module, choose M here: the module will
be called jtag.
+
+menuconfig JTAG_ASPEED
+ tristate "Aspeed SoC JTAG controller support"
+ depends on JTAG && HAS_IOMEM
+ depends on ARCH_ASPEED || COMPILE_TEST
+ help
+ This provides a support for Aspeed JTAG device, equipped on
+ Aspeed SoC 24xx and 25xx families. Drivers allows programming
+ of hardware devices, connected to SoC through the JTAG interface.
+
+ If you want this support, you should say Y here.
+
+ To compile this driver as a module, choose M here: the module will
+ be called jtag-aspeed.
diff --git a/drivers/jtag/Makefile b/drivers/jtag/Makefile
index af37493..04a855e 100644
--- a/drivers/jtag/Makefile
+++ b/drivers/jtag/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_JTAG) += jtag.o
+obj-$(CONFIG_JTAG_ASPEED) += jtag-aspeed.o
diff --git a/drivers/jtag/jtag-aspeed.c b/drivers/jtag/jtag-aspeed.c
new file mode 100644
index 0000000..2d22de0
--- /dev/null
+++ b/drivers/jtag/jtag-aspeed.c
@@ -0,0 +1,786 @@
+// SPDX-License-Identifier: GPL-2.0
+// drivers/jtag/aspeed-jtag.c
+//
+// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
+// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/jtag.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <uapi/linux/jtag.h>
+
+#define ASPEED_JTAG_DATA 0x00
+#define ASPEED_JTAG_INST 0x04
+#define ASPEED_JTAG_CTRL 0x08
+#define ASPEED_JTAG_ISR 0x0C
+#define ASPEED_JTAG_SW 0x10
+#define ASPEED_JTAG_TCK 0x14
+#define ASPEED_JTAG_EC 0x18
+
+#define ASPEED_JTAG_DATA_MSB 0x01
+#define ASPEED_JTAG_DATA_CHUNK_SIZE 0x20
+
+/* ASPEED_JTAG_CTRL: Engine Control */
+#define ASPEED_JTAG_CTL_ENG_EN BIT(31)
+#define ASPEED_JTAG_CTL_ENG_OUT_EN BIT(30)
+#define ASPEED_JTAG_CTL_FORCE_TMS BIT(29)
+#define ASPEED_JTAG_CTL_INST_LEN(x) ((x) << 20)
+#define ASPEED_JTAG_CTL_LASPEED_INST BIT(17)
+#define ASPEED_JTAG_CTL_INST_EN BIT(16)
+#define ASPEED_JTAG_CTL_DR_UPDATE BIT(10)
+#define ASPEED_JTAG_CTL_DATA_LEN(x) ((x) << 4)
+#define ASPEED_JTAG_CTL_LASPEED_DATA BIT(1)
+#define ASPEED_JTAG_CTL_DATA_EN BIT(0)
+
+/* ASPEED_JTAG_ISR : Interrupt status and enable */
+#define ASPEED_JTAG_ISR_INST_PAUSE BIT(19)
+#define ASPEED_JTAG_ISR_INST_COMPLETE BIT(18)
+#define ASPEED_JTAG_ISR_DATA_PAUSE BIT(17)
+#define ASPEED_JTAG_ISR_DATA_COMPLETE BIT(16)
+#define ASPEED_JTAG_ISR_INST_PAUSE_EN BIT(3)
+#define ASPEED_JTAG_ISR_INST_COMPLETE_EN BIT(2)
+#define ASPEED_JTAG_ISR_DATA_PAUSE_EN BIT(1)
+#define ASPEED_JTAG_ISR_DATA_COMPLETE_EN BIT(0)
+#define ASPEED_JTAG_ISR_INT_EN_MASK GENMASK(3, 0)
+#define ASPEED_JTAG_ISR_INT_MASK GENMASK(19, 16)
+
+/* ASPEED_JTAG_SW : Software Mode and Status */
+#define ASPEED_JTAG_SW_MODE_EN BIT(19)
+#define ASPEED_JTAG_SW_MODE_TCK BIT(18)
+#define ASPEED_JTAG_SW_MODE_TMS BIT(17)
+#define ASPEED_JTAG_SW_MODE_TDIO BIT(16)
+
+/* ASPEED_JTAG_TCK : TCK Control */
+#define ASPEED_JTAG_TCK_DIVISOR_MASK GENMASK(10, 0)
+#define ASPEED_JTAG_TCK_GET_DIV(x) ((x) & ASPEED_JTAG_TCK_DIVISOR_MASK)
+
+/* ASPEED_JTAG_EC : Controller set for go to IDLE */
+#define ASPEED_JTAG_EC_GO_IDLE BIT(0)
+
+#define ASPEED_JTAG_IOUT_LEN(len) (ASPEED_JTAG_CTL_ENG_EN |\
+ ASPEED_JTAG_CTL_ENG_OUT_EN |\
+ ASPEED_JTAG_CTL_INST_LEN(len))
+
+#define ASPEED_JTAG_DOUT_LEN(len) (ASPEED_JTAG_CTL_ENG_EN |\
+ ASPEED_JTAG_CTL_ENG_OUT_EN |\
+ ASPEED_JTAG_CTL_DATA_LEN(len))
+
+#define ASPEED_JTAG_TCK_WAIT 10
+#define ASPEED_JTAG_RESET_CNTR 10
+
+#define ASPEED_JTAG_NAME "jtag-aspeed"
+
+struct aspeed_jtag {
+ void __iomem *reg_base;
+ struct device *dev;
+ struct clk *pclk;
+ enum jtag_endstate status;
+ int irq;
+ struct reset_control *rst;
+ u32 flag;
+ wait_queue_head_t jtag_wq;
+ u32 mode;
+};
+
+static char *end_status_str[] = {"idle", "ir pause", "drpause"};
+
+static u32 aspeed_jtag_read(struct aspeed_jtag *aspeed_jtag, u32 reg)
+{
+ return readl(aspeed_jtag->reg_base + reg);
+}
+
+static void
+aspeed_jtag_write(struct aspeed_jtag *aspeed_jtag, u32 val, u32 reg)
+{
+ writel(val, aspeed_jtag->reg_base + reg);
+}
+
+static int aspeed_jtag_freq_set(struct jtag *jtag, u32 freq)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+ unsigned long apb_frq;
+ u32 tck_val;
+ u16 div;
+
+ apb_frq = clk_get_rate(aspeed_jtag->pclk);
+ div = (apb_frq % freq == 0) ? (apb_frq / freq) - 1 : (apb_frq / freq);
+ tck_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_TCK);
+ aspeed_jtag_write(aspeed_jtag,
+ (tck_val & ASPEED_JTAG_TCK_DIVISOR_MASK) | div,
+ ASPEED_JTAG_TCK);
+ return 0;
+}
+
+static int aspeed_jtag_freq_get(struct jtag *jtag, u32 *frq)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+ u32 pclk;
+ u32 tck;
+
+ pclk = clk_get_rate(aspeed_jtag->pclk);
+ tck = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_TCK);
+ *frq = pclk / (ASPEED_JTAG_TCK_GET_DIV(tck) + 1);
+
+ return 0;
+}
+
+static int aspeed_jtag_mode_set(struct jtag *jtag, u32 mode)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ aspeed_jtag->mode = mode;
+ return 0;
+}
+
+static void aspeed_jtag_sw_delay(struct aspeed_jtag *aspeed_jtag, int cnt)
+{
+ int i;
+
+ for (i = 0; i < cnt; i++)
+ aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_SW);
+}
+
+static char aspeed_jtag_tck_cycle(struct aspeed_jtag *aspeed_jtag,
+ u8 tms, u8 tdi)
+{
+ char tdo = 0;
+
+ /* TCK = 0 */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ (tms * ASPEED_JTAG_SW_MODE_TMS) |
+ (tdi * ASPEED_JTAG_SW_MODE_TDIO), ASPEED_JTAG_SW);
+
+ aspeed_jtag_sw_delay(aspeed_jtag, ASPEED_JTAG_TCK_WAIT);
+
+ /* TCK = 1 */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ ASPEED_JTAG_SW_MODE_TCK |
+ (tms * ASPEED_JTAG_SW_MODE_TMS) |
+ (tdi * ASPEED_JTAG_SW_MODE_TDIO), ASPEED_JTAG_SW);
+
+ if (aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_SW) &
+ ASPEED_JTAG_SW_MODE_TDIO)
+ tdo = 1;
+
+ aspeed_jtag_sw_delay(aspeed_jtag, ASPEED_JTAG_TCK_WAIT);
+
+ /* TCK = 0 */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ (tms * ASPEED_JTAG_SW_MODE_TMS) |
+ (tdi * ASPEED_JTAG_SW_MODE_TDIO), ASPEED_JTAG_SW);
+ return tdo;
+}
+
+static void aspeed_jtag_wait_instruction_pause(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq, aspeed_jtag->flag &
+ ASPEED_JTAG_ISR_INST_PAUSE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_INST_PAUSE;
+}
+
+static void
+aspeed_jtag_wait_instruction_complete(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq, aspeed_jtag->flag &
+ ASPEED_JTAG_ISR_INST_COMPLETE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_INST_COMPLETE;
+}
+
+static void
+aspeed_jtag_wait_data_pause_complete(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq, aspeed_jtag->flag &
+ ASPEED_JTAG_ISR_DATA_PAUSE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_DATA_PAUSE;
+}
+
+static void aspeed_jtag_wait_data_complete(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq, aspeed_jtag->flag &
+ ASPEED_JTAG_ISR_DATA_COMPLETE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_DATA_COMPLETE;
+}
+
+static void aspeed_jtag_sm_cycle(struct aspeed_jtag *aspeed_jtag, const u8 *tms,
+ int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ aspeed_jtag_tck_cycle(aspeed_jtag, tms[i], 0);
+}
+
+static void aspeed_jtag_run_test_idle_sw(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_run_test_idle *runtest)
+{
+ static const u8 sm_pause_irpause[] = {1, 1, 1, 1, 0, 1, 0};
+ static const u8 sm_pause_drpause[] = {1, 1, 1, 0, 1, 0};
+ static const u8 sm_idle_irpause[] = {1, 1, 0, 1, 0};
+ static const u8 sm_idle_drpause[] = {1, 0, 1, 0};
+ static const u8 sm_pause_idle[] = {1, 1, 0};
+ int i;
+
+ /* SW mode from idle/pause-> to pause/idle */
+ if (runtest->reset) {
+ for (i = 0; i < ASPEED_JTAG_RESET_CNTR; i++)
+ aspeed_jtag_tck_cycle(aspeed_jtag, 1, 0);
+ }
+
+ switch (aspeed_jtag->status) {
+ case JTAG_STATE_IDLE:
+ switch (runtest->endstate) {
+ case JTAG_STATE_PAUSEIR:
+ /* ->DRSCan->IRSCan->IRCap->IRExit1->PauseIR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_idle_irpause,
+ sizeof(sm_idle_irpause));
+
+ aspeed_jtag->status = JTAG_STATE_PAUSEIR;
+ break;
+ case JTAG_STATE_PAUSEDR:
+ /* ->DRSCan->DRCap->DRExit1->PauseDR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_idle_drpause,
+ sizeof(sm_idle_drpause));
+
+ aspeed_jtag->status = JTAG_STATE_PAUSEDR;
+ break;
+ case JTAG_STATE_IDLE:
+ /* IDLE */
+ aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0);
+ aspeed_jtag->status = JTAG_STATE_IDLE;
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case JTAG_STATE_PAUSEIR:
+ /* Fall-through */
+ case JTAG_STATE_PAUSEDR:
+ /* From IR/DR Pause */
+ switch (runtest->endstate) {
+ case JTAG_STATE_PAUSEIR:
+ /*
+ * to Exit2 IR/DR->Updt IR/DR->DRSCan->IRSCan->IRCap->
+ * IRExit1->PauseIR
+ */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_irpause,
+ sizeof(sm_pause_irpause));
+
+ aspeed_jtag->status = JTAG_STATE_PAUSEIR;
+ break;
+ case JTAG_STATE_PAUSEDR:
+ /*
+ * to Exit2 IR/DR->Updt IR/DR->DRSCan->DRCap->
+ * DRExit1->PauseDR
+ */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_drpause,
+ sizeof(sm_pause_drpause));
+ aspeed_jtag->status = JTAG_STATE_PAUSEDR;
+ break;
+ case JTAG_STATE_IDLE:
+ /* to Exit2 IR/DR->Updt IR/DR->IDLE */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_idle,
+ sizeof(sm_pause_idle));
+ aspeed_jtag->status = JTAG_STATE_IDLE;
+ break;
+ default:
+ break;
+ }
+ break;
+
+ default:
+ dev_err(aspeed_jtag->dev, "aspeed_jtag_run_test_idle error\n");
+ break;
+ }
+
+ /* Stay on IDLE for at least TCK cycle */
+ for (i = 0; i < runtest->tck; i++)
+ aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0);
+}
+
+/**
+ * aspeed_jtag_run_test_idle:
+ * JTAG reset: generates at least 9 TMS high and 1 TMS low to force
+ * devices into Run-Test/Idle State.
+ */
+static int aspeed_jtag_idle(struct jtag *jtag,
+ struct jtag_run_test_idle *runtest)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ dev_dbg(aspeed_jtag->dev, "runtest, status:%d, mode:%s, state:%s, reset:%d, tck:%d\n",
+ aspeed_jtag->status,
+ aspeed_jtag->mode & JTAG_XFER_HW_MODE ? "HW" : "SW",
+ end_status_str[runtest->endstate], runtest->reset,
+ runtest->tck);
+
+ if (!(aspeed_jtag->mode & JTAG_XFER_HW_MODE)) {
+ aspeed_jtag_run_test_idle_sw(aspeed_jtag, runtest);
+ return 0;
+ }
+
+ /* Disable sw mode */
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW);
+ /* x TMS high + 1 TMS low */
+ if (runtest->reset)
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_CTL_ENG_EN |
+ ASPEED_JTAG_CTL_ENG_OUT_EN |
+ ASPEED_JTAG_CTL_FORCE_TMS, ASPEED_JTAG_CTRL);
+ else
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_EC_GO_IDLE,
+ ASPEED_JTAG_EC);
+
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ ASPEED_JTAG_SW_MODE_TDIO, ASPEED_JTAG_SW);
+
+ aspeed_jtag->status = JTAG_STATE_IDLE;
+ return 0;
+}
+
+static void aspeed_jtag_xfer_sw(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_xfer *xfer, unsigned long *data)
+{
+ unsigned long remain_xfer = xfer->length;
+ unsigned long shift_bits = 0;
+ unsigned long index = 0;
+ unsigned long tdi;
+ char tdo;
+
+ if (xfer->direction == JTAG_READ_XFER)
+ tdi = UINT_MAX;
+ else
+ tdi = data[index];
+
+ while (remain_xfer > 1) {
+ tdo = aspeed_jtag_tck_cycle(aspeed_jtag, 0,
+ tdi & ASPEED_JTAG_DATA_MSB);
+ data[index] |= tdo << (shift_bits %
+ ASPEED_JTAG_DATA_CHUNK_SIZE);
+
+ tdi >>= 1;
+ shift_bits++;
+ remain_xfer--;
+
+ if (shift_bits % ASPEED_JTAG_DATA_CHUNK_SIZE == 0) {
+ dev_dbg(aspeed_jtag->dev, "R/W data[%lu]:%lx\n",
+ index, data[index]);
+
+ tdo = 0;
+ index++;
+
+ if (xfer->direction == JTAG_READ_XFER)
+ tdi = UINT_MAX;
+ else
+ tdi = data[index];
+ }
+ }
+
+ tdo = aspeed_jtag_tck_cycle(aspeed_jtag, 1, tdi & ASPEED_JTAG_DATA_MSB);
+ data[index] |= tdo << (shift_bits % ASPEED_JTAG_DATA_CHUNK_SIZE);
+}
+
+static void aspeed_jtag_xfer_push_data(struct aspeed_jtag *aspeed_jtag,
+ enum jtag_xfer_type type, u32 bits_len)
+{
+ dev_dbg(aspeed_jtag->dev, "shift bits %d\n", bits_len);
+
+ if (type == JTAG_SIR_XFER) {
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_IOUT_LEN(bits_len),
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_DOUT_LEN(bits_len) |
+ ASPEED_JTAG_CTL_INST_EN, ASPEED_JTAG_CTRL);
+ } else {
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_DOUT_LEN(bits_len),
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_DOUT_LEN(bits_len) |
+ ASPEED_JTAG_CTL_DATA_EN, ASPEED_JTAG_CTRL);
+ }
+}
+
+static void aspeed_jtag_xfer_push_data_last(struct aspeed_jtag *aspeed_jtag,
+ enum jtag_xfer_type type,
+ u32 shift_bits,
+ enum jtag_endstate endstate)
+{
+ if (endstate != JTAG_STATE_IDLE) {
+ if (type == JTAG_SIR_XFER) {
+ dev_dbg(aspeed_jtag->dev, "IR Keep Pause\n");
+
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits),
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_INST_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_instruction_pause(aspeed_jtag);
+ } else {
+ dev_dbg(aspeed_jtag->dev, "DR Keep Pause\n");
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_DR_UPDATE,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_DR_UPDATE |
+ ASPEED_JTAG_CTL_DATA_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_data_pause_complete(aspeed_jtag);
+ }
+ } else {
+ if (type == JTAG_SIR_XFER) {
+ dev_dbg(aspeed_jtag->dev, "IR go IDLE\n");
+
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_INST,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_INST |
+ ASPEED_JTAG_CTL_INST_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_instruction_complete(aspeed_jtag);
+ } else {
+ dev_dbg(aspeed_jtag->dev, "DR go IDLE\n");
+
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_DATA,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_DATA |
+ ASPEED_JTAG_CTL_DATA_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_data_complete(aspeed_jtag);
+ }
+ }
+}
+
+static void aspeed_jtag_xfer_hw(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_xfer *xfer, unsigned long *data)
+{
+ unsigned long remain_xfer = xfer->length;
+ unsigned long index = 0;
+ char shift_bits;
+ u32 data_reg;
+
+ data_reg = xfer->type == JTAG_SIR_XFER ?
+ ASPEED_JTAG_INST : ASPEED_JTAG_DATA;
+ while (remain_xfer) {
+ if (xfer->direction == JTAG_WRITE_XFER) {
+ dev_dbg(aspeed_jtag->dev, "W dr->dr_data[%lu]:%lx\n",
+ index, data[index]);
+
+ aspeed_jtag_write(aspeed_jtag, data[index], data_reg);
+ } else {
+ aspeed_jtag_write(aspeed_jtag, 0, data_reg);
+ }
+
+ if (remain_xfer > ASPEED_JTAG_DATA_CHUNK_SIZE) {
+ shift_bits = ASPEED_JTAG_DATA_CHUNK_SIZE;
+
+ /*
+ * Read bytes were not equals to column length
+ * and go to Pause-DR
+ */
+ aspeed_jtag_xfer_push_data(aspeed_jtag, xfer->type,
+ shift_bits);
+ } else {
+ /*
+ * Read bytes equals to column length =>
+ * Update-DR
+ */
+ shift_bits = remain_xfer;
+ aspeed_jtag_xfer_push_data_last(aspeed_jtag, xfer->type,
+ shift_bits,
+ xfer->endstate);
+ }
+
+ if (xfer->direction == JTAG_READ_XFER) {
+ if (shift_bits < ASPEED_JTAG_DATA_CHUNK_SIZE) {
+ data[index] = aspeed_jtag_read(aspeed_jtag,
+ data_reg);
+
+ data[index] >>= ASPEED_JTAG_DATA_CHUNK_SIZE -
+ shift_bits;
+ } else {
+ data[index] = aspeed_jtag_read(aspeed_jtag,
+ data_reg);
+ }
+ dev_dbg(aspeed_jtag->dev, "R dr->dr_data[%lu]:%lx\n",
+ index, data[index]);
+ }
+
+ remain_xfer = remain_xfer - shift_bits;
+ index++;
+ dev_dbg(aspeed_jtag->dev, "remain_xfer %lu\n", remain_xfer);
+ }
+}
+
+static int aspeed_jtag_xfer(struct jtag *jtag, struct jtag_xfer *xfer,
+ u8 *xfer_data)
+{
+ static const u8 sm_update_shiftir[] = {1, 1, 0, 0};
+ static const u8 sm_update_shiftdr[] = {1, 0, 0};
+ static const u8 sm_pause_idle[] = {1, 1, 0};
+ static const u8 sm_pause_update[] = {1, 1};
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+ unsigned long *data = (unsigned long *)xfer_data;
+ unsigned long remain_xfer = xfer->length;
+ char dbg_str[256];
+ int pos = 0;
+ int i;
+
+ for (i = 0; i <= xfer->length / BITS_PER_BYTE; i++) {
+ pos += snprintf(&dbg_str[pos], sizeof(dbg_str) - pos,
+ "0x%02x ", xfer_data[i]);
+ }
+
+ dev_dbg(aspeed_jtag->dev, " %s %s xfer, mode:%s, END:%d, len:%lu, TDI[%s]\n",
+ xfer->type == JTAG_SIR_XFER ? "SIR" : "SDR",
+ xfer->direction == JTAG_READ_XFER ? "READ" : "WRITE",
+ aspeed_jtag->mode & JTAG_XFER_HW_MODE ? "HW" : "SW",
+ xfer->endstate, remain_xfer, dbg_str);
+
+ if (!(aspeed_jtag->mode & JTAG_XFER_HW_MODE)) {
+ /* SW mode */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ ASPEED_JTAG_SW_MODE_TDIO, ASPEED_JTAG_SW);
+
+ if (aspeed_jtag->status != JTAG_STATE_IDLE) {
+ /*IR/DR Pause->Exit2 IR / DR->Update IR /DR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_update,
+ sizeof(sm_pause_update));
+ }
+
+ if (xfer->type == JTAG_SIR_XFER)
+ /* ->IRSCan->CapIR->ShiftIR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_update_shiftir,
+ sizeof(sm_update_shiftir));
+ else
+ /* ->DRScan->DRCap->DRShift */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_update_shiftdr,
+ sizeof(sm_update_shiftdr));
+
+ aspeed_jtag_xfer_sw(aspeed_jtag, xfer, data);
+
+ /* DIPause/DRPause */
+ aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0);
+
+ if (xfer->endstate == JTAG_STATE_IDLE) {
+ /* ->DRExit2->DRUpdate->IDLE */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_idle,
+ sizeof(sm_pause_idle));
+ }
+ } else {
+ /* hw mode */
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW);
+ aspeed_jtag_xfer_hw(aspeed_jtag, xfer, data);
+ }
+
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ ASPEED_JTAG_SW_MODE_TDIO, ASPEED_JTAG_SW);
+ aspeed_jtag->status = xfer->endstate;
+ return 0;
+}
+
+static int aspeed_jtag_status_get(struct jtag *jtag, u32 *status)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ *status = aspeed_jtag->status;
+ return 0;
+}
+
+static irqreturn_t aspeed_jtag_interrupt(s32 this_irq, void *dev_id)
+{
+ struct aspeed_jtag *aspeed_jtag = dev_id;
+ irqreturn_t ret;
+ u32 status;
+
+ status = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_ISR);
+ dev_dbg(aspeed_jtag->dev, "status %x\n", status);
+
+ if (status & ASPEED_JTAG_ISR_INT_MASK) {
+ aspeed_jtag_write(aspeed_jtag,
+ (status & ASPEED_JTAG_ISR_INT_MASK)
+ | (status & ASPEED_JTAG_ISR_INT_EN_MASK),
+ ASPEED_JTAG_ISR);
+ aspeed_jtag->flag |= status & ASPEED_JTAG_ISR_INT_MASK;
+ }
+
+ if (aspeed_jtag->flag) {
+ wake_up_interruptible(&aspeed_jtag->jtag_wq);
+ ret = IRQ_HANDLED;
+ } else {
+ dev_err(aspeed_jtag->dev, "irq status:%x\n",
+ status);
+ ret = IRQ_NONE;
+ }
+ return ret;
+}
+
+static int aspeed_jtag_init(struct platform_device *pdev,
+ struct aspeed_jtag *aspeed_jtag)
+{
+ struct resource *res;
+ int err;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ aspeed_jtag->reg_base = devm_ioremap_resource(aspeed_jtag->dev, res);
+ if (IS_ERR(aspeed_jtag->reg_base))
+ return -ENOMEM;
+
+ aspeed_jtag->pclk = devm_clk_get(aspeed_jtag->dev, NULL);
+ if (IS_ERR(aspeed_jtag->pclk)) {
+ dev_err(aspeed_jtag->dev, "devm_clk_get failed\n");
+ return PTR_ERR(aspeed_jtag->pclk);
+ }
+
+ aspeed_jtag->irq = platform_get_irq(pdev, 0);
+ if (aspeed_jtag->irq < 0) {
+ dev_err(aspeed_jtag->dev, "no irq specified\n");
+ return -ENOENT;
+ }
+
+ clk_prepare_enable(aspeed_jtag->pclk);
+
+ aspeed_jtag->rst = devm_reset_control_get_shared(aspeed_jtag->dev,
+ NULL);
+ if (IS_ERR(aspeed_jtag->rst)) {
+ dev_err(aspeed_jtag->dev,
+ "missing or invalid reset controller device tree entry");
+ return PTR_ERR(aspeed_jtag->rst);
+ }
+ reset_control_deassert(aspeed_jtag->rst);
+
+ /* Enable clock */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_CTL_ENG_EN |
+ ASPEED_JTAG_CTL_ENG_OUT_EN, ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ ASPEED_JTAG_SW_MODE_TDIO, ASPEED_JTAG_SW);
+
+ err = devm_request_irq(aspeed_jtag->dev, aspeed_jtag->irq,
+ aspeed_jtag_interrupt, 0,
+ "aspeed-jtag", aspeed_jtag);
+ if (err) {
+ dev_err(aspeed_jtag->dev, "unable to get IRQ");
+ goto clk_unprep;
+ }
+ dev_dbg(&pdev->dev, "IRQ %d.\n", aspeed_jtag->irq);
+
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_ISR_INST_PAUSE |
+ ASPEED_JTAG_ISR_INST_COMPLETE |
+ ASPEED_JTAG_ISR_DATA_PAUSE |
+ ASPEED_JTAG_ISR_DATA_COMPLETE |
+ ASPEED_JTAG_ISR_INST_PAUSE_EN |
+ ASPEED_JTAG_ISR_INST_COMPLETE_EN |
+ ASPEED_JTAG_ISR_DATA_PAUSE_EN |
+ ASPEED_JTAG_ISR_DATA_COMPLETE_EN,
+ ASPEED_JTAG_ISR);
+
+ aspeed_jtag->flag = 0;
+ aspeed_jtag->mode = 0;
+ init_waitqueue_head(&aspeed_jtag->jtag_wq);
+ return 0;
+
+clk_unprep:
+ clk_disable_unprepare(aspeed_jtag->pclk);
+ return err;
+}
+
+static int aspeed_jtag_deinit(struct platform_device *pdev,
+ struct aspeed_jtag *aspeed_jtag)
+{
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_ISR);
+ /* Disable clock */
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_CTRL);
+ reset_control_assert(aspeed_jtag->rst);
+ clk_disable_unprepare(aspeed_jtag->pclk);
+ return 0;
+}
+
+static const struct jtag_ops aspeed_jtag_ops = {
+ .freq_get = aspeed_jtag_freq_get,
+ .freq_set = aspeed_jtag_freq_set,
+ .status_get = aspeed_jtag_status_get,
+ .idle = aspeed_jtag_idle,
+ .xfer = aspeed_jtag_xfer,
+ .mode_set = aspeed_jtag_mode_set
+};
+
+static int aspeed_jtag_probe(struct platform_device *pdev)
+{
+ struct aspeed_jtag *aspeed_jtag;
+ struct device *dev;
+ struct jtag *jtag;
+ int err;
+
+ dev = &pdev->dev;
+ jtag = jtag_alloc(sizeof(*aspeed_jtag), &aspeed_jtag_ops);
+ if (!jtag)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, jtag);
+ aspeed_jtag = jtag_priv(jtag);
+ aspeed_jtag->dev = &pdev->dev;
+
+ /* Initialize device*/
+ err = aspeed_jtag_init(pdev, aspeed_jtag);
+ if (err)
+ goto err_jtag_init;
+
+ /* Initialize JTAG core structure*/
+ err = jtag_register(jtag);
+ if (err)
+ goto err_jtag_register;
+
+ return 0;
+
+err_jtag_register:
+ aspeed_jtag_deinit(pdev, aspeed_jtag);
+err_jtag_init:
+ jtag_free(jtag);
+ return err;
+}
+
+static int aspeed_jtag_remove(struct platform_device *pdev)
+{
+ struct jtag *jtag;
+
+ jtag = platform_get_drvdata(pdev);
+ aspeed_jtag_deinit(pdev, jtag_priv(jtag));
+ jtag_unregister(jtag);
+ jtag_free(jtag);
+ return 0;
+}
+
+static const struct of_device_id aspeed_jtag_of_match[] = {
+ { .compatible = "aspeed,ast2400-jtag", },
+ { .compatible = "aspeed,ast2500-jtag", },
+ {}
+};
+
+static struct platform_driver aspeed_jtag_driver = {
+ .probe = aspeed_jtag_probe,
+ .remove = aspeed_jtag_remove,
+ .driver = {
+ .name = ASPEED_JTAG_NAME,
+ .of_match_table = aspeed_jtag_of_match,
+ },
+};
+module_platform_driver(aspeed_jtag_driver);
+
+MODULE_AUTHOR("Oleksandr Shamray <oleksandrs@mellanox.com>");
+MODULE_DESCRIPTION("ASPEED JTAG driver");
+MODULE_LICENSE("GPL v2");
--
1.7.1
^ permalink raw reply related
* [patch v21 1/4] drivers: jtag: Add JTAG core driver
From: Oleksandr Shamray @ 2018-05-15 14:21 UTC (permalink / raw)
To: gregkh, arnd
Cc: linux-kernel, linux-arm-kernel, devicetree, openbmc, joel, jiri,
tklauser, linux-serial, vadimp, system-sw-low-level, robh+dt,
openocd-devel-owner, linux-api, davem, mchehab, Oleksandr Shamray,
Jiri Pirko
In-Reply-To: <1526394095-5069-1-git-send-email-oleksandrs@mellanox.com>
Initial patch for JTAG driver
JTAG class driver provide infrastructure to support hardware/software
JTAG platform drivers. It provide user layer API interface for flashing
and debugging external devices which equipped with JTAG interface
using standard transactions.
Driver exposes set of IOCTL to user space for:
- XFER:
- SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
- SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks).
- SIOCFREQ/GIOCFREQ for setting and reading JTAG frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
---
v20->v21
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- Fix JTAG dirver help in Kconfig
v19->v20
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- Fix JTAG dirver help in Kconfig
Notifications from kbuild test robot <lkp@intel.com>
- fix incompatible type casts
v18->v19
Comments pointed by Julia Cartwright <juliac@eso.teric.us>
- Fix memory leak on jtag_alloc exit
v17->v18
Comments pointed by Julia Cartwright <juliac@eso.teric.us>
- Change to return -EOPNOTSUPP in case of error in JTAG_GIOCFREQ
- Add ops callbacks check to jtag_alloc
- Add err check for copy_to_user
- Move the kfree() above the if (err) in JTAG_IOCXFER
- remove unnecessary check for error after put_user
- add padding to struct jtag_xfer
v16->v17
Comments pointed by Julia Cartwright <juliac@eso.teric.us>
- Fix memory allocation on jtag alloc
- Move out unnecessary form lock on jtag open
- Rework jtag register behavior
v15->v16
Commen ts pointed by Florian Fainelli <f.fainelli@gmail.com>
- move check jtag->ops->* in ioctl before get_user()
- change error type -EINVAL --> -EBUSY on open already opened jtag
- remove unnecessary ARCH_DMA_MINALIGN flag from kzalloc
- remove define ARCH_DMA_MINALIGN
v14->v15
v13->v14
Comments pointed by Philippe Ombredanne <pombredanne@nexb.com>
- Change style of head block comment from /**/ to //
v12->v13
Comments pointed by Philippe Ombredanne <pombredanne@nexb.com>
- Change jtag.c licence type to
SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
and reorder line with license in description
v11->v12
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- Change jtag.h licence type to
SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
and reorder line with license in description
Chip Bilbrey <chip@bilbrey.org>
- Remove Apeed reference from uapi jtag.h header
- Remove access mode from xfer and idle transactions
- Add new ioctl JTAG_SIOCMODE for set hw mode
- Add only one open per JTAG port blocking with mutex blocking
v10->v11
Notifications from kbuild test robot <lkp@intel.com>
- include types.h headeri to jtag.h
- fix incompatible type of xfer callback
- remove rdundant class defination
- Fix return order in case of xfer error
V9->v10
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- remove unnecessary alignment for pirv data
- move jtag_copy_to_user and jtag_copy_from_user code just to ioctl
- move int jtag_run_test_idle_op and jtag_xfer_op code
just to ioctl
- change return error codes to more applicable
- add missing error checks
- fix error check order in ioctl
- remove unnecessary blank lines
- add param validation to ioctl
- remove compat_ioctl
- remove only one open per JTAG port blocking.
User will care about this.
- Fix idr memory leak on jtag_exit
- change cdev device type to misc
V8->v9
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- use get_user() instead of __get_user().
- change jtag->open type from int to atomic_t
- remove spinlock on jtg_open
- remove mutex on jtag_register
- add unregister_chrdev_region on jtag_init err
- add unregister_chrdev_region on jtag_exit
- remove unnecessary pointer casts
- add *data parameter to xfer function prototype
v7->v8
Comments pointed by Moritz Fischer <moritz.fischer@ettus.com>
- Fix misspelling s/friver/driver
v6->v7
Notifications from kbuild test robot <lkp@intel.com>
- Remove include asm/types.h from jtag.h
- Add include <linux/types.h> to jtag.c
v5->v6
v4->v5
v3->v4
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- change transaction pointer tdio type to __u64
- change internal status type from enum to __u32
- reorder jtag_xfer members to avoid the implied padding
- add __packed attribute to jtag_xfer and jtag_run_test_idle
v2->v3
Notifications from kbuild test robot <lkp@intel.com>
- Change include path to <linux/types.h> in jtag.h
v1->v2
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- Change license type from GPLv2/BSD to GPLv2
- Change type of variables which crossed user/kernel to __type
- Remove "default n" from Kconfig
Comments pointed by Andrew Lunn <andrew@lunn.ch>
- Change list_add_tail in jtag_unregister to list_del
Comments pointed by Neil Armstrong <narmstrong@baylibre.com>
- Add SPDX-License-Identifier instead of license text
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- Change __copy_to_user to memdup_user
- Change __put_user to put_user
- Change type of variables to __type for compatible 32 and 64-bit systems
- Add check for maximum xfer data size
- Change lookup data mechanism to get jtag data from inode
- Add .compat_ioctl to file ops
- Add mem alignment for jtag priv data
Comments pointed by Tobias Klauser <tklauser@distanz.ch>
- Change function names to avoid match with variable types
- Fix description for jtag_ru_test_idle in uapi jtag.h
- Fix misprints IDEL/IDLE, trough/through
---
Documentation/ioctl/ioctl-number.txt | 2 +
MAINTAINERS | 10 ++
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/jtag/Kconfig | 18 +++
drivers/jtag/Makefile | 1 +
drivers/jtag/jtag.c | 274 ++++++++++++++++++++++++++++++++++
include/linux/jtag.h | 41 +++++
include/uapi/linux/jtag.h | 105 +++++++++++++
9 files changed, 454 insertions(+), 0 deletions(-)
create mode 100644 drivers/jtag/Kconfig
create mode 100644 drivers/jtag/Makefile
create mode 100644 drivers/jtag/jtag.c
create mode 100644 include/linux/jtag.h
create mode 100644 include/uapi/linux/jtag.h
diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt
index 7f7413e..c5548b5 100644
--- a/Documentation/ioctl/ioctl-number.txt
+++ b/Documentation/ioctl/ioctl-number.txt
@@ -318,6 +318,8 @@ Code Seq#(hex) Include File Comments
0xB0 all RATIO devices in development:
<mailto:vgo@ratio.de>
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
+0xB2 00-0f linux/jtag.h JTAG driver
+ <mailto:oleksandrs@mellanox.com>
0xB3 00 linux/mmc/ioctl.h
0xB4 00-0F linux/gpio.h <mailto:linux-gpio@vger.kernel.org>
0xB5 00-0F uapi/linux/rpmsg.h <mailto:linux-remoteproc@vger.kernel.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index 79bb02f..2fd22d6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7610,6 +7610,16 @@ L: linux-serial@vger.kernel.org
S: Maintained
F: drivers/tty/serial/jsm/
+JTAG SUBSYSTEM
+M: Oleksandr Shamray <oleksandrs@mellanox.com>
+M: Vadim Pasternak <vadimp@mellanox.com>
+S: Maintained
+F: include/linux/jtag.h
+F: include/uapi/linux/jtag.h
+F: drivers/jtag/
+F: Documentation/devicetree/bindings/jtag/
+F: Documentation/ABI/testing/jtag-cdev
+
K10TEMP HARDWARE MONITORING DRIVER
M: Clemens Ladisch <clemens@ladisch.de>
L: linux-hwmon@vger.kernel.org
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 95b9ccc..bb71e48 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -217,4 +217,6 @@ source "drivers/siox/Kconfig"
source "drivers/slimbus/Kconfig"
+source "drivers/jtag/Kconfig"
+
endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 24cd470..c92636b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -185,3 +185,4 @@ obj-$(CONFIG_TEE) += tee/
obj-$(CONFIG_MULTIPLEXER) += mux/
obj-$(CONFIG_UNISYS_VISORBUS) += visorbus/
obj-$(CONFIG_SIOX) += siox/
+obj-$(CONFIG_JTAG) += jtag/
diff --git a/drivers/jtag/Kconfig b/drivers/jtag/Kconfig
new file mode 100644
index 0000000..43eb9a4
--- /dev/null
+++ b/drivers/jtag/Kconfig
@@ -0,0 +1,18 @@
+menuconfig JTAG
+ tristate "JTAG support"
+ help
+ This provides basic core functionality support for JTAG class devices.
+ Hardware that is equipped with a JTAG microcontroller can be
+ supported by using this driver's interfaces.
+ This driver exposes a set of IOCTLs to the user space for
+ the following commands:
+ SDR: (Scan Data Register) Performs an IEEE 1149.1 Data Register scan
+ SIR: (Scan Instruction Register) Performs an IEEE 1149.1 Instruction
+ Register scan.
+ RUNTEST: Forces the IEEE 1149.1 bus to a run state for a specified
+ number of clocks or a specified time period.
+
+ If you want this support, you should say Y here.
+
+ To compile this driver as a module, choose M here: the module will
+ be called jtag.
diff --git a/drivers/jtag/Makefile b/drivers/jtag/Makefile
new file mode 100644
index 0000000..af37493
--- /dev/null
+++ b/drivers/jtag/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_JTAG) += jtag.o
diff --git a/drivers/jtag/jtag.c b/drivers/jtag/jtag.c
new file mode 100644
index 0000000..84c29c8
--- /dev/null
+++ b/drivers/jtag/jtag.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// drivers/jtag/jtag.c
+//
+// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
+// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
+
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/jtag.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/rtnetlink.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <uapi/linux/jtag.h>
+
+#define JTAG_NAME "jtag0"
+#define MAX_JTAG_NAME_LEN (sizeof("jtag") + 5)
+
+struct jtag {
+ struct miscdevice miscdev;
+ struct device *dev;
+ const struct jtag_ops *ops;
+ int id;
+ bool opened;
+ struct mutex open_lock;
+ unsigned long priv[0];
+};
+
+static DEFINE_IDA(jtag_ida);
+
+void *jtag_priv(struct jtag *jtag)
+{
+ return jtag->priv;
+}
+EXPORT_SYMBOL_GPL(jtag_priv);
+
+static long jtag_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+ struct jtag *jtag = file->private_data;
+ struct jtag_run_test_idle idle;
+ struct jtag_xfer xfer;
+ u8 *xfer_data;
+ u32 data_size;
+ u32 value;
+ int err;
+
+ if (!arg)
+ return -EINVAL;
+
+ switch (cmd) {
+ case JTAG_GIOCFREQ:
+ if (!jtag->ops->freq_get)
+ return -EOPNOTSUPP;
+
+ err = jtag->ops->freq_get(jtag, &value);
+ if (err)
+ break;
+
+ if (put_user(value, (__u32 __user *)arg))
+ err = -EFAULT;
+ break;
+
+ case JTAG_SIOCFREQ:
+ if (!jtag->ops->freq_set)
+ return -EOPNOTSUPP;
+
+ if (get_user(value, (__u32 __user *)arg))
+ return -EFAULT;
+ if (value == 0)
+ return -EINVAL;
+
+ err = jtag->ops->freq_set(jtag, value);
+ break;
+
+ case JTAG_IOCRUNTEST:
+ if (copy_from_user(&idle, (const void __user *)arg,
+ sizeof(struct jtag_run_test_idle)))
+ return -EFAULT;
+
+ if (idle.endstate > JTAG_STATE_PAUSEDR)
+ return -EINVAL;
+
+ err = jtag->ops->idle(jtag, &idle);
+ break;
+
+ case JTAG_IOCXFER:
+ if (copy_from_user(&xfer, (const void __user *)arg,
+ sizeof(struct jtag_xfer)))
+ return -EFAULT;
+
+ if (xfer.length >= JTAG_MAX_XFER_DATA_LEN)
+ return -EINVAL;
+
+ if (xfer.type > JTAG_SDR_XFER)
+ return -EINVAL;
+
+ if (xfer.direction > JTAG_WRITE_XFER)
+ return -EINVAL;
+
+ if (xfer.endstate > JTAG_STATE_PAUSEDR)
+ return -EINVAL;
+
+ data_size = DIV_ROUND_UP(xfer.length, BITS_PER_BYTE);
+ xfer_data = memdup_user(u64_to_user_ptr(xfer.tdio), data_size);
+
+ if (IS_ERR(xfer_data))
+ return -EFAULT;
+
+ err = jtag->ops->xfer(jtag, &xfer, xfer_data);
+ if (err) {
+ kfree(xfer_data);
+ return -EFAULT;
+ }
+
+ err = copy_to_user(u64_to_user_ptr(xfer.tdio),
+ (void *)(xfer_data), data_size);
+ kfree(xfer_data);
+ if (err)
+ return -EFAULT;
+
+ if (copy_to_user((void __user *)arg, (void *)&xfer,
+ sizeof(struct jtag_xfer)))
+ return -EFAULT;
+ break;
+
+ case JTAG_GIOCSTATUS:
+ err = jtag->ops->status_get(jtag, &value);
+ if (err)
+ break;
+
+ err = put_user(value, (__u32 __user *)arg);
+ break;
+ case JTAG_SIOCMODE:
+ if (get_user(value, (__u32 __user *)arg))
+ return -EFAULT;
+ if (value == 0)
+ return -EINVAL;
+
+ err = jtag->ops->mode_set(jtag, value);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+ return err;
+}
+
+static int jtag_open(struct inode *inode, struct file *file)
+{
+ struct jtag *jtag = container_of(file->private_data, struct jtag,
+ miscdev);
+
+ if (mutex_lock_interruptible(&jtag->open_lock))
+ return -ERESTARTSYS;
+
+ if (jtag->opened) {
+ mutex_unlock(&jtag->open_lock);
+ return -EBUSY;
+ }
+ jtag->opened = true;
+ mutex_unlock(&jtag->open_lock);
+
+ nonseekable_open(inode, file);
+ file->private_data = jtag;
+ return 0;
+}
+
+static int jtag_release(struct inode *inode, struct file *file)
+{
+ struct jtag *jtag = file->private_data;
+
+ mutex_lock(&jtag->open_lock);
+ jtag->opened = false;
+ mutex_unlock(&jtag->open_lock);
+ return 0;
+}
+
+static const struct file_operations jtag_fops = {
+ .owner = THIS_MODULE,
+ .open = jtag_open,
+ .release = jtag_release,
+ .llseek = noop_llseek,
+ .unlocked_ioctl = jtag_ioctl,
+};
+
+struct jtag *jtag_alloc(size_t priv_size, const struct jtag_ops *ops)
+{
+ struct jtag *jtag;
+
+ if (!ops)
+ return NULL;
+
+ if (!ops->idle || !ops->mode_set || !ops->status_get || !ops->xfer)
+ return NULL;
+
+ jtag = kzalloc(sizeof(*jtag) + priv_size, GFP_KERNEL);
+ if (!jtag)
+ return NULL;
+
+ jtag->ops = ops;
+ return jtag;
+}
+EXPORT_SYMBOL_GPL(jtag_alloc);
+
+void jtag_free(struct jtag *jtag)
+{
+ kfree(jtag);
+}
+EXPORT_SYMBOL_GPL(jtag_free);
+
+int jtag_register(struct jtag *jtag)
+{
+ char *name;
+ int err;
+ int id;
+
+ id = ida_simple_get(&jtag_ida, 0, 0, GFP_KERNEL);
+ if (id < 0)
+ return id;
+
+ jtag->id = id;
+ jtag->opened = false;
+
+ name = kzalloc(MAX_JTAG_NAME_LEN, GFP_KERNEL);
+ if (!name) {
+ err = -ENOMEM;
+ goto err_jtag_alloc;
+ }
+
+ err = snprintf(name, MAX_JTAG_NAME_LEN, "jtag%d", id);
+ if (err < 0)
+ goto err_jtag_name;
+
+ mutex_init(&jtag->open_lock);
+ jtag->miscdev.fops = &jtag_fops;
+ jtag->miscdev.minor = MISC_DYNAMIC_MINOR;
+ jtag->miscdev.name = name;
+
+ err = misc_register(&jtag->miscdev);
+ if (err) {
+ dev_err(jtag->dev, "Unable to register device\n");
+ goto err_jtag_name;
+ }
+ return 0;
+
+err_jtag_name:
+ kfree(name);
+err_jtag_alloc:
+ ida_simple_remove(&jtag_ida, id);
+ return err;
+}
+EXPORT_SYMBOL_GPL(jtag_register);
+
+void jtag_unregister(struct jtag *jtag)
+{
+ misc_deregister(&jtag->miscdev);
+ kfree(jtag->miscdev.name);
+ ida_simple_remove(&jtag_ida, jtag->id);
+}
+EXPORT_SYMBOL_GPL(jtag_unregister);
+
+static void __exit jtag_exit(void)
+{
+ ida_destroy(&jtag_ida);
+}
+
+module_exit(jtag_exit);
+
+MODULE_AUTHOR("Oleksandr Shamray <oleksandrs@mellanox.com>");
+MODULE_DESCRIPTION("Generic jtag support");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/jtag.h b/include/linux/jtag.h
new file mode 100644
index 0000000..80a887f
--- /dev/null
+++ b/include/linux/jtag.h
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+// include/linux/jtag.h - JTAG class driver
+//
+// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
+// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
+
+#ifndef __JTAG_H
+#define __JTAG_H
+
+#include <uapi/linux/jtag.h>
+
+#define jtag_u64_to_ptr(arg) ((void *)(uintptr_t)arg)
+
+#define JTAG_MAX_XFER_DATA_LEN 65535
+
+struct jtag;
+/**
+ * struct jtag_ops - callbacks for jtag control functions:
+ *
+ * @freq_get: get frequency function. Filled by device driver
+ * @freq_set: set frequency function. Filled by device driver
+ * @status_get: set status function. Filled by device driver
+ * @idle: set JTAG to idle state function. Filled by device driver
+ * @xfer: send JTAG xfer function. Filled by device driver
+ */
+struct jtag_ops {
+ int (*freq_get)(struct jtag *jtag, u32 *freq);
+ int (*freq_set)(struct jtag *jtag, u32 freq);
+ int (*status_get)(struct jtag *jtag, u32 *state);
+ int (*idle)(struct jtag *jtag, struct jtag_run_test_idle *idle);
+ int (*xfer)(struct jtag *jtag, struct jtag_xfer *xfer, u8 *xfer_data);
+ int (*mode_set)(struct jtag *jtag, u32 mode_mask);
+};
+
+void *jtag_priv(struct jtag *jtag);
+int jtag_register(struct jtag *jtag);
+void jtag_unregister(struct jtag *jtag);
+struct jtag *jtag_alloc(size_t priv_size, const struct jtag_ops *ops);
+void jtag_free(struct jtag *jtag);
+
+#endif /* __JTAG_H */
diff --git a/include/uapi/linux/jtag.h b/include/uapi/linux/jtag.h
new file mode 100644
index 0000000..ecd02a0
--- /dev/null
+++ b/include/uapi/linux/jtag.h
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+// include/uapi/linux/jtag.h - JTAG class driver uapi
+//
+// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
+// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
+
+#ifndef __UAPI_LINUX_JTAG_H
+#define __UAPI_LINUX_JTAG_H
+
+#include <linux/types.h>
+/*
+ * JTAG_XFER_HW_MODE: JTAG hardware mode. Used to set HW drived or bitbang
+ * mode. This is bitmask param of ioctl JTAG_SIOCMODE command
+ */
+#define JTAG_XFER_HW_MODE 1
+
+/**
+ * enum jtag_endstate:
+ *
+ * @JTAG_STATE_IDLE: JTAG state machine IDLE state
+ * @JTAG_STATE_PAUSEIR: JTAG state machine PAUSE_IR state
+ * @JTAG_STATE_PAUSEDR: JTAG state machine PAUSE_DR state
+ */
+enum jtag_endstate {
+ JTAG_STATE_IDLE,
+ JTAG_STATE_PAUSEIR,
+ JTAG_STATE_PAUSEDR,
+};
+
+/**
+ * enum jtag_xfer_type:
+ *
+ * @JTAG_SIR_XFER: SIR transfer
+ * @JTAG_SDR_XFER: SDR transfer
+ */
+enum jtag_xfer_type {
+ JTAG_SIR_XFER,
+ JTAG_SDR_XFER,
+};
+
+/**
+ * enum jtag_xfer_direction:
+ *
+ * @JTAG_READ_XFER: read transfer
+ * @JTAG_WRITE_XFER: write transfer
+ */
+enum jtag_xfer_direction {
+ JTAG_READ_XFER,
+ JTAG_WRITE_XFER,
+};
+
+/**
+ * struct jtag_run_test_idle - forces JTAG state machine to
+ * RUN_TEST/IDLE state
+ *
+ * @reset: 0 - run IDLE/PAUSE from current state
+ * 1 - go through TEST_LOGIC/RESET state before IDLE/PAUSE
+ * @end: completion flag
+ * @tck: clock counter
+ *
+ * Structure represents interface to JTAG device for jtag idle
+ * execution.
+ */
+struct jtag_run_test_idle {
+ __u8 reset;
+ __u8 endstate;
+ __u8 tck;
+};
+
+/**
+ * struct jtag_xfer - jtag xfer:
+ *
+ * @type: transfer type
+ * @direction: xfer direction
+ * @length: xfer bits len
+ * @tdio : xfer data array
+ * @endir: xfer end state
+ *
+ * Structure represents interface to JTAG device for jtag sdr xfer
+ * execution.
+ */
+struct jtag_xfer {
+ __u8 type;
+ __u8 direction;
+ __u8 endstate;
+ __u8 padding;
+ __u32 length;
+ __u64 tdio;
+};
+
+/* ioctl interface */
+#define __JTAG_IOCTL_MAGIC 0xb2
+
+#define JTAG_IOCRUNTEST _IOW(__JTAG_IOCTL_MAGIC, 0,\
+ struct jtag_run_test_idle)
+#define JTAG_SIOCFREQ _IOW(__JTAG_IOCTL_MAGIC, 1, unsigned int)
+#define JTAG_GIOCFREQ _IOR(__JTAG_IOCTL_MAGIC, 2, unsigned int)
+#define JTAG_IOCXFER _IOWR(__JTAG_IOCTL_MAGIC, 3, struct jtag_xfer)
+#define JTAG_GIOCSTATUS _IOWR(__JTAG_IOCTL_MAGIC, 4, enum jtag_endstate)
+#define JTAG_SIOCMODE _IOW(__JTAG_IOCTL_MAGIC, 5, unsigned int)
+
+#define JTAG_FIRST_MINOR 0
+#define JTAG_MAX_DEVICES 32
+
+#endif /* __UAPI_LINUX_JTAG_H */
--
1.7.1
^ permalink raw reply related
* [patch v21 0/4] JTAG driver introduction
From: Oleksandr Shamray @ 2018-05-15 14:21 UTC (permalink / raw)
To: gregkh, arnd
Cc: linux-kernel, linux-arm-kernel, devicetree, openbmc, joel, jiri,
tklauser, linux-serial, vadimp, system-sw-low-level, robh+dt,
openocd-devel-owner, linux-api, davem, mchehab, Oleksandr Shamray
When a need raise up to use JTAG interface for system's devices
programming or CPU debugging, usually the user layer
application implements jtag protocol by bit-bang or using a
proprietary connection to vendor hardware.
This method can be slow and not generic.
We propose to implement general JTAG interface and infrastructure
to communicate with user layer application. In such way, we can
have the standard JTAG interface core part and separation from
specific HW implementation.
This allow new capability to debug the CPU or program system's
device via BMC without additional devices nor cost.
This patch purpose is to add JTAG master core infrastructure by
defining new JTAG class and provide generic JTAG interface
to allow hardware specific drivers to connect this interface.
This will enable all JTAG drivers to use the common interface
part and will have separate for hardware implementation.
The JTAG (Joint Test Action Group) core driver provides minimal generic
JTAG interface, which can be used by hardware specific JTAG master
controllers. By providing common interface for the JTAG controllers,
user space device programing is hardware independent.
Modern SoC which in use for embedded system' equipped with
internal JTAG master interface.
This interface is used for programming and debugging system's
hardware components, like CPLD, FPGA, CPU, voltage and
industrial controllers.
Firmware for such devices can be upgraded through JTAG interface during
Runtime. The JTAG standard support for multiple devices programming,
is in case their lines are daisy-chained together.
For example, systems which equipped with host CPU, BMC SoC or/and
number of programmable devices are capable to connect a pin and
select system components dynamically for programming and debugging,
This is using by the BMC which is equipped with internal SoC master
controller.
For example:
BMC JTAG master --> pin selected to CPLDs chain for programming (filed
upgrade, production)
BMC JTAG master --> pin selected to voltage monitors for programming
(field upgrade, production)
BMC JTAG master --> pin selected to host CPU (on-site debugging
and developers debugging)
For example, we can have application in user space which using calls
to JTAG driver executes CPLD programming directly from SVF file
The JTAG standard (IEEE 1149.1) defines the next connector pins:
- TDI (Test Data In);
- TDO (Test Data Out);
- TCK (Test Clock);
- TMS (Test Mode Select);
- TRST (Test Reset) (Optional);
The SoC equipped with JTAG master controller, performs
device programming on command or vector level. For example
a file in a standard SVF (Serial Vector Format) that contains
boundary scan vectors, can be used by sending each vector
to the JTAG interface and the JTAG controller will execute
the programming.
Initial version provides the system calls set for:
- SIR (Scan Instruction Register, IEEE 1149.1 Instruction Register scan);
- SDR (Scan Data Register, IEEE 1149.1 Data Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardware specific driver.
Oleksandr Shamray (4):
drivers: jtag: Add JTAG core driver
drivers: jtag: Add Aspeed SoC 24xx and 25xx families JTAG master
driver
Documentation: jtag: Add bindings for Aspeed SoC 24xx and 25xx
families JTAG master driver
Documentation: jtag: Add ABI documentation
Documentation/ABI/testing/jtag-dev | 27 +
.../devicetree/bindings/jtag/aspeed-jtag.txt | 22 +
Documentation/ioctl/ioctl-number.txt | 2 +
Documentation/jtag/overview | 28 +
Documentation/jtag/transactions | 109 +++
MAINTAINERS | 10 +
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/jtag/Kconfig | 32 +
drivers/jtag/Makefile | 2 +
drivers/jtag/jtag-aspeed.c | 786 ++++++++++++++++++++
drivers/jtag/jtag.c | 274 +++++++
include/linux/jtag.h | 41 +
include/uapi/linux/jtag.h | 105 +++
14 files changed, 1441 insertions(+), 0 deletions(-)
create mode 100644 Documentation/ABI/testing/jtag-dev
create mode 100644 Documentation/devicetree/bindings/jtag/aspeed-jtag.txt
create mode 100644 Documentation/jtag/overview
create mode 100644 Documentation/jtag/transactions
create mode 100644 drivers/jtag/Kconfig
create mode 100644 drivers/jtag/Makefile
create mode 100644 drivers/jtag/jtag-aspeed.c
create mode 100644 drivers/jtag/jtag.c
create mode 100644 include/linux/jtag.h
create mode 100644 include/uapi/linux/jtag.h
^ permalink raw reply
* Re: [PATCH v2 16/40] arm64: mm: Pin down ASIDs for sharing mm with devices
From: Catalin Marinas @ 2018-05-15 14:16 UTC (permalink / raw)
To: Jean-Philippe Brucker
Cc: ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A,
kvm-u79uwXL29TY76Z2rM5mHXA, linux-pci-u79uwXL29TY76Z2rM5mHXA,
xuzaibo-hv44wF8Li93QT0dZR+AlfA, will.deacon-5wv7dgnIgG8,
okaya-sgV2jX0FEOL9JmXXK+q4OQ, linux-mm-Bw31MaZKKs3YtjvyW6yDsg,
ashok.raj-ral2JQCrhuEAvxtiuMwx3w, bharatku-gjFFaj9aHVfQT0dZR+AlfA,
linux-acpi-u79uwXL29TY76Z2rM5mHXA, rfranz-YGCgFSpz5w/QT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA, rgummal-gjFFaj9aHVfQT0dZR+AlfA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
dwmw2-wEGCiKHe2LqWVfeAwA7xHQ,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
christian.koenig-5C7GfCeVMHo
In-Reply-To: <20180511190641.23008-17-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
Hi Jean-Philippe,
On Fri, May 11, 2018 at 08:06:17PM +0100, Jean-Philippe Brucker wrote:
> +unsigned long mm_context_get(struct mm_struct *mm)
> +{
> + unsigned long flags;
> + u64 asid;
> +
> + raw_spin_lock_irqsave(&cpu_asid_lock, flags);
> +
> + asid = atomic64_read(&mm->context.id);
> +
> + if (mm->context.pinned) {
> + mm->context.pinned++;
> + asid &= ~ASID_MASK;
> + goto out_unlock;
> + }
> +
> + if (nr_pinned_asids >= max_pinned_asids) {
> + asid = 0;
> + goto out_unlock;
> + }
> +
> + if (!asid_gen_match(asid)) {
> + /*
> + * We went through one or more rollover since that ASID was
> + * used. Ensure that it is still valid, or generate a new one.
> + * The cpu argument isn't used by new_context.
> + */
> + asid = new_context(mm, 0);
> + atomic64_set(&mm->context.id, asid);
> + }
> +
> + asid &= ~ASID_MASK;
> +
> + nr_pinned_asids++;
> + __set_bit(asid2idx(asid), pinned_asid_map);
> + mm->context.pinned++;
> +
> +out_unlock:
> + raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
> +
> + return asid;
> +}
With CONFIG_UNMAP_KERNEL_AT_EL0 (a.k.a. KPTI), the hardware ASID has bit
0 set automatically when entering user space (and cleared when getting
back to the kernel). If the returned asid value here is going to be used
as is in the calling code, you should probably set bit 0 when KPTI is
enabled.
--
Catalin
^ permalink raw reply
* Re: [PATCH 10/12] platform/early: implement support for early platform drivers
From: Bartosz Golaszewski @ 2018-05-15 14:06 UTC (permalink / raw)
To: Rob Herring
Cc: Sekhar Nori, Kevin Hilman, David Lechner, Michael Turquette,
Stephen Boyd, Arnd Bergmann, Greg Kroah-Hartman, Mark Rutland,
Yoshinori Sato, Rich Felker, Andy Shevchenko, Marc Zyngier,
Rafael J . Wysocki, Peter Rosin, Jiri Slaby, Thomas Gleixner,
Daniel Lezcano, Geert Uytterhoeven, Magnus Damm, Johan Hovold
In-Reply-To: <CAL_JsqJw8UXktcLK8ADUfo1P+1un+omJ31sGcq7GFbNwJMsHKg@mail.gmail.com>
2018-05-14 15:37 GMT+02:00 Rob Herring <robh+dt@kernel.org>:
> On Fri, May 11, 2018 at 11:20 AM, Bartosz Golaszewski <brgl@bgdev.pl> wrote:
>> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>>
>> This introduces the core part of support for early platform drivers
>> and devices.
>>
>
> It looks like most of your prep patches are to separate the alloc and
> init of platform devices because you are essentially making early
> devices/drivers a sub-class. Maybe you could avoid doing that and
> simplify things a bit. Comments below based on doing that...
>
My aim was to change as little as possible for everybody else while
fixing our problem. These changes are already controversial enough
without risky reusing of existing fields in common structures. I was
just afraid that there are too many intricacies for it to be safe.
>> +/**
>> + * struct early_platform_driver
>> + *
>> + * @pdrv: real platform driver associated with this early platform driver
>> + * @list: list head for the list of early platform drivers
>> + * @early_probe: early probe callback
>> + */
>> +struct early_platform_driver {
>> + struct platform_driver pdrv;
>> + struct list_head list;
>
> Couldn't you use an existing list in driver_private until you move
> over to the normal bus infra.
>
This is something that the previous implementation did. It was quite
unreadable, so I decided to go with a separate list.
>> + int (*early_probe)(struct platform_device *);
>
> Just add this to platform_driver.
>
This would extend the structure for everybody else while there'll be
very few such devices and not all systems would even require it.
>> +};
>> +
>> +/**
>> + * struct early_platform_device
>> + *
>> + * @pdev: real platform device associated with this early platform device
>> + * @list: list head for the list of early platform devices
>> + * @deferred: true if this device's early probe was deferred
>> + * @deferred_drv: early platform driver with which this device was matched
>> + */
>> +struct early_platform_device {
>> + struct platform_device pdev;
>> + struct list_head list;
>
> Use a list in device_private?
>
>> + bool deferred;
>> + struct early_platform_driver *deferred_drv;
>
> Can't you use the existing deferred probe list?
>
I thought about it, but I was afraid there could be some timing issues
with that and decided against it. The early deferral also doesn't work
in a workque, but is synchronous instead.
Best regards,
Bartosz Golaszewski
^ permalink raw reply
* Re: [PATCH v6 1/4] drm/bridge: add support for sn65dsi86 bridge driver
From: Andrzej Hajda @ 2018-05-15 13:53 UTC (permalink / raw)
To: Sandeep Panda, dri-devel, linux-arm-msm, freedreno, devicetree
Cc: hoegsberg, chandanu, ryadav, abhinavk
In-Reply-To: <1526363564-13823-2-git-send-email-spanda@codeaurora.org>
On 15.05.2018 07:52, Sandeep Panda wrote:
> Add support for TI's sn65dsi86 dsi2edp bridge chip.
> The chip converts DSI transmitted signal to eDP signal,
> which is fed to the connected eDP panel.
>
> This chip can be controlled via either i2c interface or
> dsi interface. Currently in driver all the control registers
> are being accessed through i2c interface only.
> Also as of now HPD support has not been added to bridge
> chip driver.
>
> Changes in v1:
> - Split the dt-bindings and the driver support into separate patches
> (Andrzej Hajda).
> - Use of gpiod APIs to parse and configure gpios instead of obsolete ones
> (Andrzej Hajda).
> - Use macros to define the register offsets (Andrzej Hajda).
>
> Changes in v2:
> - Separate out edp panel specific HW resource handling from bridge
> driver and create a separate edp panel drivers to handle panel
> specific mode information and HW resources (Sean Paul).
> - Replace pr_* APIs to DRM_* APIs to log error or debug information
> (Sean Paul).
> - Remove some of the unnecessary structure/variable from driver (Sean
> Paul).
> - Rename the function and structure prefix "sn65dsi86" to "ti_sn_bridge"
> (Sean Paul / Rob Herring).
> - Remove most of the hard-coding and modified the bridge init sequence
> based on current mode (Sean Paul).
> - Remove the existing function to retrieve the EDID data and
> implemented this as an i2c_adapter and use drm_get_edid() (Sean Paul).
> - Remove the dummy irq handler implementation, will add back the
> proper irq handling later (Sean Paul).
> - Capture the required enable gpios in a single array based on dt entry
> instead of having individual descriptor for each gpio (Sean Paul).
>
> Changes in v3:
> - Remove usage of irq_gpio and replace it as "interrupts" property (Rob
> Herring).
> - Remove the unnecessary header file inclusions (Sean Paul).
> - Rearrange the header files in alphabetical order (Sean Paul).
> - Use regmap interface to perform i2c transactions.
> - Update Copyright/License field and address other review comments
> (Jordan Crouse).
>
> Changes in v4:
> - Update License/Copyright (Sean Paul).
> - Add Kconfig and Makefile changes (Sean Paul).
> - Drop i2c gpio handling from this bridge driver, since i2c sda/scl gpios
> will be handled by i2c master.
> - Update required supplies names.
> - Remove unnecessary goto statements (Sean Paul).
> - Add mutex lock to power_ctrl API to avoid race conditions (Sean
> Paul).
> - Add support to parse reference clk frequency from dt(optional).
> - Update the bridge chip enable/disable sequence.
>
> Changes in v5:
> - Fixed Kbuild test service reported warnings.
>
> Changes in v6:
> - Use PM runtime based ref-counting instead of local ref_count mechanism
> (Stephen Boyd).
> - Clean up some debug logs and indentations (Sean Paul).
> - Simplify dp rate calculation (Sean Paul).
> - Add support to configure refclk based on input REFCLK pin or DACP/N
> pin (Stephen Boyd).
>
> Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
> ---
> drivers/gpu/drm/bridge/Kconfig | 9 +
> drivers/gpu/drm/bridge/Makefile | 1 +
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 766 ++++++++++++++++++++++++++++++++++
> 3 files changed, 776 insertions(+)
> create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi86.c
>
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 3b99d5a..8153150 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -108,6 +108,15 @@ config DRM_TI_TFP410
> ---help---
> Texas Instruments TFP410 DVI/HDMI Transmitter driver
>
> +config DRM_TI_SN65DSI86
> + tristate "TI SN65DSI86 DSI to eDP bridge"
> + depends on OF
> + select DRM_KMS_HELPER
> + select REGMAP_I2C
> + select DRM_PANEL
> + ---help---
> + Texas Instruments SN65DSI86 DSI to eDP Bridge driver
> +
> source "drivers/gpu/drm/bridge/analogix/Kconfig"
>
> source "drivers/gpu/drm/bridge/adv7511/Kconfig"
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index 373eb28..3711be8 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -12,4 +12,5 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
> obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
> obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
> obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
> +obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
> obj-y += synopsys/
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> new file mode 100644
> index 0000000..1d3e549
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -0,0 +1,766 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <drm/drmP.h>
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_mipi_dsi.h>
> +#include <drm/drm_panel.h>
> +#include <linux/clk.h>
> +#include <linux/gpio.h>
> +#include <linux/i2c.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_graph.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +
> +#define SN_BRIDGE_REVISION_ID 0x2
> +
> +/* Link Training specific registers */
> +#define SN_DEVICE_REV_REG 0x08
> +#define SN_HPD_DISABLE_REG 0x5C
> +#define SN_REFCLK_FREQ_REG 0x0A
> +#define SN_DSI_LANES_REG 0x10
> +#define SN_DSIA_CLK_FREQ_REG 0x12
> +#define SN_ENH_FRAME_REG 0x5A
> +#define SN_SSC_CONFIG_REG 0x93
> +#define SN_DATARATE_CONFIG_REG 0x94
> +#define SN_PLL_ENABLE_REG 0x0D
> +#define SN_SCRAMBLE_CONFIG_REG 0x95
> +#define SN_AUX_WDATA0_REG 0x64
> +#define SN_AUX_ADDR_19_16_REG 0x74
> +#define SN_AUX_ADDR_15_8_REG 0x75
> +#define SN_AUX_ADDR_7_0_REG 0x76
> +#define SN_AUX_LENGTH_REG 0x77
> +#define SN_AUX_CMD_REG 0x78
> +#define SN_ML_TX_MODE_REG 0x96
> +/* video config specific registers */
> +#define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
> +#define SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG 0x21
> +#define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
> +#define SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG 0x25
> +#define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
> +#define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
> +#define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
> +#define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
> +#define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
> +#define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
> +#define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
> +#define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
> +#define SN_DATA_FORMAT_REG 0x5B
> +
> +#define MIN_DSI_CLK_FREQ_MHZ 40
> +
> +/* fudge factor required to account for 8b/10b encoding */
> +#define DP_CLK_FUDGE_NUM 10
> +#define DP_CLK_FUDGE_DEN 8
> +
> +#define DPPLL_CLK_SRC_REFCLK 0
> +#define DPPLL_CLK_SRC_DSICLK 1
> +
> +#define SN_DSIA_REFCLK_OFFSET 1
> +#define SN_DSIA_LANE_OFFSET 3
> +#define SN_DP_LANE_OFFSET 4
> +#define SN_DP_DATA_RATE_OFFSET 5
> +#define SN_TIMING_HIGH_OFFSET 8
> +
> +#define SN_ENABLE_VID_STREAM_BIT BIT(3)
> +#define SN_DSIA_NUM_LANES_BITS (BIT(4) | BIT(3))
> +#define SN_DP_NUM_LANES_BITS (BIT(5) | BIT(4))
> +#define SN_DP_DATA_RATE_BITS (BIT(7) | BIT(6) | BIT(5))
> +#define SN_HPD_DISABLE_BIT BIT(0)
> +
> +struct ti_sn_bridge {
> + struct device *dev;
> + struct regmap *regmap;
I have not spotted who advised you to use regmap, I think unless you
share hardware between multiple drivers it is an overkill.
Are there any features of this interface to use it over i2c?
> + struct drm_bridge bridge;
> + struct drm_connector connector;
> + struct device_node *host_node;
> + struct mipi_dsi_device *dsi;
> + struct clk *refclk;
> + struct drm_panel *panel;
> + struct gpio_desc *enable_gpio;
> + unsigned int num_supplies;
> + struct regulator_bulk_data *supplies;
> + struct i2c_adapter *ddc;
> + struct drm_display_mode curr_mode;
I think you can drop this field, current mode is always available via:
pdata->bridge.encoder.crtc->state->adjusted_mode;
> +};
> +
> +static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
> + { .range_min = 0, .range_max = 0xff },
> +};
> +
> +static const struct regmap_access_table ti_sn_bridge_volatile_table = {
> + .yes_ranges = ti_sn_bridge_volatile_ranges,
> + .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges),
> +};
> +
> +static const struct regmap_config ti_sn_bridge_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 8,
> + .volatile_table = &ti_sn_bridge_volatile_table,
> + .cache_type = REGCACHE_NONE,
> +};
> +
> +#ifdef CONFIG_PM
Please mark PM callbacks with __maybe_unused instead if conditional macros.
> +static int ti_sn_bridge_resume(struct device *dev)
> +{
> + struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
> + int ret = 0;
> +
> + ret = regulator_bulk_enable(pdata->num_supplies, pdata->supplies);
> + if (ret) {
> + DRM_ERROR("failed to enable supplies %d\n", ret);
> + return ret;
> + }
> +
> + gpiod_set_value(pdata->enable_gpio, 1);
> +
> + return ret;
> +}
> +
> +static int ti_sn_bridge_suspend(struct device *dev)
> +{
> + struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
> + int ret = 0;
> +
> + gpiod_set_value(pdata->enable_gpio, 0);
> +
> + ret = regulator_bulk_disable(pdata->num_supplies, pdata->supplies);
> + if (ret)
> + DRM_ERROR("failed to disable supplies %d\n", ret);
> +
> + return ret;
> +}
> +#endif
> +
> +static const struct dev_pm_ops ti_sn_bridge_pm_ops = {
> + SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL)
> +};
> +
> +/* Connector funcs */
> +static struct ti_sn_bridge *
> +connector_to_ti_sn_bridge(struct drm_connector *connector)
> +{
> + return container_of(connector, struct ti_sn_bridge, connector);
> +}
> +
> +static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
> +{
> + struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
> + struct drm_panel *panel = pdata->panel;
> + struct edid *edid;
> + u32 num_modes;
> +
> + if (panel) {
> + DRM_DEBUG_KMS("get mode from connected drm_panel\n");
> + return drm_panel_get_modes(panel);
> + }
> +
> + if (!pdata->ddc)
> + return 0;
> +
> + pm_runtime_get_sync(pdata->dev);
> + edid = drm_get_edid(connector, pdata->ddc);
> + pm_runtime_put_sync(pdata->dev);
> + if (!edid)
> + return 0;
> +
> + drm_mode_connector_update_edid_property(connector, edid);
> + num_modes = drm_add_edid_modes(connector, edid);
> + kfree(edid);
> +
> + return num_modes;
> +}
> +
> +static enum drm_mode_status
> +ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
> + struct drm_display_mode *mode)
> +{
> + /* maximum supported resolution is 4K at 60 fps */
> + if (mode->clock > 594000)
> + return MODE_CLOCK_HIGH;
> +
> + return MODE_OK;
> +}
> +
> +static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
> + .get_modes = ti_sn_bridge_connector_get_modes,
> + .mode_valid = ti_sn_bridge_connector_mode_valid,
> +};
> +
> +static enum drm_connector_status
> +ti_sn_bridge_connector_detect(struct drm_connector *connector, bool force)
> +{
> + struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
> +
> + /**
> + * TODO: Currently if drm_panel is present, then always
> + * return the status as connected. Need to add support to detect
> + * device state for no panel(hot pluggable) scenarios.
> + */
> + if (pdata->panel)
> + return connector_status_connected;
> + else
> + return connector_status_unknown;
> +}
> +
> +static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
> + .fill_modes = drm_helper_probe_single_connector_modes,
> + .detect = ti_sn_bridge_connector_detect,
> + .destroy = drm_connector_cleanup,
> + .reset = drm_atomic_helper_connector_reset,
> + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> +};
> +
> +static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge *bridge)
> +{
> + return container_of(bridge, struct ti_sn_bridge, bridge);
> +}
> +
> +static int ti_sn_bridge_read_device_rev(struct ti_sn_bridge *pdata)
> +{
> + unsigned int rev = 0;
> + int ret = 0;
> +
> + ret = regmap_read(pdata->regmap, SN_DEVICE_REV_REG, &rev);
> + if (ret) {
> + DRM_ERROR("Revision read failed %d\n", ret);
> + return ret;
> + }
> +
> + if (rev != SN_BRIDGE_REVISION_ID) {
> + DRM_ERROR("ti_sn_bridge revision id: 0x%x mismatch\n", rev);
> + ret = -EINVAL;
> + }
Are you sure it won't work with other revisions?
> +
> + return ret;
> +}
> +
> +static const char * const ti_sn_bridge_supply_names[] = {
> + "vcca",
> + "vcc",
> + "vccio",
> + "vpll",
> +};
> +
> +static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata)
> +{
> + unsigned int i;
> +
> + pdata->num_supplies = ARRAY_SIZE(ti_sn_bridge_supply_names);
> +
> + pdata->supplies = devm_kcalloc(pdata->dev, pdata->num_supplies,
> + sizeof(*pdata->supplies), GFP_KERNEL);
It seems there is constant number of supplies. You can convert supplies
to array and avoid dynamic allocation.
> + if (!pdata->supplies)
> + return -ENOMEM;
> +
> + for (i = 0; i < pdata->num_supplies; i++)
> + pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
> +
> + return devm_regulator_bulk_get(pdata->dev,
> + pdata->num_supplies, pdata->supplies);
> +}
> +
> +static int ti_sn_bridge_attach_panel(struct ti_sn_bridge *pdata)
> +{
> + struct device_node *panel_node, *port, *endpoint;
> +
> + pdata->panel = NULL;
> + port = of_graph_get_port_by_id(pdata->dev->of_node, 1);
> + if (!port)
> + return 0;
> +
> + endpoint = of_get_child_by_name(port, "endpoint");
> + of_node_put(port);
> + if (!endpoint) {
> + DRM_ERROR("no output endpoint found\n");
> + return -EINVAL;
> + }
Why not of_graph_get_endpoint_by_regs ?
> +
> + panel_node = of_graph_get_remote_port_parent(endpoint);
> + of_node_put(endpoint);
> + if (!panel_node) {
> + DRM_ERROR("no output node found\n");
> + return -EINVAL;
> + }
Or even of_graph_get_remote_node?
> +
> + pdata->panel = of_drm_find_panel(panel_node);
> + of_node_put(panel_node);
Or even, even drm_of_find_panel_or_bridge ? :)
> + if (!pdata->panel) {
> + DRM_ERROR("no panel node found\n");
> + return -EINVAL;
You should probably return -EPROBE_DEFER here.
> + }
> + drm_panel_attach(pdata->panel, &pdata->connector);
> + DRM_DEBUG_KMS("drm panel attached to ti_sn_bridge\n");
> +
> + return 0;
> +}
> +
> +static int ti_sn_bridge_attach(struct drm_bridge *bridge)
> +{
> + struct mipi_dsi_host *host;
> + struct mipi_dsi_device *dsi;
> + struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
> + int ret;
> + const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
> + .channel = 0,
> + .node = NULL,
> + };
> +
> + if (!bridge->encoder) {
> + DRM_ERROR("Parent encoder object not found\n");
> + return -ENODEV;
> + }
> +
> + /* HPD not supported */
> + pdata->connector.polled = 0;
You can skip this line.
> +
> + ret = drm_connector_init(bridge->dev, &pdata->connector,
> + &ti_sn_bridge_connector_funcs,
> + DRM_MODE_CONNECTOR_eDP);
> + if (ret) {
> + DRM_ERROR("Failed to initialize connector with drm\n");
> + return ret;
> + }
> +
> + drm_connector_helper_add(&pdata->connector,
> + &ti_sn_bridge_connector_helper_funcs);
> + drm_mode_connector_attach_encoder(&pdata->connector, bridge->encoder);
> +
> + host = of_find_mipi_dsi_host_by_node(pdata->host_node);
> + if (!host) {
> + DRM_ERROR("failed to find dsi host\n");
> + return -ENODEV;
Again -EPROBE_DEFER.
> + }
> +
> + dsi = mipi_dsi_device_register_full(host, &info);
> + if (IS_ERR(dsi)) {
> + DRM_ERROR("failed to create dsi device\n");
> + ret = PTR_ERR(dsi);
> + return ret;
> + }
> +
> + /* TODO: setting to 4 lanes always for now */
> + dsi->lanes = 4;
> + dsi->format = MIPI_DSI_FMT_RGB888;
> + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
> + MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
> +
> + ret = mipi_dsi_attach(dsi);
> + if (ret < 0) {
> + DRM_ERROR("failed to attach dsi to host\n");
> + mipi_dsi_device_unregister(dsi);
> + return ret;
> + }
> +
> + pdata->dsi = dsi;
> +
> + DRM_DEBUG_KMS("ti_sn_bridge attached to dsi\n");
> + /* attach panel to bridge */
> + ti_sn_bridge_attach_panel(pdata);
Function can fail, you should handle it.
> +
> + return 0;
> +}
> +
> +static void ti_sn_bridge_mode_set(struct drm_bridge *bridge,
> + struct drm_display_mode *mode,
> + struct drm_display_mode *adj_mode)
> +{
> + struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
> +
> + DRM_DEBUG("mode_set: hdisplay=%d, vdisplay=%d, vrefresh=%d, clock=%d\n",
> + adj_mode->hdisplay, adj_mode->vdisplay,
> + adj_mode->vrefresh, adj_mode->clock);
> +
> + drm_mode_copy(&pdata->curr_mode, adj_mode);
> +}
This callback can be dropped, see comment for curr_mode.
> +
> +static void ti_sn_bridge_disable(struct drm_bridge *bridge)
> +{
> + struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
> + struct drm_panel *panel = pdata->panel;
> +
> + if (panel) {
> + drm_panel_disable(panel);
> + drm_panel_unprepare(panel);
> + }
> +
> + /* disable video stream */
> + regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG,
> + SN_ENABLE_VID_STREAM_BIT, 0);
> + /* semi auto link training mode OFF */
> + regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
> + /* disable DP PLL */
> + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
> +}
> +
> +static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge *pdata)
> +{
> + u32 bit_rate_khz, clk_freq_khz;
> + struct drm_display_mode *mode = &pdata->curr_mode;
> +
> + bit_rate_khz = mode->clock *
> + mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
> + clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
> +
> + return clk_freq_khz;
> +}
> +
> +#define REFCLK_LUT_SIZE 5
> +
> +/* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
> +static const u32 ti_sn_bridge_refclk_lut[] = {
> + 12000000,
> + 19200000,
> + 26000000,
> + 27000000,
> + 38400000,
> +};
> +
> +/* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
> +static const u32 ti_sn_bridge_dsiclk_lut[] = {
> + 468000000,
> + 384000000,
> + 416000000,
> + 486000000,
> + 460800000,
> +};
> +
> +static void ti_sn_bridge_set_refclk(struct ti_sn_bridge *pdata)
> +{
> + int i = 0;
> + u8 refclk_src;
> + u32 refclk_rate;
> + const u32 *refclk_lut;
> +
> + if (pdata->refclk) {
> + refclk_src = DPPLL_CLK_SRC_REFCLK;
> + refclk_rate = clk_get_rate(pdata->refclk);
> + refclk_lut = ti_sn_bridge_refclk_lut;
> + clk_prepare_enable(pdata->refclk);
> + } else {
> + refclk_src = DPPLL_CLK_SRC_DSICLK;
> + refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
> + refclk_lut = ti_sn_bridge_dsiclk_lut;
> + }
> +
> + /* for i equals to REFCLK_LUT_SIZE means default frequency */
> + for (i = 0; i < REFCLK_LUT_SIZE; i++)
> + if (refclk_lut[i] == refclk_rate)
> + break;
> +
> + regmap_write(pdata->regmap, SN_REFCLK_FREQ_REG,
> + (refclk_src | (i << SN_DSIA_REFCLK_OFFSET)));
> +}
> +
> +/**
> + * LUT index corresponds to register value and
> + * LUT values corresponds to dp data rate supported
> + * by the bridge in Mbps unit.
> + */
> +static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
> + 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
> +};
> +
> +static void ti_sn_bridge_set_dsi_dp_rate(struct ti_sn_bridge *pdata)
> +{
> + unsigned int bit_rate_mhz, clk_freq_mhz, dp_rate_mhz;
> + unsigned int val = 0, i = 0;
> + struct drm_display_mode *mode = &pdata->curr_mode;
> +
> + /* set DSIA clk frequency */
> + bit_rate_mhz = (mode->clock / 1000) *
> + mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
> + clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
> +
> + /* for each increment in val, frequency increases by 5MHz */
> + val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
> + (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
> + regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
> +
> + /* set DP data rate */
> + dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) /
> + DP_CLK_FUDGE_DEN;
> + for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++)
> + if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz)
> + break;
> + if (i == ARRAY_SIZE(ti_sn_bridge_dp_rate_lut))
> + i--; /* set to maximum possible */
Just use: for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
> +
> + regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
> + SN_DP_DATA_RATE_BITS, i << SN_DP_DATA_RATE_OFFSET);
> +}
> +
> +static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
> +{
> + struct drm_display_mode *mode = &pdata->curr_mode;
> +
> + regmap_write(pdata->regmap, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
> + mode->hdisplay & 0xFF);
> + regmap_write(pdata->regmap, SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG,
> + (mode->hdisplay >> SN_TIMING_HIGH_OFFSET) & 0xFF);
> + regmap_write(pdata->regmap, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
> + mode->vdisplay & 0xFF);
> + regmap_write(pdata->regmap, SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG,
> + (mode->vdisplay >> SN_TIMING_HIGH_OFFSET) & 0xFF);
> + regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
> + (mode->hsync_end - mode->hsync_start) & 0xFF);
> + regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
> + ((mode->hsync_end - mode->hsync_start) >>
> + SN_TIMING_HIGH_OFFSET) & 0xFF);
> + regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
> + (mode->vsync_end - mode->vsync_start) & 0xFF);
> + regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
> + ((mode->vsync_end - mode->vsync_start) >>
> + SN_TIMING_HIGH_OFFSET) & 0xFF);
> + regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
> + (mode->htotal - mode->hsync_end) & 0xFF);
> + regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
> + (mode->vtotal - mode->vsync_end) & 0xFF);
> + regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
> + (mode->hsync_start - mode->hdisplay) & 0xFF);
> + regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
> + (mode->vsync_start - mode->vdisplay) & 0xFF);
> + usleep_range(10000, 10500); /* 10ms delay recommended by spec */
> +}
> +
> +static void ti_sn_bridge_enable(struct drm_bridge *bridge)
> +{
> + struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
> + struct drm_panel *panel = pdata->panel;
> + unsigned int val = 0;
> +
> + if (panel) {
> + drm_panel_prepare(panel);
> + /* in case drm_panel is connected then HPD is not supported */
> + regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG,
> + SN_HPD_DISABLE_BIT, SN_HPD_DISABLE_BIT);
> + }
> +
> + /* DSI_A lane config */
> + val = (4 - pdata->dsi->lanes) << SN_DSIA_LANE_OFFSET;
> + regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
> + SN_DSIA_NUM_LANES_BITS, val);
> +
> + /* DP lane config */
> + val = (pdata->dsi->lanes - 1) << SN_DP_LANE_OFFSET;
> + regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG,
> + SN_DP_NUM_LANES_BITS, val);
> +
> + /* set dsi/dp clk frequency value */
> + ti_sn_bridge_set_dsi_dp_rate(pdata);
> +
> + /* enable DP PLL */
> + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
> + usleep_range(10000, 10500); /* 10ms delay recommended by spec */
> +
> + /**
> + * The SN65DSI86 only supports ASSR Display Authentication method and
> + * this method is enabled by default. An eDP panel must support this
> + * authentication method. We need to enable this method in the eDP panel
> + * at DisplayPort address 0x0010A prior to link training.
> + */
> + regmap_write(pdata->regmap, SN_AUX_WDATA0_REG, 0x01);
> + regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, 0x00);
> + regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG, 0x01);
> + regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, 0x0A);
> + regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, 0x01);
> + regmap_write(pdata->regmap, SN_AUX_CMD_REG, 0x81);
> + usleep_range(10000, 10500); /* 10ms delay recommended by spec */
> +
> + /* Semi auto link training mode */
> + regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
> + msleep(20); /* 20ms delay recommended by spec */
> +
> + /* config video parameters */
> + ti_sn_bridge_set_video_timings(pdata);
> +
> + /* enable video stream */
> + regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG,
> + SN_ENABLE_VID_STREAM_BIT, SN_ENABLE_VID_STREAM_BIT);
> +
> + if (panel)
> + drm_panel_enable(panel);
> +}
> +
> +static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
> +{
> + struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
> +
> + pm_runtime_get_sync(pdata->dev);
> +
> + /* configure bridge CLK_SRC and ref_clk */
> + ti_sn_bridge_set_refclk(pdata);
> +}
> +
> +static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
> +{
> + struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
> +
> + if (pdata->refclk)
> + clk_disable_unprepare(pdata->refclk);
> +
> + pm_runtime_put_sync(pdata->dev);
> +}
> +
> +static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
> + .attach = ti_sn_bridge_attach,
> + .pre_enable = ti_sn_bridge_pre_enable,
> + .enable = ti_sn_bridge_enable,
> + .disable = ti_sn_bridge_disable,
> + .post_disable = ti_sn_bridge_post_disable,
> + .mode_set = ti_sn_bridge_mode_set,
> +};
> +
> +static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata)
> +{
> + struct device_node *np = pdata->dev->of_node;
> + struct device_node *end_node;
> +
> + end_node = of_graph_get_endpoint_by_regs(np, 0, 0);
> + if (!end_node) {
> + DRM_ERROR("remote endpoint not found\n");
> + return -ENODEV;
> + }
> +
> + pdata->host_node = of_graph_get_remote_port_parent(end_node);
> + of_node_put(end_node);
> + if (!pdata->host_node) {
> + DRM_ERROR("remote node not found\n");
> + return -ENODEV;
> + }
> + of_node_put(pdata->host_node);
Why not of_graph_get_remote_node ?
> +
> + return 0;
> +}
> +
> +static int ti_sn_bridge_probe(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + struct ti_sn_bridge *pdata;
> + struct device_node *ddc_node;
> + int ret = 0;
> +
> + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
> + DRM_ERROR("device doesn't support I2C\n");
> + return -ENODEV;
> + }
> +
> + pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge),
> + GFP_KERNEL);
> + if (!pdata)
> + return -ENOMEM;
> +
> + pdata->dev = &client->dev;
> + dev_set_drvdata(&client->dev, pdata);
> +
> + pdata->regmap = devm_regmap_init_i2c(client,
> + &ti_sn_bridge_regmap_config);
> + if (IS_ERR(pdata->regmap)) {
> + DRM_ERROR("regmap i2c init failed\n");
> + return PTR_ERR(pdata->regmap);
> + }
> +
> + pdata->enable_gpio = devm_gpiod_get(pdata->dev,
> + "enable", GPIOD_OUT_LOW);
> + if (IS_ERR(pdata->enable_gpio)) {
> + DRM_ERROR("failed to get enable gpio from DT\n");
> + ret = PTR_ERR(pdata->enable_gpio);
> + return ret;
> + }
> +
> + ret = ti_sn_bridge_parse_regulators(pdata);
> + if (ret) {
> + DRM_ERROR("failed to parse regulators\n");
> + return ret;
> + }
> +
> + ret = ti_sn_bridge_parse_dsi_host(pdata);
> + if (ret)
> + return ret;
> +
> + pm_runtime_enable(pdata->dev);
> + pm_runtime_get_sync(pdata->dev);
> + ret = ti_sn_bridge_read_device_rev(pdata);
> + pm_runtime_put_sync(pdata->dev);
I would put it into (pre) enable callbacks, maybe with marking it to run
only once.
Regards
Andrzej
> + if (ret)
> + goto err_rev_read;
> +
> + pdata->refclk = devm_clk_get(pdata->dev, "refclk");
> +
> + ddc_node = of_parse_phandle(pdata->dev->of_node, "ddc-i2c-bus", 0);
> + if (ddc_node) {
> + pdata->ddc = of_find_i2c_adapter_by_node(ddc_node);
> + of_node_put(ddc_node);
> + if (!pdata->ddc) {
> + DRM_DEBUG_KMS("failed to read ddc node\n");
> + ret = -EPROBE_DEFER;
> + goto err_rev_read;
> + }
> + } else {
> + DRM_DEBUG_KMS("no ddc property found\n");
> + }
> +
> + i2c_set_clientdata(client, pdata);
> +
> + pdata->bridge.funcs = &ti_sn_bridge_funcs;
> + pdata->bridge.of_node = client->dev.of_node;
> +
> + drm_bridge_add(&pdata->bridge);
> +
> + return 0;
> +
> +err_rev_read:
> + pm_runtime_disable(pdata->dev);
> + return ret;
> +}
> +
> +static int ti_sn_bridge_remove(struct i2c_client *client)
> +{
> + struct ti_sn_bridge *pdata = i2c_get_clientdata(client);
> +
> + if (!pdata)
> + return -EINVAL;
> +
> + mipi_dsi_detach(pdata->dsi);
> + mipi_dsi_device_unregister(pdata->dsi);
> +
> + drm_bridge_remove(&pdata->bridge);
> + pm_runtime_disable(pdata->dev);
> + i2c_put_adapter(pdata->ddc);
> +
> + return 0;
> +}
> +
> +static struct i2c_device_id ti_sn_bridge_id[] = {
> + { "ti,sn65dsi86", 0},
> + {},
> +};
> +MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id);
> +
> +static const struct of_device_id ti_sn_bridge_match_table[] = {
> + {.compatible = "ti,sn65dsi86"},
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table);
> +
> +static struct i2c_driver ti_sn_bridge_driver = {
> + .driver = {
> + .name = "ti_sn65dsi86",
> + .of_match_table = ti_sn_bridge_match_table,
> + .pm = &ti_sn_bridge_pm_ops,
> + },
> + .probe = ti_sn_bridge_probe,
> + .remove = ti_sn_bridge_remove,
> + .id_table = ti_sn_bridge_id,
> +};
> +
> +module_i2c_driver(ti_sn_bridge_driver);
> +MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
> +MODULE_LICENSE("GPL v2");
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^ permalink raw reply
* [PATCH v3 6/6] drm/rockchip: dw_hdmi: add dw-hdmi support for the rk3328
From: Heiko Stuebner @ 2018-05-15 13:47 UTC (permalink / raw)
To: architt, a.hajda
Cc: mark.rutland, Jose.Abreu, algea.cao, devicetree, dri-devel,
linux-rockchip, robh+dt, Laurent.pinchart, linux-arm-kernel,
zhengyang
In-Reply-To: <20180515134736.5824-1-heiko@sntech.de>
The rk3328 uses a dw-hdmi controller with an external hdmi phy from
Innosilicon which uses the generic phy framework for access.
Add the necessary data and the compatible for the rk3328 to the
rockchip dw-hdmi driver.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Robin Murphy <robin.murphy@arm.com>
---
changes in v3:
- reword as suggested by Rob to show that it's a dw-hdmi + Inno phy
.../display/rockchip/dw_hdmi-rockchip.txt | 1 +
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 106 ++++++++++++++++++
2 files changed, 107 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
index 937bfb472e1d..39143424a474 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
@@ -13,6 +13,7 @@ Required properties:
- compatible: should be one of the following:
"rockchip,rk3288-dw-hdmi"
+ "rockchip,rk3328-dw-hdmi"
"rockchip,rk3399-dw-hdmi"
- reg: See dw_hdmi.txt.
- reg-io-width: See dw_hdmi.txt. Shall be 4.
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 19f002fa0a09..237f31fd8403 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -25,6 +25,24 @@
#define RK3288_GRF_SOC_CON6 0x025C
#define RK3288_HDMI_LCDC_SEL BIT(4)
+#define RK3328_GRF_SOC_CON2 0x0408
+
+#define RK3328_HDMI_SDAIN_MSK BIT(11)
+#define RK3328_HDMI_SCLIN_MSK BIT(10)
+#define RK3328_HDMI_HPD_IOE BIT(2)
+#define RK3328_GRF_SOC_CON3 0x040c
+/* need to be unset if hdmi or i2c should control voltage */
+#define RK3328_HDMI_SDA5V_GRF BIT(15)
+#define RK3328_HDMI_SCL5V_GRF BIT(14)
+#define RK3328_HDMI_HPD5V_GRF BIT(13)
+#define RK3328_HDMI_CEC5V_GRF BIT(12)
+#define RK3328_GRF_SOC_CON4 0x0410
+#define RK3328_HDMI_HPD_SARADC BIT(13)
+#define RK3328_HDMI_CEC_5V BIT(11)
+#define RK3328_HDMI_SDA_5V BIT(10)
+#define RK3328_HDMI_SCL_5V BIT(9)
+#define RK3328_HDMI_HPD_5V BIT(8)
+
#define RK3399_GRF_SOC_CON20 0x6250
#define RK3399_HDMI_LCDC_SEL BIT(6)
@@ -292,6 +310,68 @@ static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_fun
.atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
};
+static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
+ struct drm_display_mode *mode)
+{
+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
+
+ return phy_power_on(hdmi->phy);
+}
+
+static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data)
+{
+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
+
+ phy_power_off(hdmi->phy);
+}
+
+static enum drm_connector_status
+dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data)
+{
+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
+ enum drm_connector_status status;
+
+ status = dw_hdmi_phy_read_hpd(dw_hdmi, data);
+
+ if (status == connector_status_connected)
+ regmap_write(hdmi->regmap,
+ RK3328_GRF_SOC_CON4,
+ HIWORD_UPDATE(RK3328_HDMI_CEC_5V | RK3328_HDMI_SDA_5V |
+ RK3328_HDMI_SCL_5V,
+ RK3328_HDMI_CEC_5V | RK3328_HDMI_SDA_5V |
+ RK3328_HDMI_SCL_5V));
+ else
+ regmap_write(hdmi->regmap,
+ RK3328_GRF_SOC_CON4,
+ HIWORD_UPDATE(0,
+ RK3328_HDMI_CEC_5V | RK3328_HDMI_SDA_5V |
+ RK3328_HDMI_SCL_5V));
+ return status;
+}
+
+static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
+{
+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
+
+ dw_hdmi_phy_setup_hpd(dw_hdmi, data);
+
+ /* Enable and map pins to 3V grf-controlled io-voltage */
+ regmap_write(hdmi->regmap,
+ RK3328_GRF_SOC_CON4,
+ HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |
+ RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V |
+ RK3328_HDMI_HPD_5V));
+ regmap_write(hdmi->regmap,
+ RK3328_GRF_SOC_CON3,
+ HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |
+ RK3328_HDMI_HPD5V_GRF | RK3328_HDMI_CEC5V_GRF));
+ regmap_write(hdmi->regmap,
+ RK3328_GRF_SOC_CON2,
+ HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,
+ RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK |
+ RK3328_HDMI_HPD_IOE));
+}
+
static struct rockchip_hdmi_chip_data rk3288_chip_data = {
.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
.lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
@@ -306,6 +386,29 @@ static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
.phy_data = &rk3288_chip_data,
};
+static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = {
+ .init = dw_hdmi_rockchip_genphy_init,
+ .disable = dw_hdmi_rockchip_genphy_disable,
+ .read_hpd = dw_hdmi_rk3328_read_hpd,
+ .update_hpd = dw_hdmi_phy_update_hpd,
+ .setup_hpd = dw_hdmi_rk3328_setup_hpd,
+};
+
+static struct rockchip_hdmi_chip_data rk3328_chip_data = {
+ .lcdsel_grf_reg = -1,
+};
+
+static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
+ .mode_valid = dw_hdmi_rockchip_mode_valid,
+ .mpll_cfg = rockchip_mpll_cfg,
+ .cur_ctr = rockchip_cur_ctr,
+ .phy_config = rockchip_phy_config,
+ .phy_data = &rk3328_chip_data,
+ .phy_ops = &rk3328_hdmi_phy_ops,
+ .phy_name = "inno_dw_hdmi_phy2",
+ .phy_force_vendor = true,
+};
+
static struct rockchip_hdmi_chip_data rk3399_chip_data = {
.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
.lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
@@ -324,6 +427,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
{ .compatible = "rockchip,rk3288-dw-hdmi",
.data = &rk3288_hdmi_drv_data
},
+ { .compatible = "rockchip,rk3328-dw-hdmi",
+ .data = &rk3328_hdmi_drv_data
+ },
{ .compatible = "rockchip,rk3399-dw-hdmi",
.data = &rk3399_hdmi_drv_data
},
--
2.17.0
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^ permalink raw reply related
* [PATCH v3 5/6] drm/rockchip: dw_hdmi: store rockchip_hdmi reference in phy_data object
From: Heiko Stuebner @ 2018-05-15 13:47 UTC (permalink / raw)
To: architt, a.hajda
Cc: mark.rutland, Jose.Abreu, algea.cao, devicetree, dri-devel,
linux-rockchip, robh+dt, Laurent.pinchart, linux-arm-kernel,
zhengyang
In-Reply-To: <20180515134736.5824-1-heiko@sntech.de>
When using special phy handling operations we'll often need access to
the rockchip_hdmi struct.
As the chip-data that occupies the phy_data pointer initially gets
assigned to the rockchip_hdmi struct, we can now re-use this phy_data
pointer to hold the reference to the rockchip_hdmi struct and use this
reference later on.
Inspiration for this comes from meson and sunxi dw-hdmi, which are using
the same method.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Robin Murphy <robin.murphy@arm.com>
---
changes in v3:
- reword commit message
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 57e76dfd5f6d..19f002fa0a09 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -335,7 +335,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
void *data)
{
struct platform_device *pdev = to_platform_device(dev);
- const struct dw_hdmi_plat_data *plat_data;
+ struct dw_hdmi_plat_data *plat_data;
const struct of_device_id *match;
struct drm_device *drm = data;
struct drm_encoder *encoder;
@@ -350,9 +350,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
return -ENOMEM;
match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
- plat_data = match->data;
+ plat_data = devm_kmemdup(&pdev->dev, match->data,
+ sizeof(*plat_data), GFP_KERNEL);
+ if (!plat_data)
+ return -ENOMEM;
+
hdmi->dev = &pdev->dev;
hdmi->chip_data = plat_data->phy_data;
+ plat_data->phy_data = hdmi;
encoder = &hdmi->encoder;
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
--
2.17.0
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^ permalink raw reply related
* [PATCH v3 4/6] drm/rockchip: dw_hdmi: allow including external phys
From: Heiko Stuebner @ 2018-05-15 13:47 UTC (permalink / raw)
To: architt, a.hajda
Cc: mark.rutland, Jose.Abreu, algea.cao, devicetree, dri-devel,
linux-rockchip, robh+dt, Laurent.pinchart, linux-arm-kernel,
zhengyang
In-Reply-To: <20180515134736.5824-1-heiko@sntech.de>
Some variants of the dw-hdmi on Rockchip socs use a separate phy block
accessed via the generic phy framework, so allow them to be included
if such a phy reference is found.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Robin Murphy <robin.murphy@arm.com>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index b09c3531305b..57e76dfd5f6d 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -11,6 +11,7 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
#include <linux/regmap.h>
#include <drm/drm_of.h>
@@ -49,6 +50,7 @@ struct rockchip_hdmi {
struct clk *vpll_clk;
struct clk *grf_clk;
struct dw_hdmi *hdmi;
+ struct phy *phy;
};
#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
@@ -376,6 +378,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
return ret;
}
+ hdmi->phy = devm_phy_optional_get(dev, "hdmi");
+ if (IS_ERR(hdmi->phy)) {
+ ret = PTR_ERR(hdmi->phy);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n");
+ return ret;
+ }
+
drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
DRM_MODE_ENCODER_TMDS, NULL);
--
2.17.0
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^ permalink raw reply related
* [PATCH v3 3/6] dt-bindings: allow optional phys in Rockchip dw_hdmi binding
From: Heiko Stuebner @ 2018-05-15 13:47 UTC (permalink / raw)
To: architt, a.hajda
Cc: mark.rutland, Jose.Abreu, algea.cao, devicetree, dri-devel,
linux-rockchip, robh+dt, Laurent.pinchart, linux-arm-kernel,
zhengyang
In-Reply-To: <20180515134736.5824-1-heiko@sntech.de>
Some newer Rockchip SoCs use an Innosilicon hdmiphy accessed via general
mmio, so allow these to be referenced via the regular phy interfaces
and therefore add optional phy-related properties to the binding.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
index adc94fc3c9f8..937bfb472e1d 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
@@ -34,6 +34,8 @@ Optional properties
- clock-names: May contain "cec" as defined in dw_hdmi.txt.
- clock-names: May contain "grf", power for grf io.
- clock-names: May contain "vpll", external clock for some hdmi phy.
+- phys: from general PHY binding: the phandle for the PHY device.
+- phy-names: Should be "hdmi" if phys references an external phy.
Example:
--
2.17.0
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^ permalink raw reply related
* [PATCH v3 2/6] drm/rockchip: dw_hdmi: Allow outputs that don't need output switching
From: Heiko Stuebner @ 2018-05-15 13:47 UTC (permalink / raw)
To: architt, a.hajda
Cc: mark.rutland, Jose.Abreu, algea.cao, devicetree, dri-devel,
linux-rockchip, robh+dt, Laurent.pinchart, linux-arm-kernel,
zhengyang
In-Reply-To: <20180515134736.5824-1-heiko@sntech.de>
So far we always encountered socs with 2 output crtcs needing the driver
to tell the hdmi block which output to connect to. But there also exist
socs with only one crtc like the rk3228, rk3328 and rk3368.
So adapt the register field to simply carry a negative value to signal
that no output-switching is necessary.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Robin Murphy <robin.murphy@arm.com>
---
changes in v3:
- fixed wording issue found by Robin Murphy
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 11309a2a4e43..b09c3531305b 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -36,7 +36,7 @@
* @lcdsel_lit: reg value of selecting vop little for HDMI
*/
struct rockchip_hdmi_chip_data {
- u32 lcdsel_grf_reg;
+ int lcdsel_grf_reg;
u32 lcdsel_big;
u32 lcdsel_lit;
};
@@ -245,6 +245,9 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
u32 val;
int ret;
+ if (hdmi->chip_data->lcdsel_grf_reg < 0)
+ return;
+
ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
if (ret)
val = hdmi->chip_data->lcdsel_lit;
--
2.17.0
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^ permalink raw reply related
* [PATCH v3 1/6] drm/bridge: dw-hdmi: allow forcing vendor phy-type
From: Heiko Stuebner @ 2018-05-15 13:47 UTC (permalink / raw)
To: architt, a.hajda
Cc: mark.rutland, Jose.Abreu, algea.cao, devicetree, dri-devel,
linux-rockchip, robh+dt, Laurent.pinchart, linux-arm-kernel,
zhengyang
In-Reply-To: <20180515134736.5824-1-heiko@sntech.de>
In some IP implementations the reading of the phy-type may be broken.
One example are the Rockchip rk3228 and rk3328 socs that use a separate
vendor-type phy from Innosilicon but still report the HDMI20_TX type.
So allow the glue driver to force the vendor-phy for these cases.
In the future it may be necessary to allow forcing other types, but
for now we'll keep it simply to the case actually seen in the wild.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Robin Murphy <robin.murphy@arm.com>
---
changes in v3:
- only allow forcing vendor type, as suggested by Laurent
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 +++-
include/drm/bridge/dw_hdmi.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index ec8d0006ef7c..4de82ced9370 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2212,7 +2212,9 @@ static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
unsigned int i;
u8 phy_type;
- phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID);
+ phy_type = hdmi->plat_data->phy_force_vendor ?
+ DW_HDMI_PHY_VENDOR_PHY :
+ hdmi_readb(hdmi, HDMI_CONFIG2_ID);
if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
/* Vendor PHYs require support from the glue layer. */
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index dd2a8cf7d20b..53f0ce9aeb4a 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -133,6 +133,7 @@ struct dw_hdmi_plat_data {
const struct dw_hdmi_phy_ops *phy_ops;
const char *phy_name;
void *phy_data;
+ bool phy_force_vendor;
/* Synopsys PHY support */
const struct dw_hdmi_mpll_config *mpll_cfg;
--
2.17.0
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^ permalink raw reply related
* [PATCH v3 0/6] drm/rockchip: hdmi support for rk3328
From: Heiko Stuebner @ 2018-05-15 13:47 UTC (permalink / raw)
To: architt, a.hajda
Cc: mark.rutland, Jose.Abreu, algea.cao, devicetree, dri-devel,
linux-rockchip, robh+dt, Laurent.pinchart, linux-arm-kernel,
zhengyang
The rk3228/rk3229 and rk3328 socs started using a new type of hdmi-phy
from Innosilicon that resides completely separate from the dw-hdmi block
and gets accessed via mmio.
Additionally the rk3328 dw-hdmi does not report the vendor-phy type
but a different one instead, so add the possibility to override the
phy type when the glue driver knows better than the ip block itself.
changes in v3:
- split off phy driver into a separate series
- only allow forcing vendor phy type
- wording fixes and other nits
changes in v2:
- phy: prevent overflow in tmdsclk calculation
as reported by Martin Cerveny
- phy: use unsigned long for all tmdsclk rate uses
- phy: simplify tmds rate calculation
- dropped patch exporting some dw-hdmi phy functions
as a similar patch entered drm-misc already
Heiko Stuebner (6):
drm/bridge: dw-hdmi: allow forcing vendor phy-type
drm/rockchip: dw_hdmi: Allow outputs that don't need output switching
dt-bindings: allow optional phys in Rockchip dw_hdmi binding
drm/rockchip: dw_hdmi: allow including external phys
drm/rockchip: dw_hdmi: store rockchip_hdmi reference in phy_data
object
drm/rockchip: dw_hdmi: add dw-hdmi support for the rk3328
.../display/rockchip/dw_hdmi-rockchip.txt | 3 +
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 +-
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 130 +++++++++++++++++-
include/drm/bridge/dw_hdmi.h | 1 +
4 files changed, 134 insertions(+), 4 deletions(-)
--
2.17.0
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^ permalink raw reply
* Re: [PATCH v10 03/27] clk: davinci: psc: allow for dev == NULL
From: Sekhar Nori @ 2018-05-15 13:42 UTC (permalink / raw)
To: David Lechner, linux-clk, devicetree, linux-arm-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Kevin Hilman, Bartosz Golaszewski, Adam Ford, linux-kernel
In-Reply-To: <20180509172606.29387-4-david@lechnology.com>
On Wednesday 09 May 2018 10:55 PM, David Lechner wrote:
> @@ -261,10 +263,14 @@ davinci_lpsc_clk_register(struct device *dev, const char *name,
> lpsc->pd = pd;
> lpsc->flags = flags;
>
> - ret = devm_clk_hw_register(dev, &lpsc->hw);
> + ret = clk_hw_register(dev, &lpsc->hw);
> if (ret < 0)
> return ERR_PTR(ret);
>
> + /* for now, genpd is only registered when using device-tree */
> + if (!dev || !dev->of_node)
> + return lpsc;
> +
> /* genpd attach needs a way to look up this clock */
> ret = clk_hw_register_clkdev(&lpsc->hw, name, best_dev_name(dev));
>
> @@ -378,11 +384,11 @@ __davinci_psc_register_clocks(struct device *dev,
> struct regmap *regmap;
> int i, ret;
>
> - psc = devm_kzalloc(dev, sizeof(*psc), GFP_KERNEL);
> + psc = kzalloc(sizeof(*psc), GFP_KERNEL);
> if (!psc)
> return ERR_PTR(-ENOMEM);
>
> - clks = devm_kmalloc_array(dev, num_clks, sizeof(*clks), GFP_KERNEL);
> + clks = kmalloc_array(num_clks, sizeof(*clks), GFP_KERNEL);
> if (!clks)
> return ERR_PTR(-ENOMEM);
>
> @@ -396,14 +402,14 @@ __davinci_psc_register_clocks(struct device *dev,
> for (i = 0; i < num_clks; i++)
> clks[i] = ERR_PTR(-ENOENT);
>
> - pm_domains = devm_kcalloc(dev, num_clks, sizeof(*pm_domains), GFP_KERNEL);
> + pm_domains = kcalloc(num_clks, sizeof(*pm_domains), GFP_KERNEL);
> if (!pm_domains)
> return ERR_PTR(-ENOMEM);
>
> psc->pm_data.domains = pm_domains;
> psc->pm_data.num_domains = num_clks;
>
> - regmap = devm_regmap_init_mmio(dev, base, &davinci_psc_regmap_config);
> + regmap = regmap_init_mmio(dev, base, &davinci_psc_regmap_config);
> if (IS_ERR(regmap))
> return ERR_CAST(regmap);
Here and in the PLL driver, you have dropped the devm_* variants (like
agreed upon), but not added any error path handling. For the clocks
needed for boot, its probably fine, but the same code path is used for
non-essential clocks too. Just from a code completeness perspective, it
will be nice to see the error path correctly handled.
Apart from that both 1/27 and 3/27 look good to me.
Thanks,
Sekhar
^ permalink raw reply
* Re: [PATCH v4 1/3] drm/panel: Add RGB666 variant of Innolux AT070TN90
From: Maxime Ripard @ 2018-05-15 13:35 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Rob Herring, Mark Rutland,
Chen-Yu Tsai, Thierry Reding, David Airlie
In-Reply-To: <abeac1ee792b8f063001c4c280ca7f0167ac59be.camel-W9ppeneeCTY@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 5695 bytes --]
On Mon, May 14, 2018 at 10:40:15PM +0200, Paul Kocialkowski wrote:
> Le vendredi 11 mai 2018 à 10:59 +0200, Maxime Ripard a écrit :
> > On Wed, May 09, 2018 at 01:31:23PM +0200, Paul Kocialkowski wrote:
> > > On Wed, 2018-05-09 at 09:12 +0200, Maxime Ripard wrote:
> > > > On Tue, May 08, 2018 at 12:04:11AM +0200, Paul Kocialkowski wrote:
> > > > > This adds timings for the RGB666 variant of the Innolux AT070TN90 panel,
> > > > > as found on the Ainol AW1 tablet.
> > > > >
> > > > > The panel also supports RGB888 output. When RGB666 mode is used instead,
> > > > > the two extra lanes per component are grounded.
> > > > >
> > > > > In the future, it might become necessary to introduce a dedicated
> > > > > device-tree property to specify the bus format to use instead of the
> > > > > default one for the panel. This will allow supporting different bus
> > > > > formats for the same panel modes.
> > > > >
> > > > > Signed-off-by: Paul Kocialkowski <contact-W9ppeneeCTY@public.gmane.org>
> > > > > ---
> > > > > drivers/gpu/drm/panel/panel-simple.c | 26 ++++++++++++++++++++++++++
> > > > > 1 file changed, 26 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> > > > > index cbf1ab404ee7..32e30d5a8f08 100644
> > > > > --- a/drivers/gpu/drm/panel/panel-simple.c
> > > > > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > > > > @@ -1063,6 +1063,29 @@ static const struct panel_desc innolux_at043tn24 = {
> > > > > .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
> > > > > };
> > > > >
> > > > > +static const struct drm_display_mode innolux_at070tn90_mode = {
> > > > > + .clock = 40000,
> > > > > + .hdisplay = 800,
> > > > > + .hsync_start = 800 + 112,
> > > > > + .hsync_end = 800 + 112 + 1,
> > > > > + .htotal = 800 + 112 + 1 + 87,
> > > > > + .vdisplay = 480,
> > > > > + .vsync_start = 480 + 141,
> > > > > + .vsync_end = 480 + 141 + 1,
> > > > > + .vtotal = 480 + 141 + 1 + 38,
> > > > > + .vrefresh = 60,
> > > > > +};
> > > > > +
> > > > > +static const struct panel_desc innolux_at070tn90 = {
> > > > > + .modes = &innolux_at070tn90_mode,
> > > > > + .num_modes = 1,
> > > > > + .size = {
> > > > > + .width = 154,
> > > > > + .height = 86,
> > > > > + },
> > > > > + .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
> > > > > +};
> > > > > +
> > > >
> > > > I'm not really convinced this is the right approach. You said it
> > > > yourself, the panel is using a 24-bits interface, and you just happen
> > > > to have a tablet that routed it using a 18-bits interface instead.
> > > >
> > > > That doesn't belong in the driver, especially associated to the
> > > > compatible, but where the routing is described: in the device
> > > > tree. And given that the panel interface is a 24 bits panel, if we
> > > > were to have a default, we should have this one, and not the one
> > > > fitting your use case.
> > >
> > > I fully agree, this is why I suggested introducing a dedicated dt
> > > property for selecting the bus format (in the commit message). I still
> > > proposed this patch as a temporary solution, but I'm definitely willing
> > > to craft a proper solution as well.
> > >
> > > Here is an initial proposition:
> > > 1. Making bus_format an array in struct panel_desc and listing all the
> > > relevant bus formats that the panel can support there;
> >
> > I'm not sure this is needed, the input format is always the same in
> > your case, the panel will always take a 24 bits RGB value. What you
> > want to change is the encoder output format (and I guess you want that
> > to be meaningful to enable or not the dithering).
>
> Isn't the panel format supposed to match what the encoder's output
> should be aiming for? In my case, that would be RGB666, so the idea
> would be specifying both MEDIA_BUS_FMT_RGB666_1X18 and
> MEDIA_BUS_FMT_RGB888_1X24 in a list of supported bus formats for the
> panel.
The width your panel has in input is in 24 bits. The width the encoder
outputs in is 16 bits. This is the panel driver, you should expose the
panel capabilities.
> This way, both my setup and RGB888 setups can be supported.
I don't see what prevents you to do that with my suggestion either.
> > > 2. Introducing an optional "bus-format" dt property that indicates which
> > > bus format to use, and using the first index of the bus formats array if
> > > the property is not present;
> >
> > I guess the width would be enough, and that way we can take the
> > bus-width format that is already defined (but used in the v4l2
> > framework, not in DRM yet).
>
> Well, we already have bus-format defines on the DRM side and it feels
> like mapping these directly in device-tree would be more useful as a
> description of the hardware than just having the bus width.
Having the format in the DT doesn't make much sense. A given panel can
support multiple formats, just like a given encoder can.
If you're in that situation, the DT would describe a policy over what
happens in the OS, which isn't what should be stored in the DT. The
bus width, on the other end, is a property of the hardware.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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