* [PATCH V6 06/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +++++++++
2 files changed, 10 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4e15d0d..c6cabec 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -761,6 +761,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 0000000..2d1c4c6
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+ compatible = "qcom,ipq4019-ap-dk04.1-c3";
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 07/12] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Add the common data for all dk07 based boards.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 +++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 0000000..9f1a5a66
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512MB */
+ };
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ serial1 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ soc {
+ pinctrl@1000000 {
+ serial_0_pins: serial0-pinmux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+
+ nand_pins: nand-pins {
+ pins = "gpio53", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59",
+ "gpio60", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68", "gpio69";
+ function = "qpic";
+ };
+ };
+
+ serial@78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma@7884000 {
+ status = "ok";
+ };
+
+ i2c@78b7000 { /* BLSP1 QUP2 */
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma@7984000 {
+ status = "ok";
+ };
+
+ qpic-nand@79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 08/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
From: Sricharan R @ 2018-05-16 12:50 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +++++++++++++++++++++++++
2 files changed, 65 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c6cabec..596cce3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -762,6 +762,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
+ qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 0000000..8c7ef65
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
+ compatible = "qcom,ipq4019-ap-dk07.1-c1";
+
+ soc {
+ pci@40000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 38 0x1>;
+ };
+
+ spi@78b6000 {
+ status = "ok";
+ };
+
+ pinctrl@1000000 {
+ serial_1_pins: serial1-pinmux {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+
+ spi_0_pins: spi-0-pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ serial@78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ spi@78b5000 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 12 0>;
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "n25q128a11";
+ spi-max-frequency = <24000000>;
+ };
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 09/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
From: Sricharan R @ 2018-05-16 12:50 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 +++++++++++++++++++++++++
2 files changed, 26 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 596cce3..02b7f1d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -763,6 +763,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
+ qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
new file mode 100644
index 0000000..af7a902
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
+ compatible = "qcom,ipq4019-ap-dk07.1-c2";
+
+ soc {
+ pinctrl@1000000 {
+ serial_1_pins: serial1-pinmux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ serial@78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 10/12] ARM: dts: ipq8074: Add peripheral nodes
From: Sricharan R @ 2018-05-16 12:50 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Add serial, i2c, bam, spi, qpic peripheral nodes.
While here, fix the PMU node's irq trigger to avoid
the boot warnings from GIC.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 156 +++++++++++++++++++++++++++++++++-
1 file changed, 155 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2bc5dec..bd58ab4 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -32,6 +32,45 @@
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
+
+ serial_4_pins: serial4-pinmux {
+ pins = "gpio23", "gpio24";
+ function = "blsp4_uart1";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+ pins = "gpio42", "gpio43";
+ function = "blsp1_i2c";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ spi_0_pins: spi-0-pins {
+ pins = "gpio38", "gpio39", "gpio40", "gpio41";
+ function = "blsp0_spi";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ hsuart_pins: hsuart-pins {
+ pins = "gpio46", "gpio47", "gpio48", "gpio49";
+ function = "blsp2_uart";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ qpic_pins: qpic-pins {
+ pins = "gpio1", "gpio3", "gpio4",
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17";
+ function = "qpic";
+ drive-strength = <8>;
+ bias-disable;
+ };
};
intc: interrupt-controller@b000000 {
@@ -122,6 +161,121 @@
clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ pinctrl-0 = <&serial_4_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ blsp_dma: dma@7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7884000 0x2b000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ blsp1_uart1: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78af000 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart3: serial@78b1000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78b1000 0x200>;
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 4>,
+ <&blsp_dma 5>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&hsuart_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ blsp1_spi1: spi@78b5000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b5000 0x600>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ blsp1_i2c2: i2c@78b6000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b6000 0x600>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ dmas = <&blsp_dma 15>, <&blsp_dma 14>;
+ dma-names = "rx", "tx";
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ blsp1_i2c3: i2c@78b7000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b7000 0x600>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <100000>;
+ dmas = <&blsp_dma 17>, <&blsp_dma 16>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ qpic_bam: dma@7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7984000 0x1a000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ qpic_nand: nand@79b0000 {
+ compatible = "qcom,ipq8074-nand";
+ reg = <0x79b0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ pinctrl-0 = <&qpic_pins>;
+ pinctrl-names = "default";
status = "disabled";
};
};
@@ -175,7 +329,7 @@
pmu {
compatible = "arm,armv8-pmuv3";
- interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
clocks {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 11/12] ARM: dts: ipq8074: Add pcie nodes
From: Sricharan R @ 2018-05-16 12:50 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +++++++++++++++++++++++++++++++++-
1 file changed, 156 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index bd58ab4..1822698 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
- pinctrl@1000000 {
+ tlmm: pinctrl@1000000 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
@@ -278,6 +278,161 @@
pinctrl-names = "default";
status = "disabled";
};
+
+ pcie_phy0: phy@86000 {
+ compatible = "qcom,ipq8074-qmp-pcie-phy";
+ reg = <0x86000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe_clk";
+ clock-output-names = "pcie20_phy0_pipe_clk";
+
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie0: pci@20000000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x20000000 0xf1d
+ 0x20000f20 0xa8
+ 0x80000 0x2000
+ 0x20100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie_phy0>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0 0x20200000 0x20200000
+ 0 0x100000 /* downstream I/O */
+ 0x82000000 0 0x20300000 0x20300000
+ 0 0xd00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 75
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_AUX_CLK>;
+
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_SLEEP_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+ status = "disabled";
+ };
+
+ pcie_phy1: phy@8e000 {
+ compatible = "qcom,ipq8074-qmp-pcie-phy";
+ reg = <0x8e000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+ clock-names = "pipe_clk";
+ clock-output-names = "pcie20_phy1_pipe_clk";
+
+ resets = <&gcc GCC_PCIE1_PHY_BCR>,
+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie1: pci@10000000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x10000000 0xf1d
+ 0x10000f20 0xa8
+ 0x88000 0x2000
+ 0x10100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie_phy1>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0 0x10200000 0x10200000
+ 0 0x100000 /* downstream I/O */
+ 0x82000000 0 0x10300000 0x10300000
+ 0 0xd00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
+ <&gcc GCC_PCIE1_AXI_M_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_AUX_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+ <&gcc GCC_PCIE1_SLEEP_ARES>,
+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE1_AHB_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+ status = "disabled";
+ };
};
cpus {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 12/12] ARM: dts: ipq8074: Enable few peripherals for hk01 board
From: Sricharan R @ 2018-05-16 12:50 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 62 ++++++++++++++++++++++++++-----
1 file changed, 52 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..c13ddee 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -21,6 +21,7 @@
aliases {
serial0 = &blsp1_uart5;
+ serial1 = &blsp1_uart3;
};
chosen {
@@ -33,20 +34,61 @@
};
soc {
- pinctrl@1000000 {
- serial_4_pins: serial4_pinmux {
- mux {
- pins = "gpio23", "gpio24";
- function = "blsp4_uart1";
- bias-disable;
- };
+ serial@78b3000 {
+ status = "ok";
+ };
+
+ spi@78b5000 {
+ status = "ok";
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
};
};
- serial@78b3000 {
- pinctrl-0 = <&serial_4_pins>;
- pinctrl-names = "default";
+ serial@78b1000 {
+ status = "ok";
+ };
+
+ i2c@78b6000 {
+ status = "ok";
+ };
+
+ dma@7984000 {
+ status = "ok";
+ };
+
+ nand@79b0000 {
+ status = "ok";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+ };
+
+ phy@86000 {
+ status = "ok";
+ };
+
+ phy@8e000 {
+ status = "ok";
+ };
+
+ pci@20000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 58 0x1>;
+ };
+
+ pci@10000000 {
status = "ok";
+ perst-gpio = <&tlmm 61 0x1>;
};
};
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH] pci: cadence: Host and EP driver updates for PHY and power management
From: Alan Douglas @ 2018-05-16 13:06 UTC (permalink / raw)
To: bhelgaas@google.com, kishon@ti.com, lorenzo.pieralisi@arm.com
Cc: cyrille.pitchen@free-electrons.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
nsekhar@ti.com
From: Alan Douglas <adouglas@cadence.com>
This patch is based on next branch in Bjorn Helgaas' linux-pci git repository.
Allow optional list of generic PHYs to be provided via DTS for cadence RP and EP drivers.
Added power management ops which will enable/disable these PHYs.
Corrected parameters for cdns_pcie_writel function, value to be written had too
small width.
Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
.../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 4 +
.../bindings/pci/cdns,cdns-pcie-host.txt | 5 +
drivers/pci/cadence/pcie-cadence-ep.c | 15 +++-
drivers/pci/cadence/pcie-cadence-host.c | 36 ++++++-
drivers/pci/cadence/pcie-cadence.c | 123 ++++++++++++++++++++
drivers/pci/cadence/pcie-cadence.h | 13 ++-
6 files changed, 193 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
index 9a30523..e40c635 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
@@ -9,6 +9,8 @@ Required properties:
Optional properties:
- max-functions: Maximum number of functions that can be configured (default 1).
+- phys: From PHY bindings: List of Generic PHY phandles.
+- phy-names: List of names to identify the PHY.
Example:
@@ -19,4 +21,6 @@ pcie@fc000000 {
reg-names = "reg", "mem";
cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <8>;
+ phys = <&ep_phy0 &ep_phy1>;
+ phy-names = "pcie-lane0","pcie-lane1";
};
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
index 20a33f3..13be218 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
@@ -24,6 +24,8 @@ Optional properties:
translations (default 32)
- vendor-id: The PCI vendor ID (16 bits, default is design dependent)
- device-id: The PCI device ID (16 bits, default is design dependent)
+- phys: From PHY bindings: List of Generic PHY phandles.
+- phy-names: List of names to identify the PHY.
Example:
@@ -57,4 +59,7 @@ pcie@fb000000 {
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
msi-parent = <&its_pci>;
+
+ phys = <&pcie_phy0>;
+ phy-names = "pcie-phy";
};
diff --git a/drivers/pci/cadence/pcie-cadence-ep.c b/drivers/pci/cadence/pcie-cadence-ep.c
index 3d8283e..e74b8a4 100644
--- a/drivers/pci/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/cadence/pcie-cadence-ep.c
@@ -439,6 +439,7 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
struct pci_epc *epc;
struct resource *res;
int ret;
+ int phy_count;
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
if (!ep)
@@ -472,6 +473,12 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
if (!ep->ob_addr)
return -ENOMEM;
+ ret = cdns_pcie_init_phy(dev, pcie);
+ if (ret) {
+ dev_err(dev, "failed to init phy\n");
+ return ret;
+ }
+ platform_set_drvdata(pdev, pcie);
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (ret < 0) {
@@ -520,6 +527,10 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
err_get_sync:
pm_runtime_disable(dev);
+ cdns_pcie_disable_phy(pcie);
+ phy_count = pcie->phy_count;
+ while (phy_count--)
+ device_link_del(pcie->link[phy_count]);
return ret;
}
@@ -527,6 +538,7 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ struct cdns_pcie *pcie = dev_get_drvdata(dev);
int ret;
ret = pm_runtime_put_sync(dev);
@@ -535,13 +547,14 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
pm_runtime_disable(dev);
- /* The PCIe controller can't be disabled. */
+ cdns_pcie_disable_phy(pcie);
}
static struct platform_driver cdns_pcie_ep_driver = {
.driver = {
.name = "cdns-pcie-ep",
.of_match_table = cdns_pcie_ep_of_match,
+ .pm = &cdns_pcie_pm_ops,
},
.probe = cdns_pcie_ep_probe,
.shutdown = cdns_pcie_ep_shutdown,
diff --git a/drivers/pci/cadence/pcie-cadence-host.c b/drivers/pci/cadence/pcie-cadence-host.c
index a4ebbd3..992ebe2 100644
--- a/drivers/pci/cadence/pcie-cadence-host.c
+++ b/drivers/pci/cadence/pcie-cadence-host.c
@@ -37,7 +37,6 @@ struct cdns_pcie_rc {
u16 vendor_id;
u16 device_id;
};
-
static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
int where)
{
@@ -46,6 +45,7 @@ struct cdns_pcie_rc {
struct cdns_pcie *pcie = &rc->pcie;
unsigned int busn = bus->number;
u32 addr0, desc0;
+ u32 link_status;
if (busn == rc->bus_range->start) {
/*
@@ -58,6 +58,11 @@ struct cdns_pcie_rc {
return pcie->reg_base + (where & 0xfff);
}
+ /* Check that the link is up. Clear AXI link-down status */
+ link_status = cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE);
+ if (!(link_status & 0x1))
+ return NULL;
+ cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0);
/* Update Output registers for AXI region 0. */
addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
@@ -239,6 +244,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
struct cdns_pcie *pcie;
struct resource *res;
int ret;
+ int phy_count;
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
if (!bridge)
@@ -290,6 +296,13 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
}
pcie->mem_res = res;
+ ret = cdns_pcie_init_phy(dev, pcie);
+ if (ret) {
+ dev_err(dev, "failed to init phy\n");
+ return ret;
+ }
+ platform_set_drvdata(pdev, pcie);
+
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (ret < 0) {
@@ -322,15 +335,36 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
err_get_sync:
pm_runtime_disable(dev);
+ cdns_pcie_disable_phy(pcie);
+ phy_count = pcie->phy_count;
+ while (phy_count--)
+ device_link_del(pcie->link[phy_count]);
return ret;
}
+static void cdns_pcie_shutdown(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct cdns_pcie *pcie = dev_get_drvdata(dev);
+ int ret;
+
+ ret = pm_runtime_put_sync(dev);
+ if (ret < 0)
+ dev_dbg(dev, "pm_runtime_put_sync failed\n");
+
+ pm_runtime_disable(dev);
+ cdns_pcie_disable_phy(pcie);
+}
+
+
static struct platform_driver cdns_pcie_host_driver = {
.driver = {
.name = "cdns-pcie-host",
.of_match_table = cdns_pcie_host_of_match,
+ .pm = &cdns_pcie_pm_ops,
},
.probe = cdns_pcie_host_probe,
+ .shutdown = cdns_pcie_shutdown,
};
builtin_platform_driver(cdns_pcie_host_driver);
diff --git a/drivers/pci/cadence/pcie-cadence.c b/drivers/pci/cadence/pcie-cadence.c
index 138d113..7a34780 100644
--- a/drivers/pci/cadence/pcie-cadence.c
+++ b/drivers/pci/cadence/pcie-cadence.c
@@ -124,3 +124,126 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r)
cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), 0);
cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), 0);
}
+
+void cdns_pcie_disable_phy(struct cdns_pcie *pcie)
+{
+ int i = pcie->phy_count;
+
+ while (i--) {
+ phy_power_off(pcie->phy[i]);
+ phy_exit(pcie->phy[i]);
+ }
+}
+
+int cdns_pcie_enable_phy(struct cdns_pcie *pcie)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < pcie->phy_count; i++) {
+ ret = phy_init(pcie->phy[i]);
+ if (ret < 0)
+ goto err_phy;
+
+ ret = phy_power_on(pcie->phy[i]);
+ if (ret < 0) {
+ phy_exit(pcie->phy[i]);
+ goto err_phy;
+ }
+ }
+
+ return 0;
+
+err_phy:
+ while (--i >= 0) {
+ phy_power_off(pcie->phy[i]);
+ phy_exit(pcie->phy[i]);
+ }
+
+ return ret;
+}
+
+int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
+{
+ struct device_node *np = dev->of_node;
+ int phy_count;
+ struct phy **phy;
+ struct device_link **link;
+ int i;
+ int ret;
+ const char *name;
+
+ phy_count = of_property_count_strings(np, "phy-names");
+ if (phy_count < 1) {
+ dev_err(dev, "no phy-names. PHY will not be initialized\n");
+ pcie->phy_count = 0;
+ return 0;
+ }
+
+ phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL);
+ if (!link)
+ return -ENOMEM;
+
+ for (i = 0; i < phy_count; i++) {
+ of_property_read_string_index(np, "phy-names", i, &name);
+ phy[i] = devm_phy_get(dev, name);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
+ if (!link[i]) {
+ ret = -EINVAL;
+ goto err_link;
+ }
+ }
+
+ pcie->phy_count = phy_count;
+ pcie->phy = phy;
+ pcie->link = link;
+
+ ret = cdns_pcie_enable_phy(pcie);
+ if (ret)
+ goto err_link;
+
+ return 0;
+
+err_link:
+ while (--i >= 0)
+ device_link_del(link[i]);
+
+ return ret;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int cdns_pcie_suspend_noirq(struct device *dev)
+{
+ struct cdns_pcie *pcie = dev_get_drvdata(dev);
+
+ cdns_pcie_disable_phy(pcie);
+
+ return 0;
+}
+
+static int cdns_pcie_resume_noirq(struct device *dev)
+{
+ struct cdns_pcie *pcie = dev_get_drvdata(dev);
+ int ret;
+
+ ret = cdns_pcie_enable_phy(pcie);
+ if (ret) {
+ dev_err(dev, "failed to enable phy\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+const struct dev_pm_ops cdns_pcie_pm_ops = {
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,
+ cdns_pcie_resume_noirq)
+};
diff --git a/drivers/pci/cadence/pcie-cadence.h b/drivers/pci/cadence/pcie-cadence.h
index 4bb2733..ae6bf2a 100644
--- a/drivers/pci/cadence/pcie-cadence.h
+++ b/drivers/pci/cadence/pcie-cadence.h
@@ -8,6 +8,7 @@
#include <linux/kernel.h>
#include <linux/pci.h>
+#include <linux/phy/phy.h>
/*
* Local Management Registers
@@ -165,6 +166,9 @@
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
+/* AXI link down register */
+#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
+
enum cdns_pcie_rp_bar {
RP_BAR0,
RP_BAR1,
@@ -229,6 +233,9 @@ struct cdns_pcie {
struct resource *mem_res;
bool is_rc;
u8 bus;
+ int phy_count;
+ struct phy **phy;
+ struct device_link **link;
};
/* Register access */
@@ -279,7 +286,7 @@ static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn,
}
static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
- u32 reg, u16 value)
+ u32 reg, u32 value)
{
writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
}
@@ -307,5 +314,9 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
u32 r, u64 cpu_addr);
void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
+void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
+int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
+int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
+extern const struct dev_pm_ops cdns_pcie_pm_ops;
#endif /* _PCIE_CADENCE_H */
--
1.7.1
^ permalink raw reply related
* [PATCH 1/2] dmaengine: usb-dmac: Document R8A7799{0,5} bindings
From: Ulrich Hecht @ 2018-05-16 13:06 UTC (permalink / raw)
To: linux-renesas-soc
Cc: horms, dmaengine, devicetree, Hiroyuki Yokoyama, Ulrich Hecht
From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Renesas R-Car D3 (R8A77995) and E3 (R8A77990) SoCs also have the R-Car
gen2/3 compatible DMA controllers, so document the SoC specific binding.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
[uli: squashed]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
---
Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
index 9dc935e..482e543 100644
--- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
+++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
@@ -12,6 +12,8 @@ Required Properties:
- "renesas,r8a7795-usb-dmac" (R-Car H3)
- "renesas,r8a7796-usb-dmac" (R-Car M3-W)
- "renesas,r8a77965-usb-dmac" (R-Car M3-N)
+ - "renesas,r8a77990-usb-dmac" (R-Car E3)
+ - "renesas,r8a77995-usb-dmac" (R-Car D3)
- reg: base address and length of the registers block for the DMAC
- interrupts: interrupt specifiers for the DMAC, one for each entry in
interrupt-names.
--
2.7.4
^ permalink raw reply related
* [PATCH 2/2] dmaengine: rcar-dmac: Document R8A77990 bindings
From: Ulrich Hecht @ 2018-05-16 13:06 UTC (permalink / raw)
To: linux-renesas-soc
Cc: horms, dmaengine, devicetree, Hiroyuki Yokoyama, Ulrich Hecht
In-Reply-To: <1526475979-13891-1-git-send-email-ulrich.hecht+renesas@gmail.com>
From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Renesas R-Car E3 (R8A77990) SoC also has the R-Car gen2/3 compatible DMA
controllers, so document the SoC specific binding.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
---
Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
index b1ba6395..946229c 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
@@ -29,6 +29,7 @@ Required Properties:
- "renesas,dmac-r8a77965" (R-Car M3-N)
- "renesas,dmac-r8a77970" (R-Car V3M)
- "renesas,dmac-r8a77980" (R-Car V3H)
+ - "renesas,dmac-r8a77990" (R-Car E3)
- "renesas,dmac-r8a77995" (R-Car D3)
- reg: base address and length of the registers block for the DMAC
--
2.7.4
^ permalink raw reply related
* Re: [PATCH/RFT v3 0/3] thermal: add support for r8a77995
From: Ulrich Hecht @ 2018-05-16 13:07 UTC (permalink / raw)
To: jacopo mondi
Cc: Yoshihiro Kaneko, Linux-Renesas, Zhang Rui, Eduardo Valentin,
Rob Herring, Linux PM list, devicetree
In-Reply-To: <20180411090122.GK6436@w540>
On Wed, Apr 11, 2018 at 11:01 AM, jacopo mondi <jacopo@jmondi.org> wrote:
> Hello Kaneko-san,
>
> On Tue, Apr 03, 2018 at 09:43:02PM +0900, Yoshihiro Kaneko wrote:
>> This series adds thermal support for r8a77995.
>> R-Car D3 (r8a77995) have a thermal sensor module which is similar to Gen2.
>> Therefore this series adds r8a77995 support to rcar_thermal driver not
>> rcar_gen3_thermal driver.
>
> I tested this on D3 Draak.
>
> I generated load expecting the detected temperature to rise.
>
> It took a while, and I only see a slight increase of the temperature
> reported by the 'temp' attribute.
Pointing a heat gun at the SoC, I managed to get the temperature up to
80000, and it went back to 40000 when I removed it. I'd say this
works.
Tested-By: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
CU
Uli
^ permalink raw reply
* Re: [PATCH v7 00/14] CPU scaling support for msm8996
From: Amit Kucheria @ 2018-05-16 13:11 UTC (permalink / raw)
To: Ilia Lin
Cc: Michael Turquette, sboyd, Rob Herring, Mark Rutland, Viresh Kumar,
nm, lgirdwood, broonie, Andy Gross, David Brown, catalin.marinas,
will.deacon, Rafael J. Wysocki, linux-clk, devicetree, LKML,
Linux PM list, linux-arm-msm, linux-soc, lakml, Rajendra Nayak,
nicolas.dechesne, celster, tfinkel
In-Reply-To: <1526375616-16904-1-git-send-email-ilialin@codeaurora.org>
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote:
> [v7]
> * Addressed comments from Viresh about resourses deallocation
> and DT compatible
Hi Ilia,
Thanks for working on this series. Here a few comments regarding the
series as a whole.
- The series could use a better cover letter describing how the
various patches are grouped. e.g. 1-7 are clock related and probably
will get merged through the clk maintainers tree. The regulator bits
might get merged through the regulator maintainer tree and so forth.
If there are any dependencies, please outline those as well so
maintainers can decide how best to merge this.
- Please describe what features this series adds - just frequency
scaling or more. Please describe in more detail what the dependency on
the SAW regulator changes is.
- Please get rid of the GPL boiler plate since you already have the
SPDX tags. See comments on patch 1 for what I'm referring to.
- You also mention that ACD is not implemented in the earlier patches
and then there is a patch that seems to add ACD related features
(7/14).
A few other comments follow across the individual patches.
Regards,
Amit
> [v6]
> * Addressed comments from Viresh about:
> ** Comments style
> ** Kconfig bool instead of tristate
> ** DT and documentation style
> ** Resourses deallocation on an error
> ** Typos
>
> [v5]
> * Rebased
> * Addressed comments from Bjorn about SPDX style,
> functions and parameters naming
> * Addressed comments from Viresh DT properties and style, comments style,
> resourses deallocation, documentation placement
> * Addressed comments from Sricharan about unnessesary include
> * Addressed comments from Nicolas
> * Addressed comments from Rob about the commit messages and acks
> * Addressed comments from Mark
>
> [v4]
> * Adressed all comments from Stephen
> * Added CPU regulator support
> * Added qcom-cpufreq-kryo driver
>
> [v3]
> * Rebased on top of the latest PLL driver changes
> * Addressed comment from Rob Herring for bindings
>
> [v2]
> * Addressed comments from Rob Herring for bindings
> * Addressed comments from Mark Rutland for memory barrier
> * Addressed comments from Julien Thierry for clock reenabling condition
> * Tuned the HW configuration for clock frequencies below 600MHz
>
> Clocks:
> This series adds support for the CPU clocks on msm8996 devices.
> The driver uses the existing PLL drivers and is required to control
> the CPU frequency scaling on the MSM8996.
>
> Regulators:
> Added SAW regulator support to the SPMI regulator driver. The SAW regulators
> will be controlled through special CPU registers instead of direct
> SPMI accesses.
>
> Cpufreq:
> The qcom-cpufreq-kryo driver is aimed to support different SOC versions.
> The driver reads eFuse information and chooses the required OPP subset
> by passing the OPP supported-hw parameter.
>
> A previous post of RFC can be found here:
> https://patchwork.kernel.org/patch/10398455/
>
> Ilia Lin (11):
> soc: qcom: Separate kryo l2 accessors from PMU driver
> clk: qcom: Add CPU clock driver for msm8996
> clk: qcom: Add DT bindings for CPU clock driver for msm8996
> clk: qcom: Add ACD path to CPU clock driver for msm8996
> dt: qcom: Add opp and thermal to the msm8996
> regulator: qcom_spmi: Add support for SAW
> dt-bindings: qcom_spmi: Add support for SAW documentation
> dt: qcom: Add SAW regulator for 8x96 CPUs
> cpufreq: Add Kryo CPU scaling driver
> dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu
> dt: qcom: Add qcom-cpufreq-kryo driver configuration
>
> Rajendra Nayak (3):
> clk: qcom: Make clk_alpha_pll_configure available to modules
> clk: qcom: cpu-8996: Add support to switch to alternate PLL
> clk: qcom: cpu-8996: Add support to switch below 600Mhz
>
> .../devicetree/bindings/clock/qcom,kryocc.txt | 17 +
> .../devicetree/bindings/opp/kryo-cpufreq.txt | 680 +++++++++++++++++++++
> .../bindings/regulator/qcom,spmi-regulator.txt | 45 ++
> arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +-
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 651 +++++++++++++++++++-
> drivers/clk/clk-fixed-factor.c | 2 +-
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/clk-alpha-pll.c | 1 +
> drivers/clk/qcom/clk-alpha-pll.h | 6 +
> drivers/clk/qcom/clk-cpu-8996.c | 519 ++++++++++++++++
> drivers/cpufreq/Kconfig.arm | 11 +
> drivers/cpufreq/Makefile | 1 +
> drivers/cpufreq/cpufreq-dt-platdev.c | 3 +
> drivers/cpufreq/qcom-cpufreq-kryo.c | 150 +++++
> drivers/perf/Kconfig | 1 +
> drivers/perf/qcom_l2_pmu.c | 90 +--
> drivers/regulator/qcom_spmi-regulator.c | 133 +++-
> drivers/soc/qcom/Kconfig | 3 +
> drivers/soc/qcom/Makefile | 1 +
> drivers/soc/qcom/kryo-l2-accessors.c | 65 ++
> include/soc/qcom/kryo-l2-accessors.h | 21 +
> 22 files changed, 2332 insertions(+), 80 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,kryocc.txt
> create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
> create mode 100644 drivers/clk/qcom/clk-cpu-8996.c
> create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
> create mode 100644 drivers/soc/qcom/kryo-l2-accessors.c
> create mode 100644 include/soc/qcom/kryo-l2-accessors.h
>
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v7 01/14] soc: qcom: Separate kryo l2 accessors from PMU driver
From: Amit Kucheria @ 2018-05-16 13:12 UTC (permalink / raw)
To: Ilia Lin
Cc: Michael Turquette, sboyd, Rob Herring, Mark Rutland, Viresh Kumar,
nm, lgirdwood, broonie, Andy Gross, David Brown, catalin.marinas,
will.deacon, Rafael J. Wysocki, linux-clk, devicetree, LKML,
Linux PM list, linux-arm-msm, linux-soc, lakml, Rajendra Nayak,
nicolas.dechesne, celster, tfinkel
In-Reply-To: <1526375616-16904-2-git-send-email-ilialin@codeaurora.org>
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote:
> The driver provides kernel level API for other drivers
> to access the MSM8996 L2 cache registers.
> Separating the L2 access code from the PMU driver and
> making it public to allow other drivers use it.
> The accesses must be separated with a single spinlock,
> maintained in this driver.
>
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> drivers/perf/Kconfig | 1 +
> drivers/perf/qcom_l2_pmu.c | 90 ++++++++++--------------------------
> drivers/soc/qcom/Kconfig | 3 ++
> drivers/soc/qcom/Makefile | 1 +
> drivers/soc/qcom/kryo-l2-accessors.c | 65 ++++++++++++++++++++++++++
> include/soc/qcom/kryo-l2-accessors.h | 21 +++++++++
> 6 files changed, 115 insertions(+), 66 deletions(-)
> create mode 100644 drivers/soc/qcom/kryo-l2-accessors.c
> create mode 100644 include/soc/qcom/kryo-l2-accessors.h
>
> diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
> index 28bb5a0..561252a 100644
> --- a/drivers/perf/Kconfig
> +++ b/drivers/perf/Kconfig
> @@ -69,6 +69,7 @@ config HISI_PMU
> config QCOM_L2_PMU
> bool "Qualcomm Technologies L2-cache PMU"
> depends on ARCH_QCOM && ARM64 && ACPI
> + select QCOM_KRYO_L2_ACCESSORS
> help
> Provides support for the L2 cache performance monitor unit (PMU)
> in Qualcomm Technologies processors.
> diff --git a/drivers/perf/qcom_l2_pmu.c b/drivers/perf/qcom_l2_pmu.c
> index 842135c..cc31f51 100644
> --- a/drivers/perf/qcom_l2_pmu.c
> +++ b/drivers/perf/qcom_l2_pmu.c
> @@ -31,6 +31,7 @@
> #include <asm/barrier.h>
> #include <asm/local64.h>
> #include <asm/sysreg.h>
> +#include <soc/qcom/kryo-l2-accessors.h>
>
> #define MAX_L2_CTRS 9
>
> @@ -87,8 +88,6 @@
> #define L2_COUNTER_RELOAD BIT_ULL(31)
> #define L2_CYCLE_COUNTER_RELOAD BIT_ULL(63)
>
> -#define L2CPUSRSELR_EL1 sys_reg(3, 3, 15, 0, 6)
> -#define L2CPUSRDR_EL1 sys_reg(3, 3, 15, 0, 7)
>
> #define reg_idx(reg, i) (((i) * IA_L2_REG_OFFSET) + reg##_BASE)
>
> @@ -107,48 +106,7 @@
> #define L2_EVENT_STREX 0x421
> #define L2_EVENT_CLREX 0x422
>
> -static DEFINE_RAW_SPINLOCK(l2_access_lock);
>
> -/**
> - * set_l2_indirect_reg: write value to an L2 register
> - * @reg: Address of L2 register.
> - * @value: Value to be written to register.
> - *
> - * Use architecturally required barriers for ordering between system register
> - * accesses
> - */
> -static void set_l2_indirect_reg(u64 reg, u64 val)
> -{
> - unsigned long flags;
> -
> - raw_spin_lock_irqsave(&l2_access_lock, flags);
> - write_sysreg_s(reg, L2CPUSRSELR_EL1);
> - isb();
> - write_sysreg_s(val, L2CPUSRDR_EL1);
> - isb();
> - raw_spin_unlock_irqrestore(&l2_access_lock, flags);
> -}
> -
> -/**
> - * get_l2_indirect_reg: read an L2 register value
> - * @reg: Address of L2 register.
> - *
> - * Use architecturally required barriers for ordering between system register
> - * accesses
> - */
> -static u64 get_l2_indirect_reg(u64 reg)
> -{
> - u64 val;
> - unsigned long flags;
> -
> - raw_spin_lock_irqsave(&l2_access_lock, flags);
> - write_sysreg_s(reg, L2CPUSRSELR_EL1);
> - isb();
> - val = read_sysreg_s(L2CPUSRDR_EL1);
> - raw_spin_unlock_irqrestore(&l2_access_lock, flags);
> -
> - return val;
> -}
>
> struct cluster_pmu;
>
> @@ -219,28 +177,28 @@ static inline struct cluster_pmu *get_cluster_pmu(
> static void cluster_pmu_reset(void)
> {
> /* Reset all counters */
> - set_l2_indirect_reg(L2PMCR, L2PMCR_RESET_ALL);
> - set_l2_indirect_reg(L2PMCNTENCLR, l2_counter_present_mask);
> - set_l2_indirect_reg(L2PMINTENCLR, l2_counter_present_mask);
> - set_l2_indirect_reg(L2PMOVSCLR, l2_counter_present_mask);
> + kryo_l2_set_indirect_reg(L2PMCR, L2PMCR_RESET_ALL);
> + kryo_l2_set_indirect_reg(L2PMCNTENCLR, l2_counter_present_mask);
> + kryo_l2_set_indirect_reg(L2PMINTENCLR, l2_counter_present_mask);
> + kryo_l2_set_indirect_reg(L2PMOVSCLR, l2_counter_present_mask);
> }
>
> static inline void cluster_pmu_enable(void)
> {
> - set_l2_indirect_reg(L2PMCR, L2PMCR_COUNTERS_ENABLE);
> + kryo_l2_set_indirect_reg(L2PMCR, L2PMCR_COUNTERS_ENABLE);
> }
>
> static inline void cluster_pmu_disable(void)
> {
> - set_l2_indirect_reg(L2PMCR, L2PMCR_COUNTERS_DISABLE);
> + kryo_l2_set_indirect_reg(L2PMCR, L2PMCR_COUNTERS_DISABLE);
> }
>
> static inline void cluster_pmu_counter_set_value(u32 idx, u64 value)
> {
> if (idx == l2_cycle_ctr_idx)
> - set_l2_indirect_reg(L2PMCCNTR, value);
> + kryo_l2_set_indirect_reg(L2PMCCNTR, value);
> else
> - set_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx), value);
> + kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx), value);
> }
>
> static inline u64 cluster_pmu_counter_get_value(u32 idx)
> @@ -248,46 +206,46 @@ static inline u64 cluster_pmu_counter_get_value(u32 idx)
> u64 value;
>
> if (idx == l2_cycle_ctr_idx)
> - value = get_l2_indirect_reg(L2PMCCNTR);
> + value = kryo_l2_get_indirect_reg(L2PMCCNTR);
> else
> - value = get_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx));
> + value = kryo_l2_get_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx));
>
> return value;
> }
>
> static inline void cluster_pmu_counter_enable(u32 idx)
> {
> - set_l2_indirect_reg(L2PMCNTENSET, idx_to_reg_bit(idx));
> + kryo_l2_set_indirect_reg(L2PMCNTENSET, idx_to_reg_bit(idx));
> }
>
> static inline void cluster_pmu_counter_disable(u32 idx)
> {
> - set_l2_indirect_reg(L2PMCNTENCLR, idx_to_reg_bit(idx));
> + kryo_l2_set_indirect_reg(L2PMCNTENCLR, idx_to_reg_bit(idx));
> }
>
> static inline void cluster_pmu_counter_enable_interrupt(u32 idx)
> {
> - set_l2_indirect_reg(L2PMINTENSET, idx_to_reg_bit(idx));
> + kryo_l2_set_indirect_reg(L2PMINTENSET, idx_to_reg_bit(idx));
> }
>
> static inline void cluster_pmu_counter_disable_interrupt(u32 idx)
> {
> - set_l2_indirect_reg(L2PMINTENCLR, idx_to_reg_bit(idx));
> + kryo_l2_set_indirect_reg(L2PMINTENCLR, idx_to_reg_bit(idx));
> }
>
> static inline void cluster_pmu_set_evccntcr(u32 val)
> {
> - set_l2_indirect_reg(L2PMCCNTCR, val);
> + kryo_l2_set_indirect_reg(L2PMCCNTCR, val);
> }
>
> static inline void cluster_pmu_set_evcntcr(u32 ctr, u32 val)
> {
> - set_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTCR, ctr), val);
> + kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVCNTCR, ctr), val);
> }
>
> static inline void cluster_pmu_set_evtyper(u32 ctr, u32 val)
> {
> - set_l2_indirect_reg(reg_idx(IA_L2PMXEVTYPER, ctr), val);
> + kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVTYPER, ctr), val);
> }
>
> static void cluster_pmu_set_resr(struct cluster_pmu *cluster,
> @@ -303,11 +261,11 @@ static void cluster_pmu_set_resr(struct cluster_pmu *cluster,
>
> spin_lock_irqsave(&cluster->pmu_lock, flags);
>
> - resr_val = get_l2_indirect_reg(L2PMRESR);
> + resr_val = kryo_l2_get_indirect_reg(L2PMRESR);
> resr_val &= ~(L2PMRESR_GROUP_MASK << shift);
> resr_val |= field;
> resr_val |= L2PMRESR_EN;
> - set_l2_indirect_reg(L2PMRESR, resr_val);
> + kryo_l2_set_indirect_reg(L2PMRESR, resr_val);
>
> spin_unlock_irqrestore(&cluster->pmu_lock, flags);
> }
> @@ -323,14 +281,14 @@ static inline void cluster_pmu_set_evfilter_sys_mode(u32 ctr)
> L2PMXEVFILTER_ORGFILTER_IDINDEP |
> L2PMXEVFILTER_ORGFILTER_ALL;
>
> - set_l2_indirect_reg(reg_idx(IA_L2PMXEVFILTER, ctr), val);
> + kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVFILTER, ctr), val);
> }
>
> static inline u32 cluster_pmu_getreset_ovsr(void)
> {
> - u32 result = get_l2_indirect_reg(L2PMOVSSET);
> + u32 result = kryo_l2_get_indirect_reg(L2PMOVSSET);
>
> - set_l2_indirect_reg(L2PMOVSCLR, result);
> + kryo_l2_set_indirect_reg(L2PMOVSCLR, result);
> return result;
> }
>
> @@ -783,7 +741,7 @@ static int get_num_counters(void)
> {
> int val;
>
> - val = get_l2_indirect_reg(L2PMCR);
> + val = kryo_l2_get_indirect_reg(L2PMCR);
>
> /*
> * Read number of counters from L2PMCR and add 1
> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
> index 7093fe7..0567dff 100644
> --- a/drivers/soc/qcom/Kconfig
> +++ b/drivers/soc/qcom/Kconfig
> @@ -39,6 +39,9 @@ config QCOM_GSBI
> functions for connecting the underlying serial UART, SPI, and I2C
> devices to the output pins.
>
> +config QCOM_KRYO_L2_ACCESSORS
> + bool
> +
> config QCOM_MDT_LOADER
> tristate
> select QCOM_SCM
> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> index cbf414c..e4d3f5a 100644
> --- a/drivers/soc/qcom/Makefile
> +++ b/drivers/soc/qcom/Makefile
> @@ -14,3 +14,4 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o
> obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
> obj-$(CONFIG_QCOM_SMSM) += smsm.o
> obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
> +obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o
> diff --git a/drivers/soc/qcom/kryo-l2-accessors.c b/drivers/soc/qcom/kryo-l2-accessors.c
> new file mode 100644
> index 0000000..d35a860
> --- /dev/null
> +++ b/drivers/soc/qcom/kryo-l2-accessors.c
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2014-2015, 2018, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
Get rid of the GPL boilerplate i.e. everything after the Copyright
line. You only need the SPDX line at the top.
> +#include <linux/spinlock.h>
> +#include <asm/sysreg.h>
> +#include <soc/qcom/kryo-l2-accessors.h>
> +
> +#define L2CPUSRSELR_EL1 sys_reg(3, 3, 15, 0, 6)
> +#define L2CPUSRDR_EL1 sys_reg(3, 3, 15, 0, 7)
> +
> +static DEFINE_RAW_SPINLOCK(l2_access_lock);
> +
> +/**
> + * kryo_l2_set_indirect_reg() - write value to an L2 register
> + * @reg: Address of L2 register.
> + * @value: Value to be written to register.
> + *
> + * Use architecturally required barriers for ordering between system register
> + * accesses, and system registers with respect to device memory
> + */
> +void kryo_l2_set_indirect_reg(u64 reg, u64 val)
> +{
> + unsigned long flags;
> +
> + raw_spin_lock_irqsave(&l2_access_lock, flags);
> + write_sysreg_s(reg, L2CPUSRSELR_EL1);
> + isb();
> + write_sysreg_s(val, L2CPUSRDR_EL1);
> + isb();
> + raw_spin_unlock_irqrestore(&l2_access_lock, flags);
> +}
> +EXPORT_SYMBOL(kryo_l2_set_indirect_reg);
> +
> +/**
> + * kryo_l2_get_indirect_reg() - read an L2 register value
> + * @reg: Address of L2 register.
> + *
> + * Use architecturally required barriers for ordering between system register
> + * accesses, and system registers with respect to device memory
> + */
> +u64 kryo_l2_get_indirect_reg(u64 reg)
> +{
> + u64 val;
> + unsigned long flags;
> +
> + raw_spin_lock_irqsave(&l2_access_lock, flags);
> + write_sysreg_s(reg, L2CPUSRSELR_EL1);
> + isb();
> + val = read_sysreg_s(L2CPUSRDR_EL1);
> + raw_spin_unlock_irqrestore(&l2_access_lock, flags);
> +
> + return val;
> +}
> +EXPORT_SYMBOL(kryo_l2_get_indirect_reg);
> diff --git a/include/soc/qcom/kryo-l2-accessors.h b/include/soc/qcom/kryo-l2-accessors.h
> new file mode 100644
> index 0000000..0840e87
> --- /dev/null
> +++ b/include/soc/qcom/kryo-l2-accessors.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
Get rid of the GPL boilerplate i.e. everything after the Copyright
line. You only need the SPDX line at the top.
> +#ifndef __SOC_ARCH_QCOM_KRYO_L2_ACCESSORS_H
> +#define __SOC_ARCH_QCOM_KRYO_L2_ACCESSORS_H
> +
> +void kryo_l2_set_indirect_reg(u64 reg, u64 val);
> +u64 kryo_l2_get_indirect_reg(u64 reg);
> +
> +#endif
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v7 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu
From: Amit Kucheria @ 2018-05-16 13:12 UTC (permalink / raw)
To: Ilia Lin
Cc: Michael Turquette, sboyd, Rob Herring, Mark Rutland, Viresh Kumar,
nm, lgirdwood, broonie, Andy Gross, David Brown, catalin.marinas,
will.deacon, Rafael J. Wysocki, linux-clk, devicetree, LKML,
Linux PM list, linux-arm-msm, linux-soc, lakml, Rajendra Nayak,
nicolas.dechesne, celster, tfinkel
In-Reply-To: <1526375616-16904-14-git-send-email-ilialin@codeaurora.org>
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote:
> In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
> that have KRYO processors, the CPU ferequencies subset and voltage value
s/ferequencies/frequency
> of each OPP varies based on the silicon variant in use.
> Qualcomm Technologies, Inc. Process Voltage Scaling Tables
> defines the voltage and frequency value based on the msm-id in SMEM
> and speedbin blown in the efuse combination.
> The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
> to provide the OPP framework with required information.
> This is used to determine the voltage and frequency value for each OPP of
> operating-points-v2 table when it is parsed by the OPP framework.
>
> This change adds documentation.
Change this to actually document the extension of the op-v2 binding
with a list of compatible HW.
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> ---
> .../devicetree/bindings/opp/kryo-cpufreq.txt | 680 +++++++++++++++++++++
> 1 file changed, 680 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
>
> diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt b/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
> new file mode 100644
> index 0000000..c2127b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
> @@ -0,0 +1,680 @@
> +Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings
> +===================================
> +
> +In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
> +that have KRYO processors, the CPU ferequencies subset and voltage value
> +of each OPP varies based on the silicon variant in use.
> +Qualcomm Technologies, Inc. Process Voltage Scaling Tables
> +defines the voltage and frequency value based on the msm-id in SMEM
> +and speedbin blown in the efuse combination.
> +The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
> +to provide the OPP framework with required information (existing HW bitmap).
> +This is used to determine the voltage and frequency value for each OPP of
> +operating-points-v2 table when it is parsed by the OPP framework.
> +
> +Required properties:
> +--------------------
> +In 'cpus' nodes:
> +- operating-points-v2: Phandle to the operating-points-v2 table to use.
> +
> +In 'operating-points-v2' table:
> +- compatible: Should be
> + - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
> +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
> + efuse registers that has information about the
> + speedbin that is used to select the right frequency/voltage
> + value pair.
> + Please refer the for nvmem-cells
> + bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
> + and also examples below.
> +
> +In every OPP node:
> +- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
> + Bitmap:
> + 0: MSM8996 V3, speedbin 0
> + 1: MSM8996 V3, speedbin 1
> + 2: MSM8996 V3, speedbin 2
> + 3: unused
> + 4: MSM8996 SG, speedbin 0
> + 5: MSM8996 SG, speedbin 1
> + 6: MSM8996 SG, speedbin 2
> + 7-31: unused
> +
> +Example 1:
> +---------
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + clocks = <&kryocc 0>;
> + cpu-supply = <&pm8994_s11_saw>;
> + operating-points-v2 = <&cluster0_opp>;
> + #cooling-cells = <2>;
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> + };
> +
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + clocks = <&kryocc 0>;
> + cpu-supply = <&pm8994_s11_saw>;
> + operating-points-v2 = <&cluster0_opp>;
> + #cooling-cells = <2>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU2: cpu@100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + clocks = <&kryocc 1>;
> + cpu-supply = <&pm8994_s11_saw>;
> + operating-points-v2 = <&cluster1_opp>;
> + #cooling-cells = <2>;
> + next-level-cache = <&L2_1>;
> + L2_1: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> + };
> +
> + CPU3: cpu@101 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x101>;
> + enable-method = "psci";
> + clocks = <&kryocc 1>;
> + cpu-supply = <&pm8994_s11_saw>;
> + operating-points-v2 = <&cluster1_opp>;
> + #cooling-cells = <2>;
> + next-level-cache = <&L2_1>;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> +
> + core1 {
> + cpu = <&CPU1>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&CPU2>;
> + };
> +
> + core1 {
> + cpu = <&CPU3>;
> + };
> + };
> + };
> + };
> +
> + cluster0_opp: opp_table0 {
> + compatible = "operating-points-v2-kryo-cpu";
> + nvmem-cells = <&speedbin_efuse>;
> + opp-shared;
> +
> + opp-307200000 {
> + opp-hz = /bits/ 64 <307200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x77>;
> + clock-latency-ns = <200000>;
> + };
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-422400000 {
> + opp-hz = /bits/ 64 <422400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-460800000 {
> + opp-hz = /bits/ 64 <460800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-480000000 {
> + opp-hz = /bits/ 64 <480000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-537600000 {
> + opp-hz = /bits/ 64 <537600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-556800000 {
> + opp-hz = /bits/ 64 <556800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-614400000 {
> + opp-hz = /bits/ 64 <614400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-652800000 {
> + opp-hz = /bits/ 64 <652800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-691200000 {
> + opp-hz = /bits/ 64 <691200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-729600000 {
> + opp-hz = /bits/ 64 <729600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-768000000 {
> + opp-hz = /bits/ 64 <768000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-844800000 {
> + opp-hz = /bits/ 64 <844800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x77>;
> + clock-latency-ns = <200000>;
> + };
> + opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-960000000 {
> + opp-hz = /bits/ 64 <960000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-979200000 {
> + opp-hz = /bits/ 64 <979200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1036800000 {
> + opp-hz = /bits/ 64 <1036800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1113600000 {
> + opp-hz = /bits/ 64 <1113600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1132800000 {
> + opp-hz = /bits/ 64 <1132800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1190400000 {
> + opp-hz = /bits/ 64 <1190400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1209600000 {
> + opp-hz = /bits/ 64 <1209600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1228800000 {
> + opp-hz = /bits/ 64 <1228800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1286400000 {
> + opp-hz = /bits/ 64 <1286400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1324800000 {
> + opp-hz = /bits/ 64 <1324800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x5>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1363200000 {
> + opp-hz = /bits/ 64 <1363200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x72>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1401600000 {
> + opp-hz = /bits/ 64 <1401600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x5>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1440000000 {
> + opp-hz = /bits/ 64 <1440000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1478400000 {
> + opp-hz = /bits/ 64 <1478400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1497600000 {
> + opp-hz = /bits/ 64 <1497600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x4>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1516800000 {
> + opp-hz = /bits/ 64 <1516800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1593600000 {
> + opp-hz = /bits/ 64 <1593600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x71>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1996800000 {
> + opp-hz = /bits/ 64 <1996800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x20>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2188800000 {
> + opp-hz = /bits/ 64 <2188800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x10>;
> + clock-latency-ns = <200000>;
> + };
> + };
> +
> + cluster1_opp: opp_table1 {
> + compatible = "operating-points-v2-kryo-cpu";
> + nvmem-cells = <&speedbin_efuse>;
> + opp-shared;
> +
> + opp-307200000 {
> + opp-hz = /bits/ 64 <307200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x77>;
> + clock-latency-ns = <200000>;
> + };
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-403200000 {
> + opp-hz = /bits/ 64 <403200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-460800000 {
> + opp-hz = /bits/ 64 <460800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-480000000 {
> + opp-hz = /bits/ 64 <480000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-537600000 {
> + opp-hz = /bits/ 64 <537600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-556800000 {
> + opp-hz = /bits/ 64 <556800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-614400000 {
> + opp-hz = /bits/ 64 <614400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-652800000 {
> + opp-hz = /bits/ 64 <652800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-691200000 {
> + opp-hz = /bits/ 64 <691200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-729600000 {
> + opp-hz = /bits/ 64 <729600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-748800000 {
> + opp-hz = /bits/ 64 <748800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-806400000 {
> + opp-hz = /bits/ 64 <806400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-825600000 {
> + opp-hz = /bits/ 64 <825600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-883200000 {
> + opp-hz = /bits/ 64 <883200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-940800000 {
> + opp-hz = /bits/ 64 <940800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-979200000 {
> + opp-hz = /bits/ 64 <979200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1036800000 {
> + opp-hz = /bits/ 64 <1036800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1113600000 {
> + opp-hz = /bits/ 64 <1113600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1132800000 {
> + opp-hz = /bits/ 64 <1132800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1190400000 {
> + opp-hz = /bits/ 64 <1190400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1209600000 {
> + opp-hz = /bits/ 64 <1209600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1286400000 {
> + opp-hz = /bits/ 64 <1286400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1324800000 {
> + opp-hz = /bits/ 64 <1324800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1363200000 {
> + opp-hz = /bits/ 64 <1363200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1401600000 {
> + opp-hz = /bits/ 64 <1401600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1440000000 {
> + opp-hz = /bits/ 64 <1440000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1478400000 {
> + opp-hz = /bits/ 64 <1478400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1516800000 {
> + opp-hz = /bits/ 64 <1516800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1555200000 {
> + opp-hz = /bits/ 64 <1555200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1593600000 {
> + opp-hz = /bits/ 64 <1593600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1632000000 {
> + opp-hz = /bits/ 64 <1632000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1670400000 {
> + opp-hz = /bits/ 64 <1670400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1708800000 {
> + opp-hz = /bits/ 64 <1708800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1747200000 {
> + opp-hz = /bits/ 64 <1747200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1785600000 {
> + opp-hz = /bits/ 64 <1785600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1804800000 {
> + opp-hz = /bits/ 64 <1804800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x6>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1824000000 {
> + opp-hz = /bits/ 64 <1824000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x71>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1900800000 {
> + opp-hz = /bits/ 64 <1900800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x74>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1920000000 {
> + opp-hz = /bits/ 64 <1920000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1977600000 {
> + opp-hz = /bits/ 64 <1977600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x30>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1996800000 {
> + opp-hz = /bits/ 64 <1996800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2054400000 {
> + opp-hz = /bits/ 64 <2054400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x30>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2073600000 {
> + opp-hz = /bits/ 64 <2073600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2150400000 {
> + opp-hz = /bits/ 64 <2150400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x31>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2246400000 {
> + opp-hz = /bits/ 64 <2246400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x10>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2342400000 {
> + opp-hz = /bits/ 64 <2342400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x10>;
> + clock-latency-ns = <200000>;
> + };
> + };
> +
> +....
> +
> +reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +....
> + smem_mem: smem-mem@86000000 {
> + reg = <0x0 0x86000000 0x0 0x200000>;
> + no-map;
> + };
> +....
> +};
> +
> +smem {
> + compatible = "qcom,smem";
> + memory-region = <&smem_mem>;
> + hwlocks = <&tcsr_mutex 3>;
> +};
> +
> +soc {
> +....
> + qfprom: qfprom@74000 {
> + compatible = "qcom,qfprom";
> + reg = <0x00074000 0x8ff>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ....
> + speedbin_efuse: speedbin@133 {
> + reg = <0x133 0x1>;
> + bits = <5 3>;
> + };
> + };
> +};
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v7 14/14] dt: qcom: Add qcom-cpufreq-kryo driver configuration
From: Amit Kucheria @ 2018-05-16 13:12 UTC (permalink / raw)
To: Ilia Lin
Cc: Michael Turquette, sboyd, Rob Herring, Mark Rutland, Viresh Kumar,
nm, lgirdwood, broonie, Andy Gross, David Brown, catalin.marinas,
will.deacon, Rafael J. Wysocki, linux-clk, devicetree, LKML,
Linux PM list, linux-arm-msm, linux-soc, lakml, Rajendra Nayak,
nicolas.dechesne, celster, tfinkel
In-Reply-To: <1526375616-16904-15-git-send-email-ilialin@codeaurora.org>
2018-05-15 12:13 GMT+03:00 Ilia Lin <ilialin@codeaurora.org>:
No commit message?
Perhaps something listing the different hw types?
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +-
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 311 +++++++++++++++++++++++++++-
> 2 files changed, 310 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
> index 230e9c8..da23bda 100644
> --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
> +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
> @@ -17,5 +17,5 @@
>
> / {
> model = "Qualcomm Technologies, Inc. DB820c";
> - compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
> + compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
> };
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index d7adef9..1dedfb8 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -174,218 +174,520 @@
> };
>
> cluster0_opp: opp_table0 {
> - compatible = "operating-points-v2";
> + compatible = "operating-points-v2-kryo-cpu",
> + "operating-points-v2";
> + nvmem-cells = <&speedbin_efuse>;
> opp-shared;
>
> opp-307200000 {
> opp-hz = /bits/ 64 <307200000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x77>;
> + clock-latency-ns = <200000>;
> + };
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-422400000 {
> opp-hz = /bits/ 64 <422400000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-460800000 {
> + opp-hz = /bits/ 64 <460800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-480000000 {
> opp-hz = /bits/ 64 <480000000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-537600000 {
> + opp-hz = /bits/ 64 <537600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-556800000 {
> opp-hz = /bits/ 64 <556800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-614400000 {
> + opp-hz = /bits/ 64 <614400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-652800000 {
> opp-hz = /bits/ 64 <652800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-691200000 {
> + opp-hz = /bits/ 64 <691200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-729600000 {
> opp-hz = /bits/ 64 <729600000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-768000000 {
> + opp-hz = /bits/ 64 <768000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-844800000 {
> opp-hz = /bits/ 64 <844800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x77>;
> + clock-latency-ns = <200000>;
> + };
> + opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-960000000 {
> opp-hz = /bits/ 64 <960000000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-979200000 {
> + opp-hz = /bits/ 64 <979200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1036800000 {
> opp-hz = /bits/ 64 <1036800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1113600000 {
> opp-hz = /bits/ 64 <1113600000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1132800000 {
> + opp-hz = /bits/ 64 <1132800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1190400000 {
> opp-hz = /bits/ 64 <1190400000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1209600000 {
> + opp-hz = /bits/ 64 <1209600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1228800000 {
> opp-hz = /bits/ 64 <1228800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1286400000 {
> + opp-hz = /bits/ 64 <1286400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1324800000 {
> opp-hz = /bits/ 64 <1324800000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x5>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1363200000 {
> + opp-hz = /bits/ 64 <1363200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x72>;
> clock-latency-ns = <200000>;
> };
> opp-1401600000 {
> opp-hz = /bits/ 64 <1401600000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x5>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1440000000 {
> + opp-hz = /bits/ 64 <1440000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1478400000 {
> opp-hz = /bits/ 64 <1478400000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1497600000 {
> + opp-hz = /bits/ 64 <1497600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x4>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1516800000 {
> + opp-hz = /bits/ 64 <1516800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1593600000 {
> opp-hz = /bits/ 64 <1593600000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x71>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1996800000 {
> + opp-hz = /bits/ 64 <1996800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x20>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2188800000 {
> + opp-hz = /bits/ 64 <2188800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x10>;
> clock-latency-ns = <200000>;
> };
> };
>
> cluster1_opp: opp_table1 {
> - compatible = "operating-points-v2";
> + compatible = "operating-points-v2-kryo-cpu";
> + nvmem-cells = <&speedbin_efuse>;
> opp-shared;
>
> opp-307200000 {
> opp-hz = /bits/ 64 <307200000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x77>;
> + clock-latency-ns = <200000>;
> + };
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-403200000 {
> opp-hz = /bits/ 64 <403200000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-460800000 {
> + opp-hz = /bits/ 64 <460800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-480000000 {
> opp-hz = /bits/ 64 <480000000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-537600000 {
> + opp-hz = /bits/ 64 <537600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-556800000 {
> opp-hz = /bits/ 64 <556800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-614400000 {
> + opp-hz = /bits/ 64 <614400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-652800000 {
> opp-hz = /bits/ 64 <652800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-691200000 {
> + opp-hz = /bits/ 64 <691200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-729600000 {
> opp-hz = /bits/ 64 <729600000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-748800000 {
> + opp-hz = /bits/ 64 <748800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-806400000 {
> opp-hz = /bits/ 64 <806400000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-825600000 {
> + opp-hz = /bits/ 64 <825600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-883200000 {
> opp-hz = /bits/ 64 <883200000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-940800000 {
> opp-hz = /bits/ 64 <940800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-979200000 {
> + opp-hz = /bits/ 64 <979200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1036800000 {
> opp-hz = /bits/ 64 <1036800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1113600000 {
> opp-hz = /bits/ 64 <1113600000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1132800000 {
> + opp-hz = /bits/ 64 <1132800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1190400000 {
> opp-hz = /bits/ 64 <1190400000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1209600000 {
> + opp-hz = /bits/ 64 <1209600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1248000000 {
> opp-hz = /bits/ 64 <1248000000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1286400000 {
> + opp-hz = /bits/ 64 <1286400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1324800000 {
> opp-hz = /bits/ 64 <1324800000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1363200000 {
> + opp-hz = /bits/ 64 <1363200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1401600000 {
> opp-hz = /bits/ 64 <1401600000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1440000000 {
> + opp-hz = /bits/ 64 <1440000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1478400000 {
> opp-hz = /bits/ 64 <1478400000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1516800000 {
> + opp-hz = /bits/ 64 <1516800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1555200000 {
> opp-hz = /bits/ 64 <1555200000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1593600000 {
> + opp-hz = /bits/ 64 <1593600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1632000000 {
> opp-hz = /bits/ 64 <1632000000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1670400000 {
> + opp-hz = /bits/ 64 <1670400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1708800000 {
> opp-hz = /bits/ 64 <1708800000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1747200000 {
> + opp-hz = /bits/ 64 <1747200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1785600000 {
> opp-hz = /bits/ 64 <1785600000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1804800000 {
> + opp-hz = /bits/ 64 <1804800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x6>;
> clock-latency-ns = <200000>;
> };
> opp-1824000000 {
> opp-hz = /bits/ 64 <1824000000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x71>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1900800000 {
> + opp-hz = /bits/ 64 <1900800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x74>;
> clock-latency-ns = <200000>;
> };
> opp-1920000000 {
> opp-hz = /bits/ 64 <1920000000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1977600000 {
> + opp-hz = /bits/ 64 <1977600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x30>;
> clock-latency-ns = <200000>;
> };
> opp-1996800000 {
> opp-hz = /bits/ 64 <1996800000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2054400000 {
> + opp-hz = /bits/ 64 <2054400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x30>;
> clock-latency-ns = <200000>;
> };
> opp-2073600000 {
> opp-hz = /bits/ 64 <2073600000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> clock-latency-ns = <200000>;
> };
> opp-2150400000 {
> opp-hz = /bits/ 64 <2150400000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x31>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2246400000 {
> + opp-hz = /bits/ 64 <2246400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x10>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2342400000 {
> + opp-hz = /bits/ 64 <2342400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x10>;
> clock-latency-ns = <200000>;
> };
> };
> @@ -992,6 +1294,11 @@
> reg = <0x24f 0x1>;
> bits = <1 4>;
> };
> +
> + speedbin_efuse: speedbin@133 {
> + reg = <0x133 0x1>;
> + bits = <5 3>;
> + };
> };
>
> phy@34000 {
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v7 12/14] cpufreq: Add Kryo CPU scaling driver
From: Amit Kucheria @ 2018-05-16 13:12 UTC (permalink / raw)
To: Ilia Lin
Cc: Michael Turquette, sboyd, Rob Herring, Mark Rutland, Viresh Kumar,
nm, lgirdwood, broonie, Andy Gross, David Brown, catalin.marinas,
will.deacon, Rafael J. Wysocki, linux-clk, devicetree, LKML,
Linux PM list, linux-arm-msm, linux-soc, lakml, Rajendra Nayak,
nicolas.dechesne, celster, tfinkel
In-Reply-To: <1526375616-16904-13-git-send-email-ilialin@codeaurora.org>
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote:
> In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
> the CPU ferequencies subset and voltage value of each OPP varies
s/ferequencies/frequency
> based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
> defines the voltage and frequency value based on the msm-id in SMEM
> and speedbin blown in the efuse combination.
> The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
> to provide the OPP framework with required information.
> This is used to determine the voltage and frequency value for each OPP of
> operating-points-v2 table when it is parsed by the OPP framework.
>
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> drivers/cpufreq/Kconfig.arm | 11 +++
> drivers/cpufreq/Makefile | 1 +
> drivers/cpufreq/cpufreq-dt-platdev.c | 3 +
> drivers/cpufreq/qcom-cpufreq-kryo.c | 150 +++++++++++++++++++++++++++++++++++
> 4 files changed, 165 insertions(+)
> create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
>
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index de55c7d..5c16f05 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -124,6 +124,17 @@ config ARM_OMAP2PLUS_CPUFREQ
> depends on ARCH_OMAP2PLUS
> default ARCH_OMAP2PLUS
>
> +config ARM_QCOM_CPUFREQ_KRYO
> + bool "Qualcomm Technologies, Inc. Kryo based CPUFreq"
"Qualcomm Kryo CPUFreq support" should be enough. Kconfig isn't the
place for Trademark compliance :-)
> + depends on QCOM_QFPROM
> + depends on QCOM_SMEM
> + select PM_OPP
> + help
> + This adds the CPUFreq driver for
> + Qualcomm Technologies, Inc. Kryo SoC based boards.
> +
> + If in doubt, say N.
> +
> config ARM_S3C_CPUFREQ
> bool
> help
> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
> index 8d24ade..fb4a2ec 100644
> --- a/drivers/cpufreq/Makefile
> +++ b/drivers/cpufreq/Makefile
> @@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
> obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
> obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
> obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
> +obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o
> obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
> obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o
> obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index 3b585e4..77d6ab8 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -118,6 +118,9 @@
>
> { .compatible = "nvidia,tegra124", },
>
> + { .compatible = "qcom,apq8096", },
> + { .compatible = "qcom,msm8996", },
> +
> { .compatible = "st,stih407", },
> { .compatible = "st,stih410", },
>
> diff --git a/drivers/cpufreq/qcom-cpufreq-kryo.c b/drivers/cpufreq/qcom-cpufreq-kryo.c
> new file mode 100644
> index 0000000..10d7236
> --- /dev/null
> +++ b/drivers/cpufreq/qcom-cpufreq-kryo.c
> @@ -0,0 +1,150 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
Stray space here.
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/cpu.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/nvmem-consumer.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/slab.h>
> +#include <linux/soc/qcom/smem.h>
> +
> +#define MSM_ID_SMEM 137
> +#define SILVER_LEAD 0
> +#define GOLD_LEAD 2
> +
> +enum _msm_id {
> + MSM8996V3 = 0xF6ul,
> + APQ8096V3 = 0x123ul,
> + MSM8996SG = 0x131ul,
> + APQ8096SG = 0x138ul,
> +};
> +
> +enum _msm8996_version {
> + MSM8996_V3,
> + MSM8996_SG,
> + NUM_OF_MSM8996_VERSIONS,
> +};
> +
> +static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id(void)
> +{
> + size_t len;
> + u32 *msm_id;
> + enum _msm8996_version version;
> +
> + msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len);
> + /* The first 4 bytes are format, next to them is the actual msm-id */
> + msm_id++;
> +
> + switch ((enum _msm_id)*msm_id) {
> + case MSM8996V3:
> + case APQ8096V3:
> + version = MSM8996_V3;
> + break;
> + case MSM8996SG:
> + case APQ8096SG:
> + version = MSM8996_SG;
> + break;
> + default:
> + version = NUM_OF_MSM8996_VERSIONS;
> + }
> +
> + return version;
> +}
> +
> +static int __init qcom_cpufreq_kryo_driver_init(void)
> +{
> + size_t len;
> + int ret;
> + u32 versions;
> + enum _msm8996_version msm8996_version;
> + u8 *speedbin;
> + struct device *cpu_dev;
> + struct device_node *np;
> + struct nvmem_cell *speedbin_nvmem;
> + struct opp_table *opp_temp = NULL;
> +
> + cpu_dev = get_cpu_device(SILVER_LEAD);
> + if (IS_ERR_OR_NULL(cpu_dev))
> + return PTR_ERR(cpu_dev);
> +
> + msm8996_version = qcom_cpufreq_kryo_get_msm_id();
> + if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
> + dev_err(cpu_dev, "Not Snapdragon 820/821!");
> + return -ENODEV;
> + }
Use tab instead of spaces.
> +
> + np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
> + if (IS_ERR_OR_NULL(np))
> + return PTR_ERR(np);
> +
> + if (!of_device_is_compatible(np, "operating-points-v2-kryo-cpu")) {
> + ret = -ENOENT;
> + goto free_np;
> + }
> +
> + speedbin_nvmem = of_nvmem_cell_get(np, NULL);
> + if (IS_ERR(speedbin_nvmem)) {
> + ret = PTR_ERR(speedbin_nvmem);
> + dev_err(cpu_dev, "Could not get nvmem cell: %d\n", ret);
> + goto free_np;
> + }
> +
> + speedbin = nvmem_cell_read(speedbin_nvmem, &len);
> +
> + switch (msm8996_version) {
> + case MSM8996_V3:
> + versions = 1 << (unsigned int)(*speedbin);
> + break;
> + case MSM8996_SG:
> + versions = 1 << ((unsigned int)(*speedbin) + 4);
> + break;
> + default:
> + BUG();
> + break;
> + }
> +
> + ret = PTR_ERR_OR_ZERO(opp_temp =
> + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1));
> + if (0 > ret)
Any particular reason to prefer this over (ret < 0) that is generally
used? I've seen it used to avoid the == vs. = typos, but not for other
comparisons.
Suggest sticking to what is commonly used i.e. ret < 0.
> + goto free_opp;
> +
> + cpu_dev = get_cpu_device(GOLD_LEAD);
Error check cpu_dev here?
> + ret = PTR_ERR_OR_ZERO(opp_temp =
> + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1));
> + if (0 > ret)
> + goto free_opp;
> +
> +
> + ret = PTR_ERR_OR_ZERO(platform_device_register_simple("cpufreq-dt",
> + -1, NULL, 0));
> +
> + if (0 == ret)
> + return 0;
> +
> +free_opp:
> + dev_pm_opp_put_supported_hw(opp_temp);
This is not needed because dev_pm_opp_set_supported_hw will free
memory in case of failure. This call in only needed in case of a
successful get.
> +
> +free_np:
> + of_node_put(np);
> + return ret;
Suggest something like this instead:
.
.
opp_temp = dev_pm_opp_set_supported_hw(cpu_dev,&versions,1));
if (IS_ERR(opp_temp)) {
dev_err(cpu_dev, "Failed to set supported hardware\n");
ret = PTR_ERR(opp_temp);
goto free_np;
}
cpu_dev = get_cpu_device(GOLD_LEAD);
opp_temp = dev_pm_opp_set_supported_hw(cpu_dev,&versions,1));
if (IS_ERR(opp_temp)) {
dev_err(cpu_dev, "Failed to set supported hardware\n");
ret = PTR_ERR(opp_temp);
goto free_np;
}
ret = platform_device_register_simple("cpufreq-dt", -1, NULL, 0));
if (!IS_ERR_OR_NULL(ret))
goto out;
free_np:
of_node_put(np);
out:
return ret;
> +}
> +late_initcall(qcom_cpufreq_kryo_driver_init);
> +
> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver");
> +MODULE_LICENSE("GPL v2");
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v7 10/14] dt-bindings: qcom_spmi: Add support for SAW documentation
From: Amit Kucheria @ 2018-05-16 13:12 UTC (permalink / raw)
To: Ilia Lin
Cc: Michael Turquette, sboyd, Rob Herring, Mark Rutland, Viresh Kumar,
nm, lgirdwood, broonie, Andy Gross, David Brown, catalin.marinas,
will.deacon, Rafael J. Wysocki, linux-clk, devicetree, LKML,
Linux PM list, linux-arm-msm, linux-soc, lakml, Rajendra Nayak,
nicolas.dechesne, celster, tfinkel
In-Reply-To: <1526375616-16904-11-git-send-email-ilialin@codeaurora.org>
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote:
> Add support for SAW controlled regulators.
> The regulators defined as SAW controlled in the device tree
> will be controlled through special CPU registers instead of direct
> SPMI accesses.
> This is required especially for CPU supply regulators to synchronize
> with clock scaling and for Automatic Voltage Switching.
> Document it.
Replace this boiler plate with what this patch actual does. Besides
changing the subject, it could be, for example,
"Document the DT bindings for the SAW regulators.
The saw-slave property allows ganging (grouping) of several regulators
so that their outputs can be combined... blah blah.
The saw-leader is the only one that then is configurable in DT"
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> .../bindings/regulator/qcom,spmi-regulator.txt | 45 ++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt
> index 57d2c65..406f2e5 100644
> --- a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt
> +++ b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt
> @@ -110,6 +110,11 @@ Qualcomm SPMI Regulators
> Definition: Reference to regulator supplying the input pin, as
> described in the data sheet.
>
> +- qcom,saw-reg:
> + Usage: optional
> + Value type: <phandle>
> + Description: Reference to syscon node defining the SAW registers.
> +
>
> The regulator node houses sub-nodes for each regulator within the device. Each
> sub-node is identified using the node's name, with valid values listed for each
> @@ -201,6 +206,17 @@ see regulator.txt - with additional custom properties described below:
> 2 = 0.55 uA
> 3 = 0.75 uA
>
> +- qcom,saw-slave:
> + Usage: optional
> + Value type: <boo>
> + Description: SAW controlled gang slave. Will not be configured.
> +
> +- qcom,saw-leader:
> + Usage: optional
> + Value type: <boo>
> + Description: SAW controlled gang leader. Will be configured as
> + SAW regulator.
> +
> Example:
>
> regulators {
> @@ -221,3 +237,32 @@ Example:
>
> ....
> };
> +
> +Example 2:
> +
> + saw3: syscon@9A10000 {
> + compatible = "syscon";
> + reg = <0x9A10000 0x1000>;
> + };
> +
> + ...
> +
> + spm-regulators {
> + compatible = "qcom,pm8994-regulators";
> + qcom,saw-reg = <&saw3>;
> + s8 {
> + qcom,saw-slave;
> + };
> + s9 {
> + qcom,saw-slave;
> + };
> + s10 {
> + qcom,saw-slave;
> + };
> + pm8994_s11_saw: s11 {
> + qcom,saw-leader;
> + regulator-always-on;
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1140000>;
> + };
> + };
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v7 03/14] clk: qcom: Add CPU clock driver for msm8996
From: Amit Kucheria @ 2018-05-16 13:12 UTC (permalink / raw)
To: Ilia Lin
Cc: Michael Turquette, sboyd, Rob Herring, Mark Rutland, Viresh Kumar,
nm, lgirdwood, broonie, Andy Gross, David Brown, catalin.marinas,
will.deacon, Rafael J. Wysocki, linux-clk, devicetree, LKML,
Linux PM list, linux-arm-msm, linux-soc, lakml, Rajendra Nayak,
nicolas.dechesne, celster, tfinkel
In-Reply-To: <1526375616-16904-4-git-send-email-ilialin@codeaurora.org>
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote:
> Each of the CPU clusters (Power and Perf) on msm8996 are
> clocked via 2 PLLs, a primary and alternate. There are also
> 2 Mux'es, a primary and secondary all connected together
> as shown below
>
> +-------+
> XO | |
> +------------------>0 |
> | |
> PLL/2 | SMUX +----+
> +------->1 | |
> | | | |
> | +-------+ | +-------+
> | +---->0 |
> | | |
> +---------------+ | +----------->1 | CPU clk
> |Primary PLL +----+ PLL_EARLY | | +------>
> | +------+-----------+ +------>2 PMUX |
> +---------------+ | | | |
> | +------+ | +-->3 |
> +--^+ ACD +-----+ | +-------+
> +---------------+ +------+ |
> |Alt PLL | |
> | +---------------------------+
> +---------------+ PLL_EARLY
>
> The primary PLL is what drives the CPU clk, except for times
> when we are reprogramming the PLL itself (for rate changes) when
> we temporarily switch to an alternate PLL. A subsequent patch adds
> support to switch between primary and alternate PLL during rate
> changes.
>
> The primary PLL operates on a single VCO range, between 600MHz
> and 3GHz. However the CPUs do support OPPs with frequencies
> between 300MHz and 600MHz. In order to support running the CPUs
> at those frequencies we end up having to lock the PLL at twice
> the rate and drive the CPU clk via the PLL/2 output and SMUX.
>
> So for frequencies above 600MHz we follow the following path
> Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
> and for frequencies between 300MHz and 600MHz we follow
> Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
> Support for this is added in a subsequent patch as well.
>
> ACD stands for Adaptive Clock Distribution and is used to
> detect voltage droops. We do not add support for ACD as yet.
>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> drivers/clk/clk-fixed-factor.c | 2 +-
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/clk-alpha-pll.h | 6 +
> drivers/clk/qcom/clk-cpu-8996.c | 412 +++++++++++++++++++++++++++++++++++++++
> 5 files changed, 429 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/qcom/clk-cpu-8996.c
>
> diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
> index a5d402d..8e39bda 100644
> --- a/drivers/clk/clk-fixed-factor.c
> +++ b/drivers/clk/clk-fixed-factor.c
> @@ -94,7 +94,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
> init.num_parents = 1;
>
> hw = &fix->hw;
> - ret = clk_hw_register(dev, hw);
> + ret = devm_clk_hw_register(dev, hw);
This should probably go in its own separate patch.
> if (ret) {
> kfree(fix);
> hw = ERR_PTR(ret);
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index e42e1af..866ce1f 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -33,6 +33,15 @@ config QCOM_CLK_APCS_MSM8916
> Say Y if you want to support CPU frequency scaling on devices
> such as msm8916.
>
> +config QCOM_CLK_APCC_MSM8996
> + tristate "MSM8996 CPU Clock Controller"
> + depends on COMMON_CLK_QCOM
> + select QCOM_KRYO_L2_ACCESSORS
> + help
> + Support for the CPU clock controller on msm8996 devices.
> + Say Y if you want to support CPU clock scaling using CPUfreq
> + drivers for dyanmic power management.
> +
> config QCOM_CLK_RPM
> tristate "RPM based Clock Controller"
> depends on COMMON_CLK_QCOM && MFD_QCOM_RPM
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 7c09ab1..a822fc8 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
> obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
> obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
> obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
> +obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o
> obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
> obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
> obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> index f981b48..9ce2a32 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.h
> +++ b/drivers/clk/qcom/clk-alpha-pll.h
> @@ -50,6 +50,12 @@ struct pll_vco {
> u32 val;
> };
>
> +#define VCO(a, b, c) { \
> + .val = a,\
> + .min_freq = b,\
> + .max_freq = c,\
> +}
> +
> /**
> * struct clk_alpha_pll - phase locked loop (PLL)
> * @offset: base address of registers
> diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
> new file mode 100644
> index 0000000..beb97eb
> --- /dev/null
> +++ b/drivers/clk/qcom/clk-cpu-8996.c
> @@ -0,0 +1,412 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/*
> + * Each of the CPU clusters (Power and Perf) on msm8996 are
> + * clocked via 2 PLLs, a primary and alternate. There are also
> + * 2 Mux'es, a primary and secondary all connected together
> + * as shown below
> + *
> + * +-------+
> + * XO | |
> + * +------------------>0 |
> + * | |
> + * PLL/2 | SMUX +----+
> + * +------->1 | |
> + * | | | |
> + * | +-------+ | +-------+
> + * | +---->0 |
> + * | | |
> + * +---------------+ | +----------->1 | CPU clk
> + * |Primary PLL +----+ PLL_EARLY | | +------>
> + * | +------+-----------+ +------>2 PMUX |
> + * +---------------+ | | | |
> + * | +------+ | +-->3 |
> + * +--^+ ACD +-----+ | +-------+
> + * +---------------+ +------+ |
> + * |Alt PLL | |
> + * | +---------------------------+
> + * +---------------+ PLL_EARLY
> + *
> + * The primary PLL is what drives the CPU clk, except for times
> + * when we are reprogramming the PLL itself (for rate changes) when
> + * we temporarily switch to an alternate PLL. A subsequent patch adds
> + * support to switch between primary and alternate PLL during rate
> + * changes.
> + *
> + * The primary PLL operates on a single VCO range, between 600MHz
> + * and 3GHz. However the CPUs do support OPPs with frequencies
> + * between 300MHz and 600MHz. In order to support running the CPUs
> + * at those frequencies we end up having to lock the PLL at twice
> + * the rate and drive the CPU clk via the PLL/2 output and SMUX.
> + *
> + * So for frequencies above 600MHz we follow the following path
> + * Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
> + * and for frequencies between 300MHz and 600MHz we follow
> + * Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
> + * Support for this is added in a subsequent patch as well.
> + *
> + * ACD stands for Adaptive Clock Distribution and is used to
> + * detect voltage droops. We do not add support for ACD as yet.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-regmap.h"
> +
> +enum _pmux_input {
> + DIV_2_INDEX = 0,
> + PLL_INDEX,
> + ACD_INDEX,
> + ALT_INDEX,
> + NUM_OF_PMUX_INPUTS
> +};
> +
> +static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
> + [PLL_OFF_L_VAL] = 0x04,
> + [PLL_OFF_ALPHA_VAL] = 0x08,
> + [PLL_OFF_USER_CTL] = 0x10,
> + [PLL_OFF_CONFIG_CTL] = 0x18,
> + [PLL_OFF_CONFIG_CTL_U] = 0x1c,
> + [PLL_OFF_TEST_CTL] = 0x20,
> + [PLL_OFF_TEST_CTL_U] = 0x24,
> + [PLL_OFF_STATUS] = 0x28,
> +};
> +
> +static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = {
> + [PLL_OFF_L_VAL] = 0x04,
> + [PLL_OFF_ALPHA_VAL] = 0x08,
> + [PLL_OFF_ALPHA_VAL_U] = 0x0c,
> + [PLL_OFF_USER_CTL] = 0x10,
> + [PLL_OFF_USER_CTL_U] = 0x14,
> + [PLL_OFF_CONFIG_CTL] = 0x18,
> + [PLL_OFF_TEST_CTL] = 0x20,
> + [PLL_OFF_TEST_CTL_U] = 0x24,
> + [PLL_OFF_STATUS] = 0x28,
> +};
> +
> +/* PLLs */
> +
> +static const struct alpha_pll_config hfpll_config = {
> + .l = 60,
> + .config_ctl_val = 0x200d4828,
> + .config_ctl_hi_val = 0x006,
> + .pre_div_mask = BIT(12),
> + .post_div_mask = 0x3 << 8,
> + .main_output_mask = BIT(0),
> + .early_output_mask = BIT(3),
> +};
> +
> +static struct clk_alpha_pll perfcl_pll = {
> + .offset = 0x80000,
> + .regs = prim_pll_regs,
> + .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "perfcl_pll",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_huayra_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll pwrcl_pll = {
> + .offset = 0x0,
> + .regs = prim_pll_regs,
> + .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "pwrcl_pll",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_huayra_ops,
> + },
> +};
> +
> +static const struct pll_vco alt_pll_vco_modes[] = {
> + VCO(3, 250000000, 500000000),
> + VCO(2, 500000000, 750000000),
> + VCO(1, 750000000, 1000000000),
> + VCO(0, 1000000000, 2150400000),
> +};
> +
> +static const struct alpha_pll_config altpll_config = {
> + .l = 16,
> + .vco_val = 0x3 << 20,
> + .vco_mask = 0x3 << 20,
> + .config_ctl_val = 0x4001051b,
> + .post_div_mask = 0x3 << 8,
> + .post_div_val = 0x1,
> + .main_output_mask = BIT(0),
> + .early_output_mask = BIT(3),
> +};
> +
> +static struct clk_alpha_pll perfcl_alt_pll = {
> + .offset = 0x80100,
> + .regs = alt_pll_regs,
> + .vco_table = alt_pll_vco_modes,
> + .num_vco = ARRAY_SIZE(alt_pll_vco_modes),
> + .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "perfcl_alt_pll",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_hwfsm_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll pwrcl_alt_pll = {
> + .offset = 0x100,
> + .regs = alt_pll_regs,
> + .vco_table = alt_pll_vco_modes,
> + .num_vco = ARRAY_SIZE(alt_pll_vco_modes),
> + .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "pwrcl_alt_pll",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_hwfsm_ops,
> + },
> +};
> +
> +/* Mux'es */
> +
> +struct clk_cpu_8996_mux {
> + u32 reg;
> + u8 shift;
> + u8 width;
> + struct clk_hw *pll;
> + struct clk_regmap clkr;
> +};
> +
> +static inline
> +struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw)
> +{
> + return container_of(to_clk_regmap(hw), struct clk_cpu_8996_mux, clkr);
> +}
> +
> +static u8 clk_cpu_8996_mux_get_parent(struct clk_hw *hw)
> +{
> + u32 val;
> + struct clk_regmap *clkr = to_clk_regmap(hw);
> + struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
> + u32 mask = (u32)GENMASK(cpuclk->width - 1, 0);
> +
> + regmap_read(clkr->regmap, cpuclk->reg, &val);
> + val >>= (u32)(cpuclk->shift);
> +
> + return (u8)(val & mask);
> +}
> +
> +static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
> +{
> + u32 val;
> + struct clk_regmap *clkr = to_clk_regmap(hw);
> + struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
> + unsigned int mask = GENMASK(cpuclk->width + cpuclk->shift - 1,
> + cpuclk->shift);
> +
> + val = (u32)index;
> + val <<= (u32)(cpuclk->shift);
> +
> + return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);
> +}
> +
> +static int
> +clk_cpu_8996_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
> +{
> + struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
> + struct clk_hw *parent = cpuclk->pll;
> +
> + req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
> + req->best_parent_hw = parent;
> +
> + return 0;
> +}
> +
> +const struct clk_ops clk_cpu_8996_mux_ops = {
> + .set_parent = clk_cpu_8996_mux_set_parent,
> + .get_parent = clk_cpu_8996_mux_get_parent,
> + .determine_rate = clk_cpu_8996_mux_determine_rate,
> +};
> +
> +static struct clk_cpu_8996_mux pwrcl_smux = {
> + .reg = 0x40,
> + .shift = 2,
> + .width = 2,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "pwrcl_smux",
> + .parent_names = (const char *[]){
> + "xo",
> + "pwrcl_pll_main",
> + },
> + .num_parents = 2,
> + .ops = &clk_cpu_8996_mux_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_cpu_8996_mux perfcl_smux = {
> + .reg = 0x80040,
> + .shift = 2,
> + .width = 2,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "perfcl_smux",
> + .parent_names = (const char *[]){
> + "xo",
> + "perfcl_pll_main",
> + },
> + .num_parents = 2,
> + .ops = &clk_cpu_8996_mux_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_cpu_8996_mux pwrcl_pmux = {
> + .reg = 0x40,
> + .shift = 0,
> + .width = 2,
> + .pll = &pwrcl_pll.clkr.hw,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "pwrcl_pmux",
> + .parent_names = (const char *[]){
> + "pwrcl_smux",
> + "pwrcl_pll",
> + "pwrcl_pll_acd",
> + "pwrcl_alt_pll",
> + },
> + .num_parents = 4,
> + .ops = &clk_cpu_8996_mux_ops,
> + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> + },
> +};
> +
> +static struct clk_cpu_8996_mux perfcl_pmux = {
> + .reg = 0x80040,
> + .shift = 0,
> + .width = 2,
> + .pll = &perfcl_pll.clkr.hw,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "perfcl_pmux",
> + .parent_names = (const char *[]){
> + "perfcl_smux",
> + "perfcl_pll",
> + "perfcl_pll_acd",
> + "perfcl_alt_pll",
> + },
> + .num_parents = 4,
> + .ops = &clk_cpu_8996_mux_ops,
> + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> + },
> +};
> +
> +static const struct regmap_config cpu_msm8996_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x80210,
> + .fast_io = true,
> + .val_format_endian = REGMAP_ENDIAN_LITTLE,
> +};
> +
> +struct clk_regmap *clks[] = {
> + &perfcl_pll.clkr,
> + &pwrcl_pll.clkr,
> + &perfcl_alt_pll.clkr,
> + &pwrcl_alt_pll.clkr,
> + &perfcl_smux.clkr,
> + &pwrcl_smux.clkr,
> + &perfcl_pmux.clkr,
> + &pwrcl_pmux.clkr,
> +};
> +
> +static int
> +qcom_cpu_clk_msm8996_register_clks(struct device *dev, struct regmap *regmap)
> +{
> + int i, ret;
> +
> + perfcl_smux.pll = clk_hw_register_fixed_factor(dev, "perfcl_pll_main",
> + "perfcl_pll",
> + CLK_SET_RATE_PARENT, 1, 2);
> +
> + pwrcl_smux.pll = clk_hw_register_fixed_factor(dev, "pwrcl_pll_main",
> + "pwrcl_pll",
> + CLK_SET_RATE_PARENT, 1, 2);
> +
> + for (i = 0; i < ARRAY_SIZE(clks); i++) {
> + ret = devm_clk_register_regmap(dev, clks[i]);
> + if (ret)
> + return ret;
> + }
> +
> + clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
> + clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);
> + clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
> + clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
> +
> + return ret;
> +}
> +
> +static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
> +{
> + int ret;
> + void __iomem *base;
> + struct resource *res;
> + struct regmap *regmap;
> + struct clk_hw_onecell_data *data;
> + struct device *dev = &pdev->dev;
> +
> + data = devm_kzalloc(dev, sizeof(*data) + 2 * sizeof(struct clk_hw *),
> + GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + regmap = devm_regmap_init_mmio(dev, base, &cpu_msm8996_regmap_config);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + ret = qcom_cpu_clk_msm8996_register_clks(dev, regmap);
> + if (ret)
> + return ret;
> +
> + data->hws[0] = &pwrcl_pmux.clkr.hw;
> + data->hws[1] = &perfcl_pmux.clkr.hw;
> + data->num = 2;
> +
> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
> +}
> +
> +static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = {
> + { .compatible = "qcom,msm8996-apcc" },
> + {}
> +};
> +
> +static struct platform_driver qcom_cpu_clk_msm8996_driver = {
> + .probe = qcom_cpu_clk_msm8996_driver_probe,
> + .driver = {
> + .name = "qcom-msm8996-apcc",
> + .of_match_table = qcom_cpu_clk_msm8996_match_table,
> + },
> +};
> +module_platform_driver(qcom_cpu_clk_msm8996_driver);
> +
> +MODULE_ALIAS("platform:msm8996-apcc");
> +MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver");
> +MODULE_LICENSE("GPL v2");
> --
> 1.9.1
>
^ permalink raw reply
* Re: 答复: [PATCH v9 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs
From: Rob Herring @ 2018-05-16 13:16 UTC (permalink / raw)
To: liwei (CM)
Cc: mark.rutland@arm.com, catalin.marinas@arm.com,
will.deacon@arm.com, vinholikatti@gmail.com,
jejb@linux.vnet.ibm.com, martin.petersen@oracle.com,
khilman@baylibre.com, arnd@arndb.de,
gregory.clement@free-electrons.com,
thomas.petazzoni@free-electrons.com,
yamada.masahiro@socionext.com, riku.voipio@linaro.org,
treding@nvidia.com, krzk@kernel.org
In-Reply-To: <1699CE87DE933F49876AD744B5DC140FA5AC86@DGGEMM506-MBS.china.huawei.com>
On Tue, Apr 24, 2018 at 8:54 AM, liwei (CM) <liwei213@huawei.com> wrote:
> Hi, Rob
>
> Thanks for your patience.
>
> Hi, Arnd
>
> From Rob's suggestion, we have to list the properties node in ufs-hisi.txt bingings even if documented in the common binding.
>
> -----邮件原件-----
> 发件人: Rob Herring [mailto:robh@kernel.org]
> 发送时间: 2018年4月24日 20:58
> 收件人: liwei (CM)
> 抄送: mark.rutland@arm.com; catalin.marinas@arm.com; will.deacon@arm.com; vinholikatti@gmail.com; jejb@linux.vnet.ibm.com; martin.petersen@oracle.com; khilman@baylibre.com; arnd@arndb.de; gregory.clement@free-electrons.com; thomas.petazzoni@free-electrons.com; yamada.masahiro@socionext.com; riku.voipio@linaro.org; treding@nvidia.com; krzk@kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-scsi@vger.kernel.org; zangleigang; Gengjianfeng; guodong.xu@linaro.org
> 主题: Re: [PATCH v9 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs
>
> On Tue, Apr 17, 2018 at 10:08:11PM +0800, Li Wei wrote:
>> add ufs node document for Hisilicon.
>>
>> Signed-off-by: Li Wei <liwei213@huawei.com>
>> ---
>> Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 29 ++++++++++++++++++++++
>> .../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 10 +++++---
>> 2 files changed, 36 insertions(+), 3 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt
>>
>> diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
>> new file mode 100644
>> index 000000000000..d49ab7d8f31d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
>> @@ -0,0 +1,29 @@
>> +* Hisilicon Universal Flash Storage (UFS) Host Controller
>> +
>> +UFS nodes are defined to describe on-chip UFS hardware macro.
>> +Each UFS Host Controller should have its own node.
>> +
>> +Required properties:
>> +- compatible : compatible list, contains one of the following -
>> + "hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs
>> + host controller present on Hi36xx chipset.
>> +- reg : should contain UFS register address space & UFS SYS CTRL register address,
>> +- interrupt-parent : interrupt device
>> +- interrupts : interrupt number
>> +- resets : reset node register, the "arst" corresponds to reset the APB/AXI bus.
>
> arst belongs in reset-names.
>
> OK, I will fix it in next patch;
>
>> +- reset-names : describe reset node register
>
> What happened to clocks? You still have to list which ones apply even if
> documented in the common binding.
>
> OK, I will fix it in next patch;
>
>> +
>> +Example:
>> +
>> + ufs: ufs@ff3b0000 {
>> + compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
>> + /* 0: HCI standard */
>> + /* 1: UFS SYS CTRL */
>> + reg = <0x0 0xff3b0000 0x0 0x1000>,
>> + <0x0 0xff3b1000 0x0 0x1000>;
>> + interrupt-parent = <&gic>;
>> + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
>> + /* offset: 0x84; bit: 7 */
>> + resets = <&crg_rst 0x84 7>;
>> + reset-names = "arst";
>> + };
>> diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
>> index c39dfef76a18..adcfb79f63f5 100644
>> --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
>> +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
>> @@ -41,6 +41,8 @@ Optional properties:
>> -lanes-per-direction : number of lanes available per direction - either 1 or 2.
>> Note that it is assume same number of lanes is used both
>> directions at once. If not specified, default is 2 lanes per direction.
>> +- resets : reset node register, the "rst" corresponds to reset the whole UFS IP.
>> +- reset-names : describe reset node register
>
> Does your controller have 1 or 2 resets? There's no point in adding this
> here if it doesn't apply to your controller.
>
> There are 2 reset in our soc init, the "rst" corresponds to reset the whole UFS IP, and " arst " only reset the APB/AXI bus.
> Discussed with our soc colleagues that "arst" is assert by default and needs to deassert,but it done in bootloader,so will remove 'arst' in next patch.
>
> About the 'reset' property，it seems that Arnd Bergmann has different suggestion，he suggested that add 'rst' to ufshcd-pltfrm because it seems common.
> But it looks like only our soc init needs it. What's your opinion? Does it still needs add to common bindings?
For a single reset, then I'm fine with it being in the common
bindings. If there are multiple then it should be in the specific
bindings as the reset names are likely different.
Rob
^ permalink raw reply
* AW: [PATCH v3] Input: add bu21029 touch driver
From: Jonas Mark (BT-FIR/ENG1) @ 2018-05-16 13:24 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Dmitry Torokhov, Rob Herring, Mark Rutland, linux-input,
devicetree, Linux Kernel Mailing List, Heiko Schocher,
ZHU Yi (BT-FIR/ENG1-Zhu), Jonas Mark (BT-FIR/ENG1)
In-Reply-To: <CAHp75Vf=eJbJPv5=y3fDKZapAnmABD0=v+WRhrBhMv+RSoBnKg@mail.gmail.com>
Hello Andy,
> > Add Rohm BU21029 resistive touch panel controller support with I2C
> > interface.
>
> > +#include <linux/of.h>
>
> This becomes redundant (see below).
Removed.
> > +#define STOP_DELAY_US 50L
> > +#define START_DELAY_MS 2L
> > +#define BUF_LEN 8L
>
> No need to use L for such small numbers. Integer promotion is a part
> of C standard.
OK.
> > +#define SCALE_12BIT (1 << 12)
> > +#define MAX_12BIT ((1 << 12) - 1)
>
> BIT(12)
> GENMASK(11, 0)
We are not convinced that we should use BIT() and GENMASK() here.
The reason is that SCALE_12BIT is actually not used as a bit but as an
input value for DIV_ROUND_CLOSEST. We think that the BIT() macro will
hide the meaning of the value.
MAX_12BIT is also a value and not a bit mask. Thus, we also think that
using the GENMASK() macro will hide its purpose. Also, the
documentation of GENMASK() says that it is a mask and not a value.
> > +static int bu21029_touch_report(struct bu21029_ts_data *bu21029)
> > +{
> > + struct i2c_client *i2c = bu21029->client;
> > + u8 buf[BUF_LEN];
> > + int error = bu21029_touch_report(bu21029);
>
> > +
>
> Redundant empty line.
Removed.
> > + if (error) {
>
> > + dev_err(&i2c->dev, "failed to report (error: %d)\n", error);
>
> Potential spamming case.
>
> > + return IRQ_NONE;
> > + }
You are right, we will remove the error message.
> > +static void bu21029_stop_chip(struct input_dev *dev)
> > +{
> > + struct bu21029_ts_data *bu21029 = input_get_drvdata(dev);
> > +
> > + disable_irq(bu21029->client->irq);
> > + del_timer_sync(&bu21029->timer);
> > +
> > + /* put chip into reset */
> > + gpiod_set_value_cansleep(bu21029->reset_gpios, 1);
>
> > + udelay(STOP_DELAY_US);
>
> udelay() ?!
>
> > +}
According to the datasheet disabling the chip will take 30 microseconds.
In the defines we added a buffer of 20 microseconds and thus
STOP_DELAY_US is 50. The function guarantees that the chip is stopped
before it returns.
We think that it is ok to use udelay() here because in normal operation
the chip is not stopped. It is only stopped when loading or unloading
the driver, or when the system suspends.
We would like to keep it like it is.
> > +static int bu21029_start_chip(struct input_dev *dev)
> > +{
>
> > + u16 hwid;
> > +
> > + /* take chip out of reset */
> > + gpiod_set_value_cansleep(bu21029->reset_gpios, 0);
>
> > + mdelay(START_DELAY_MS);
>
> mdelay()?!
>
> > +
> > + error = i2c_smbus_read_i2c_block_data(i2c,
> > + BU21029_HWID_REG,
> > + 2,
> > + (u8 *)&hwid);
> > + if (error < 0) {
> > + dev_err(&i2c->dev, "failed to read HW ID\n");
> > + goto out;
> > + }
After de-asserting the reset chip takes 1 millisecond until it is
operational. We added a 1 millisecond buffer to it. Thus,
START_DELAY_MS is 2.
The following I2C read will not succeed without waiting for the chip
being ready.
> > + if (cpu_to_be16(hwid) != SUPPORTED_HWID) {
>
> Hmm... Why cpu_to_be16() is required?
>
> > + dev_err(&i2c->dev, "unsupported HW ID 0x%x\n", hwid);
> > + error = -ENODEV;
> > + goto out;
> > + }
> > +}
You are right, it works but what we meant to do here is to convert the
chip's value (big endian) into the CPU endianness. We will change it to
be16_to_cpu().
> > +static int bu21029_parse_dt(struct bu21029_ts_data *bu21029)
>
> You can get rid of DT requirement by...
>
> > +{
> > + struct device *dev = &bu21029->client->dev;
> > + struct device_node *np = dev->of_node;
> > + u32 val32;
> > + int error;
>
> > + if (!np) {
> > + dev_err(dev, "no device tree data\n");
> > + return -EINVAL;
> > + }
>
> (this becomes redundant)
>
> > +
> > + bu21029->reset_gpios = devm_gpiod_get(dev, "reset",
> GPIOD_OUT_HIGH);
> > + if (IS_ERR(bu21029->reset_gpios)) {
> > + error = PTR_ERR(bu21029->reset_gpios);
> > + if (error != -EPROBE_DEFER)
> > + dev_err(dev, "invalid 'reset-gpios':%d\n", error);
> > + return error;
> > + }
> > +
>
> > + if (of_property_read_u32(np, "rohm,x-plate-ohms", &val32)) {
>
> ...simple calling device_property_read_u32() instead.
>
> > + dev_err(dev, "invalid 'x-plate-ohms' supplied\n");
> > + return -EINVAL;
> > + }
> > + bu21029->x_plate_ohms = val32;
> > +
> > + touchscreen_parse_properties(bu21029->in_dev, false, &bu21029->prop);
> > +
> > + return 0;
> > +}
Thank you, changed.
> > +#ifdef CONFIG_PM_SLEEP
>
> Instead...
>
> > +static int bu21029_suspend(struct device *dev)
>
> ...use __maby_unused annotation.
>
> > +static int bu21029_resume(struct device *dev)
>
> Ditto.
OK, added.
Regards,
Mark
Mark Jonas
Building Technologies, Panel Software Fire (BT-FIR/ENG1)
Bosch Sicherheitssysteme GmbH | Postfach 11 11 | 85626 Grasbrunn | GERMANY | www.boschsecurity.com
Sitz: Stuttgart, Registergericht: Amtsgericht Stuttgart HRB 23118
Aufsichtsratsvorsitzender: Stefan Hartung; Geschäftsführung: Gert van Iperen, Andreas Bartz, Thomas Quante, Bernhard Schuster
^ permalink raw reply
* [PATCH v4] Input: add bu21029 touch driver
From: Mark Jonas @ 2018-05-16 13:25 UTC (permalink / raw)
To: Dmitry Torokhov, Rob Herring, Mark Rutland
Cc: linux-input, devicetree, linux-kernel, hs, andy.shevchenko,
Zhu Yi, Mark Jonas
In-Reply-To: <1521651874-15379-1-git-send-email-mark.jonas@de.bosch.com>
From: Zhu Yi <yi.zhu5@cn.bosch.com>
Add Rohm BU21029 resistive touch panel controller support with I2C
interface.
Signed-off-by: Zhu Yi <yi.zhu5@cn.bosch.com>
Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes in v4:
- remove potential kernel log spamming from irq handler
- fix bug in endianess conversion of the chip's HW ID
- simplify device tree reading
- flag resume and suspend functions as potentially unused
---
Changes in v3:
- reviewed by Rob Herring
---
Changes in v2:
- make ABS_PRESSURE proportionally rising with finger pressure
- fix race between interrupt and timer during shutdown
- use infrastructure from include/linux/input/touchscreen.h
- add SPDX tag for the driver
- improve binding documentation
- fix multi-line comments
---
.../bindings/input/touchscreen/bu21029.txt | 34 ++
drivers/input/touchscreen/Kconfig | 12 +
drivers/input/touchscreen/Makefile | 1 +
drivers/input/touchscreen/bu21029_ts.c | 475 +++++++++++++++++++++
4 files changed, 522 insertions(+)
create mode 100644 Documentation/devicetree/bindings/input/touchscreen/bu21029.txt
create mode 100644 drivers/input/touchscreen/bu21029_ts.c
diff --git a/Documentation/devicetree/bindings/input/touchscreen/bu21029.txt b/Documentation/devicetree/bindings/input/touchscreen/bu21029.txt
new file mode 100644
index 0000000..030a888
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/bu21029.txt
@@ -0,0 +1,34 @@
+* Rohm BU21029 Touch Screen Controller
+
+Required properties:
+ - compatible : must be "rohm,bu21029"
+ - reg : i2c device address of the chip (0x40 or 0x41)
+ - interrupt-parent : the phandle for the gpio controller
+ - interrupts : (gpio) interrupt to which the chip is connected
+ - reset-gpios : gpio pin to reset the chip (active low)
+ - rohm,x-plate-ohms : x-plate resistance in Ohm
+
+Optional properties:
+ - touchscreen-size-x : horizontal resolution of touchscreen (in pixels)
+ - touchscreen-size-y : vertical resolution of touchscreen (in pixels)
+ - touchscreen-max-pressure: maximum pressure value
+
+Example:
+
+ &i2c1 {
+ /* ... */
+
+ bu21029: bu21029@40 {
+ compatible = "rohm,bu21029";
+ reg = <0x40>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
+ rohm,x-plate-ohms = <600>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ touchscreen-max-pressure = <4095>;
+ };
+
+ /* ... */
+ };
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 4f15496..e09fe8f 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -151,6 +151,18 @@ config TOUCHSCREEN_BU21013
To compile this driver as a module, choose M here: the
module will be called bu21013_ts.
+config TOUCHSCREEN_BU21029
+ tristate "Rohm BU21029 based touch panel controllers"
+ depends on I2C
+ help
+ Say Y here if you have a Rohm BU21029 touchscreen controller
+ connected to your system.
+
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called bu21029_ts.
+
config TOUCHSCREEN_CHIPONE_ICN8318
tristate "chipone icn8318 touchscreen controller"
depends on GPIOLIB || COMPILE_TEST
diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
index dddae79..f50624c 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_TOUCHSCREEN_AR1021_I2C) += ar1021_i2c.o
obj-$(CONFIG_TOUCHSCREEN_ATMEL_MXT) += atmel_mxt_ts.o
obj-$(CONFIG_TOUCHSCREEN_AUO_PIXCIR) += auo-pixcir-ts.o
obj-$(CONFIG_TOUCHSCREEN_BU21013) += bu21013_ts.o
+obj-$(CONFIG_TOUCHSCREEN_BU21029) += bu21029_ts.o
obj-$(CONFIG_TOUCHSCREEN_CHIPONE_ICN8318) += chipone_icn8318.o
obj-$(CONFIG_TOUCHSCREEN_CY8CTMG110) += cy8ctmg110_ts.o
obj-$(CONFIG_TOUCHSCREEN_CYTTSP_CORE) += cyttsp_core.o
diff --git a/drivers/input/touchscreen/bu21029_ts.c b/drivers/input/touchscreen/bu21029_ts.c
new file mode 100644
index 0000000..2bd63d1
--- /dev/null
+++ b/drivers/input/touchscreen/bu21029_ts.c
@@ -0,0 +1,475 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rohm BU21029 touchscreen controller driver
+ *
+ * Copyright (C) 2015-2018 Bosch Sicherheitssysteme GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/input/touchscreen.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/timer.h>
+
+/*
+ * HW_ID1 Register (PAGE=0, ADDR=0x0E, Reset value=0x02, Read only)
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | HW_IDH |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * HW_ID2 Register (PAGE=0, ADDR=0x0F, Reset value=0x29, Read only)
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | HW_IDL |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * HW_IDH: high 8bits of IC's ID
+ * HW_IDL: low 8bits of IC's ID
+ */
+#define BU21029_HWID_REG (0x0E << 3)
+#define SUPPORTED_HWID 0x0229
+
+/*
+ * CFR0 Register (PAGE=0, ADDR=0x00, Reset value=0x20)
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | 0 | 0 | CALIB | INTRM | 0 | 0 | 0 | 0 |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * CALIB: 0 = not to use calibration result (*)
+ * 1 = use calibration result
+ * INTRM: 0 = INT output depend on "pen down" (*)
+ * 1 = INT output always "0"
+ */
+#define BU21029_CFR0_REG (0x00 << 3)
+#define CFR0_VALUE 0x00
+
+/*
+ * CFR1 Register (PAGE=0, ADDR=0x01, Reset value=0xA6)
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | MAV | AVE[2:0] | 0 | SMPL[2:0] |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * MAV: 0 = median average filter off
+ * 1 = median average filter on (*)
+ * AVE: AVE+1 = number of average samples for MAV,
+ * if AVE>SMPL, then AVE=SMPL (=3)
+ * SMPL: SMPL+1 = number of conversion samples for MAV (=7)
+ */
+#define BU21029_CFR1_REG (0x01 << 3)
+#define CFR1_VALUE 0xA6
+
+/*
+ * CFR2 Register (PAGE=0, ADDR=0x02, Reset value=0x04)
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | INTVL_TIME[3:0] | TIME_ST_ADC[3:0] |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * INTVL_TIME: waiting time between completion of conversion
+ * and start of next conversion, only usable in
+ * autoscan mode (=20.480ms)
+ * TIME_ST_ADC: waiting time between application of voltage
+ * to panel and start of A/D conversion (=100us)
+ */
+#define BU21029_CFR2_REG (0x02 << 3)
+#define CFR2_VALUE 0xC9
+
+/*
+ * CFR3 Register (PAGE=0, ADDR=0x0B, Reset value=0x72)
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | RM8 | STRETCH| PU90K | DUAL | PIDAC_OFS[3:0] |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * RM8: 0 = coordinate resolution is 12bit (*)
+ * 1 = coordinate resolution is 8bit
+ * STRETCH: 0 = SCL_STRETCH function off
+ * 1 = SCL_STRETCH function on (*)
+ * PU90K: 0 = internal pull-up resistance for touch detection is ~50kohms (*)
+ * 1 = internal pull-up resistance for touch detection is ~90kohms
+ * DUAL: 0 = dual touch detection off (*)
+ * 1 = dual touch detection on
+ * PIDAC_OFS: dual touch detection circuit adjustment, it is not necessary
+ * to change this from initial value
+ */
+#define BU21029_CFR3_REG (0x0B << 3)
+#define CFR3_VALUE 0x42
+
+/*
+ * LDO Register (PAGE=0, ADDR=0x0C, Reset value=0x00)
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | 0 | PVDD[2:0] | 0 | AVDD[2:0] |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * PVDD: output voltage of panel output regulator (=2.000V)
+ * AVDD: output voltage of analog circuit regulator (=2.000V)
+ */
+#define BU21029_LDO_REG (0x0C << 3)
+#define LDO_VALUE 0x77
+
+/*
+ * Serial Interface Command Byte 1 (CID=1)
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * | 1 | CF | CMSK | PDM | STP |
+ * +--------+--------+--------+--------+--------+--------+--------+--------+
+ * CF: conversion function, see table 3 in datasheet p6 (=0000, automatic scan)
+ * CMSK: 0 = executes convert function (*)
+ * 1 = reads the convert result
+ * PDM: 0 = power down after convert function stops (*)
+ * 1 = keep power on after convert function stops
+ * STP: 1 = abort current conversion and power down, set to "0" automatically
+ */
+#define BU21029_AUTOSCAN 0x80
+
+/*
+ * The timeout value needs to be larger than INTVL_TIME + tConv4 (sample and
+ * conversion time), where tConv4 is calculated by formula:
+ * tPON + tDLY1 + (tTIME_ST_ADC + (tADC * tSMPL) * 2 + tDLY2) * 3
+ * see figure 8 in datasheet p15 for details of each field.
+ */
+#define PEN_UP_TIMEOUT msecs_to_jiffies(50)
+
+#define STOP_DELAY_US 50
+#define START_DELAY_MS 2
+#define BUF_LEN 8
+#define SCALE_12BIT (1 << 12)
+#define MAX_12BIT ((1 << 12) - 1)
+#define DRIVER_NAME "bu21029"
+
+struct bu21029_ts_data {
+ struct i2c_client *client;
+ struct input_dev *in_dev;
+ struct timer_list timer;
+ struct gpio_desc *reset_gpios;
+ u32 x_plate_ohms;
+ struct touchscreen_properties prop;
+};
+
+static int bu21029_touch_report(struct bu21029_ts_data *bu21029)
+{
+ struct i2c_client *i2c = bu21029->client;
+ u8 buf[BUF_LEN];
+ u16 x, y, z1, z2;
+ u32 rz;
+ s32 max_pressure = bu21029->in_dev->absinfo[ABS_PRESSURE].maximum;
+
+ /* read touch data and deassert INT (by restarting the autoscan mode) */
+ int error = i2c_smbus_read_i2c_block_data(i2c,
+ BU21029_AUTOSCAN,
+ BUF_LEN,
+ buf);
+ if (error < 0)
+ return error;
+
+ /*
+ * compose upper 8 and lower 4 bits into a 12bit value:
+ * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+ * | ByteH | ByteL |
+ * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+ * |b07|b06|b05|b04|b03|b02|b01|b00|b07|b06|b05|b04|b03|b02|b01|b00|
+ * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+ * |v11|v10|v09|v08|v07|v06|v05|v04|v03|v02|v01|v00| 0 | 0 | 0 | 0 |
+ * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+ */
+ x = (buf[0] << 4) | (buf[1] >> 4);
+ y = (buf[2] << 4) | (buf[3] >> 4);
+ z1 = (buf[4] << 4) | (buf[5] >> 4);
+ z2 = (buf[6] << 4) | (buf[7] >> 4);
+
+ if (z1 == 0 || z2 == 0)
+ return 0;
+
+ /*
+ * calculate Rz (pressure resistance value) by equation:
+ * Rz = Rx * (x/Q) * ((z2/z1) - 1), where
+ * Rx is x-plate resistance,
+ * Q is the touch screen resolution (8bit = 256, 12bit = 4096)
+ * x, z1, z2 are the measured positions.
+ */
+ rz = z2 - z1;
+ rz *= x;
+ rz *= bu21029->x_plate_ohms;
+ rz /= z1;
+ rz = DIV_ROUND_CLOSEST(rz, SCALE_12BIT);
+ if (rz <= max_pressure) {
+ touchscreen_report_pos(bu21029->in_dev, &bu21029->prop,
+ x, y, false);
+ input_report_abs(bu21029->in_dev, ABS_PRESSURE,
+ max_pressure - rz);
+ input_report_key(bu21029->in_dev, BTN_TOUCH, 1);
+ input_sync(bu21029->in_dev);
+ }
+
+ return 0;
+}
+
+static void bu21029_touch_release(struct timer_list *t)
+{
+ struct bu21029_ts_data *bu21029 = from_timer(bu21029, t, timer);
+
+ input_report_abs(bu21029->in_dev, ABS_PRESSURE, 0);
+ input_report_key(bu21029->in_dev, BTN_TOUCH, 0);
+ input_sync(bu21029->in_dev);
+}
+
+static irqreturn_t bu21029_touch_soft_irq(int irq, void *data)
+{
+ struct bu21029_ts_data *bu21029 = data;
+
+ /*
+ * report touch and deassert interrupt (will assert again after
+ * INTVL_TIME + tConv4 for continuous touch)
+ */
+ int error = bu21029_touch_report(bu21029);
+
+ if (error)
+ return IRQ_NONE;
+
+ /* reset timer for pen up detection */
+ mod_timer(&bu21029->timer, jiffies + PEN_UP_TIMEOUT);
+
+ return IRQ_HANDLED;
+}
+
+static void bu21029_stop_chip(struct input_dev *dev)
+{
+ struct bu21029_ts_data *bu21029 = input_get_drvdata(dev);
+
+ disable_irq(bu21029->client->irq);
+ del_timer_sync(&bu21029->timer);
+
+ /* put chip into reset */
+ gpiod_set_value_cansleep(bu21029->reset_gpios, 1);
+ udelay(STOP_DELAY_US);
+}
+
+static int bu21029_start_chip(struct input_dev *dev)
+{
+ struct bu21029_ts_data *bu21029 = input_get_drvdata(dev);
+ struct i2c_client *i2c = bu21029->client;
+ struct {
+ u8 reg;
+ u8 value;
+ } init_table[] = {
+ {BU21029_CFR0_REG, CFR0_VALUE},
+ {BU21029_CFR1_REG, CFR1_VALUE},
+ {BU21029_CFR2_REG, CFR2_VALUE},
+ {BU21029_CFR3_REG, CFR3_VALUE},
+ {BU21029_LDO_REG, LDO_VALUE}
+ };
+ int error, i;
+ u16 hwid;
+
+ /* take chip out of reset */
+ gpiod_set_value_cansleep(bu21029->reset_gpios, 0);
+ mdelay(START_DELAY_MS);
+
+ error = i2c_smbus_read_i2c_block_data(i2c,
+ BU21029_HWID_REG,
+ 2,
+ (u8 *)&hwid);
+ if (error < 0) {
+ dev_err(&i2c->dev, "failed to read HW ID\n");
+ goto out;
+ }
+
+ if (be16_to_cpu(hwid) != SUPPORTED_HWID) {
+ dev_err(&i2c->dev, "unsupported HW ID 0x%x\n", hwid);
+ error = -ENODEV;
+ goto out;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(init_table); ++i) {
+ error = i2c_smbus_write_byte_data(i2c,
+ init_table[i].reg,
+ init_table[i].value);
+ if (error < 0) {
+ dev_err(&i2c->dev,
+ "failed to write 0x%x to register 0x%x\n",
+ init_table[i].value,
+ init_table[i].reg);
+ goto out;
+ }
+ }
+
+ error = i2c_smbus_write_byte(i2c, BU21029_AUTOSCAN);
+ if (error < 0) {
+ dev_err(&i2c->dev, "failed to start autoscan\n");
+ goto out;
+ }
+
+ enable_irq(bu21029->client->irq);
+ return 0;
+
+out:
+ bu21029_stop_chip(dev);
+ return error;
+}
+
+static int bu21029_parse_dt(struct bu21029_ts_data *bu21029)
+{
+ struct device *dev = &bu21029->client->dev;
+ int error;
+
+ bu21029->reset_gpios = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(bu21029->reset_gpios)) {
+ error = PTR_ERR(bu21029->reset_gpios);
+ if (error != -EPROBE_DEFER)
+ dev_err(dev, "invalid 'reset-gpios':%d\n", error);
+ return error;
+ }
+
+ error = device_property_read_u32(dev, "rohm,x-plate-ohms",
+ &bu21029->x_plate_ohms);
+ if (error) {
+ dev_err(dev, "invalid 'x-plate-ohms' supplied:%d\n", error);
+ return error;
+ }
+
+ touchscreen_parse_properties(bu21029->in_dev, false, &bu21029->prop);
+
+ return 0;
+}
+
+static int bu21029_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct bu21029_ts_data *bu21029;
+ struct input_dev *in_dev;
+ int error;
+
+ if (!i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_WRITE_BYTE |
+ I2C_FUNC_SMBUS_WRITE_BYTE_DATA |
+ I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
+ dev_err(&client->dev,
+ "i2c functionality support is not sufficient\n");
+ return -EIO;
+ }
+
+ bu21029 = devm_kzalloc(&client->dev, sizeof(*bu21029), GFP_KERNEL);
+ if (!bu21029)
+ return -ENOMEM;
+
+ in_dev = devm_input_allocate_device(&client->dev);
+ if (!in_dev) {
+ dev_err(&client->dev, "unable to allocate input device\n");
+ return -ENOMEM;
+ }
+
+ bu21029->client = client;
+ bu21029->in_dev = in_dev;
+ timer_setup(&bu21029->timer, bu21029_touch_release, 0);
+
+ in_dev->name = DRIVER_NAME;
+ in_dev->id.bustype = BUS_I2C;
+ in_dev->open = bu21029_start_chip;
+ in_dev->close = bu21029_stop_chip;
+
+ input_set_capability(in_dev, EV_KEY, BTN_TOUCH);
+ input_set_abs_params(in_dev, ABS_X, 0, MAX_12BIT, 0, 0);
+ input_set_abs_params(in_dev, ABS_Y, 0, MAX_12BIT, 0, 0);
+ input_set_abs_params(in_dev, ABS_PRESSURE, 0, MAX_12BIT, 0, 0);
+
+ error = bu21029_parse_dt(bu21029);
+ if (error)
+ return error;
+
+ input_set_drvdata(in_dev, bu21029);
+
+ error = devm_request_threaded_irq(&client->dev,
+ client->irq,
+ NULL,
+ bu21029_touch_soft_irq,
+ IRQF_ONESHOT,
+ DRIVER_NAME,
+ bu21029);
+ if (error) {
+ dev_err(&client->dev, "unable to request touch irq\n");
+ return error;
+ }
+
+ bu21029_stop_chip(in_dev);
+
+ error = input_register_device(in_dev);
+ if (error) {
+ dev_err(&client->dev, "unable to register input device\n");
+ return error;
+ }
+
+ i2c_set_clientdata(client, bu21029);
+
+ return 0;
+}
+
+static int bu21029_remove(struct i2c_client *client)
+{
+ struct bu21029_ts_data *bu21029 = i2c_get_clientdata(client);
+
+ bu21029_stop_chip(bu21029->in_dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int __maybe_unused bu21029_suspend(struct device *dev)
+{
+ struct i2c_client *i2c = to_i2c_client(dev);
+ struct bu21029_ts_data *bu21029 = i2c_get_clientdata(i2c);
+
+ mutex_lock(&bu21029->in_dev->mutex);
+ if (bu21029->in_dev->users)
+ bu21029_stop_chip(bu21029->in_dev);
+ mutex_unlock(&bu21029->in_dev->mutex);
+
+ return 0;
+}
+
+static int __maybe_unused bu21029_resume(struct device *dev)
+{
+ struct i2c_client *i2c = to_i2c_client(dev);
+ struct bu21029_ts_data *bu21029 = i2c_get_clientdata(i2c);
+
+ mutex_lock(&bu21029->in_dev->mutex);
+ if (bu21029->in_dev->users)
+ bu21029_start_chip(bu21029->in_dev);
+ mutex_unlock(&bu21029->in_dev->mutex);
+
+ return 0;
+}
+#endif
+static SIMPLE_DEV_PM_OPS(bu21029_pm_ops, bu21029_suspend, bu21029_resume);
+
+static const struct i2c_device_id bu21029_ids[] = {
+ {DRIVER_NAME, 0},
+ {}
+};
+MODULE_DEVICE_TABLE(i2c, bu21029_ids);
+
+static struct i2c_driver bu21029_driver = {
+ .driver = {
+ .name = DRIVER_NAME,
+ .pm = &bu21029_pm_ops,
+ },
+ .id_table = bu21029_ids,
+ .probe = bu21029_probe,
+ .remove = bu21029_remove,
+};
+module_i2c_driver(bu21029_driver);
+
+MODULE_AUTHOR("Zhu Yi <yi.zhu5@cn.bosch.com>");
+MODULE_DESCRIPTION("Rohm BU21029 touchscreen controller driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related
* Re: [PATCH net-next v2 15/15] arm64: dts: allwinner: a64: add SRAM controller device tree node
From: Maxime Ripard @ 2018-05-16 13:31 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Icenowy Zheng, linux-arm-kernel, Mark Rutland, devicetree,
Stephen Boyd, netdev, Michael Turquette, Rob Herring,
Corentin Labbe, Mark Brown, Giuseppe Cavallaro, linux-clk
In-Reply-To: <CAGb2v65uZeueE=2FfsxWen9zNvCtMsJ+b=KgMfSh-ZKmO+S=cQ@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 4635 bytes --]
Hi,
On Tue, May 15, 2018 at 11:47:16PM -0700, Chen-Yu Tsai wrote:
> On Mon, May 14, 2018 at 1:03 AM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> > 1;5201;0c
> > On Sun, May 13, 2018 at 12:37:49PM -0700, Chen-Yu Tsai wrote:
> >> On Wed, May 2, 2018 at 4:54 AM, Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >> > On Wed, May 02, 2018 at 06:19:51PM +0800, Icenowy Zheng wrote:
> >> >>
> >> >>
> >> >> 于 2018年5月2日 GMT+08:00 下午5:53:21, Chen-Yu Tsai <wens@csie.org> 写到:
> >> >> >On Wed, May 2, 2018 at 5:51 PM, Maxime Ripard
> >> >> ><maxime.ripard@bootlin.com> wrote:
> >> >> >> Hi,
> >> >> >>
> >> >> >> On Wed, May 02, 2018 at 12:12:27AM +0800, Chen-Yu Tsai wrote:
> >> >> >>> From: Icenowy Zheng <icenowy@aosc.io>
> >> >> >>>
> >> >> >>> Allwinner A64 has a SRAM controller, and in the device tree
> >> >> >currently
> >> >> >>> we have a syscon node to enable EMAC driver to access the EMAC clock
> >> >> >>> register. As SRAM controller driver can now export regmap for this
> >> >> >>> register, replace the syscon node to the SRAM controller device
> >> >> >node,
> >> >> >>> and let EMAC driver to acquire its EMAC clock regmap.
> >> >> >>>
> >> >> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >> >> >>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >> >> >>> ---
> >> >> >>> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 23
> >> >> >+++++++++++++++----
> >> >> >>> 1 file changed, 19 insertions(+), 4 deletions(-)
> >> >> >>>
> >> >> >>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> >> >b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> >> >>> index 1b2ef28c42bd..1c37659d9d41 100644
> >> >> >>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> >> >>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> >> >>> @@ -168,10 +168,25 @@
> >> >> >>> #size-cells = <1>;
> >> >> >>> ranges;
> >> >> >>>
> >> >> >>> - syscon: syscon@1c00000 {
> >> >> >>> - compatible =
> >> >> >"allwinner,sun50i-a64-system-controller",
> >> >> >>> - "syscon";
> >> >> >>> + sram_controller: sram-controller@1c00000 {
> >> >> >>> + compatible =
> >> >> >"allwinner,sun50i-a64-sram-controller";
> >> >> >>
> >> >> >> I don't think there's anything preventing us from keeping the
> >> >> >> -system-controller compatible. It's what was in the DT before, and
> >> >> >> it's how it's called in the datasheet.
> >> >> >
> >> >> >I actually meant to ask you about this. The -system-controller
> >> >> >compatible matches the datasheet better. Maybe we should just
> >> >> >switch to that one?
> >> >>
> >> >> No, if we do the switch the system-controller compatible,
> >> >> the device will be probed on the same memory region with
> >> >> a syscon on old DTs.
> >> >
> >> > The device hasn't magically changed either. Maybe we just need to add
> >> > a check to make sure we don't have the syscon compatible in the SRAM
> >> > driver probe so that the double driver issue doesn't happen?
> >>
> >> The syscon interface (which is not even a full blown device driver)
> >> only looks at the "syscon" compatible. Either way we're removing that
> >> part from the device tree so things should be ok for new device trees.
> >> As Maxime mentioned we can do a check for the syscon compatible and
> >> either give a warning to the user asking them to update their device
> >> tree, or not register our custom regmap, or not probe the SRAM driver.
> >> Personally I prefer the first option. The system controller block is
> >> probed before any syscon users, so we should be fine, given the dwmac
> >> driver goes the custom regmap path first.
> >>
> >> BTW, I still might end up changing the compatible. The manual uses
> >> "system control", not "system controller", which I think makes sense,
> >> since it is just a bunch of register files, kind of like the GRF
> >> (General Register Files) block found in Rockchip SoCs [1], and not an
> >> actual "controller".
> >
> > I'm not really fond of that, but we should at least make it consistent
> > on the other patches Paul sent then.
>
> For the A10s / A13 right?
And A33, yep.
> I think my naming is slightly better, but it's just a minor detail.
Let's do this then.
> While we're still debating this, can I merge the R40 stuff first?
> The driver bits are already in.
Yep, go ahead.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply
* Re: [PATCH v5 0/7] pcal6524 extensions and fixes for pca953x driver
From: H. Nikolaus Schaller @ 2018-05-16 13:32 UTC (permalink / raw)
To: Linus Walleij
Cc: Kumar Gala, Andy Shevchenko, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Alexandre Courbot,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org,
Discussions about the Letux Kernel, kernel
In-Reply-To: <CACRpkdbk0rNZ3cUN_noqVtNYgDrydGtCCn2fk7yqVRPoroYqpA@mail.gmail.com>
Hi,
> Am 16.05.2018 um 13:53 schrieb Linus Walleij <linus.walleij@linaro.org>:
>
> On Sat, Apr 28, 2018 at 6:31 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
>
>> V5:
>> * fix wrong split up between patches 1/7and 2/7.
>
> I applied patches 1, 2, 3 so we get some movement on the patch
> set and not too much for you to rebase.
thanks!
Well, I already had edited the commit messages for resending...
>
> It's fine to just resend the rest next time.
There is only one point open before resending:
what is the preferred style to be used for PCAL_GPIO_MASK?
* GENMASK(4, 0)
* or 0x1f
BR,
Nikolaus
^ permalink raw reply
* Re: [PATCHv3] arm64: dts: stratix10: Add QSPI support for Stratix10
From: Dinh Nguyen @ 2018-05-16 13:36 UTC (permalink / raw)
To: thor.thayer, robh+dt, mark.rutland
Cc: catalin.marinas, will.deacon, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <1526423187-27521-1-git-send-email-thor.thayer@linux.intel.com>
On 05/15/2018 05:26 PM, thor.thayer@linux.intel.com wrote:
> From: Thor Thayer <thor.thayer@linux.intel.com>
>
> Add qspi_clock
> The qspi_clk frequency is updated by U-Boot before starting Linux.
> Add QSPI interface node.
> Add QSPI flash memory child node.
> Setup the QSPI memory in 2 partitions.
>
> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
> ---
> v2 s/_/-/ in qspi-clk
> rename flash node.
> use partition child node notation
> v3 remove unused bus-num node
> use device id from table (n25q00a)
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 21 +++++++++++++
> .../boot/dts/altera/socfpga_stratix10_socdk.dts | 35 ++++++++++++++++++++++
> 2 files changed, 56 insertions(+)
>
Applied!
Thanks,
Dinh
^ permalink raw reply
* [PATCH RFC 0/6] hwmon: Add support for Raspberry Pi voltage sensor
From: Stefan Wahren @ 2018-05-16 13:37 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jean Delvare, Guenter Roeck,
Eric Anholt
Cc: linux-hwmon, devicetree, Florian Fainelli, Scott Branden, Ray Jui,
Stefan Wahren, Phil Elwell, bcm-kernel-feedback-list,
linux-rpi-kernel, linux-arm-kernel
A common issue for the Raspberry Pi is an inadequate power supply.
Noralf Trønnes started a discussion [1] about writting such under-voltage
conditions into the kernel log.
This series is a draft to upstream the resulting kernel patch and is not
intended for 4.18.
[1] - https://github.com/raspberrypi/linux/issues/2367
Stefan Wahren (6):
ARM: bcm2835: Add GET_THROTTLED firmware property
dt-bindings: hwmon: Add Raspberry Pi voltage sensor
hwmon: Add support for RPi voltage sensor
ARM: bcm2835_defconfig: Enable RPi voltage sensor
ARM: multi_v7_defconfig: Enable RPi voltage sensor
arm64: defconfig: Enable RPi voltage sensor
.../bindings/hwmon/raspberrypi-hwmon.txt | 19 ++
arch/arm/configs/bcm2835_defconfig | 2 +-
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm64/configs/defconfig | 1 +
drivers/hwmon/Kconfig | 10 +
drivers/hwmon/Makefile | 1 +
drivers/hwmon/raspberrypi-hwmon.c | 207 +++++++++++++++++++++
include/soc/bcm2835/raspberrypi-firmware.h | 1 +
8 files changed, 241 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/hwmon/raspberrypi-hwmon.txt
create mode 100644 drivers/hwmon/raspberrypi-hwmon.c
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
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